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e1000_82575.c (194865) e1000_82575.c (200243)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 194865 2009-06-24 17:41:29Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82575.c 200243 2009-12-08 01:07:44Z jfv $*/
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter

--- 12 unchanged lines hidden (view full) ---

54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57static s32 e1000_init_hw_82575(struct e1000_hw *hw);
58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
34
35/*
36 * 82575EB Gigabit Network Connection
37 * 82575EB Gigabit Backplane Connection
38 * 82575GB Gigabit Network Connection
39 * 82575GB Gigabit Network Connection
40 * 82576 Gigabit Network Connection
41 * 82576 Quad Port Gigabit Mezzanine Adapter

--- 12 unchanged lines hidden (view full) ---

54static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
55static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
56 u16 *duplex);
57static s32 e1000_init_hw_82575(struct e1000_hw *hw);
58static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
59static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
60 u16 *data);
61static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
62static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
63static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
64 u32 offset, u16 *data);
65static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
66 u32 offset, u16 data);
62static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
63 bool active);
64static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
67static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
68 bool active);
69static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
65static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw);
70static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
66static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
67static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
68 u32 offset, u16 data);
69static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
70static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
71static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
72static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
73 u32 offset, u16 data);
74static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
75static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
71static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw);
72static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
73 u16 *speed, u16 *duplex);
74static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
75static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
76static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
77static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
78static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
79static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
76static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
77 u16 *speed, u16 *duplex);
78static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
79static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
80static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
81static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
82static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
83static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
80void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw);
84static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
81static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
82
85static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
86
87static const u16 e1000_82580_rxpbs_table[] =
88 { 36, 72, 144, 1, 2, 4, 8, 16,
89 35, 70, 140 };
90#define E1000_82580_RXPBS_TABLE_SIZE \
91 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
92
83/**
84 * e1000_init_phy_params_82575 - Init PHY func ptrs.
85 * @hw: pointer to the HW structure
86 **/
87static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
88{
89 struct e1000_phy_info *phy = &hw->phy;
90 s32 ret_val = E1000_SUCCESS;
91
92 DEBUGFUNC("e1000_init_phy_params_82575");
93
94 if (hw->phy.media_type != e1000_media_type_copper) {
95 phy->type = e1000_phy_none;
96 goto out;
93/**
94 * e1000_init_phy_params_82575 - Init PHY func ptrs.
95 * @hw: pointer to the HW structure
96 **/
97static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
98{
99 struct e1000_phy_info *phy = &hw->phy;
100 s32 ret_val = E1000_SUCCESS;
101
102 DEBUGFUNC("e1000_init_phy_params_82575");
103
104 if (hw->phy.media_type != e1000_media_type_copper) {
105 phy->type = e1000_phy_none;
106 goto out;
97 } else {
98 phy->ops.power_up = e1000_power_up_phy_copper;
99 phy->ops.power_down = e1000_power_down_phy_copper_82575;
100 }
101
107 }
108
109 phy->ops.power_up = e1000_power_up_phy_copper;
110 phy->ops.power_down = e1000_power_down_phy_copper_82575;
111
102 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
103 phy->reset_delay_us = 100;
104
105 phy->ops.acquire = e1000_acquire_phy_82575;
106 phy->ops.check_reset_block = e1000_check_reset_block_generic;
107 phy->ops.commit = e1000_phy_sw_reset_generic;
108 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
109 phy->ops.release = e1000_release_phy_82575;
110
111 if (e1000_sgmii_active_82575(hw)) {
112 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
113 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
114 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
112 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
113 phy->reset_delay_us = 100;
114
115 phy->ops.acquire = e1000_acquire_phy_82575;
116 phy->ops.check_reset_block = e1000_check_reset_block_generic;
117 phy->ops.commit = e1000_phy_sw_reset_generic;
118 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
119 phy->ops.release = e1000_release_phy_82575;
120
121 if (e1000_sgmii_active_82575(hw)) {
122 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
123 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
124 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
125 } else if ((hw->mac.type == e1000_82580) ||
126 (hw->mac.type == e1000_82580er)) {
127 phy->ops.reset = e1000_phy_hw_reset_generic;
128 phy->ops.read_reg = e1000_read_phy_reg_82580;
129 phy->ops.write_reg = e1000_write_phy_reg_82580;
115 } else {
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.read_reg = e1000_read_phy_reg_igp;
118 phy->ops.write_reg = e1000_write_phy_reg_igp;
119 }
120
121 /* Set phy->phy_addr and phy->id. */
122 ret_val = e1000_get_phy_id_82575(hw);

--- 12 unchanged lines hidden (view full) ---

135 phy->type = e1000_phy_igp_3;
136 phy->ops.check_polarity = e1000_check_polarity_igp;
137 phy->ops.get_info = e1000_get_phy_info_igp;
138 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
139 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
140 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
141 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
142 break;
130 } else {
131 phy->ops.reset = e1000_phy_hw_reset_generic;
132 phy->ops.read_reg = e1000_read_phy_reg_igp;
133 phy->ops.write_reg = e1000_write_phy_reg_igp;
134 }
135
136 /* Set phy->phy_addr and phy->id. */
137 ret_val = e1000_get_phy_id_82575(hw);

--- 12 unchanged lines hidden (view full) ---

150 phy->type = e1000_phy_igp_3;
151 phy->ops.check_polarity = e1000_check_polarity_igp;
152 phy->ops.get_info = e1000_get_phy_info_igp;
153 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
154 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
155 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
156 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
157 break;
158 case I82580_I_PHY_ID:
159 phy->type = e1000_phy_82580;
160 phy->ops.check_polarity = e1000_check_polarity_82577;
161 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82577;
162 phy->ops.get_cable_length = e1000_get_cable_length_82577;
163 phy->ops.get_info = e1000_get_phy_info_82577;
164 break;
143 default:
144 ret_val = -E1000_ERR_PHY;
145 goto out;
146 }
147
148out:
149 return ret_val;
150}

--- 36 unchanged lines hidden (view full) ---

187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
189 */
190 size += NVM_WORD_SIZE_BASE_SHIFT;
191
192 /* EEPROM access above 16k is unsupported */
193 if (size > 14)
194 size = 14;
165 default:
166 ret_val = -E1000_ERR_PHY;
167 goto out;
168 }
169
170out:
171 return ret_val;
172}

--- 36 unchanged lines hidden (view full) ---

209 * Added to a constant, "size" becomes the left-shift value
210 * for setting word_size.
211 */
212 size += NVM_WORD_SIZE_BASE_SHIFT;
213
214 /* EEPROM access above 16k is unsupported */
215 if (size > 14)
216 size = 14;
195 nvm->word_size = 1 << size;
217 nvm->word_size = 1 << size;
196
197 /* Function Pointers */
198 nvm->ops.acquire = e1000_acquire_nvm_82575;
199 nvm->ops.read = e1000_read_nvm_eerd;
200 nvm->ops.release = e1000_release_nvm_82575;
201 nvm->ops.update = e1000_update_nvm_checksum_generic;
202 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
203 nvm->ops.validate = e1000_validate_nvm_checksum_generic;

--- 21 unchanged lines hidden (view full) ---

225 * is no distinguishable difference between fiber and internal
226 * SerDes mode on the 82575. There can be an external PHY attached
227 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
228 */
229 hw->phy.media_type = e1000_media_type_copper;
230 dev_spec->sgmii_active = FALSE;
231
232 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
218
219 /* Function Pointers */
220 nvm->ops.acquire = e1000_acquire_nvm_82575;
221 nvm->ops.read = e1000_read_nvm_eerd;
222 nvm->ops.release = e1000_release_nvm_82575;
223 nvm->ops.update = e1000_update_nvm_checksum_generic;
224 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
225 nvm->ops.validate = e1000_validate_nvm_checksum_generic;

--- 21 unchanged lines hidden (view full) ---

247 * is no distinguishable difference between fiber and internal
248 * SerDes mode on the 82575. There can be an external PHY attached
249 * on the SGMII interface. For this, we'll set sgmii_active to TRUE.
250 */
251 hw->phy.media_type = e1000_media_type_copper;
252 dev_spec->sgmii_active = FALSE;
253
254 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
233 if ((ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) ==
234 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES) {
235 hw->phy.media_type = e1000_media_type_internal_serdes;
236 ctrl_ext |= E1000_CTRL_I2C_ENA;
237 } else if (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_SGMII) {
255 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
256 case E1000_CTRL_EXT_LINK_MODE_SGMII:
238 dev_spec->sgmii_active = TRUE;
239 ctrl_ext |= E1000_CTRL_I2C_ENA;
257 dev_spec->sgmii_active = TRUE;
258 ctrl_ext |= E1000_CTRL_I2C_ENA;
240 } else {
259 break;
260 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
261 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
262 hw->phy.media_type = e1000_media_type_internal_serdes;
263 ctrl_ext |= E1000_CTRL_I2C_ENA;
264 break;
265 default:
241 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
266 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
267 break;
242 }
268 }
269
243 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
244
270 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
271
272 /*
273 * if using i2c make certain the MDICNFG register is cleared to prevent
274 * communications from being misrouted to the mdic registers
275 */
276 if ((ctrl_ext & E1000_CTRL_I2C_ENA) &&
277 ((hw->mac.type == e1000_82580) || (hw->mac.type == e1000_82580er)))
278 E1000_WRITE_REG(hw, E1000_MDICNFG, 0);
279
245 /* Set mta register count */
246 mac->mta_reg_count = 128;
280 /* Set mta register count */
281 mac->mta_reg_count = 128;
282 /* Set uta register count */
283 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
247 /* Set rar entry count */
248 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
249 if (mac->type == e1000_82576)
250 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
284 /* Set rar entry count */
285 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
286 if (mac->type == e1000_82576)
287 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
288 if ((mac->type == e1000_82580) || (mac->type == e1000_82580er))
289 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
251 /* Set if part includes ASF firmware */
252 mac->asf_firmware_present = TRUE;
253 /* Set if manageability features are enabled. */
254 mac->arc_subsystem_valid =
255 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
256 ? TRUE : FALSE;
257
258 /* Function pointers */
259
260 /* bus type/speed/width */
261 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
262 /* reset */
290 /* Set if part includes ASF firmware */
291 mac->asf_firmware_present = TRUE;
292 /* Set if manageability features are enabled. */
293 mac->arc_subsystem_valid =
294 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
295 ? TRUE : FALSE;
296
297 /* Function pointers */
298
299 /* bus type/speed/width */
300 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
301 /* reset */
302 if ((mac->type == e1000_82580) || (mac->type == e1000_82580er))
303 mac->ops.reset_hw = e1000_reset_hw_82580;
304 else
263 mac->ops.reset_hw = e1000_reset_hw_82575;
264 /* hw initialization */
265 mac->ops.init_hw = e1000_init_hw_82575;
266 /* link setup */
267 mac->ops.setup_link = e1000_setup_link_generic;
268 /* physical interface link setup */
269 mac->ops.setup_physical_interface =
270 (hw->phy.media_type == e1000_media_type_copper)
271 ? e1000_setup_copper_link_82575
305 mac->ops.reset_hw = e1000_reset_hw_82575;
306 /* hw initialization */
307 mac->ops.init_hw = e1000_init_hw_82575;
308 /* link setup */
309 mac->ops.setup_link = e1000_setup_link_generic;
310 /* physical interface link setup */
311 mac->ops.setup_physical_interface =
312 (hw->phy.media_type == e1000_media_type_copper)
313 ? e1000_setup_copper_link_82575
272 : e1000_setup_fiber_serdes_link_82575;
314 : e1000_setup_serdes_link_82575;
273 /* physical interface shutdown */
315 /* physical interface shutdown */
274 mac->ops.shutdown_serdes = e1000_shutdown_fiber_serdes_link_82575;
316 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
275 /* check for link */
276 mac->ops.check_for_link = e1000_check_for_link_82575;
277 /* receive address register setting */
278 mac->ops.rar_set = e1000_rar_set_generic;
279 /* read mac address */
280 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
281 /* multicast address update */
282 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;

--- 14 unchanged lines hidden (view full) ---

297 /* turn on/off LED */
298 mac->ops.led_on = e1000_led_on_generic;
299 mac->ops.led_off = e1000_led_off_generic;
300 /* clear hardware counters */
301 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
302 /* link info */
303 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
304
317 /* check for link */
318 mac->ops.check_for_link = e1000_check_for_link_82575;
319 /* receive address register setting */
320 mac->ops.rar_set = e1000_rar_set_generic;
321 /* read mac address */
322 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
323 /* multicast address update */
324 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;

--- 14 unchanged lines hidden (view full) ---

339 /* turn on/off LED */
340 mac->ops.led_on = e1000_led_on_generic;
341 mac->ops.led_off = e1000_led_off_generic;
342 /* clear hardware counters */
343 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
344 /* link info */
345 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
346
347 /* set lan id for port to determine which phy lock to use */
348 hw->mac.ops.set_lan_id(hw);
349
305 return E1000_SUCCESS;
306}
307
308/**
309 * e1000_init_function_pointers_82575 - Init func ptrs.
310 * @hw: pointer to the HW structure
311 *
312 * Called to initialize all function pointers and parameters.

--- 16 unchanged lines hidden (view full) ---

329static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
330{
331 u16 mask = E1000_SWFW_PHY0_SM;
332
333 DEBUGFUNC("e1000_acquire_phy_82575");
334
335 if (hw->bus.func == E1000_FUNC_1)
336 mask = E1000_SWFW_PHY1_SM;
350 return E1000_SUCCESS;
351}
352
353/**
354 * e1000_init_function_pointers_82575 - Init func ptrs.
355 * @hw: pointer to the HW structure
356 *
357 * Called to initialize all function pointers and parameters.

--- 16 unchanged lines hidden (view full) ---

374static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
375{
376 u16 mask = E1000_SWFW_PHY0_SM;
377
378 DEBUGFUNC("e1000_acquire_phy_82575");
379
380 if (hw->bus.func == E1000_FUNC_1)
381 mask = E1000_SWFW_PHY1_SM;
382 else if (hw->bus.func == E1000_FUNC_2)
383 mask = E1000_SWFW_PHY2_SM;
384 else if (hw->bus.func == E1000_FUNC_3)
385 mask = E1000_SWFW_PHY3_SM;
337
338 return e1000_acquire_swfw_sync_82575(hw, mask);
339}
340
341/**
342 * e1000_release_phy_82575 - Release rights to access PHY
343 * @hw: pointer to the HW structure
344 *
345 * A wrapper to release access rights to the correct PHY.
346 **/
347static void e1000_release_phy_82575(struct e1000_hw *hw)
348{
349 u16 mask = E1000_SWFW_PHY0_SM;
350
351 DEBUGFUNC("e1000_release_phy_82575");
352
353 if (hw->bus.func == E1000_FUNC_1)
354 mask = E1000_SWFW_PHY1_SM;
386
387 return e1000_acquire_swfw_sync_82575(hw, mask);
388}
389
390/**
391 * e1000_release_phy_82575 - Release rights to access PHY
392 * @hw: pointer to the HW structure
393 *
394 * A wrapper to release access rights to the correct PHY.
395 **/
396static void e1000_release_phy_82575(struct e1000_hw *hw)
397{
398 u16 mask = E1000_SWFW_PHY0_SM;
399
400 DEBUGFUNC("e1000_release_phy_82575");
401
402 if (hw->bus.func == E1000_FUNC_1)
403 mask = E1000_SWFW_PHY1_SM;
404 else if (hw->bus.func == E1000_FUNC_2)
405 mask = E1000_SWFW_PHY2_SM;
406 else if (hw->bus.func == E1000_FUNC_3)
407 mask = E1000_SWFW_PHY3_SM;
355
356 e1000_release_swfw_sync_82575(hw, mask);
357}
358
359/**
360 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
361 * @hw: pointer to the HW structure
362 * @offset: register offset to be read
363 * @data: pointer to the read data
364 *
365 * Reads the PHY register at offset using the serial gigabit media independent
366 * interface and stores the retrieved information in data.
367 **/
368static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
369 u16 *data)
370{
408
409 e1000_release_swfw_sync_82575(hw, mask);
410}
411
412/**
413 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
414 * @hw: pointer to the HW structure
415 * @offset: register offset to be read
416 * @data: pointer to the read data
417 *
418 * Reads the PHY register at offset using the serial gigabit media independent
419 * interface and stores the retrieved information in data.
420 **/
421static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
422 u16 *data)
423{
371 struct e1000_phy_info *phy = &hw->phy;
372 u32 i, i2ccmd = 0;
424 s32 ret_val = -E1000_ERR_PARAM;
373
374 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
375
376 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
377 DEBUGOUT1("PHY Address %u is out of range\n", offset);
425
426 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
427
428 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
429 DEBUGOUT1("PHY Address %u is out of range\n", offset);
378 return -E1000_ERR_PARAM;
430 goto out;
379 }
380
431 }
432
381 /*
382 * Set up Op-code, Phy Address, and register address in the I2CCMD
383 * register. The MAC will take care of interfacing with the
384 * PHY to retrieve the desired data.
385 */
386 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
387 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
388 (E1000_I2CCMD_OPCODE_READ));
433 ret_val = hw->phy.ops.acquire(hw);
434 if (ret_val)
435 goto out;
389
436
390 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
437 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
391
438
392 /* Poll the ready bit to see if the I2C read completed */
393 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
394 usec_delay(50);
395 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
396 if (i2ccmd & E1000_I2CCMD_READY)
397 break;
398 }
399 if (!(i2ccmd & E1000_I2CCMD_READY)) {
400 DEBUGOUT("I2CCMD Read did not complete\n");
401 return -E1000_ERR_PHY;
402 }
403 if (i2ccmd & E1000_I2CCMD_ERROR) {
404 DEBUGOUT("I2CCMD Error bit set\n");
405 return -E1000_ERR_PHY;
406 }
439 hw->phy.ops.release(hw);
407
440
408 /* Need to byte-swap the 16-bit value. */
409 *data = ((i2ccmd >> 8) & 0x00FF) | ((i2ccmd << 8) & 0xFF00);
410
411 return E1000_SUCCESS;
441out:
442 return ret_val;
412}
413
414/**
415 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
416 * @hw: pointer to the HW structure
417 * @offset: register offset to write to
418 * @data: data to write at register offset
419 *
420 * Writes the data to PHY register at the offset using the serial gigabit
421 * media independent interface.
422 **/
423static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
424 u16 data)
425{
443}
444
445/**
446 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
447 * @hw: pointer to the HW structure
448 * @offset: register offset to write to
449 * @data: data to write at register offset
450 *
451 * Writes the data to PHY register at the offset using the serial gigabit
452 * media independent interface.
453 **/
454static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
455 u16 data)
456{
426 struct e1000_phy_info *phy = &hw->phy;
427 u32 i, i2ccmd = 0;
428 u16 phy_data_swapped;
457 s32 ret_val = -E1000_ERR_PARAM;
429
430 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
431
432 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
433 DEBUGOUT1("PHY Address %d is out of range\n", offset);
458
459 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
460
461 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
462 DEBUGOUT1("PHY Address %d is out of range\n", offset);
434 return -E1000_ERR_PARAM;
463 goto out;
435 }
436
464 }
465
437 /* Swap the data bytes for the I2C interface */
438 phy_data_swapped = ((data >> 8) & 0x00FF) | ((data << 8) & 0xFF00);
466 ret_val = hw->phy.ops.acquire(hw);
467 if (ret_val)
468 goto out;
439
469
440 /*
441 * Set up Op-code, Phy Address, and register address in the I2CCMD
442 * register. The MAC will take care of interfacing with the
443 * PHY to retrieve the desired data.
444 */
445 i2ccmd = ((offset << E1000_I2CCMD_REG_ADDR_SHIFT) |
446 (phy->addr << E1000_I2CCMD_PHY_ADDR_SHIFT) |
447 E1000_I2CCMD_OPCODE_WRITE |
448 phy_data_swapped);
470 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
449
471
450 E1000_WRITE_REG(hw, E1000_I2CCMD, i2ccmd);
472 hw->phy.ops.release(hw);
451
473
452 /* Poll the ready bit to see if the I2C read completed */
453 for (i = 0; i < E1000_I2CCMD_PHY_TIMEOUT; i++) {
454 usec_delay(50);
455 i2ccmd = E1000_READ_REG(hw, E1000_I2CCMD);
456 if (i2ccmd & E1000_I2CCMD_READY)
457 break;
458 }
459 if (!(i2ccmd & E1000_I2CCMD_READY)) {
460 DEBUGOUT("I2CCMD Write did not complete\n");
461 return -E1000_ERR_PHY;
462 }
463 if (i2ccmd & E1000_I2CCMD_ERROR) {
464 DEBUGOUT("I2CCMD Error bit set\n");
465 return -E1000_ERR_PHY;
466 }
467
468 return E1000_SUCCESS;
474out:
475 return ret_val;
469}
470
471/**
472 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
473 * @hw: pointer to the HW structure
474 *
475 * Retrieves the PHY address and ID for both PHY's which do and do not use
476 * sgmi interface.
477 **/
478static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
479{
480 struct e1000_phy_info *phy = &hw->phy;
481 s32 ret_val = E1000_SUCCESS;
482 u16 phy_id;
476}
477
478/**
479 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
480 * @hw: pointer to the HW structure
481 *
482 * Retrieves the PHY address and ID for both PHY's which do and do not use
483 * sgmi interface.
484 **/
485static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
486{
487 struct e1000_phy_info *phy = &hw->phy;
488 s32 ret_val = E1000_SUCCESS;
489 u16 phy_id;
490 u32 ctrl_ext;
483
484 DEBUGFUNC("e1000_get_phy_id_82575");
485
486 /*
487 * For SGMII PHYs, we try the list of possible addresses until
488 * we find one that works. For non-SGMII PHYs
489 * (e.g. integrated copper PHYs), an address of 1 should
490 * work. The result of this function should mean phy->phy_addr
491 * and phy->id are set correctly.
492 */
491
492 DEBUGFUNC("e1000_get_phy_id_82575");
493
494 /*
495 * For SGMII PHYs, we try the list of possible addresses until
496 * we find one that works. For non-SGMII PHYs
497 * (e.g. integrated copper PHYs), an address of 1 should
498 * work. The result of this function should mean phy->phy_addr
499 * and phy->id are set correctly.
500 */
493 if (!(e1000_sgmii_active_82575(hw))) {
501 if (!e1000_sgmii_active_82575(hw)) {
494 phy->addr = 1;
495 ret_val = e1000_get_phy_id(hw);
496 goto out;
497 }
498
502 phy->addr = 1;
503 ret_val = e1000_get_phy_id(hw);
504 goto out;
505 }
506
507 /* Power on sgmii phy if it is disabled */
508 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
509 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
510 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
511 E1000_WRITE_FLUSH(hw);
512 msec_delay(300);
513
499 /*
500 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
501 * Therefore, we need to test 1-7
502 */
503 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
504 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
505 if (ret_val == E1000_SUCCESS) {
506 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",

--- 10 unchanged lines hidden (view full) ---

517 phy->addr);
518 }
519 }
520
521 /* A valid PHY type couldn't be found. */
522 if (phy->addr == 8) {
523 phy->addr = 0;
524 ret_val = -E1000_ERR_PHY;
514 /*
515 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
516 * Therefore, we need to test 1-7
517 */
518 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
519 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
520 if (ret_val == E1000_SUCCESS) {
521 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",

--- 10 unchanged lines hidden (view full) ---

532 phy->addr);
533 }
534 }
535
536 /* A valid PHY type couldn't be found. */
537 if (phy->addr == 8) {
538 phy->addr = 0;
539 ret_val = -E1000_ERR_PHY;
525 goto out;
540 } else {
541 ret_val = e1000_get_phy_id(hw);
526 }
527
542 }
543
528 ret_val = e1000_get_phy_id(hw);
544 /* restore previous sfp cage power state */
545 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
529
530out:
531 return ret_val;
532}
533
534/**
535 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
536 * @hw: pointer to the HW structure

--- 250 unchanged lines hidden (view full) ---

787 s32 timeout = PHY_CFG_TIMEOUT;
788 s32 ret_val = E1000_SUCCESS;
789 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
790
791 DEBUGFUNC("e1000_get_cfg_done_82575");
792
793 if (hw->bus.func == E1000_FUNC_1)
794 mask = E1000_NVM_CFG_DONE_PORT_1;
546
547out:
548 return ret_val;
549}
550
551/**
552 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
553 * @hw: pointer to the HW structure

--- 250 unchanged lines hidden (view full) ---

804 s32 timeout = PHY_CFG_TIMEOUT;
805 s32 ret_val = E1000_SUCCESS;
806 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
807
808 DEBUGFUNC("e1000_get_cfg_done_82575");
809
810 if (hw->bus.func == E1000_FUNC_1)
811 mask = E1000_NVM_CFG_DONE_PORT_1;
812 else if (hw->bus.func == E1000_FUNC_2)
813 mask = E1000_NVM_CFG_DONE_PORT_2;
814 else if (hw->bus.func == E1000_FUNC_3)
815 mask = E1000_NVM_CFG_DONE_PORT_3;
795 while (timeout) {
796 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
797 break;
798 msec_delay(1);
799 timeout--;
800 }
816 while (timeout) {
817 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
818 break;
819 msec_delay(1);
820 timeout--;
821 }
801 if (!timeout) {
822 if (!timeout)
802 DEBUGOUT("MNG configuration cycle has not completed.\n");
823 DEBUGOUT("MNG configuration cycle has not completed.\n");
803 }
804
805 /* If EEPROM is not marked present, init the PHY manually */
806 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
824
825 /* If EEPROM is not marked present, init the PHY manually */
826 if (((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0) &&
807 (hw->phy.type == e1000_phy_igp_3)) {
827 (hw->phy.type == e1000_phy_igp_3))
808 e1000_phy_init_script_igp3(hw);
828 e1000_phy_init_script_igp3(hw);
809 }
810
811 return ret_val;
812}
813
814/**
815 * e1000_get_link_up_info_82575 - Get link speed/duplex info
816 * @hw: pointer to the HW structure
817 * @speed: stores the current speed

--- 5 unchanged lines hidden (view full) ---

823 **/
824static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
825 u16 *duplex)
826{
827 s32 ret_val;
828
829 DEBUGFUNC("e1000_get_link_up_info_82575");
830
829
830 return ret_val;
831}
832
833/**
834 * e1000_get_link_up_info_82575 - Get link speed/duplex info
835 * @hw: pointer to the HW structure
836 * @speed: stores the current speed

--- 5 unchanged lines hidden (view full) ---

842 **/
843static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
844 u16 *duplex)
845{
846 s32 ret_val;
847
848 DEBUGFUNC("e1000_get_link_up_info_82575");
849
831 if (hw->phy.media_type != e1000_media_type_copper ||
832 e1000_sgmii_active_82575(hw)) {
850 if (hw->phy.media_type != e1000_media_type_copper)
833 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
834 duplex);
851 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
852 duplex);
835 } else {
853 else
836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
837 duplex);
854 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
855 duplex);
838 }
839
840 return ret_val;
841}
842
843/**
844 * e1000_check_for_link_82575 - Check for link
845 * @hw: pointer to the HW structure
846 *
847 * If sgmii is enabled, then use the pcs register to determine link, otherwise
848 * use the generic interface for determining link.
849 **/
850static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
851{
852 s32 ret_val;
853 u16 speed, duplex;
854
855 DEBUGFUNC("e1000_check_for_link_82575");
856
856
857 return ret_val;
858}
859
860/**
861 * e1000_check_for_link_82575 - Check for link
862 * @hw: pointer to the HW structure
863 *
864 * If sgmii is enabled, then use the pcs register to determine link, otherwise
865 * use the generic interface for determining link.
866 **/
867static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
868{
869 s32 ret_val;
870 u16 speed, duplex;
871
872 DEBUGFUNC("e1000_check_for_link_82575");
873
857 /* SGMII link check is done through the PCS register. */
858 if ((hw->phy.media_type != e1000_media_type_copper) ||
859 (e1000_sgmii_active_82575(hw))) {
874 if (hw->phy.media_type != e1000_media_type_copper) {
860 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
861 &duplex);
862 /*
863 * Use this flag to determine if link needs to be checked or
864 * not. If we have link clear the flag so that we do not
865 * continue to check for link.
866 */
867 hw->mac.get_link_status = !hw->mac.serdes_has_link;

--- 57 unchanged lines hidden (view full) ---

925 *duplex = HALF_DUPLEX;
926 }
927 }
928
929 return E1000_SUCCESS;
930}
931
932/**
875 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
876 &duplex);
877 /*
878 * Use this flag to determine if link needs to be checked or
879 * not. If we have link clear the flag so that we do not
880 * continue to check for link.
881 */
882 hw->mac.get_link_status = !hw->mac.serdes_has_link;

--- 57 unchanged lines hidden (view full) ---

940 *duplex = HALF_DUPLEX;
941 }
942 }
943
944 return E1000_SUCCESS;
945}
946
947/**
933 * e1000_shutdown_fiber_serdes_link_82575 - Remove link during power down
948 * e1000_shutdown_serdes_link_82575 - Remove link during power down
934 * @hw: pointer to the HW structure
935 *
949 * @hw: pointer to the HW structure
950 *
936 * In the case of fiber serdes shut down optics and PCS on driver unload
951 * In the case of serdes shut down sfp and PCS on driver unload
937 * when management pass thru is not enabled.
938 **/
952 * when management pass thru is not enabled.
953 **/
939void e1000_shutdown_fiber_serdes_link_82575(struct e1000_hw *hw)
954void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
940{
941 u32 reg;
942 u16 eeprom_data = 0;
943
955{
956 u32 reg;
957 u16 eeprom_data = 0;
958
944 if (hw->phy.media_type != e1000_media_type_internal_serdes)
959 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
960 !e1000_sgmii_active_82575(hw))
945 return;
946
947 if (hw->bus.func == E1000_FUNC_0)
948 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
961 return;
962
963 if (hw->bus.func == E1000_FUNC_0)
964 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
965 else if ((hw->mac.type == e1000_82580) ||
966 (hw->mac.type == e1000_82580er))
967 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
968 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
969 &eeprom_data);
949 else if (hw->bus.func == E1000_FUNC_1)
950 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
951
952 /*
953 * If APM is not enabled in the EEPROM and management interface is
954 * not enabled, then power down.
955 */
956 if (!(eeprom_data & E1000_NVM_APME_82575) &&
957 !e1000_enable_mng_pass_thru(hw)) {
958 /* Disable PCS to turn off link */
959 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
960 reg &= ~E1000_PCS_CFG_PCS_EN;
961 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
962
963 /* shutdown the laser */
964 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
970 else if (hw->bus.func == E1000_FUNC_1)
971 hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
972
973 /*
974 * If APM is not enabled in the EEPROM and management interface is
975 * not enabled, then power down.
976 */
977 if (!(eeprom_data & E1000_NVM_APME_82575) &&
978 !e1000_enable_mng_pass_thru(hw)) {
979 /* Disable PCS to turn off link */
980 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
981 reg &= ~E1000_PCS_CFG_PCS_EN;
982 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
983
984 /* shutdown the laser */
985 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
965 reg |= E1000_CTRL_EXT_SDP7_DATA;
986 reg |= E1000_CTRL_EXT_SDP3_DATA;
966 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
967
987 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
988
968 /* flush the write to verfiy completion */
989 /* flush the write to verify completion */
969 E1000_WRITE_FLUSH(hw);
970 msec_delay(1);
971 }
972
973 return;
974}
975
976/**
990 E1000_WRITE_FLUSH(hw);
991 msec_delay(1);
992 }
993
994 return;
995}
996
997/**
977 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
978 * @hw: pointer to the HW structure
979 * @enable: state to enter, either enabled or disabled
980 *
981 * enables/disables L2 switch loopback functionality
982 **/
983void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
984{
985 u32 reg;
986
987 reg = E1000_READ_REG(hw, E1000_DTXSWC);
988 if (enable)
989 reg |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
990 else
991 reg &= ~(E1000_DTXSWC_VMDQ_LOOPBACK_EN);
992 E1000_WRITE_REG(hw, E1000_DTXSWC, reg);
993}
994
995/**
996 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
997 * @hw: pointer to the HW structure
998 * @enable: state to enter, either enabled or disabled
999 *
1000 * enables/disables replication of packets across multiple pools
1001 **/
1002void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1003{
1004 u32 reg;
1005
1006 reg = E1000_READ_REG(hw, E1000_VT_CTL);
1007 if (enable)
1008 reg |= E1000_VT_CTL_VM_REPL_EN;
1009 else
1010 reg &= ~(E1000_VT_CTL_VM_REPL_EN);
1011
1012 E1000_WRITE_REG(hw, E1000_VT_CTL, reg);
1013}
1014
1015/**
1016 * e1000_reset_hw_82575 - Reset hardware
1017 * @hw: pointer to the HW structure
1018 *
1019 * This resets the hardware into a known state.
1020 **/
1021static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1022{
1023 u32 ctrl, icr;

--- 82 unchanged lines hidden (view full) ---

1106 /* Setup the receive address */
1107 e1000_init_rx_addrs_generic(hw, rar_count);
1108
1109 /* Zero out the Multicast HASH table */
1110 DEBUGOUT("Zeroing the MTA\n");
1111 for (i = 0; i < mac->mta_reg_count; i++)
1112 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1113
998 * e1000_reset_hw_82575 - Reset hardware
999 * @hw: pointer to the HW structure
1000 *
1001 * This resets the hardware into a known state.
1002 **/
1003static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1004{
1005 u32 ctrl, icr;

--- 82 unchanged lines hidden (view full) ---

1088 /* Setup the receive address */
1089 e1000_init_rx_addrs_generic(hw, rar_count);
1090
1091 /* Zero out the Multicast HASH table */
1092 DEBUGOUT("Zeroing the MTA\n");
1093 for (i = 0; i < mac->mta_reg_count; i++)
1094 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1095
1096 /* Zero out the Unicast HASH table */
1097 DEBUGOUT("Zeroing the UTA\n");
1098 for (i = 0; i < mac->uta_reg_count; i++)
1099 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1100
1114 /* Setup link and flow control */
1115 ret_val = mac->ops.setup_link(hw);
1116
1117 /*
1118 * Clear all of the statistics registers (clear on read). It is
1119 * important that we do this after we have tried to establish link
1120 * because the symbol error count will increment wildly if there
1121 * is no link.

--- 10 unchanged lines hidden (view full) ---

1132 * Configures the link for auto-neg or forced speed and duplex. Then we check
1133 * for link, once link is established calls to configure collision distance
1134 * and flow control are called.
1135 **/
1136static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1137{
1138 u32 ctrl;
1139 s32 ret_val;
1101 /* Setup link and flow control */
1102 ret_val = mac->ops.setup_link(hw);
1103
1104 /*
1105 * Clear all of the statistics registers (clear on read). It is
1106 * important that we do this after we have tried to establish link
1107 * because the symbol error count will increment wildly if there
1108 * is no link.

--- 10 unchanged lines hidden (view full) ---

1119 * Configures the link for auto-neg or forced speed and duplex. Then we check
1120 * for link, once link is established calls to configure collision distance
1121 * and flow control are called.
1122 **/
1123static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1124{
1125 u32 ctrl;
1126 s32 ret_val;
1140 bool link;
1141
1142 DEBUGFUNC("e1000_setup_copper_link_82575");
1143
1144 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1145 ctrl |= E1000_CTRL_SLU;
1146 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1147 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1148
1127
1128 DEBUGFUNC("e1000_setup_copper_link_82575");
1129
1130 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1131 ctrl |= E1000_CTRL_SLU;
1132 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1133 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1134
1135 ret_val = e1000_setup_serdes_link_82575(hw);
1136 if (ret_val)
1137 goto out;
1138
1139 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1140 /* allow time for SFP cage time to power up phy */
1141 msec_delay(300);
1142
1143 ret_val = hw->phy.ops.reset(hw);
1144 if (ret_val) {
1145 DEBUGOUT("Error resetting the PHY.\n");
1146 goto out;
1147 }
1148 }
1149 switch (hw->phy.type) {
1150 case e1000_phy_m88:
1151 ret_val = e1000_copper_link_setup_m88(hw);
1152 break;
1153 case e1000_phy_igp_3:
1154 ret_val = e1000_copper_link_setup_igp(hw);
1155 break;
1149 switch (hw->phy.type) {
1150 case e1000_phy_m88:
1151 ret_val = e1000_copper_link_setup_m88(hw);
1152 break;
1153 case e1000_phy_igp_3:
1154 ret_val = e1000_copper_link_setup_igp(hw);
1155 break;
1156 case e1000_phy_82580:
1157 ret_val = e1000_copper_link_setup_82577(hw);
1158 break;
1156 default:
1157 ret_val = -E1000_ERR_PHY;
1158 break;
1159 }
1160
1161 if (ret_val)
1162 goto out;
1163
1159 default:
1160 ret_val = -E1000_ERR_PHY;
1161 break;
1162 }
1163
1164 if (ret_val)
1165 goto out;
1166
1164 if (hw->mac.autoneg) {
1165 /*
1166 * Setup autoneg and flow control advertisement
1167 * and perform autonegotiation.
1168 */
1169 ret_val = e1000_copper_link_autoneg(hw);
1170 if (ret_val)
1171 goto out;
1172 } else {
1173 /*
1174 * PHY will be set to 10H, 10F, 100H or 100F
1175 * depending on user settings.
1176 */
1177 DEBUGOUT("Forcing Speed and Duplex\n");
1178 ret_val = hw->phy.ops.force_speed_duplex(hw);
1179 if (ret_val) {
1180 DEBUGOUT("Error Forcing Speed and Duplex\n");
1181 goto out;
1182 }
1183 }
1184
1185 ret_val = e1000_configure_pcs_link_82575(hw);
1186 if (ret_val)
1187 goto out;
1188
1189 /*
1190 * Check link status. Wait up to 100 microseconds for link to become
1191 * valid.
1192 */
1193 ret_val = e1000_phy_has_link_generic(hw,
1194 COPPER_LINK_UP_LIMIT,
1195 10,
1196 &link);
1197 if (ret_val)
1198 goto out;
1199
1200 if (link) {
1201 DEBUGOUT("Valid link established!!!\n");
1202 /* Config the MAC and PHY after link is up */
1203 e1000_config_collision_dist_generic(hw);
1204 ret_val = e1000_config_fc_after_link_up_generic(hw);
1205 } else {
1206 DEBUGOUT("Unable to establish link!!!\n");
1207 }
1208
1167 ret_val = e1000_setup_copper_link_generic(hw);
1209out:
1210 return ret_val;
1211}
1212
1213/**
1168out:
1169 return ret_val;
1170}
1171
1172/**
1214 * e1000_setup_fiber_serdes_link_82575 - Setup link for fiber/serdes
1173 * e1000_setup_serdes_link_82575 - Setup link for serdes
1215 * @hw: pointer to the HW structure
1216 *
1174 * @hw: pointer to the HW structure
1175 *
1217 * Configures speed and duplex for fiber and serdes links.
1176 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1177 * used on copper connections where the serialized gigabit media independent
1178 * interface (sgmii), or serdes fiber is being used. Configures the link
1179 * for auto-negotiation or forces speed/duplex.
1218 **/
1180 **/
1219static s32 e1000_setup_fiber_serdes_link_82575(struct e1000_hw *hw)
1181static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1220{
1182{
1221 u32 reg;
1183 u32 ctrl_ext, ctrl_reg, reg;
1184 bool pcs_autoneg;
1222
1185
1223 DEBUGFUNC("e1000_setup_fiber_serdes_link_82575");
1186 DEBUGFUNC("e1000_setup_serdes_link_82575");
1224
1187
1188 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1189 !e1000_sgmii_active_82575(hw))
1190 return E1000_SUCCESS;
1191
1225 /*
1226 * On the 82575, SerDes loopback mode persists until it is
1227 * explicitly turned off or a power cycle is performed. A read to
1228 * the register does not indicate its status. Therefore, we ensure
1229 * loopback mode is disabled during initialization.
1230 */
1231 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1232
1192 /*
1193 * On the 82575, SerDes loopback mode persists until it is
1194 * explicitly turned off or a power cycle is performed. A read to
1195 * the register does not indicate its status. Therefore, we ensure
1196 * loopback mode is disabled during initialization.
1197 */
1198 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1199
1233 /* Force link up, set 1gb */
1234 reg = E1000_READ_REG(hw, E1000_CTRL);
1235 reg |= E1000_CTRL_SLU | E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD;
1200 /* power on the sfp cage if present */
1201 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1202 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1203 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1204
1205 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1206 ctrl_reg |= E1000_CTRL_SLU;
1207
1236 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1237 /* set both sw defined pins */
1208 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576) {
1209 /* set both sw defined pins */
1238 reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1210 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1211
1212 /* Set switch control to serdes energy detect */
1213 reg = E1000_READ_REG(hw, E1000_CONNSW);
1214 reg |= E1000_CONNSW_ENRGSRC;
1215 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1239 }
1216 }
1240 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1241 /* Power on phy for 82576 fiber adapters */
1242 if (hw->mac.type == e1000_82576) {
1243 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244 reg &= ~E1000_CTRL_EXT_SDP7_DATA;
1245 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1217
1218 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1219
1220 /* default pcs_autoneg to the same setting as mac autoneg */
1221 pcs_autoneg = hw->mac.autoneg;
1222
1223 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1224 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1225 /* sgmii mode lets the phy handle forcing speed/duplex */
1226 pcs_autoneg = TRUE;
1227 /* autoneg time out should be disabled for SGMII mode */
1228 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1229 break;
1230 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1231 /* disable PCS autoneg and support parallel detect only */
1232 pcs_autoneg = FALSE;
1233 default:
1234 /*
1235 * non-SGMII modes only supports a speed of 1000/Full for the
1236 * link so it is best to just force the MAC and let the pcs
1237 * link either autoneg or be forced to 1000/Full
1238 */
1239 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1240 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1241
1242 /* set speed of 1000/Full if speed/duplex is forced */
1243 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1244 break;
1246 }
1247
1245 }
1246
1248 /* Set switch control to serdes energy detect */
1249 reg = E1000_READ_REG(hw, E1000_CONNSW);
1250 reg |= E1000_CONNSW_ENRGSRC;
1251 E1000_WRITE_REG(hw, E1000_CONNSW, reg);
1247 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1252
1253 /*
1254 * New SerDes mode allows for forcing speed or autonegotiating speed
1255 * at 1gb. Autoneg should be default set by most drivers. This is the
1256 * mode that will be compatible with older link partners and switches.
1257 * However, both are supported by the hardware and some drivers/tools.
1258 */
1248
1249 /*
1250 * New SerDes mode allows for forcing speed or autonegotiating speed
1251 * at 1gb. Autoneg should be default set by most drivers. This is the
1252 * mode that will be compatible with older link partners and switches.
1253 * However, both are supported by the hardware and some drivers/tools.
1254 */
1259 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1260
1261 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1255 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1262 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1256 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1263
1257
1264 if (hw->mac.autoneg) {
1258 /*
1259 * We force flow control to prevent the CTRL register values from being
1260 * overwritten by the autonegotiated flow control values
1261 */
1262 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1263
1264 if (pcs_autoneg) {
1265 /* Set PCS register for autoneg */
1265 /* Set PCS register for autoneg */
1266 reg |= E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1267 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1268 E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1269 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1270 DEBUGOUT1("Configuring Autoneg; PCS_LCTL = 0x%08X\n", reg);
1266 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1267 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1268 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1271 } else {
1269 } else {
1272 /* Set PCS register for forced speed */
1273 reg |= E1000_PCS_LCTL_FLV_LINK_UP | /* Force link up */
1274 E1000_PCS_LCTL_FSV_1000 | /* Force 1000 */
1275 E1000_PCS_LCTL_FDV_FULL | /* SerDes Full duplex */
1276 E1000_PCS_LCTL_FSD | /* Force Speed */
1277 E1000_PCS_LCTL_FORCE_LINK; /* Force Link */
1278 DEBUGOUT1("Configuring Forced Link; PCS_LCTL = 0x%08X\n", reg);
1279 }
1270 /* Set PCS register for forced link */
1271 reg |= E1000_PCS_LCTL_FSD | /* Force Speed */
1272 E1000_PCS_LCTL_FORCE_LINK | /* Force Link */
1273 E1000_PCS_LCTL_FLV_LINK_UP; /* Force link value up */
1280
1274
1281 if (hw->mac.type == e1000_82576) {
1282 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1283 e1000_force_mac_fc_generic(hw);
1275 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1284 }
1285
1286 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1287
1276 }
1277
1278 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1279
1280 if (!e1000_sgmii_active_82575(hw))
1281 e1000_force_mac_fc_generic(hw);
1282
1288 return E1000_SUCCESS;
1289}
1290
1291/**
1292 * e1000_valid_led_default_82575 - Verify a valid default LED config
1293 * @hw: pointer to the HW structure
1294 * @data: pointer to the NVM (EEPROM)
1295 *

--- 23 unchanged lines hidden (view full) ---

1319 break;
1320 }
1321 }
1322out:
1323 return ret_val;
1324}
1325
1326/**
1283 return E1000_SUCCESS;
1284}
1285
1286/**
1287 * e1000_valid_led_default_82575 - Verify a valid default LED config
1288 * @hw: pointer to the HW structure
1289 * @data: pointer to the NVM (EEPROM)
1290 *

--- 23 unchanged lines hidden (view full) ---

1314 break;
1315 }
1316 }
1317out:
1318 return ret_val;
1319}
1320
1321/**
1327 * e1000_configure_pcs_link_82575 - Configure PCS link
1328 * @hw: pointer to the HW structure
1329 *
1330 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1331 * only used on copper connections where the serialized gigabit media
1332 * independent interface (sgmii) is being used. Configures the link
1333 * for auto-negotiation or forces speed/duplex.
1334 **/
1335static s32 e1000_configure_pcs_link_82575(struct e1000_hw *hw)
1336{
1337 struct e1000_mac_info *mac = &hw->mac;
1338 u32 reg = 0;
1339
1340 DEBUGFUNC("e1000_configure_pcs_link_82575");
1341
1342 if (hw->phy.media_type != e1000_media_type_copper ||
1343 !(e1000_sgmii_active_82575(hw)))
1344 goto out;
1345
1346 /* For SGMII, we need to issue a PCS autoneg restart */
1347 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1348
1349 /* AN time out should be disabled for SGMII mode */
1350 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1351
1352 if (mac->autoneg) {
1353 /* Make sure forced speed and force link are not set */
1354 reg &= ~(E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1355
1356 /*
1357 * The PHY should be setup prior to calling this function.
1358 * All we need to do is restart autoneg and enable autoneg.
1359 */
1360 reg |= E1000_PCS_LCTL_AN_RESTART | E1000_PCS_LCTL_AN_ENABLE;
1361 } else {
1362 /* Set PCS register for forced speed */
1363
1364 /* Turn off bits for full duplex, speed, and autoneg */
1365 reg &= ~(E1000_PCS_LCTL_FSV_1000 |
1366 E1000_PCS_LCTL_FSV_100 |
1367 E1000_PCS_LCTL_FDV_FULL |
1368 E1000_PCS_LCTL_AN_ENABLE);
1369
1370 /* Check for duplex first */
1371 if (mac->forced_speed_duplex & E1000_ALL_FULL_DUPLEX)
1372 reg |= E1000_PCS_LCTL_FDV_FULL;
1373
1374 /* Now set speed */
1375 if (mac->forced_speed_duplex & E1000_ALL_100_SPEED)
1376 reg |= E1000_PCS_LCTL_FSV_100;
1377
1378 /* Force speed and force link */
1379 reg |= E1000_PCS_LCTL_FSD |
1380 E1000_PCS_LCTL_FORCE_LINK |
1381 E1000_PCS_LCTL_FLV_LINK_UP;
1382
1383 DEBUGOUT1("Wrote 0x%08X to PCS_LCTL to configure forced link\n",
1384 reg);
1385 }
1386 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1387
1388out:
1389 return E1000_SUCCESS;
1390}
1391
1392/**
1393 * e1000_sgmii_active_82575 - Return sgmii state
1394 * @hw: pointer to the HW structure
1395 *
1396 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1397 * which can be enabled for use in the embedded applications. Simply
1398 * return the current state of the sgmii interface.
1399 **/
1400static bool e1000_sgmii_active_82575(struct e1000_hw *hw)

--- 142 unchanged lines hidden (view full) ---

1543 E1000_READ_REG(hw, E1000_HTCBDPC);
1544 E1000_READ_REG(hw, E1000_HGORCL);
1545 E1000_READ_REG(hw, E1000_HGORCH);
1546 E1000_READ_REG(hw, E1000_HGOTCL);
1547 E1000_READ_REG(hw, E1000_HGOTCH);
1548 E1000_READ_REG(hw, E1000_LENERRS);
1549
1550 /* This register should not be read in copper configurations */
1322 * e1000_sgmii_active_82575 - Return sgmii state
1323 * @hw: pointer to the HW structure
1324 *
1325 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1326 * which can be enabled for use in the embedded applications. Simply
1327 * return the current state of the sgmii interface.
1328 **/
1329static bool e1000_sgmii_active_82575(struct e1000_hw *hw)

--- 142 unchanged lines hidden (view full) ---

1472 E1000_READ_REG(hw, E1000_HTCBDPC);
1473 E1000_READ_REG(hw, E1000_HGORCL);
1474 E1000_READ_REG(hw, E1000_HGORCH);
1475 E1000_READ_REG(hw, E1000_HGOTCL);
1476 E1000_READ_REG(hw, E1000_HGOTCH);
1477 E1000_READ_REG(hw, E1000_LENERRS);
1478
1479 /* This register should not be read in copper configurations */
1551 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1480 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
1481 e1000_sgmii_active_82575(hw))
1552 E1000_READ_REG(hw, E1000_SCVPC);
1553}
1554
1555/**
1556 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1557 * @hw: pointer to the HW structure
1558 *
1559 * After rx enable if managability is enabled then there is likely some

--- 112 unchanged lines hidden (view full) ---

1672out:
1673 /* disable completion timeout resend */
1674 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1675
1676 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1677 return ret_val;
1678}
1679
1482 E1000_READ_REG(hw, E1000_SCVPC);
1483}
1484
1485/**
1486 * e1000_rx_fifo_flush_82575 - Clean rx fifo after RX enable
1487 * @hw: pointer to the HW structure
1488 *
1489 * After rx enable if managability is enabled then there is likely some

--- 112 unchanged lines hidden (view full) ---

1602out:
1603 /* disable completion timeout resend */
1604 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
1605
1606 E1000_WRITE_REG(hw, E1000_GCR, gcr);
1607 return ret_val;
1608}
1609
1610/**
1611 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
1612 * @hw: pointer to the hardware struct
1613 * @enable: state to enter, either enabled or disabled
1614 *
1615 * enables/disables L2 switch loopback functionality.
1616 **/
1617void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
1618{
1619 u32 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
1620
1621 if (enable)
1622 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1623 else
1624 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
1625
1626 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
1627}
1628
1629/**
1630 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
1631 * @hw: pointer to the hardware struct
1632 * @enable: state to enter, either enabled or disabled
1633 *
1634 * enables/disables replication of packets across multiple pools.
1635 **/
1636void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
1637{
1638 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
1639
1640 if (enable)
1641 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
1642 else
1643 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
1644
1645 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
1646}
1647
1648/**
1649 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
1650 * @hw: pointer to the HW structure
1651 * @offset: register offset to be read
1652 * @data: pointer to the read data
1653 *
1654 * Reads the MDI control register in the PHY at offset and stores the
1655 * information read to data.
1656 **/
1657static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
1658{
1659 u32 mdicnfg = 0;
1660 s32 ret_val;
1661
1662 DEBUGFUNC("e1000_read_phy_reg_82580");
1663
1664 ret_val = hw->phy.ops.acquire(hw);
1665 if (ret_val)
1666 goto out;
1667
1668 /*
1669 * We config the phy address in MDICNFG register now. Same bits
1670 * as before. The values in MDIC can be written but will be
1671 * ignored. This allows us to call the old function after
1672 * configuring the PHY address in the new register
1673 */
1674 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1675 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1676
1677 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
1678
1679 hw->phy.ops.release(hw);
1680
1681out:
1682 return ret_val;
1683}
1684
1685/**
1686 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
1687 * @hw: pointer to the HW structure
1688 * @offset: register offset to write to
1689 * @data: data to write to register at offset
1690 *
1691 * Writes data to MDI control register in the PHY at offset.
1692 **/
1693static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
1694{
1695 u32 mdicnfg = 0;
1696 s32 ret_val;
1697
1698 DEBUGFUNC("e1000_write_phy_reg_82580");
1699
1700 ret_val = hw->phy.ops.acquire(hw);
1701 if (ret_val)
1702 goto out;
1703
1704 /*
1705 * We config the phy address in MDICNFG register now. Same bits
1706 * as before. The values in MDIC can be written but will be
1707 * ignored. This allows us to call the old function after
1708 * configuring the PHY address in the new register
1709 */
1710 mdicnfg = (hw->phy.addr << E1000_MDIC_PHY_SHIFT);
1711 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
1712
1713 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
1714
1715 hw->phy.ops.release(hw);
1716
1717out:
1718 return ret_val;
1719}
1720/**
1721 * e1000_reset_hw_82580 - Reset hardware
1722 * @hw: pointer to the HW structure
1723 *
1724 * This resets function or entire device (all ports, etc.)
1725 * to a known state.
1726 **/
1727static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
1728{
1729 s32 ret_val = E1000_SUCCESS;
1730 /* BH SW mailbox bit in SW_FW_SYNC */
1731 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
1732 u32 ctrl, icr;
1733 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
1734
1735 DEBUGFUNC("e1000_reset_hw_82580");
1736
1737 hw->dev_spec._82575.global_device_reset = FALSE;
1738
1739 /* Get current control state. */
1740 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1741
1742 /*
1743 * Prevent the PCI-E bus from sticking if there is no TLP connection
1744 * on the last TLP read/write transaction when MAC is reset.
1745 */
1746 ret_val = e1000_disable_pcie_master_generic(hw);
1747 if (ret_val)
1748 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1749
1750 DEBUGOUT("Masking off all interrupts\n");
1751 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1752 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1753 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1754 E1000_WRITE_FLUSH(hw);
1755
1756 msec_delay(10);
1757
1758 /* Determine whether or not a global dev reset is requested */
1759 if (global_device_reset &&
1760 e1000_acquire_swfw_sync_82575(hw, swmbsw_mask))
1761 global_device_reset = FALSE;
1762
1763 if (global_device_reset &&
1764 !(E1000_READ_REG(hw, E1000_STATUS) & E1000_STAT_DEV_RST_SET))
1765 ctrl |= E1000_CTRL_DEV_RST;
1766 else
1767 ctrl |= E1000_CTRL_RST;
1768
1769 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1770
1771 /* Add delay to insure DEV_RST has time to complete */
1772 if (global_device_reset)
1773 msec_delay(5);
1774
1775 ret_val = e1000_get_auto_rd_done_generic(hw);
1776 if (ret_val) {
1777 /*
1778 * When auto config read does not complete, do not
1779 * return with an error. This can happen in situations
1780 * where there is no eeprom and prevents getting link.
1781 */
1782 DEBUGOUT("Auto Read Done did not complete\n");
1783 }
1784
1785 /* If EEPROM is not present, run manual init scripts */
1786 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) == 0)
1787 e1000_reset_init_script_82575(hw);
1788
1789 /* clear global device reset status bit */
1790 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
1791
1792 /* Clear any pending interrupt events. */
1793 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1794 icr = E1000_READ_REG(hw, E1000_ICR);
1795
1796 /* Install any alternate MAC address into RAR0 */
1797 ret_val = e1000_check_alt_mac_addr_generic(hw);
1798
1799 /* Release semaphore */
1800 if (global_device_reset)
1801 e1000_release_swfw_sync_82575(hw, swmbsw_mask);
1802
1803 return ret_val;
1804}
1805
1806/**
1807 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual RX PBA size
1808 * @data: data received by reading RXPBS register
1809 *
1810 * The 82580 uses a table based approach for packet buffer allocation sizes.
1811 * This function converts the retrieved value into the correct table value
1812 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
1813 * 0x0 36 72 144 1 2 4 8 16
1814 * 0x8 35 70 140 rsv rsv rsv rsv rsv
1815 */
1816u16 e1000_rxpbs_adjust_82580(u32 data)
1817{
1818 u16 ret_val = 0;
1819
1820 if (data < E1000_82580_RXPBS_TABLE_SIZE)
1821 ret_val = e1000_82580_rxpbs_table[data];
1822
1823 return ret_val;
1824}
1825/**
1826 * e1000_erfuse_check_82580 - ER Fuse check
1827 * @hw: pointer to the HW structure
1828 *
1829 * This function returns the status of the ER Fuse
1830 **/
1831s32 e1000_erfuse_check_82580(struct e1000_hw *hw)
1832{
1833 s32 ret_val = E1000_SUCCESS;
1834 s32 ufuse_reg;
1835
1836 ufuse_reg = E1000_READ_REG(hw, E1000_UFUSE);
1837 if ((ufuse_reg & E1000_ERFUSE) == E1000_ERFUSE)
1838 ret_val = E1000_ERFUSE_FAILURE;
1839
1840 return ret_val;
1841}