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e1000_82571.c (218588) e1000_82571.c (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 218588 2011-02-12 00:07:40Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35/*
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule

--- 10 unchanged lines hidden (view full) ---

52#include "e1000_api.h"
53
54static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
55static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
56static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
57static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
58static void e1000_release_nvm_82571(struct e1000_hw *hw);
59static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
34
35/*
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule

--- 10 unchanged lines hidden (view full) ---

52#include "e1000_api.h"
53
54static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
55static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
56static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);
57static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw);
58static void e1000_release_nvm_82571(struct e1000_hw *hw);
59static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
60 u16 words, u16 *data);
60 u16 words, u16 *data);
61static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
62static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
63static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
64static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
61static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
62static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
63static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw);
64static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
65 bool active);
65 bool active);
66static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
67static s32 e1000_init_hw_82571(struct e1000_hw *hw);
68static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70static s32 e1000_led_on_82574(struct e1000_hw *hw);
71static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
73static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

--- 4 unchanged lines hidden (view full) ---

78static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
79static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
80static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
81static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
82static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
83static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
84static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
85static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
66static s32 e1000_reset_hw_82571(struct e1000_hw *hw);
67static s32 e1000_init_hw_82571(struct e1000_hw *hw);
68static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70static s32 e1000_led_on_82574(struct e1000_hw *hw);
71static s32 e1000_setup_link_82571(struct e1000_hw *hw);
72static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
73static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);

--- 4 unchanged lines hidden (view full) ---

78static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
79static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
80static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
81static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw);
82static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
83static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
84static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
85static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw,
86 bool active);
86 bool active);
87static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
87static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw,
88 bool active);
88 bool active);
89static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
90static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
89static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
90static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
91 u16 words, u16 *data);
91 u16 words, u16 *data);
92static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
93static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
94
95/**
96 * e1000_init_phy_params_82571 - Init PHY func ptrs.
97 * @hw: pointer to the HW structure
98 **/
99static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
100{
101 struct e1000_phy_info *phy = &hw->phy;
102 s32 ret_val = E1000_SUCCESS;
103
104 DEBUGFUNC("e1000_init_phy_params_82571");
105
106 if (hw->phy.media_type != e1000_media_type_copper) {
107 phy->type = e1000_phy_none;
108 goto out;
109 }
110
92static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw);
93static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
94
95/**
96 * e1000_init_phy_params_82571 - Init PHY func ptrs.
97 * @hw: pointer to the HW structure
98 **/
99static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
100{
101 struct e1000_phy_info *phy = &hw->phy;
102 s32 ret_val = E1000_SUCCESS;
103
104 DEBUGFUNC("e1000_init_phy_params_82571");
105
106 if (hw->phy.media_type != e1000_media_type_copper) {
107 phy->type = e1000_phy_none;
108 goto out;
109 }
110
111 phy->addr = 1;
112 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
113 phy->reset_delay_us = 100;
111 phy->addr = 1;
112 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
113 phy->reset_delay_us = 100;
114
114
115 phy->ops.check_reset_block = e1000_check_reset_block_generic;
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
119 phy->ops.power_up = e1000_power_up_phy_copper;
120 phy->ops.power_down = e1000_power_down_phy_copper_82571;
115 phy->ops.check_reset_block = e1000_check_reset_block_generic;
116 phy->ops.reset = e1000_phy_hw_reset_generic;
117 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
118 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
119 phy->ops.power_up = e1000_power_up_phy_copper;
120 phy->ops.power_down = e1000_power_down_phy_copper_82571;
121
122 switch (hw->mac.type) {
123 case e1000_82571:
124 case e1000_82572:
121
122 switch (hw->mac.type) {
123 case e1000_82571:
124 case e1000_82572:
125 phy->type = e1000_phy_igp_2;
126 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
127 phy->ops.get_info = e1000_get_phy_info_igp;
128 phy->ops.check_polarity = e1000_check_polarity_igp;
125 phy->type = e1000_phy_igp_2;
126 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
127 phy->ops.get_info = e1000_get_phy_info_igp;
128 phy->ops.check_polarity = e1000_check_polarity_igp;
129 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
129 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
130 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
131 phy->ops.read_reg = e1000_read_phy_reg_igp;
132 phy->ops.write_reg = e1000_write_phy_reg_igp;
133 phy->ops.acquire = e1000_get_hw_semaphore_82571;
134 phy->ops.release = e1000_put_hw_semaphore_82571;
130 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
131 phy->ops.read_reg = e1000_read_phy_reg_igp;
132 phy->ops.write_reg = e1000_write_phy_reg_igp;
133 phy->ops.acquire = e1000_get_hw_semaphore_82571;
134 phy->ops.release = e1000_put_hw_semaphore_82571;
135 break;
136 case e1000_82573:
135 break;
136 case e1000_82573:
137 phy->type = e1000_phy_m88;
138 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
139 phy->ops.get_info = e1000_get_phy_info_m88;
140 phy->ops.check_polarity = e1000_check_polarity_m88;
141 phy->ops.commit = e1000_phy_sw_reset_generic;
137 phy->type = e1000_phy_m88;
138 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
139 phy->ops.get_info = e1000_get_phy_info_m88;
140 phy->ops.check_polarity = e1000_check_polarity_m88;
141 phy->ops.commit = e1000_phy_sw_reset_generic;
142 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
142 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
143 phy->ops.get_cable_length = e1000_get_cable_length_m88;
144 phy->ops.read_reg = e1000_read_phy_reg_m88;
145 phy->ops.write_reg = e1000_write_phy_reg_m88;
146 phy->ops.acquire = e1000_get_hw_semaphore_82571;
147 phy->ops.release = e1000_put_hw_semaphore_82571;
143 phy->ops.get_cable_length = e1000_get_cable_length_m88;
144 phy->ops.read_reg = e1000_read_phy_reg_m88;
145 phy->ops.write_reg = e1000_write_phy_reg_m88;
146 phy->ops.acquire = e1000_get_hw_semaphore_82571;
147 phy->ops.release = e1000_put_hw_semaphore_82571;
148 break;
149 case e1000_82574:
150 case e1000_82583:
151 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
152
148 break;
149 case e1000_82574:
150 case e1000_82583:
151 E1000_MUTEX_INIT(&hw->dev_spec._82571.swflag_mutex);
152
153 phy->type = e1000_phy_bm;
154 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
155 phy->ops.get_info = e1000_get_phy_info_m88;
156 phy->ops.check_polarity = e1000_check_polarity_m88;
157 phy->ops.commit = e1000_phy_sw_reset_generic;
153 phy->type = e1000_phy_bm;
154 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
155 phy->ops.get_info = e1000_get_phy_info_m88;
156 phy->ops.check_polarity = e1000_check_polarity_m88;
157 phy->ops.commit = e1000_phy_sw_reset_generic;
158 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
158 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
159 phy->ops.get_cable_length = e1000_get_cable_length_m88;
160 phy->ops.read_reg = e1000_read_phy_reg_bm2;
161 phy->ops.write_reg = e1000_write_phy_reg_bm2;
162 phy->ops.acquire = e1000_get_hw_semaphore_82574;
163 phy->ops.release = e1000_put_hw_semaphore_82574;
164 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
165 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
159 phy->ops.get_cable_length = e1000_get_cable_length_m88;
160 phy->ops.read_reg = e1000_read_phy_reg_bm2;
161 phy->ops.write_reg = e1000_write_phy_reg_bm2;
162 phy->ops.acquire = e1000_get_hw_semaphore_82574;
163 phy->ops.release = e1000_put_hw_semaphore_82574;
164 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
165 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
166 break;
167 default:
168 ret_val = -E1000_ERR_PHY;
169 goto out;
170 break;
171 }
172
173 /* This can only be done after all function pointers are setup. */

--- 74 unchanged lines hidden (view full) ---

248 eecd &= ~E1000_EECD_AUPDEN;
249 E1000_WRITE_REG(hw, E1000_EECD, eecd);
250 break;
251 }
252 /* Fall Through */
253 default:
254 nvm->type = e1000_nvm_eeprom_spi;
255 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
166 break;
167 default:
168 ret_val = -E1000_ERR_PHY;
169 goto out;
170 break;
171 }
172
173 /* This can only be done after all function pointers are setup. */

--- 74 unchanged lines hidden (view full) ---

248 eecd &= ~E1000_EECD_AUPDEN;
249 E1000_WRITE_REG(hw, E1000_EECD, eecd);
250 break;
251 }
252 /* Fall Through */
253 default:
254 nvm->type = e1000_nvm_eeprom_spi;
255 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
256 E1000_EECD_SIZE_EX_SHIFT);
256 E1000_EECD_SIZE_EX_SHIFT);
257 /*
258 * Added to a constant, "size" becomes the left-shift value
259 * for setting word_size.
260 */
261 size += NVM_WORD_SIZE_BASE_SHIFT;
262
263 /* EEPROM access above 16k is unsupported */
264 if (size > 14)
265 size = 14;
257 /*
258 * Added to a constant, "size" becomes the left-shift value
259 * for setting word_size.
260 */
261 size += NVM_WORD_SIZE_BASE_SHIFT;
262
263 /* EEPROM access above 16k is unsupported */
264 if (size > 14)
265 size = 14;
266 nvm->word_size = 1 << size;
266 nvm->word_size = 1 << size;
267 break;
268 }
269
270 /* Function Pointers */
271 switch (hw->mac.type) {
272 case e1000_82574:
273 case e1000_82583:
274 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
275 nvm->ops.release = e1000_put_hw_semaphore_82574;
276 break;
277 default:
278 nvm->ops.acquire = e1000_acquire_nvm_82571;
279 nvm->ops.release = e1000_release_nvm_82571;
280 break;
281 }
267 break;
268 }
269
270 /* Function Pointers */
271 switch (hw->mac.type) {
272 case e1000_82574:
273 case e1000_82583:
274 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
275 nvm->ops.release = e1000_put_hw_semaphore_82574;
276 break;
277 default:
278 nvm->ops.acquire = e1000_acquire_nvm_82571;
279 nvm->ops.release = e1000_release_nvm_82571;
280 break;
281 }
282 nvm->ops.read = e1000_read_nvm_eerd;
283 nvm->ops.update = e1000_update_nvm_checksum_82571;
284 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
282 nvm->ops.read = e1000_read_nvm_eerd;
283 nvm->ops.update = e1000_update_nvm_checksum_82571;
284 nvm->ops.validate = e1000_validate_nvm_checksum_82571;
285 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
285 nvm->ops.valid_led_default = e1000_valid_led_default_82571;
286 nvm->ops.write = e1000_write_nvm_82571;
286 nvm->ops.write = e1000_write_nvm_82571;
287
288 return E1000_SUCCESS;
289}
290
291/**
292 * e1000_init_mac_params_82571 - Init MAC func ptrs.
293 * @hw: pointer to the HW structure
294 **/

--- 63 unchanged lines hidden (view full) ---

358 /* writing VFTA */
359 mac->ops.write_vfta = e1000_write_vfta_generic;
360 /* clearing VFTA */
361 mac->ops.clear_vfta = e1000_clear_vfta_82571;
362 /* read mac address */
363 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
364 /* ID LED init */
365 mac->ops.id_led_init = e1000_id_led_init_generic;
287
288 return E1000_SUCCESS;
289}
290
291/**
292 * e1000_init_mac_params_82571 - Init MAC func ptrs.
293 * @hw: pointer to the HW structure
294 **/

--- 63 unchanged lines hidden (view full) ---

358 /* writing VFTA */
359 mac->ops.write_vfta = e1000_write_vfta_generic;
360 /* clearing VFTA */
361 mac->ops.clear_vfta = e1000_clear_vfta_82571;
362 /* read mac address */
363 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
364 /* ID LED init */
365 mac->ops.id_led_init = e1000_id_led_init_generic;
366 /* blink LED */
367 mac->ops.blink_led = e1000_blink_led_generic;
368 /* setup LED */
369 mac->ops.setup_led = e1000_setup_led_generic;
370 /* cleanup LED */
371 mac->ops.cleanup_led = e1000_cleanup_led_generic;
372 /* turn off LED */
373 mac->ops.led_off = e1000_led_off_generic;
374 /* clear hardware counters */
375 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
376
377 /* MAC-specific function pointers */
378 switch (hw->mac.type) {
379 case e1000_82573:
380 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
381 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
382 mac->ops.led_on = e1000_led_on_generic;
366 /* setup LED */
367 mac->ops.setup_led = e1000_setup_led_generic;
368 /* cleanup LED */
369 mac->ops.cleanup_led = e1000_cleanup_led_generic;
370 /* turn off LED */
371 mac->ops.led_off = e1000_led_off_generic;
372 /* clear hardware counters */
373 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
374
375 /* MAC-specific function pointers */
376 switch (hw->mac.type) {
377 case e1000_82573:
378 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
379 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
380 mac->ops.led_on = e1000_led_on_generic;
381 mac->ops.blink_led = e1000_blink_led_generic;
383
384 /* FWSM register */
385 mac->has_fwsm = TRUE;
386 /*
387 * ARC supported; valid only if manageability features are
388 * enabled.
389 */
382
383 /* FWSM register */
384 mac->has_fwsm = TRUE;
385 /*
386 * ARC supported; valid only if manageability features are
387 * enabled.
388 */
390 mac->arc_subsystem_valid =
391 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
392 ? TRUE : FALSE;
389 mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
390 E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
393 break;
394 case e1000_82574:
395 case e1000_82583:
396 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
397 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
398 mac->ops.led_on = e1000_led_on_82574;
399 break;
400 default:
401 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
402 mac->ops.led_on = e1000_led_on_generic;
391 break;
392 case e1000_82574:
393 case e1000_82583:
394 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
395 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
396 mac->ops.led_on = e1000_led_on_82574;
397 break;
398 default:
399 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
400 mac->ops.led_on = e1000_led_on_generic;
401 mac->ops.blink_led = e1000_blink_led_generic;
403
404 /* FWSM register */
405 mac->has_fwsm = TRUE;
406 break;
407 }
408
409 /*
410 * Ensure that the inter-port SWSM.SMBI lock bit is clear before

--- 4 unchanged lines hidden (view full) ---

415 */
416 switch (hw->mac.type) {
417 case e1000_82571:
418 case e1000_82572:
419 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
420
421 if (!(swsm2 & E1000_SWSM2_LOCK)) {
422 /* Only do this for the first interface on this card */
402
403 /* FWSM register */
404 mac->has_fwsm = TRUE;
405 break;
406 }
407
408 /*
409 * Ensure that the inter-port SWSM.SMBI lock bit is clear before

--- 4 unchanged lines hidden (view full) ---

414 */
415 switch (hw->mac.type) {
416 case e1000_82571:
417 case e1000_82572:
418 swsm2 = E1000_READ_REG(hw, E1000_SWSM2);
419
420 if (!(swsm2 & E1000_SWSM2_LOCK)) {
421 /* Only do this for the first interface on this card */
423 E1000_WRITE_REG(hw, E1000_SWSM2,
424 swsm2 | E1000_SWSM2_LOCK);
422 E1000_WRITE_REG(hw, E1000_SWSM2, swsm2 |
423 E1000_SWSM2_LOCK);
425 force_clear_smbi = TRUE;
426 } else
427 force_clear_smbi = FALSE;
428 break;
429 default:
430 force_clear_smbi = TRUE;
431 break;
432 }

--- 308 unchanged lines hidden (view full) ---

741{
742 u16 data = E1000_READ_REG(hw, E1000_POEMB);
743
744 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
745
746 if (!active) {
747 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
748 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
424 force_clear_smbi = TRUE;
425 } else
426 force_clear_smbi = FALSE;
427 break;
428 default:
429 force_clear_smbi = TRUE;
430 break;
431 }

--- 308 unchanged lines hidden (view full) ---

740{
741 u16 data = E1000_READ_REG(hw, E1000_POEMB);
742
743 DEBUGFUNC("e1000_set_d3_lplu_state_82574");
744
745 if (!active) {
746 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
747 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
749 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
750 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
748 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
749 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
751 data |= E1000_PHY_CTRL_NOND0A_LPLU;
752 }
753
754 E1000_WRITE_REG(hw, E1000_POEMB, data);
755 return E1000_SUCCESS;
756}
757
758/**

--- 52 unchanged lines hidden (view full) ---

811 * @data: 16 bit word(s) to be written to the EEPROM
812 *
813 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
814 *
815 * If e1000_update_nvm_checksum is not called after this function, the
816 * EEPROM will most likely contain an invalid checksum.
817 **/
818static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
750 data |= E1000_PHY_CTRL_NOND0A_LPLU;
751 }
752
753 E1000_WRITE_REG(hw, E1000_POEMB, data);
754 return E1000_SUCCESS;
755}
756
757/**

--- 52 unchanged lines hidden (view full) ---

810 * @data: 16 bit word(s) to be written to the EEPROM
811 *
812 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
813 *
814 * If e1000_update_nvm_checksum is not called after this function, the
815 * EEPROM will most likely contain an invalid checksum.
816 **/
817static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
819 u16 *data)
818 u16 *data)
820{
821 s32 ret_val = E1000_SUCCESS;
822
823 DEBUGFUNC("e1000_write_nvm_82571");
824
825 switch (hw->mac.type) {
826 case e1000_82573:
827 case e1000_82574:

--- 108 unchanged lines hidden (view full) ---

936 * After checking for invalid values, poll the EEPROM to ensure the previous
937 * command has completed before trying to write the next word. After write
938 * poll for completion.
939 *
940 * If e1000_update_nvm_checksum is not called after this function, the
941 * EEPROM will most likely contain an invalid checksum.
942 **/
943static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
819{
820 s32 ret_val = E1000_SUCCESS;
821
822 DEBUGFUNC("e1000_write_nvm_82571");
823
824 switch (hw->mac.type) {
825 case e1000_82573:
826 case e1000_82574:

--- 108 unchanged lines hidden (view full) ---

935 * After checking for invalid values, poll the EEPROM to ensure the previous
936 * command has completed before trying to write the next word. After write
937 * poll for completion.
938 *
939 * If e1000_update_nvm_checksum is not called after this function, the
940 * EEPROM will most likely contain an invalid checksum.
941 **/
942static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
944 u16 words, u16 *data)
943 u16 words, u16 *data)
945{
946 struct e1000_nvm_info *nvm = &hw->nvm;
947 u32 i, eewr = 0;
948 s32 ret_val = 0;
949
950 DEBUGFUNC("e1000_write_nvm_eewr_82571");
951
952 /*

--- 81 unchanged lines hidden (view full) ---

1034
1035 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1036 if (ret_val)
1037 goto out;
1038
1039 if (active) {
1040 data |= IGP02E1000_PM_D0_LPLU;
1041 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
944{
945 struct e1000_nvm_info *nvm = &hw->nvm;
946 u32 i, eewr = 0;
947 s32 ret_val = 0;
948
949 DEBUGFUNC("e1000_write_nvm_eewr_82571");
950
951 /*

--- 81 unchanged lines hidden (view full) ---

1033
1034 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
1035 if (ret_val)
1036 goto out;
1037
1038 if (active) {
1039 data |= IGP02E1000_PM_D0_LPLU;
1040 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1042 data);
1041 data);
1043 if (ret_val)
1044 goto out;
1045
1046 /* When LPLU is enabled, we should disable SmartSpeed */
1047 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1042 if (ret_val)
1043 goto out;
1044
1045 /* When LPLU is enabled, we should disable SmartSpeed */
1046 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1048 &data);
1047 &data);
1049 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1050 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1048 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1049 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1051 data);
1050 data);
1052 if (ret_val)
1053 goto out;
1054 } else {
1055 data &= ~IGP02E1000_PM_D0_LPLU;
1056 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1051 if (ret_val)
1052 goto out;
1053 } else {
1054 data &= ~IGP02E1000_PM_D0_LPLU;
1055 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
1057 data);
1056 data);
1058 /*
1059 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1060 * during Dx states where the power conservation is most
1061 * important. During driver activity we should enable
1062 * SmartSpeed, so performance is maintained.
1063 */
1064 if (phy->smart_speed == e1000_smart_speed_on) {
1065 ret_val = phy->ops.read_reg(hw,
1057 /*
1058 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
1059 * during Dx states where the power conservation is most
1060 * important. During driver activity we should enable
1061 * SmartSpeed, so performance is maintained.
1062 */
1063 if (phy->smart_speed == e1000_smart_speed_on) {
1064 ret_val = phy->ops.read_reg(hw,
1066 IGP01E1000_PHY_PORT_CONFIG,
1067 &data);
1065 IGP01E1000_PHY_PORT_CONFIG,
1066 &data);
1068 if (ret_val)
1069 goto out;
1070
1071 data |= IGP01E1000_PSCFR_SMART_SPEED;
1072 ret_val = phy->ops.write_reg(hw,
1067 if (ret_val)
1068 goto out;
1069
1070 data |= IGP01E1000_PSCFR_SMART_SPEED;
1071 ret_val = phy->ops.write_reg(hw,
1073 IGP01E1000_PHY_PORT_CONFIG,
1074 data);
1072 IGP01E1000_PHY_PORT_CONFIG,
1073 data);
1075 if (ret_val)
1076 goto out;
1077 } else if (phy->smart_speed == e1000_smart_speed_off) {
1078 ret_val = phy->ops.read_reg(hw,
1074 if (ret_val)
1075 goto out;
1076 } else if (phy->smart_speed == e1000_smart_speed_off) {
1077 ret_val = phy->ops.read_reg(hw,
1079 IGP01E1000_PHY_PORT_CONFIG,
1080 &data);
1078 IGP01E1000_PHY_PORT_CONFIG,
1079 &data);
1081 if (ret_val)
1082 goto out;
1083
1084 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1085 ret_val = phy->ops.write_reg(hw,
1080 if (ret_val)
1081 goto out;
1082
1083 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1084 ret_val = phy->ops.write_reg(hw,
1086 IGP01E1000_PHY_PORT_CONFIG,
1087 data);
1085 IGP01E1000_PHY_PORT_CONFIG,
1086 data);
1088 if (ret_val)
1089 goto out;
1090 }
1091 }
1092
1093out:
1094 return ret_val;
1095}

--- 154 unchanged lines hidden (view full) ---

1250 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1251
1252 /* Setup link and flow control */
1253 ret_val = mac->ops.setup_link(hw);
1254
1255 /* Set the transmit descriptor write-back policy */
1256 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1257 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1087 if (ret_val)
1088 goto out;
1089 }
1090 }
1091
1092out:
1093 return ret_val;
1094}

--- 154 unchanged lines hidden (view full) ---

1249 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1250
1251 /* Setup link and flow control */
1252 ret_val = mac->ops.setup_link(hw);
1253
1254 /* Set the transmit descriptor write-back policy */
1255 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1256 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1258 E1000_TXDCTL_FULL_TX_DESC_WB |
1259 E1000_TXDCTL_COUNT_DESC;
1257 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
1260 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1261
1262 /* ...for both queues. */
1263 switch (mac->type) {
1264 case e1000_82573:
1265 e1000_enable_tx_pkt_filtering_generic(hw);
1266 /* fall through */
1267 case e1000_82574:
1268 case e1000_82583:
1269 reg_data = E1000_READ_REG(hw, E1000_GCR);
1270 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1271 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1272 break;
1273 default:
1274 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1275 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1258 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1259
1260 /* ...for both queues. */
1261 switch (mac->type) {
1262 case e1000_82573:
1263 e1000_enable_tx_pkt_filtering_generic(hw);
1264 /* fall through */
1265 case e1000_82574:
1266 case e1000_82583:
1267 reg_data = E1000_READ_REG(hw, E1000_GCR);
1268 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1269 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1270 break;
1271 default:
1272 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1273 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1276 E1000_TXDCTL_FULL_TX_DESC_WB |
1277 E1000_TXDCTL_COUNT_DESC;
1274 E1000_TXDCTL_FULL_TX_DESC_WB |
1275 E1000_TXDCTL_COUNT_DESC;
1278 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1279 break;
1280 }
1281
1282 /*
1283 * Clear all of the statistics registers (clear on read). It is
1284 * important that we do this after we have tried to establish link
1285 * because the symbol error count will increment wildly if there

--- 29 unchanged lines hidden (view full) ---

1315 /* Transmit Arbitration Control 0 */
1316 reg = E1000_READ_REG(hw, E1000_TARC(0));
1317 reg &= ~(0xF << 27); /* 30:27 */
1318 switch (hw->mac.type) {
1319 case e1000_82571:
1320 case e1000_82572:
1321 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1322 break;
1276 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1277 break;
1278 }
1279
1280 /*
1281 * Clear all of the statistics registers (clear on read). It is
1282 * important that we do this after we have tried to establish link
1283 * because the symbol error count will increment wildly if there

--- 29 unchanged lines hidden (view full) ---

1313 /* Transmit Arbitration Control 0 */
1314 reg = E1000_READ_REG(hw, E1000_TARC(0));
1315 reg &= ~(0xF << 27); /* 30:27 */
1316 switch (hw->mac.type) {
1317 case e1000_82571:
1318 case e1000_82572:
1319 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1320 break;
1321 case e1000_82574:
1322 case e1000_82583:
1323 reg |= (1 << 26);
1324 break;
1323 default:
1324 break;
1325 }
1326 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1327
1328 /* Transmit Arbitration Control 1 */
1329 reg = E1000_READ_REG(hw, E1000_TARC(1));
1330 switch (hw->mac.type) {

--- 191 unchanged lines hidden (view full) ---

1522
1523 DEBUGFUNC("e1000_check_phy_82574");
1524
1525 /*
1526 * Read PHY Receive Error counter first, if its is max - all F's then
1527 * read the Base1000T status register If both are max then PHY is hung.
1528 */
1529 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1325 default:
1326 break;
1327 }
1328 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1329
1330 /* Transmit Arbitration Control 1 */
1331 reg = E1000_READ_REG(hw, E1000_TARC(1));
1332 switch (hw->mac.type) {

--- 191 unchanged lines hidden (view full) ---

1524
1525 DEBUGFUNC("e1000_check_phy_82574");
1526
1527 /*
1528 * Read PHY Receive Error counter first, if its is max - all F's then
1529 * read the Base1000T status register If both are max then PHY is hung.
1530 */
1531 ret_val = hw->phy.ops.read_reg(hw, E1000_RECEIVE_ERROR_COUNTER,
1530 &receive_errors);
1532 &receive_errors);
1531 if (ret_val)
1532 goto out;
1533 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1534 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1533 if (ret_val)
1534 goto out;
1535 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1536 ret_val = hw->phy.ops.read_reg(hw, E1000_BASE1000T_STATUS,
1535 &status_1kbt);
1537 &status_1kbt);
1536 if (ret_val)
1537 goto out;
1538 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1539 E1000_IDLE_ERROR_COUNT_MASK)
1540 phy_hung = TRUE;
1541 }
1542out:
1543 return phy_hung;

--- 91 unchanged lines hidden (view full) ---

1635 case e1000_82572:
1636 /*
1637 * If SerDes loopback mode is entered, there is no form
1638 * of reset to take the adapter out of that mode. So we
1639 * have to explicitly take the adapter out of loopback
1640 * mode. This prevents drivers from twiddling their thumbs
1641 * if another tool failed to take it out of loopback mode.
1642 */
1538 if (ret_val)
1539 goto out;
1540 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1541 E1000_IDLE_ERROR_COUNT_MASK)
1542 phy_hung = TRUE;
1543 }
1544out:
1545 return phy_hung;

--- 91 unchanged lines hidden (view full) ---

1637 case e1000_82572:
1638 /*
1639 * If SerDes loopback mode is entered, there is no form
1640 * of reset to take the adapter out of that mode. So we
1641 * have to explicitly take the adapter out of loopback
1642 * mode. This prevents drivers from twiddling their thumbs
1643 * if another tool failed to take it out of loopback mode.
1644 */
1643 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1645 E1000_WRITE_REG(hw, E1000_SCTL,
1646 E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1644 break;
1645 default:
1646 break;
1647 }
1648
1649 return e1000_setup_fiber_serdes_link_generic(hw);
1650}
1651

--- 7 unchanged lines hidden (view full) ---

1659 * determined by the result of autonegotiation. This is the most likely case.
1660 * If autonegotiation is not supported by the link partner, and the link
1661 * has a valid signal, force the link up.
1662 *
1663 * The link state is represented internally here by 4 states:
1664 *
1665 * 1) down
1666 * 2) autoneg_progress
1647 break;
1648 default:
1649 break;
1650 }
1651
1652 return e1000_setup_fiber_serdes_link_generic(hw);
1653}
1654

--- 7 unchanged lines hidden (view full) ---

1662 * determined by the result of autonegotiation. This is the most likely case.
1663 * If autonegotiation is not supported by the link partner, and the link
1664 * has a valid signal, force the link up.
1665 *
1666 * The link state is represented internally here by 4 states:
1667 *
1668 * 1) down
1669 * 2) autoneg_progress
1667 * 3) autoneg_complete (the link sucessfully autonegotiated)
1670 * 3) autoneg_complete (the link successfully autonegotiated)
1668 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1669 *
1670 **/
1671static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1672{
1673 struct e1000_mac_info *mac = &hw->mac;
1674 u32 rxcw;
1675 u32 ctrl;

--- 82 unchanged lines hidden (view full) ---

1758 /* Configure Flow Control after link up. */
1759 ret_val =
1760 e1000_config_fc_after_link_up_generic(hw);
1761 if (ret_val) {
1762 DEBUGOUT("Error config flow control\n");
1763 break;
1764 }
1765 mac->serdes_link_state =
1671 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1672 *
1673 **/
1674static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1675{
1676 struct e1000_mac_info *mac = &hw->mac;
1677 u32 rxcw;
1678 u32 ctrl;

--- 82 unchanged lines hidden (view full) ---

1761 /* Configure Flow Control after link up. */
1762 ret_val =
1763 e1000_config_fc_after_link_up_generic(hw);
1764 if (ret_val) {
1765 DEBUGOUT("Error config flow control\n");
1766 break;
1767 }
1768 mac->serdes_link_state =
1766 e1000_serdes_link_forced_up;
1769 e1000_serdes_link_forced_up;
1767 mac->serdes_has_link = TRUE;
1768 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1769 }
1770 break;
1771
1772 case e1000_serdes_link_down:
1773 default:
1774 /*
1775 * The link was down but the receiver has now gained
1776 * valid sync, so lets see if we can bring the link
1777 * up.
1778 */
1779 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1770 mac->serdes_has_link = TRUE;
1771 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1772 }
1773 break;
1774
1775 case e1000_serdes_link_down:
1776 default:
1777 /*
1778 * The link was down but the receiver has now gained
1779 * valid sync, so lets see if we can bring the link
1780 * up.
1781 */
1782 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1780 E1000_WRITE_REG(hw, E1000_CTRL,
1781 (ctrl & ~E1000_CTRL_SLU));
1783 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl &
1784 ~E1000_CTRL_SLU));
1782 mac->serdes_link_state =
1785 mac->serdes_link_state =
1783 e1000_serdes_link_autoneg_progress;
1786 e1000_serdes_link_autoneg_progress;
1784 mac->serdes_has_link = FALSE;
1785 DEBUGOUT("DOWN -> AN_PROG\n");
1786 break;
1787 }
1788 } else {
1789 if (!(rxcw & E1000_RXCW_SYNCH)) {
1790 mac->serdes_has_link = FALSE;
1791 mac->serdes_link_state = e1000_serdes_link_down;

--- 7 unchanged lines hidden (view full) ---

1799 for (i = 0; i < AN_RETRY_COUNT; i++) {
1800 usec_delay(10);
1801 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1802 if ((rxcw & E1000_RXCW_IV) &&
1803 !((rxcw & E1000_RXCW_SYNCH) &&
1804 (rxcw & E1000_RXCW_C))) {
1805 mac->serdes_has_link = FALSE;
1806 mac->serdes_link_state =
1787 mac->serdes_has_link = FALSE;
1788 DEBUGOUT("DOWN -> AN_PROG\n");
1789 break;
1790 }
1791 } else {
1792 if (!(rxcw & E1000_RXCW_SYNCH)) {
1793 mac->serdes_has_link = FALSE;
1794 mac->serdes_link_state = e1000_serdes_link_down;

--- 7 unchanged lines hidden (view full) ---

1802 for (i = 0; i < AN_RETRY_COUNT; i++) {
1803 usec_delay(10);
1804 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1805 if ((rxcw & E1000_RXCW_IV) &&
1806 !((rxcw & E1000_RXCW_SYNCH) &&
1807 (rxcw & E1000_RXCW_C))) {
1808 mac->serdes_has_link = FALSE;
1809 mac->serdes_link_state =
1807 e1000_serdes_link_down;
1810 e1000_serdes_link_down;
1808 DEBUGOUT("ANYSTATE -> DOWN\n");
1809 break;
1810 }
1811 }
1812
1813 if (i == AN_RETRY_COUNT) {
1814 txcw = E1000_READ_REG(hw, E1000_TXCW);
1815 txcw |= E1000_TXCW_ANE;
1816 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1817 mac->serdes_link_state =
1811 DEBUGOUT("ANYSTATE -> DOWN\n");
1812 break;
1813 }
1814 }
1815
1816 if (i == AN_RETRY_COUNT) {
1817 txcw = E1000_READ_REG(hw, E1000_TXCW);
1818 txcw |= E1000_TXCW_ANE;
1819 E1000_WRITE_REG(hw, E1000_TXCW, txcw);
1820 mac->serdes_link_state =
1818 e1000_serdes_link_autoneg_progress;
1821 e1000_serdes_link_autoneg_progress;
1819 mac->serdes_has_link = FALSE;
1820 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1821 }
1822 }
1823 }
1824
1825 return ret_val;
1826}

--- 73 unchanged lines hidden (view full) ---

1900 /*
1901 * Hold a copy of the LAA in RAR[14] This is done so that
1902 * between the time RAR[0] gets clobbered and the time it
1903 * gets fixed, the actual LAA is in one of the RARs and no
1904 * incoming packets directed to this port are dropped.
1905 * Eventually the LAA will be in RAR[0] and RAR[14].
1906 */
1907 e1000_rar_set_generic(hw, hw->mac.addr,
1822 mac->serdes_has_link = FALSE;
1823 DEBUGOUT("ANYSTATE -> AN_PROG\n");
1824 }
1825 }
1826 }
1827
1828 return ret_val;
1829}

--- 73 unchanged lines hidden (view full) ---

1903 /*
1904 * Hold a copy of the LAA in RAR[14] This is done so that
1905 * between the time RAR[0] gets clobbered and the time it
1906 * gets fixed, the actual LAA is in one of the RARs and no
1907 * incoming packets directed to this port are dropped.
1908 * Eventually the LAA will be in RAR[0] and RAR[14].
1909 */
1910 e1000_rar_set_generic(hw, hw->mac.addr,
1908 hw->mac.rar_entry_count - 1);
1911 hw->mac.rar_entry_count - 1);
1909 return;
1910}
1911
1912/**
1913 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1914 * @hw: pointer to the HW structure
1915 *
1916 * Verifies that the EEPROM has completed the update. After updating the

--- 147 unchanged lines hidden --- 		1912 return;
1913}
1914
1915/**
1916 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1917 * @hw: pointer to the HW structure
1918 *
1919 * Verifies that the EEPROM has completed the update. After updating the

--- 147 unchanged lines hidden ---