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e1000_82571.c (194865) e1000_82571.c (200243)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 194865 2009-06-24 17:41:29Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82571.c 200243 2009-12-08 01:07:44Z jfv $*/
34
35/*
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * 82572EI Gigabit Ethernet Controller (Copper)
43 * 82572EI Gigabit Ethernet Controller (Fiber)
44 * 82572EI Gigabit Ethernet Controller
45 * 82573V Gigabit Ethernet Controller (Copper)
46 * 82573E Gigabit Ethernet Controller (Copper)
47 * 82573L Gigabit Ethernet Controller
48 * 82574L Gigabit Network Connection
34
35/*
36 * 82571EB Gigabit Ethernet Controller
37 * 82571EB Gigabit Ethernet Controller (Copper)
38 * 82571EB Gigabit Ethernet Controller (Fiber)
39 * 82571EB Dual Port Gigabit Mezzanine Adapter
40 * 82571EB Quad Port Gigabit Mezzanine Adapter
41 * 82571PT Gigabit PT Quad Port Server ExpressModule
42 * 82572EI Gigabit Ethernet Controller (Copper)
43 * 82572EI Gigabit Ethernet Controller (Fiber)
44 * 82572EI Gigabit Ethernet Controller
45 * 82573V Gigabit Ethernet Controller (Copper)
46 * 82573E Gigabit Ethernet Controller (Copper)
47 * 82573L Gigabit Ethernet Controller
48 * 82574L Gigabit Network Connection
49 * 82574L Gigabit Network Connection
50 * 82583V Gigabit Network Connection
51 */
52
53#include "e1000_api.h"
54
55static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
56static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
57static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);

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101 goto out;
102 }
103
104 phy->addr = 1;
105 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
106 phy->reset_delay_us = 100;
107
108 phy->ops.acquire = e1000_get_hw_semaphore_82571;
49 * 82583V Gigabit Network Connection
50 */
51
52#include "e1000_api.h"
53
54static s32 e1000_init_phy_params_82571(struct e1000_hw *hw);
55static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw);
56static s32 e1000_init_mac_params_82571(struct e1000_hw *hw);

--- 43 unchanged lines hidden (view full) ---

100 goto out;
101 }
102
103 phy->addr = 1;
104 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
105 phy->reset_delay_us = 100;
106
107 phy->ops.acquire = e1000_get_hw_semaphore_82571;
109 phy->ops.check_polarity = e1000_check_polarity_igp;
110 phy->ops.check_reset_block = e1000_check_reset_block_generic;
111 phy->ops.release = e1000_put_hw_semaphore_82571;
112 phy->ops.reset = e1000_phy_hw_reset_generic;
113 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
114 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
115 phy->ops.power_up = e1000_power_up_phy_copper;
116 phy->ops.power_down = e1000_power_down_phy_copper_82571;
117
118 switch (hw->mac.type) {
119 case e1000_82571:
120 case e1000_82572:
121 phy->type = e1000_phy_igp_2;
122 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
123 phy->ops.get_info = e1000_get_phy_info_igp;
108 phy->ops.check_reset_block = e1000_check_reset_block_generic;
109 phy->ops.release = e1000_put_hw_semaphore_82571;
110 phy->ops.reset = e1000_phy_hw_reset_generic;
111 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82571;
112 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
113 phy->ops.power_up = e1000_power_up_phy_copper;
114 phy->ops.power_down = e1000_power_down_phy_copper_82571;
115
116 switch (hw->mac.type) {
117 case e1000_82571:
118 case e1000_82572:
119 phy->type = e1000_phy_igp_2;
120 phy->ops.get_cfg_done = e1000_get_cfg_done_82571;
121 phy->ops.get_info = e1000_get_phy_info_igp;
122 phy->ops.check_polarity = e1000_check_polarity_igp;
124 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
125 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
126 phy->ops.read_reg = e1000_read_phy_reg_igp;
127 phy->ops.write_reg = e1000_write_phy_reg_igp;
128
129 /* This uses above function pointers */
130 ret_val = e1000_get_phy_id_82571(hw);
131
132 /* Verify PHY ID */
133 if (phy->id != IGP01E1000_I_PHY_ID) {
134 ret_val = -E1000_ERR_PHY;
123 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
124 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
125 phy->ops.read_reg = e1000_read_phy_reg_igp;
126 phy->ops.write_reg = e1000_write_phy_reg_igp;
127
128 /* This uses above function pointers */
129 ret_val = e1000_get_phy_id_82571(hw);
130
131 /* Verify PHY ID */
132 if (phy->id != IGP01E1000_I_PHY_ID) {
133 ret_val = -E1000_ERR_PHY;
134 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
135 goto out;
136 }
137 break;
138 case e1000_82573:
139 phy->type = e1000_phy_m88;
140 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
141 phy->ops.get_info = e1000_get_phy_info_m88;
135 goto out;
136 }
137 break;
138 case e1000_82573:
139 phy->type = e1000_phy_m88;
140 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
141 phy->ops.get_info = e1000_get_phy_info_m88;
142 phy->ops.check_polarity = e1000_check_polarity_m88;
142 phy->ops.commit = e1000_phy_sw_reset_generic;
143 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
144 phy->ops.get_cable_length = e1000_get_cable_length_m88;
145 phy->ops.read_reg = e1000_read_phy_reg_m88;
146 phy->ops.write_reg = e1000_write_phy_reg_m88;
147
148 /* This uses above function pointers */
149 ret_val = e1000_get_phy_id_82571(hw);
150
151 /* Verify PHY ID */
152 if (phy->id != M88E1111_I_PHY_ID) {
153 ret_val = -E1000_ERR_PHY;
154 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
155 goto out;
156 }
157 break;
143 phy->ops.commit = e1000_phy_sw_reset_generic;
144 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
145 phy->ops.get_cable_length = e1000_get_cable_length_m88;
146 phy->ops.read_reg = e1000_read_phy_reg_m88;
147 phy->ops.write_reg = e1000_write_phy_reg_m88;
148
149 /* This uses above function pointers */
150 ret_val = e1000_get_phy_id_82571(hw);
151
152 /* Verify PHY ID */
153 if (phy->id != M88E1111_I_PHY_ID) {
154 ret_val = -E1000_ERR_PHY;
155 DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
156 goto out;
157 }
158 break;
158 case e1000_82583:
159 case e1000_82574:
159 case e1000_82574:
160 case e1000_82583:
160 phy->type = e1000_phy_bm;
161 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
162 phy->ops.get_info = e1000_get_phy_info_m88;
161 phy->type = e1000_phy_bm;
162 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
163 phy->ops.get_info = e1000_get_phy_info_m88;
164 phy->ops.check_polarity = e1000_check_polarity_m88;
163 phy->ops.commit = e1000_phy_sw_reset_generic;
164 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
165 phy->ops.get_cable_length = e1000_get_cable_length_m88;
166 phy->ops.read_reg = e1000_read_phy_reg_bm2;
167 phy->ops.write_reg = e1000_write_phy_reg_bm2;
168
169 /* This uses above function pointers */
170 ret_val = e1000_get_phy_id_82571(hw);

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261
262/**
263 * e1000_init_mac_params_82571 - Init MAC func ptrs.
264 * @hw: pointer to the HW structure
265 **/
266static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
267{
268 struct e1000_mac_info *mac = &hw->mac;
165 phy->ops.commit = e1000_phy_sw_reset_generic;
166 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
167 phy->ops.get_cable_length = e1000_get_cable_length_m88;
168 phy->ops.read_reg = e1000_read_phy_reg_bm2;
169 phy->ops.write_reg = e1000_write_phy_reg_bm2;
170
171 /* This uses above function pointers */
172 ret_val = e1000_get_phy_id_82571(hw);

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263
264/**
265 * e1000_init_mac_params_82571 - Init MAC func ptrs.
266 * @hw: pointer to the HW structure
267 **/
268static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
269{
270 struct e1000_mac_info *mac = &hw->mac;
269 s32 ret_val = E1000_SUCCESS;
270 u32 swsm = 0;
271 u32 swsm2 = 0;
272 bool force_clear_smbi = FALSE;
273
274 DEBUGFUNC("e1000_init_mac_params_82571");
275
271 u32 swsm = 0;
272 u32 swsm2 = 0;
273 bool force_clear_smbi = FALSE;
274
275 DEBUGFUNC("e1000_init_mac_params_82571");
276
276 /* Set media type */
277 /* Set media type and media-dependent function pointers */
277 switch (hw->device_id) {
278 case E1000_DEV_ID_82571EB_FIBER:
279 case E1000_DEV_ID_82572EI_FIBER:
280 case E1000_DEV_ID_82571EB_QUAD_FIBER:
281 hw->phy.media_type = e1000_media_type_fiber;
278 switch (hw->device_id) {
279 case E1000_DEV_ID_82571EB_FIBER:
280 case E1000_DEV_ID_82572EI_FIBER:
281 case E1000_DEV_ID_82571EB_QUAD_FIBER:
282 hw->phy.media_type = e1000_media_type_fiber;
283 mac->ops.setup_physical_interface =
284 e1000_setup_fiber_serdes_link_82571;
285 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
286 mac->ops.get_link_up_info =
287 e1000_get_speed_and_duplex_fiber_serdes_generic;
282 break;
283 case E1000_DEV_ID_82571EB_SERDES:
284 case E1000_DEV_ID_82571EB_SERDES_DUAL:
285 case E1000_DEV_ID_82571EB_SERDES_QUAD:
286 case E1000_DEV_ID_82572EI_SERDES:
287 hw->phy.media_type = e1000_media_type_internal_serdes;
288 break;
289 case E1000_DEV_ID_82571EB_SERDES:
290 case E1000_DEV_ID_82571EB_SERDES_DUAL:
291 case E1000_DEV_ID_82571EB_SERDES_QUAD:
292 case E1000_DEV_ID_82572EI_SERDES:
293 hw->phy.media_type = e1000_media_type_internal_serdes;
294 mac->ops.setup_physical_interface =
295 e1000_setup_fiber_serdes_link_82571;
296 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
297 mac->ops.get_link_up_info =
298 e1000_get_speed_and_duplex_fiber_serdes_generic;
288 break;
289 default:
290 hw->phy.media_type = e1000_media_type_copper;
299 break;
300 default:
301 hw->phy.media_type = e1000_media_type_copper;
302 mac->ops.setup_physical_interface =
303 e1000_setup_copper_link_82571;
304 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
305 mac->ops.get_link_up_info =
306 e1000_get_speed_and_duplex_copper_generic;
291 break;
292 }
293
294 /* Set mta register count */
295 mac->mta_reg_count = 128;
296 /* Set rar entry count */
297 mac->rar_entry_count = E1000_RAR_ENTRIES;
298 /* Set if part includes ASF firmware */
299 mac->asf_firmware_present = TRUE;
300 /* Set if manageability features are enabled. */
301 mac->arc_subsystem_valid =
302 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
303 ? TRUE : FALSE;
307 break;
308 }
309
310 /* Set mta register count */
311 mac->mta_reg_count = 128;
312 /* Set rar entry count */
313 mac->rar_entry_count = E1000_RAR_ENTRIES;
314 /* Set if part includes ASF firmware */
315 mac->asf_firmware_present = TRUE;
316 /* Set if manageability features are enabled. */
317 mac->arc_subsystem_valid =
318 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
319 ? TRUE : FALSE;
320 /* Adaptive IFS supported */
321 mac->adaptive_ifs = TRUE;
304
305 /* Function pointers */
306
307 /* bus type/speed/width */
308 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
322
323 /* Function pointers */
324
325 /* bus type/speed/width */
326 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
309 /* function id */
310 switch (hw->mac.type) {
311 case e1000_82573:
312 case e1000_82574:
313 case e1000_82583:
314 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
315 break;
316 default:
317 break;
318 }
319 /* reset */
320 mac->ops.reset_hw = e1000_reset_hw_82571;
321 /* hw initialization */
322 mac->ops.init_hw = e1000_init_hw_82571;
323 /* link setup */
324 mac->ops.setup_link = e1000_setup_link_82571;
327 /* reset */
328 mac->ops.reset_hw = e1000_reset_hw_82571;
329 /* hw initialization */
330 mac->ops.init_hw = e1000_init_hw_82571;
331 /* link setup */
332 mac->ops.setup_link = e1000_setup_link_82571;
325 /* physical interface link setup */
326 mac->ops.setup_physical_interface =
327 (hw->phy.media_type == e1000_media_type_copper)
328 ? e1000_setup_copper_link_82571
329 : e1000_setup_fiber_serdes_link_82571;
330 /* check for link */
331 switch (hw->phy.media_type) {
332 case e1000_media_type_copper:
333 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
334 break;
335 case e1000_media_type_fiber:
336 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
337 break;
338 case e1000_media_type_internal_serdes:
339 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
340 break;
341 default:
342 ret_val = -E1000_ERR_CONFIG;
343 goto out;
344 break;
345 }
346 /* check management mode */
347 switch (hw->mac.type) {
348 case e1000_82574:
349 case e1000_82583:
350 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
351 break;
352 default:
353 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
354 break;
355 }
356 /* multicast address update */
357 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
358 /* writing VFTA */
359 mac->ops.write_vfta = e1000_write_vfta_generic;
360 /* clearing VFTA */
361 mac->ops.clear_vfta = e1000_clear_vfta_82571;
362 /* setting MTA */
363 mac->ops.mta_set = e1000_mta_set_generic;
364 /* read mac address */
365 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
366 /* ID LED init */
367 mac->ops.id_led_init = e1000_id_led_init_generic;
368 /* blink LED */
369 mac->ops.blink_led = e1000_blink_led_generic;
370 /* setup LED */
371 mac->ops.setup_led = e1000_setup_led_generic;
372 /* cleanup LED */
373 mac->ops.cleanup_led = e1000_cleanup_led_generic;
333 /* multicast address update */
334 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
335 /* writing VFTA */
336 mac->ops.write_vfta = e1000_write_vfta_generic;
337 /* clearing VFTA */
338 mac->ops.clear_vfta = e1000_clear_vfta_82571;
339 /* setting MTA */
340 mac->ops.mta_set = e1000_mta_set_generic;
341 /* read mac address */
342 mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
343 /* ID LED init */
344 mac->ops.id_led_init = e1000_id_led_init_generic;
345 /* blink LED */
346 mac->ops.blink_led = e1000_blink_led_generic;
347 /* setup LED */
348 mac->ops.setup_led = e1000_setup_led_generic;
349 /* cleanup LED */
350 mac->ops.cleanup_led = e1000_cleanup_led_generic;
374 /* turn on/off LED */
351 /* turn off LED */
352 mac->ops.led_off = e1000_led_off_generic;
353 /* clear hardware counters */
354 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
355
356 /* MAC-specific function pointers */
375 switch (hw->mac.type) {
357 switch (hw->mac.type) {
358 case e1000_82573:
359 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
360 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
361 mac->ops.led_on = e1000_led_on_generic;
362 break;
376 case e1000_82574:
377 case e1000_82583:
363 case e1000_82574:
364 case e1000_82583:
365 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
366 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
378 mac->ops.led_on = e1000_led_on_82574;
379 break;
380 default:
367 mac->ops.led_on = e1000_led_on_82574;
368 break;
369 default:
370 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
381 mac->ops.led_on = e1000_led_on_generic;
382 break;
383 }
371 mac->ops.led_on = e1000_led_on_generic;
372 break;
373 }
384 mac->ops.led_off = e1000_led_off_generic;
385 /* clear hardware counters */
386 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
387 /* link info */
388 mac->ops.get_link_up_info =
389 (hw->phy.media_type == e1000_media_type_copper)
390 ? e1000_get_speed_and_duplex_copper_generic
391 : e1000_get_speed_and_duplex_fiber_serdes_generic;
392
393 /*
394 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
395 * first NVM or PHY acess. This should be done for single-port
396 * devices, and for one port only on dual-port devices so that
397 * for those devices we can still use the SMBI lock to synchronize
398 * inter-port accesses to the PHY & NVM.
399 */

--- 29 unchanged lines hidden (view full) ---

429 }
430
431 /*
432 * Initialze device specific counter of SMBI acquisition
433 * timeouts.
434 */
435 hw->dev_spec._82571.smb_counter = 0;
436
374
375 /*
376 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
377 * first NVM or PHY acess. This should be done for single-port
378 * devices, and for one port only on dual-port devices so that
379 * for those devices we can still use the SMBI lock to synchronize
380 * inter-port accesses to the PHY & NVM.
381 */

--- 29 unchanged lines hidden (view full) ---

411 }
412
413 /*
414 * Initialze device specific counter of SMBI acquisition
415 * timeouts.
416 */
417 hw->dev_spec._82571.smb_counter = 0;
418
437out:
438 return ret_val;
419 return E1000_SUCCESS;
439}
440
441/**
442 * e1000_init_function_pointers_82571 - Init func ptrs.
443 * @hw: pointer to the HW structure
444 *
445 * Called to initialize all function pointers and parameters.
446 **/

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496
497 phy->id |= (u32)(phy_id);
498 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
499 break;
500 default:
501 ret_val = -E1000_ERR_PHY;
502 break;
503 }
420}
421
422/**
423 * e1000_init_function_pointers_82571 - Init func ptrs.
424 * @hw: pointer to the HW structure
425 *
426 * Called to initialize all function pointers and parameters.
427 **/

--- 49 unchanged lines hidden (view full) ---

477
478 phy->id |= (u32)(phy_id);
479 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
480 break;
481 default:
482 ret_val = -E1000_ERR_PHY;
483 break;
484 }
504
505out:
506 return ret_val;
507}
508
509/**
510 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
511 * @hw: pointer to the HW structure
512 *
513 * Acquire the HW semaphore to access the PHY or NVM
514 **/
485out:
486 return ret_val;
487}
488
489/**
490 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
491 * @hw: pointer to the HW structure
492 *
493 * Acquire the HW semaphore to access the PHY or NVM
494 **/
515s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
495static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
516{
517 u32 swsm;
518 s32 ret_val = E1000_SUCCESS;
519 s32 sw_timeout = hw->nvm.word_size + 1;
520 s32 fw_timeout = hw->nvm.word_size + 1;
521 s32 i = 0;
522
523 DEBUGFUNC("e1000_get_hw_semaphore_82571");

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572}
573
574/**
575 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
576 * @hw: pointer to the HW structure
577 *
578 * Release hardware semaphore used to access the PHY or NVM
579 **/
496{
497 u32 swsm;
498 s32 ret_val = E1000_SUCCESS;
499 s32 sw_timeout = hw->nvm.word_size + 1;
500 s32 fw_timeout = hw->nvm.word_size + 1;
501 s32 i = 0;
502
503 DEBUGFUNC("e1000_get_hw_semaphore_82571");

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552}
553
554/**
555 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
556 * @hw: pointer to the HW structure
557 *
558 * Release hardware semaphore used to access the PHY or NVM
559 **/
580void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
560static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
581{
582 u32 swsm;
583
584 DEBUGFUNC("e1000_put_hw_semaphore_generic");
585
586 swsm = E1000_READ_REG(hw, E1000_SWSM);
587
588 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

--- 16 unchanged lines hidden (view full) ---

605
606 DEBUGFUNC("e1000_acquire_nvm_82571");
607
608 ret_val = e1000_get_hw_semaphore_82571(hw);
609 if (ret_val)
610 goto out;
611
612 switch (hw->mac.type) {
561{
562 u32 swsm;
563
564 DEBUGFUNC("e1000_put_hw_semaphore_generic");
565
566 swsm = E1000_READ_REG(hw, E1000_SWSM);
567
568 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);

--- 16 unchanged lines hidden (view full) ---

585
586 DEBUGFUNC("e1000_acquire_nvm_82571");
587
588 ret_val = e1000_get_hw_semaphore_82571(hw);
589 if (ret_val)
590 goto out;
591
592 switch (hw->mac.type) {
593 case e1000_82573:
613 case e1000_82574:
614 case e1000_82583:
594 case e1000_82574:
595 case e1000_82583:
615 case e1000_82573:
616 break;
617 default:
618 ret_val = e1000_acquire_nvm_generic(hw);
619 break;
620 }
621
622 if (ret_val)
623 e1000_put_hw_semaphore_82571(hw);

--- 202 unchanged lines hidden (view full) ---

826static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
827{
828 s32 timeout = PHY_CFG_TIMEOUT;
829 s32 ret_val = E1000_SUCCESS;
830
831 DEBUGFUNC("e1000_get_cfg_done_82571");
832
833 while (timeout) {
596 break;
597 default:
598 ret_val = e1000_acquire_nvm_generic(hw);
599 break;
600 }
601
602 if (ret_val)
603 e1000_put_hw_semaphore_82571(hw);

--- 202 unchanged lines hidden (view full) ---

806static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
807{
808 s32 timeout = PHY_CFG_TIMEOUT;
809 s32 ret_val = E1000_SUCCESS;
810
811 DEBUGFUNC("e1000_get_cfg_done_82571");
812
813 while (timeout) {
834 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
814 if (E1000_READ_REG(hw, E1000_EEMNGCTL) &
815 E1000_NVM_CFG_DONE_PORT_0)
835 break;
836 msec_delay(1);
837 timeout--;
838 }
839 if (!timeout) {
840 DEBUGOUT("MNG configuration cycle has not completed.\n");
841 ret_val = -E1000_ERR_RESET;
842 goto out;

--- 118 unchanged lines hidden (view full) ---

961
962 msec_delay(10);
963
964 /*
965 * Must acquire the MDIO ownership before MAC reset.
966 * Ownership defaults to firmware after a reset.
967 */
968 switch (hw->mac.type) {
816 break;
817 msec_delay(1);
818 timeout--;
819 }
820 if (!timeout) {
821 DEBUGOUT("MNG configuration cycle has not completed.\n");
822 ret_val = -E1000_ERR_RESET;
823 goto out;

--- 118 unchanged lines hidden (view full) ---

942
943 msec_delay(10);
944
945 /*
946 * Must acquire the MDIO ownership before MAC reset.
947 * Ownership defaults to firmware after a reset.
948 */
949 switch (hw->mac.type) {
950 case e1000_82573:
969 case e1000_82574:
970 case e1000_82583:
951 case e1000_82574:
952 case e1000_82583:
971 case e1000_82573:
972 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
973 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
974
975 do {
976 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
977 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
978
979 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

--- 29 unchanged lines hidden (view full) ---

1009
1010 /*
1011 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
1012 * Need to wait for Phy configuration completion before accessing
1013 * NVM and Phy.
1014 */
1015
1016 switch (hw->mac.type) {
953 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
954 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
955
956 do {
957 E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
958 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
959
960 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)

--- 29 unchanged lines hidden (view full) ---

990
991 /*
992 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
993 * Need to wait for Phy configuration completion before accessing
994 * NVM and Phy.
995 */
996
997 switch (hw->mac.type) {
998 case e1000_82573:
1017 case e1000_82574:
1018 case e1000_82583:
999 case e1000_82574:
1000 case e1000_82583:
1019 case e1000_82573:
1020 msec_delay(25);
1021 break;
1022 default:
1023 break;
1024 }
1025
1026 /* Clear any pending interrupt events. */
1027 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);

--- 28 unchanged lines hidden (view full) ---

1056 u16 i, rar_count = mac->rar_entry_count;
1057
1058 DEBUGFUNC("e1000_init_hw_82571");
1059
1060 e1000_initialize_hw_bits_82571(hw);
1061
1062 /* Initialize identification LED */
1063 ret_val = mac->ops.id_led_init(hw);
1001 msec_delay(25);
1002 break;
1003 default:
1004 break;
1005 }
1006
1007 /* Clear any pending interrupt events. */
1008 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);

--- 28 unchanged lines hidden (view full) ---

1037 u16 i, rar_count = mac->rar_entry_count;
1038
1039 DEBUGFUNC("e1000_init_hw_82571");
1040
1041 e1000_initialize_hw_bits_82571(hw);
1042
1043 /* Initialize identification LED */
1044 ret_val = mac->ops.id_led_init(hw);
1064 if (ret_val) {
1045 if (ret_val)
1065 DEBUGOUT("Error initializing identification LED\n");
1066 /* This is not fatal and we should not stop init due to this */
1046 DEBUGOUT("Error initializing identification LED\n");
1047 /* This is not fatal and we should not stop init due to this */
1067 }
1068
1069 /* Disabling VLAN filtering */
1070 DEBUGOUT("Initializing the IEEE VLAN\n");
1071 mac->ops.clear_vfta(hw);
1072
1073 /* Setup the receive address. */
1074 /*
1075 * If, however, a locally administered address was assigned to the

--- 16 unchanged lines hidden (view full) ---

1092 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1093 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1094 E1000_TXDCTL_FULL_TX_DESC_WB |
1095 E1000_TXDCTL_COUNT_DESC;
1096 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1097
1098 /* ...for both queues. */
1099 switch (mac->type) {
1048
1049 /* Disabling VLAN filtering */
1050 DEBUGOUT("Initializing the IEEE VLAN\n");
1051 mac->ops.clear_vfta(hw);
1052
1053 /* Setup the receive address. */
1054 /*
1055 * If, however, a locally administered address was assigned to the

--- 16 unchanged lines hidden (view full) ---

1072 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
1073 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1074 E1000_TXDCTL_FULL_TX_DESC_WB |
1075 E1000_TXDCTL_COUNT_DESC;
1076 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
1077
1078 /* ...for both queues. */
1079 switch (mac->type) {
1080 case e1000_82573:
1100 case e1000_82574:
1101 case e1000_82583:
1081 case e1000_82574:
1082 case e1000_82583:
1102 case e1000_82573:
1103 e1000_enable_tx_pkt_filtering_generic(hw);
1104 reg_data = E1000_READ_REG(hw, E1000_GCR);
1105 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1106 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1107 break;
1108 default:
1109 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1110 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1083 e1000_enable_tx_pkt_filtering_generic(hw);
1084 reg_data = E1000_READ_REG(hw, E1000_GCR);
1085 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1086 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
1087 break;
1088 default:
1089 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
1090 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1111 E1000_TXDCTL_FULL_TX_DESC_WB |
1112 E1000_TXDCTL_COUNT_DESC;
1091 E1000_TXDCTL_FULL_TX_DESC_WB |
1092 E1000_TXDCTL_COUNT_DESC;
1113 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1114 break;
1115 }
1116
1117 /*
1118 * Clear all of the statistics registers (clear on read). It is
1119 * important that we do this after we have tried to establish link
1120 * because the symbol error count will increment wildly if there

--- 52 unchanged lines hidden (view full) ---

1173 reg |= (1 << 28);
1174 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1175 break;
1176 default:
1177 break;
1178 }
1179
1180 /* Device Control */
1093 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
1094 break;
1095 }
1096
1097 /*
1098 * Clear all of the statistics registers (clear on read). It is
1099 * important that we do this after we have tried to establish link
1100 * because the symbol error count will increment wildly if there

--- 52 unchanged lines hidden (view full) ---

1153 reg |= (1 << 28);
1154 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1155 break;
1156 default:
1157 break;
1158 }
1159
1160 /* Device Control */
1181
1182 switch (hw->mac.type) {
1161 switch (hw->mac.type) {
1162 case e1000_82573:
1183 case e1000_82574:
1184 case e1000_82583:
1163 case e1000_82574:
1164 case e1000_82583:
1185 case e1000_82573:
1186 reg = E1000_READ_REG(hw, E1000_CTRL);
1187 reg &= ~(1 << 29);
1188 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1189 break;
1190 default:
1191 break;
1192 }
1193
1194 /* Extended Device Control */
1195 switch (hw->mac.type) {
1165 reg = E1000_READ_REG(hw, E1000_CTRL);
1166 reg &= ~(1 << 29);
1167 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1168 break;
1169 default:
1170 break;
1171 }
1172
1173 /* Extended Device Control */
1174 switch (hw->mac.type) {
1175 case e1000_82573:
1196 case e1000_82574:
1197 case e1000_82583:
1176 case e1000_82574:
1177 case e1000_82583:
1198 case e1000_82573:
1199 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1200 reg &= ~(1 << 23);
1201 reg |= (1 << 22);
1202 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1203 break;
1204 default:
1205 break;
1206 }
1207
1178 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1179 reg &= ~(1 << 23);
1180 reg |= (1 << 22);
1181 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1182 break;
1183 default:
1184 break;
1185 }
1186
1208
1209 if (hw->mac.type == e1000_82571) {
1210 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1211 reg |= E1000_PBA_ECC_CORR_EN;
1212 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1213 }
1214
1215 /*
1216 * Workaround for hardware errata.
1217 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1218 */
1187 if (hw->mac.type == e1000_82571) {
1188 reg = E1000_READ_REG(hw, E1000_PBA_ECC);
1189 reg |= E1000_PBA_ECC_CORR_EN;
1190 E1000_WRITE_REG(hw, E1000_PBA_ECC, reg);
1191 }
1192
1193 /*
1194 * Workaround for hardware errata.
1195 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1196 */
1219
1220 if ((hw->mac.type == e1000_82571) ||
1221 (hw->mac.type == e1000_82572)) {
1222 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1223 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1224 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1225 }
1226
1227 /* PCI-Ex Control Registers */
1197 if ((hw->mac.type == e1000_82571) ||
1198 (hw->mac.type == e1000_82572)) {
1199 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1200 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1201 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1202 }
1203
1204 /* PCI-Ex Control Registers */
1228
1229 switch (hw->mac.type) {
1230 case e1000_82574:
1231 case e1000_82583:
1232 reg = E1000_READ_REG(hw, E1000_GCR);
1233 reg |= (1 << 22);
1234 E1000_WRITE_REG(hw, E1000_GCR, reg);
1205 switch (hw->mac.type) {
1206 case e1000_82574:
1207 case e1000_82583:
1208 reg = E1000_READ_REG(hw, E1000_GCR);
1209 reg |= (1 << 22);
1210 E1000_WRITE_REG(hw, E1000_GCR, reg);
1211
1235 /*
1236 * Workaround for hardware errata.
1237 * apply workaround for hardware errata documented in errata
1238 * docs Fixes issue where some error prone or unreliable PCIe
1239 * completions are occurring, particularly with ASPM enabled.
1240 * Without fix, issue can cause tx timeouts.
1241 */
1242 reg = E1000_READ_REG(hw, E1000_GCR2);

--- 19 unchanged lines hidden (view full) ---

1262 u32 offset;
1263 u32 vfta_value = 0;
1264 u32 vfta_offset = 0;
1265 u32 vfta_bit_in_reg = 0;
1266
1267 DEBUGFUNC("e1000_clear_vfta_82571");
1268
1269 switch (hw->mac.type) {
1212 /*
1213 * Workaround for hardware errata.
1214 * apply workaround for hardware errata documented in errata
1215 * docs Fixes issue where some error prone or unreliable PCIe
1216 * completions are occurring, particularly with ASPM enabled.
1217 * Without fix, issue can cause tx timeouts.
1218 */
1219 reg = E1000_READ_REG(hw, E1000_GCR2);

--- 19 unchanged lines hidden (view full) ---

1239 u32 offset;
1240 u32 vfta_value = 0;
1241 u32 vfta_offset = 0;
1242 u32 vfta_bit_in_reg = 0;
1243
1244 DEBUGFUNC("e1000_clear_vfta_82571");
1245
1246 switch (hw->mac.type) {
1247 case e1000_82573:
1270 case e1000_82574:
1271 case e1000_82583:
1248 case e1000_82574:
1249 case e1000_82583:
1272 case e1000_82573:
1273 if (hw->mng_cookie.vlan_id != 0) {
1274 /*
1250 if (hw->mng_cookie.vlan_id != 0) {
1251 /*
1275 *The VFTA is a 4096b bit-field, each identifying
1276 *a single VLAN ID. The following operations
1277 *determine which 32b entry (i.e. offset) into the
1278 *array we want to set the VLAN ID (i.e. bit) of
1279 *the manageability unit.
1280 */
1252 * The VFTA is a 4096b bit-field, each identifying
1253 * a single VLAN ID. The following operations
1254 * determine which 32b entry (i.e. offset) into the
1255 * array we want to set the VLAN ID (i.e. bit) of
1256 * the manageability unit.
1257 */
1281 vfta_offset = (hw->mng_cookie.vlan_id >>
1282 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1283 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1284 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1285 }
1258 vfta_offset = (hw->mng_cookie.vlan_id >>
1259 E1000_VFTA_ENTRY_SHIFT) & E1000_VFTA_ENTRY_MASK;
1260 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1261 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1262 }
1286
1287 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1288 /*
1289 *If the offset we want to clear is the same offset of
1290 *the manageability VLAN ID, then clear all bits except
1291 *that of the manageability unit
1292 */
1293 vfta_value = (offset == vfta_offset) ?
1294 vfta_bit_in_reg : 0;
1295 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset,
1296 vfta_value);
1297 E1000_WRITE_FLUSH(hw);
1298 }
1299 break;
1300 default:
1301 break;
1302 }
1263 break;
1264 default:
1265 break;
1266 }
1267 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1268 /*
1269 * If the offset we want to clear is the same offset of the
1270 * manageability VLAN ID, then clear all bits except that of
1271 * the manageability unit.
1272 */
1273 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1274 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1275 E1000_WRITE_FLUSH(hw);
1276 }
1303}
1304
1305/**
1306 * e1000_check_mng_mode_82574 - Check manageability is enabled
1307 * @hw: pointer to the HW structure
1308 *
1309 * Reads the NVM Initialization Control Word 2 and returns TRUE
1310 * (>0) if any manageability is enabled, else FALSE (0).

--- 53 unchanged lines hidden (view full) ---

1364 DEBUGFUNC("e1000_setup_link_82571");
1365
1366 /*
1367 * 82573 does not have a word in the NVM to determine
1368 * the default flow control setting, so we explicitly
1369 * set it to full.
1370 */
1371 switch (hw->mac.type) {
1277}
1278
1279/**
1280 * e1000_check_mng_mode_82574 - Check manageability is enabled
1281 * @hw: pointer to the HW structure
1282 *
1283 * Reads the NVM Initialization Control Word 2 and returns TRUE
1284 * (>0) if any manageability is enabled, else FALSE (0).

--- 53 unchanged lines hidden (view full) ---

1338 DEBUGFUNC("e1000_setup_link_82571");
1339
1340 /*
1341 * 82573 does not have a word in the NVM to determine
1342 * the default flow control setting, so we explicitly
1343 * set it to full.
1344 */
1345 switch (hw->mac.type) {
1346 case e1000_82573:
1372 case e1000_82574:
1373 case e1000_82583:
1347 case e1000_82574:
1348 case e1000_82583:
1374 case e1000_82573:
1375 if (hw->fc.requested_mode == e1000_fc_default)
1376 hw->fc.requested_mode = e1000_fc_full;
1377 break;
1378 default:
1379 break;
1380 }
1381 return e1000_setup_link_generic(hw);
1382}

--- 72 unchanged lines hidden (view full) ---

1455
1456/**
1457 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1458 * @hw: pointer to the HW structure
1459 *
1460 * Reports the link state as up or down.
1461 *
1462 * If autonegotiation is supported by the link partner, the link state is
1349 if (hw->fc.requested_mode == e1000_fc_default)
1350 hw->fc.requested_mode = e1000_fc_full;
1351 break;
1352 default:
1353 break;
1354 }
1355 return e1000_setup_link_generic(hw);
1356}

--- 72 unchanged lines hidden (view full) ---

1429
1430/**
1431 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1432 * @hw: pointer to the HW structure
1433 *
1434 * Reports the link state as up or down.
1435 *
1436 * If autonegotiation is supported by the link partner, the link state is
1463 * determined by the result of autongotiation. This is the most likely case.
1437 * determined by the result of autonegotiation. This is the most likely case.
1464 * If autonegotiation is not supported by the link partner, and the link
1465 * has a valid signal, force the link up.
1466 *
1467 * The link state is represented internally here by 4 states:
1468 *
1469 * 1) down
1470 * 2) autoneg_progress
1471 * 3) autoneg_complete (the link sucessfully autonegotiated)
1472 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1473 *
1474 **/
1438 * If autonegotiation is not supported by the link partner, and the link
1439 * has a valid signal, force the link up.
1440 *
1441 * The link state is represented internally here by 4 states:
1442 *
1443 * 1) down
1444 * 2) autoneg_progress
1445 * 3) autoneg_complete (the link sucessfully autonegotiated)
1446 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1447 *
1448 **/
1475s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1449static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1476{
1477 struct e1000_mac_info *mac = &hw->mac;
1478 u32 rxcw;
1479 u32 ctrl;
1480 u32 status;
1481 s32 ret_val = E1000_SUCCESS;
1482
1483 DEBUGFUNC("e1000_check_for_serdes_link_82571");

--- 35 unchanged lines hidden (view full) ---

1519 e1000_serdes_link_autoneg_progress;
1520 mac->serdes_has_link = FALSE;
1521 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1522 }
1523 break;
1524
1525 case e1000_serdes_link_autoneg_progress:
1526 if (rxcw & E1000_RXCW_C) {
1450{
1451 struct e1000_mac_info *mac = &hw->mac;
1452 u32 rxcw;
1453 u32 ctrl;
1454 u32 status;
1455 s32 ret_val = E1000_SUCCESS;
1456
1457 DEBUGFUNC("e1000_check_for_serdes_link_82571");

--- 35 unchanged lines hidden (view full) ---

1493 e1000_serdes_link_autoneg_progress;
1494 mac->serdes_has_link = FALSE;
1495 DEBUGOUT("FORCED_UP -> AN_PROG\n");
1496 }
1497 break;
1498
1499 case e1000_serdes_link_autoneg_progress:
1500 if (rxcw & E1000_RXCW_C) {
1527 /* We received /C/ ordered sets, meaning the
1501 /*
1502 * We received /C/ ordered sets, meaning the
1528 * link partner has autonegotiated, and we can
1503 * link partner has autonegotiated, and we can
1529 * trust the Link Up (LU) status bit
1504 * trust the Link Up (LU) status bit.
1530 */
1531 if (status & E1000_STATUS_LU) {
1532 mac->serdes_link_state =
1533 e1000_serdes_link_autoneg_complete;
1534 DEBUGOUT("AN_PROG -> AN_UP\n");
1535 mac->serdes_has_link = TRUE;
1536 } else {
1505 */
1506 if (status & E1000_STATUS_LU) {
1507 mac->serdes_link_state =
1508 e1000_serdes_link_autoneg_complete;
1509 DEBUGOUT("AN_PROG -> AN_UP\n");
1510 mac->serdes_has_link = TRUE;
1511 } else {
1537 /* Autoneg completed, but failed */
1512 /* Autoneg completed, but failed. */
1538 mac->serdes_link_state =
1539 e1000_serdes_link_down;
1540 DEBUGOUT("AN_PROG -> DOWN\n");
1541 }
1542 } else {
1513 mac->serdes_link_state =
1514 e1000_serdes_link_down;
1515 DEBUGOUT("AN_PROG -> DOWN\n");
1516 }
1517 } else {
1543 /* The link partner did not autoneg.
1518 /*
1519 * The link partner did not autoneg.
1544 * Force link up and full duplex, and change
1545 * state to forced.
1546 */
1547 E1000_WRITE_REG(hw, E1000_TXCW,
1548 (mac->txcw & ~E1000_TXCW_ANE));
1549 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1551

--- 8 unchanged lines hidden (view full) ---

1560 e1000_serdes_link_forced_up;
1561 mac->serdes_has_link = TRUE;
1562 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1563 }
1564 break;
1565
1566 case e1000_serdes_link_down:
1567 default:
1520 * Force link up and full duplex, and change
1521 * state to forced.
1522 */
1523 E1000_WRITE_REG(hw, E1000_TXCW,
1524 (mac->txcw & ~E1000_TXCW_ANE));
1525 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1526 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1527

--- 8 unchanged lines hidden (view full) ---

1536 e1000_serdes_link_forced_up;
1537 mac->serdes_has_link = TRUE;
1538 DEBUGOUT("AN_PROG -> FORCED_UP\n");
1539 }
1540 break;
1541
1542 case e1000_serdes_link_down:
1543 default:
1568 /* The link was down but the receiver has now gained
1544 /*
1545 * The link was down but the receiver has now gained
1569 * valid sync, so lets see if we can bring the link
1546 * valid sync, so lets see if we can bring the link
1570 * up. */
1547 * up.
1548 */
1571 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1572 E1000_WRITE_REG(hw, E1000_CTRL,
1573 (ctrl & ~E1000_CTRL_SLU));
1574 mac->serdes_link_state =
1575 e1000_serdes_link_autoneg_progress;
1576 DEBUGOUT("DOWN -> AN_PROG\n");
1577 break;
1578 }
1579 } else {
1580 if (!(rxcw & E1000_RXCW_SYNCH)) {
1581 mac->serdes_has_link = FALSE;
1582 mac->serdes_link_state = e1000_serdes_link_down;
1583 DEBUGOUT("ANYSTATE -> DOWN\n");
1584 } else {
1585 /*
1549 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1550 E1000_WRITE_REG(hw, E1000_CTRL,
1551 (ctrl & ~E1000_CTRL_SLU));
1552 mac->serdes_link_state =
1553 e1000_serdes_link_autoneg_progress;
1554 DEBUGOUT("DOWN -> AN_PROG\n");
1555 break;
1556 }
1557 } else {
1558 if (!(rxcw & E1000_RXCW_SYNCH)) {
1559 mac->serdes_has_link = FALSE;
1560 mac->serdes_link_state = e1000_serdes_link_down;
1561 DEBUGOUT("ANYSTATE -> DOWN\n");
1562 } else {
1563 /*
1586 * We have sync, and can tolerate one
1587 * invalid (IV) codeword before declaring
1588 * link down, so reread to look again
1564 * We have sync, and can tolerate one invalid (IV)
1565 * codeword before declaring link down, so reread
1566 * to look again.
1589 */
1590 usec_delay(10);
1591 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1592 if (rxcw & E1000_RXCW_IV) {
1593 mac->serdes_link_state = e1000_serdes_link_down;
1594 mac->serdes_has_link = FALSE;
1595 DEBUGOUT("ANYSTATE -> DOWN\n");
1596 }

--- 19 unchanged lines hidden (view full) ---

1616
1617 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1618 if (ret_val) {
1619 DEBUGOUT("NVM Read Error\n");
1620 goto out;
1621 }
1622
1623 switch (hw->mac.type) {
1567 */
1568 usec_delay(10);
1569 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1570 if (rxcw & E1000_RXCW_IV) {
1571 mac->serdes_link_state = e1000_serdes_link_down;
1572 mac->serdes_has_link = FALSE;
1573 DEBUGOUT("ANYSTATE -> DOWN\n");
1574 }

--- 19 unchanged lines hidden (view full) ---

1594
1595 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1596 if (ret_val) {
1597 DEBUGOUT("NVM Read Error\n");
1598 goto out;
1599 }
1600
1601 switch (hw->mac.type) {
1602 case e1000_82573:
1624 case e1000_82574:
1625 case e1000_82583:
1603 case e1000_82574:
1604 case e1000_82583:
1626 case e1000_82573:
1627 if(*data == ID_LED_RESERVED_F746)
1605 if (*data == ID_LED_RESERVED_F746)
1628 *data = ID_LED_DEFAULT_82573;
1629 break;
1630 default:
1631 if (*data == ID_LED_RESERVED_0000 ||
1606 *data = ID_LED_DEFAULT_82573;
1607 break;
1608 default:
1609 if (*data == ID_LED_RESERVED_0000 ||
1632 *data == ID_LED_RESERVED_FFFF)
1610 *data == ID_LED_RESERVED_FFFF)
1633 *data = ID_LED_DEFAULT;
1634 break;
1635 }
1636
1637out:
1638 return ret_val;
1639}
1640

--- 196 unchanged lines hidden --- 		1611 *data = ID_LED_DEFAULT;
1612 break;
1613 }
1614
1615out:
1616 return ret_val;
1617}
1618

--- 196 unchanged lines hidden ---