1/******************************************************************************
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3 Copyright (c) 2001-2011, Intel Corporation
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32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82543.c 238148 2012-07-05 20:26:57Z jfv $*/
34
35/*
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
42 */
43
44#include "e1000_api.h"
45
46static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
50 u16 *data);
51static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
52 u16 data);
53static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62static s32 e1000_led_on_82543(struct e1000_hw *hw);
63static s32 e1000_led_off_82543(struct e1000_hw *hw);
64static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
65 u32 value);
66static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
74 u16 count);
75static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
78
79
80/**
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure
83 **/
84static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
85{
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = E1000_SUCCESS;
88
89 DEBUGFUNC("e1000_init_phy_params_82543");
90
91 if (hw->phy.media_type != e1000_media_type_copper) {
92 phy->type = e1000_phy_none;
93 goto out;
94 } else {
95 phy->ops.power_up = e1000_power_up_phy_copper;
96 phy->ops.power_down = e1000_power_down_phy_copper;
97 }
98
99 phy->addr = 1;
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
101 phy->reset_delay_us = 10000;
102 phy->type = e1000_phy_m88;
103
104 /* Function Pointers */
105 phy->ops.check_polarity = e1000_check_polarity_m88;
106 phy->ops.commit = e1000_phy_sw_reset_generic;
107 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
108 phy->ops.get_cable_length = e1000_get_cable_length_m88;
109 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
111 ? e1000_read_phy_reg_82543
112 : e1000_read_phy_reg_m88;
113 phy->ops.reset = (hw->mac.type == e1000_82543)
114 ? e1000_phy_hw_reset_82543
115 : e1000_phy_hw_reset_generic;
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
117 ? e1000_write_phy_reg_82543
118 : e1000_write_phy_reg_m88;
119 phy->ops.get_info = e1000_get_phy_info_m88;
120
121 /*
122 * The external PHY of the 82543 can be in a funky state.
123 * Resetting helps us read the PHY registers for acquiring
124 * the PHY ID.
125 */
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
128 if (ret_val) {
129 DEBUGOUT("Resetting PHY during init failed.\n");
130 goto out;
131 }
132 msec_delay(20);
133 }
134
135 ret_val = e1000_get_phy_id(hw);
136 if (ret_val)
137 goto out;
138
139 /* Verify phy id */
140 switch (hw->mac.type) {
141 case e1000_82543:
142 if (phy->id != M88E1000_E_PHY_ID) {
143 ret_val = -E1000_ERR_PHY;
144 goto out;
145 }
146 break;
147 case e1000_82544:
148 if (phy->id != M88E1000_I_PHY_ID) {
149 ret_val = -E1000_ERR_PHY;
150 goto out;
151 }
152 break;
153 default:
154 ret_val = -E1000_ERR_PHY;
155 goto out;
156 break;
157 }
158
159out:
160 return ret_val;
161}
162
163/**
164 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
165 * @hw: pointer to the HW structure
166 **/
167static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
168{
169 struct e1000_nvm_info *nvm = &hw->nvm;
170
171 DEBUGFUNC("e1000_init_nvm_params_82543");
172
173 nvm->type = e1000_nvm_eeprom_microwire;
174 nvm->word_size = 64;
175 nvm->delay_usec = 50;
176 nvm->address_bits = 6;
177 nvm->opcode_bits = 3;
178
179 /* Function Pointers */
180 nvm->ops.read = e1000_read_nvm_microwire;
181 nvm->ops.update = e1000_update_nvm_checksum_generic;
182 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
183 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
184 nvm->ops.write = e1000_write_nvm_microwire;
185
186 return E1000_SUCCESS;
187}
188
189/**
190 * e1000_init_mac_params_82543 - Init MAC func ptrs.
191 * @hw: pointer to the HW structure
192 **/
193static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
194{
195 struct e1000_mac_info *mac = &hw->mac;
196
197 DEBUGFUNC("e1000_init_mac_params_82543");
198
199 /* Set media type */
200 switch (hw->device_id) {
201 case E1000_DEV_ID_82543GC_FIBER:
202 case E1000_DEV_ID_82544EI_FIBER:
203 hw->phy.media_type = e1000_media_type_fiber;
204 break;
205 default:
206 hw->phy.media_type = e1000_media_type_copper;
207 break;
208 }
209
210 /* Set mta register count */
211 mac->mta_reg_count = 128;
212 /* Set rar entry count */
213 mac->rar_entry_count = E1000_RAR_ENTRIES;
214
215 /* Function pointers */
216
217 /* bus type/speed/width */
218 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
219 /* function id */
220 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
221 /* reset */
222 mac->ops.reset_hw = e1000_reset_hw_82543;
223 /* hw initialization */
224 mac->ops.init_hw = e1000_init_hw_82543;
225 /* link setup */
226 mac->ops.setup_link = e1000_setup_link_82543;
227 /* physical interface setup */
228 mac->ops.setup_physical_interface =
229 (hw->phy.media_type == e1000_media_type_copper)
230 ? e1000_setup_copper_link_82543
231 : e1000_setup_fiber_link_82543;
232 /* check for link */
233 mac->ops.check_for_link =
234 (hw->phy.media_type == e1000_media_type_copper)
235 ? e1000_check_for_copper_link_82543
236 : e1000_check_for_fiber_link_82543;
237 /* link info */
238 mac->ops.get_link_up_info =
239 (hw->phy.media_type == e1000_media_type_copper)
240 ? e1000_get_speed_and_duplex_copper_generic
241 : e1000_get_speed_and_duplex_fiber_serdes_generic;
242 /* multicast address update */
243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
244 /* writing VFTA */
245 mac->ops.write_vfta = e1000_write_vfta_82543;
246 /* clearing VFTA */
247 mac->ops.clear_vfta = e1000_clear_vfta_generic;
248 /* read mac address */
249 mac->ops.read_mac_addr = e1000_read_mac_addr_82543;
250 /* turn on/off LED */
251 mac->ops.led_on = e1000_led_on_82543;
252 mac->ops.led_off = e1000_led_off_82543;
253 /* clear hardware counters */
254 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
255
256 /* Set tbi compatibility */
257 if ((hw->mac.type != e1000_82543) ||
258 (hw->phy.media_type == e1000_media_type_fiber))
259 e1000_set_tbi_compatibility_82543(hw, FALSE);
260
261 return E1000_SUCCESS;
262}
263
264/**
265 * e1000_init_function_pointers_82543 - Init func ptrs.
266 * @hw: pointer to the HW structure
267 *
268 * Called to initialize all function pointers and parameters.
269 **/
270void e1000_init_function_pointers_82543(struct e1000_hw *hw)
271{
272 DEBUGFUNC("e1000_init_function_pointers_82543");
273
274 hw->mac.ops.init_params = e1000_init_mac_params_82543;
275 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
276 hw->phy.ops.init_params = e1000_init_phy_params_82543;
277}
278
279/**
280 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
281 * @hw: pointer to the HW structure
282 *
283 * Returns the current status of 10-bit Interface (TBI) compatibility
284 * (enabled/disabled).
285 **/
286static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
287{
288 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
289 bool state = FALSE;
290
291 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
292
293 if (hw->mac.type != e1000_82543) {
294 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
295 goto out;
296 }
297
298 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
299 ? TRUE : FALSE;
300
301out:
302 return state;
303}
304
305/**
306 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
307 * @hw: pointer to the HW structure
308 * @state: enable/disable TBI compatibility
309 *
310 * Enables or disabled 10-bit Interface (TBI) compatibility.
311 **/
312void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
313{
314 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
315
316 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
317
318 if (hw->mac.type != e1000_82543) {
319 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
320 goto out;
321 }
322
323 if (state)
324 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
325 else
326 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
327
328out:
329 return;
330}
331
332/**
333 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
334 * @hw: pointer to the HW structure
335 *
336 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
337 * (enabled/disabled).
338 **/
339bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
340{
341 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
342 bool state = FALSE;
343
344 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
345
346 if (hw->mac.type != e1000_82543) {
347 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
348 goto out;
349 }
350
351 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
352 ? TRUE : FALSE;
353
354out:
355 return state;
356}
357
358/**
359 * e1000_set_tbi_sbp_82543 - Set TBI SBP
360 * @hw: pointer to the HW structure
361 * @state: enable/disable TBI store bad packet
362 *
363 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
364 **/
365static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
366{
367 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
368
369 DEBUGFUNC("e1000_set_tbi_sbp_82543");
370
371 if (state && e1000_tbi_compatibility_enabled_82543(hw))
372 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
373 else
374 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
375
376 return;
377}
378
379/**
380 * e1000_init_phy_disabled_82543 - Returns init PHY status
381 * @hw: pointer to the HW structure
382 *
383 * Returns the current status of whether PHY initialization is disabled.
384 * True if PHY initialization is disabled else FALSE.
385 **/
386static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
387{
388 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
389 bool ret_val;
390
391 DEBUGFUNC("e1000_init_phy_disabled_82543");
392
393 if (hw->mac.type != e1000_82543) {
394 ret_val = FALSE;
395 goto out;
396 }
397
398 ret_val = dev_spec->init_phy_disabled;
399
400out:
401 return ret_val;
402}
403
404/**
405 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
406 * @hw: pointer to the HW structure
407 * @stats: Struct containing statistic register values
408 * @frame_len: The length of the frame in question
409 * @mac_addr: The Ethernet destination address of the frame in question
410 * @max_frame_size: The maximum frame size
411 *
412 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
413 **/
414void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
415 struct e1000_hw_stats *stats, u32 frame_len,
416 u8 *mac_addr, u32 max_frame_size)
417{
418 if (!(e1000_tbi_sbp_enabled_82543(hw)))
419 goto out;
420
421 /* First adjust the frame length. */
422 frame_len--;
423 /*
424 * We need to adjust the statistics counters, since the hardware
425 * counters overcount this packet as a CRC error and undercount
426 * the packet as a good packet
427 */
428 /* This packet should not be counted as a CRC error. */
429 stats->crcerrs--;
430 /* This packet does count as a Good Packet Received. */
431 stats->gprc++;
432
433 /* Adjust the Good Octets received counters */
434 stats->gorc += frame_len;
435
436 /*
437 * Is this a broadcast or multicast? Check broadcast first,
438 * since the test for a multicast frame will test positive on
439 * a broadcast frame.
440 */
441 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
442 /* Broadcast packet */
443 stats->bprc++;
444 else if (*mac_addr & 0x01)
445 /* Multicast packet */
446 stats->mprc++;
447
448 /*
449 * In this case, the hardware has overcounted the number of
450 * oversize frames.
451 */
452 if ((frame_len == max_frame_size) && (stats->roc > 0))
453 stats->roc--;
454
455 /*
456 * Adjust the bin counters when the extra byte put the frame in the
457 * wrong bin. Remember that the frame_len was adjusted above.
458 */
459 if (frame_len == 64) {
460 stats->prc64++;
461 stats->prc127--;
462 } else if (frame_len == 127) {
463 stats->prc127++;
464 stats->prc255--;
465 } else if (frame_len == 255) {
466 stats->prc255++;
467 stats->prc511--;
468 } else if (frame_len == 511) {
469 stats->prc511++;
470 stats->prc1023--;
471 } else if (frame_len == 1023) {
472 stats->prc1023++;
473 stats->prc1522--;
474 } else if (frame_len == 1522) {
475 stats->prc1522++;
476 }
477
478out:
479 return;
480}
481
482/**
483 * e1000_read_phy_reg_82543 - Read PHY register
484 * @hw: pointer to the HW structure
485 * @offset: register offset to be read
486 * @data: pointer to the read data
487 *
488 * Reads the PHY at offset and stores the information read to data.
489 **/
490static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
491{
492 u32 mdic;
493 s32 ret_val = E1000_SUCCESS;
494
495 DEBUGFUNC("e1000_read_phy_reg_82543");
496
497 if (offset > MAX_PHY_REG_ADDRESS) {
498 DEBUGOUT1("PHY Address %d is out of range\n", offset);
499 ret_val = -E1000_ERR_PARAM;
500 goto out;
501 }
502
503 /*
504 * We must first send a preamble through the MDIO pin to signal the
505 * beginning of an MII instruction. This is done by sending 32
506 * consecutive "1" bits.
507 */
508 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
509
510 /*
511 * Now combine the next few fields that are required for a read
512 * operation. We use this method instead of calling the
513 * e1000_shift_out_mdi_bits routine five different times. The format
514 * of an MII read instruction consists of a shift out of 14 bits and
515 * is defined as follows:
516 * <Preamble><SOF><Op Code><Phy Addr><Offset>
517 * followed by a shift in of 18 bits. This first two bits shifted in
518 * are TurnAround bits used to avoid contention on the MDIO pin when a
519 * READ operation is performed. These two bits are thrown away
520 * followed by a shift in of 16 bits which contains the desired data.
521 */
522 mdic = (offset | (hw->phy.addr << 5) |
523 (PHY_OP_READ << 10) | (PHY_SOF << 12));
524
525 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
526
527 /*
528 * Now that we've shifted out the read command to the MII, we need to
529 * "shift in" the 16-bit value (18 total bits) of the requested PHY
530 * register address.
531 */
532 *data = e1000_shift_in_mdi_bits_82543(hw);
533
534out:
535 return ret_val;
536}
537
538/**
539 * e1000_write_phy_reg_82543 - Write PHY register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be written
542 * @data: pointer to the data to be written at offset
543 *
544 * Writes data to the PHY at offset.
545 **/
546static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
547{
548 u32 mdic;
549 s32 ret_val = E1000_SUCCESS;
550
551 DEBUGFUNC("e1000_write_phy_reg_82543");
552
553 if (offset > MAX_PHY_REG_ADDRESS) {
554 DEBUGOUT1("PHY Address %d is out of range\n", offset);
555 ret_val = -E1000_ERR_PARAM;
556 goto out;
557 }
558
559 /*
560 * We'll need to use the SW defined pins to shift the write command
561 * out to the PHY. We first send a preamble to the PHY to signal the
562 * beginning of the MII instruction. This is done by sending 32
563 * consecutive "1" bits.
564 */
565 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
566
567 /*
568 * Now combine the remaining required fields that will indicate a
569 * write operation. We use this method instead of calling the
570 * e1000_shift_out_mdi_bits routine for each field in the command. The
571 * format of a MII write instruction is as follows:
572 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
573 */
574 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
575 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
576 mdic <<= 16;
577 mdic |= (u32) data;
578
579 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
580
581out:
582 return ret_val;
583}
584
585/**
586 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
587 * @hw: pointer to the HW structure
588 * @ctrl: pointer to the control register
589 *
590 * Raise the management data input clock by setting the MDC bit in the control
591 * register.
592 **/
593static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
594{
595 /*
596 * Raise the clock input to the Management Data Clock (by setting the
597 * MDC bit), and then delay a sufficient amount of time.
598 */
599 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
600 E1000_WRITE_FLUSH(hw);
601 usec_delay(10);
602}
603
604/**
605 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
606 * @hw: pointer to the HW structure
607 * @ctrl: pointer to the control register
608 *
609 * Lower the management data input clock by clearing the MDC bit in the
610 * control register.
611 **/
612static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
613{
614 /*
615 * Lower the clock input to the Management Data Clock (by clearing the
616 * MDC bit), and then delay a sufficient amount of time.
617 */
618 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
619 E1000_WRITE_FLUSH(hw);
620 usec_delay(10);
621}
622
623/**
624 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
625 * @hw: pointer to the HW structure
626 * @data: data to send to the PHY
627 * @count: number of bits to shift out
628 *
629 * We need to shift 'count' bits out to the PHY. So, the value in the
630 * "data" parameter will be shifted out to the PHY one bit at a time.
631 * In order to do this, "data" must be broken down into bits.
632 **/
633static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
634 u16 count)
635{
636 u32 ctrl, mask;
637
638 /*
639 * We need to shift "count" number of bits out to the PHY. So, the
640 * value in the "data" parameter will be shifted out to the PHY one
641 * bit at a time. In order to do this, "data" must be broken down
642 * into bits.
643 */
644 mask = 0x01;
645 mask <<= (count -1);
646
647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
648
649 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
650 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
651
652 while (mask) {
653 /*
654 * A "1" is shifted out to the PHY by setting the MDIO bit to
655 * "1" and then raising and lowering the Management Data Clock.
656 * A "0" is shifted out to the PHY by setting the MDIO bit to
657 * "0" and then raising and lowering the clock.
658 */
659 if (data & mask) ctrl |= E1000_CTRL_MDIO;
660 else ctrl &= ~E1000_CTRL_MDIO;
661
662 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
663 E1000_WRITE_FLUSH(hw);
664
665 usec_delay(10);
666
667 e1000_raise_mdi_clk_82543(hw, &ctrl);
668 e1000_lower_mdi_clk_82543(hw, &ctrl);
669
670 mask >>= 1;
671 }
672}
673
674/**
675 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
676 * @hw: pointer to the HW structure
677 *
678 * In order to read a register from the PHY, we need to shift 18 bits
679 * in from the PHY. Bits are "shifted in" by raising the clock input to
680 * the PHY (setting the MDC bit), and then reading the value of the data out
681 * MDIO bit.
682 **/
683static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
684{
685 u32 ctrl;
686 u16 data = 0;
687 u8 i;
688
689 /*
690 * In order to read a register from the PHY, we need to shift in a
691 * total of 18 bits from the PHY. The first two bit (turnaround)
692 * times are used to avoid contention on the MDIO pin when a read
693 * operation is performed. These two bits are ignored by us and
694 * thrown away. Bits are "shifted in" by raising the input to the
695 * Management Data Clock (setting the MDC bit) and then reading the
696 * value of the MDIO bit.
697 */
698 ctrl = E1000_READ_REG(hw, E1000_CTRL);
699
700 /*
701 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
702 * input.
703 */
704 ctrl &= ~E1000_CTRL_MDIO_DIR;
705 ctrl &= ~E1000_CTRL_MDIO;
706
707 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
708 E1000_WRITE_FLUSH(hw);
709
710 /*
711 * Raise and lower the clock before reading in the data. This accounts
712 * for the turnaround bits. The first clock occurred when we clocked
713 * out the last bit of the Register Address.
714 */
715 e1000_raise_mdi_clk_82543(hw, &ctrl);
716 e1000_lower_mdi_clk_82543(hw, &ctrl);
717
718 for (data = 0, i = 0; i < 16; i++) {
719 data <<= 1;
720 e1000_raise_mdi_clk_82543(hw, &ctrl);
721 ctrl = E1000_READ_REG(hw, E1000_CTRL);
722 /* Check to see if we shifted in a "1". */
723 if (ctrl & E1000_CTRL_MDIO)
724 data |= 1;
725 e1000_lower_mdi_clk_82543(hw, &ctrl);
726 }
727
728 e1000_raise_mdi_clk_82543(hw, &ctrl);
729 e1000_lower_mdi_clk_82543(hw, &ctrl);
730
731 return data;
732}
733
734/**
735 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
736 * @hw: pointer to the HW structure
737 *
738 * Calls the function to force speed and duplex for the m88 PHY, and
739 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
740 * then call the function for polarity reversal workaround.
741 **/
742static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
743{
744 s32 ret_val;
745
746 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
747
748 ret_val = e1000_phy_force_speed_duplex_m88(hw);
749 if (ret_val)
750 goto out;
751
752 if (!hw->mac.autoneg &&
753 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
754 ret_val = e1000_polarity_reversal_workaround_82543(hw);
755
756out:
757 return ret_val;
758}
759
760/**
761 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
762 * @hw: pointer to the HW structure
763 *
764 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
765 * inadvertently. To workaround the issue, we disable the transmitter on
766 * the PHY until we have established the link partner's link parameters.
767 **/
768static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
769{
770 s32 ret_val = E1000_SUCCESS;
771 u16 mii_status_reg;
772 u16 i;
773 bool link;
774
775 if (!(hw->phy.ops.write_reg))
776 goto out;
777
778 /* Polarity reversal workaround for forced 10F/10H links. */
779
780 /* Disable the transmitter on the PHY */
781
782 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
783 if (ret_val)
784 goto out;
785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
786 if (ret_val)
787 goto out;
788
789 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
790 if (ret_val)
791 goto out;
792
793 /*
794 * This loop will early-out if the NO link condition has been met.
795 * In other words, DO NOT use e1000_phy_has_link_generic() here.
796 */
797 for (i = PHY_FORCE_TIME; i > 0; i--) {
798 /*
799 * Read the MII Status Register and wait for Link Status bit
800 * to be clear.
801 */
802
803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
804 if (ret_val)
805 goto out;
806
807 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
808 if (ret_val)
809 goto out;
810
811 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
812 break;
813 msec_delay_irq(100);
814 }
815
816 /* Recommended delay time after link has been lost */
817 msec_delay_irq(1000);
818
819 /* Now we will re-enable the transmitter on the PHY */
820
821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
822 if (ret_val)
823 goto out;
824 msec_delay_irq(50);
825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
826 if (ret_val)
827 goto out;
828 msec_delay_irq(50);
829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
830 if (ret_val)
831 goto out;
832 msec_delay_irq(50);
833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
834 if (ret_val)
835 goto out;
836
837 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
838 if (ret_val)
839 goto out;
840
841 /*
842 * Read the MII Status Register and wait for Link Status bit
843 * to be set.
844 */
845 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
846 if (ret_val)
847 goto out;
848
849out:
850 return ret_val;
851}
852
853/**
854 * e1000_phy_hw_reset_82543 - PHY hardware reset
855 * @hw: pointer to the HW structure
856 *
857 * Sets the PHY_RESET_DIR bit in the extended device control register
858 * to put the PHY into a reset and waits for completion. Once the reset
859 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
860 * of reset.
861 **/
862static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
863{
864 u32 ctrl_ext;
865 s32 ret_val;
866
867 DEBUGFUNC("e1000_phy_hw_reset_82543");
868
869 /*
870 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
871 * bit to put the PHY into reset...
872 */
873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
874 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
875 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
877 E1000_WRITE_FLUSH(hw);
878
879 msec_delay(10);
880
881 /* ...then take it out of reset. */
882 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
883 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
884 E1000_WRITE_FLUSH(hw);
885
886 usec_delay(150);
887
888 if (!(hw->phy.ops.get_cfg_done))
889 return E1000_SUCCESS;
890
891 ret_val = hw->phy.ops.get_cfg_done(hw);
892
893 return ret_val;
894}
895
896/**
897 * e1000_reset_hw_82543 - Reset hardware
898 * @hw: pointer to the HW structure
899 *
900 * This resets the hardware into a known state.
901 **/
902static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
903{
904 u32 ctrl, icr;
905 s32 ret_val = E1000_SUCCESS;
906
907 DEBUGFUNC("e1000_reset_hw_82543");
908
909 DEBUGOUT("Masking off all interrupts\n");
910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911
912 E1000_WRITE_REG(hw, E1000_RCTL, 0);
913 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
914 E1000_WRITE_FLUSH(hw);
915
916 e1000_set_tbi_sbp_82543(hw, FALSE);
917
918 /*
919 * Delay to allow any outstanding PCI transactions to complete before
920 * resetting the device
921 */
922 msec_delay(10);
923
924 ctrl = E1000_READ_REG(hw, E1000_CTRL);
925
926 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
927 if (hw->mac.type == e1000_82543) {
928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
929 } else {
930 /*
931 * The 82544 can't ACK the 64-bit write when issuing the
932 * reset, so use IO-mapping as a workaround.
933 */
934 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
935 }
936
937 /*
938 * After MAC reset, force reload of NVM to restore power-on
939 * settings to device.
940 */
941 hw->nvm.ops.reload(hw);
942 msec_delay(2);
943
944 /* Masking off and clearing any pending interrupts */
945 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
946 icr = E1000_READ_REG(hw, E1000_ICR);
947
948 return ret_val;
949}
950
951/**
952 * e1000_init_hw_82543 - Initialize hardware
953 * @hw: pointer to the HW structure
954 *
955 * This inits the hardware readying it for operation.
956 **/
957static s32 e1000_init_hw_82543(struct e1000_hw *hw)
958{
959 struct e1000_mac_info *mac = &hw->mac;
960 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
961 u32 ctrl;
962 s32 ret_val;
963 u16 i;
964
965 DEBUGFUNC("e1000_init_hw_82543");
966
967 /* Disabling VLAN filtering */
968 E1000_WRITE_REG(hw, E1000_VET, 0);
969 mac->ops.clear_vfta(hw);
970
971 /* Setup the receive address. */
972 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
973
974 /* Zero out the Multicast HASH table */
975 DEBUGOUT("Zeroing the MTA\n");
976 for (i = 0; i < mac->mta_reg_count; i++) {
977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
978 E1000_WRITE_FLUSH(hw);
979 }
980
981 /*
982 * Set the PCI priority bit correctly in the CTRL register. This
983 * determines if the adapter gives priority to receives, or if it
984 * gives equal priority to transmits and receives.
985 */
986 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
989 }
990
991 e1000_pcix_mmrbc_workaround_generic(hw);
992
993 /* Setup link and flow control */
994 ret_val = mac->ops.setup_link(hw);
995
996 /*
997 * Clear all of the statistics registers (clear on read). It is
998 * important that we do this after we have tried to establish link
999 * because the symbol error count will increment wildly if there
1000 * is no link.
1001 */
1002 e1000_clear_hw_cntrs_82543(hw);
1003
1004 return ret_val;
1005}
1006
1007/**
1008 * e1000_setup_link_82543 - Setup flow control and link settings
1009 * @hw: pointer to the HW structure
1010 *
1011 * Read the EEPROM to determine the initial polarity value and write the
1012 * extended device control register with the information before calling
1013 * the generic setup link function, which does the following:
1014 * Determines which flow control settings to use, then configures flow
1015 * control. Calls the appropriate media-specific link configuration
1016 * function. Assuming the adapter has a valid link partner, a valid link
1017 * should be established. Assumes the hardware has previously been reset
1018 * and the transmitter and receiver are not enabled.
1019 **/
1020static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1021{
1022 u32 ctrl_ext;
1023 s32 ret_val;
1024 u16 data;
1025
1026 DEBUGFUNC("e1000_setup_link_82543");
1027
1028 /*
1029 * Take the 4 bits from NVM word 0xF that determine the initial
1030 * polarity value for the SW controlled pins, and setup the
1031 * Extended Device Control reg with that info.
1032 * This is needed because one of the SW controlled pins is used for
1033 * signal detection. So this should be done before phy setup.
1034 */
1035 if (hw->mac.type == e1000_82543) {
1036 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1037 if (ret_val) {
1038 DEBUGOUT("NVM Read Error\n");
1039 ret_val = -E1000_ERR_NVM;
1040 goto out;
1041 }
1042 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1043 NVM_SWDPIO_EXT_SHIFT);
1044 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1045 }
1046
1047 ret_val = e1000_setup_link_generic(hw);
1048
1049out:
1050 return ret_val;
1051}
1052
1053/**
1054 * e1000_setup_copper_link_82543 - Configure copper link settings
1055 * @hw: pointer to the HW structure
1056 *
1057 * Configures the link for auto-neg or forced speed and duplex. Then we check
1058 * for link, once link is established calls to configure collision distance
1059 * and flow control are called.
1060 **/
1061static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1062{
1063 u32 ctrl;
1064 s32 ret_val;
1065 bool link;
1066
1067 DEBUGFUNC("e1000_setup_copper_link_82543");
1068
1069 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1070 /*
1071 * With 82543, we need to force speed and duplex on the MAC
1072 * equal to what the PHY speed and duplex configuration is.
1073 * In addition, we need to perform a hardware reset on the
1074 * PHY to take it out of reset.
1075 */
1076 if (hw->mac.type == e1000_82543) {
1077 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079 ret_val = hw->phy.ops.reset(hw);
1080 if (ret_val)
1081 goto out;
1082 } else {
1083 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1085 }
1086
1087 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1088 ret_val = e1000_copper_link_setup_m88(hw);
1089 if (ret_val)
1090 goto out;
1091
1092 if (hw->mac.autoneg) {
1093 /*
1094 * Setup autoneg and flow control advertisement and perform
1095 * autonegotiation.
1096 */
1097 ret_val = e1000_copper_link_autoneg(hw);
1098 if (ret_val)
1099 goto out;
1100 } else {
1101 /*
1102 * PHY will be set to 10H, 10F, 100H or 100F
1103 * depending on user settings.
1104 */
1105 DEBUGOUT("Forcing Speed and Duplex\n");
1106 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1107 if (ret_val) {
1108 DEBUGOUT("Error Forcing Speed and Duplex\n");
1109 goto out;
1110 }
1111 }
1112
1113 /*
1114 * Check link status. Wait up to 100 microseconds for link to become
1115 * valid.
1116 */
1117 ret_val = e1000_phy_has_link_generic(hw,
1118 COPPER_LINK_UP_LIMIT,
1119 10,
1120 &link);
1121 if (ret_val)
1122 goto out;
1123
1124
1125 if (link) {
1126 DEBUGOUT("Valid link established!!!\n");
1127 /* Config the MAC and PHY after link is up */
1128 if (hw->mac.type == e1000_82544) {
1129 hw->mac.ops.config_collision_dist(hw);
1130 } else {
1131 ret_val = e1000_config_mac_to_phy_82543(hw);
1132 if (ret_val)
1133 goto out;
1134 }
1135 ret_val = e1000_config_fc_after_link_up_generic(hw);
1136 } else {
1137 DEBUGOUT("Unable to establish link!!!\n");
1138 }
1139
1140out:
1141 return ret_val;
1142}
1143
1144/**
1145 * e1000_setup_fiber_link_82543 - Setup link for fiber
1146 * @hw: pointer to the HW structure
1147 *
1148 * Configures collision distance and flow control for fiber links. Upon
1149 * successful setup, poll for link.
1150 **/
1151static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1152{
1153 u32 ctrl;
1154 s32 ret_val;
1155
1156 DEBUGFUNC("e1000_setup_fiber_link_82543");
1157
1158 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1159
1160 /* Take the link out of reset */
1161 ctrl &= ~E1000_CTRL_LRST;
1162
1163 hw->mac.ops.config_collision_dist(hw);
1164
1165 ret_val = e1000_commit_fc_settings_generic(hw);
1166 if (ret_val)
1167 goto out;
1168
1169 DEBUGOUT("Auto-negotiation enabled\n");
1170
1171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1172 E1000_WRITE_FLUSH(hw);
1173 msec_delay(1);
1174
1175 /*
1176 * For these adapters, the SW definable pin 1 is cleared when the
1177 * optics detect a signal. If we have a signal, then poll for a
1178 * "Link-Up" indication.
1179 */
1180 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1181 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1182 } else {
1183 DEBUGOUT("No signal detected\n");
1184 }
1185
1186out:
1187 return ret_val;
1188}
1189
1190/**
1191 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1192 * @hw: pointer to the HW structure
1193 *
1194 * Checks the phy for link, if link exists, do the following:
1195 * - check for downshift
1196 * - do polarity workaround (if necessary)
1197 * - configure collision distance
1198 * - configure flow control after link up
1199 * - configure tbi compatibility
1200 **/
1201static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1202{
1203 struct e1000_mac_info *mac = &hw->mac;
1204 u32 icr, rctl;
1205 s32 ret_val;
1206 u16 speed, duplex;
1207 bool link;
1208
1209 DEBUGFUNC("e1000_check_for_copper_link_82543");
1210
1211 if (!mac->get_link_status) {
1212 ret_val = E1000_SUCCESS;
1213 goto out;
1214 }
1215
1216 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1217 if (ret_val)
1218 goto out;
1219
1220 if (!link)
1221 goto out; /* No link detected */
1222
1223 mac->get_link_status = FALSE;
1224
1225 e1000_check_downshift_generic(hw);
1226
1227 /*
1228 * If we are forcing speed/duplex, then we can return since
1229 * we have already determined whether we have link or not.
1230 */
1231 if (!mac->autoneg) {
1232 /*
1233 * If speed and duplex are forced to 10H or 10F, then we will
1234 * implement the polarity reversal workaround. We disable
1235 * interrupts first, and upon returning, place the devices
1236 * interrupt state to its previous value except for the link
1237 * status change interrupt which will happened due to the
1238 * execution of this workaround.
1239 */
1240 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1241 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1242 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1243 icr = E1000_READ_REG(hw, E1000_ICR);
1244 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1245 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1246 }
1247
1248 ret_val = -E1000_ERR_CONFIG;
1249 goto out;
1250 }
1251
1252 /*
1253 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1254 * have Si on board that is 82544 or newer, Auto
1255 * Speed Detection takes care of MAC speed/duplex
1256 * configuration. So we only need to configure Collision
1257 * Distance in the MAC. Otherwise, we need to force
1258 * speed/duplex on the MAC to the current PHY speed/duplex
1259 * settings.
1260 */
1261 if (mac->type == e1000_82544)
1262 hw->mac.ops.config_collision_dist(hw);
1263 else {
1264 ret_val = e1000_config_mac_to_phy_82543(hw);
1265 if (ret_val) {
1266 DEBUGOUT("Error configuring MAC to PHY settings\n");
1267 goto out;
1268 }
1269 }
1270
1271 /*
1272 * Configure Flow Control now that Auto-Neg has completed.
1273 * First, we need to restore the desired flow control
1274 * settings because we may have had to re-autoneg with a
1275 * different link partner.
1276 */
1277 ret_val = e1000_config_fc_after_link_up_generic(hw);
1278 if (ret_val) {
1279 DEBUGOUT("Error configuring flow control\n");
1280 }
1281
1282 /*
1283 * At this point we know that we are on copper and we have
1284 * auto-negotiated link. These are conditions for checking the link
1285 * partner capability register. We use the link speed to determine if
1286 * TBI compatibility needs to be turned on or off. If the link is not
1287 * at gigabit speed, then TBI compatibility is not needed. If we are
1288 * at gigabit speed, we turn on TBI compatibility.
1289 */
1290 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1291 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1292 if (ret_val) {
1293 DEBUGOUT("Error getting link speed and duplex\n");
1294 return ret_val;
1295 }
1296 if (speed != SPEED_1000) {
1297 /*
1298 * If link speed is not set to gigabit speed,
1299 * we do not need to enable TBI compatibility.
1300 */
1301 if (e1000_tbi_sbp_enabled_82543(hw)) {
1302 /*
1303 * If we previously were in the mode,
1304 * turn it off.
1305 */
1306 e1000_set_tbi_sbp_82543(hw, FALSE);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1308 rctl &= ~E1000_RCTL_SBP;
1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 }
1311 } else {
1312 /*
1313 * If TBI compatibility is was previously off,
1314 * turn it on. For compatibility with a TBI link
1315 * partner, we will store bad packets. Some
1316 * frames have an additional byte on the end and
1317 * will look like CRC errors to to the hardware.
1318 */
1319 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1320 e1000_set_tbi_sbp_82543(hw, TRUE);
1321 rctl = E1000_READ_REG(hw, E1000_RCTL);
1322 rctl |= E1000_RCTL_SBP;
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324 }
1325 }
1326 }
1327out:
1328 return ret_val;
1329}
1330
1331/**
1332 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1333 * @hw: pointer to the HW structure
1334 *
1335 * Checks for link up on the hardware. If link is not up and we have
1336 * a signal, then we need to force link up.
1337 **/
1338static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1339{
1340 struct e1000_mac_info *mac = &hw->mac;
1341 u32 rxcw, ctrl, status;
1342 s32 ret_val = E1000_SUCCESS;
1343
1344 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1345
1346 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1347 status = E1000_READ_REG(hw, E1000_STATUS);
1348 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1349
1350 /*
1351 * If we don't have link (auto-negotiation failed or link partner
1352 * cannot auto-negotiate), the cable is plugged in (we have signal),
1353 * and our link partner is not trying to auto-negotiate with us (we
1354 * are receiving idles or data), we need to force link up. We also
1355 * need to give auto-negotiation time to complete, in case the cable
1356 * was just plugged in. The autoneg_failed flag does this.
1357 */
1358 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1359 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1360 (!(status & E1000_STATUS_LU)) &&
1361 (!(rxcw & E1000_RXCW_C))) {
1362 if (mac->autoneg_failed == 0) {
1363 mac->autoneg_failed = 1;
1364 ret_val = 0;
1365 goto out;
1366 }
1367 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1368
1369 /* Disable auto-negotiation in the TXCW register */
1370 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1371
1372 /* Force link-up and also force full-duplex. */
1373 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1374 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1375 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1376
1377 /* Configure Flow Control after forcing link up. */
1378 ret_val = e1000_config_fc_after_link_up_generic(hw);
1379 if (ret_val) {
1380 DEBUGOUT("Error configuring flow control\n");
1381 goto out;
1382 }
1383 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1384 /*
1385 * If we are forcing link and we are receiving /C/ ordered
1386 * sets, re-enable auto-negotiation in the TXCW register
1387 * and disable forced link in the Device Control register
1388 * in an attempt to auto-negotiate with our link partner.
1389 */
1390 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1391 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1392 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1393
1394 mac->serdes_has_link = TRUE;
1395 }
1396
1397out:
1398 return ret_val;
1399}
1400
1401/**
1402 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1403 * @hw: pointer to the HW structure
1404 *
1405 * For the 82543 silicon, we need to set the MAC to match the settings
1406 * of the PHY, even if the PHY is auto-negotiating.
1407 **/
1408static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1409{
1410 u32 ctrl;
1411 s32 ret_val = E1000_SUCCESS;
1412 u16 phy_data;
1413
1414 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1415
1416 if (!(hw->phy.ops.read_reg))
1417 goto out;
1418
1419 /* Set the bits to force speed and duplex */
1420 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1421 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1422 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1423
1424 /*
1425 * Set up duplex in the Device Control and Transmit Control
1426 * registers depending on negotiated values.
1427 */
1428 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1429 if (ret_val)
1430 goto out;
1431
1432 ctrl &= ~E1000_CTRL_FD;
1433 if (phy_data & M88E1000_PSSR_DPLX)
1434 ctrl |= E1000_CTRL_FD;
1435
1436 hw->mac.ops.config_collision_dist(hw);
1437
1438 /*
1439 * Set up speed in the Device Control register depending on
1440 * negotiated values.
1441 */
1442 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1443 ctrl |= E1000_CTRL_SPD_1000;
1444 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1445 ctrl |= E1000_CTRL_SPD_100;
1446
1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1448
1449out:
1450 return ret_val;
1451}
1452
1453/**
1454 * e1000_write_vfta_82543 - Write value to VLAN filter table
1455 * @hw: pointer to the HW structure
1456 * @offset: the 32-bit offset in which to write the value to.
1457 * @value: the 32-bit value to write at location offset.
1458 *
1459 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1460 * table.
1461 **/
1462static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1463{
1464 u32 temp;
1465
1466 DEBUGFUNC("e1000_write_vfta_82543");
1467
1468 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1469 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1470 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1471 E1000_WRITE_FLUSH(hw);
1472 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1473 E1000_WRITE_FLUSH(hw);
1474 } else {
1475 e1000_write_vfta_generic(hw, offset, value);
1476 }
1477}
1478
1479/**
1480 * e1000_led_on_82543 - Turn on SW controllable LED
1481 * @hw: pointer to the HW structure
1482 *
1483 * Turns the SW defined LED on.
1484 **/
1485static s32 e1000_led_on_82543(struct e1000_hw *hw)
1486{
1487 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1488
1489 DEBUGFUNC("e1000_led_on_82543");
1490
1491 if (hw->mac.type == e1000_82544 &&
1492 hw->phy.media_type == e1000_media_type_copper) {
1493 /* Clear SW-definable Pin 0 to turn on the LED */
1494 ctrl &= ~E1000_CTRL_SWDPIN0;
1495 ctrl |= E1000_CTRL_SWDPIO0;
1496 } else {
1497 /* Fiber 82544 and all 82543 use this method */
1498 ctrl |= E1000_CTRL_SWDPIN0;
1499 ctrl |= E1000_CTRL_SWDPIO0;
1500 }
1501 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1502
1503 return E1000_SUCCESS;
1504}
1505
1506/**
1507 * e1000_led_off_82543 - Turn off SW controllable LED
1508 * @hw: pointer to the HW structure
1509 *
1510 * Turns the SW defined LED off.
1511 **/
1512static s32 e1000_led_off_82543(struct e1000_hw *hw)
1513{
1514 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1515
1516 DEBUGFUNC("e1000_led_off_82543");
1517
1518 if (hw->mac.type == e1000_82544 &&
1519 hw->phy.media_type == e1000_media_type_copper) {
1520 /* Set SW-definable Pin 0 to turn off the LED */
1521 ctrl |= E1000_CTRL_SWDPIN0;
1522 ctrl |= E1000_CTRL_SWDPIO0;
1523 } else {
1524 ctrl &= ~E1000_CTRL_SWDPIN0;
1525 ctrl |= E1000_CTRL_SWDPIO0;
1526 }
1527 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1528
1529 return E1000_SUCCESS;
1530}
1531
1532/**
1533 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1534 * @hw: pointer to the HW structure
1535 *
1536 * Clears the hardware counters by reading the counter registers.
1537 **/
1538static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1539{
1540 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1541
1542 e1000_clear_hw_cntrs_base_generic(hw);
1543
1544 E1000_READ_REG(hw, E1000_PRC64);
1545 E1000_READ_REG(hw, E1000_PRC127);
1546 E1000_READ_REG(hw, E1000_PRC255);
1547 E1000_READ_REG(hw, E1000_PRC511);
1548 E1000_READ_REG(hw, E1000_PRC1023);
1549 E1000_READ_REG(hw, E1000_PRC1522);
1550 E1000_READ_REG(hw, E1000_PTC64);
1551 E1000_READ_REG(hw, E1000_PTC127);
1552 E1000_READ_REG(hw, E1000_PTC255);
1553 E1000_READ_REG(hw, E1000_PTC511);
1554 E1000_READ_REG(hw, E1000_PTC1023);
1555 E1000_READ_REG(hw, E1000_PTC1522);
1556
1557 E1000_READ_REG(hw, E1000_ALGNERRC);
1558 E1000_READ_REG(hw, E1000_RXERRC);
1559 E1000_READ_REG(hw, E1000_TNCRS);
1560 E1000_READ_REG(hw, E1000_CEXTERR);
1561 E1000_READ_REG(hw, E1000_TSCTC);
1562 E1000_READ_REG(hw, E1000_TSCTFC);
1563}
1564
1565/**
1566 * e1000_read_mac_addr_82543 - Read device MAC address
1567 * @hw: pointer to the HW structure
1568 *
1569 * Reads the device MAC address from the EEPROM and stores the value.
1570 * Since devices with two ports use the same EEPROM, we increment the
1571 * last bit in the MAC address for the second port.
1572 *
1573 **/
1574s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1575{
1576 s32 ret_val = E1000_SUCCESS;
1577 u16 offset, nvm_data, i;
1578
1579 DEBUGFUNC("e1000_read_mac_addr");
1580
1581 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1582 offset = i >> 1;
1583 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1584 if (ret_val) {
1585 DEBUGOUT("NVM Read Error\n");
1586 goto out;
1587 }
1588 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1589 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1590 }
1591
1592 /* Flip last bit of mac address if we're on second port */
1593 if (hw->bus.func == E1000_FUNC_1)
1594 hw->mac.perm_addr[5] ^= 1;
1595
1596 for (i = 0; i < ETH_ADDR_LEN; i++)
1597 hw->mac.addr[i] = hw->mac.perm_addr[i];
1598
1599out:
1600 return ret_val;
1601}
2
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82543.c 238148 2012-07-05 20:26:57Z jfv $*/
34
35/*
36 * 82543GC Gigabit Ethernet Controller (Fiber)
37 * 82543GC Gigabit Ethernet Controller (Copper)
38 * 82544EI Gigabit Ethernet Controller (Copper)
39 * 82544EI Gigabit Ethernet Controller (Fiber)
40 * 82544GC Gigabit Ethernet Controller (Copper)
41 * 82544GC Gigabit Ethernet Controller (LOM)
42 */
43
44#include "e1000_api.h"
45
46static s32 e1000_init_phy_params_82543(struct e1000_hw *hw);
47static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw);
48static s32 e1000_init_mac_params_82543(struct e1000_hw *hw);
49static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset,
50 u16 *data);
51static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset,
52 u16 data);
53static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw);
54static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw);
55static s32 e1000_reset_hw_82543(struct e1000_hw *hw);
56static s32 e1000_init_hw_82543(struct e1000_hw *hw);
57static s32 e1000_setup_link_82543(struct e1000_hw *hw);
58static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw);
59static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw);
60static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw);
61static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw);
62static s32 e1000_led_on_82543(struct e1000_hw *hw);
63static s32 e1000_led_off_82543(struct e1000_hw *hw);
64static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset,
65 u32 value);
66static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw);
67static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw);
68static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw);
69static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
70static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw);
71static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl);
72static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw);
73static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
74 u16 count);
75static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw);
76static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state);
77static s32 e1000_read_mac_addr_82543(struct e1000_hw *hw);
78
79
80/**
81 * e1000_init_phy_params_82543 - Init PHY func ptrs.
82 * @hw: pointer to the HW structure
83 **/
84static s32 e1000_init_phy_params_82543(struct e1000_hw *hw)
85{
86 struct e1000_phy_info *phy = &hw->phy;
87 s32 ret_val = E1000_SUCCESS;
88
89 DEBUGFUNC("e1000_init_phy_params_82543");
90
91 if (hw->phy.media_type != e1000_media_type_copper) {
92 phy->type = e1000_phy_none;
93 goto out;
94 } else {
95 phy->ops.power_up = e1000_power_up_phy_copper;
96 phy->ops.power_down = e1000_power_down_phy_copper;
97 }
98
99 phy->addr = 1;
100 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
101 phy->reset_delay_us = 10000;
102 phy->type = e1000_phy_m88;
103
104 /* Function Pointers */
105 phy->ops.check_polarity = e1000_check_polarity_m88;
106 phy->ops.commit = e1000_phy_sw_reset_generic;
107 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_82543;
108 phy->ops.get_cable_length = e1000_get_cable_length_m88;
109 phy->ops.get_cfg_done = e1000_get_cfg_done_generic;
110 phy->ops.read_reg = (hw->mac.type == e1000_82543)
111 ? e1000_read_phy_reg_82543
112 : e1000_read_phy_reg_m88;
113 phy->ops.reset = (hw->mac.type == e1000_82543)
114 ? e1000_phy_hw_reset_82543
115 : e1000_phy_hw_reset_generic;
116 phy->ops.write_reg = (hw->mac.type == e1000_82543)
117 ? e1000_write_phy_reg_82543
118 : e1000_write_phy_reg_m88;
119 phy->ops.get_info = e1000_get_phy_info_m88;
120
121 /*
122 * The external PHY of the 82543 can be in a funky state.
123 * Resetting helps us read the PHY registers for acquiring
124 * the PHY ID.
125 */
126 if (!e1000_init_phy_disabled_82543(hw)) {
127 ret_val = phy->ops.reset(hw);
128 if (ret_val) {
129 DEBUGOUT("Resetting PHY during init failed.\n");
130 goto out;
131 }
132 msec_delay(20);
133 }
134
135 ret_val = e1000_get_phy_id(hw);
136 if (ret_val)
137 goto out;
138
139 /* Verify phy id */
140 switch (hw->mac.type) {
141 case e1000_82543:
142 if (phy->id != M88E1000_E_PHY_ID) {
143 ret_val = -E1000_ERR_PHY;
144 goto out;
145 }
146 break;
147 case e1000_82544:
148 if (phy->id != M88E1000_I_PHY_ID) {
149 ret_val = -E1000_ERR_PHY;
150 goto out;
151 }
152 break;
153 default:
154 ret_val = -E1000_ERR_PHY;
155 goto out;
156 break;
157 }
158
159out:
160 return ret_val;
161}
162
163/**
164 * e1000_init_nvm_params_82543 - Init NVM func ptrs.
165 * @hw: pointer to the HW structure
166 **/
167static s32 e1000_init_nvm_params_82543(struct e1000_hw *hw)
168{
169 struct e1000_nvm_info *nvm = &hw->nvm;
170
171 DEBUGFUNC("e1000_init_nvm_params_82543");
172
173 nvm->type = e1000_nvm_eeprom_microwire;
174 nvm->word_size = 64;
175 nvm->delay_usec = 50;
176 nvm->address_bits = 6;
177 nvm->opcode_bits = 3;
178
179 /* Function Pointers */
180 nvm->ops.read = e1000_read_nvm_microwire;
181 nvm->ops.update = e1000_update_nvm_checksum_generic;
182 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
183 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
184 nvm->ops.write = e1000_write_nvm_microwire;
185
186 return E1000_SUCCESS;
187}
188
189/**
190 * e1000_init_mac_params_82543 - Init MAC func ptrs.
191 * @hw: pointer to the HW structure
192 **/
193static s32 e1000_init_mac_params_82543(struct e1000_hw *hw)
194{
195 struct e1000_mac_info *mac = &hw->mac;
196
197 DEBUGFUNC("e1000_init_mac_params_82543");
198
199 /* Set media type */
200 switch (hw->device_id) {
201 case E1000_DEV_ID_82543GC_FIBER:
202 case E1000_DEV_ID_82544EI_FIBER:
203 hw->phy.media_type = e1000_media_type_fiber;
204 break;
205 default:
206 hw->phy.media_type = e1000_media_type_copper;
207 break;
208 }
209
210 /* Set mta register count */
211 mac->mta_reg_count = 128;
212 /* Set rar entry count */
213 mac->rar_entry_count = E1000_RAR_ENTRIES;
214
215 /* Function pointers */
216
217 /* bus type/speed/width */
218 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic;
219 /* function id */
220 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
221 /* reset */
222 mac->ops.reset_hw = e1000_reset_hw_82543;
223 /* hw initialization */
224 mac->ops.init_hw = e1000_init_hw_82543;
225 /* link setup */
226 mac->ops.setup_link = e1000_setup_link_82543;
227 /* physical interface setup */
228 mac->ops.setup_physical_interface =
229 (hw->phy.media_type == e1000_media_type_copper)
230 ? e1000_setup_copper_link_82543
231 : e1000_setup_fiber_link_82543;
232 /* check for link */
233 mac->ops.check_for_link =
234 (hw->phy.media_type == e1000_media_type_copper)
235 ? e1000_check_for_copper_link_82543
236 : e1000_check_for_fiber_link_82543;
237 /* link info */
238 mac->ops.get_link_up_info =
239 (hw->phy.media_type == e1000_media_type_copper)
240 ? e1000_get_speed_and_duplex_copper_generic
241 : e1000_get_speed_and_duplex_fiber_serdes_generic;
242 /* multicast address update */
243 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
244 /* writing VFTA */
245 mac->ops.write_vfta = e1000_write_vfta_82543;
246 /* clearing VFTA */
247 mac->ops.clear_vfta = e1000_clear_vfta_generic;
248 /* read mac address */
249 mac->ops.read_mac_addr = e1000_read_mac_addr_82543;
250 /* turn on/off LED */
251 mac->ops.led_on = e1000_led_on_82543;
252 mac->ops.led_off = e1000_led_off_82543;
253 /* clear hardware counters */
254 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82543;
255
256 /* Set tbi compatibility */
257 if ((hw->mac.type != e1000_82543) ||
258 (hw->phy.media_type == e1000_media_type_fiber))
259 e1000_set_tbi_compatibility_82543(hw, FALSE);
260
261 return E1000_SUCCESS;
262}
263
264/**
265 * e1000_init_function_pointers_82543 - Init func ptrs.
266 * @hw: pointer to the HW structure
267 *
268 * Called to initialize all function pointers and parameters.
269 **/
270void e1000_init_function_pointers_82543(struct e1000_hw *hw)
271{
272 DEBUGFUNC("e1000_init_function_pointers_82543");
273
274 hw->mac.ops.init_params = e1000_init_mac_params_82543;
275 hw->nvm.ops.init_params = e1000_init_nvm_params_82543;
276 hw->phy.ops.init_params = e1000_init_phy_params_82543;
277}
278
279/**
280 * e1000_tbi_compatibility_enabled_82543 - Returns TBI compat status
281 * @hw: pointer to the HW structure
282 *
283 * Returns the current status of 10-bit Interface (TBI) compatibility
284 * (enabled/disabled).
285 **/
286static bool e1000_tbi_compatibility_enabled_82543(struct e1000_hw *hw)
287{
288 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
289 bool state = FALSE;
290
291 DEBUGFUNC("e1000_tbi_compatibility_enabled_82543");
292
293 if (hw->mac.type != e1000_82543) {
294 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
295 goto out;
296 }
297
298 state = (dev_spec->tbi_compatibility & TBI_COMPAT_ENABLED)
299 ? TRUE : FALSE;
300
301out:
302 return state;
303}
304
305/**
306 * e1000_set_tbi_compatibility_82543 - Set TBI compatibility
307 * @hw: pointer to the HW structure
308 * @state: enable/disable TBI compatibility
309 *
310 * Enables or disabled 10-bit Interface (TBI) compatibility.
311 **/
312void e1000_set_tbi_compatibility_82543(struct e1000_hw *hw, bool state)
313{
314 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
315
316 DEBUGFUNC("e1000_set_tbi_compatibility_82543");
317
318 if (hw->mac.type != e1000_82543) {
319 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
320 goto out;
321 }
322
323 if (state)
324 dev_spec->tbi_compatibility |= TBI_COMPAT_ENABLED;
325 else
326 dev_spec->tbi_compatibility &= ~TBI_COMPAT_ENABLED;
327
328out:
329 return;
330}
331
332/**
333 * e1000_tbi_sbp_enabled_82543 - Returns TBI SBP status
334 * @hw: pointer to the HW structure
335 *
336 * Returns the current status of 10-bit Interface (TBI) store bad packet (SBP)
337 * (enabled/disabled).
338 **/
339bool e1000_tbi_sbp_enabled_82543(struct e1000_hw *hw)
340{
341 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
342 bool state = FALSE;
343
344 DEBUGFUNC("e1000_tbi_sbp_enabled_82543");
345
346 if (hw->mac.type != e1000_82543) {
347 DEBUGOUT("TBI compatibility workaround for 82543 only.\n");
348 goto out;
349 }
350
351 state = (dev_spec->tbi_compatibility & TBI_SBP_ENABLED)
352 ? TRUE : FALSE;
353
354out:
355 return state;
356}
357
358/**
359 * e1000_set_tbi_sbp_82543 - Set TBI SBP
360 * @hw: pointer to the HW structure
361 * @state: enable/disable TBI store bad packet
362 *
363 * Enables or disabled 10-bit Interface (TBI) store bad packet (SBP).
364 **/
365static void e1000_set_tbi_sbp_82543(struct e1000_hw *hw, bool state)
366{
367 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
368
369 DEBUGFUNC("e1000_set_tbi_sbp_82543");
370
371 if (state && e1000_tbi_compatibility_enabled_82543(hw))
372 dev_spec->tbi_compatibility |= TBI_SBP_ENABLED;
373 else
374 dev_spec->tbi_compatibility &= ~TBI_SBP_ENABLED;
375
376 return;
377}
378
379/**
380 * e1000_init_phy_disabled_82543 - Returns init PHY status
381 * @hw: pointer to the HW structure
382 *
383 * Returns the current status of whether PHY initialization is disabled.
384 * True if PHY initialization is disabled else FALSE.
385 **/
386static bool e1000_init_phy_disabled_82543(struct e1000_hw *hw)
387{
388 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
389 bool ret_val;
390
391 DEBUGFUNC("e1000_init_phy_disabled_82543");
392
393 if (hw->mac.type != e1000_82543) {
394 ret_val = FALSE;
395 goto out;
396 }
397
398 ret_val = dev_spec->init_phy_disabled;
399
400out:
401 return ret_val;
402}
403
404/**
405 * e1000_tbi_adjust_stats_82543 - Adjust stats when TBI enabled
406 * @hw: pointer to the HW structure
407 * @stats: Struct containing statistic register values
408 * @frame_len: The length of the frame in question
409 * @mac_addr: The Ethernet destination address of the frame in question
410 * @max_frame_size: The maximum frame size
411 *
412 * Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
413 **/
414void e1000_tbi_adjust_stats_82543(struct e1000_hw *hw,
415 struct e1000_hw_stats *stats, u32 frame_len,
416 u8 *mac_addr, u32 max_frame_size)
417{
418 if (!(e1000_tbi_sbp_enabled_82543(hw)))
419 goto out;
420
421 /* First adjust the frame length. */
422 frame_len--;
423 /*
424 * We need to adjust the statistics counters, since the hardware
425 * counters overcount this packet as a CRC error and undercount
426 * the packet as a good packet
427 */
428 /* This packet should not be counted as a CRC error. */
429 stats->crcerrs--;
430 /* This packet does count as a Good Packet Received. */
431 stats->gprc++;
432
433 /* Adjust the Good Octets received counters */
434 stats->gorc += frame_len;
435
436 /*
437 * Is this a broadcast or multicast? Check broadcast first,
438 * since the test for a multicast frame will test positive on
439 * a broadcast frame.
440 */
441 if ((mac_addr[0] == 0xff) && (mac_addr[1] == 0xff))
442 /* Broadcast packet */
443 stats->bprc++;
444 else if (*mac_addr & 0x01)
445 /* Multicast packet */
446 stats->mprc++;
447
448 /*
449 * In this case, the hardware has overcounted the number of
450 * oversize frames.
451 */
452 if ((frame_len == max_frame_size) && (stats->roc > 0))
453 stats->roc--;
454
455 /*
456 * Adjust the bin counters when the extra byte put the frame in the
457 * wrong bin. Remember that the frame_len was adjusted above.
458 */
459 if (frame_len == 64) {
460 stats->prc64++;
461 stats->prc127--;
462 } else if (frame_len == 127) {
463 stats->prc127++;
464 stats->prc255--;
465 } else if (frame_len == 255) {
466 stats->prc255++;
467 stats->prc511--;
468 } else if (frame_len == 511) {
469 stats->prc511++;
470 stats->prc1023--;
471 } else if (frame_len == 1023) {
472 stats->prc1023++;
473 stats->prc1522--;
474 } else if (frame_len == 1522) {
475 stats->prc1522++;
476 }
477
478out:
479 return;
480}
481
482/**
483 * e1000_read_phy_reg_82543 - Read PHY register
484 * @hw: pointer to the HW structure
485 * @offset: register offset to be read
486 * @data: pointer to the read data
487 *
488 * Reads the PHY at offset and stores the information read to data.
489 **/
490static s32 e1000_read_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 *data)
491{
492 u32 mdic;
493 s32 ret_val = E1000_SUCCESS;
494
495 DEBUGFUNC("e1000_read_phy_reg_82543");
496
497 if (offset > MAX_PHY_REG_ADDRESS) {
498 DEBUGOUT1("PHY Address %d is out of range\n", offset);
499 ret_val = -E1000_ERR_PARAM;
500 goto out;
501 }
502
503 /*
504 * We must first send a preamble through the MDIO pin to signal the
505 * beginning of an MII instruction. This is done by sending 32
506 * consecutive "1" bits.
507 */
508 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
509
510 /*
511 * Now combine the next few fields that are required for a read
512 * operation. We use this method instead of calling the
513 * e1000_shift_out_mdi_bits routine five different times. The format
514 * of an MII read instruction consists of a shift out of 14 bits and
515 * is defined as follows:
516 * <Preamble><SOF><Op Code><Phy Addr><Offset>
517 * followed by a shift in of 18 bits. This first two bits shifted in
518 * are TurnAround bits used to avoid contention on the MDIO pin when a
519 * READ operation is performed. These two bits are thrown away
520 * followed by a shift in of 16 bits which contains the desired data.
521 */
522 mdic = (offset | (hw->phy.addr << 5) |
523 (PHY_OP_READ << 10) | (PHY_SOF << 12));
524
525 e1000_shift_out_mdi_bits_82543(hw, mdic, 14);
526
527 /*
528 * Now that we've shifted out the read command to the MII, we need to
529 * "shift in" the 16-bit value (18 total bits) of the requested PHY
530 * register address.
531 */
532 *data = e1000_shift_in_mdi_bits_82543(hw);
533
534out:
535 return ret_val;
536}
537
538/**
539 * e1000_write_phy_reg_82543 - Write PHY register
540 * @hw: pointer to the HW structure
541 * @offset: register offset to be written
542 * @data: pointer to the data to be written at offset
543 *
544 * Writes data to the PHY at offset.
545 **/
546static s32 e1000_write_phy_reg_82543(struct e1000_hw *hw, u32 offset, u16 data)
547{
548 u32 mdic;
549 s32 ret_val = E1000_SUCCESS;
550
551 DEBUGFUNC("e1000_write_phy_reg_82543");
552
553 if (offset > MAX_PHY_REG_ADDRESS) {
554 DEBUGOUT1("PHY Address %d is out of range\n", offset);
555 ret_val = -E1000_ERR_PARAM;
556 goto out;
557 }
558
559 /*
560 * We'll need to use the SW defined pins to shift the write command
561 * out to the PHY. We first send a preamble to the PHY to signal the
562 * beginning of the MII instruction. This is done by sending 32
563 * consecutive "1" bits.
564 */
565 e1000_shift_out_mdi_bits_82543(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
566
567 /*
568 * Now combine the remaining required fields that will indicate a
569 * write operation. We use this method instead of calling the
570 * e1000_shift_out_mdi_bits routine for each field in the command. The
571 * format of a MII write instruction is as follows:
572 * <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
573 */
574 mdic = ((PHY_TURNAROUND) | (offset << 2) | (hw->phy.addr << 7) |
575 (PHY_OP_WRITE << 12) | (PHY_SOF << 14));
576 mdic <<= 16;
577 mdic |= (u32) data;
578
579 e1000_shift_out_mdi_bits_82543(hw, mdic, 32);
580
581out:
582 return ret_val;
583}
584
585/**
586 * e1000_raise_mdi_clk_82543 - Raise Management Data Input clock
587 * @hw: pointer to the HW structure
588 * @ctrl: pointer to the control register
589 *
590 * Raise the management data input clock by setting the MDC bit in the control
591 * register.
592 **/
593static void e1000_raise_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
594{
595 /*
596 * Raise the clock input to the Management Data Clock (by setting the
597 * MDC bit), and then delay a sufficient amount of time.
598 */
599 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl | E1000_CTRL_MDC));
600 E1000_WRITE_FLUSH(hw);
601 usec_delay(10);
602}
603
604/**
605 * e1000_lower_mdi_clk_82543 - Lower Management Data Input clock
606 * @hw: pointer to the HW structure
607 * @ctrl: pointer to the control register
608 *
609 * Lower the management data input clock by clearing the MDC bit in the
610 * control register.
611 **/
612static void e1000_lower_mdi_clk_82543(struct e1000_hw *hw, u32 *ctrl)
613{
614 /*
615 * Lower the clock input to the Management Data Clock (by clearing the
616 * MDC bit), and then delay a sufficient amount of time.
617 */
618 E1000_WRITE_REG(hw, E1000_CTRL, (*ctrl & ~E1000_CTRL_MDC));
619 E1000_WRITE_FLUSH(hw);
620 usec_delay(10);
621}
622
623/**
624 * e1000_shift_out_mdi_bits_82543 - Shift data bits our to the PHY
625 * @hw: pointer to the HW structure
626 * @data: data to send to the PHY
627 * @count: number of bits to shift out
628 *
629 * We need to shift 'count' bits out to the PHY. So, the value in the
630 * "data" parameter will be shifted out to the PHY one bit at a time.
631 * In order to do this, "data" must be broken down into bits.
632 **/
633static void e1000_shift_out_mdi_bits_82543(struct e1000_hw *hw, u32 data,
634 u16 count)
635{
636 u32 ctrl, mask;
637
638 /*
639 * We need to shift "count" number of bits out to the PHY. So, the
640 * value in the "data" parameter will be shifted out to the PHY one
641 * bit at a time. In order to do this, "data" must be broken down
642 * into bits.
643 */
644 mask = 0x01;
645 mask <<= (count -1);
646
647 ctrl = E1000_READ_REG(hw, E1000_CTRL);
648
649 /* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
650 ctrl |= (E1000_CTRL_MDIO_DIR | E1000_CTRL_MDC_DIR);
651
652 while (mask) {
653 /*
654 * A "1" is shifted out to the PHY by setting the MDIO bit to
655 * "1" and then raising and lowering the Management Data Clock.
656 * A "0" is shifted out to the PHY by setting the MDIO bit to
657 * "0" and then raising and lowering the clock.
658 */
659 if (data & mask) ctrl |= E1000_CTRL_MDIO;
660 else ctrl &= ~E1000_CTRL_MDIO;
661
662 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
663 E1000_WRITE_FLUSH(hw);
664
665 usec_delay(10);
666
667 e1000_raise_mdi_clk_82543(hw, &ctrl);
668 e1000_lower_mdi_clk_82543(hw, &ctrl);
669
670 mask >>= 1;
671 }
672}
673
674/**
675 * e1000_shift_in_mdi_bits_82543 - Shift data bits in from the PHY
676 * @hw: pointer to the HW structure
677 *
678 * In order to read a register from the PHY, we need to shift 18 bits
679 * in from the PHY. Bits are "shifted in" by raising the clock input to
680 * the PHY (setting the MDC bit), and then reading the value of the data out
681 * MDIO bit.
682 **/
683static u16 e1000_shift_in_mdi_bits_82543(struct e1000_hw *hw)
684{
685 u32 ctrl;
686 u16 data = 0;
687 u8 i;
688
689 /*
690 * In order to read a register from the PHY, we need to shift in a
691 * total of 18 bits from the PHY. The first two bit (turnaround)
692 * times are used to avoid contention on the MDIO pin when a read
693 * operation is performed. These two bits are ignored by us and
694 * thrown away. Bits are "shifted in" by raising the input to the
695 * Management Data Clock (setting the MDC bit) and then reading the
696 * value of the MDIO bit.
697 */
698 ctrl = E1000_READ_REG(hw, E1000_CTRL);
699
700 /*
701 * Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as
702 * input.
703 */
704 ctrl &= ~E1000_CTRL_MDIO_DIR;
705 ctrl &= ~E1000_CTRL_MDIO;
706
707 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
708 E1000_WRITE_FLUSH(hw);
709
710 /*
711 * Raise and lower the clock before reading in the data. This accounts
712 * for the turnaround bits. The first clock occurred when we clocked
713 * out the last bit of the Register Address.
714 */
715 e1000_raise_mdi_clk_82543(hw, &ctrl);
716 e1000_lower_mdi_clk_82543(hw, &ctrl);
717
718 for (data = 0, i = 0; i < 16; i++) {
719 data <<= 1;
720 e1000_raise_mdi_clk_82543(hw, &ctrl);
721 ctrl = E1000_READ_REG(hw, E1000_CTRL);
722 /* Check to see if we shifted in a "1". */
723 if (ctrl & E1000_CTRL_MDIO)
724 data |= 1;
725 e1000_lower_mdi_clk_82543(hw, &ctrl);
726 }
727
728 e1000_raise_mdi_clk_82543(hw, &ctrl);
729 e1000_lower_mdi_clk_82543(hw, &ctrl);
730
731 return data;
732}
733
734/**
735 * e1000_phy_force_speed_duplex_82543 - Force speed/duplex for PHY
736 * @hw: pointer to the HW structure
737 *
738 * Calls the function to force speed and duplex for the m88 PHY, and
739 * if the PHY is not auto-negotiating and the speed is forced to 10Mbit,
740 * then call the function for polarity reversal workaround.
741 **/
742static s32 e1000_phy_force_speed_duplex_82543(struct e1000_hw *hw)
743{
744 s32 ret_val;
745
746 DEBUGFUNC("e1000_phy_force_speed_duplex_82543");
747
748 ret_val = e1000_phy_force_speed_duplex_m88(hw);
749 if (ret_val)
750 goto out;
751
752 if (!hw->mac.autoneg &&
753 (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED))
754 ret_val = e1000_polarity_reversal_workaround_82543(hw);
755
756out:
757 return ret_val;
758}
759
760/**
761 * e1000_polarity_reversal_workaround_82543 - Workaround polarity reversal
762 * @hw: pointer to the HW structure
763 *
764 * When forcing link to 10 Full or 10 Half, the PHY can reverse the polarity
765 * inadvertently. To workaround the issue, we disable the transmitter on
766 * the PHY until we have established the link partner's link parameters.
767 **/
768static s32 e1000_polarity_reversal_workaround_82543(struct e1000_hw *hw)
769{
770 s32 ret_val = E1000_SUCCESS;
771 u16 mii_status_reg;
772 u16 i;
773 bool link;
774
775 if (!(hw->phy.ops.write_reg))
776 goto out;
777
778 /* Polarity reversal workaround for forced 10F/10H links. */
779
780 /* Disable the transmitter on the PHY */
781
782 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
783 if (ret_val)
784 goto out;
785 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
786 if (ret_val)
787 goto out;
788
789 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
790 if (ret_val)
791 goto out;
792
793 /*
794 * This loop will early-out if the NO link condition has been met.
795 * In other words, DO NOT use e1000_phy_has_link_generic() here.
796 */
797 for (i = PHY_FORCE_TIME; i > 0; i--) {
798 /*
799 * Read the MII Status Register and wait for Link Status bit
800 * to be clear.
801 */
802
803 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
804 if (ret_val)
805 goto out;
806
807 ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS, &mii_status_reg);
808 if (ret_val)
809 goto out;
810
811 if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0)
812 break;
813 msec_delay_irq(100);
814 }
815
816 /* Recommended delay time after link has been lost */
817 msec_delay_irq(1000);
818
819 /* Now we will re-enable the transmitter on the PHY */
820
821 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
822 if (ret_val)
823 goto out;
824 msec_delay_irq(50);
825 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
826 if (ret_val)
827 goto out;
828 msec_delay_irq(50);
829 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
830 if (ret_val)
831 goto out;
832 msec_delay_irq(50);
833 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
834 if (ret_val)
835 goto out;
836
837 ret_val = hw->phy.ops.write_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
838 if (ret_val)
839 goto out;
840
841 /*
842 * Read the MII Status Register and wait for Link Status bit
843 * to be set.
844 */
845 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_TIME, 100000, &link);
846 if (ret_val)
847 goto out;
848
849out:
850 return ret_val;
851}
852
853/**
854 * e1000_phy_hw_reset_82543 - PHY hardware reset
855 * @hw: pointer to the HW structure
856 *
857 * Sets the PHY_RESET_DIR bit in the extended device control register
858 * to put the PHY into a reset and waits for completion. Once the reset
859 * has been accomplished, clear the PHY_RESET_DIR bit to take the PHY out
860 * of reset.
861 **/
862static s32 e1000_phy_hw_reset_82543(struct e1000_hw *hw)
863{
864 u32 ctrl_ext;
865 s32 ret_val;
866
867 DEBUGFUNC("e1000_phy_hw_reset_82543");
868
869 /*
870 * Read the Extended Device Control Register, assert the PHY_RESET_DIR
871 * bit to put the PHY into reset...
872 */
873 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
874 ctrl_ext |= E1000_CTRL_EXT_SDP4_DIR;
875 ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
876 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
877 E1000_WRITE_FLUSH(hw);
878
879 msec_delay(10);
880
881 /* ...then take it out of reset. */
882 ctrl_ext |= E1000_CTRL_EXT_SDP4_DATA;
883 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
884 E1000_WRITE_FLUSH(hw);
885
886 usec_delay(150);
887
888 if (!(hw->phy.ops.get_cfg_done))
889 return E1000_SUCCESS;
890
891 ret_val = hw->phy.ops.get_cfg_done(hw);
892
893 return ret_val;
894}
895
896/**
897 * e1000_reset_hw_82543 - Reset hardware
898 * @hw: pointer to the HW structure
899 *
900 * This resets the hardware into a known state.
901 **/
902static s32 e1000_reset_hw_82543(struct e1000_hw *hw)
903{
904 u32 ctrl, icr;
905 s32 ret_val = E1000_SUCCESS;
906
907 DEBUGFUNC("e1000_reset_hw_82543");
908
909 DEBUGOUT("Masking off all interrupts\n");
910 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
911
912 E1000_WRITE_REG(hw, E1000_RCTL, 0);
913 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
914 E1000_WRITE_FLUSH(hw);
915
916 e1000_set_tbi_sbp_82543(hw, FALSE);
917
918 /*
919 * Delay to allow any outstanding PCI transactions to complete before
920 * resetting the device
921 */
922 msec_delay(10);
923
924 ctrl = E1000_READ_REG(hw, E1000_CTRL);
925
926 DEBUGOUT("Issuing a global reset to 82543/82544 MAC\n");
927 if (hw->mac.type == e1000_82543) {
928 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
929 } else {
930 /*
931 * The 82544 can't ACK the 64-bit write when issuing the
932 * reset, so use IO-mapping as a workaround.
933 */
934 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
935 }
936
937 /*
938 * After MAC reset, force reload of NVM to restore power-on
939 * settings to device.
940 */
941 hw->nvm.ops.reload(hw);
942 msec_delay(2);
943
944 /* Masking off and clearing any pending interrupts */
945 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
946 icr = E1000_READ_REG(hw, E1000_ICR);
947
948 return ret_val;
949}
950
951/**
952 * e1000_init_hw_82543 - Initialize hardware
953 * @hw: pointer to the HW structure
954 *
955 * This inits the hardware readying it for operation.
956 **/
957static s32 e1000_init_hw_82543(struct e1000_hw *hw)
958{
959 struct e1000_mac_info *mac = &hw->mac;
960 struct e1000_dev_spec_82543 *dev_spec = &hw->dev_spec._82543;
961 u32 ctrl;
962 s32 ret_val;
963 u16 i;
964
965 DEBUGFUNC("e1000_init_hw_82543");
966
967 /* Disabling VLAN filtering */
968 E1000_WRITE_REG(hw, E1000_VET, 0);
969 mac->ops.clear_vfta(hw);
970
971 /* Setup the receive address. */
972 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
973
974 /* Zero out the Multicast HASH table */
975 DEBUGOUT("Zeroing the MTA\n");
976 for (i = 0; i < mac->mta_reg_count; i++) {
977 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
978 E1000_WRITE_FLUSH(hw);
979 }
980
981 /*
982 * Set the PCI priority bit correctly in the CTRL register. This
983 * determines if the adapter gives priority to receives, or if it
984 * gives equal priority to transmits and receives.
985 */
986 if (hw->mac.type == e1000_82543 && dev_spec->dma_fairness) {
987 ctrl = E1000_READ_REG(hw, E1000_CTRL);
988 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
989 }
990
991 e1000_pcix_mmrbc_workaround_generic(hw);
992
993 /* Setup link and flow control */
994 ret_val = mac->ops.setup_link(hw);
995
996 /*
997 * Clear all of the statistics registers (clear on read). It is
998 * important that we do this after we have tried to establish link
999 * because the symbol error count will increment wildly if there
1000 * is no link.
1001 */
1002 e1000_clear_hw_cntrs_82543(hw);
1003
1004 return ret_val;
1005}
1006
1007/**
1008 * e1000_setup_link_82543 - Setup flow control and link settings
1009 * @hw: pointer to the HW structure
1010 *
1011 * Read the EEPROM to determine the initial polarity value and write the
1012 * extended device control register with the information before calling
1013 * the generic setup link function, which does the following:
1014 * Determines which flow control settings to use, then configures flow
1015 * control. Calls the appropriate media-specific link configuration
1016 * function. Assuming the adapter has a valid link partner, a valid link
1017 * should be established. Assumes the hardware has previously been reset
1018 * and the transmitter and receiver are not enabled.
1019 **/
1020static s32 e1000_setup_link_82543(struct e1000_hw *hw)
1021{
1022 u32 ctrl_ext;
1023 s32 ret_val;
1024 u16 data;
1025
1026 DEBUGFUNC("e1000_setup_link_82543");
1027
1028 /*
1029 * Take the 4 bits from NVM word 0xF that determine the initial
1030 * polarity value for the SW controlled pins, and setup the
1031 * Extended Device Control reg with that info.
1032 * This is needed because one of the SW controlled pins is used for
1033 * signal detection. So this should be done before phy setup.
1034 */
1035 if (hw->mac.type == e1000_82543) {
1036 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1037 if (ret_val) {
1038 DEBUGOUT("NVM Read Error\n");
1039 ret_val = -E1000_ERR_NVM;
1040 goto out;
1041 }
1042 ctrl_ext = ((data & NVM_WORD0F_SWPDIO_EXT_MASK) <<
1043 NVM_SWDPIO_EXT_SHIFT);
1044 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1045 }
1046
1047 ret_val = e1000_setup_link_generic(hw);
1048
1049out:
1050 return ret_val;
1051}
1052
1053/**
1054 * e1000_setup_copper_link_82543 - Configure copper link settings
1055 * @hw: pointer to the HW structure
1056 *
1057 * Configures the link for auto-neg or forced speed and duplex. Then we check
1058 * for link, once link is established calls to configure collision distance
1059 * and flow control are called.
1060 **/
1061static s32 e1000_setup_copper_link_82543(struct e1000_hw *hw)
1062{
1063 u32 ctrl;
1064 s32 ret_val;
1065 bool link;
1066
1067 DEBUGFUNC("e1000_setup_copper_link_82543");
1068
1069 ctrl = E1000_READ_REG(hw, E1000_CTRL) | E1000_CTRL_SLU;
1070 /*
1071 * With 82543, we need to force speed and duplex on the MAC
1072 * equal to what the PHY speed and duplex configuration is.
1073 * In addition, we need to perform a hardware reset on the
1074 * PHY to take it out of reset.
1075 */
1076 if (hw->mac.type == e1000_82543) {
1077 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1078 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1079 ret_val = hw->phy.ops.reset(hw);
1080 if (ret_val)
1081 goto out;
1082 } else {
1083 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1084 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1085 }
1086
1087 /* Set MDI/MDI-X, Polarity Reversal, and downshift settings */
1088 ret_val = e1000_copper_link_setup_m88(hw);
1089 if (ret_val)
1090 goto out;
1091
1092 if (hw->mac.autoneg) {
1093 /*
1094 * Setup autoneg and flow control advertisement and perform
1095 * autonegotiation.
1096 */
1097 ret_val = e1000_copper_link_autoneg(hw);
1098 if (ret_val)
1099 goto out;
1100 } else {
1101 /*
1102 * PHY will be set to 10H, 10F, 100H or 100F
1103 * depending on user settings.
1104 */
1105 DEBUGOUT("Forcing Speed and Duplex\n");
1106 ret_val = e1000_phy_force_speed_duplex_82543(hw);
1107 if (ret_val) {
1108 DEBUGOUT("Error Forcing Speed and Duplex\n");
1109 goto out;
1110 }
1111 }
1112
1113 /*
1114 * Check link status. Wait up to 100 microseconds for link to become
1115 * valid.
1116 */
1117 ret_val = e1000_phy_has_link_generic(hw,
1118 COPPER_LINK_UP_LIMIT,
1119 10,
1120 &link);
1121 if (ret_val)
1122 goto out;
1123
1124
1125 if (link) {
1126 DEBUGOUT("Valid link established!!!\n");
1127 /* Config the MAC and PHY after link is up */
1128 if (hw->mac.type == e1000_82544) {
1129 hw->mac.ops.config_collision_dist(hw);
1130 } else {
1131 ret_val = e1000_config_mac_to_phy_82543(hw);
1132 if (ret_val)
1133 goto out;
1134 }
1135 ret_val = e1000_config_fc_after_link_up_generic(hw);
1136 } else {
1137 DEBUGOUT("Unable to establish link!!!\n");
1138 }
1139
1140out:
1141 return ret_val;
1142}
1143
1144/**
1145 * e1000_setup_fiber_link_82543 - Setup link for fiber
1146 * @hw: pointer to the HW structure
1147 *
1148 * Configures collision distance and flow control for fiber links. Upon
1149 * successful setup, poll for link.
1150 **/
1151static s32 e1000_setup_fiber_link_82543(struct e1000_hw *hw)
1152{
1153 u32 ctrl;
1154 s32 ret_val;
1155
1156 DEBUGFUNC("e1000_setup_fiber_link_82543");
1157
1158 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1159
1160 /* Take the link out of reset */
1161 ctrl &= ~E1000_CTRL_LRST;
1162
1163 hw->mac.ops.config_collision_dist(hw);
1164
1165 ret_val = e1000_commit_fc_settings_generic(hw);
1166 if (ret_val)
1167 goto out;
1168
1169 DEBUGOUT("Auto-negotiation enabled\n");
1170
1171 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1172 E1000_WRITE_FLUSH(hw);
1173 msec_delay(1);
1174
1175 /*
1176 * For these adapters, the SW definable pin 1 is cleared when the
1177 * optics detect a signal. If we have a signal, then poll for a
1178 * "Link-Up" indication.
1179 */
1180 if (!(E1000_READ_REG(hw, E1000_CTRL) & E1000_CTRL_SWDPIN1)) {
1181 ret_val = e1000_poll_fiber_serdes_link_generic(hw);
1182 } else {
1183 DEBUGOUT("No signal detected\n");
1184 }
1185
1186out:
1187 return ret_val;
1188}
1189
1190/**
1191 * e1000_check_for_copper_link_82543 - Check for link (Copper)
1192 * @hw: pointer to the HW structure
1193 *
1194 * Checks the phy for link, if link exists, do the following:
1195 * - check for downshift
1196 * - do polarity workaround (if necessary)
1197 * - configure collision distance
1198 * - configure flow control after link up
1199 * - configure tbi compatibility
1200 **/
1201static s32 e1000_check_for_copper_link_82543(struct e1000_hw *hw)
1202{
1203 struct e1000_mac_info *mac = &hw->mac;
1204 u32 icr, rctl;
1205 s32 ret_val;
1206 u16 speed, duplex;
1207 bool link;
1208
1209 DEBUGFUNC("e1000_check_for_copper_link_82543");
1210
1211 if (!mac->get_link_status) {
1212 ret_val = E1000_SUCCESS;
1213 goto out;
1214 }
1215
1216 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link);
1217 if (ret_val)
1218 goto out;
1219
1220 if (!link)
1221 goto out; /* No link detected */
1222
1223 mac->get_link_status = FALSE;
1224
1225 e1000_check_downshift_generic(hw);
1226
1227 /*
1228 * If we are forcing speed/duplex, then we can return since
1229 * we have already determined whether we have link or not.
1230 */
1231 if (!mac->autoneg) {
1232 /*
1233 * If speed and duplex are forced to 10H or 10F, then we will
1234 * implement the polarity reversal workaround. We disable
1235 * interrupts first, and upon returning, place the devices
1236 * interrupt state to its previous value except for the link
1237 * status change interrupt which will happened due to the
1238 * execution of this workaround.
1239 */
1240 if (mac->forced_speed_duplex & E1000_ALL_10_SPEED) {
1241 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
1242 ret_val = e1000_polarity_reversal_workaround_82543(hw);
1243 icr = E1000_READ_REG(hw, E1000_ICR);
1244 E1000_WRITE_REG(hw, E1000_ICS, (icr & ~E1000_ICS_LSC));
1245 E1000_WRITE_REG(hw, E1000_IMS, IMS_ENABLE_MASK);
1246 }
1247
1248 ret_val = -E1000_ERR_CONFIG;
1249 goto out;
1250 }
1251
1252 /*
1253 * We have a M88E1000 PHY and Auto-Neg is enabled. If we
1254 * have Si on board that is 82544 or newer, Auto
1255 * Speed Detection takes care of MAC speed/duplex
1256 * configuration. So we only need to configure Collision
1257 * Distance in the MAC. Otherwise, we need to force
1258 * speed/duplex on the MAC to the current PHY speed/duplex
1259 * settings.
1260 */
1261 if (mac->type == e1000_82544)
1262 hw->mac.ops.config_collision_dist(hw);
1263 else {
1264 ret_val = e1000_config_mac_to_phy_82543(hw);
1265 if (ret_val) {
1266 DEBUGOUT("Error configuring MAC to PHY settings\n");
1267 goto out;
1268 }
1269 }
1270
1271 /*
1272 * Configure Flow Control now that Auto-Neg has completed.
1273 * First, we need to restore the desired flow control
1274 * settings because we may have had to re-autoneg with a
1275 * different link partner.
1276 */
1277 ret_val = e1000_config_fc_after_link_up_generic(hw);
1278 if (ret_val) {
1279 DEBUGOUT("Error configuring flow control\n");
1280 }
1281
1282 /*
1283 * At this point we know that we are on copper and we have
1284 * auto-negotiated link. These are conditions for checking the link
1285 * partner capability register. We use the link speed to determine if
1286 * TBI compatibility needs to be turned on or off. If the link is not
1287 * at gigabit speed, then TBI compatibility is not needed. If we are
1288 * at gigabit speed, we turn on TBI compatibility.
1289 */
1290 if (e1000_tbi_compatibility_enabled_82543(hw)) {
1291 ret_val = mac->ops.get_link_up_info(hw, &speed, &duplex);
1292 if (ret_val) {
1293 DEBUGOUT("Error getting link speed and duplex\n");
1294 return ret_val;
1295 }
1296 if (speed != SPEED_1000) {
1297 /*
1298 * If link speed is not set to gigabit speed,
1299 * we do not need to enable TBI compatibility.
1300 */
1301 if (e1000_tbi_sbp_enabled_82543(hw)) {
1302 /*
1303 * If we previously were in the mode,
1304 * turn it off.
1305 */
1306 e1000_set_tbi_sbp_82543(hw, FALSE);
1307 rctl = E1000_READ_REG(hw, E1000_RCTL);
1308 rctl &= ~E1000_RCTL_SBP;
1309 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1310 }
1311 } else {
1312 /*
1313 * If TBI compatibility is was previously off,
1314 * turn it on. For compatibility with a TBI link
1315 * partner, we will store bad packets. Some
1316 * frames have an additional byte on the end and
1317 * will look like CRC errors to to the hardware.
1318 */
1319 if (!e1000_tbi_sbp_enabled_82543(hw)) {
1320 e1000_set_tbi_sbp_82543(hw, TRUE);
1321 rctl = E1000_READ_REG(hw, E1000_RCTL);
1322 rctl |= E1000_RCTL_SBP;
1323 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
1324 }
1325 }
1326 }
1327out:
1328 return ret_val;
1329}
1330
1331/**
1332 * e1000_check_for_fiber_link_82543 - Check for link (Fiber)
1333 * @hw: pointer to the HW structure
1334 *
1335 * Checks for link up on the hardware. If link is not up and we have
1336 * a signal, then we need to force link up.
1337 **/
1338static s32 e1000_check_for_fiber_link_82543(struct e1000_hw *hw)
1339{
1340 struct e1000_mac_info *mac = &hw->mac;
1341 u32 rxcw, ctrl, status;
1342 s32 ret_val = E1000_SUCCESS;
1343
1344 DEBUGFUNC("e1000_check_for_fiber_link_82543");
1345
1346 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1347 status = E1000_READ_REG(hw, E1000_STATUS);
1348 rxcw = E1000_READ_REG(hw, E1000_RXCW);
1349
1350 /*
1351 * If we don't have link (auto-negotiation failed or link partner
1352 * cannot auto-negotiate), the cable is plugged in (we have signal),
1353 * and our link partner is not trying to auto-negotiate with us (we
1354 * are receiving idles or data), we need to force link up. We also
1355 * need to give auto-negotiation time to complete, in case the cable
1356 * was just plugged in. The autoneg_failed flag does this.
1357 */
1358 /* (ctrl & E1000_CTRL_SWDPIN1) == 0 == have signal */
1359 if ((!(ctrl & E1000_CTRL_SWDPIN1)) &&
1360 (!(status & E1000_STATUS_LU)) &&
1361 (!(rxcw & E1000_RXCW_C))) {
1362 if (mac->autoneg_failed == 0) {
1363 mac->autoneg_failed = 1;
1364 ret_val = 0;
1365 goto out;
1366 }
1367 DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
1368
1369 /* Disable auto-negotiation in the TXCW register */
1370 E1000_WRITE_REG(hw, E1000_TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1371
1372 /* Force link-up and also force full-duplex. */
1373 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1374 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1375 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1376
1377 /* Configure Flow Control after forcing link up. */
1378 ret_val = e1000_config_fc_after_link_up_generic(hw);
1379 if (ret_val) {
1380 DEBUGOUT("Error configuring flow control\n");
1381 goto out;
1382 }
1383 } else if ((ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
1384 /*
1385 * If we are forcing link and we are receiving /C/ ordered
1386 * sets, re-enable auto-negotiation in the TXCW register
1387 * and disable forced link in the Device Control register
1388 * in an attempt to auto-negotiate with our link partner.
1389 */
1390 DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
1391 E1000_WRITE_REG(hw, E1000_TXCW, mac->txcw);
1392 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl & ~E1000_CTRL_SLU));
1393
1394 mac->serdes_has_link = TRUE;
1395 }
1396
1397out:
1398 return ret_val;
1399}
1400
1401/**
1402 * e1000_config_mac_to_phy_82543 - Configure MAC to PHY settings
1403 * @hw: pointer to the HW structure
1404 *
1405 * For the 82543 silicon, we need to set the MAC to match the settings
1406 * of the PHY, even if the PHY is auto-negotiating.
1407 **/
1408static s32 e1000_config_mac_to_phy_82543(struct e1000_hw *hw)
1409{
1410 u32 ctrl;
1411 s32 ret_val = E1000_SUCCESS;
1412 u16 phy_data;
1413
1414 DEBUGFUNC("e1000_config_mac_to_phy_82543");
1415
1416 if (!(hw->phy.ops.read_reg))
1417 goto out;
1418
1419 /* Set the bits to force speed and duplex */
1420 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1421 ctrl |= (E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1422 ctrl &= ~(E1000_CTRL_SPD_SEL | E1000_CTRL_ILOS);
1423
1424 /*
1425 * Set up duplex in the Device Control and Transmit Control
1426 * registers depending on negotiated values.
1427 */
1428 ret_val = hw->phy.ops.read_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
1429 if (ret_val)
1430 goto out;
1431
1432 ctrl &= ~E1000_CTRL_FD;
1433 if (phy_data & M88E1000_PSSR_DPLX)
1434 ctrl |= E1000_CTRL_FD;
1435
1436 hw->mac.ops.config_collision_dist(hw);
1437
1438 /*
1439 * Set up speed in the Device Control register depending on
1440 * negotiated values.
1441 */
1442 if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
1443 ctrl |= E1000_CTRL_SPD_1000;
1444 else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
1445 ctrl |= E1000_CTRL_SPD_100;
1446
1447 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1448
1449out:
1450 return ret_val;
1451}
1452
1453/**
1454 * e1000_write_vfta_82543 - Write value to VLAN filter table
1455 * @hw: pointer to the HW structure
1456 * @offset: the 32-bit offset in which to write the value to.
1457 * @value: the 32-bit value to write at location offset.
1458 *
1459 * This writes a 32-bit value to a 32-bit offset in the VLAN filter
1460 * table.
1461 **/
1462static void e1000_write_vfta_82543(struct e1000_hw *hw, u32 offset, u32 value)
1463{
1464 u32 temp;
1465
1466 DEBUGFUNC("e1000_write_vfta_82543");
1467
1468 if ((hw->mac.type == e1000_82544) && (offset & 1)) {
1469 temp = E1000_READ_REG_ARRAY(hw, E1000_VFTA, offset - 1);
1470 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
1471 E1000_WRITE_FLUSH(hw);
1472 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset - 1, temp);
1473 E1000_WRITE_FLUSH(hw);
1474 } else {
1475 e1000_write_vfta_generic(hw, offset, value);
1476 }
1477}
1478
1479/**
1480 * e1000_led_on_82543 - Turn on SW controllable LED
1481 * @hw: pointer to the HW structure
1482 *
1483 * Turns the SW defined LED on.
1484 **/
1485static s32 e1000_led_on_82543(struct e1000_hw *hw)
1486{
1487 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1488
1489 DEBUGFUNC("e1000_led_on_82543");
1490
1491 if (hw->mac.type == e1000_82544 &&
1492 hw->phy.media_type == e1000_media_type_copper) {
1493 /* Clear SW-definable Pin 0 to turn on the LED */
1494 ctrl &= ~E1000_CTRL_SWDPIN0;
1495 ctrl |= E1000_CTRL_SWDPIO0;
1496 } else {
1497 /* Fiber 82544 and all 82543 use this method */
1498 ctrl |= E1000_CTRL_SWDPIN0;
1499 ctrl |= E1000_CTRL_SWDPIO0;
1500 }
1501 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1502
1503 return E1000_SUCCESS;
1504}
1505
1506/**
1507 * e1000_led_off_82543 - Turn off SW controllable LED
1508 * @hw: pointer to the HW structure
1509 *
1510 * Turns the SW defined LED off.
1511 **/
1512static s32 e1000_led_off_82543(struct e1000_hw *hw)
1513{
1514 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1515
1516 DEBUGFUNC("e1000_led_off_82543");
1517
1518 if (hw->mac.type == e1000_82544 &&
1519 hw->phy.media_type == e1000_media_type_copper) {
1520 /* Set SW-definable Pin 0 to turn off the LED */
1521 ctrl |= E1000_CTRL_SWDPIN0;
1522 ctrl |= E1000_CTRL_SWDPIO0;
1523 } else {
1524 ctrl &= ~E1000_CTRL_SWDPIN0;
1525 ctrl |= E1000_CTRL_SWDPIO0;
1526 }
1527 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1528
1529 return E1000_SUCCESS;
1530}
1531
1532/**
1533 * e1000_clear_hw_cntrs_82543 - Clear device specific hardware counters
1534 * @hw: pointer to the HW structure
1535 *
1536 * Clears the hardware counters by reading the counter registers.
1537 **/
1538static void e1000_clear_hw_cntrs_82543(struct e1000_hw *hw)
1539{
1540 DEBUGFUNC("e1000_clear_hw_cntrs_82543");
1541
1542 e1000_clear_hw_cntrs_base_generic(hw);
1543
1544 E1000_READ_REG(hw, E1000_PRC64);
1545 E1000_READ_REG(hw, E1000_PRC127);
1546 E1000_READ_REG(hw, E1000_PRC255);
1547 E1000_READ_REG(hw, E1000_PRC511);
1548 E1000_READ_REG(hw, E1000_PRC1023);
1549 E1000_READ_REG(hw, E1000_PRC1522);
1550 E1000_READ_REG(hw, E1000_PTC64);
1551 E1000_READ_REG(hw, E1000_PTC127);
1552 E1000_READ_REG(hw, E1000_PTC255);
1553 E1000_READ_REG(hw, E1000_PTC511);
1554 E1000_READ_REG(hw, E1000_PTC1023);
1555 E1000_READ_REG(hw, E1000_PTC1522);
1556
1557 E1000_READ_REG(hw, E1000_ALGNERRC);
1558 E1000_READ_REG(hw, E1000_RXERRC);
1559 E1000_READ_REG(hw, E1000_TNCRS);
1560 E1000_READ_REG(hw, E1000_CEXTERR);
1561 E1000_READ_REG(hw, E1000_TSCTC);
1562 E1000_READ_REG(hw, E1000_TSCTFC);
1563}
1564
1565/**
1566 * e1000_read_mac_addr_82543 - Read device MAC address
1567 * @hw: pointer to the HW structure
1568 *
1569 * Reads the device MAC address from the EEPROM and stores the value.
1570 * Since devices with two ports use the same EEPROM, we increment the
1571 * last bit in the MAC address for the second port.
1572 *
1573 **/
1574s32 e1000_read_mac_addr_82543(struct e1000_hw *hw)
1575{
1576 s32 ret_val = E1000_SUCCESS;
1577 u16 offset, nvm_data, i;
1578
1579 DEBUGFUNC("e1000_read_mac_addr");
1580
1581 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
1582 offset = i >> 1;
1583 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
1584 if (ret_val) {
1585 DEBUGOUT("NVM Read Error\n");
1586 goto out;
1587 }
1588 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
1589 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
1590 }
1591
1592 /* Flip last bit of mac address if we're on second port */
1593 if (hw->bus.func == E1000_FUNC_1)
1594 hw->mac.perm_addr[5] ^= 1;
1595
1596 for (i = 0; i < ETH_ADDR_LEN; i++)
1597 hw->mac.addr[i] = hw->mac.perm_addr[i];
1598
1599out:
1600 return ret_val;
1601}