1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
| 1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Intel Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
|
33/*$FreeBSD: head/sys/dev/e1000/e1000_82542.c 287990 2015-09-19 18:22:59Z sbruno $*/
| 33/*$FreeBSD: head/sys/dev/e1000/e1000_82542.c 295323 2016-02-05 17:14:37Z erj $*/
|
34
35/*
36 * 82542 Gigabit Ethernet Controller
37 */
38
39#include "e1000_api.h"
40
41static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
42static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
43static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
44static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
45static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
46static s32 e1000_init_hw_82542(struct e1000_hw *hw);
47static s32 e1000_setup_link_82542(struct e1000_hw *hw);
48static s32 e1000_led_on_82542(struct e1000_hw *hw);
49static s32 e1000_led_off_82542(struct e1000_hw *hw);
50static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
52static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);
53
54/**
55 * e1000_init_phy_params_82542 - Init PHY func ptrs.
56 * @hw: pointer to the HW structure
57 **/
58static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
59{
60 struct e1000_phy_info *phy = &hw->phy;
61 s32 ret_val = E1000_SUCCESS;
62
63 DEBUGFUNC("e1000_init_phy_params_82542");
64
65 phy->type = e1000_phy_none;
66
67 return ret_val;
68}
69
70/**
71 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
72 * @hw: pointer to the HW structure
73 **/
74static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
75{
76 struct e1000_nvm_info *nvm = &hw->nvm;
77
78 DEBUGFUNC("e1000_init_nvm_params_82542");
79
80 nvm->address_bits = 6;
81 nvm->delay_usec = 50;
82 nvm->opcode_bits = 3;
83 nvm->type = e1000_nvm_eeprom_microwire;
84 nvm->word_size = 64;
85
86 /* Function Pointers */
87 nvm->ops.read = e1000_read_nvm_microwire;
88 nvm->ops.release = e1000_stop_nvm;
89 nvm->ops.write = e1000_write_nvm_microwire;
90 nvm->ops.update = e1000_update_nvm_checksum_generic;
91 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
92
93 return E1000_SUCCESS;
94}
95
96/**
97 * e1000_init_mac_params_82542 - Init MAC func ptrs.
98 * @hw: pointer to the HW structure
99 **/
100static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
101{
102 struct e1000_mac_info *mac = &hw->mac;
103
104 DEBUGFUNC("e1000_init_mac_params_82542");
105
106 /* Set media type */
107 hw->phy.media_type = e1000_media_type_fiber;
108
109 /* Set mta register count */
110 mac->mta_reg_count = 128;
111 /* Set rar entry count */
112 mac->rar_entry_count = E1000_RAR_ENTRIES;
113
114 /* Function pointers */
115
116 /* bus type/speed/width */
117 mac->ops.get_bus_info = e1000_get_bus_info_82542;
118 /* function id */
119 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
120 /* reset */
121 mac->ops.reset_hw = e1000_reset_hw_82542;
122 /* hw initialization */
123 mac->ops.init_hw = e1000_init_hw_82542;
124 /* link setup */
125 mac->ops.setup_link = e1000_setup_link_82542;
126 /* phy/fiber/serdes setup */
127 mac->ops.setup_physical_interface =
128 e1000_setup_fiber_serdes_link_generic;
129 /* check for link */
130 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
131 /* multicast address update */
132 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
133 /* writing VFTA */
134 mac->ops.write_vfta = e1000_write_vfta_generic;
135 /* clearing VFTA */
136 mac->ops.clear_vfta = e1000_clear_vfta_generic;
137 /* read mac address */
138 mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
139 /* set RAR */
140 mac->ops.rar_set = e1000_rar_set_82542;
141 /* turn on/off LED */
142 mac->ops.led_on = e1000_led_on_82542;
143 mac->ops.led_off = e1000_led_off_82542;
144 /* clear hardware counters */
145 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
146 /* link info */
147 mac->ops.get_link_up_info =
148 e1000_get_speed_and_duplex_fiber_serdes_generic;
149
150 return E1000_SUCCESS;
151}
152
153/**
154 * e1000_init_function_pointers_82542 - Init func ptrs.
155 * @hw: pointer to the HW structure
156 *
157 * Called to initialize all function pointers and parameters.
158 **/
159void e1000_init_function_pointers_82542(struct e1000_hw *hw)
160{
161 DEBUGFUNC("e1000_init_function_pointers_82542");
162
163 hw->mac.ops.init_params = e1000_init_mac_params_82542;
164 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
165 hw->phy.ops.init_params = e1000_init_phy_params_82542;
166}
167
168/**
169 * e1000_get_bus_info_82542 - Obtain bus information for adapter
170 * @hw: pointer to the HW structure
171 *
172 * This will obtain information about the HW bus for which the
173 * adapter is attached and stores it in the hw structure.
174 **/
175static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
176{
177 DEBUGFUNC("e1000_get_bus_info_82542");
178
179 hw->bus.type = e1000_bus_type_pci;
180 hw->bus.speed = e1000_bus_speed_unknown;
181 hw->bus.width = e1000_bus_width_unknown;
182
183 return E1000_SUCCESS;
184}
185
186/**
187 * e1000_reset_hw_82542 - Reset hardware
188 * @hw: pointer to the HW structure
189 *
190 * This resets the hardware into a known state.
191 **/
192static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
193{
194 struct e1000_bus_info *bus = &hw->bus;
195 s32 ret_val = E1000_SUCCESS;
196 u32 ctrl;
197
198 DEBUGFUNC("e1000_reset_hw_82542");
199
200 if (hw->revision_id == E1000_REVISION_2) {
201 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
202 e1000_pci_clear_mwi(hw);
203 }
204
205 DEBUGOUT("Masking off all interrupts\n");
206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
207
208 E1000_WRITE_REG(hw, E1000_RCTL, 0);
209 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
210 E1000_WRITE_FLUSH(hw);
211
212 /*
213 * Delay to allow any outstanding PCI transactions to complete before
214 * resetting the device
215 */
216 msec_delay(10);
217
218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
219
220 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
221 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
222
223 hw->nvm.ops.reload(hw);
224 msec_delay(2);
225
226 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
227 E1000_READ_REG(hw, E1000_ICR);
228
229 if (hw->revision_id == E1000_REVISION_2) {
230 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
231 e1000_pci_set_mwi(hw);
232 }
233
234 return ret_val;
235}
236
237/**
238 * e1000_init_hw_82542 - Initialize hardware
239 * @hw: pointer to the HW structure
240 *
241 * This inits the hardware readying it for operation.
242 **/
243static s32 e1000_init_hw_82542(struct e1000_hw *hw)
244{
245 struct e1000_mac_info *mac = &hw->mac;
246 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
247 s32 ret_val = E1000_SUCCESS;
248 u32 ctrl;
249 u16 i;
250
251 DEBUGFUNC("e1000_init_hw_82542");
252
253 /* Disabling VLAN filtering */
254 E1000_WRITE_REG(hw, E1000_VET, 0);
255 mac->ops.clear_vfta(hw);
256
257 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
258 if (hw->revision_id == E1000_REVISION_2) {
259 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
260 e1000_pci_clear_mwi(hw);
261 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
262 E1000_WRITE_FLUSH(hw);
263 msec_delay(5);
264 }
265
266 /* Setup the receive address. */
267 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
268
269 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
270 if (hw->revision_id == E1000_REVISION_2) {
271 E1000_WRITE_REG(hw, E1000_RCTL, 0);
272 E1000_WRITE_FLUSH(hw);
273 msec_delay(1);
274 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
275 e1000_pci_set_mwi(hw);
276 }
277
278 /* Zero out the Multicast HASH table */
279 DEBUGOUT("Zeroing the MTA\n");
280 for (i = 0; i < mac->mta_reg_count; i++)
281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
282
283 /*
284 * Set the PCI priority bit correctly in the CTRL register. This
285 * determines if the adapter gives priority to receives, or if it
286 * gives equal priority to transmits and receives.
287 */
288 if (dev_spec->dma_fairness) {
289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
290 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
291 }
292
293 /* Setup link and flow control */
294 ret_val = e1000_setup_link_82542(hw);
295
296 /*
297 * Clear all of the statistics registers (clear on read). It is
298 * important that we do this after we have tried to establish link
299 * because the symbol error count will increment wildly if there
300 * is no link.
301 */
302 e1000_clear_hw_cntrs_82542(hw);
303
304 return ret_val;
305}
306
307/**
308 * e1000_setup_link_82542 - Setup flow control and link settings
309 * @hw: pointer to the HW structure
310 *
311 * Determines which flow control settings to use, then configures flow
312 * control. Calls the appropriate media-specific link configuration
313 * function. Assuming the adapter has a valid link partner, a valid link
314 * should be established. Assumes the hardware has previously been reset
315 * and the transmitter and receiver are not enabled.
316 **/
317static s32 e1000_setup_link_82542(struct e1000_hw *hw)
318{
319 struct e1000_mac_info *mac = &hw->mac;
| 34
35/*
36 * 82542 Gigabit Ethernet Controller
37 */
38
39#include "e1000_api.h"
40
41static s32 e1000_init_phy_params_82542(struct e1000_hw *hw);
42static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw);
43static s32 e1000_init_mac_params_82542(struct e1000_hw *hw);
44static s32 e1000_get_bus_info_82542(struct e1000_hw *hw);
45static s32 e1000_reset_hw_82542(struct e1000_hw *hw);
46static s32 e1000_init_hw_82542(struct e1000_hw *hw);
47static s32 e1000_setup_link_82542(struct e1000_hw *hw);
48static s32 e1000_led_on_82542(struct e1000_hw *hw);
49static s32 e1000_led_off_82542(struct e1000_hw *hw);
50static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index);
51static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw);
52static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw);
53
54/**
55 * e1000_init_phy_params_82542 - Init PHY func ptrs.
56 * @hw: pointer to the HW structure
57 **/
58static s32 e1000_init_phy_params_82542(struct e1000_hw *hw)
59{
60 struct e1000_phy_info *phy = &hw->phy;
61 s32 ret_val = E1000_SUCCESS;
62
63 DEBUGFUNC("e1000_init_phy_params_82542");
64
65 phy->type = e1000_phy_none;
66
67 return ret_val;
68}
69
70/**
71 * e1000_init_nvm_params_82542 - Init NVM func ptrs.
72 * @hw: pointer to the HW structure
73 **/
74static s32 e1000_init_nvm_params_82542(struct e1000_hw *hw)
75{
76 struct e1000_nvm_info *nvm = &hw->nvm;
77
78 DEBUGFUNC("e1000_init_nvm_params_82542");
79
80 nvm->address_bits = 6;
81 nvm->delay_usec = 50;
82 nvm->opcode_bits = 3;
83 nvm->type = e1000_nvm_eeprom_microwire;
84 nvm->word_size = 64;
85
86 /* Function Pointers */
87 nvm->ops.read = e1000_read_nvm_microwire;
88 nvm->ops.release = e1000_stop_nvm;
89 nvm->ops.write = e1000_write_nvm_microwire;
90 nvm->ops.update = e1000_update_nvm_checksum_generic;
91 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
92
93 return E1000_SUCCESS;
94}
95
96/**
97 * e1000_init_mac_params_82542 - Init MAC func ptrs.
98 * @hw: pointer to the HW structure
99 **/
100static s32 e1000_init_mac_params_82542(struct e1000_hw *hw)
101{
102 struct e1000_mac_info *mac = &hw->mac;
103
104 DEBUGFUNC("e1000_init_mac_params_82542");
105
106 /* Set media type */
107 hw->phy.media_type = e1000_media_type_fiber;
108
109 /* Set mta register count */
110 mac->mta_reg_count = 128;
111 /* Set rar entry count */
112 mac->rar_entry_count = E1000_RAR_ENTRIES;
113
114 /* Function pointers */
115
116 /* bus type/speed/width */
117 mac->ops.get_bus_info = e1000_get_bus_info_82542;
118 /* function id */
119 mac->ops.set_lan_id = e1000_set_lan_id_multi_port_pci;
120 /* reset */
121 mac->ops.reset_hw = e1000_reset_hw_82542;
122 /* hw initialization */
123 mac->ops.init_hw = e1000_init_hw_82542;
124 /* link setup */
125 mac->ops.setup_link = e1000_setup_link_82542;
126 /* phy/fiber/serdes setup */
127 mac->ops.setup_physical_interface =
128 e1000_setup_fiber_serdes_link_generic;
129 /* check for link */
130 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
131 /* multicast address update */
132 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
133 /* writing VFTA */
134 mac->ops.write_vfta = e1000_write_vfta_generic;
135 /* clearing VFTA */
136 mac->ops.clear_vfta = e1000_clear_vfta_generic;
137 /* read mac address */
138 mac->ops.read_mac_addr = e1000_read_mac_addr_82542;
139 /* set RAR */
140 mac->ops.rar_set = e1000_rar_set_82542;
141 /* turn on/off LED */
142 mac->ops.led_on = e1000_led_on_82542;
143 mac->ops.led_off = e1000_led_off_82542;
144 /* clear hardware counters */
145 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82542;
146 /* link info */
147 mac->ops.get_link_up_info =
148 e1000_get_speed_and_duplex_fiber_serdes_generic;
149
150 return E1000_SUCCESS;
151}
152
153/**
154 * e1000_init_function_pointers_82542 - Init func ptrs.
155 * @hw: pointer to the HW structure
156 *
157 * Called to initialize all function pointers and parameters.
158 **/
159void e1000_init_function_pointers_82542(struct e1000_hw *hw)
160{
161 DEBUGFUNC("e1000_init_function_pointers_82542");
162
163 hw->mac.ops.init_params = e1000_init_mac_params_82542;
164 hw->nvm.ops.init_params = e1000_init_nvm_params_82542;
165 hw->phy.ops.init_params = e1000_init_phy_params_82542;
166}
167
168/**
169 * e1000_get_bus_info_82542 - Obtain bus information for adapter
170 * @hw: pointer to the HW structure
171 *
172 * This will obtain information about the HW bus for which the
173 * adapter is attached and stores it in the hw structure.
174 **/
175static s32 e1000_get_bus_info_82542(struct e1000_hw *hw)
176{
177 DEBUGFUNC("e1000_get_bus_info_82542");
178
179 hw->bus.type = e1000_bus_type_pci;
180 hw->bus.speed = e1000_bus_speed_unknown;
181 hw->bus.width = e1000_bus_width_unknown;
182
183 return E1000_SUCCESS;
184}
185
186/**
187 * e1000_reset_hw_82542 - Reset hardware
188 * @hw: pointer to the HW structure
189 *
190 * This resets the hardware into a known state.
191 **/
192static s32 e1000_reset_hw_82542(struct e1000_hw *hw)
193{
194 struct e1000_bus_info *bus = &hw->bus;
195 s32 ret_val = E1000_SUCCESS;
196 u32 ctrl;
197
198 DEBUGFUNC("e1000_reset_hw_82542");
199
200 if (hw->revision_id == E1000_REVISION_2) {
201 DEBUGOUT("Disabling MWI on 82542 rev 2\n");
202 e1000_pci_clear_mwi(hw);
203 }
204
205 DEBUGOUT("Masking off all interrupts\n");
206 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
207
208 E1000_WRITE_REG(hw, E1000_RCTL, 0);
209 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
210 E1000_WRITE_FLUSH(hw);
211
212 /*
213 * Delay to allow any outstanding PCI transactions to complete before
214 * resetting the device
215 */
216 msec_delay(10);
217
218 ctrl = E1000_READ_REG(hw, E1000_CTRL);
219
220 DEBUGOUT("Issuing a global reset to 82542/82543 MAC\n");
221 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
222
223 hw->nvm.ops.reload(hw);
224 msec_delay(2);
225
226 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
227 E1000_READ_REG(hw, E1000_ICR);
228
229 if (hw->revision_id == E1000_REVISION_2) {
230 if (bus->pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
231 e1000_pci_set_mwi(hw);
232 }
233
234 return ret_val;
235}
236
237/**
238 * e1000_init_hw_82542 - Initialize hardware
239 * @hw: pointer to the HW structure
240 *
241 * This inits the hardware readying it for operation.
242 **/
243static s32 e1000_init_hw_82542(struct e1000_hw *hw)
244{
245 struct e1000_mac_info *mac = &hw->mac;
246 struct e1000_dev_spec_82542 *dev_spec = &hw->dev_spec._82542;
247 s32 ret_val = E1000_SUCCESS;
248 u32 ctrl;
249 u16 i;
250
251 DEBUGFUNC("e1000_init_hw_82542");
252
253 /* Disabling VLAN filtering */
254 E1000_WRITE_REG(hw, E1000_VET, 0);
255 mac->ops.clear_vfta(hw);
256
257 /* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
258 if (hw->revision_id == E1000_REVISION_2) {
259 DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
260 e1000_pci_clear_mwi(hw);
261 E1000_WRITE_REG(hw, E1000_RCTL, E1000_RCTL_RST);
262 E1000_WRITE_FLUSH(hw);
263 msec_delay(5);
264 }
265
266 /* Setup the receive address. */
267 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
268
269 /* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
270 if (hw->revision_id == E1000_REVISION_2) {
271 E1000_WRITE_REG(hw, E1000_RCTL, 0);
272 E1000_WRITE_FLUSH(hw);
273 msec_delay(1);
274 if (hw->bus.pci_cmd_word & CMD_MEM_WRT_INVALIDATE)
275 e1000_pci_set_mwi(hw);
276 }
277
278 /* Zero out the Multicast HASH table */
279 DEBUGOUT("Zeroing the MTA\n");
280 for (i = 0; i < mac->mta_reg_count; i++)
281 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
282
283 /*
284 * Set the PCI priority bit correctly in the CTRL register. This
285 * determines if the adapter gives priority to receives, or if it
286 * gives equal priority to transmits and receives.
287 */
288 if (dev_spec->dma_fairness) {
289 ctrl = E1000_READ_REG(hw, E1000_CTRL);
290 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_PRIOR);
291 }
292
293 /* Setup link and flow control */
294 ret_val = e1000_setup_link_82542(hw);
295
296 /*
297 * Clear all of the statistics registers (clear on read). It is
298 * important that we do this after we have tried to establish link
299 * because the symbol error count will increment wildly if there
300 * is no link.
301 */
302 e1000_clear_hw_cntrs_82542(hw);
303
304 return ret_val;
305}
306
307/**
308 * e1000_setup_link_82542 - Setup flow control and link settings
309 * @hw: pointer to the HW structure
310 *
311 * Determines which flow control settings to use, then configures flow
312 * control. Calls the appropriate media-specific link configuration
313 * function. Assuming the adapter has a valid link partner, a valid link
314 * should be established. Assumes the hardware has previously been reset
315 * and the transmitter and receiver are not enabled.
316 **/
317static s32 e1000_setup_link_82542(struct e1000_hw *hw)
318{
319 struct e1000_mac_info *mac = &hw->mac;
|
320 s32 ret_val = E1000_SUCCESS;
| 320 s32 ret_val;
|
321
322 DEBUGFUNC("e1000_setup_link_82542");
323
324 ret_val = e1000_set_default_fc_generic(hw);
325 if (ret_val)
326 goto out;
327
328 hw->fc.requested_mode &= ~e1000_fc_tx_pause;
329
330 if (mac->report_tx_early)
331 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
332
333 /*
334 * Save off the requested flow control mode for use later. Depending
335 * on the link partner's capabilities, we may or may not use this mode.
336 */
337 hw->fc.current_mode = hw->fc.requested_mode;
338
339 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
340 hw->fc.current_mode);
341
342 /* Call the necessary subroutine to configure the link. */
343 ret_val = mac->ops.setup_physical_interface(hw);
344 if (ret_val)
345 goto out;
346
347 /*
348 * Initialize the flow control address, type, and PAUSE timer
349 * registers to their default values. This is done even if flow
350 * control is disabled, because it does not hurt anything to
351 * initialize these registers.
352 */
353 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
354
355 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
356 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
357 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
358
359 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
360
361 ret_val = e1000_set_fc_watermarks_generic(hw);
362
363out:
364 return ret_val;
365}
366
367/**
368 * e1000_led_on_82542 - Turn on SW controllable LED
369 * @hw: pointer to the HW structure
370 *
371 * Turns the SW defined LED on.
372 **/
373static s32 e1000_led_on_82542(struct e1000_hw *hw)
374{
375 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
376
377 DEBUGFUNC("e1000_led_on_82542");
378
379 ctrl |= E1000_CTRL_SWDPIN0;
380 ctrl |= E1000_CTRL_SWDPIO0;
381 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
382
383 return E1000_SUCCESS;
384}
385
386/**
387 * e1000_led_off_82542 - Turn off SW controllable LED
388 * @hw: pointer to the HW structure
389 *
390 * Turns the SW defined LED off.
391 **/
392static s32 e1000_led_off_82542(struct e1000_hw *hw)
393{
394 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
395
396 DEBUGFUNC("e1000_led_off_82542");
397
398 ctrl &= ~E1000_CTRL_SWDPIN0;
399 ctrl |= E1000_CTRL_SWDPIO0;
400 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
401
402 return E1000_SUCCESS;
403}
404
405/**
406 * e1000_rar_set_82542 - Set receive address register
407 * @hw: pointer to the HW structure
408 * @addr: pointer to the receive address
409 * @index: receive address array register
410 *
411 * Sets the receive address array register at index to the address passed
412 * in by addr.
413 **/
414static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
415{
416 u32 rar_low, rar_high;
417
418 DEBUGFUNC("e1000_rar_set_82542");
419
420 /*
421 * HW expects these in little endian so we reverse the byte order
422 * from network order (big endian) to little endian
423 */
424 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
425 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
426
427 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
428
429 /* If MAC address zero, no need to set the AV bit */
430 if (rar_low || rar_high)
431 rar_high |= E1000_RAH_AV;
432
433 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
434 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
435
436 return E1000_SUCCESS;
437}
438
439/**
440 * e1000_translate_register_82542 - Translate the proper register offset
441 * @reg: e1000 register to be read
442 *
443 * Registers in 82542 are located in different offsets than other adapters
444 * even though they function in the same manner. This function takes in
445 * the name of the register to read and returns the correct offset for
446 * 82542 silicon.
447 **/
448u32 e1000_translate_register_82542(u32 reg)
449{
450 /*
451 * Some of the 82542 registers are located at different
452 * offsets than they are in newer adapters.
453 * Despite the difference in location, the registers
454 * function in the same manner.
455 */
456 switch (reg) {
457 case E1000_RA:
458 reg = 0x00040;
459 break;
460 case E1000_RDTR:
461 reg = 0x00108;
462 break;
463 case E1000_RDBAL(0):
464 reg = 0x00110;
465 break;
466 case E1000_RDBAH(0):
467 reg = 0x00114;
468 break;
469 case E1000_RDLEN(0):
470 reg = 0x00118;
471 break;
472 case E1000_RDH(0):
473 reg = 0x00120;
474 break;
475 case E1000_RDT(0):
476 reg = 0x00128;
477 break;
478 case E1000_RDBAL(1):
479 reg = 0x00138;
480 break;
481 case E1000_RDBAH(1):
482 reg = 0x0013C;
483 break;
484 case E1000_RDLEN(1):
485 reg = 0x00140;
486 break;
487 case E1000_RDH(1):
488 reg = 0x00148;
489 break;
490 case E1000_RDT(1):
491 reg = 0x00150;
492 break;
493 case E1000_FCRTH:
494 reg = 0x00160;
495 break;
496 case E1000_FCRTL:
497 reg = 0x00168;
498 break;
499 case E1000_MTA:
500 reg = 0x00200;
501 break;
502 case E1000_TDBAL(0):
503 reg = 0x00420;
504 break;
505 case E1000_TDBAH(0):
506 reg = 0x00424;
507 break;
508 case E1000_TDLEN(0):
509 reg = 0x00428;
510 break;
511 case E1000_TDH(0):
512 reg = 0x00430;
513 break;
514 case E1000_TDT(0):
515 reg = 0x00438;
516 break;
517 case E1000_TIDV:
518 reg = 0x00440;
519 break;
520 case E1000_VFTA:
521 reg = 0x00600;
522 break;
523 case E1000_TDFH:
524 reg = 0x08010;
525 break;
526 case E1000_TDFT:
527 reg = 0x08018;
528 break;
529 default:
530 break;
531 }
532
533 return reg;
534}
535
536/**
537 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
538 * @hw: pointer to the HW structure
539 *
540 * Clears the hardware counters by reading the counter registers.
541 **/
542static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
543{
544 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
545
546 e1000_clear_hw_cntrs_base_generic(hw);
547
548 E1000_READ_REG(hw, E1000_PRC64);
549 E1000_READ_REG(hw, E1000_PRC127);
550 E1000_READ_REG(hw, E1000_PRC255);
551 E1000_READ_REG(hw, E1000_PRC511);
552 E1000_READ_REG(hw, E1000_PRC1023);
553 E1000_READ_REG(hw, E1000_PRC1522);
554 E1000_READ_REG(hw, E1000_PTC64);
555 E1000_READ_REG(hw, E1000_PTC127);
556 E1000_READ_REG(hw, E1000_PTC255);
557 E1000_READ_REG(hw, E1000_PTC511);
558 E1000_READ_REG(hw, E1000_PTC1023);
559 E1000_READ_REG(hw, E1000_PTC1522);
560}
561
562/**
563 * e1000_read_mac_addr_82542 - Read device MAC address
564 * @hw: pointer to the HW structure
565 *
566 * Reads the device MAC address from the EEPROM and stores the value.
567 **/
| 321
322 DEBUGFUNC("e1000_setup_link_82542");
323
324 ret_val = e1000_set_default_fc_generic(hw);
325 if (ret_val)
326 goto out;
327
328 hw->fc.requested_mode &= ~e1000_fc_tx_pause;
329
330 if (mac->report_tx_early)
331 hw->fc.requested_mode &= ~e1000_fc_rx_pause;
332
333 /*
334 * Save off the requested flow control mode for use later. Depending
335 * on the link partner's capabilities, we may or may not use this mode.
336 */
337 hw->fc.current_mode = hw->fc.requested_mode;
338
339 DEBUGOUT1("After fix-ups FlowControl is now = %x\n",
340 hw->fc.current_mode);
341
342 /* Call the necessary subroutine to configure the link. */
343 ret_val = mac->ops.setup_physical_interface(hw);
344 if (ret_val)
345 goto out;
346
347 /*
348 * Initialize the flow control address, type, and PAUSE timer
349 * registers to their default values. This is done even if flow
350 * control is disabled, because it does not hurt anything to
351 * initialize these registers.
352 */
353 DEBUGOUT("Initializing Flow Control address, type and timer regs\n");
354
355 E1000_WRITE_REG(hw, E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
356 E1000_WRITE_REG(hw, E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
357 E1000_WRITE_REG(hw, E1000_FCT, FLOW_CONTROL_TYPE);
358
359 E1000_WRITE_REG(hw, E1000_FCTTV, hw->fc.pause_time);
360
361 ret_val = e1000_set_fc_watermarks_generic(hw);
362
363out:
364 return ret_val;
365}
366
367/**
368 * e1000_led_on_82542 - Turn on SW controllable LED
369 * @hw: pointer to the HW structure
370 *
371 * Turns the SW defined LED on.
372 **/
373static s32 e1000_led_on_82542(struct e1000_hw *hw)
374{
375 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
376
377 DEBUGFUNC("e1000_led_on_82542");
378
379 ctrl |= E1000_CTRL_SWDPIN0;
380 ctrl |= E1000_CTRL_SWDPIO0;
381 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
382
383 return E1000_SUCCESS;
384}
385
386/**
387 * e1000_led_off_82542 - Turn off SW controllable LED
388 * @hw: pointer to the HW structure
389 *
390 * Turns the SW defined LED off.
391 **/
392static s32 e1000_led_off_82542(struct e1000_hw *hw)
393{
394 u32 ctrl = E1000_READ_REG(hw, E1000_CTRL);
395
396 DEBUGFUNC("e1000_led_off_82542");
397
398 ctrl &= ~E1000_CTRL_SWDPIN0;
399 ctrl |= E1000_CTRL_SWDPIO0;
400 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
401
402 return E1000_SUCCESS;
403}
404
405/**
406 * e1000_rar_set_82542 - Set receive address register
407 * @hw: pointer to the HW structure
408 * @addr: pointer to the receive address
409 * @index: receive address array register
410 *
411 * Sets the receive address array register at index to the address passed
412 * in by addr.
413 **/
414static int e1000_rar_set_82542(struct e1000_hw *hw, u8 *addr, u32 index)
415{
416 u32 rar_low, rar_high;
417
418 DEBUGFUNC("e1000_rar_set_82542");
419
420 /*
421 * HW expects these in little endian so we reverse the byte order
422 * from network order (big endian) to little endian
423 */
424 rar_low = ((u32) addr[0] | ((u32) addr[1] << 8) |
425 ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
426
427 rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
428
429 /* If MAC address zero, no need to set the AV bit */
430 if (rar_low || rar_high)
431 rar_high |= E1000_RAH_AV;
432
433 E1000_WRITE_REG_ARRAY(hw, E1000_RA, (index << 1), rar_low);
434 E1000_WRITE_REG_ARRAY(hw, E1000_RA, ((index << 1) + 1), rar_high);
435
436 return E1000_SUCCESS;
437}
438
439/**
440 * e1000_translate_register_82542 - Translate the proper register offset
441 * @reg: e1000 register to be read
442 *
443 * Registers in 82542 are located in different offsets than other adapters
444 * even though they function in the same manner. This function takes in
445 * the name of the register to read and returns the correct offset for
446 * 82542 silicon.
447 **/
448u32 e1000_translate_register_82542(u32 reg)
449{
450 /*
451 * Some of the 82542 registers are located at different
452 * offsets than they are in newer adapters.
453 * Despite the difference in location, the registers
454 * function in the same manner.
455 */
456 switch (reg) {
457 case E1000_RA:
458 reg = 0x00040;
459 break;
460 case E1000_RDTR:
461 reg = 0x00108;
462 break;
463 case E1000_RDBAL(0):
464 reg = 0x00110;
465 break;
466 case E1000_RDBAH(0):
467 reg = 0x00114;
468 break;
469 case E1000_RDLEN(0):
470 reg = 0x00118;
471 break;
472 case E1000_RDH(0):
473 reg = 0x00120;
474 break;
475 case E1000_RDT(0):
476 reg = 0x00128;
477 break;
478 case E1000_RDBAL(1):
479 reg = 0x00138;
480 break;
481 case E1000_RDBAH(1):
482 reg = 0x0013C;
483 break;
484 case E1000_RDLEN(1):
485 reg = 0x00140;
486 break;
487 case E1000_RDH(1):
488 reg = 0x00148;
489 break;
490 case E1000_RDT(1):
491 reg = 0x00150;
492 break;
493 case E1000_FCRTH:
494 reg = 0x00160;
495 break;
496 case E1000_FCRTL:
497 reg = 0x00168;
498 break;
499 case E1000_MTA:
500 reg = 0x00200;
501 break;
502 case E1000_TDBAL(0):
503 reg = 0x00420;
504 break;
505 case E1000_TDBAH(0):
506 reg = 0x00424;
507 break;
508 case E1000_TDLEN(0):
509 reg = 0x00428;
510 break;
511 case E1000_TDH(0):
512 reg = 0x00430;
513 break;
514 case E1000_TDT(0):
515 reg = 0x00438;
516 break;
517 case E1000_TIDV:
518 reg = 0x00440;
519 break;
520 case E1000_VFTA:
521 reg = 0x00600;
522 break;
523 case E1000_TDFH:
524 reg = 0x08010;
525 break;
526 case E1000_TDFT:
527 reg = 0x08018;
528 break;
529 default:
530 break;
531 }
532
533 return reg;
534}
535
536/**
537 * e1000_clear_hw_cntrs_82542 - Clear device specific hardware counters
538 * @hw: pointer to the HW structure
539 *
540 * Clears the hardware counters by reading the counter registers.
541 **/
542static void e1000_clear_hw_cntrs_82542(struct e1000_hw *hw)
543{
544 DEBUGFUNC("e1000_clear_hw_cntrs_82542");
545
546 e1000_clear_hw_cntrs_base_generic(hw);
547
548 E1000_READ_REG(hw, E1000_PRC64);
549 E1000_READ_REG(hw, E1000_PRC127);
550 E1000_READ_REG(hw, E1000_PRC255);
551 E1000_READ_REG(hw, E1000_PRC511);
552 E1000_READ_REG(hw, E1000_PRC1023);
553 E1000_READ_REG(hw, E1000_PRC1522);
554 E1000_READ_REG(hw, E1000_PTC64);
555 E1000_READ_REG(hw, E1000_PTC127);
556 E1000_READ_REG(hw, E1000_PTC255);
557 E1000_READ_REG(hw, E1000_PTC511);
558 E1000_READ_REG(hw, E1000_PTC1023);
559 E1000_READ_REG(hw, E1000_PTC1522);
560}
561
562/**
563 * e1000_read_mac_addr_82542 - Read device MAC address
564 * @hw: pointer to the HW structure
565 *
566 * Reads the device MAC address from the EEPROM and stores the value.
567 **/
|
568static s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
| 568s32 e1000_read_mac_addr_82542(struct e1000_hw *hw)
|
569{
570 s32 ret_val = E1000_SUCCESS;
571 u16 offset, nvm_data, i;
572
573 DEBUGFUNC("e1000_read_mac_addr");
574
575 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
576 offset = i >> 1;
577 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
578 if (ret_val) {
579 DEBUGOUT("NVM Read Error\n");
580 goto out;
581 }
582 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
583 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
584 }
585
586 for (i = 0; i < ETH_ADDR_LEN; i++)
587 hw->mac.addr[i] = hw->mac.perm_addr[i];
588
589out:
590 return ret_val;
591}
| 569{
570 s32 ret_val = E1000_SUCCESS;
571 u16 offset, nvm_data, i;
572
573 DEBUGFUNC("e1000_read_mac_addr");
574
575 for (i = 0; i < ETH_ADDR_LEN; i += 2) {
576 offset = i >> 1;
577 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
578 if (ret_val) {
579 DEBUGOUT("NVM Read Error\n");
580 goto out;
581 }
582 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF);
583 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8);
584 }
585
586 for (i = 0; i < ETH_ADDR_LEN; i++)
587 hw->mac.addr[i] = hw->mac.perm_addr[i];
588
589out:
590 return ret_val;
591}
|