34 35/* 36 * 82541EI Gigabit Ethernet Controller 37 * 82541ER Gigabit Ethernet Controller 38 * 82541GI Gigabit Ethernet Controller 39 * 82541PI Gigabit Ethernet Controller 40 * 82547EI Gigabit Ethernet Controller 41 * 82547GI Gigabit Ethernet Controller 42 */ 43 44#include "e1000_api.h" 45 46static s32 e1000_init_phy_params_82541(struct e1000_hw *hw); 47static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw); 48static s32 e1000_init_mac_params_82541(struct e1000_hw *hw); 49static s32 e1000_reset_hw_82541(struct e1000_hw *hw); 50static s32 e1000_init_hw_82541(struct e1000_hw *hw); 51static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 52 u16 *duplex); 53static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw); 54static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw); 55static s32 e1000_check_for_link_82541(struct e1000_hw *hw); 56static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw); 57static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, 58 bool active); 59static s32 e1000_setup_led_82541(struct e1000_hw *hw); 60static s32 e1000_cleanup_led_82541(struct e1000_hw *hw); 61static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw); 62static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw); 63static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 64 bool link_up); 65static s32 e1000_phy_init_script_82541(struct e1000_hw *hw); 66static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw); 67 68static const u16 e1000_igp_cable_length_table[] = 69 { 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 70 5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25, 71 25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40, 72 40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60, 73 60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90, 74 90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100, 75 100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 76 110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120}; 77#define IGP01E1000_AGC_LENGTH_TABLE_SIZE \ 78 (sizeof(e1000_igp_cable_length_table) / \ 79 sizeof(e1000_igp_cable_length_table[0])) 80 81/** 82 * e1000_init_phy_params_82541 - Init PHY func ptrs. 83 * @hw: pointer to the HW structure 84 **/ 85static s32 e1000_init_phy_params_82541(struct e1000_hw *hw) 86{ 87 struct e1000_phy_info *phy = &hw->phy; 88 s32 ret_val = E1000_SUCCESS; 89 90 DEBUGFUNC("e1000_init_phy_params_82541"); 91 92 phy->addr = 1; 93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT; 94 phy->reset_delay_us = 10000; 95 phy->type = e1000_phy_igp; 96 97 /* Function Pointers */ 98 phy->ops.check_polarity = e1000_check_polarity_igp; 99 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp; 100 phy->ops.get_cable_length = e1000_get_cable_length_igp_82541; 101 phy->ops.get_cfg_done = e1000_get_cfg_done_generic; 102 phy->ops.get_info = e1000_get_phy_info_igp; 103 phy->ops.read_reg = e1000_read_phy_reg_igp; 104 phy->ops.reset = e1000_phy_hw_reset_82541; 105 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82541; 106 phy->ops.write_reg = e1000_write_phy_reg_igp; 107 phy->ops.power_up = e1000_power_up_phy_copper; 108 phy->ops.power_down = e1000_power_down_phy_copper_82541; 109 110 ret_val = e1000_get_phy_id(hw); 111 if (ret_val) 112 goto out; 113 114 /* Verify phy id */ 115 if (phy->id != IGP01E1000_I_PHY_ID) { 116 ret_val = -E1000_ERR_PHY; 117 goto out; 118 } 119 120out: 121 return ret_val; 122} 123 124/** 125 * e1000_init_nvm_params_82541 - Init NVM func ptrs. 126 * @hw: pointer to the HW structure 127 **/ 128static s32 e1000_init_nvm_params_82541(struct e1000_hw *hw) 129{ 130 struct e1000_nvm_info *nvm = &hw->nvm; 131 s32 ret_val = E1000_SUCCESS; 132 u32 eecd = E1000_READ_REG(hw, E1000_EECD); 133 u16 size; 134 135 DEBUGFUNC("e1000_init_nvm_params_82541"); 136 137 switch (nvm->override) { 138 case e1000_nvm_override_spi_large: 139 nvm->type = e1000_nvm_eeprom_spi; 140 eecd |= E1000_EECD_ADDR_BITS; 141 break; 142 case e1000_nvm_override_spi_small: 143 nvm->type = e1000_nvm_eeprom_spi; 144 eecd &= ~E1000_EECD_ADDR_BITS; 145 break; 146 case e1000_nvm_override_microwire_large: 147 nvm->type = e1000_nvm_eeprom_microwire; 148 eecd |= E1000_EECD_SIZE; 149 break; 150 case e1000_nvm_override_microwire_small: 151 nvm->type = e1000_nvm_eeprom_microwire; 152 eecd &= ~E1000_EECD_SIZE; 153 break; 154 default: 155 nvm->type = eecd & E1000_EECD_TYPE 156 ? e1000_nvm_eeprom_spi 157 : e1000_nvm_eeprom_microwire; 158 break; 159 } 160 161 if (nvm->type == e1000_nvm_eeprom_spi) { 162 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 163 ? 16 : 8; 164 nvm->delay_usec = 1; 165 nvm->opcode_bits = 8; 166 nvm->page_size = (eecd & E1000_EECD_ADDR_BITS) 167 ? 32 : 8; 168 169 /* Function Pointers */ 170 nvm->ops.acquire = e1000_acquire_nvm_generic; 171 nvm->ops.read = e1000_read_nvm_spi; 172 nvm->ops.release = e1000_release_nvm_generic; 173 nvm->ops.update = e1000_update_nvm_checksum_generic; 174 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 175 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 176 nvm->ops.write = e1000_write_nvm_spi; 177 178 /* 179 * nvm->word_size must be discovered after the pointers 180 * are set so we can verify the size from the nvm image 181 * itself. Temporarily set it to a dummy value so the 182 * read will work. 183 */ 184 nvm->word_size = 64; 185 ret_val = nvm->ops.read(hw, NVM_CFG, 1, &size); 186 if (ret_val) 187 goto out; 188 size = (size & NVM_SIZE_MASK) >> NVM_SIZE_SHIFT; 189 /* 190 * if size != 0, it can be added to a constant and become 191 * the left-shift value to set the word_size. Otherwise, 192 * word_size stays at 64. 193 */ 194 if (size) { 195 size += NVM_WORD_SIZE_BASE_SHIFT_82541; 196 nvm->word_size = 1 << size; 197 } 198 } else { 199 nvm->address_bits = (eecd & E1000_EECD_ADDR_BITS) 200 ? 8 : 6; 201 nvm->delay_usec = 50; 202 nvm->opcode_bits = 3; 203 nvm->word_size = (eecd & E1000_EECD_ADDR_BITS) 204 ? 256 : 64; 205 206 /* Function Pointers */ 207 nvm->ops.acquire = e1000_acquire_nvm_generic; 208 nvm->ops.read = e1000_read_nvm_microwire; 209 nvm->ops.release = e1000_release_nvm_generic; 210 nvm->ops.update = e1000_update_nvm_checksum_generic; 211 nvm->ops.valid_led_default = e1000_valid_led_default_generic; 212 nvm->ops.validate = e1000_validate_nvm_checksum_generic; 213 nvm->ops.write = e1000_write_nvm_microwire; 214 } 215 216out: 217 return ret_val; 218} 219 220/** 221 * e1000_init_mac_params_82541 - Init MAC func ptrs. 222 * @hw: pointer to the HW structure 223 **/ 224static s32 e1000_init_mac_params_82541(struct e1000_hw *hw) 225{ 226 struct e1000_mac_info *mac = &hw->mac; 227 228 DEBUGFUNC("e1000_init_mac_params_82541"); 229 230 /* Set media type */ 231 hw->phy.media_type = e1000_media_type_copper; 232 /* Set mta register count */ 233 mac->mta_reg_count = 128; 234 /* Set rar entry count */ 235 mac->rar_entry_count = E1000_RAR_ENTRIES; 236 /* Set if part includes ASF firmware */ 237 mac->asf_firmware_present = TRUE; 238 239 /* Function Pointers */ 240 241 /* bus type/speed/width */ 242 mac->ops.get_bus_info = e1000_get_bus_info_pci_generic; 243 /* function id */ 244 mac->ops.set_lan_id = e1000_set_lan_id_single_port; 245 /* reset */ 246 mac->ops.reset_hw = e1000_reset_hw_82541; 247 /* hw initialization */ 248 mac->ops.init_hw = e1000_init_hw_82541; 249 /* link setup */ 250 mac->ops.setup_link = e1000_setup_link_generic; 251 /* physical interface link setup */ 252 mac->ops.setup_physical_interface = e1000_setup_copper_link_82541; 253 /* check for link */ 254 mac->ops.check_for_link = e1000_check_for_link_82541; 255 /* link info */ 256 mac->ops.get_link_up_info = e1000_get_link_up_info_82541; 257 /* multicast address update */ 258 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic; 259 /* writing VFTA */ 260 mac->ops.write_vfta = e1000_write_vfta_generic; 261 /* clearing VFTA */ 262 mac->ops.clear_vfta = e1000_clear_vfta_generic; 263 /* read mac address */ 264 mac->ops.read_mac_addr = e1000_read_mac_addr_82541; 265 /* ID LED init */ 266 mac->ops.id_led_init = e1000_id_led_init_generic; 267 /* setup LED */ 268 mac->ops.setup_led = e1000_setup_led_82541; 269 /* cleanup LED */ 270 mac->ops.cleanup_led = e1000_cleanup_led_82541; 271 /* turn on/off LED */ 272 mac->ops.led_on = e1000_led_on_generic; 273 mac->ops.led_off = e1000_led_off_generic; 274 /* clear hardware counters */ 275 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82541; 276 277 return E1000_SUCCESS; 278} 279 280/** 281 * e1000_init_function_pointers_82541 - Init func ptrs. 282 * @hw: pointer to the HW structure 283 * 284 * Called to initialize all function pointers and parameters. 285 **/ 286void e1000_init_function_pointers_82541(struct e1000_hw *hw) 287{ 288 DEBUGFUNC("e1000_init_function_pointers_82541"); 289 290 hw->mac.ops.init_params = e1000_init_mac_params_82541; 291 hw->nvm.ops.init_params = e1000_init_nvm_params_82541; 292 hw->phy.ops.init_params = e1000_init_phy_params_82541; 293} 294 295/** 296 * e1000_reset_hw_82541 - Reset hardware 297 * @hw: pointer to the HW structure 298 * 299 * This resets the hardware into a known state. 300 **/ 301static s32 e1000_reset_hw_82541(struct e1000_hw *hw) 302{ 303 u32 ledctl, ctrl, icr, manc; 304 305 DEBUGFUNC("e1000_reset_hw_82541"); 306 307 DEBUGOUT("Masking off all interrupts\n"); 308 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 309 310 E1000_WRITE_REG(hw, E1000_RCTL, 0); 311 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP); 312 E1000_WRITE_FLUSH(hw); 313 314 /* 315 * Delay to allow any outstanding PCI transactions to complete 316 * before resetting the device. 317 */ 318 msec_delay(10); 319 320 ctrl = E1000_READ_REG(hw, E1000_CTRL); 321 322 /* Must reset the Phy before resetting the MAC */ 323 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 324 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST)); 325 msec_delay(5); 326 } 327 328 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n"); 329 switch (hw->mac.type) { 330 case e1000_82541: 331 case e1000_82541_rev_2: 332 /* 333 * These controllers can't ack the 64-bit write when 334 * issuing the reset, so we use IO-mapping as a 335 * workaround to issue the reset. 336 */ 337 E1000_WRITE_REG_IO(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 338 break; 339 default: 340 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST); 341 break; 342 } 343 344 /* Wait for NVM reload */ 345 msec_delay(20); 346 347 /* Disable HW ARPs on ASF enabled adapters */ 348 manc = E1000_READ_REG(hw, E1000_MANC); 349 manc &= ~E1000_MANC_ARP_EN; 350 E1000_WRITE_REG(hw, E1000_MANC, manc); 351 352 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 353 e1000_phy_init_script_82541(hw); 354 355 /* Configure activity LED after Phy reset */ 356 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 357 ledctl &= IGP_ACTIVITY_LED_MASK; 358 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 359 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 360 } 361 362 /* Once again, mask the interrupts */ 363 DEBUGOUT("Masking off all interrupts\n"); 364 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF); 365 366 /* Clear any pending interrupt events. */ 367 icr = E1000_READ_REG(hw, E1000_ICR); 368 369 return E1000_SUCCESS; 370} 371 372/** 373 * e1000_init_hw_82541 - Initialize hardware 374 * @hw: pointer to the HW structure 375 * 376 * This inits the hardware readying it for operation. 377 **/ 378static s32 e1000_init_hw_82541(struct e1000_hw *hw) 379{ 380 struct e1000_mac_info *mac = &hw->mac; 381 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 382 u32 i, txdctl; 383 s32 ret_val; 384 385 DEBUGFUNC("e1000_init_hw_82541"); 386 387 /* Initialize identification LED */ 388 ret_val = mac->ops.id_led_init(hw); 389 if (ret_val) { 390 DEBUGOUT("Error initializing identification LED\n"); 391 /* This is not fatal and we should not stop init due to this */ 392 } 393 394 /* Storing the Speed Power Down value for later use */ 395 ret_val = hw->phy.ops.read_reg(hw, 396 IGP01E1000_GMII_FIFO, 397 &dev_spec->spd_default); 398 if (ret_val) 399 goto out; 400 401 /* Disabling VLAN filtering */ 402 DEBUGOUT("Initializing the IEEE VLAN\n"); 403 mac->ops.clear_vfta(hw); 404 405 /* Setup the receive address. */ 406 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count); 407 408 /* Zero out the Multicast HASH table */ 409 DEBUGOUT("Zeroing the MTA\n"); 410 for (i = 0; i < mac->mta_reg_count; i++) { 411 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0); 412 /* 413 * Avoid back to back register writes by adding the register 414 * read (flush). This is to protect against some strange 415 * bridge configurations that may issue Memory Write Block 416 * (MWB) to our register space. 417 */ 418 E1000_WRITE_FLUSH(hw); 419 } 420 421 /* Setup link and flow control */ 422 ret_val = mac->ops.setup_link(hw); 423 424 txdctl = E1000_READ_REG(hw, E1000_TXDCTL(0)); 425 txdctl = (txdctl & ~E1000_TXDCTL_WTHRESH) | 426 E1000_TXDCTL_FULL_TX_DESC_WB; 427 E1000_WRITE_REG(hw, E1000_TXDCTL(0), txdctl); 428 429 /* 430 * Clear all of the statistics registers (clear on read). It is 431 * important that we do this after we have tried to establish link 432 * because the symbol error count will increment wildly if there 433 * is no link. 434 */ 435 e1000_clear_hw_cntrs_82541(hw); 436 437out: 438 return ret_val; 439} 440 441/** 442 * e1000_get_link_up_info_82541 - Report speed and duplex 443 * @hw: pointer to the HW structure 444 * @speed: pointer to speed buffer 445 * @duplex: pointer to duplex buffer 446 * 447 * Retrieve the current speed and duplex configuration. 448 **/ 449static s32 e1000_get_link_up_info_82541(struct e1000_hw *hw, u16 *speed, 450 u16 *duplex) 451{ 452 struct e1000_phy_info *phy = &hw->phy; 453 s32 ret_val; 454 u16 data; 455 456 DEBUGFUNC("e1000_get_link_up_info_82541"); 457 458 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed, duplex); 459 if (ret_val) 460 goto out; 461 462 if (!phy->speed_downgraded) 463 goto out; 464 465 /* 466 * IGP01 PHY may advertise full duplex operation after speed 467 * downgrade even if it is operating at half duplex. 468 * Here we set the duplex settings to match the duplex in the 469 * link partner's capabilities. 470 */ 471 ret_val = phy->ops.read_reg(hw, PHY_AUTONEG_EXP, &data); 472 if (ret_val) 473 goto out; 474 475 if (!(data & NWAY_ER_LP_NWAY_CAPS)) { 476 *duplex = HALF_DUPLEX; 477 } else { 478 ret_val = phy->ops.read_reg(hw, PHY_LP_ABILITY, &data); 479 if (ret_val) 480 goto out; 481 482 if (*speed == SPEED_100) { 483 if (!(data & NWAY_LPAR_100TX_FD_CAPS)) 484 *duplex = HALF_DUPLEX; 485 } else if (*speed == SPEED_10) { 486 if (!(data & NWAY_LPAR_10T_FD_CAPS)) 487 *duplex = HALF_DUPLEX; 488 } 489 } 490 491out: 492 return ret_val; 493} 494 495/** 496 * e1000_phy_hw_reset_82541 - PHY hardware reset 497 * @hw: pointer to the HW structure 498 * 499 * Verify the reset block is not blocking us from resetting. Acquire 500 * semaphore (if necessary) and read/set/write the device control reset 501 * bit in the PHY. Wait the appropriate delay time for the device to 502 * reset and release the semaphore (if necessary). 503 **/ 504static s32 e1000_phy_hw_reset_82541(struct e1000_hw *hw) 505{ 506 s32 ret_val; 507 u32 ledctl; 508 509 DEBUGFUNC("e1000_phy_hw_reset_82541"); 510 511 ret_val = e1000_phy_hw_reset_generic(hw); 512 if (ret_val) 513 goto out; 514 515 e1000_phy_init_script_82541(hw); 516 517 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) { 518 /* Configure activity LED after PHY reset */ 519 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 520 ledctl &= IGP_ACTIVITY_LED_MASK; 521 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 522 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 523 } 524 525out: 526 return ret_val; 527} 528 529/** 530 * e1000_setup_copper_link_82541 - Configure copper link settings 531 * @hw: pointer to the HW structure 532 * 533 * Calls the appropriate function to configure the link for auto-neg or forced 534 * speed and duplex. Then we check for link, once link is established calls 535 * to configure collision distance and flow control are called. If link is 536 * not established, we return -E1000_ERR_PHY (-2). 537 **/ 538static s32 e1000_setup_copper_link_82541(struct e1000_hw *hw) 539{ 540 struct e1000_phy_info *phy = &hw->phy; 541 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 542 s32 ret_val; 543 u32 ctrl, ledctl; 544 545 DEBUGFUNC("e1000_setup_copper_link_82541"); 546 547 ctrl = E1000_READ_REG(hw, E1000_CTRL); 548 ctrl |= E1000_CTRL_SLU; 549 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX); 550 E1000_WRITE_REG(hw, E1000_CTRL, ctrl); 551 552 /* Earlier revs of the IGP phy require us to force MDI. */ 553 if (hw->mac.type == e1000_82541 || hw->mac.type == e1000_82547) { 554 dev_spec->dsp_config = e1000_dsp_config_disabled; 555 phy->mdix = 1; 556 } else { 557 dev_spec->dsp_config = e1000_dsp_config_enabled; 558 } 559 560 ret_val = e1000_copper_link_setup_igp(hw); 561 if (ret_val) 562 goto out; 563 564 if (hw->mac.autoneg) { 565 if (dev_spec->ffe_config == e1000_ffe_config_active) 566 dev_spec->ffe_config = e1000_ffe_config_enabled; 567 } 568 569 /* Configure activity LED after Phy reset */ 570 ledctl = E1000_READ_REG(hw, E1000_LEDCTL); 571 ledctl &= IGP_ACTIVITY_LED_MASK; 572 ledctl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE); 573 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl); 574 575 ret_val = e1000_setup_copper_link_generic(hw); 576 577out: 578 return ret_val; 579} 580 581/** 582 * e1000_check_for_link_82541 - Check/Store link connection 583 * @hw: pointer to the HW structure 584 * 585 * This checks the link condition of the adapter and stores the 586 * results in the hw->mac structure. 587 **/ 588static s32 e1000_check_for_link_82541(struct e1000_hw *hw) 589{ 590 struct e1000_mac_info *mac = &hw->mac; 591 s32 ret_val; 592 bool link; 593 594 DEBUGFUNC("e1000_check_for_link_82541"); 595 596 /* 597 * We only want to go out to the PHY registers to see if Auto-Neg 598 * has completed and/or if our link status has changed. The 599 * get_link_status flag is set upon receiving a Link Status 600 * Change or Rx Sequence Error interrupt. 601 */ 602 if (!mac->get_link_status) { 603 ret_val = E1000_SUCCESS; 604 goto out; 605 } 606 607 /* 608 * First we want to see if the MII Status Register reports 609 * link. If so, then we want to get the current speed/duplex 610 * of the PHY. 611 */ 612 ret_val = e1000_phy_has_link_generic(hw, 1, 0, &link); 613 if (ret_val) 614 goto out; 615 616 if (!link) { 617 ret_val = e1000_config_dsp_after_link_change_82541(hw, FALSE); 618 goto out; /* No link detected */ 619 } 620 621 mac->get_link_status = FALSE; 622 623 /* 624 * Check if there was DownShift, must be checked 625 * immediately after link-up 626 */ 627 e1000_check_downshift_generic(hw); 628 629 /* 630 * If we are forcing speed/duplex, then we simply return since 631 * we have already determined whether we have link or not. 632 */ 633 if (!mac->autoneg) { 634 ret_val = -E1000_ERR_CONFIG; 635 goto out; 636 } 637 638 ret_val = e1000_config_dsp_after_link_change_82541(hw, TRUE); 639 640 /* 641 * Auto-Neg is enabled. Auto Speed Detection takes care 642 * of MAC speed/duplex configuration. So we only need to 643 * configure Collision Distance in the MAC. 644 */ 645 mac->ops.config_collision_dist(hw); 646 647 /* 648 * Configure Flow Control now that Auto-Neg has completed. 649 * First, we need to restore the desired flow control 650 * settings because we may have had to re-autoneg with a 651 * different link partner. 652 */ 653 ret_val = e1000_config_fc_after_link_up_generic(hw); 654 if (ret_val) { 655 DEBUGOUT("Error configuring flow control\n"); 656 } 657 658out: 659 return ret_val; 660} 661 662/** 663 * e1000_config_dsp_after_link_change_82541 - Config DSP after link 664 * @hw: pointer to the HW structure 665 * @link_up: boolean flag for link up status 666 * 667 * Return E1000_ERR_PHY when failing to read/write the PHY, else E1000_SUCCESS 668 * at any other case. 669 * 670 * 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a 671 * gigabit link is achieved to improve link quality. 672 **/ 673static s32 e1000_config_dsp_after_link_change_82541(struct e1000_hw *hw, 674 bool link_up) 675{ 676 struct e1000_phy_info *phy = &hw->phy; 677 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 678 s32 ret_val; 679 u32 idle_errs = 0; 680 u16 phy_data, phy_saved_data, speed, duplex, i; 681 u16 ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20; 682 u16 dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 683 {IGP01E1000_PHY_AGC_PARAM_A, 684 IGP01E1000_PHY_AGC_PARAM_B, 685 IGP01E1000_PHY_AGC_PARAM_C, 686 IGP01E1000_PHY_AGC_PARAM_D}; 687 688 DEBUGFUNC("e1000_config_dsp_after_link_change_82541"); 689 690 if (link_up) { 691 ret_val = hw->mac.ops.get_link_up_info(hw, &speed, &duplex); 692 if (ret_val) { 693 DEBUGOUT("Error getting link speed and duplex\n"); 694 goto out; 695 } 696 697 if (speed != SPEED_1000) { 698 ret_val = E1000_SUCCESS; 699 goto out; 700 } 701 702 ret_val = phy->ops.get_cable_length(hw); 703 if (ret_val) 704 goto out; 705 706 if ((dev_spec->dsp_config == e1000_dsp_config_enabled) && 707 phy->min_cable_length >= 50) { 708 709 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 710 ret_val = phy->ops.read_reg(hw, 711 dsp_reg_array[i], 712 &phy_data); 713 if (ret_val) 714 goto out; 715 716 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 717 718 ret_val = phy->ops.write_reg(hw, 719 dsp_reg_array[i], 720 phy_data); 721 if (ret_val) 722 goto out; 723 } 724 dev_spec->dsp_config = e1000_dsp_config_activated; 725 } 726 727 if ((dev_spec->ffe_config != e1000_ffe_config_enabled) || 728 (phy->min_cable_length >= 50)) { 729 ret_val = E1000_SUCCESS; 730 goto out; 731 } 732 733 /* clear previous idle error counts */ 734 ret_val = phy->ops.read_reg(hw, PHY_1000T_STATUS, &phy_data); 735 if (ret_val) 736 goto out; 737 738 for (i = 0; i < ffe_idle_err_timeout; i++) { 739 usec_delay(1000); 740 ret_val = phy->ops.read_reg(hw, 741 PHY_1000T_STATUS, 742 &phy_data); 743 if (ret_val) 744 goto out; 745 746 idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT); 747 if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) { 748 dev_spec->ffe_config = e1000_ffe_config_active; 749 750 ret_val = phy->ops.write_reg(hw, 751 IGP01E1000_PHY_DSP_FFE, 752 IGP01E1000_PHY_DSP_FFE_CM_CP); 753 if (ret_val) 754 goto out; 755 break; 756 } 757 758 if (idle_errs) 759 ffe_idle_err_timeout = 760 FFE_IDLE_ERR_COUNT_TIMEOUT_100; 761 } 762 } else { 763 if (dev_spec->dsp_config == e1000_dsp_config_activated) { 764 /* 765 * Save off the current value of register 0x2F5B 766 * to be restored at the end of the routines. 767 */ 768 ret_val = phy->ops.read_reg(hw, 769 0x2F5B, 770 &phy_saved_data); 771 if (ret_val) 772 goto out; 773 774 /* Disable the PHY transmitter */ 775 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 776 if (ret_val) 777 goto out; 778 779 msec_delay_irq(20); 780 781 ret_val = phy->ops.write_reg(hw, 782 0x0000, 783 IGP01E1000_IEEE_FORCE_GIG); 784 if (ret_val) 785 goto out; 786 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 787 ret_val = phy->ops.read_reg(hw, 788 dsp_reg_array[i], 789 &phy_data); 790 if (ret_val) 791 goto out; 792 793 phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX; 794 phy_data |= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS; 795 796 ret_val = phy->ops.write_reg(hw, 797 dsp_reg_array[i], 798 phy_data); 799 if (ret_val) 800 goto out; 801 } 802 803 ret_val = phy->ops.write_reg(hw, 804 0x0000, 805 IGP01E1000_IEEE_RESTART_AUTONEG); 806 if (ret_val) 807 goto out; 808 809 msec_delay_irq(20); 810 811 /* Now enable the transmitter */ 812 ret_val = phy->ops.write_reg(hw, 813 0x2F5B, 814 phy_saved_data); 815 if (ret_val) 816 goto out; 817 818 dev_spec->dsp_config = e1000_dsp_config_enabled; 819 } 820 821 if (dev_spec->ffe_config != e1000_ffe_config_active) { 822 ret_val = E1000_SUCCESS; 823 goto out; 824 } 825 826 /* 827 * Save off the current value of register 0x2F5B 828 * to be restored at the end of the routines. 829 */ 830 ret_val = phy->ops.read_reg(hw, 0x2F5B, &phy_saved_data); 831 if (ret_val) 832 goto out; 833 834 /* Disable the PHY transmitter */ 835 ret_val = phy->ops.write_reg(hw, 0x2F5B, 0x0003); 836 if (ret_val) 837 goto out; 838 839 msec_delay_irq(20); 840 841 ret_val = phy->ops.write_reg(hw, 842 0x0000, 843 IGP01E1000_IEEE_FORCE_GIG); 844 if (ret_val) 845 goto out; 846 847 ret_val = phy->ops.write_reg(hw, 848 IGP01E1000_PHY_DSP_FFE, 849 IGP01E1000_PHY_DSP_FFE_DEFAULT); 850 if (ret_val) 851 goto out; 852 853 ret_val = phy->ops.write_reg(hw, 854 0x0000, 855 IGP01E1000_IEEE_RESTART_AUTONEG); 856 if (ret_val) 857 goto out; 858 859 msec_delay_irq(20); 860 861 /* Now enable the transmitter */ 862 ret_val = phy->ops.write_reg(hw, 0x2F5B, phy_saved_data); 863 864 if (ret_val) 865 goto out; 866 867 dev_spec->ffe_config = e1000_ffe_config_enabled; 868 } 869 870out: 871 return ret_val; 872} 873 874/** 875 * e1000_get_cable_length_igp_82541 - Determine cable length for igp PHY 876 * @hw: pointer to the HW structure 877 * 878 * The automatic gain control (agc) normalizes the amplitude of the 879 * received signal, adjusting for the attenuation produced by the 880 * cable. By reading the AGC registers, which represent the 881 * combination of coarse and fine gain value, the value can be put 882 * into a lookup table to obtain the approximate cable length 883 * for each channel. 884 **/ 885static s32 e1000_get_cable_length_igp_82541(struct e1000_hw *hw) 886{ 887 struct e1000_phy_info *phy = &hw->phy; 888 s32 ret_val = E1000_SUCCESS; 889 u16 i, data; 890 u16 cur_agc_value, agc_value = 0; 891 u16 min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE; 892 u16 agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] = 893 {IGP01E1000_PHY_AGC_A, 894 IGP01E1000_PHY_AGC_B, 895 IGP01E1000_PHY_AGC_C, 896 IGP01E1000_PHY_AGC_D}; 897 898 DEBUGFUNC("e1000_get_cable_length_igp_82541"); 899 900 /* Read the AGC registers for all channels */ 901 for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) { 902 ret_val = phy->ops.read_reg(hw, agc_reg_array[i], &data); 903 if (ret_val) 904 goto out; 905 906 cur_agc_value = data >> IGP01E1000_AGC_LENGTH_SHIFT; 907 908 /* Bounds checking */ 909 if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) || 910 (cur_agc_value == 0)) { 911 ret_val = -E1000_ERR_PHY; 912 goto out; 913 } 914 915 agc_value += cur_agc_value; 916 917 if (min_agc_value > cur_agc_value) 918 min_agc_value = cur_agc_value; 919 } 920 921 /* Remove the minimal AGC result for length < 50m */ 922 if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * 50) { 923 agc_value -= min_agc_value; 924 /* Average the three remaining channels for the length. */ 925 agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1); 926 } else { 927 /* Average the channels for the length. */ 928 agc_value /= IGP01E1000_PHY_CHANNEL_NUM; 929 } 930 931 phy->min_cable_length = (e1000_igp_cable_length_table[agc_value] > 932 IGP01E1000_AGC_RANGE) 933 ? (e1000_igp_cable_length_table[agc_value] - 934 IGP01E1000_AGC_RANGE) 935 : 0; 936 phy->max_cable_length = e1000_igp_cable_length_table[agc_value] + 937 IGP01E1000_AGC_RANGE; 938 939 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2; 940 941out: 942 return ret_val; 943} 944 945/** 946 * e1000_set_d3_lplu_state_82541 - Sets low power link up state for D3 947 * @hw: pointer to the HW structure 948 * @active: boolean used to enable/disable lplu 949 * 950 * Success returns 0, Failure returns 1 951 * 952 * The low power link up (lplu) state is set to the power management level D3 953 * and SmartSpeed is disabled when active is TRUE, else clear lplu for D3 954 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU 955 * is used during Dx states where the power conservation is most important. 956 * During driver activity, SmartSpeed should be enabled so performance is 957 * maintained. 958 **/ 959static s32 e1000_set_d3_lplu_state_82541(struct e1000_hw *hw, bool active) 960{ 961 struct e1000_phy_info *phy = &hw->phy; 962 s32 ret_val; 963 u16 data; 964 965 DEBUGFUNC("e1000_set_d3_lplu_state_82541"); 966 967 switch (hw->mac.type) { 968 case e1000_82541_rev_2: 969 case e1000_82547_rev_2: 970 break; 971 default: 972 ret_val = e1000_set_d3_lplu_state_generic(hw, active); 973 goto out; 974 break; 975 } 976 977 ret_val = phy->ops.read_reg(hw, IGP01E1000_GMII_FIFO, &data); 978 if (ret_val) 979 goto out; 980 981 if (!active) { 982 data &= ~IGP01E1000_GMII_FLEX_SPD; 983 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 984 if (ret_val) 985 goto out; 986 987 /* 988 * LPLU and SmartSpeed are mutually exclusive. LPLU is used 989 * during Dx states where the power conservation is most 990 * important. During driver activity we should enable 991 * SmartSpeed, so performance is maintained. 992 */ 993 if (phy->smart_speed == e1000_smart_speed_on) { 994 ret_val = phy->ops.read_reg(hw, 995 IGP01E1000_PHY_PORT_CONFIG, 996 &data); 997 if (ret_val) 998 goto out; 999 1000 data |= IGP01E1000_PSCFR_SMART_SPEED; 1001 ret_val = phy->ops.write_reg(hw, 1002 IGP01E1000_PHY_PORT_CONFIG, 1003 data); 1004 if (ret_val) 1005 goto out; 1006 } else if (phy->smart_speed == e1000_smart_speed_off) { 1007 ret_val = phy->ops.read_reg(hw, 1008 IGP01E1000_PHY_PORT_CONFIG, 1009 &data); 1010 if (ret_val) 1011 goto out; 1012 1013 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1014 ret_val = phy->ops.write_reg(hw, 1015 IGP01E1000_PHY_PORT_CONFIG, 1016 data); 1017 if (ret_val) 1018 goto out; 1019 } 1020 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) || 1021 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) || 1022 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) { 1023 data |= IGP01E1000_GMII_FLEX_SPD; 1024 ret_val = phy->ops.write_reg(hw, IGP01E1000_GMII_FIFO, data); 1025 if (ret_val) 1026 goto out; 1027 1028 /* When LPLU is enabled, we should disable SmartSpeed */ 1029 ret_val = phy->ops.read_reg(hw, 1030 IGP01E1000_PHY_PORT_CONFIG, 1031 &data); 1032 if (ret_val) 1033 goto out; 1034 1035 data &= ~IGP01E1000_PSCFR_SMART_SPEED; 1036 ret_val = phy->ops.write_reg(hw, 1037 IGP01E1000_PHY_PORT_CONFIG, 1038 data); 1039 } 1040 1041out: 1042 return ret_val; 1043} 1044 1045/** 1046 * e1000_setup_led_82541 - Configures SW controllable LED 1047 * @hw: pointer to the HW structure 1048 * 1049 * This prepares the SW controllable LED for use and saves the current state 1050 * of the LED so it can be later restored. 1051 **/ 1052static s32 e1000_setup_led_82541(struct e1000_hw *hw) 1053{ 1054 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1055 s32 ret_val; 1056 1057 DEBUGFUNC("e1000_setup_led_82541"); 1058 1059 ret_val = hw->phy.ops.read_reg(hw, 1060 IGP01E1000_GMII_FIFO, 1061 &dev_spec->spd_default); 1062 if (ret_val) 1063 goto out; 1064 1065 ret_val = hw->phy.ops.write_reg(hw, 1066 IGP01E1000_GMII_FIFO, 1067 (u16)(dev_spec->spd_default & 1068 ~IGP01E1000_GMII_SPD)); 1069 if (ret_val) 1070 goto out; 1071 1072 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_mode1); 1073 1074out: 1075 return ret_val; 1076} 1077 1078/** 1079 * e1000_cleanup_led_82541 - Set LED config to default operation 1080 * @hw: pointer to the HW structure 1081 * 1082 * Remove the current LED configuration and set the LED configuration 1083 * to the default value, saved from the EEPROM. 1084 **/ 1085static s32 e1000_cleanup_led_82541(struct e1000_hw *hw) 1086{ 1087 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1088 s32 ret_val; 1089 1090 DEBUGFUNC("e1000_cleanup_led_82541"); 1091 1092 ret_val = hw->phy.ops.write_reg(hw, 1093 IGP01E1000_GMII_FIFO, 1094 dev_spec->spd_default); 1095 if (ret_val) 1096 goto out; 1097 1098 E1000_WRITE_REG(hw, E1000_LEDCTL, hw->mac.ledctl_default); 1099 1100out: 1101 return ret_val; 1102} 1103 1104/** 1105 * e1000_phy_init_script_82541 - Initialize GbE PHY 1106 * @hw: pointer to the HW structure 1107 * 1108 * Initializes the IGP PHY. 1109 **/ 1110static s32 e1000_phy_init_script_82541(struct e1000_hw *hw) 1111{ 1112 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1113 u32 ret_val; 1114 u16 phy_saved_data; 1115 1116 DEBUGFUNC("e1000_phy_init_script_82541"); 1117 1118 if (!dev_spec->phy_init_script) { 1119 ret_val = E1000_SUCCESS; 1120 goto out; 1121 } 1122 1123 /* Delay after phy reset to enable NVM configuration to load */ 1124 msec_delay(20); 1125 1126 /* 1127 * Save off the current value of register 0x2F5B to be restored at 1128 * the end of this routine. 1129 */ 1130 ret_val = hw->phy.ops.read_reg(hw, 0x2F5B, &phy_saved_data); 1131 1132 /* Disabled the PHY transmitter */ 1133 hw->phy.ops.write_reg(hw, 0x2F5B, 0x0003); 1134 1135 msec_delay(20); 1136 1137 hw->phy.ops.write_reg(hw, 0x0000, 0x0140); 1138 1139 msec_delay(5); 1140 1141 switch (hw->mac.type) { 1142 case e1000_82541: 1143 case e1000_82547: 1144 hw->phy.ops.write_reg(hw, 0x1F95, 0x0001); 1145 1146 hw->phy.ops.write_reg(hw, 0x1F71, 0xBD21); 1147 1148 hw->phy.ops.write_reg(hw, 0x1F79, 0x0018); 1149 1150 hw->phy.ops.write_reg(hw, 0x1F30, 0x1600); 1151 1152 hw->phy.ops.write_reg(hw, 0x1F31, 0x0014); 1153 1154 hw->phy.ops.write_reg(hw, 0x1F32, 0x161C); 1155 1156 hw->phy.ops.write_reg(hw, 0x1F94, 0x0003); 1157 1158 hw->phy.ops.write_reg(hw, 0x1F96, 0x003F); 1159 1160 hw->phy.ops.write_reg(hw, 0x2010, 0x0008); 1161 break; 1162 case e1000_82541_rev_2: 1163 case e1000_82547_rev_2: 1164 hw->phy.ops.write_reg(hw, 0x1F73, 0x0099); 1165 break; 1166 default: 1167 break; 1168 } 1169 1170 hw->phy.ops.write_reg(hw, 0x0000, 0x3300); 1171 1172 msec_delay(20); 1173 1174 /* Now enable the transmitter */ 1175 hw->phy.ops.write_reg(hw, 0x2F5B, phy_saved_data); 1176 1177 if (hw->mac.type == e1000_82547) { 1178 u16 fused, fine, coarse; 1179 1180 /* Move to analog registers page */ 1181 hw->phy.ops.read_reg(hw, 1182 IGP01E1000_ANALOG_SPARE_FUSE_STATUS, 1183 &fused); 1184 1185 if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) { 1186 hw->phy.ops.read_reg(hw, 1187 IGP01E1000_ANALOG_FUSE_STATUS, 1188 &fused); 1189 1190 fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK; 1191 coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK; 1192 1193 if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) { 1194 coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10; 1195 fine -= IGP01E1000_ANALOG_FUSE_FINE_1; 1196 } else if (coarse == 1197 IGP01E1000_ANALOG_FUSE_COARSE_THRESH) 1198 fine -= IGP01E1000_ANALOG_FUSE_FINE_10; 1199 1200 fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) | 1201 (fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) | 1202 (coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK); 1203 1204 hw->phy.ops.write_reg(hw, 1205 IGP01E1000_ANALOG_FUSE_CONTROL, 1206 fused); 1207 hw->phy.ops.write_reg(hw, 1208 IGP01E1000_ANALOG_FUSE_BYPASS, 1209 IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL); 1210 } 1211 } 1212 1213out: 1214 return ret_val; 1215} 1216 1217/** 1218 * e1000_init_script_state_82541 - Enable/Disable PHY init script 1219 * @hw: pointer to the HW structure 1220 * @state: boolean value used to enable/disable PHY init script 1221 * 1222 * Allows the driver to enable/disable the PHY init script, if the PHY is an 1223 * IGP PHY. 1224 **/ 1225void e1000_init_script_state_82541(struct e1000_hw *hw, bool state) 1226{ 1227 struct e1000_dev_spec_82541 *dev_spec = &hw->dev_spec._82541; 1228 1229 DEBUGFUNC("e1000_init_script_state_82541"); 1230 1231 if (hw->phy.type != e1000_phy_igp) { 1232 DEBUGOUT("Initialization script not necessary.\n"); 1233 goto out; 1234 } 1235 1236 dev_spec->phy_init_script = state; 1237 1238out: 1239 return; 1240} 1241 1242/** 1243 * e1000_power_down_phy_copper_82541 - Remove link in case of PHY power down 1244 * @hw: pointer to the HW structure 1245 * 1246 * In the case of a PHY power down to save power, or to turn off link during a 1247 * driver unload, or wake on lan is not enabled, remove the link. 1248 **/ 1249static void e1000_power_down_phy_copper_82541(struct e1000_hw *hw) 1250{ 1251 /* If the management interface is not enabled, then power down */ 1252 if (!(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_SMBUS_EN)) 1253 e1000_power_down_phy_copper(hw); 1254 1255 return; 1256} 1257 1258/** 1259 * e1000_clear_hw_cntrs_82541 - Clear device specific hardware counters 1260 * @hw: pointer to the HW structure 1261 * 1262 * Clears the hardware counters by reading the counter registers. 1263 **/ 1264static void e1000_clear_hw_cntrs_82541(struct e1000_hw *hw) 1265{ 1266 DEBUGFUNC("e1000_clear_hw_cntrs_82541"); 1267 1268 e1000_clear_hw_cntrs_base_generic(hw); 1269 1270 E1000_READ_REG(hw, E1000_PRC64); 1271 E1000_READ_REG(hw, E1000_PRC127); 1272 E1000_READ_REG(hw, E1000_PRC255); 1273 E1000_READ_REG(hw, E1000_PRC511); 1274 E1000_READ_REG(hw, E1000_PRC1023); 1275 E1000_READ_REG(hw, E1000_PRC1522); 1276 E1000_READ_REG(hw, E1000_PTC64); 1277 E1000_READ_REG(hw, E1000_PTC127); 1278 E1000_READ_REG(hw, E1000_PTC255); 1279 E1000_READ_REG(hw, E1000_PTC511); 1280 E1000_READ_REG(hw, E1000_PTC1023); 1281 E1000_READ_REG(hw, E1000_PTC1522); 1282 1283 E1000_READ_REG(hw, E1000_ALGNERRC); 1284 E1000_READ_REG(hw, E1000_RXERRC); 1285 E1000_READ_REG(hw, E1000_TNCRS); 1286 E1000_READ_REG(hw, E1000_CEXTERR); 1287 E1000_READ_REG(hw, E1000_TSCTC); 1288 E1000_READ_REG(hw, E1000_TSCTFC); 1289 1290 E1000_READ_REG(hw, E1000_MGTPRC); 1291 E1000_READ_REG(hw, E1000_MGTPDC); 1292 E1000_READ_REG(hw, E1000_MGTPTC); 1293} 1294 1295/** 1296 * e1000_read_mac_addr_82541 - Read device MAC address 1297 * @hw: pointer to the HW structure 1298 * 1299 * Reads the device MAC address from the EEPROM and stores the value. 1300 **/ 1301static s32 e1000_read_mac_addr_82541(struct e1000_hw *hw) 1302{ 1303 s32 ret_val = E1000_SUCCESS; 1304 u16 offset, nvm_data, i; 1305 1306 DEBUGFUNC("e1000_read_mac_addr"); 1307 1308 for (i = 0; i < ETH_ADDR_LEN; i += 2) { 1309 offset = i >> 1; 1310 ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data); 1311 if (ret_val) { 1312 DEBUGOUT("NVM Read Error\n"); 1313 goto out; 1314 } 1315 hw->mac.perm_addr[i] = (u8)(nvm_data & 0xFF); 1316 hw->mac.perm_addr[i+1] = (u8)(nvm_data >> 8); 1317 } 1318 1319 for (i = 0; i < ETH_ADDR_LEN; i++) 1320 hw->mac.addr[i] = hw->mac.perm_addr[i]; 1321 1322out: 1323 return ret_val; 1324} 1325
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