1/******************************************************************************
2
3 Copyright (c) 2001-2015, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_82541.c 287990 2015-09-19 18:22:59Z sbruno $*/
34
35/*
36 * 82541EI Gigabit Ethernet Controller
37 * 82541ER Gigabit Ethernet Controller
38 * 82541GI Gigabit Ethernet Controller
39 * 82541PI Gigabit Ethernet Controller
40 * 82547EI Gigabit Ethernet Controller
41 * 82547GI Gigabit Ethernet Controller

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80
81/**
82 * e1000_init_phy_params_82541 - Init PHY func ptrs.
83 * @hw: pointer to the HW structure
84 **/
85static s32 e1000_init_phy_params_82541(struct e1000_hw *hw)
86{
87 struct e1000_phy_info *phy = &hw->phy;
88 s32 ret_val = E1000_SUCCESS;
89
90 DEBUGFUNC("e1000_init_phy_params_82541");
91
92 phy->addr = 1;
93 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
94 phy->reset_delay_us = 10000;
95 phy->type = e1000_phy_igp;
96

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290/**
291 * e1000_reset_hw_82541 - Reset hardware
292 * @hw: pointer to the HW structure
293 *
294 * This resets the hardware into a known state.
295 **/
296static s32 e1000_reset_hw_82541(struct e1000_hw *hw)
297{
298 u32 ledctl, ctrl, icr, manc;
299
300 DEBUGFUNC("e1000_reset_hw_82541");
301
302 DEBUGOUT("Masking off all interrupts\n");
303 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
304
305 E1000_WRITE_REG(hw, E1000_RCTL, 0);
306 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);

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312 */
313 msec_delay(10);
314
315 ctrl = E1000_READ_REG(hw, E1000_CTRL);
316
317 /* Must reset the Phy before resetting the MAC */
318 if ((hw->mac.type == e1000_82541) || (hw->mac.type == e1000_82547)) {
319 E1000_WRITE_REG(hw, E1000_CTRL, (ctrl | E1000_CTRL_PHY_RST));
320 msec_delay(5);
321 }
322
323 DEBUGOUT("Issuing a global reset to 82541/82547 MAC\n");
324 switch (hw->mac.type) {
325 case e1000_82541:
326 case e1000_82541_rev_2:
327 /*

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354 E1000_WRITE_REG(hw, E1000_LEDCTL, ledctl);
355 }
356
357 /* Once again, mask the interrupts */
358 DEBUGOUT("Masking off all interrupts\n");
359 E1000_WRITE_REG(hw, E1000_IMC, 0xFFFFFFFF);
360
361 /* Clear any pending interrupt events. */
362 icr = E1000_READ_REG(hw, E1000_ICR);
363
364 return E1000_SUCCESS;
365}
366
367/**
368 * e1000_init_hw_82541 - Initialize hardware
369 * @hw: pointer to the HW structure
370 *

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