Cross Reference: /freebsd-11.0-release/sys/dev/e1000/e1000

1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/

33/*$FreeBSD: head/sys/dev/em/e1000_80003es2lan.h 169589 2007-05-16 00:14:23Z jfv $*/

33/* $FreeBSD: head/sys/dev/em/e1000_80003es2lan.h 173788 2007-11-20 21:41:22Z jfv $ */

34
35
36#ifndef _E1000_80003ES2LAN_H_
37#define _E1000_80003ES2LAN_H_
38
39#define E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL 0x00
40#define E1000_KMRNCTRLSTA_OFFSET_INB_CTRL 0x02
41#define E1000_KMRNCTRLSTA_OFFSET_HD_CTRL 0x10

42#define E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE 0x1F

42
43#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
44#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
45#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
46
47#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
48#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000

43
44#define E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS 0x0008
45#define E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS 0x0800
46#define E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING 0x0010
47
48#define E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT 0x0004
49#define E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT 0x0000

50#define E1000_KMRNCTRLSTA_OPMODE_E_IDLE 0x2000

49
50#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

51
52#define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */

51#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000

53#define DEFAULT_TCTL_EXT_GCEX_80003ES2LAN 0x00010000

52

54

53#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
54#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9

55#define DEFAULT_TIPG_IPGT_1000_80003ES2LAN 0x8
56#define DEFAULT_TIPG_IPGT_10_100_80003ES2LAN 0x9

55
56/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
57#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
58#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
59#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
60#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
61#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
62
63/* PHY Specific Control Register 2 (Page 0, Register 26) */

57
58/* GG82563 PHY Specific Status Register (Page 0, Register 16 */
59#define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Reversal Disabled */
60#define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060
61#define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI */
62#define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX */
63#define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Auto crossover */
64
65/* PHY Specific Control Register 2 (Page 0, Register 26) */

64#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000

66#define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000

65 /* 1=Reverse Auto-Negotiation */
66
67/* MAC Specific Control Register (Page 2, Register 21) */
68/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

67 /* 1=Reverse Auto-Negotiation */
68
69/* MAC Specific Control Register (Page 2, Register 21) */
70/* Tx clock speed for Link Down and 1000BASE-T for the following speeds */

69#define GG82563_MSCR_TX_CLK_MASK 0x0007
70#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
71#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
72#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006
73#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007

71#define GG82563_MSCR_TX_CLK_MASK 0x0007
72#define GG82563_MSCR_TX_CLK_10MBPS_2_5 0x0004
73#define GG82563_MSCR_TX_CLK_100MBPS_25 0x0005
74#define GG82563_MSCR_TX_CLK_1000MBPS_2_5 0x0006
75#define GG82563_MSCR_TX_CLK_1000MBPS_25 0x0007

74

76

75#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */

77#define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */

76
77/* DSP Distance Register (Page 5, Register 26) */

78
79/* DSP Distance Register (Page 5, Register 26) */

78#define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M;
79 1 = 50-80M;
80 2 = 80-110M;
81 3 = 110-140M;
82 4 = >140M */

80/*
81 * 0 = <50M
82 * 1 = 50-80M
83 * 2 = 80-100M
84 * 3 = 110-140M
85 * 4 = >140M
86 */
87#define GG82563_DSPD_CABLE_LENGTH 0x0007

83
84/* Kumeran Mode Control Register (Page 193, Register 16) */

88
89/* Kumeran Mode Control Register (Page 193, Register 16) */

85#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800

90#define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800

86
87/* Max number of times Kumeran read/write should be validated */

91
92/* Max number of times Kumeran read/write should be validated */

88#define GG82563_MAX_KMRN_RETRY 0x5

93#define GG82563_MAX_KMRN_RETRY 0x5

89
90/* Power Management Control Register (Page 193, Register 20) */

94
95/* Power Management Control Register (Page 193, Register 20) */

91#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001

96#define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001

92 /* 1=Enable SERDES Electrical Idle */
93
94/* In-Band Control Register (Page 194, Register 18) */

97 /* 1=Enable SERDES Electrical Idle */
98
99/* In-Band Control Register (Page 194, Register 18) */

95#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */

100#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding */