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e1000_80003es2lan.c (218588) e1000_80003es2lan.c (228386)
1/******************************************************************************
2
1/******************************************************************************
2
3 Copyright (c) 2001-2010, Intel Corporation
3 Copyright (c) 2001-2011, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

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25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11

--- 13 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 218588 2011-02-12 00:07:40Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 228386 2011-12-10 06:55:02Z jfv $*/
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41
42static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
43static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
44static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
45static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
46static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
47static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
48static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
49static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41
42static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw);
43static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw);
44static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw);
45static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw);
46static void e1000_release_phy_80003es2lan(struct e1000_hw *hw);
47static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw);
48static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw);
49static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
50 u32 offset,
51 u16 *data);
50 u32 offset,
51 u16 *data);
52static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
52static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
53 u32 offset,
54 u16 data);
53 u32 offset,
54 u16 data);
55static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
55static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
56 u16 words, u16 *data);
56 u16 words, u16 *data);
57static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
58static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
59static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
60static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
57static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw);
58static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw);
59static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw);
60static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
61 u16 *duplex);
61 u16 *duplex);
62static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
63static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
64static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
65static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
66static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
67static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
68static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
69static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
70static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
62static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw);
63static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw);
64static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
65static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
66static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
67static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
68static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
69static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw);
70static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
71 u16 *data);
71 u16 *data);
72static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
72static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
73 u16 data);
73 u16 data);
74static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
75static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
76static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
77static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80/*
81 * A table for the GG82563 cable length where the range is defined
82 * with a lower bound at "index" and the upper bound at
83 * "index + 5".
84 */
85static const u16 e1000_gg82563_cable_length_table[] = {
86 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
87#define GG82563_CABLE_LENGTH_TABLE_SIZE \
74static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
75static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
76static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
77static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw);
78static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
79
80/*
81 * A table for the GG82563 cable length where the range is defined
82 * with a lower bound at "index" and the upper bound at
83 * "index + 5".
84 */
85static const u16 e1000_gg82563_cable_length_table[] = {
86 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
87#define GG82563_CABLE_LENGTH_TABLE_SIZE \
88 (sizeof(e1000_gg82563_cable_length_table) / \
89 sizeof(e1000_gg82563_cable_length_table[0]))
88 (sizeof(e1000_gg82563_cable_length_table) / \
89 sizeof(e1000_gg82563_cable_length_table[0]))
90
91/**
92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
93 * @hw: pointer to the HW structure
94 **/
95static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
96{
97 struct e1000_phy_info *phy = &hw->phy;
98 s32 ret_val = E1000_SUCCESS;
99
100 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
101
102 if (hw->phy.media_type != e1000_media_type_copper) {
90
91/**
92 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
93 * @hw: pointer to the HW structure
94 **/
95static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
96{
97 struct e1000_phy_info *phy = &hw->phy;
98 s32 ret_val = E1000_SUCCESS;
99
100 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
101
102 if (hw->phy.media_type != e1000_media_type_copper) {
103 phy->type = e1000_phy_none;
103 phy->type = e1000_phy_none;
104 goto out;
105 } else {
106 phy->ops.power_up = e1000_power_up_phy_copper;
107 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
108 }
109
104 goto out;
105 } else {
106 phy->ops.power_up = e1000_power_up_phy_copper;
107 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
108 }
109
110 phy->addr = 1;
111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
112 phy->reset_delay_us = 100;
113 phy->type = e1000_phy_gg82563;
110 phy->addr = 1;
111 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
112 phy->reset_delay_us = 100;
113 phy->type = e1000_phy_gg82563;
114
114
115 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
116 phy->ops.check_polarity = e1000_check_polarity_m88;
117 phy->ops.check_reset_block = e1000_check_reset_block_generic;
118 phy->ops.commit = e1000_phy_sw_reset_generic;
119 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
120 phy->ops.get_info = e1000_get_phy_info_m88;
121 phy->ops.release = e1000_release_phy_80003es2lan;
122 phy->ops.reset = e1000_phy_hw_reset_generic;
123 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
115 phy->ops.acquire = e1000_acquire_phy_80003es2lan;
116 phy->ops.check_polarity = e1000_check_polarity_m88;
117 phy->ops.check_reset_block = e1000_check_reset_block_generic;
118 phy->ops.commit = e1000_phy_sw_reset_generic;
119 phy->ops.get_cfg_done = e1000_get_cfg_done_80003es2lan;
120 phy->ops.get_info = e1000_get_phy_info_m88;
121 phy->ops.release = e1000_release_phy_80003es2lan;
122 phy->ops.reset = e1000_phy_hw_reset_generic;
123 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
124
125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
124
125 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan;
126 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
127 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
128 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
126 phy->ops.get_cable_length = e1000_get_cable_length_80003es2lan;
127 phy->ops.read_reg = e1000_read_phy_reg_gg82563_80003es2lan;
128 phy->ops.write_reg = e1000_write_phy_reg_gg82563_80003es2lan;
129
129
130 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
130 phy->ops.cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan;
131
132 /* This can only be done after all function pointers are setup. */
133 ret_val = e1000_get_phy_id(hw);
134
135 /* Verify phy id */
136 if (phy->id != GG82563_E_PHY_ID) {
137 ret_val = -E1000_ERR_PHY;
138 goto out;

--- 10 unchanged lines hidden (view full) ---

149static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
150{
151 struct e1000_nvm_info *nvm = &hw->nvm;
152 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
153 u16 size;
154
155 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
156
131
132 /* This can only be done after all function pointers are setup. */
133 ret_val = e1000_get_phy_id(hw);
134
135 /* Verify phy id */
136 if (phy->id != GG82563_E_PHY_ID) {
137 ret_val = -E1000_ERR_PHY;
138 goto out;

--- 10 unchanged lines hidden (view full) ---

149static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
150{
151 struct e1000_nvm_info *nvm = &hw->nvm;
152 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
153 u16 size;
154
155 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
156
157 nvm->opcode_bits = 8;
158 nvm->delay_usec = 1;
157 nvm->opcode_bits = 8;
158 nvm->delay_usec = 1;
159 switch (nvm->override) {
160 case e1000_nvm_override_spi_large:
159 switch (nvm->override) {
160 case e1000_nvm_override_spi_large:
161 nvm->page_size = 32;
161 nvm->page_size = 32;
162 nvm->address_bits = 16;
163 break;
164 case e1000_nvm_override_spi_small:
162 nvm->address_bits = 16;
163 break;
164 case e1000_nvm_override_spi_small:
165 nvm->page_size = 8;
165 nvm->page_size = 8;
166 nvm->address_bits = 8;
167 break;
168 default:
166 nvm->address_bits = 8;
167 break;
168 default:
169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 break;
172 }
173
174 nvm->type = e1000_nvm_eeprom_spi;
175
176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 break;
172 }
173
174 nvm->type = e1000_nvm_eeprom_spi;
175
176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
177 E1000_EECD_SIZE_EX_SHIFT);
177 E1000_EECD_SIZE_EX_SHIFT);
178
179 /*
180 * Added to a constant, "size" becomes the left-shift value
181 * for setting word_size.
182 */
183 size += NVM_WORD_SIZE_BASE_SHIFT;
184
185 /* EEPROM access above 16k is unsupported */
186 if (size > 14)
187 size = 14;
178
179 /*
180 * Added to a constant, "size" becomes the left-shift value
181 * for setting word_size.
182 */
183 size += NVM_WORD_SIZE_BASE_SHIFT;
184
185 /* EEPROM access above 16k is unsupported */
186 if (size > 14)
187 size = 14;
188 nvm->word_size = 1 << size;
188 nvm->word_size = 1 << size;
189
190 /* Function Pointers */
189
190 /* Function Pointers */
191 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
192 nvm->ops.read = e1000_read_nvm_eerd;
193 nvm->ops.release = e1000_release_nvm_80003es2lan;
194 nvm->ops.update = e1000_update_nvm_checksum_generic;
191 nvm->ops.acquire = e1000_acquire_nvm_80003es2lan;
192 nvm->ops.read = e1000_read_nvm_eerd;
193 nvm->ops.release = e1000_release_nvm_80003es2lan;
194 nvm->ops.update = e1000_update_nvm_checksum_generic;
195 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
195 nvm->ops.valid_led_default = e1000_valid_led_default_generic;
196 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
197 nvm->ops.write = e1000_write_nvm_80003es2lan;
196 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
197 nvm->ops.write = e1000_write_nvm_80003es2lan;
198
199 return E1000_SUCCESS;
200}
201
202/**
203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/

--- 4 unchanged lines hidden (view full) ---

210 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
211
212 /* Set media type and media-dependent function pointers */
213 switch (hw->device_id) {
214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
215 hw->phy.media_type = e1000_media_type_internal_serdes;
216 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
217 mac->ops.setup_physical_interface =
198
199 return E1000_SUCCESS;
200}
201
202/**
203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/

--- 4 unchanged lines hidden (view full) ---

210 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
211
212 /* Set media type and media-dependent function pointers */
213 switch (hw->device_id) {
214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
215 hw->phy.media_type = e1000_media_type_internal_serdes;
216 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
217 mac->ops.setup_physical_interface =
218 e1000_setup_fiber_serdes_link_generic;
218 e1000_setup_fiber_serdes_link_generic;
219 break;
220 default:
221 hw->phy.media_type = e1000_media_type_copper;
222 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
223 mac->ops.setup_physical_interface =
219 break;
220 default:
221 hw->phy.media_type = e1000_media_type_copper;
222 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
223 mac->ops.setup_physical_interface =
224 e1000_setup_copper_link_80003es2lan;
224 e1000_setup_copper_link_80003es2lan;
225 break;
226 }
227
228 /* Set mta register count */
229 mac->mta_reg_count = 128;
230 /* Set rar entry count */
231 mac->rar_entry_count = E1000_RAR_ENTRIES;
232 /* Set if part includes ASF firmware */
233 mac->asf_firmware_present = TRUE;
234 /* FWSM register */
235 mac->has_fwsm = TRUE;
236 /* ARC supported; valid only if manageability features are enabled. */
225 break;
226 }
227
228 /* Set mta register count */
229 mac->mta_reg_count = 128;
230 /* Set rar entry count */
231 mac->rar_entry_count = E1000_RAR_ENTRIES;
232 /* Set if part includes ASF firmware */
233 mac->asf_firmware_present = TRUE;
234 /* FWSM register */
235 mac->has_fwsm = TRUE;
236 /* ARC supported; valid only if manageability features are enabled. */
237 mac->arc_subsystem_valid =
238 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
239 ? TRUE : FALSE;
237 mac->arc_subsystem_valid = (E1000_READ_REG(hw, E1000_FWSM) &
238 E1000_FWSM_MODE_MASK) ? TRUE : FALSE;
240 /* Adaptive IFS not supported */
241 mac->adaptive_ifs = FALSE;
242
243 /* Function pointers */
244
245 /* bus type/speed/width */
246 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
247 /* reset */

--- 77 unchanged lines hidden (view full) ---

325
326 DEBUGFUNC("e1000_release_phy_80003es2lan");
327
328 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
329 e1000_release_swfw_sync_80003es2lan(hw, mask);
330}
331
332/**
239 /* Adaptive IFS not supported */
240 mac->adaptive_ifs = FALSE;
241
242 /* Function pointers */
243
244 /* bus type/speed/width */
245 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
246 /* reset */

--- 77 unchanged lines hidden (view full) ---

324
325 DEBUGFUNC("e1000_release_phy_80003es2lan");
326
327 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
328 e1000_release_swfw_sync_80003es2lan(hw, mask);
329}
330
331/**
333 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
332 * e1000_acquire_mac_csr_80003es2lan - Acquire right to access Kumeran register
334 * @hw: pointer to the HW structure
335 *
336 * Acquire the semaphore to access the Kumeran interface.
337 *
338 **/
339static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
340{
341 u16 mask;
342
343 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
344
345 mask = E1000_SWFW_CSR_SM;
346
347 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
348}
349
350/**
333 * @hw: pointer to the HW structure
334 *
335 * Acquire the semaphore to access the Kumeran interface.
336 *
337 **/
338static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
339{
340 u16 mask;
341
342 DEBUGFUNC("e1000_acquire_mac_csr_80003es2lan");
343
344 mask = E1000_SWFW_CSR_SM;
345
346 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
347}
348
349/**
351 * e1000_release_mac_csr_80003es2lan - Release rights to access Kumeran Register
350 * e1000_release_mac_csr_80003es2lan - Release right to access Kumeran Register
352 * @hw: pointer to the HW structure
353 *
354 * Release the semaphore used to access the Kumeran interface
355 **/
356static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
357{
358 u16 mask;
359

--- 123 unchanged lines hidden (view full) ---

483 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
484 * @hw: pointer to the HW structure
485 * @offset: offset of the register to read
486 * @data: pointer to the data returned from the operation
487 *
488 * Read the GG82563 PHY register.
489 **/
490static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
351 * @hw: pointer to the HW structure
352 *
353 * Release the semaphore used to access the Kumeran interface
354 **/
355static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
356{
357 u16 mask;
358

--- 123 unchanged lines hidden (view full) ---

482 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
483 * @hw: pointer to the HW structure
484 * @offset: offset of the register to read
485 * @data: pointer to the data returned from the operation
486 *
487 * Read the GG82563 PHY register.
488 **/
489static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
491 u32 offset, u16 *data)
490 u32 offset, u16 *data)
492{
493 s32 ret_val;
494 u32 page_select;
495 u16 temp;
496
497 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
498
499 ret_val = e1000_acquire_phy_80003es2lan(hw);

--- 33 unchanged lines hidden (view full) ---

533 ret_val = -E1000_ERR_PHY;
534 e1000_release_phy_80003es2lan(hw);
535 goto out;
536 }
537
538 usec_delay(200);
539
540 ret_val = e1000_read_phy_reg_mdic(hw,
491{
492 s32 ret_val;
493 u32 page_select;
494 u16 temp;
495
496 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
497
498 ret_val = e1000_acquire_phy_80003es2lan(hw);

--- 33 unchanged lines hidden (view full) ---

532 ret_val = -E1000_ERR_PHY;
533 e1000_release_phy_80003es2lan(hw);
534 goto out;
535 }
536
537 usec_delay(200);
538
539 ret_val = e1000_read_phy_reg_mdic(hw,
541 MAX_PHY_REG_ADDRESS & offset,
542 data);
540 MAX_PHY_REG_ADDRESS & offset,
541 data);
543
544 usec_delay(200);
545 } else {
546 ret_val = e1000_read_phy_reg_mdic(hw,
542
543 usec_delay(200);
544 } else {
545 ret_val = e1000_read_phy_reg_mdic(hw,
547 MAX_PHY_REG_ADDRESS & offset,
548 data);
546 MAX_PHY_REG_ADDRESS & offset,
547 data);
549 }
550
551 e1000_release_phy_80003es2lan(hw);
552
553out:
554 return ret_val;
555}
556
557/**
558 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
559 * @hw: pointer to the HW structure
560 * @offset: offset of the register to read
561 * @data: value to write to the register
562 *
563 * Write to the GG82563 PHY register.
564 **/
565static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
548 }
549
550 e1000_release_phy_80003es2lan(hw);
551
552out:
553 return ret_val;
554}
555
556/**
557 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
558 * @hw: pointer to the HW structure
559 * @offset: offset of the register to read
560 * @data: value to write to the register
561 *
562 * Write to the GG82563 PHY register.
563 **/
564static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
566 u32 offset, u16 data)
565 u32 offset, u16 data)
567{
568 s32 ret_val;
569 u32 page_select;
570 u16 temp;
571
572 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
573
574 ret_val = e1000_acquire_phy_80003es2lan(hw);

--- 33 unchanged lines hidden (view full) ---

608 ret_val = -E1000_ERR_PHY;
609 e1000_release_phy_80003es2lan(hw);
610 goto out;
611 }
612
613 usec_delay(200);
614
615 ret_val = e1000_write_phy_reg_mdic(hw,
566{
567 s32 ret_val;
568 u32 page_select;
569 u16 temp;
570
571 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
572
573 ret_val = e1000_acquire_phy_80003es2lan(hw);

--- 33 unchanged lines hidden (view full) ---

607 ret_val = -E1000_ERR_PHY;
608 e1000_release_phy_80003es2lan(hw);
609 goto out;
610 }
611
612 usec_delay(200);
613
614 ret_val = e1000_write_phy_reg_mdic(hw,
616 MAX_PHY_REG_ADDRESS & offset,
617 data);
615 MAX_PHY_REG_ADDRESS & offset,
616 data);
618
619 usec_delay(200);
620 } else {
621 ret_val = e1000_write_phy_reg_mdic(hw,
617
618 usec_delay(200);
619 } else {
620 ret_val = e1000_write_phy_reg_mdic(hw,
622 MAX_PHY_REG_ADDRESS & offset,
623 data);
621 MAX_PHY_REG_ADDRESS & offset,
622 data);
624 }
625
626 e1000_release_phy_80003es2lan(hw);
627
628out:
629 return ret_val;
630}
631
632/**
633 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
634 * @hw: pointer to the HW structure
635 * @offset: offset of the register to read
636 * @words: number of words to write
637 * @data: buffer of data to write to the NVM
638 *
639 * Write "words" of data to the ESB2 NVM.
640 **/
641static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
623 }
624
625 e1000_release_phy_80003es2lan(hw);
626
627out:
628 return ret_val;
629}
630
631/**
632 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM
633 * @hw: pointer to the HW structure
634 * @offset: offset of the register to read
635 * @words: number of words to write
636 * @data: buffer of data to write to the NVM
637 *
638 * Write "words" of data to the ESB2 NVM.
639 **/
640static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
642 u16 words, u16 *data)
641 u16 words, u16 *data)
643{
644 DEBUGFUNC("e1000_write_nvm_80003es2lan");
645
646 return e1000_write_nvm_spi(hw, offset, words, data);
647}
648
649/**
650 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

--- 73 unchanged lines hidden (view full) ---

724
725 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
726 if (ret_val)
727 goto out;
728
729 usec_delay(1);
730
731 if (hw->phy.autoneg_wait_to_complete) {
642{
643 DEBUGFUNC("e1000_write_nvm_80003es2lan");
644
645 return e1000_write_nvm_spi(hw, offset, words, data);
646}
647
648/**
649 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete

--- 73 unchanged lines hidden (view full) ---

723
724 ret_val = hw->phy.ops.write_reg(hw, PHY_CONTROL, phy_data);
725 if (ret_val)
726 goto out;
727
728 usec_delay(1);
729
730 if (hw->phy.autoneg_wait_to_complete) {
732 DEBUGOUT("Waiting for forced speed/duplex link "
733 "on GG82563 phy.\n");
731 DEBUGOUT("Waiting for forced speed/duplex link on GG82563 phy.\n");
734
735 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
732
733 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
736 100000, &link);
734 100000, &link);
737 if (ret_val)
738 goto out;
739
740 if (!link) {
741 /*
742 * We didn't get link.
743 * Reset the DSP and cross our fingers.
744 */
745 ret_val = e1000_phy_reset_dsp_generic(hw);
746 if (ret_val)
747 goto out;
748 }
749
750 /* Try once more */
751 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
735 if (ret_val)
736 goto out;
737
738 if (!link) {
739 /*
740 * We didn't get link.
741 * Reset the DSP and cross our fingers.
742 */
743 ret_val = e1000_phy_reset_dsp_generic(hw);
744 if (ret_val)
745 goto out;
746 }
747
748 /* Try once more */
749 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
752 100000, &link);
750 100000, &link);
753 if (ret_val)
754 goto out;
755 }
756
751 if (ret_val)
752 goto out;
753 }
754
757 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
755 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
756 &phy_data);
758 if (ret_val)
759 goto out;
760
761 /*
762 * Resetting the phy means we need to verify the TX_CLK corresponds
763 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
764 */
765 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
766 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
767 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
768 else
769 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
770
771 /*
772 * In addition, we must re-enable CRS on Tx for both half and full
773 * duplex.
774 */
775 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
757 if (ret_val)
758 goto out;
759
760 /*
761 * Resetting the phy means we need to verify the TX_CLK corresponds
762 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
763 */
764 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
765 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
766 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
767 else
768 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
769
770 /*
771 * In addition, we must re-enable CRS on Tx for both half and full
772 * duplex.
773 */
774 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
776 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
775 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
776 phy_data);
777
778out:
779 return ret_val;
780}
781
782/**
783 * e1000_get_cable_length_80003es2lan - Set approximate cable length
784 * @hw: pointer to the HW structure

--- 36 unchanged lines hidden (view full) ---

821 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
822 * @hw: pointer to the HW structure
823 * @speed: pointer to speed buffer
824 * @duplex: pointer to duplex buffer
825 *
826 * Retrieve the current speed and duplex configuration.
827 **/
828static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
777
778out:
779 return ret_val;
780}
781
782/**
783 * e1000_get_cable_length_80003es2lan - Set approximate cable length
784 * @hw: pointer to the HW structure

--- 36 unchanged lines hidden (view full) ---

821 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
822 * @hw: pointer to the HW structure
823 * @speed: pointer to speed buffer
824 * @duplex: pointer to duplex buffer
825 *
826 * Retrieve the current speed and duplex configuration.
827 **/
828static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
829 u16 *duplex)
829 u16 *duplex)
830{
831 s32 ret_val;
832
833 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
834
835 if (hw->phy.media_type == e1000_media_type_copper) {
830{
831 s32 ret_val;
832
833 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
834
835 if (hw->phy.media_type == e1000_media_type_copper) {
836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
837 speed,
838 duplex);
836 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
837 duplex);
839 hw->phy.ops.cfg_on_link_up(hw);
840 } else {
841 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
838 hw->phy.ops.cfg_on_link_up(hw);
839 } else {
840 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
842 speed,
843 duplex);
841 speed,
842 duplex);
844 }
845
846 return ret_val;
847}
848
849/**
850 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
851 * @hw: pointer to the HW structure

--- 82 unchanged lines hidden (view full) ---

934 for (i = 0; i < mac->mta_reg_count; i++)
935 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
936
937 /* Setup link and flow control */
938 ret_val = mac->ops.setup_link(hw);
939
940 /* Disable IBIST slave mode (far-end loopback) */
941 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
843 }
844
845 return ret_val;
846}
847
848/**
849 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
850 * @hw: pointer to the HW structure

--- 82 unchanged lines hidden (view full) ---

933 for (i = 0; i < mac->mta_reg_count; i++)
934 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
935
936 /* Setup link and flow control */
937 ret_val = mac->ops.setup_link(hw);
938
939 /* Disable IBIST slave mode (far-end loopback) */
940 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
942 &kum_reg_data);
941 &kum_reg_data);
943 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
944 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
942 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
943 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
945 kum_reg_data);
944 kum_reg_data);
946
947 /* Set the transmit descriptor write-back policy */
948 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
949 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
945
946 /* Set the transmit descriptor write-back policy */
947 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
948 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
950 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
949 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
951 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
952
953 /* ...for both queues. */
954 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
955 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
950 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
951
952 /* ...for both queues. */
953 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
954 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
956 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
955 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
957 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
958
959 /* Enable retransmit on late collisions */
960 reg_data = E1000_READ_REG(hw, E1000_TCTL);
961 reg_data |= E1000_TCTL_RTLC;
962 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
963
964 /* Configure Gigabit Carry Extend Padding */

--- 11 unchanged lines hidden (view full) ---

976 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
977 reg_data &= ~0x00100000;
978 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
979
980 /* default to TRUE to enable the MDIC W/A */
981 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
982
983 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
956 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
957
958 /* Enable retransmit on late collisions */
959 reg_data = E1000_READ_REG(hw, E1000_TCTL);
960 reg_data |= E1000_TCTL_RTLC;
961 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
962
963 /* Configure Gigabit Carry Extend Padding */

--- 11 unchanged lines hidden (view full) ---

975 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
976 reg_data &= ~0x00100000;
977 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
978
979 /* default to TRUE to enable the MDIC W/A */
980 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
981
982 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
984 E1000_KMRNCTRLSTA_OFFSET >>
985 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
986 &i);
983 E1000_KMRNCTRLSTA_OFFSET >>
984 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
985 &i);
987 if (!ret_val) {
988 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
989 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
990 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
991 }
992
993 /*
994 * Clear all of the statistics registers (clear on read). It is

--- 56 unchanged lines hidden (view full) ---

1051{
1052 struct e1000_phy_info *phy = &hw->phy;
1053 s32 ret_val;
1054 u32 ctrl_ext;
1055 u16 data;
1056
1057 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1058
986 if (!ret_val) {
987 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
988 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
989 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
990 }
991
992 /*
993 * Clear all of the statistics registers (clear on read). It is

--- 56 unchanged lines hidden (view full) ---

1050{
1051 struct e1000_phy_info *phy = &hw->phy;
1052 s32 ret_val;
1053 u32 ctrl_ext;
1054 u16 data;
1055
1056 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
1057
1059 if (phy->reset_disable)
1060 goto skip_reset;
1061
1062 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1063 &data);
1058 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
1064 if (ret_val)
1065 goto out;
1066
1067 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1068 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1069 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1070
1059 if (ret_val)
1060 goto out;
1061
1062 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
1063 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1064 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1065
1071 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1072 data);
1066 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
1073 if (ret_val)
1074 goto out;
1075
1076 /*
1077 * Options:
1078 * MDI/MDI-X = 0 (default)
1079 * 0 - Auto for all speeds
1080 * 1 - MDI mode

--- 36 unchanged lines hidden (view full) ---

1117
1118 /* SW Reset the PHY so all changes take effect */
1119 ret_val = hw->phy.ops.commit(hw);
1120 if (ret_val) {
1121 DEBUGOUT("Error Resetting the PHY\n");
1122 goto out;
1123 }
1124
1067 if (ret_val)
1068 goto out;
1069
1070 /*
1071 * Options:
1072 * MDI/MDI-X = 0 (default)
1073 * 0 - Auto for all speeds
1074 * 1 - MDI mode

--- 36 unchanged lines hidden (view full) ---

1111
1112 /* SW Reset the PHY so all changes take effect */
1113 ret_val = hw->phy.ops.commit(hw);
1114 if (ret_val) {
1115 DEBUGOUT("Error Resetting the PHY\n");
1116 goto out;
1117 }
1118
1125skip_reset:
1126 /* Bypass Rx and Tx FIFO's */
1127 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1128 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1129 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1130 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1131 if (ret_val)
1132 goto out;
1133
1134 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1119 /* Bypass Rx and Tx FIFO's */
1120 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1121 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1122 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1123 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1124 if (ret_val)
1125 goto out;
1126
1127 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1135 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1136 &data);
1128 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, &data);
1137 if (ret_val)
1138 goto out;
1139 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1140 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1129 if (ret_val)
1130 goto out;
1131 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1132 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1141 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1142 data);
1133 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE, data);
1143 if (ret_val)
1144 goto out;
1145
1146 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1147 if (ret_val)
1148 goto out;
1149
1150 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;

--- 13 unchanged lines hidden (view full) ---

1164 * Do not init these registers when the HW is in IAMT mode, since the
1165 * firmware will have already initialized them. We only initialize
1166 * them if the HW is not in IAMT mode.
1167 */
1168 if (!(hw->mac.ops.check_mng_mode(hw))) {
1169 /* Enable Electrical Idle on the PHY */
1170 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1171 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1134 if (ret_val)
1135 goto out;
1136
1137 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1138 if (ret_val)
1139 goto out;
1140
1141 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;

--- 13 unchanged lines hidden (view full) ---

1155 * Do not init these registers when the HW is in IAMT mode, since the
1156 * firmware will have already initialized them. We only initialize
1157 * them if the HW is not in IAMT mode.
1158 */
1159 if (!(hw->mac.ops.check_mng_mode(hw))) {
1160 /* Enable Electrical Idle on the PHY */
1161 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1162 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1172 data);
1163 data);
1173 if (ret_val)
1174 goto out;
1175
1176 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1164 if (ret_val)
1165 goto out;
1166
1167 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1177 &data);
1168 &data);
1178 if (ret_val)
1179 goto out;
1180
1181 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1182 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1169 if (ret_val)
1170 goto out;
1171
1172 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1173 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1183 data);
1174 data);
1184 if (ret_val)
1185 goto out;
1186 }
1187
1188 /*
1189 * Workaround: Disable padding in Kumeran interface in the MAC
1190 * and in the PHY to avoid CRC errors.
1191 */

--- 31 unchanged lines hidden (view full) ---

1223 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1224
1225 /*
1226 * Set the mac to wait the maximum time between each
1227 * iteration and increase the max iterations when
1228 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1229 */
1230 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1175 if (ret_val)
1176 goto out;
1177 }
1178
1179 /*
1180 * Workaround: Disable padding in Kumeran interface in the MAC
1181 * and in the PHY to avoid CRC errors.
1182 */

--- 31 unchanged lines hidden (view full) ---

1214 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1215
1216 /*
1217 * Set the mac to wait the maximum time between each
1218 * iteration and increase the max iterations when
1219 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1220 */
1221 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1231 0xFFFF);
1222 0xFFFF);
1232 if (ret_val)
1233 goto out;
1234 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1223 if (ret_val)
1224 goto out;
1225 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1235 &reg_data);
1226 &reg_data);
1236 if (ret_val)
1237 goto out;
1238 reg_data |= 0x3F;
1239 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1227 if (ret_val)
1228 goto out;
1229 reg_data |= 0x3F;
1230 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1240 reg_data);
1231 reg_data);
1241 if (ret_val)
1242 goto out;
1243 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1232 if (ret_val)
1233 goto out;
1234 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
1244 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1245 &reg_data);
1235 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, &reg_data);
1246 if (ret_val)
1247 goto out;
1248 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1249 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1236 if (ret_val)
1237 goto out;
1238 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1239 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1250 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1251 reg_data);
1240 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL, reg_data);
1252 if (ret_val)
1253 goto out;
1254
1255 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1256 if (ret_val)
1257 goto out;
1258
1259 ret_val = e1000_setup_copper_link_generic(hw);

--- 14 unchanged lines hidden (view full) ---

1274{
1275 s32 ret_val = E1000_SUCCESS;
1276 u16 speed;
1277 u16 duplex;
1278
1279 DEBUGFUNC("e1000_configure_on_link_up");
1280
1281 if (hw->phy.media_type == e1000_media_type_copper) {
1241 if (ret_val)
1242 goto out;
1243
1244 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1245 if (ret_val)
1246 goto out;
1247
1248 ret_val = e1000_setup_copper_link_generic(hw);

--- 14 unchanged lines hidden (view full) ---

1263{
1264 s32 ret_val = E1000_SUCCESS;
1265 u16 speed;
1266 u16 duplex;
1267
1268 DEBUGFUNC("e1000_configure_on_link_up");
1269
1270 if (hw->phy.media_type == e1000_media_type_copper) {
1282 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
1283 &speed,
1284 &duplex);
1271 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, &speed,
1272 &duplex);
1285 if (ret_val)
1286 goto out;
1287
1288 if (speed == SPEED_1000)
1289 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1290 else
1291 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1292 }

--- 16 unchanged lines hidden (view full) ---

1309 u32 tipg;
1310 u32 i = 0;
1311 u16 reg_data, reg_data2;
1312
1313 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1314
1315 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1316 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1273 if (ret_val)
1274 goto out;
1275
1276 if (speed == SPEED_1000)
1277 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1278 else
1279 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1280 }

--- 16 unchanged lines hidden (view full) ---

1297 u32 tipg;
1298 u32 i = 0;
1299 u16 reg_data, reg_data2;
1300
1301 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1302
1303 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1304 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1317 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1318 reg_data);
1305 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1306 reg_data);
1319 if (ret_val)
1320 goto out;
1321
1322 /* Configure Transmit Inter-Packet Gap */
1323 tipg = E1000_READ_REG(hw, E1000_TIPG);
1324 tipg &= ~E1000_TIPG_IPGT_MASK;
1325 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1326 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1327
1328 do {
1329 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1307 if (ret_val)
1308 goto out;
1309
1310 /* Configure Transmit Inter-Packet Gap */
1311 tipg = E1000_READ_REG(hw, E1000_TIPG);
1312 tipg &= ~E1000_TIPG_IPGT_MASK;
1313 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1314 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1315
1316 do {
1317 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1330 &reg_data);
1318 &reg_data);
1331 if (ret_val)
1332 goto out;
1333
1334 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1319 if (ret_val)
1320 goto out;
1321
1322 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1335 &reg_data2);
1323 &reg_data2);
1336 if (ret_val)
1337 goto out;
1338 i++;
1339 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1340
1341 if (duplex == HALF_DUPLEX)
1342 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1343 else
1344 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1345
1324 if (ret_val)
1325 goto out;
1326 i++;
1327 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1328
1329 if (duplex == HALF_DUPLEX)
1330 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1331 else
1332 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1333
1346 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1334 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1335 reg_data);
1347
1348out:
1349 return ret_val;
1350}
1351
1352/**
1353 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1354 * @hw: pointer to the HW structure

--- 7 unchanged lines hidden (view full) ---

1362 u16 reg_data, reg_data2;
1363 u32 tipg;
1364 u32 i = 0;
1365
1366 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1367
1368 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1369 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1336
1337out:
1338 return ret_val;
1339}
1340
1341/**
1342 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1343 * @hw: pointer to the HW structure

--- 7 unchanged lines hidden (view full) ---

1351 u16 reg_data, reg_data2;
1352 u32 tipg;
1353 u32 i = 0;
1354
1355 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1356
1357 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1358 ret_val = e1000_write_kmrn_reg_80003es2lan(hw,
1370 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1371 reg_data);
1359 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL, reg_data);
1372 if (ret_val)
1373 goto out;
1374
1375 /* Configure Transmit Inter-Packet Gap */
1376 tipg = E1000_READ_REG(hw, E1000_TIPG);
1377 tipg &= ~E1000_TIPG_IPGT_MASK;
1378 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1379 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1380
1381 do {
1382 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1360 if (ret_val)
1361 goto out;
1362
1363 /* Configure Transmit Inter-Packet Gap */
1364 tipg = E1000_READ_REG(hw, E1000_TIPG);
1365 tipg &= ~E1000_TIPG_IPGT_MASK;
1366 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1367 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1368
1369 do {
1370 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1383 &reg_data);
1371 &reg_data);
1384 if (ret_val)
1385 goto out;
1386
1387 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1372 if (ret_val)
1373 goto out;
1374
1375 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1388 &reg_data2);
1376 &reg_data2);
1389 if (ret_val)
1390 goto out;
1391 i++;
1392 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1393
1394 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1377 if (ret_val)
1378 goto out;
1379 i++;
1380 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1381
1382 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1395 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1383 ret_val = hw->phy.ops.write_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1384 reg_data);
1396
1397out:
1398 return ret_val;
1399}
1400
1401/**
1402 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1403 * @hw: pointer to the HW structure
1404 * @offset: register offset to be read
1405 * @data: pointer to the read data
1406 *
1407 * Acquire semaphore, then read the PHY register at offset
1408 * using the kumeran interface. The information retrieved is stored in data.
1409 * Release the semaphore before exiting.
1410 **/
1411static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1385
1386out:
1387 return ret_val;
1388}
1389
1390/**
1391 * e1000_read_kmrn_reg_80003es2lan - Read kumeran register
1392 * @hw: pointer to the HW structure
1393 * @offset: register offset to be read
1394 * @data: pointer to the read data
1395 *
1396 * Acquire semaphore, then read the PHY register at offset
1397 * using the kumeran interface. The information retrieved is stored in data.
1398 * Release the semaphore before exiting.
1399 **/
1400static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1412 u16 *data)
1401 u16 *data)
1413{
1414 u32 kmrnctrlsta;
1415 s32 ret_val = E1000_SUCCESS;
1416
1417 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1418
1419 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1420 if (ret_val)
1421 goto out;
1422
1423 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1402{
1403 u32 kmrnctrlsta;
1404 s32 ret_val = E1000_SUCCESS;
1405
1406 DEBUGFUNC("e1000_read_kmrn_reg_80003es2lan");
1407
1408 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1409 if (ret_val)
1410 goto out;
1411
1412 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1424 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1413 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1425 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1414 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1415 E1000_WRITE_FLUSH(hw);
1426
1427 usec_delay(2);
1428
1429 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1430 *data = (u16)kmrnctrlsta;
1431
1432 e1000_release_mac_csr_80003es2lan(hw);
1433

--- 7 unchanged lines hidden (view full) ---

1441 * @offset: register offset to write to
1442 * @data: data to write at register offset
1443 *
1444 * Acquire semaphore, then write the data to PHY register
1445 * at the offset using the kumeran interface. Release semaphore
1446 * before exiting.
1447 **/
1448static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1416
1417 usec_delay(2);
1418
1419 kmrnctrlsta = E1000_READ_REG(hw, E1000_KMRNCTRLSTA);
1420 *data = (u16)kmrnctrlsta;
1421
1422 e1000_release_mac_csr_80003es2lan(hw);
1423

--- 7 unchanged lines hidden (view full) ---

1431 * @offset: register offset to write to
1432 * @data: data to write at register offset
1433 *
1434 * Acquire semaphore, then write the data to PHY register
1435 * at the offset using the kumeran interface. Release semaphore
1436 * before exiting.
1437 **/
1438static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1449 u16 data)
1439 u16 data)
1450{
1451 u32 kmrnctrlsta;
1452 s32 ret_val = E1000_SUCCESS;
1453
1454 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1455
1456 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1457 if (ret_val)
1458 goto out;
1459
1460 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1440{
1441 u32 kmrnctrlsta;
1442 s32 ret_val = E1000_SUCCESS;
1443
1444 DEBUGFUNC("e1000_write_kmrn_reg_80003es2lan");
1445
1446 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1447 if (ret_val)
1448 goto out;
1449
1450 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1461 E1000_KMRNCTRLSTA_OFFSET) | data;
1451 E1000_KMRNCTRLSTA_OFFSET) | data;
1462 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1452 E1000_WRITE_REG(hw, E1000_KMRNCTRLSTA, kmrnctrlsta);
1453 E1000_WRITE_FLUSH(hw);
1463
1464 usec_delay(2);
1465
1466 e1000_release_mac_csr_80003es2lan(hw);
1467
1468out:
1469 return ret_val;
1470}

--- 90 unchanged lines hidden --- 		1454
1455 usec_delay(2);
1456
1457 e1000_release_mac_csr_80003es2lan(hw);
1458
1459out:
1460 return ret_val;
1461}

--- 90 unchanged lines hidden ---