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e1000_80003es2lan.c (190872) e1000_80003es2lan.c (200243)
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
1/******************************************************************************
2
3 Copyright (c) 2001-2009, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32******************************************************************************/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 190872 2009-04-10 00:05:46Z jfv $*/
33/*$FreeBSD: head/sys/dev/e1000/e1000_80003es2lan.c 200243 2009-12-08 01:07:44Z jfv $*/
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41

--- 124 unchanged lines hidden (view full) ---

166 nvm->address_bits = 8;
167 break;
168 default:
169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 break;
172 }
173
34
35/*
36 * 80003ES2LAN Gigabit Ethernet Controller (Copper)
37 * 80003ES2LAN Gigabit Ethernet Controller (Serdes)
38 */
39
40#include "e1000_api.h"
41

--- 124 unchanged lines hidden (view full) ---

166 nvm->address_bits = 8;
167 break;
168 default:
169 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
170 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
171 break;
172 }
173
174 nvm->type = e1000_nvm_eeprom_spi;
174 nvm->type = e1000_nvm_eeprom_spi;
175
176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
177 E1000_EECD_SIZE_EX_SHIFT);
178
179 /*
180 * Added to a constant, "size" becomes the left-shift value
181 * for setting word_size.
182 */

--- 18 unchanged lines hidden (view full) ---

201
202/**
203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/
206static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
207{
208 struct e1000_mac_info *mac = &hw->mac;
175
176 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
177 E1000_EECD_SIZE_EX_SHIFT);
178
179 /*
180 * Added to a constant, "size" becomes the left-shift value
181 * for setting word_size.
182 */

--- 18 unchanged lines hidden (view full) ---

201
202/**
203 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/
206static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
207{
208 struct e1000_mac_info *mac = &hw->mac;
209 s32 ret_val = E1000_SUCCESS;
210
211 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
212
209
210 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
211
213 /* Set media type */
212 /* Set media type and media-dependent function pointers */
214 switch (hw->device_id) {
215 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
216 hw->phy.media_type = e1000_media_type_internal_serdes;
213 switch (hw->device_id) {
214 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
215 hw->phy.media_type = e1000_media_type_internal_serdes;
216 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
217 mac->ops.setup_physical_interface =
218 e1000_setup_fiber_serdes_link_generic;
217 break;
218 default:
219 hw->phy.media_type = e1000_media_type_copper;
219 break;
220 default:
221 hw->phy.media_type = e1000_media_type_copper;
222 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
223 mac->ops.setup_physical_interface =
224 e1000_setup_copper_link_80003es2lan;
220 break;
221 }
222
223 /* Set mta register count */
224 mac->mta_reg_count = 128;
225 /* Set rar entry count */
226 mac->rar_entry_count = E1000_RAR_ENTRIES;
227 /* Set if part includes ASF firmware */
228 mac->asf_firmware_present = TRUE;
229 /* Set if manageability features are enabled. */
230 mac->arc_subsystem_valid =
231 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
232 ? TRUE : FALSE;
225 break;
226 }
227
228 /* Set mta register count */
229 mac->mta_reg_count = 128;
230 /* Set rar entry count */
231 mac->rar_entry_count = E1000_RAR_ENTRIES;
232 /* Set if part includes ASF firmware */
233 mac->asf_firmware_present = TRUE;
234 /* Set if manageability features are enabled. */
235 mac->arc_subsystem_valid =
236 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
237 ? TRUE : FALSE;
238 /* Adaptive IFS not supported */
239 mac->adaptive_ifs = FALSE;
233
234 /* Function pointers */
235
236 /* bus type/speed/width */
237 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
238 /* reset */
239 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
240 /* hw initialization */
241 mac->ops.init_hw = e1000_init_hw_80003es2lan;
242 /* link setup */
243 mac->ops.setup_link = e1000_setup_link_generic;
240
241 /* Function pointers */
242
243 /* bus type/speed/width */
244 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
245 /* reset */
246 mac->ops.reset_hw = e1000_reset_hw_80003es2lan;
247 /* hw initialization */
248 mac->ops.init_hw = e1000_init_hw_80003es2lan;
249 /* link setup */
250 mac->ops.setup_link = e1000_setup_link_generic;
244 /* physical interface link setup */
245 mac->ops.setup_physical_interface =
246 (hw->phy.media_type == e1000_media_type_copper)
247 ? e1000_setup_copper_link_80003es2lan
248 : e1000_setup_fiber_serdes_link_generic;
249 /* check for link */
250 switch (hw->phy.media_type) {
251 case e1000_media_type_copper:
252 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
253 break;
254 case e1000_media_type_fiber:
255 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
256 break;
257 case e1000_media_type_internal_serdes:
258 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
259 break;
260 default:
261 ret_val = -E1000_ERR_CONFIG;
262 goto out;
263 break;
264 }
265 /* check management mode */
266 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
267 /* multicast address update */
268 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
269 /* writing VFTA */
270 mac->ops.write_vfta = e1000_write_vfta_generic;
271 /* clearing VFTA */
272 mac->ops.clear_vfta = e1000_clear_vfta_generic;

--- 12 unchanged lines hidden (view full) ---

285 /* turn on/off LED */
286 mac->ops.led_on = e1000_led_on_generic;
287 mac->ops.led_off = e1000_led_off_generic;
288 /* clear hardware counters */
289 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
290 /* link info */
291 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
292
251 /* check management mode */
252 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
253 /* multicast address update */
254 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
255 /* writing VFTA */
256 mac->ops.write_vfta = e1000_write_vfta_generic;
257 /* clearing VFTA */
258 mac->ops.clear_vfta = e1000_clear_vfta_generic;

--- 12 unchanged lines hidden (view full) ---

271 /* turn on/off LED */
272 mac->ops.led_on = e1000_led_on_generic;
273 mac->ops.led_off = e1000_led_off_generic;
274 /* clear hardware counters */
275 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan;
276 /* link info */
277 mac->ops.get_link_up_info = e1000_get_link_up_info_80003es2lan;
278
293out:
294 return ret_val;
279 /* set lan id for port to determine which phy lock to use */
280 hw->mac.ops.set_lan_id(hw);
281
282 return E1000_SUCCESS;
295}
296
297/**
298 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
299 * @hw: pointer to the HW structure
300 *
301 * Called to initialize all function pointers and parameters.
302 **/
303void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
304{
305 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
306
307 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
308 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
309 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
283}
284
285/**
286 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
287 * @hw: pointer to the HW structure
288 *
289 * Called to initialize all function pointers and parameters.
290 **/
291void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
292{
293 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
294
295 hw->mac.ops.init_params = e1000_init_mac_params_80003es2lan;
296 hw->nvm.ops.init_params = e1000_init_nvm_params_80003es2lan;
297 hw->phy.ops.init_params = e1000_init_phy_params_80003es2lan;
310 e1000_get_bus_info_pcie_generic(hw);
311}
312
313/**
314 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
315 * @hw: pointer to the HW structure
316 *
317 * A wrapper to acquire access rights to the correct PHY.
318 **/

--- 18 unchanged lines hidden (view full) ---

337 u16 mask;
338
339 DEBUGFUNC("e1000_release_phy_80003es2lan");
340
341 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
342 e1000_release_swfw_sync_80003es2lan(hw, mask);
343}
344
298}
299
300/**
301 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
302 * @hw: pointer to the HW structure
303 *
304 * A wrapper to acquire access rights to the correct PHY.
305 **/

--- 18 unchanged lines hidden (view full) ---

324 u16 mask;
325
326 DEBUGFUNC("e1000_release_phy_80003es2lan");
327
328 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
329 e1000_release_swfw_sync_80003es2lan(hw, mask);
330}
331
345
346/**
347 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
348 * @hw: pointer to the HW structure
349 *
350 * Acquire the semaphore to access the Kumeran interface.
351 *
352 **/
353static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

--- 173 unchanged lines hidden (view full) ---

527
528 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
529 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
530 if (ret_val) {
531 e1000_release_phy_80003es2lan(hw);
532 goto out;
533 }
534
332/**
333 * e1000_acquire_mac_csr_80003es2lan - Acquire rights to access Kumeran register
334 * @hw: pointer to the HW structure
335 *
336 * Acquire the semaphore to access the Kumeran interface.
337 *
338 **/
339static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)

--- 173 unchanged lines hidden (view full) ---

513
514 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
515 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
516 if (ret_val) {
517 e1000_release_phy_80003es2lan(hw);
518 goto out;
519 }
520
535 /*
536 * The "ready" bit in the MDIC register may be incorrectly set
537 * before the device has completed the "Page Select" MDI
538 * transaction. So we wait 200us after each MDI command...
539 */
540 usec_delay(200);
521 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
522 /*
523 * The "ready" bit in the MDIC register may be incorrectly set
524 * before the device has completed the "Page Select" MDI
525 * transaction. So we wait 200us after each MDI command...
526 */
527 usec_delay(200);
541
528
542 /* ...and verify the command was successful. */
543 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
529 /* ...and verify the command was successful. */
530 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
544
531
545 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
546 ret_val = -E1000_ERR_PHY;
547 e1000_release_phy_80003es2lan(hw);
548 goto out;
549 }
532 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
533 ret_val = -E1000_ERR_PHY;
534 e1000_release_phy_80003es2lan(hw);
535 goto out;
536 }
550
537
551 usec_delay(200);
538 usec_delay(200);
552
539
553 ret_val = e1000_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
554 data);
540 ret_val = e1000_read_phy_reg_mdic(hw,
541 MAX_PHY_REG_ADDRESS & offset,
542 data);
555
543
556 usec_delay(200);
544 usec_delay(200);
545 } else {
546 ret_val = e1000_read_phy_reg_mdic(hw,
547 MAX_PHY_REG_ADDRESS & offset,
548 data);
549 }
550
557 e1000_release_phy_80003es2lan(hw);
558
559out:
560 return ret_val;
561}
562
563/**
564 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

--- 29 unchanged lines hidden (view full) ---

594
595 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
596 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
597 if (ret_val) {
598 e1000_release_phy_80003es2lan(hw);
599 goto out;
600 }
601
551 e1000_release_phy_80003es2lan(hw);
552
553out:
554 return ret_val;
555}
556
557/**
558 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register

--- 29 unchanged lines hidden (view full) ---

588
589 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
590 ret_val = e1000_write_phy_reg_mdic(hw, page_select, temp);
591 if (ret_val) {
592 e1000_release_phy_80003es2lan(hw);
593 goto out;
594 }
595
596 if (hw->dev_spec._80003es2lan.mdic_wa_enable == TRUE) {
597 /*
598 * The "ready" bit in the MDIC register may be incorrectly set
599 * before the device has completed the "Page Select" MDI
600 * transaction. So we wait 200us after each MDI command...
601 */
602 usec_delay(200);
602
603
603 /*
604 * The "ready" bit in the MDIC register may be incorrectly set
605 * before the device has completed the "Page Select" MDI
606 * transaction. So we wait 200us after each MDI command...
607 */
608 usec_delay(200);
604 /* ...and verify the command was successful. */
605 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
609
606
610 /* ...and verify the command was successful. */
611 ret_val = e1000_read_phy_reg_mdic(hw, page_select, &temp);
607 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
608 ret_val = -E1000_ERR_PHY;
609 e1000_release_phy_80003es2lan(hw);
610 goto out;
611 }
612
612
613 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
614 ret_val = -E1000_ERR_PHY;
615 e1000_release_phy_80003es2lan(hw);
616 goto out;
617 }
613 usec_delay(200);
618
614
619 usec_delay(200);
615 ret_val = e1000_write_phy_reg_mdic(hw,
616 MAX_PHY_REG_ADDRESS & offset,
617 data);
620
618
621 ret_val = e1000_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset,
622 data);
619 usec_delay(200);
620 } else {
621 ret_val = e1000_write_phy_reg_mdic(hw,
622 MAX_PHY_REG_ADDRESS & offset,
623 data);
624 }
623
625
624 usec_delay(200);
625 e1000_release_phy_80003es2lan(hw);
626
627out:
628 return ret_val;
629}
630
631/**
632 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM

--- 164 unchanged lines hidden (view full) ---

797 goto out;
798
799 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
800 if (ret_val)
801 goto out;
802
803 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
804
626 e1000_release_phy_80003es2lan(hw);
627
628out:
629 return ret_val;
630}
631
632/**
633 * e1000_write_nvm_80003es2lan - Write to ESB2 NVM

--- 164 unchanged lines hidden (view full) ---

798 goto out;
799
800 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
801 if (ret_val)
802 goto out;
803
804 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
805
805 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE + 5) {
806 ret_val = E1000_ERR_PHY;
806 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5) {
807 ret_val = -E1000_ERR_PHY;
807 goto out;
808 }
809
810 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
808 goto out;
809 }
810
811 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
811 phy->max_cable_length = e1000_gg82563_cable_length_table[index+5];
812 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
812
813 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
814
815out:
816 return ret_val;
817}
818
819/**

--- 91 unchanged lines hidden (view full) ---

911 u16 i;
912
913 DEBUGFUNC("e1000_init_hw_80003es2lan");
914
915 e1000_initialize_hw_bits_80003es2lan(hw);
916
917 /* Initialize identification LED */
918 ret_val = mac->ops.id_led_init(hw);
813
814 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
815
816out:
817 return ret_val;
818}
819
820/**

--- 91 unchanged lines hidden (view full) ---

912 u16 i;
913
914 DEBUGFUNC("e1000_init_hw_80003es2lan");
915
916 e1000_initialize_hw_bits_80003es2lan(hw);
917
918 /* Initialize identification LED */
919 ret_val = mac->ops.id_led_init(hw);
919 if (ret_val) {
920 if (ret_val)
920 DEBUGOUT("Error initializing identification LED\n");
921 /* This is not fatal and we should not stop init due to this */
921 DEBUGOUT("Error initializing identification LED\n");
922 /* This is not fatal and we should not stop init due to this */
922 }
923
924 /* Disabling VLAN filtering */
925 DEBUGOUT("Initializing the IEEE VLAN\n");
926 mac->ops.clear_vfta(hw);
927
928 /* Setup the receive address. */
929 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
930

--- 33 unchanged lines hidden (view full) ---

964 reg_data &= ~E1000_TIPG_IPGT_MASK;
965 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
966 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
967
968 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
969 reg_data &= ~0x00100000;
970 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
971
923
924 /* Disabling VLAN filtering */
925 DEBUGOUT("Initializing the IEEE VLAN\n");
926 mac->ops.clear_vfta(hw);
927
928 /* Setup the receive address. */
929 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
930

--- 33 unchanged lines hidden (view full) ---

964 reg_data &= ~E1000_TIPG_IPGT_MASK;
965 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
966 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
967
968 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
969 reg_data &= ~0x00100000;
970 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
971
972 /* default to TRUE to enable the MDIC W/A */
973 hw->dev_spec._80003es2lan.mdic_wa_enable = TRUE;
974
975 ret_val = e1000_read_kmrn_reg_80003es2lan(hw,
976 E1000_KMRNCTRLSTA_OFFSET >>
977 E1000_KMRNCTRLSTA_OFFSET_SHIFT,
978 &i);
979 if (!ret_val) {
980 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
981 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
982 hw->dev_spec._80003es2lan.mdic_wa_enable = FALSE;
983 }
984
972 /*
973 * Clear all of the statistics registers (clear on read). It is
974 * important that we do this after we have tried to establish link
975 * because the symbol error count will increment wildly if there
976 * is no link.
977 */
978 e1000_clear_hw_cntrs_80003es2lan(hw);
979

--- 318 unchanged lines hidden (view full) ---

1298 goto out;
1299
1300 /* Configure Transmit Inter-Packet Gap */
1301 tipg = E1000_READ_REG(hw, E1000_TIPG);
1302 tipg &= ~E1000_TIPG_IPGT_MASK;
1303 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1304 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1305
985 /*
986 * Clear all of the statistics registers (clear on read). It is
987 * important that we do this after we have tried to establish link
988 * because the symbol error count will increment wildly if there
989 * is no link.
990 */
991 e1000_clear_hw_cntrs_80003es2lan(hw);
992

--- 318 unchanged lines hidden (view full) ---

1311 goto out;
1312
1313 /* Configure Transmit Inter-Packet Gap */
1314 tipg = E1000_READ_REG(hw, E1000_TIPG);
1315 tipg &= ~E1000_TIPG_IPGT_MASK;
1316 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1317 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1318
1306
1307 do {
1308 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1309 &reg_data);
1310 if (ret_val)
1311 goto out;
1312
1313 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1314 &reg_data2);

--- 37 unchanged lines hidden (view full) ---

1352 goto out;
1353
1354 /* Configure Transmit Inter-Packet Gap */
1355 tipg = E1000_READ_REG(hw, E1000_TIPG);
1356 tipg &= ~E1000_TIPG_IPGT_MASK;
1357 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1358 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1359
1319 do {
1320 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1321 &reg_data);
1322 if (ret_val)
1323 goto out;
1324
1325 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1326 &reg_data2);

--- 37 unchanged lines hidden (view full) ---

1364 goto out;
1365
1366 /* Configure Transmit Inter-Packet Gap */
1367 tipg = E1000_READ_REG(hw, E1000_TIPG);
1368 tipg &= ~E1000_TIPG_IPGT_MASK;
1369 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1370 E1000_WRITE_REG(hw, E1000_TIPG, tipg);
1371
1360
1361 do {
1362 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1363 &reg_data);
1364 if (ret_val)
1365 goto out;
1366
1367 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1368 &reg_data2);

--- 172 unchanged lines hidden --- 		1372 do {
1373 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1374 &reg_data);
1375 if (ret_val)
1376 goto out;
1377
1378 ret_val = hw->phy.ops.read_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1379 &reg_data2);

--- 172 unchanged lines hidden ---