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e1000_80003es2lan.c (169589) e1000_80003es2lan.c (173788)
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
1/*******************************************************************************
2
3 Copyright (c) 2001-2007, Intel Corporation
4 All rights reserved.
5
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8

--- 16 unchanged lines hidden (view full) ---

25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30 POSSIBILITY OF SUCH DAMAGE.
31
32*******************************************************************************/
33/*$FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 169589 2007-05-16 00:14:23Z jfv $*/
33/* $FreeBSD: head/sys/dev/em/e1000_80003es2lan.c 173788 2007-11-20 21:41:22Z jfv $ */
34
35/* e1000_80003es2lan
36 */
37
38#include "e1000_api.h"
39#include "e1000_80003es2lan.h"
40
41void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);

--- 23 unchanged lines hidden (view full) ---

65STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
66STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
67static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
68static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
69static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
70static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
71static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
72static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
34
35/* e1000_80003es2lan
36 */
37
38#include "e1000_api.h"
39#include "e1000_80003es2lan.h"
40
41void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw);

--- 23 unchanged lines hidden (view full) ---

65STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
66STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
67static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
68static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
69static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
70static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw);
71static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
72static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
73STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
73
74
74/* A table for the GG82563 cable length where the range is defined
75/*
76 * A table for the GG82563 cable length where the range is defined
75 * with a lower bound at "index" and the upper bound at
76 * "index + 5".
77 */
77 * with a lower bound at "index" and the upper bound at
78 * "index + 5".
79 */
78static const
79u16 e1000_gg82563_cable_length_table[] =
80static const u16 e1000_gg82563_cable_length_table[] =
80 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
81#define GG82563_CABLE_LENGTH_TABLE_SIZE \
82 (sizeof(e1000_gg82563_cable_length_table) / \
83 sizeof(e1000_gg82563_cable_length_table[0]))
84
85/**
86 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
87 * @hw: pointer to the HW structure
88 *
89 * This is a function pointer entry point called by the api module.
90 **/
81 { 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF };
82#define GG82563_CABLE_LENGTH_TABLE_SIZE \
83 (sizeof(e1000_gg82563_cable_length_table) / \
84 sizeof(e1000_gg82563_cable_length_table[0]))
85
86/**
87 * e1000_init_phy_params_80003es2lan - Init ESB2 PHY func ptrs.
88 * @hw: pointer to the HW structure
89 *
90 * This is a function pointer entry point called by the api module.
91 **/
91STATIC s32
92e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
92STATIC s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
93{
94 struct e1000_phy_info *phy = &hw->phy;
95 struct e1000_functions *func = &hw->func;
96 s32 ret_val = E1000_SUCCESS;
97
98 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
99
93{
94 struct e1000_phy_info *phy = &hw->phy;
95 struct e1000_functions *func = &hw->func;
96 s32 ret_val = E1000_SUCCESS;
97
98 DEBUGFUNC("e1000_init_phy_params_80003es2lan");
99
100 if (hw->media_type != e1000_media_type_copper) {
100 if (hw->phy.media_type != e1000_media_type_copper) {
101 phy->type = e1000_phy_none;
102 goto out;
101 phy->type = e1000_phy_none;
102 goto out;
103 } else {
104 func->power_up_phy = e1000_power_up_phy_copper;
105 func->power_down_phy = e1000_power_down_phy_copper_80003es2lan;
103 }
104
105 phy->addr = 1;
106 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
107 phy->reset_delay_us = 100;
108 phy->type = e1000_phy_gg82563;
109
110 func->acquire_phy = e1000_acquire_phy_80003es2lan;

--- 25 unchanged lines hidden (view full) ---

136}
137
138/**
139 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
140 * @hw: pointer to the HW structure
141 *
142 * This is a function pointer entry point called by the api module.
143 **/
106 }
107
108 phy->addr = 1;
109 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
110 phy->reset_delay_us = 100;
111 phy->type = e1000_phy_gg82563;
112
113 func->acquire_phy = e1000_acquire_phy_80003es2lan;

--- 25 unchanged lines hidden (view full) ---

139}
140
141/**
142 * e1000_init_nvm_params_80003es2lan - Init ESB2 NVM func ptrs.
143 * @hw: pointer to the HW structure
144 *
145 * This is a function pointer entry point called by the api module.
146 **/
144STATIC s32
145e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
147STATIC s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
146{
147 struct e1000_nvm_info *nvm = &hw->nvm;
148 struct e1000_functions *func = &hw->func;
149 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
150 u16 size;
151
152 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
153

--- 14 unchanged lines hidden (view full) ---

168 break;
169 }
170
171 nvm->type = e1000_nvm_eeprom_spi;
172
173 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
174 E1000_EECD_SIZE_EX_SHIFT);
175
148{
149 struct e1000_nvm_info *nvm = &hw->nvm;
150 struct e1000_functions *func = &hw->func;
151 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
152 u16 size;
153
154 DEBUGFUNC("e1000_init_nvm_params_80003es2lan");
155

--- 14 unchanged lines hidden (view full) ---

170 break;
171 }
172
173 nvm->type = e1000_nvm_eeprom_spi;
174
175 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
176 E1000_EECD_SIZE_EX_SHIFT);
177
176 /* Added to a constant, "size" becomes the left-shift value
178 /*
179 * Added to a constant, "size" becomes the left-shift value
177 * for setting word_size.
178 */
179 size += NVM_WORD_SIZE_BASE_SHIFT;
180 * for setting word_size.
181 */
182 size += NVM_WORD_SIZE_BASE_SHIFT;
183
184 /* EEPROM access above 16k is unsupported */
185 if (size > 14)
186 size = 14;
180 nvm->word_size = 1 << size;
181
182 /* Function Pointers */
183 func->acquire_nvm = e1000_acquire_nvm_80003es2lan;
184 func->read_nvm = e1000_read_nvm_eerd;
185 func->release_nvm = e1000_release_nvm_80003es2lan;
186 func->update_nvm = e1000_update_nvm_checksum_generic;
187 func->valid_led_default = e1000_valid_led_default_generic;

--- 4 unchanged lines hidden (view full) ---

192}
193
194/**
195 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
196 * @hw: pointer to the HW structure
197 *
198 * This is a function pointer entry point called by the api module.
199 **/
187 nvm->word_size = 1 << size;
188
189 /* Function Pointers */
190 func->acquire_nvm = e1000_acquire_nvm_80003es2lan;
191 func->read_nvm = e1000_read_nvm_eerd;
192 func->release_nvm = e1000_release_nvm_80003es2lan;
193 func->update_nvm = e1000_update_nvm_checksum_generic;
194 func->valid_led_default = e1000_valid_led_default_generic;

--- 4 unchanged lines hidden (view full) ---

199}
200
201/**
202 * e1000_init_mac_params_80003es2lan - Init ESB2 MAC func ptrs.
203 * @hw: pointer to the HW structure
204 *
205 * This is a function pointer entry point called by the api module.
206 **/
200STATIC s32
201e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
207STATIC s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
202{
203 struct e1000_mac_info *mac = &hw->mac;
204 struct e1000_functions *func = &hw->func;
205 s32 ret_val = E1000_SUCCESS;
206
207 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
208
209 /* Set media type */
210 switch (hw->device_id) {
211 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
208{
209 struct e1000_mac_info *mac = &hw->mac;
210 struct e1000_functions *func = &hw->func;
211 s32 ret_val = E1000_SUCCESS;
212
213 DEBUGFUNC("e1000_init_mac_params_80003es2lan");
214
215 /* Set media type */
216 switch (hw->device_id) {
217 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
212 hw->media_type = e1000_media_type_internal_serdes;
218 hw->phy.media_type = e1000_media_type_internal_serdes;
213 break;
214 default:
219 break;
220 default:
215 hw->media_type = e1000_media_type_copper;
221 hw->phy.media_type = e1000_media_type_copper;
216 break;
217 }
218
219 /* Set mta register count */
220 mac->mta_reg_count = 128;
221 /* Set rar entry count */
222 mac->rar_entry_count = E1000_RAR_ENTRIES;
223 /* Set if part includes ASF firmware */

--- 10 unchanged lines hidden (view full) ---

234 /* reset */
235 func->reset_hw = e1000_reset_hw_80003es2lan;
236 /* hw initialization */
237 func->init_hw = e1000_init_hw_80003es2lan;
238 /* link setup */
239 func->setup_link = e1000_setup_link_generic;
240 /* physical interface link setup */
241 func->setup_physical_interface =
222 break;
223 }
224
225 /* Set mta register count */
226 mac->mta_reg_count = 128;
227 /* Set rar entry count */
228 mac->rar_entry_count = E1000_RAR_ENTRIES;
229 /* Set if part includes ASF firmware */

--- 10 unchanged lines hidden (view full) ---

240 /* reset */
241 func->reset_hw = e1000_reset_hw_80003es2lan;
242 /* hw initialization */
243 func->init_hw = e1000_init_hw_80003es2lan;
244 /* link setup */
245 func->setup_link = e1000_setup_link_generic;
246 /* physical interface link setup */
247 func->setup_physical_interface =
242 (hw->media_type == e1000_media_type_copper)
248 (hw->phy.media_type == e1000_media_type_copper)
243 ? e1000_setup_copper_link_80003es2lan
244 : e1000_setup_fiber_serdes_link_generic;
245 /* check for link */
249 ? e1000_setup_copper_link_80003es2lan
250 : e1000_setup_fiber_serdes_link_generic;
251 /* check for link */
246 switch (hw->media_type) {
252 switch (hw->phy.media_type) {
247 case e1000_media_type_copper:
248 func->check_for_link = e1000_check_for_copper_link_generic;
249 break;
250 case e1000_media_type_fiber:
251 func->check_for_link = e1000_check_for_fiber_link_generic;
252 break;
253 case e1000_media_type_internal_serdes:
254 func->check_for_link = e1000_check_for_serdes_link_generic;
255 break;
256 default:
257 ret_val = -E1000_ERR_CONFIG;
258 goto out;
259 break;
260 }
261 /* check management mode */
262 func->check_mng_mode = e1000_check_mng_mode_generic;
263 /* multicast address update */
253 case e1000_media_type_copper:
254 func->check_for_link = e1000_check_for_copper_link_generic;
255 break;
256 case e1000_media_type_fiber:
257 func->check_for_link = e1000_check_for_fiber_link_generic;
258 break;
259 case e1000_media_type_internal_serdes:
260 func->check_for_link = e1000_check_for_serdes_link_generic;
261 break;
262 default:
263 ret_val = -E1000_ERR_CONFIG;
264 goto out;
265 break;
266 }
267 /* check management mode */
268 func->check_mng_mode = e1000_check_mng_mode_generic;
269 /* multicast address update */
264 func->mc_addr_list_update = e1000_mc_addr_list_update_generic;
270 func->update_mc_addr_list = e1000_update_mc_addr_list_generic;
265 /* writing VFTA */
266 func->write_vfta = e1000_write_vfta_generic;
267 /* clearing VFTA */
268 func->clear_vfta = e1000_clear_vfta_generic;
269 /* setting MTA */
270 func->mta_set = e1000_mta_set_generic;
271 /* blink LED */
272 func->blink_led = e1000_blink_led_generic;

--- 17 unchanged lines hidden (view full) ---

290
291/**
292 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
293 * @hw: pointer to the HW structure
294 *
295 * The only function explicitly called by the api module to initialize
296 * all function pointers and parameters.
297 **/
271 /* writing VFTA */
272 func->write_vfta = e1000_write_vfta_generic;
273 /* clearing VFTA */
274 func->clear_vfta = e1000_clear_vfta_generic;
275 /* setting MTA */
276 func->mta_set = e1000_mta_set_generic;
277 /* blink LED */
278 func->blink_led = e1000_blink_led_generic;

--- 17 unchanged lines hidden (view full) ---

296
297/**
298 * e1000_init_function_pointers_80003es2lan - Init ESB2 func ptrs.
299 * @hw: pointer to the HW structure
300 *
301 * The only function explicitly called by the api module to initialize
302 * all function pointers and parameters.
303 **/
298void
299e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
304void e1000_init_function_pointers_80003es2lan(struct e1000_hw *hw)
300{
301 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
302
303 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan;
304 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan;
305 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan;
306}
307
308/**
309 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
310 * @hw: pointer to the HW structure
311 *
312 * A wrapper to acquire access rights to the correct PHY. This is a
313 * function pointer entry point called by the api module.
314 **/
305{
306 DEBUGFUNC("e1000_init_function_pointers_80003es2lan");
307
308 hw->func.init_mac_params = e1000_init_mac_params_80003es2lan;
309 hw->func.init_nvm_params = e1000_init_nvm_params_80003es2lan;
310 hw->func.init_phy_params = e1000_init_phy_params_80003es2lan;
311}
312
313/**
314 * e1000_acquire_phy_80003es2lan - Acquire rights to access PHY
315 * @hw: pointer to the HW structure
316 *
317 * A wrapper to acquire access rights to the correct PHY. This is a
318 * function pointer entry point called by the api module.
319 **/
315STATIC s32
316e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
320STATIC s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
317{
318 u16 mask;
319
320 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
321
322 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
323
324 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
325}
326
327/**
328 * e1000_release_phy_80003es2lan - Release rights to access PHY
329 * @hw: pointer to the HW structure
330 *
331 * A wrapper to release access rights to the correct PHY. This is a
332 * function pointer entry point called by the api module.
333 **/
321{
322 u16 mask;
323
324 DEBUGFUNC("e1000_acquire_phy_80003es2lan");
325
326 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
327
328 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
329}
330
331/**
332 * e1000_release_phy_80003es2lan - Release rights to access PHY
333 * @hw: pointer to the HW structure
334 *
335 * A wrapper to release access rights to the correct PHY. This is a
336 * function pointer entry point called by the api module.
337 **/
334STATIC void
335e1000_release_phy_80003es2lan(struct e1000_hw *hw)
338STATIC void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
336{
337 u16 mask;
338
339 DEBUGFUNC("e1000_release_phy_80003es2lan");
340
341 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
342 e1000_release_swfw_sync_80003es2lan(hw, mask);
343}
344
345/**
346 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
347 * @hw: pointer to the HW structure
348 *
349 * Acquire the semaphore to access the EEPROM. This is a function
350 * pointer entry point called by the api module.
351 **/
339{
340 u16 mask;
341
342 DEBUGFUNC("e1000_release_phy_80003es2lan");
343
344 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
345 e1000_release_swfw_sync_80003es2lan(hw, mask);
346}
347
348/**
349 * e1000_acquire_nvm_80003es2lan - Acquire rights to access NVM
350 * @hw: pointer to the HW structure
351 *
352 * Acquire the semaphore to access the EEPROM. This is a function
353 * pointer entry point called by the api module.
354 **/
352STATIC s32
353e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
355STATIC s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
354{
355 s32 ret_val;
356
357 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
358
359 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
360 if (ret_val)
361 goto out;

--- 9 unchanged lines hidden (view full) ---

371
372/**
373 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
374 * @hw: pointer to the HW structure
375 *
376 * Release the semaphore used to access the EEPROM. This is a
377 * function pointer entry point called by the api module.
378 **/
356{
357 s32 ret_val;
358
359 DEBUGFUNC("e1000_acquire_nvm_80003es2lan");
360
361 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
362 if (ret_val)
363 goto out;

--- 9 unchanged lines hidden (view full) ---

373
374/**
375 * e1000_release_nvm_80003es2lan - Relinquish rights to access NVM
376 * @hw: pointer to the HW structure
377 *
378 * Release the semaphore used to access the EEPROM. This is a
379 * function pointer entry point called by the api module.
380 **/
379STATIC void
380e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
381STATIC void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
381{
382 DEBUGFUNC("e1000_release_nvm_80003es2lan");
383
384 e1000_release_nvm_generic(hw);
385 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
386}
387
388/**
389 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
390 * @hw: pointer to the HW structure
391 * @mask: specifies which semaphore to acquire
392 *
393 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
394 * will also specify which port we're acquiring the lock for.
395 **/
382{
383 DEBUGFUNC("e1000_release_nvm_80003es2lan");
384
385 e1000_release_nvm_generic(hw);
386 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
387}
388
389/**
390 * e1000_acquire_swfw_sync_80003es2lan - Acquire SW/FW semaphore
391 * @hw: pointer to the HW structure
392 * @mask: specifies which semaphore to acquire
393 *
394 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
395 * will also specify which port we're acquiring the lock for.
396 **/
396static s32
397e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
397static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
398{
399 u32 swfw_sync;
400 u32 swmask = mask;
401 u32 fwmask = mask << 16;
402 s32 ret_val = E1000_SUCCESS;
403 s32 i = 0, timeout = 200;
404
405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
406
407 while (i < timeout) {
408 if (e1000_get_hw_semaphore_generic(hw)) {
409 ret_val = -E1000_ERR_SWFW_SYNC;
410 goto out;
411 }
412
413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
414 if (!(swfw_sync & (fwmask | swmask)))
415 break;
416
398{
399 u32 swfw_sync;
400 u32 swmask = mask;
401 u32 fwmask = mask << 16;
402 s32 ret_val = E1000_SUCCESS;
403 s32 i = 0, timeout = 200;
404
405 DEBUGFUNC("e1000_acquire_swfw_sync_80003es2lan");
406
407 while (i < timeout) {
408 if (e1000_get_hw_semaphore_generic(hw)) {
409 ret_val = -E1000_ERR_SWFW_SYNC;
410 goto out;
411 }
412
413 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
414 if (!(swfw_sync & (fwmask | swmask)))
415 break;
416
417 /* Firmware currently using resource (fwmask)
418 * or other software thread using resource (swmask) */
417 /*
418 * Firmware currently using resource (fwmask)
419 * or other software thread using resource (swmask)
420 */
419 e1000_put_hw_semaphore_generic(hw);
420 msec_delay_irq(5);
421 i++;
422 }
423
424 if (i == timeout) {
425 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
426 ret_val = -E1000_ERR_SWFW_SYNC;

--- 12 unchanged lines hidden (view full) ---

439/**
440 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
441 * @hw: pointer to the HW structure
442 * @mask: specifies which semaphore to acquire
443 *
444 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
445 * will also specify which port we're releasing the lock for.
446 **/
421 e1000_put_hw_semaphore_generic(hw);
422 msec_delay_irq(5);
423 i++;
424 }
425
426 if (i == timeout) {
427 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
428 ret_val = -E1000_ERR_SWFW_SYNC;

--- 12 unchanged lines hidden (view full) ---

441/**
442 * e1000_release_swfw_sync_80003es2lan - Release SW/FW semaphore
443 * @hw: pointer to the HW structure
444 * @mask: specifies which semaphore to acquire
445 *
446 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
447 * will also specify which port we're releasing the lock for.
448 **/
447static void
448e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
449static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
449{
450 u32 swfw_sync;
451
452 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
453
454 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
455 /* Empty */
456

--- 8 unchanged lines hidden (view full) ---

465 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
466 * @hw: pointer to the HW structure
467 * @offset: offset of the register to read
468 * @data: pointer to the data returned from the operation
469 *
470 * Read the GG82563 PHY register. This is a function pointer entry
471 * point called by the api module.
472 **/
450{
451 u32 swfw_sync;
452
453 DEBUGFUNC("e1000_release_swfw_sync_80003es2lan");
454
455 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS);
456 /* Empty */
457

--- 8 unchanged lines hidden (view full) ---

466 * e1000_read_phy_reg_gg82563_80003es2lan - Read GG82563 PHY register
467 * @hw: pointer to the HW structure
468 * @offset: offset of the register to read
469 * @data: pointer to the data returned from the operation
470 *
471 * Read the GG82563 PHY register. This is a function pointer entry
472 * point called by the api module.
473 **/
473STATIC s32
474e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset,
475 u16 *data)
474STATIC s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
475 u32 offset, u16 *data)
476{
477 s32 ret_val;
478 u32 page_select;
479 u16 temp;
480
481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
482
483 /* Select Configuration Page */
476{
477 s32 ret_val;
478 u32 page_select;
479 u16 temp;
480
481 DEBUGFUNC("e1000_read_phy_reg_gg82563_80003es2lan");
482
483 /* Select Configuration Page */
484 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
484 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
485 page_select = GG82563_PHY_PAGE_SELECT;
485 page_select = GG82563_PHY_PAGE_SELECT;
486 else {
487 /* Use Alternative Page Select register to access
486 } else {
487 /*
488 * Use Alternative Page Select register to access
488 * registers 30 and 31
489 */
490 page_select = GG82563_PHY_PAGE_SELECT_ALT;
491 }
492
493 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
494 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp);
495 if (ret_val)
496 goto out;
497
489 * registers 30 and 31
490 */
491 page_select = GG82563_PHY_PAGE_SELECT_ALT;
492 }
493
494 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
495 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp);
496 if (ret_val)
497 goto out;
498
498 /* The "ready" bit in the MDIC register may be incorrectly set
499 /*
500 * The "ready" bit in the MDIC register may be incorrectly set
499 * before the device has completed the "Page Select" MDI
500 * transaction. So we wait 200us after each MDI command...
501 */
502 usec_delay(200);
503
504 /* ...and verify the command was successful. */
505 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp);
506

--- 18 unchanged lines hidden (view full) ---

525 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
526 * @hw: pointer to the HW structure
527 * @offset: offset of the register to read
528 * @data: value to write to the register
529 *
530 * Write to the GG82563 PHY register. This is a function pointer entry
531 * point called by the api module.
532 **/
501 * before the device has completed the "Page Select" MDI
502 * transaction. So we wait 200us after each MDI command...
503 */
504 usec_delay(200);
505
506 /* ...and verify the command was successful. */
507 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp);
508

--- 18 unchanged lines hidden (view full) ---

527 * e1000_write_phy_reg_gg82563_80003es2lan - Write GG82563 PHY register
528 * @hw: pointer to the HW structure
529 * @offset: offset of the register to read
530 * @data: value to write to the register
531 *
532 * Write to the GG82563 PHY register. This is a function pointer entry
533 * point called by the api module.
534 **/
533STATIC s32
534e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw, u32 offset,
535 u16 data)
535STATIC s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
536 u32 offset, u16 data)
536{
537 s32 ret_val;
538 u32 page_select;
539 u16 temp;
540
541 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
542
543 /* Select Configuration Page */
537{
538 s32 ret_val;
539 u32 page_select;
540 u16 temp;
541
542 DEBUGFUNC("e1000_write_phy_reg_gg82563_80003es2lan");
543
544 /* Select Configuration Page */
544 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG)
545 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
545 page_select = GG82563_PHY_PAGE_SELECT;
546 page_select = GG82563_PHY_PAGE_SELECT;
546 else {
547 /* Use Alternative Page Select register to access
547 } else {
548 /*
549 * Use Alternative Page Select register to access
548 * registers 30 and 31
549 */
550 page_select = GG82563_PHY_PAGE_SELECT_ALT;
551 }
552
553 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
554 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp);
555 if (ret_val)
556 goto out;
557
558
550 * registers 30 and 31
551 */
552 page_select = GG82563_PHY_PAGE_SELECT_ALT;
553 }
554
555 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
556 ret_val = e1000_write_phy_reg_m88(hw, page_select, temp);
557 if (ret_val)
558 goto out;
559
560
559 /* The "ready" bit in the MDIC register may be incorrectly set
561 /*
562 * The "ready" bit in the MDIC register may be incorrectly set
560 * before the device has completed the "Page Select" MDI
561 * transaction. So we wait 200us after each MDI command...
562 */
563 usec_delay(200);
564
565 /* ...and verify the command was successful. */
566 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp);
567

--- 19 unchanged lines hidden (view full) ---

587 * @hw: pointer to the HW structure
588 * @offset: offset of the register to read
589 * @words: number of words to write
590 * @data: buffer of data to write to the NVM
591 *
592 * Write "words" of data to the ESB2 NVM. This is a function
593 * pointer entry point called by the api module.
594 **/
563 * before the device has completed the "Page Select" MDI
564 * transaction. So we wait 200us after each MDI command...
565 */
566 usec_delay(200);
567
568 /* ...and verify the command was successful. */
569 ret_val = e1000_read_phy_reg_m88(hw, page_select, &temp);
570

--- 19 unchanged lines hidden (view full) ---

590 * @hw: pointer to the HW structure
591 * @offset: offset of the register to read
592 * @words: number of words to write
593 * @data: buffer of data to write to the NVM
594 *
595 * Write "words" of data to the ESB2 NVM. This is a function
596 * pointer entry point called by the api module.
597 **/
595STATIC s32
596e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
598STATIC s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
597 u16 words, u16 *data)
598{
599 DEBUGFUNC("e1000_write_nvm_80003es2lan");
600
601 return e1000_write_nvm_spi(hw, offset, words, data);
602}
603
604/**
605 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
606 * @hw: pointer to the HW structure
607 *
608 * Wait a specific amount of time for manageability processes to complete.
609 * This is a function pointer entry point called by the phy module.
610 **/
599 u16 words, u16 *data)
600{
601 DEBUGFUNC("e1000_write_nvm_80003es2lan");
602
603 return e1000_write_nvm_spi(hw, offset, words, data);
604}
605
606/**
607 * e1000_get_cfg_done_80003es2lan - Wait for configuration to complete
608 * @hw: pointer to the HW structure
609 *
610 * Wait a specific amount of time for manageability processes to complete.
611 * This is a function pointer entry point called by the phy module.
612 **/
611STATIC s32
612e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
613STATIC s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
613{
614 s32 timeout = PHY_CFG_TIMEOUT;
615 s32 ret_val = E1000_SUCCESS;
616 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
617
618 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
619
620 if (hw->bus.func == 1)

--- 17 unchanged lines hidden (view full) ---

638
639/**
640 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
641 * @hw: pointer to the HW structure
642 *
643 * Force the speed and duplex settings onto the PHY. This is a
644 * function pointer entry point called by the phy module.
645 **/
614{
615 s32 timeout = PHY_CFG_TIMEOUT;
616 s32 ret_val = E1000_SUCCESS;
617 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
618
619 DEBUGFUNC("e1000_get_cfg_done_80003es2lan");
620
621 if (hw->bus.func == 1)

--- 17 unchanged lines hidden (view full) ---

639
640/**
641 * e1000_phy_force_speed_duplex_80003es2lan - Force PHY speed and duplex
642 * @hw: pointer to the HW structure
643 *
644 * Force the speed and duplex settings onto the PHY. This is a
645 * function pointer entry point called by the phy module.
646 **/
646STATIC s32
647e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
647STATIC s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
648{
649 s32 ret_val;
650 u16 phy_data;
648{
649 s32 ret_val;
650 u16 phy_data;
651 boolean_t link;
651 bool link;
652
653 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
654
652
653 DEBUGFUNC("e1000_phy_force_speed_duplex_80003es2lan");
654
655 /* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
655 /*
656 * Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
656 * forced whenever speed and duplex are forced.
657 */
658 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
659 if (ret_val)
660 goto out;
661
662 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
663 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);

--- 12 unchanged lines hidden (view full) ---

676 phy_data |= MII_CR_RESET;
677
678 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
679 if (ret_val)
680 goto out;
681
682 usec_delay(1);
683
657 * forced whenever speed and duplex are forced.
658 */
659 ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
660 if (ret_val)
661 goto out;
662
663 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
664 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);

--- 12 unchanged lines hidden (view full) ---

677 phy_data |= MII_CR_RESET;
678
679 ret_val = e1000_write_phy_reg(hw, PHY_CONTROL, phy_data);
680 if (ret_val)
681 goto out;
682
683 usec_delay(1);
684
684 if (hw->phy.wait_for_link) {
685 if (hw->phy.autoneg_wait_to_complete) {
685 DEBUGOUT("Waiting for forced speed/duplex link "
686 "on GG82563 phy.\n");
687
688 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
689 100000, &link);
690 if (ret_val)
691 goto out;
692
693 if (!link) {
686 DEBUGOUT("Waiting for forced speed/duplex link "
687 "on GG82563 phy.\n");
688
689 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
690 100000, &link);
691 if (ret_val)
692 goto out;
693
694 if (!link) {
694 /* We didn't get link.
695 /*
696 * We didn't get link.
695 * Reset the DSP and cross our fingers.
696 */
697 ret_val = e1000_phy_reset_dsp_generic(hw);
698 if (ret_val)
699 goto out;
700 }
701
702 /* Try once more */
703 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
704 100000, &link);
705 if (ret_val)
706 goto out;
707 }
708
709 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
710 if (ret_val)
711 goto out;
712
697 * Reset the DSP and cross our fingers.
698 */
699 ret_val = e1000_phy_reset_dsp_generic(hw);
700 if (ret_val)
701 goto out;
702 }
703
704 /* Try once more */
705 ret_val = e1000_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
706 100000, &link);
707 if (ret_val)
708 goto out;
709 }
710
711 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
712 if (ret_val)
713 goto out;
714
713 /* Resetting the phy means we need to verify the TX_CLK corresponds
715 /*
716 * Resetting the phy means we need to verify the TX_CLK corresponds
714 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
715 */
716 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
717 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
718 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
719 else
720 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
721
717 * to the link speed. 10Mbps -> 2.5MHz, else 25MHz.
718 */
719 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
720 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
721 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
722 else
723 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
724
722 /* In addition, we must re-enable CRS on Tx for both half and full
725 /*
726 * In addition, we must re-enable CRS on Tx for both half and full
723 * duplex.
724 */
725 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
726 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
727
728out:
729 return ret_val;
730}
731
732/**
733 * e1000_get_cable_length_80003es2lan - Set approximate cable length
734 * @hw: pointer to the HW structure
735 *
736 * Find the approximate cable length as measured by the GG82563 PHY.
737 * This is a function pointer entry point called by the phy module.
738 **/
727 * duplex.
728 */
729 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
730 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
731
732out:
733 return ret_val;
734}
735
736/**
737 * e1000_get_cable_length_80003es2lan - Set approximate cable length
738 * @hw: pointer to the HW structure
739 *
740 * Find the approximate cable length as measured by the GG82563 PHY.
741 * This is a function pointer entry point called by the phy module.
742 **/
739STATIC s32
740e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
743STATIC s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
741{
742 struct e1000_phy_info *phy = &hw->phy;
743 s32 ret_val;
744 u16 phy_data, index;
745
746 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
747
748 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);

--- 14 unchanged lines hidden (view full) ---

763 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
764 * @hw: pointer to the HW structure
765 * @speed: pointer to speed buffer
766 * @duplex: pointer to duplex buffer
767 *
768 * Retrieve the current speed and duplex configuration.
769 * This is a function pointer entry point called by the api module.
770 **/
744{
745 struct e1000_phy_info *phy = &hw->phy;
746 s32 ret_val;
747 u16 phy_data, index;
748
749 DEBUGFUNC("e1000_get_cable_length_80003es2lan");
750
751 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);

--- 14 unchanged lines hidden (view full) ---

766 * e1000_get_link_up_info_80003es2lan - Report speed and duplex
767 * @hw: pointer to the HW structure
768 * @speed: pointer to speed buffer
769 * @duplex: pointer to duplex buffer
770 *
771 * Retrieve the current speed and duplex configuration.
772 * This is a function pointer entry point called by the api module.
773 **/
771STATIC s32
772e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed, u16 *duplex)
774STATIC s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
775 u16 *duplex)
773{
774 s32 ret_val;
775
776 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
777
776{
777 s32 ret_val;
778
779 DEBUGFUNC("e1000_get_link_up_info_80003es2lan");
780
778 if (hw->media_type == e1000_media_type_copper) {
781 if (hw->phy.media_type == e1000_media_type_copper) {
779 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
780 speed,
781 duplex);
782 if (ret_val)
783 goto out;
784 if (*speed == SPEED_1000)
785 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
786 else
787 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
788 *duplex);
782 ret_val = e1000_get_speed_and_duplex_copper_generic(hw,
783 speed,
784 duplex);
785 if (ret_val)
786 goto out;
787 if (*speed == SPEED_1000)
788 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
789 else
790 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw,
791 *duplex);
789 } else
792 } else {
790 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
791 speed,
792 duplex);
793 ret_val = e1000_get_speed_and_duplex_fiber_serdes_generic(hw,
794 speed,
795 duplex);
796 }
793
794out:
795 return ret_val;
796}
797
798/**
799 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
800 * @hw: pointer to the HW structure
801 *
802 * Perform a global reset to the ESB2 controller.
803 * This is a function pointer entry point called by the api module.
804 **/
797
798out:
799 return ret_val;
800}
801
802/**
803 * e1000_reset_hw_80003es2lan - Reset the ESB2 controller
804 * @hw: pointer to the HW structure
805 *
806 * Perform a global reset to the ESB2 controller.
807 * This is a function pointer entry point called by the api module.
808 **/
805STATIC s32
806e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
809STATIC s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
807{
808 u32 ctrl, icr;
809 s32 ret_val;
810
811 DEBUGFUNC("e1000_reset_hw_80003es2lan");
812
810{
811 u32 ctrl, icr;
812 s32 ret_val;
813
814 DEBUGFUNC("e1000_reset_hw_80003es2lan");
815
813 /* Prevent the PCI-E bus from sticking if there is no TLP connection
816 /*
817 * Prevent the PCI-E bus from sticking if there is no TLP connection
814 * on the last TLP read/write transaction when MAC is reset.
815 */
816 ret_val = e1000_disable_pcie_master_generic(hw);
817 if (ret_val) {
818 DEBUGOUT("PCI-E Master disable polling has failed.\n");
819 }
820
821 DEBUGOUT("Masking off all interrupts\n");

--- 25 unchanged lines hidden (view full) ---

847
848/**
849 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
850 * @hw: pointer to the HW structure
851 *
852 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
853 * This is a function pointer entry point called by the api module.
854 **/
818 * on the last TLP read/write transaction when MAC is reset.
819 */
820 ret_val = e1000_disable_pcie_master_generic(hw);
821 if (ret_val) {
822 DEBUGOUT("PCI-E Master disable polling has failed.\n");
823 }
824
825 DEBUGOUT("Masking off all interrupts\n");

--- 25 unchanged lines hidden (view full) ---

851
852/**
853 * e1000_init_hw_80003es2lan - Initialize the ESB2 controller
854 * @hw: pointer to the HW structure
855 *
856 * Initialize the hw bits, LED, VFTA, MTA, link and hw counters.
857 * This is a function pointer entry point called by the api module.
858 **/
855STATIC s32
856e1000_init_hw_80003es2lan(struct e1000_hw *hw)
859STATIC s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
857{
858 struct e1000_mac_info *mac = &hw->mac;
859 u32 reg_data;
860 s32 ret_val;
861 u16 i;
862
863 DEBUGFUNC("e1000_init_hw_80003es2lan");
864
865 e1000_initialize_hw_bits_80003es2lan(hw);
866
867 /* Initialize identification LED */
868 ret_val = e1000_id_led_init_generic(hw);
869 if (ret_val) {
870 DEBUGOUT("Error initializing identification LED\n");
860{
861 struct e1000_mac_info *mac = &hw->mac;
862 u32 reg_data;
863 s32 ret_val;
864 u16 i;
865
866 DEBUGFUNC("e1000_init_hw_80003es2lan");
867
868 e1000_initialize_hw_bits_80003es2lan(hw);
869
870 /* Initialize identification LED */
871 ret_val = e1000_id_led_init_generic(hw);
872 if (ret_val) {
873 DEBUGOUT("Error initializing identification LED\n");
871 goto out;
874 /* This is not fatal and we should not stop init due to this */
872 }
873
874 /* Disabling VLAN filtering */
875 DEBUGOUT("Initializing the IEEE VLAN\n");
876 e1000_clear_vfta(hw);
877
878 /* Setup the receive address. */
879 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
880
881 /* Zero out the Multicast HASH table */
882 DEBUGOUT("Zeroing the MTA\n");
883 for (i = 0; i < mac->mta_reg_count; i++)
884 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
885
886 /* Setup link and flow control */
887 ret_val = e1000_setup_link(hw);
888
889 /* Set the transmit descriptor write-back policy */
875 }
876
877 /* Disabling VLAN filtering */
878 DEBUGOUT("Initializing the IEEE VLAN\n");
879 e1000_clear_vfta(hw);
880
881 /* Setup the receive address. */
882 e1000_init_rx_addrs_generic(hw, mac->rar_entry_count);
883
884 /* Zero out the Multicast HASH table */
885 DEBUGOUT("Zeroing the MTA\n");
886 for (i = 0; i < mac->mta_reg_count; i++)
887 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
888
889 /* Setup link and flow control */
890 ret_val = e1000_setup_link(hw);
891
892 /* Set the transmit descriptor write-back policy */
890 reg_data = E1000_READ_REG(hw, E1000_TXDCTL);
893 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
891 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
892 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
894 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
895 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
893 E1000_WRITE_REG(hw, E1000_TXDCTL, reg_data);
896 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
894
895 /* ...for both queues. */
897
898 /* ...for both queues. */
896 reg_data = E1000_READ_REG(hw, E1000_TXDCTL1);
899 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
897 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
898 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
900 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
901 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC;
899 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg_data);
902 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
900
901 /* Enable retransmit on late collisions */
902 reg_data = E1000_READ_REG(hw, E1000_TCTL);
903 reg_data |= E1000_TCTL_RTLC;
904 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
905
906 /* Configure Gigabit Carry Extend Padding */
907 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);

--- 6 unchanged lines hidden (view full) ---

914 reg_data &= ~E1000_TIPG_IPGT_MASK;
915 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
916 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
917
918 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
919 reg_data &= ~0x00100000;
920 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
921
903
904 /* Enable retransmit on late collisions */
905 reg_data = E1000_READ_REG(hw, E1000_TCTL);
906 reg_data |= E1000_TCTL_RTLC;
907 E1000_WRITE_REG(hw, E1000_TCTL, reg_data);
908
909 /* Configure Gigabit Carry Extend Padding */
910 reg_data = E1000_READ_REG(hw, E1000_TCTL_EXT);

--- 6 unchanged lines hidden (view full) ---

917 reg_data &= ~E1000_TIPG_IPGT_MASK;
918 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
919 E1000_WRITE_REG(hw, E1000_TIPG, reg_data);
920
921 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
922 reg_data &= ~0x00100000;
923 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
924
922 /* Clear all of the statistics registers (clear on read). It is
925 /*
926 * Clear all of the statistics registers (clear on read). It is
923 * important that we do this after we have tried to establish link
924 * because the symbol error count will increment wildly if there
925 * is no link.
926 */
927 e1000_clear_hw_cntrs_80003es2lan(hw);
928
927 * important that we do this after we have tried to establish link
928 * because the symbol error count will increment wildly if there
929 * is no link.
930 */
931 e1000_clear_hw_cntrs_80003es2lan(hw);
932
929out:
930 return ret_val;
931}
932
933/**
934 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
935 * @hw: pointer to the HW structure
936 *
937 * Initializes required hardware-dependent bits needed for normal operation.
938 **/
933 return ret_val;
934}
935
936/**
937 * e1000_initialize_hw_bits_80003es2lan - Init hw bits of ESB2
938 * @hw: pointer to the HW structure
939 *
940 * Initializes required hardware-dependent bits needed for normal operation.
941 **/
939static void
940e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
942static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
941{
942 u32 reg;
943
944 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
945
946 if (hw->mac.disable_hw_init_bits)
947 goto out;
948
949 /* Transmit Descriptor Control 0 */
943{
944 u32 reg;
945
946 DEBUGFUNC("e1000_initialize_hw_bits_80003es2lan");
947
948 if (hw->mac.disable_hw_init_bits)
949 goto out;
950
951 /* Transmit Descriptor Control 0 */
950 reg = E1000_READ_REG(hw, E1000_TXDCTL);
952 reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
951 reg |= (1 << 22);
953 reg |= (1 << 22);
952 E1000_WRITE_REG(hw, E1000_TXDCTL, reg);
954 E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
953
954 /* Transmit Descriptor Control 1 */
955
956 /* Transmit Descriptor Control 1 */
955 reg = E1000_READ_REG(hw, E1000_TXDCTL1);
957 reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
956 reg |= (1 << 22);
958 reg |= (1 << 22);
957 E1000_WRITE_REG(hw, E1000_TXDCTL1, reg);
959 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
958
959 /* Transmit Arbitration Control 0 */
960
961 /* Transmit Arbitration Control 0 */
960 reg = E1000_READ_REG(hw, E1000_TARC0);
962 reg = E1000_READ_REG(hw, E1000_TARC(0));
961 reg &= ~(0xF << 27); /* 30:27 */
963 reg &= ~(0xF << 27); /* 30:27 */
962 if (hw->media_type != e1000_media_type_copper)
964 if (hw->phy.media_type != e1000_media_type_copper)
963 reg &= ~(1 << 20);
965 reg &= ~(1 << 20);
964 E1000_WRITE_REG(hw, E1000_TARC0, reg);
966 E1000_WRITE_REG(hw, E1000_TARC(0), reg);
965
966 /* Transmit Arbitration Control 1 */
967
968 /* Transmit Arbitration Control 1 */
967 reg = E1000_READ_REG(hw, E1000_TARC1);
969 reg = E1000_READ_REG(hw, E1000_TARC(1));
968 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
969 reg &= ~(1 << 28);
970 else
971 reg |= (1 << 28);
970 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
971 reg &= ~(1 << 28);
972 else
973 reg |= (1 << 28);
972 E1000_WRITE_REG(hw, E1000_TARC1, reg);
974 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
973
974out:
975 return;
976}
977
978/**
979 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
980 * @hw: pointer to the HW structure
981 *
982 * Setup some GG82563 PHY registers for obtaining link
983 **/
975
976out:
977 return;
978}
979
980/**
981 * e1000_copper_link_setup_gg82563_80003es2lan - Configure GG82563 Link
982 * @hw: pointer to the HW structure
983 *
984 * Setup some GG82563 PHY registers for obtaining link
985 **/
984static s32
985e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
986static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
986{
987 struct e1000_phy_info *phy = &hw->phy;
988 s32 ret_val;
989 u32 ctrl_ext;
990 u16 data;
991
992 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
993

--- 7 unchanged lines hidden (view full) ---

1001 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1002 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1003
1004 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1005 data);
1006 if (ret_val)
1007 goto out;
1008
987{
988 struct e1000_phy_info *phy = &hw->phy;
989 s32 ret_val;
990 u32 ctrl_ext;
991 u16 data;
992
993 DEBUGFUNC("e1000_copper_link_setup_gg82563_80003es2lan");
994

--- 7 unchanged lines hidden (view full) ---

1002 /* Use 25MHz for both link down and 1000Base-T for Tx clock. */
1003 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
1004
1005 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1006 data);
1007 if (ret_val)
1008 goto out;
1009
1009 /* Options:
1010 /*
1011 * Options:
1010 * MDI/MDI-X = 0 (default)
1011 * 0 - Auto for all speeds
1012 * 1 - MDI mode
1013 * 2 - MDI-X mode
1014 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1015 */
1016 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1017 if (ret_val)

--- 9 unchanged lines hidden (view full) ---

1027 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1028 break;
1029 case 0:
1030 default:
1031 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1032 break;
1033 }
1034
1012 * MDI/MDI-X = 0 (default)
1013 * 0 - Auto for all speeds
1014 * 1 - MDI mode
1015 * 2 - MDI-X mode
1016 * 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1017 */
1018 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &data);
1019 if (ret_val)

--- 9 unchanged lines hidden (view full) ---

1029 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1030 break;
1031 case 0:
1032 default:
1033 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1034 break;
1035 }
1036
1035 /* Options:
1037 /*
1038 * Options:
1036 * disable_polarity_correction = 0 (default)
1037 * Automatic Correction for Reversed Cable Polarity
1038 * 0 - Disabled
1039 * 1 - Enabled
1040 */
1041 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1039 * disable_polarity_correction = 0 (default)
1040 * Automatic Correction for Reversed Cable Polarity
1041 * 0 - Disabled
1042 * 1 - Enabled
1043 */
1044 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1042 if (phy->disable_polarity_correction == TRUE)
1045 if (phy->disable_polarity_correction)
1043 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1044
1045 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1046 if (ret_val)
1047 goto out;
1048
1049 /* SW Reset the PHY so all changes take effect */
1050 ret_val = e1000_phy_commit(hw);
1051 if (ret_val) {
1052 DEBUGOUT("Error Resetting the PHY\n");
1053 goto out;
1054 }
1055
1056 }
1057
1046 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1047
1048 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, data);
1049 if (ret_val)
1050 goto out;
1051
1052 /* SW Reset the PHY so all changes take effect */
1053 ret_val = e1000_phy_commit(hw);
1054 if (ret_val) {
1055 DEBUGOUT("Error Resetting the PHY\n");
1056 goto out;
1057 }
1058
1059 }
1060
1058 /* Bypass RX and TX FIFO's */
1061 /* Bypass Rx and Tx FIFO's */
1059 ret_val = e1000_write_kmrn_reg(hw,
1060 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1061 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1062 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1063 if (ret_val)
1064 goto out;
1065
1062 ret_val = e1000_write_kmrn_reg(hw,
1063 E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL,
1064 E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
1065 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
1066 if (ret_val)
1067 goto out;
1068
1069 ret_val = e1000_read_kmrn_reg(hw,
1070 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1071 &data);
1072 if (ret_val)
1073 goto out;
1074 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
1075 ret_val = e1000_write_kmrn_reg(hw,
1076 E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE,
1077 data);
1078 if (ret_val)
1079 goto out;
1080
1066 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1067 if (ret_val)
1068 goto out;
1069
1070 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1071 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1072 if (ret_val)
1073 goto out;
1074
1075 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1076 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1077 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1078
1079 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1080 if (ret_val)
1081 goto out;
1082
1081 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &data);
1082 if (ret_val)
1083 goto out;
1084
1085 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1086 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, data);
1087 if (ret_val)
1088 goto out;
1089
1090 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1091 ctrl_ext &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1092 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1093
1094 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
1095 if (ret_val)
1096 goto out;
1097
1083 /* Do not init these registers when the HW is in IAMT mode, since the
1098 /*
1099 * Do not init these registers when the HW is in IAMT mode, since the
1084 * firmware will have already initialized them. We only initialize
1085 * them if the HW is not in IAMT mode.
1086 */
1100 * firmware will have already initialized them. We only initialize
1101 * them if the HW is not in IAMT mode.
1102 */
1087 if (e1000_check_mng_mode(hw) == FALSE) {
1103 if (!(e1000_check_mng_mode(hw))) {
1088 /* Enable Electrical Idle on the PHY */
1089 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1090 ret_val = e1000_write_phy_reg(hw,
1091 GG82563_PHY_PWR_MGMT_CTRL,
1092 data);
1093 if (ret_val)
1094 goto out;
1095

--- 7 unchanged lines hidden (view full) ---

1103 ret_val = e1000_write_phy_reg(hw,
1104 GG82563_PHY_KMRN_MODE_CTRL,
1105 data);
1106
1107 if (ret_val)
1108 goto out;
1109 }
1110
1104 /* Enable Electrical Idle on the PHY */
1105 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1106 ret_val = e1000_write_phy_reg(hw,
1107 GG82563_PHY_PWR_MGMT_CTRL,
1108 data);
1109 if (ret_val)
1110 goto out;
1111

--- 7 unchanged lines hidden (view full) ---

1119 ret_val = e1000_write_phy_reg(hw,
1120 GG82563_PHY_KMRN_MODE_CTRL,
1121 data);
1122
1123 if (ret_val)
1124 goto out;
1125 }
1126
1111 /* Workaround: Disable padding in Kumeran interface in the MAC
1127 /*
1128 * Workaround: Disable padding in Kumeran interface in the MAC
1112 * and in the PHY to avoid CRC errors.
1113 */
1114 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1115 if (ret_val)
1116 goto out;
1117
1118 data |= GG82563_ICR_DIS_PADDING;
1119 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data);

--- 6 unchanged lines hidden (view full) ---

1126
1127/**
1128 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1129 * @hw: pointer to the HW structure
1130 *
1131 * Essentially a wrapper for setting up all things "copper" related.
1132 * This is a function pointer entry point called by the mac module.
1133 **/
1129 * and in the PHY to avoid CRC errors.
1130 */
1131 ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL, &data);
1132 if (ret_val)
1133 goto out;
1134
1135 data |= GG82563_ICR_DIS_PADDING;
1136 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL, data);

--- 6 unchanged lines hidden (view full) ---

1143
1144/**
1145 * e1000_setup_copper_link_80003es2lan - Setup Copper Link for ESB2
1146 * @hw: pointer to the HW structure
1147 *
1148 * Essentially a wrapper for setting up all things "copper" related.
1149 * This is a function pointer entry point called by the mac module.
1150 **/
1134STATIC s32
1135e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1151STATIC s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1136{
1137 u32 ctrl;
1138 s32 ret_val;
1139 u16 reg_data;
1140
1141 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1142
1143 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1144 ctrl |= E1000_CTRL_SLU;
1145 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1146 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1147
1152{
1153 u32 ctrl;
1154 s32 ret_val;
1155 u16 reg_data;
1156
1157 DEBUGFUNC("e1000_setup_copper_link_80003es2lan");
1158
1159 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1160 ctrl |= E1000_CTRL_SLU;
1161 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1162 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1163
1148 /* Set the mac to wait the maximum time between each
1164 /*
1165 * Set the mac to wait the maximum time between each
1149 * iteration and increase the max iterations when
1166 * iteration and increase the max iterations when
1150 * polling the phy; this fixes erroneous timeouts at 10Mbps. */
1167 * polling the phy; this fixes erroneous timeouts at 10Mbps.
1168 */
1151 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1152 if (ret_val)
1153 goto out;
1154 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1155 if (ret_val)
1156 goto out;
1157 reg_data |= 0x3F;
1158 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);

--- 24 unchanged lines hidden (view full) ---

1183/**
1184 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1185 * @hw: pointer to the HW structure
1186 * @duplex: current duplex setting
1187 *
1188 * Configure the KMRN interface by applying last minute quirks for
1189 * 10/100 operation.
1190 **/
1169 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
1170 if (ret_val)
1171 goto out;
1172 ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
1173 if (ret_val)
1174 goto out;
1175 reg_data |= 0x3F;
1176 ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);

--- 24 unchanged lines hidden (view full) ---

1201/**
1202 * e1000_cfg_kmrn_10_100_80003es2lan - Apply "quirks" for 10/100 operation
1203 * @hw: pointer to the HW structure
1204 * @duplex: current duplex setting
1205 *
1206 * Configure the KMRN interface by applying last minute quirks for
1207 * 10/100 operation.
1208 **/
1191static s32
1192e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1209static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1193{
1194 s32 ret_val = E1000_SUCCESS;
1195 u32 tipg;
1196 u32 i = 0;
1197 u16 reg_data, reg_data2;
1198
1199 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1200

--- 37 unchanged lines hidden (view full) ---

1238
1239/**
1240 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1241 * @hw: pointer to the HW structure
1242 *
1243 * Configure the KMRN interface by applying last minute quirks for
1244 * gigabit operation.
1245 **/
1210{
1211 s32 ret_val = E1000_SUCCESS;
1212 u32 tipg;
1213 u32 i = 0;
1214 u16 reg_data, reg_data2;
1215
1216 DEBUGFUNC("e1000_configure_kmrn_for_10_100");
1217

--- 37 unchanged lines hidden (view full) ---

1255
1256/**
1257 * e1000_cfg_kmrn_1000_80003es2lan - Apply "quirks" for gigabit operation
1258 * @hw: pointer to the HW structure
1259 *
1260 * Configure the KMRN interface by applying last minute quirks for
1261 * gigabit operation.
1262 **/
1246static s32
1247e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1263static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1248{
1249 s32 ret_val = E1000_SUCCESS;
1250 u16 reg_data, reg_data2;
1251 u32 tipg;
1252 u32 i = 0;
1253
1254 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1255

--- 27 unchanged lines hidden (view full) ---

1283 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1284 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1285
1286out:
1287 return ret_val;
1288}
1289
1290/**
1264{
1265 s32 ret_val = E1000_SUCCESS;
1266 u16 reg_data, reg_data2;
1267 u32 tipg;
1268 u32 i = 0;
1269
1270 DEBUGFUNC("e1000_configure_kmrn_for_1000");
1271

--- 27 unchanged lines hidden (view full) ---

1299 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1300 ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1301
1302out:
1303 return ret_val;
1304}
1305
1306/**
1307 * e1000_power_down_phy_copper_80003es2lan - Remove link during PHY power down
1308 * @hw: pointer to the HW structure
1309 *
1310 * In the case of a PHY power down to save power, or to turn off link during a
1311 * driver unload, or wake on lan is not enabled, remove the link.
1312 **/
1313STATIC void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1314{
1315 /* If the management interface is not enabled, then power down */
1316 if (!(e1000_check_mng_mode(hw) || e1000_check_reset_block(hw)))
1317 e1000_power_down_phy_copper(hw);
1318
1319 return;
1320}
1321
1322/**
1291 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1292 * @hw: pointer to the HW structure
1293 *
1294 * Clears the hardware counters by reading the counter registers.
1295 **/
1323 * e1000_clear_hw_cntrs_80003es2lan - Clear device specific hardware counters
1324 * @hw: pointer to the HW structure
1325 *
1326 * Clears the hardware counters by reading the counter registers.
1327 **/
1296STATIC void
1297e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1328STATIC void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1298{
1299 volatile u32 temp;
1300
1301 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1302
1303 e1000_clear_hw_cntrs_base_generic(hw);
1304
1305 temp = E1000_READ_REG(hw, E1000_PRC64);

--- 34 unchanged lines hidden --- 		1329{
1330 volatile u32 temp;
1331
1332 DEBUGFUNC("e1000_clear_hw_cntrs_80003es2lan");
1333
1334 e1000_clear_hw_cntrs_base_generic(hw);
1335
1336 temp = E1000_READ_REG(hw, E1000_PRC64);

--- 34 unchanged lines hidden ---