31
32#include <dev/drm2/drmP.h>
33#include <dev/drm2/drm_crtc_helper.h>
34#include <dev/drm2/radeon/radeon_drm.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "atom.h"
38
39static const char radeon_family_name[][16] = {
40 "R100",
41 "RV100",
42 "RS100",
43 "RV200",
44 "RS200",
45 "R200",
46 "RV250",
47 "RS300",
48 "RV280",
49 "R300",
50 "R350",
51 "RV350",
52 "RV380",
53 "R420",
54 "R423",
55 "RV410",
56 "RS400",
57 "RS480",
58 "RS600",
59 "RS690",
60 "RS740",
61 "RV515",
62 "R520",
63 "RV530",
64 "RV560",
65 "RV570",
66 "R580",
67 "R600",
68 "RV610",
69 "RV630",
70 "RV670",
71 "RV620",
72 "RV635",
73 "RS780",
74 "RS880",
75 "RV770",
76 "RV730",
77 "RV710",
78 "RV740",
79 "CEDAR",
80 "REDWOOD",
81 "JUNIPER",
82 "CYPRESS",
83 "HEMLOCK",
84 "PALM",
85 "SUMO",
86 "SUMO2",
87 "BARTS",
88 "TURKS",
89 "CAICOS",
90 "CAYMAN",
91 "ARUBA",
92 "TAHITI",
93 "PITCAIRN",
94 "VERDE",
95 "LAST",
96};
97
98/**
99 * radeon_surface_init - Clear GPU surface registers.
100 *
101 * @rdev: radeon_device pointer
102 *
103 * Clear GPU surface registers (r1xx-r5xx).
104 */
105void radeon_surface_init(struct radeon_device *rdev)
106{
107 /* FIXME: check this out */
108 if (rdev->family < CHIP_R600) {
109 int i;
110
111 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
112 if (rdev->surface_regs[i].bo)
113 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
114 else
115 radeon_clear_surface_reg(rdev, i);
116 }
117 /* enable surfaces */
118 WREG32(RADEON_SURFACE_CNTL, 0);
119 }
120}
121
122/*
123 * GPU scratch registers helpers function.
124 */
125/**
126 * radeon_scratch_init - Init scratch register driver information.
127 *
128 * @rdev: radeon_device pointer
129 *
130 * Init CP scratch register driver information (r1xx-r5xx)
131 */
132void radeon_scratch_init(struct radeon_device *rdev)
133{
134 int i;
135
136 /* FIXME: check this out */
137 if (rdev->family < CHIP_R300) {
138 rdev->scratch.num_reg = 5;
139 } else {
140 rdev->scratch.num_reg = 7;
141 }
142 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
143 for (i = 0; i < rdev->scratch.num_reg; i++) {
144 rdev->scratch.free[i] = true;
145 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
146 }
147}
148
149/**
150 * radeon_scratch_get - Allocate a scratch register
151 *
152 * @rdev: radeon_device pointer
153 * @reg: scratch register mmio offset
154 *
155 * Allocate a CP scratch register for use by the driver (all asics).
156 * Returns 0 on success or -EINVAL on failure.
157 */
158int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
159{
160 int i;
161
162 for (i = 0; i < rdev->scratch.num_reg; i++) {
163 if (rdev->scratch.free[i]) {
164 rdev->scratch.free[i] = false;
165 *reg = rdev->scratch.reg[i];
166 return 0;
167 }
168 }
169 return -EINVAL;
170}
171
172/**
173 * radeon_scratch_free - Free a scratch register
174 *
175 * @rdev: radeon_device pointer
176 * @reg: scratch register mmio offset
177 *
178 * Free a CP scratch register allocated for use by the driver (all asics)
179 */
180void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
181{
182 int i;
183
184 for (i = 0; i < rdev->scratch.num_reg; i++) {
185 if (rdev->scratch.reg[i] == reg) {
186 rdev->scratch.free[i] = true;
187 return;
188 }
189 }
190}
191
192/*
193 * radeon_wb_*()
| 31
32#include <dev/drm2/drmP.h>
33#include <dev/drm2/drm_crtc_helper.h>
34#include <dev/drm2/radeon/radeon_drm.h>
35#include "radeon_reg.h"
36#include "radeon.h"
37#include "atom.h"
38
39static const char radeon_family_name[][16] = {
40 "R100",
41 "RV100",
42 "RS100",
43 "RV200",
44 "RS200",
45 "R200",
46 "RV250",
47 "RS300",
48 "RV280",
49 "R300",
50 "R350",
51 "RV350",
52 "RV380",
53 "R420",
54 "R423",
55 "RV410",
56 "RS400",
57 "RS480",
58 "RS600",
59 "RS690",
60 "RS740",
61 "RV515",
62 "R520",
63 "RV530",
64 "RV560",
65 "RV570",
66 "R580",
67 "R600",
68 "RV610",
69 "RV630",
70 "RV670",
71 "RV620",
72 "RV635",
73 "RS780",
74 "RS880",
75 "RV770",
76 "RV730",
77 "RV710",
78 "RV740",
79 "CEDAR",
80 "REDWOOD",
81 "JUNIPER",
82 "CYPRESS",
83 "HEMLOCK",
84 "PALM",
85 "SUMO",
86 "SUMO2",
87 "BARTS",
88 "TURKS",
89 "CAICOS",
90 "CAYMAN",
91 "ARUBA",
92 "TAHITI",
93 "PITCAIRN",
94 "VERDE",
95 "LAST",
96};
97
98/**
99 * radeon_surface_init - Clear GPU surface registers.
100 *
101 * @rdev: radeon_device pointer
102 *
103 * Clear GPU surface registers (r1xx-r5xx).
104 */
105void radeon_surface_init(struct radeon_device *rdev)
106{
107 /* FIXME: check this out */
108 if (rdev->family < CHIP_R600) {
109 int i;
110
111 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
112 if (rdev->surface_regs[i].bo)
113 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
114 else
115 radeon_clear_surface_reg(rdev, i);
116 }
117 /* enable surfaces */
118 WREG32(RADEON_SURFACE_CNTL, 0);
119 }
120}
121
122/*
123 * GPU scratch registers helpers function.
124 */
125/**
126 * radeon_scratch_init - Init scratch register driver information.
127 *
128 * @rdev: radeon_device pointer
129 *
130 * Init CP scratch register driver information (r1xx-r5xx)
131 */
132void radeon_scratch_init(struct radeon_device *rdev)
133{
134 int i;
135
136 /* FIXME: check this out */
137 if (rdev->family < CHIP_R300) {
138 rdev->scratch.num_reg = 5;
139 } else {
140 rdev->scratch.num_reg = 7;
141 }
142 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
143 for (i = 0; i < rdev->scratch.num_reg; i++) {
144 rdev->scratch.free[i] = true;
145 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
146 }
147}
148
149/**
150 * radeon_scratch_get - Allocate a scratch register
151 *
152 * @rdev: radeon_device pointer
153 * @reg: scratch register mmio offset
154 *
155 * Allocate a CP scratch register for use by the driver (all asics).
156 * Returns 0 on success or -EINVAL on failure.
157 */
158int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
159{
160 int i;
161
162 for (i = 0; i < rdev->scratch.num_reg; i++) {
163 if (rdev->scratch.free[i]) {
164 rdev->scratch.free[i] = false;
165 *reg = rdev->scratch.reg[i];
166 return 0;
167 }
168 }
169 return -EINVAL;
170}
171
172/**
173 * radeon_scratch_free - Free a scratch register
174 *
175 * @rdev: radeon_device pointer
176 * @reg: scratch register mmio offset
177 *
178 * Free a CP scratch register allocated for use by the driver (all asics)
179 */
180void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
181{
182 int i;
183
184 for (i = 0; i < rdev->scratch.num_reg; i++) {
185 if (rdev->scratch.reg[i] == reg) {
186 rdev->scratch.free[i] = true;
187 return;
188 }
189 }
190}
191
192/*
193 * radeon_wb_*()
|
195 * in memory with the status of certain GPU events (fences, ring pointers,
196 * etc.).
197 */
198
199/**
200 * radeon_wb_disable - Disable Writeback
201 *
202 * @rdev: radeon_device pointer
203 *
204 * Disables Writeback (all asics). Used for suspend.
205 */
206void radeon_wb_disable(struct radeon_device *rdev)
207{
208 int r;
209
210 if (rdev->wb.wb_obj) {
211 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
212 if (unlikely(r != 0))
213 return;
214 radeon_bo_kunmap(rdev->wb.wb_obj);
215 radeon_bo_unpin(rdev->wb.wb_obj);
216 radeon_bo_unreserve(rdev->wb.wb_obj);
217 }
218 rdev->wb.enabled = false;
219}
220
221/**
222 * radeon_wb_fini - Disable Writeback and free memory
223 *
224 * @rdev: radeon_device pointer
225 *
226 * Disables Writeback and frees the Writeback memory (all asics).
227 * Used at driver shutdown.
228 */
229void radeon_wb_fini(struct radeon_device *rdev)
230{
231 radeon_wb_disable(rdev);
232 if (rdev->wb.wb_obj) {
233 radeon_bo_unref(&rdev->wb.wb_obj);
234 rdev->wb.wb = NULL;
235 rdev->wb.wb_obj = NULL;
236 }
237}
238
239/**
240 * radeon_wb_init- Init Writeback driver info and allocate memory
241 *
242 * @rdev: radeon_device pointer
243 *
244 * Disables Writeback and frees the Writeback memory (all asics).
245 * Used at driver startup.
246 * Returns 0 on success or an -error on failure.
247 */
248int radeon_wb_init(struct radeon_device *rdev)
249{
250 int r;
251 void *wb_ptr; /* FreeBSD: to please GCC 4.2. */
252
253 if (rdev->wb.wb_obj == NULL) {
254 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
255 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
256 if (r) {
257 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
258 return r;
259 }
260 }
261 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
262 if (unlikely(r != 0)) {
263 radeon_wb_fini(rdev);
264 return r;
265 }
266 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
267 &rdev->wb.gpu_addr);
268 if (r) {
269 radeon_bo_unreserve(rdev->wb.wb_obj);
270 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
271 radeon_wb_fini(rdev);
272 return r;
273 }
274 wb_ptr = &rdev->wb.wb;
275 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr);
276 radeon_bo_unreserve(rdev->wb.wb_obj);
277 if (r) {
278 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
279 radeon_wb_fini(rdev);
280 return r;
281 }
282
283 /* clear wb memory */
284 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE);
285 /* disable event_write fences */
286 rdev->wb.use_event = false;
287 /* disabled via module param */
288 if (radeon_no_wb == 1) {
289 rdev->wb.enabled = false;
290 } else {
291 if (rdev->flags & RADEON_IS_AGP) {
292 /* often unreliable on AGP */
293 rdev->wb.enabled = false;
294 } else if (rdev->family < CHIP_R300) {
295 /* often unreliable on pre-r300 */
296 rdev->wb.enabled = false;
297 } else {
298 rdev->wb.enabled = true;
299 /* event_write fences are only available on r600+ */
300 if (rdev->family >= CHIP_R600) {
301 rdev->wb.use_event = true;
302 }
303 }
304 }
305 /* always use writeback/events on NI, APUs */
306 if (rdev->family >= CHIP_PALM) {
307 rdev->wb.enabled = true;
308 rdev->wb.use_event = true;
309 }
310
311 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
312
313 return 0;
314}
315
316/**
317 * radeon_vram_location - try to find VRAM location
318 * @rdev: radeon device structure holding all necessary informations
319 * @mc: memory controller structure holding memory informations
320 * @base: base address at which to put VRAM
321 *
322 * Function will place try to place VRAM at base address provided
323 * as parameter (which is so far either PCI aperture address or
324 * for IGP TOM base address).
325 *
326 * If there is not enough space to fit the unvisible VRAM in the 32bits
327 * address space then we limit the VRAM size to the aperture.
328 *
329 * If we are using AGP and if the AGP aperture doesn't allow us to have
330 * room for all the VRAM than we restrict the VRAM to the PCI aperture
331 * size and print a warning.
332 *
333 * This function will never fails, worst case are limiting VRAM.
334 *
335 * Note: GTT start, end, size should be initialized before calling this
336 * function on AGP platform.
337 *
338 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
339 * this shouldn't be a problem as we are using the PCI aperture as a reference.
340 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
341 * not IGP.
342 *
343 * Note: we use mc_vram_size as on some board we need to program the mc to
344 * cover the whole aperture even if VRAM size is inferior to aperture size
345 * Novell bug 204882 + along with lots of ubuntu ones
346 *
347 * Note: when limiting vram it's safe to overwritte real_vram_size because
348 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
349 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
350 * ones)
351 *
352 * Note: IGP TOM addr should be the same as the aperture addr, we don't
353 * explicitly check for that thought.
354 *
355 * FIXME: when reducing VRAM size align new size on power of 2.
356 */
357void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
358{
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
360
361 mc->vram_start = base;
362 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size;
366 }
367 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
368 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
369 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
370 mc->real_vram_size = mc->aper_size;
371 mc->mc_vram_size = mc->aper_size;
372 }
373 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
374 if (limit && limit < mc->real_vram_size)
375 mc->real_vram_size = limit;
376 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
377 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
378 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
379}
380
381/**
382 * radeon_gtt_location - try to find GTT location
383 * @rdev: radeon device structure holding all necessary informations
384 * @mc: memory controller structure holding memory informations
385 *
386 * Function will place try to place GTT before or after VRAM.
387 *
388 * If GTT size is bigger than space left then we ajust GTT size.
389 * Thus function will never fails.
390 *
391 * FIXME: when reducing GTT size align new size on power of 2.
392 */
393void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
394{
395 u64 size_af, size_bf;
396
397 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) {
401 dev_warn(rdev->dev, "limiting GTT\n");
402 mc->gtt_size = size_bf;
403 }
404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
405 } else {
406 if (mc->gtt_size > size_af) {
407 dev_warn(rdev->dev, "limiting GTT\n");
408 mc->gtt_size = size_af;
409 }
410 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
411 }
412 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
413 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
414 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end);
415}
416
417/*
418 * GPU helpers function.
419 */
420/**
421 * radeon_card_posted - check if the hw has already been initialized
422 *
423 * @rdev: radeon_device pointer
424 *
425 * Check if the asic has been initialized (all asics).
426 * Used at driver startup.
427 * Returns true if initialized or false if not.
428 */
429bool radeon_card_posted(struct radeon_device *rdev)
430{
431 uint32_t reg;
432
433#ifdef FREEBSD_WIP
434 if (efi_enabled(EFI_BOOT) &&
435 rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE)
436 return false;
437#endif /* FREEBSD_WIP */
438
439 /* first check CRTCs */
440 if (ASIC_IS_DCE41(rdev)) {
441 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
442 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
443 if (reg & EVERGREEN_CRTC_MASTER_EN)
444 return true;
445 } else if (ASIC_IS_DCE4(rdev)) {
446 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
451 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
452 if (reg & EVERGREEN_CRTC_MASTER_EN)
453 return true;
454 } else if (ASIC_IS_AVIVO(rdev)) {
455 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
456 RREG32(AVIVO_D2CRTC_CONTROL);
457 if (reg & AVIVO_CRTC_EN) {
458 return true;
459 }
460 } else {
461 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
462 RREG32(RADEON_CRTC2_GEN_CNTL);
463 if (reg & RADEON_CRTC_EN) {
464 return true;
465 }
466 }
467
468 /* then check MEM_SIZE, in case the crtcs are off */
469 if (rdev->family >= CHIP_R600)
470 reg = RREG32(R600_CONFIG_MEMSIZE);
471 else
472 reg = RREG32(RADEON_CONFIG_MEMSIZE);
473
474 if (reg)
475 return true;
476
477 return false;
478
479}
480
481/**
482 * radeon_update_bandwidth_info - update display bandwidth params
483 *
484 * @rdev: radeon_device pointer
485 *
486 * Used when sclk/mclk are switched or display modes are set.
487 * params are used to calculate display watermarks (all asics)
488 */
489void radeon_update_bandwidth_info(struct radeon_device *rdev)
490{
491 fixed20_12 a;
492 u32 sclk = rdev->pm.current_sclk;
493 u32 mclk = rdev->pm.current_mclk;
494
495 /* sclk/mclk in Mhz */
496 a.full = dfixed_const(100);
497 rdev->pm.sclk.full = dfixed_const(sclk);
498 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
499 rdev->pm.mclk.full = dfixed_const(mclk);
500 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
501
502 if (rdev->flags & RADEON_IS_IGP) {
503 a.full = dfixed_const(16);
504 /* core_bandwidth = sclk(Mhz) * 16 */
505 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
506 }
507}
508
509/**
510 * radeon_boot_test_post_card - check and possibly initialize the hw
511 *
512 * @rdev: radeon_device pointer
513 *
514 * Check if the asic is initialized and if not, attempt to initialize
515 * it (all asics).
516 * Returns true if initialized or false if not.
517 */
518bool radeon_boot_test_post_card(struct radeon_device *rdev)
519{
520 if (radeon_card_posted(rdev))
521 return true;
522
523 if (rdev->bios) {
524 DRM_INFO("GPU not posted. posting now...\n");
525 if (rdev->is_atom_bios)
526 atom_asic_init(rdev->mode_info.atom_context);
527 else
528 radeon_combios_asic_init(rdev->ddev);
529 return true;
530 } else {
531 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
532 return false;
533 }
534}
535
536/**
537 * radeon_dummy_page_init - init dummy page used by the driver
538 *
539 * @rdev: radeon_device pointer
540 *
541 * Allocate the dummy page used by the driver (all asics).
542 * This dummy page is used by the driver as a filler for gart entries
543 * when pages are taken out of the GART
544 * Returns 0 on success, -ENOMEM on failure.
545 */
546int radeon_dummy_page_init(struct radeon_device *rdev)
547{
548 if (rdev->dummy_page.dmah)
549 return 0;
550 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev,
551 PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXADDR_32BIT);
552 if (rdev->dummy_page.dmah == NULL)
553 return -ENOMEM;
554 rdev->dummy_page.addr = rdev->dummy_page.dmah->busaddr;
555 return 0;
556}
557
558/**
559 * radeon_dummy_page_fini - free dummy page used by the driver
560 *
561 * @rdev: radeon_device pointer
562 *
563 * Frees the dummy page used by the driver (all asics).
564 */
565void radeon_dummy_page_fini(struct radeon_device *rdev)
566{
567 if (rdev->dummy_page.dmah == NULL)
568 return;
569 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah);
570 rdev->dummy_page.dmah = NULL;
571 rdev->dummy_page.addr = 0;
572}
573
574
575/* ATOM accessor methods */
576/*
577 * ATOM is an interpreted byte code stored in tables in the vbios. The
578 * driver registers callbacks to access registers and the interpreter
579 * in the driver parses the tables and executes then to program specific
580 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
581 * atombios.h, and atom.c
582 */
583
584/**
585 * cail_pll_read - read PLL register
586 *
587 * @info: atom card_info pointer
588 * @reg: PLL register offset
589 *
590 * Provides a PLL register accessor for the atom interpreter (r4xx+).
591 * Returns the value of the PLL register.
592 */
593static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
594{
595 struct radeon_device *rdev = info->dev->dev_private;
596 uint32_t r;
597
598 r = rdev->pll_rreg(rdev, reg);
599 return r;
600}
601
602/**
603 * cail_pll_write - write PLL register
604 *
605 * @info: atom card_info pointer
606 * @reg: PLL register offset
607 * @val: value to write to the pll register
608 *
609 * Provides a PLL register accessor for the atom interpreter (r4xx+).
610 */
611static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
612{
613 struct radeon_device *rdev = info->dev->dev_private;
614
615 rdev->pll_wreg(rdev, reg, val);
616}
617
618/**
619 * cail_mc_read - read MC (Memory Controller) register
620 *
621 * @info: atom card_info pointer
622 * @reg: MC register offset
623 *
624 * Provides an MC register accessor for the atom interpreter (r4xx+).
625 * Returns the value of the MC register.
626 */
627static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
628{
629 struct radeon_device *rdev = info->dev->dev_private;
630 uint32_t r;
631
632 r = rdev->mc_rreg(rdev, reg);
633 return r;
634}
635
636/**
637 * cail_mc_write - write MC (Memory Controller) register
638 *
639 * @info: atom card_info pointer
640 * @reg: MC register offset
641 * @val: value to write to the pll register
642 *
643 * Provides a MC register accessor for the atom interpreter (r4xx+).
644 */
645static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
646{
647 struct radeon_device *rdev = info->dev->dev_private;
648
649 rdev->mc_wreg(rdev, reg, val);
650}
651
652/**
653 * cail_reg_write - write MMIO register
654 *
655 * @info: atom card_info pointer
656 * @reg: MMIO register offset
657 * @val: value to write to the pll register
658 *
659 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
660 */
661static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
662{
663 struct radeon_device *rdev = info->dev->dev_private;
664
665 WREG32(reg*4, val);
666}
667
668/**
669 * cail_reg_read - read MMIO register
670 *
671 * @info: atom card_info pointer
672 * @reg: MMIO register offset
673 *
674 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
675 * Returns the value of the MMIO register.
676 */
677static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
678{
679 struct radeon_device *rdev = info->dev->dev_private;
680 uint32_t r;
681
682 r = RREG32(reg*4);
683 return r;
684}
685
686/**
687 * cail_ioreg_write - write IO register
688 *
689 * @info: atom card_info pointer
690 * @reg: IO register offset
691 * @val: value to write to the pll register
692 *
693 * Provides a IO register accessor for the atom interpreter (r4xx+).
694 */
695static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
696{
697 struct radeon_device *rdev = info->dev->dev_private;
698
699 WREG32_IO(reg*4, val);
700}
701
702/**
703 * cail_ioreg_read - read IO register
704 *
705 * @info: atom card_info pointer
706 * @reg: IO register offset
707 *
708 * Provides an IO register accessor for the atom interpreter (r4xx+).
709 * Returns the value of the IO register.
710 */
711static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
712{
713 struct radeon_device *rdev = info->dev->dev_private;
714 uint32_t r;
715
716 r = RREG32_IO(reg*4);
717 return r;
718}
719
720/**
721 * radeon_atombios_init - init the driver info and callbacks for atombios
722 *
723 * @rdev: radeon_device pointer
724 *
725 * Initializes the driver info and register access callbacks for the
726 * ATOM interpreter (r4xx+).
727 * Returns 0 on success, -ENOMEM on failure.
728 * Called at driver startup.
729 */
730int radeon_atombios_init(struct radeon_device *rdev)
731{
732 struct card_info *atom_card_info =
733 malloc(sizeof(struct card_info),
734 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
735
736 if (!atom_card_info)
737 return -ENOMEM;
738
739 rdev->mode_info.atom_card_info = atom_card_info;
740 atom_card_info->dev = rdev->ddev;
741 atom_card_info->reg_read = cail_reg_read;
742 atom_card_info->reg_write = cail_reg_write;
743 /* needed for iio ops */
744 if (rdev->rio_mem) {
745 atom_card_info->ioreg_read = cail_ioreg_read;
746 atom_card_info->ioreg_write = cail_ioreg_write;
747 } else {
748 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
749 atom_card_info->ioreg_read = cail_reg_read;
750 atom_card_info->ioreg_write = cail_reg_write;
751 }
752 atom_card_info->mc_read = cail_mc_read;
753 atom_card_info->mc_write = cail_mc_write;
754 atom_card_info->pll_read = cail_pll_read;
755 atom_card_info->pll_write = cail_pll_write;
756
757 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
758 sx_init(&rdev->mode_info.atom_context->mutex,
759 "drm__radeon_device__mode_info__atom_context__mutex");
760 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
761 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
762 return 0;
763}
764
765/**
766 * radeon_atombios_fini - free the driver info and callbacks for atombios
767 *
768 * @rdev: radeon_device pointer
769 *
770 * Frees the driver info and register access callbacks for the ATOM
771 * interpreter (r4xx+).
772 * Called at driver shutdown.
773 */
774void radeon_atombios_fini(struct radeon_device *rdev)
775{
776 if (rdev->mode_info.atom_context) {
777 free(rdev->mode_info.atom_context->scratch, DRM_MEM_DRIVER);
778 atom_destroy(rdev->mode_info.atom_context);
779 }
780 free(rdev->mode_info.atom_card_info, DRM_MEM_DRIVER);
781}
782
783/* COMBIOS */
784/*
785 * COMBIOS is the bios format prior to ATOM. It provides
786 * command tables similar to ATOM, but doesn't have a unified
787 * parser. See radeon_combios.c
788 */
789
790/**
791 * radeon_combios_init - init the driver info for combios
792 *
793 * @rdev: radeon_device pointer
794 *
795 * Initializes the driver info for combios (r1xx-r3xx).
796 * Returns 0 on success.
797 * Called at driver startup.
798 */
799int radeon_combios_init(struct radeon_device *rdev)
800{
801 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
802 return 0;
803}
804
805/**
806 * radeon_combios_fini - free the driver info for combios
807 *
808 * @rdev: radeon_device pointer
809 *
810 * Frees the driver info for combios (r1xx-r3xx).
811 * Called at driver shutdown.
812 */
813void radeon_combios_fini(struct radeon_device *rdev)
814{
815}
816
817#ifdef FREEBSD_WIP
818/* if we get transitioned to only one device, take VGA back */
819/**
820 * radeon_vga_set_decode - enable/disable vga decode
821 *
822 * @cookie: radeon_device pointer
823 * @state: enable/disable vga decode
824 *
825 * Enable/disable vga decode (all asics).
826 * Returns VGA resource flags.
827 */
828static unsigned int radeon_vga_set_decode(void *cookie, bool state)
829{
830 struct radeon_device *rdev = cookie;
831 radeon_vga_set_state(rdev, state);
832 if (state)
833 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
834 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
835 else
836 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
837}
838#endif /* FREEBSD_WIP */
839
840/**
841 * radeon_check_pot_argument - check that argument is a power of two
842 *
843 * @arg: value to check
844 *
845 * Validates that a certain argument is a power of two (all asics).
846 * Returns true if argument is valid.
847 */
848static bool radeon_check_pot_argument(int arg)
849{
850 return (arg & (arg - 1)) == 0;
851}
852
853/**
854 * radeon_check_arguments - validate module params
855 *
856 * @rdev: radeon_device pointer
857 *
858 * Validates certain module parameters and updates
859 * the associated values used by the driver (all asics).
860 */
861static void radeon_check_arguments(struct radeon_device *rdev)
862{
863 /* vramlimit must be a power of two */
864 if (!radeon_check_pot_argument(radeon_vram_limit)) {
865 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
866 radeon_vram_limit);
867 radeon_vram_limit = 0;
868 }
869
870 /* gtt size must be power of two and greater or equal to 32M */
871 if (radeon_gart_size < 32) {
872 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
873 radeon_gart_size);
874 radeon_gart_size = 512;
875
876 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
877 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
878 radeon_gart_size);
879 radeon_gart_size = 512;
880 }
881 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
882
883 /* AGP mode can only be -1, 1, 2, 4, 8 */
884 switch (radeon_agpmode) {
885 case -1:
886 case 0:
887 case 1:
888 case 2:
889 case 4:
890 case 8:
891 break;
892 default:
893 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
894 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
895 radeon_agpmode = 0;
896 break;
897 }
898}
899
900/**
901 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
902 * needed for waking up.
903 *
904 * @pdev: pci dev pointer
905 */
906#ifdef FREEBSD_WIP
907static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
908{
909
910 /* 6600m in a macbook pro */
911 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
912 pdev->subsystem_device == 0x00e2) {
913 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
914 return true;
915 }
916
917 return false;
918}
919#endif /* FREEBSD_WIP */
920
921/**
922 * radeon_switcheroo_set_state - set switcheroo state
923 *
924 * @pdev: pci dev pointer
925 * @state: vga switcheroo state
926 *
927 * Callback for the switcheroo driver. Suspends or resumes the
928 * the asics before or after it is powered up using ACPI methods.
929 */
930#ifdef FREEBSD_WIP
931static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
932{
933 struct drm_device *dev = pci_get_drvdata(pdev);
934 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
935 if (state == VGA_SWITCHEROO_ON) {
936 unsigned d3_delay = dev->pdev->d3_delay;
937
938 printk(KERN_INFO "radeon: switched on\n");
939 /* don't suspend or resume card normally */
940 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
941
942 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
943 dev->pdev->d3_delay = 20;
944
945 radeon_resume_kms(dev);
946
947 dev->pdev->d3_delay = d3_delay;
948
949 dev->switch_power_state = DRM_SWITCH_POWER_ON;
950 drm_kms_helper_poll_enable(dev);
951 } else {
952 printk(KERN_INFO "radeon: switched off\n");
953 drm_kms_helper_poll_disable(dev);
954 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
955 radeon_suspend_kms(dev, pmm);
956 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
957 }
958}
959#endif /* FREEBSD_WIP */
960
961/**
962 * radeon_switcheroo_can_switch - see if switcheroo state can change
963 *
964 * @pdev: pci dev pointer
965 *
966 * Callback for the switcheroo driver. Check of the switcheroo
967 * state can be changed.
968 * Returns true if the state can be changed, false if not.
969 */
970#ifdef FREEBSD_WIP
971static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
972{
973 struct drm_device *dev = pci_get_drvdata(pdev);
974 bool can_switch;
975
976 spin_lock(&dev->count_lock);
977 can_switch = (dev->open_count == 0);
978 spin_unlock(&dev->count_lock);
979 return can_switch;
980}
981
982static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
983 .set_gpu_state = radeon_switcheroo_set_state,
984 .reprobe = NULL,
985 .can_switch = radeon_switcheroo_can_switch,
986};
987#endif /* FREEBSD_WIP */
988
989/**
990 * radeon_device_init - initialize the driver
991 *
992 * @rdev: radeon_device pointer
993 * @pdev: drm dev pointer
994 * @flags: driver flags
995 *
996 * Initializes the driver info and hw (all asics).
997 * Returns 0 for success or an error on failure.
998 * Called at driver startup.
999 */
1000int radeon_device_init(struct radeon_device *rdev,
1001 struct drm_device *ddev,
1002 uint32_t flags)
1003{
1004 int r, i;
1005 int dma_bits;
1006
1007 rdev->shutdown = false;
1008 rdev->dev = ddev->dev;
1009 rdev->ddev = ddev;
1010 rdev->flags = flags;
1011 rdev->family = flags & RADEON_FAMILY_MASK;
1012 rdev->is_atom_bios = false;
1013 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1014 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1015 rdev->accel_working = false;
1016 rdev->fictitious_range_registered = false;
1017 rdev->fictitious_agp_range_registered = false;
1018 /* set up ring ids */
1019 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1020 rdev->ring[i].idx = i;
1021 }
1022
1023 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1024 radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device,
1025 ddev->pci_subvendor, ddev->pci_subdevice);
1026
1027 /* mutex initialization are all done here so we
1028 * can recall function without having locking issues */
1029 sx_init(&rdev->ring_lock, "drm__radeon_device__ring_lock");
1030 sx_init(&rdev->dc_hw_i2c_mutex, "drm__radeon_device__dc_hw_i2c_mutex");
1031 atomic_set(&rdev->ih.lock, 0);
1032 sx_init(&rdev->gem.mutex, "drm__radeon_device__gem__mutex");
1033 sx_init(&rdev->pm.mutex, "drm__radeon_device__pm__mutex");
1034 sx_init(&rdev->gpu_clock_mutex, "drm__radeon_device__gpu_clock_mutex");
1035 sx_init(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock");
1036 sx_init(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock");
1037 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue);
1038 r = radeon_gem_init(rdev);
1039 if (r)
1040 return r;
1041 /* initialize vm here */
1042 sx_init(&rdev->vm_manager.lock, "drm__radeon_device__vm_manager__lock");
1043 /* Adjust VM size here.
1044 * Currently set to 4GB ((1 << 20) 4k pages).
1045 * Max GPUVM size for cayman and SI is 40 bits.
1046 */
1047 rdev->vm_manager.max_pfn = 1 << 20;
1048 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1049
1050 /* Set asic functions */
1051 r = radeon_asic_init(rdev);
1052 if (r)
1053 return r;
1054 radeon_check_arguments(rdev);
1055
1056 /* all of the newer IGP chips have an internal gart
1057 * However some rs4xx report as AGP, so remove that here.
1058 */
1059 if ((rdev->family >= CHIP_RS400) &&
1060 (rdev->flags & RADEON_IS_IGP)) {
1061 rdev->flags &= ~RADEON_IS_AGP;
1062 }
1063
1064 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1065 radeon_agp_disable(rdev);
1066 }
1067
1068 /* set DMA mask + need_dma32 flags.
1069 * PCIE - can handle 40-bits.
1070 * IGP - can handle 40-bits
1071 * AGP - generally dma32 is safest
1072 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1073 */
1074 rdev->need_dma32 = false;
1075 if (rdev->flags & RADEON_IS_AGP)
1076 rdev->need_dma32 = true;
1077 if ((rdev->flags & RADEON_IS_PCI) &&
1078 (rdev->family <= CHIP_RS740))
1079 rdev->need_dma32 = true;
1080
1081 dma_bits = rdev->need_dma32 ? 32 : 40;
1082#ifdef FREEBSD_WIP
1083 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1084 if (r) {
1085 rdev->need_dma32 = true;
1086 dma_bits = 32;
1087 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1088 }
1089 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1090 if (r) {
1091 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1092 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1093 }
1094#endif /* FREEBSD_WIP */
1095
1096 /* Registers mapping */
1097 /* TODO: block userspace mapping of io register */
1098 DRM_SPININIT(&rdev->mmio_idx_lock, "drm__radeon_device__mmio_idx_lock");
1099 rdev->rmmio_rid = PCIR_BAR(2);
1100 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY,
1101 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE);
1102 if (rdev->rmmio == NULL) {
1103 return -ENOMEM;
1104 }
1105 rdev->rmmio_base = rman_get_start(rdev->rmmio);
1106 rdev->rmmio_size = rman_get_size(rdev->rmmio);
1107 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1108 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1109
1110 /* io port mapping */
1111 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) {
1112 uint32_t data;
1113
1114 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4);
1115 if (PCI_BAR_IO(data)) {
1116 rdev->rio_rid = PCIR_BAR(i);
1117 rdev->rio_mem = bus_alloc_resource_any(rdev->dev,
1118 SYS_RES_IOPORT, &rdev->rio_rid,
1119 RF_ACTIVE | RF_SHAREABLE);
1120 break;
1121 }
1122 }
1123 if (rdev->rio_mem == NULL)
1124 DRM_ERROR("Unable to find PCI I/O BAR\n");
1125
1126 rdev->tq = taskqueue_create("radeonkms", M_WAITOK,
1127 taskqueue_thread_enqueue, &rdev->tq);
1128 taskqueue_start_threads(&rdev->tq, 1, PWAIT, "radeon taskq");
1129
1130#ifdef FREEBSD_WIP
1131 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1132 /* this will fail for cards that aren't VGA class devices, just
1133 * ignore it */
1134 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1135 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1136#endif /* FREEBSD_WIP */
1137
1138 r = radeon_init(rdev);
1139 if (r)
1140 return r;
1141
1142 r = radeon_ib_ring_tests(rdev);
1143 if (r)
1144 DRM_ERROR("ib ring test failed (%d).\n", r);
1145
1146 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1147 /* Acceleration not working on AGP card try again
1148 * with fallback to PCI or PCIE GART
1149 */
1150 radeon_asic_reset(rdev);
1151 radeon_fini(rdev);
1152 radeon_agp_disable(rdev);
1153 r = radeon_init(rdev);
1154 if (r)
1155 return r;
1156 }
1157
1158 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1159 __func__, (uintmax_t)rdev->mc.aper_base,
1160 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size);
1161 r = vm_phys_fictitious_reg_range(
1162 rdev->mc.aper_base,
1163 rdev->mc.aper_base + rdev->mc.visible_vram_size,
1164 VM_MEMATTR_WRITE_COMBINING);
1165 if (r != 0) {
1166 DRM_ERROR("Failed to register fictitious range "
1167 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base,
1168 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r);
1169 return (-r);
1170 }
1171 rdev->fictitious_range_registered = true;
1172#if __OS_HAS_AGP
1173 if (rdev->flags & RADEON_IS_AGP) {
1174 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1175 __func__, (uintmax_t)rdev->mc.agp_base,
1176 (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size);
1177 r = vm_phys_fictitious_reg_range(
1178 rdev->mc.agp_base,
1179 rdev->mc.agp_base + rdev->mc.gtt_size,
1180 VM_MEMATTR_WRITE_COMBINING);
1181 if (r != 0) {
1182 DRM_ERROR("Failed to register fictitious range "
1183 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.agp_base,
1184 (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size, r);
1185 return (-r);
1186 }
1187 rdev->fictitious_agp_range_registered = true;
1188 }
1189#endif
1190
1191 if ((radeon_testing & 1)) {
1192 radeon_test_moves(rdev);
1193 }
1194 if ((radeon_testing & 2)) {
1195 radeon_test_syncing(rdev);
1196 }
1197 if (radeon_benchmarking) {
1198 radeon_benchmark(rdev, radeon_benchmarking);
1199 }
1200 return 0;
1201}
1202
1203#ifdef FREEBSD_WIP
1204static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1205#endif /* FREEBSD_WIP */
1206
1207/**
1208 * radeon_device_fini - tear down the driver
1209 *
1210 * @rdev: radeon_device pointer
1211 *
1212 * Tear down the driver info (all asics).
1213 * Called at driver shutdown.
1214 */
1215void radeon_device_fini(struct radeon_device *rdev)
1216{
1217 DRM_INFO("radeon: finishing device.\n");
1218 rdev->shutdown = true;
1219 /* evict vram memory */
1220 radeon_bo_evict_vram(rdev);
1221
1222 if (rdev->fictitious_range_registered) {
1223 vm_phys_fictitious_unreg_range(
1224 rdev->mc.aper_base,
1225 rdev->mc.aper_base + rdev->mc.visible_vram_size);
1226 }
1227#if __OS_HAS_AGP
1228 if (rdev->fictitious_agp_range_registered) {
1229 vm_phys_fictitious_unreg_range(
1230 rdev->mc.agp_base,
1231 rdev->mc.agp_base + rdev->mc.gtt_size);
1232 }
1233#endif
1234
1235 radeon_fini(rdev);
1236#ifdef FREEBSD_WIP
1237 vga_switcheroo_unregister_client(rdev->pdev);
1238 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1239#endif /* FREEBSD_WIP */
1240
1241 if (rdev->tq != NULL) {
1242 taskqueue_free(rdev->tq);
1243 rdev->tq = NULL;
1244 }
1245
1246 if (rdev->rio_mem)
1247 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid,
1248 rdev->rio_mem);
1249 rdev->rio_mem = NULL;
1250 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid,
1251 rdev->rmmio);
1252 rdev->rmmio = NULL;
1253#ifdef FREEBSD_WIP
1254 radeon_debugfs_remove_files(rdev);
1255#endif /* FREEBSD_WIP */
1256}
1257
1258
1259/*
1260 * Suspend & resume.
1261 */
1262/**
1263 * radeon_suspend_kms - initiate device suspend
1264 *
1265 * @pdev: drm dev pointer
1266 * @state: suspend state
1267 *
1268 * Puts the hw in the suspend state (all asics).
1269 * Returns 0 for success or an error on failure.
1270 * Called at driver suspend.
1271 */
1272int radeon_suspend_kms(struct drm_device *dev)
1273{
1274 struct radeon_device *rdev;
1275 struct drm_crtc *crtc;
1276 struct drm_connector *connector;
1277 int i, r;
1278 bool force_completion = false;
1279
1280 if (dev == NULL || dev->dev_private == NULL) {
1281 return -ENODEV;
1282 }
1283#ifdef FREEBSD_WIP
1284 if (state.event == PM_EVENT_PRETHAW) {
1285 return 0;
1286 }
1287#endif /* FREEBSD_WIP */
1288 rdev = dev->dev_private;
1289
1290 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1291 return 0;
1292
1293 drm_kms_helper_poll_disable(dev);
1294
1295 /* turn off display hw */
1296 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1297 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1298 }
1299
1300 /* unpin the front buffers */
1301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1302 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1303 struct radeon_bo *robj;
1304
1305 if (rfb == NULL || rfb->obj == NULL) {
1306 continue;
1307 }
1308 robj = gem_to_radeon_bo(rfb->obj);
1309 /* don't unpin kernel fb objects */
1310 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1311 r = radeon_bo_reserve(robj, false);
1312 if (r == 0) {
1313 radeon_bo_unpin(robj);
1314 radeon_bo_unreserve(robj);
1315 }
1316 }
1317 }
1318 /* evict vram memory */
1319 radeon_bo_evict_vram(rdev);
1320
1321 sx_xlock(&rdev->ring_lock);
1322 /* wait for gpu to finish processing current batch */
1323 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1324 r = radeon_fence_wait_empty_locked(rdev, i);
1325 if (r) {
1326 /* delay GPU reset to resume */
1327 force_completion = true;
1328 }
1329 }
1330 if (force_completion) {
1331 radeon_fence_driver_force_completion(rdev);
1332 }
1333 sx_xunlock(&rdev->ring_lock);
1334
1335 radeon_save_bios_scratch_regs(rdev);
1336
1337 radeon_pm_suspend(rdev);
1338 radeon_suspend(rdev);
1339 radeon_hpd_fini(rdev);
1340 /* evict remaining vram memory */
1341 radeon_bo_evict_vram(rdev);
1342
1343 radeon_agp_suspend(rdev);
1344
1345#ifdef FREEBSD_WIP
1346 if (state.event == PM_EVENT_SUSPEND) {
1347 /* Shut down the device */
1348 pci_disable_device(dev->pdev);
1349 }
1350 console_lock();
1351#endif /* FREEBSD_WIP */
1352 radeon_fbdev_set_suspend(rdev, 1);
1353#ifdef FREEBSD_WIP
1354 console_unlock();
1355#endif /* FREEBSD_WIP */
1356 return 0;
1357}
1358
1359/**
1360 * radeon_resume_kms - initiate device resume
1361 *
1362 * @pdev: drm dev pointer
1363 *
1364 * Bring the hw back to operating state (all asics).
1365 * Returns 0 for success or an error on failure.
1366 * Called at driver resume.
1367 */
1368int radeon_resume_kms(struct drm_device *dev)
1369{
1370 struct drm_connector *connector;
1371 struct radeon_device *rdev = dev->dev_private;
1372 int r;
1373
1374 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1375 return 0;
1376
1377#ifdef FREEBSD_WIP
1378 console_lock();
1379 if (pci_enable_device(dev->pdev)) {
1380 console_unlock();
1381 return -1;
1382 }
1383#endif /* FREEBSD_WIP */
1384 /* resume AGP if in use */
1385 radeon_agp_resume(rdev);
1386 radeon_resume(rdev);
1387
1388 r = radeon_ib_ring_tests(rdev);
1389 if (r)
1390 DRM_ERROR("ib ring test failed (%d).\n", r);
1391
1392 radeon_pm_resume(rdev);
1393 radeon_restore_bios_scratch_regs(rdev);
1394
1395 radeon_fbdev_set_suspend(rdev, 0);
1396#ifdef FREEBSD_WIP
1397 console_unlock();
1398#endif /* FREEBSD_WIP */
1399
1400 /* init dig PHYs, disp eng pll */
1401 if (rdev->is_atom_bios) {
1402 radeon_atom_encoder_init(rdev);
1403 radeon_atom_disp_eng_pll_init(rdev);
1404 /* turn on the BL */
1405 if (rdev->mode_info.bl_encoder) {
1406 u8 bl_level = radeon_get_backlight_level(rdev,
1407 rdev->mode_info.bl_encoder);
1408 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1409 bl_level);
1410 }
1411 }
1412 /* reset hpd state */
1413 radeon_hpd_init(rdev);
1414 /* blat the mode back in */
1415 drm_helper_resume_force_mode(dev);
1416 /* turn on display hw */
1417 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1418 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1419 }
1420
1421 drm_kms_helper_poll_enable(dev);
1422 return 0;
1423}
1424
1425/**
1426 * radeon_gpu_reset - reset the asic
1427 *
1428 * @rdev: radeon device pointer
1429 *
1430 * Attempt the reset the GPU if it has hung (all asics).
1431 * Returns 0 for success or an error on failure.
1432 */
1433int radeon_gpu_reset(struct radeon_device *rdev)
1434{
1435 unsigned ring_sizes[RADEON_NUM_RINGS];
1436 uint32_t *ring_data[RADEON_NUM_RINGS];
1437
1438 bool saved = false;
1439
1440 int i, r;
1441 int resched;
1442
1443 sx_xlock(&rdev->exclusive_lock);
1444 radeon_save_bios_scratch_regs(rdev);
1445 /* block TTM */
1446 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1447 radeon_suspend(rdev);
1448
1449 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1450 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1451 &ring_data[i]);
1452 if (ring_sizes[i]) {
1453 saved = true;
1454 dev_info(rdev->dev, "Saved %d dwords of commands "
1455 "on ring %d.\n", ring_sizes[i], i);
1456 }
1457 }
1458
1459retry:
1460 r = radeon_asic_reset(rdev);
1461 if (!r) {
1462 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1463 radeon_resume(rdev);
1464 }
1465
1466 radeon_restore_bios_scratch_regs(rdev);
1467
1468 if (!r) {
1469 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1470 radeon_ring_restore(rdev, &rdev->ring[i],
1471 ring_sizes[i], ring_data[i]);
1472 ring_sizes[i] = 0;
1473 ring_data[i] = NULL;
1474 }
1475
1476 r = radeon_ib_ring_tests(rdev);
1477 if (r) {
1478 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1479 if (saved) {
1480 saved = false;
1481 radeon_suspend(rdev);
1482 goto retry;
1483 }
1484 }
1485 } else {
1486 radeon_fence_driver_force_completion(rdev);
1487 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1488 free(ring_data[i], DRM_MEM_DRIVER);
1489 }
1490 }
1491
1492 drm_helper_resume_force_mode(rdev->ddev);
1493
1494 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1495 if (r) {
1496 /* bad news, how to tell it to userspace ? */
1497 dev_info(rdev->dev, "GPU reset failed\n");
1498 }
1499
1500 sx_xunlock(&rdev->exclusive_lock);
1501 return r;
1502}
1503
1504
1505/*
1506 * Debugfs
1507 */
1508#ifdef FREEBSD_WIP
1509int radeon_debugfs_add_files(struct radeon_device *rdev,
1510 struct drm_info_list *files,
1511 unsigned nfiles)
1512{
1513 unsigned i;
1514
1515 for (i = 0; i < rdev->debugfs_count; i++) {
1516 if (rdev->debugfs[i].files == files) {
1517 /* Already registered */
1518 return 0;
1519 }
1520 }
1521
1522 i = rdev->debugfs_count + 1;
1523 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1524 DRM_ERROR("Reached maximum number of debugfs components.\n");
1525 DRM_ERROR("Report so we increase "
1526 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1527 return -EINVAL;
1528 }
1529 rdev->debugfs[rdev->debugfs_count].files = files;
1530 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1531 rdev->debugfs_count = i;
1532#if defined(CONFIG_DEBUG_FS)
1533 drm_debugfs_create_files(files, nfiles,
1534 rdev->ddev->control->debugfs_root,
1535 rdev->ddev->control);
1536 drm_debugfs_create_files(files, nfiles,
1537 rdev->ddev->primary->debugfs_root,
1538 rdev->ddev->primary);
1539#endif
1540 return 0;
1541}
1542
1543static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1544{
1545#if defined(CONFIG_DEBUG_FS)
1546 unsigned i;
1547
1548 for (i = 0; i < rdev->debugfs_count; i++) {
1549 drm_debugfs_remove_files(rdev->debugfs[i].files,
1550 rdev->debugfs[i].num_files,
1551 rdev->ddev->control);
1552 drm_debugfs_remove_files(rdev->debugfs[i].files,
1553 rdev->debugfs[i].num_files,
1554 rdev->ddev->primary);
1555 }
1556#endif
1557}
1558
1559#if defined(CONFIG_DEBUG_FS)
1560int radeon_debugfs_init(struct drm_minor *minor)
1561{
1562 return 0;
1563}
1564
1565void radeon_debugfs_cleanup(struct drm_minor *minor)
1566{
1567}
1568#endif /* FREEBSD_WIP */
1569#endif
| 195 * in memory with the status of certain GPU events (fences, ring pointers,
196 * etc.).
197 */
198
199/**
200 * radeon_wb_disable - Disable Writeback
201 *
202 * @rdev: radeon_device pointer
203 *
204 * Disables Writeback (all asics). Used for suspend.
205 */
206void radeon_wb_disable(struct radeon_device *rdev)
207{
208 int r;
209
210 if (rdev->wb.wb_obj) {
211 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
212 if (unlikely(r != 0))
213 return;
214 radeon_bo_kunmap(rdev->wb.wb_obj);
215 radeon_bo_unpin(rdev->wb.wb_obj);
216 radeon_bo_unreserve(rdev->wb.wb_obj);
217 }
218 rdev->wb.enabled = false;
219}
220
221/**
222 * radeon_wb_fini - Disable Writeback and free memory
223 *
224 * @rdev: radeon_device pointer
225 *
226 * Disables Writeback and frees the Writeback memory (all asics).
227 * Used at driver shutdown.
228 */
229void radeon_wb_fini(struct radeon_device *rdev)
230{
231 radeon_wb_disable(rdev);
232 if (rdev->wb.wb_obj) {
233 radeon_bo_unref(&rdev->wb.wb_obj);
234 rdev->wb.wb = NULL;
235 rdev->wb.wb_obj = NULL;
236 }
237}
238
239/**
240 * radeon_wb_init- Init Writeback driver info and allocate memory
241 *
242 * @rdev: radeon_device pointer
243 *
244 * Disables Writeback and frees the Writeback memory (all asics).
245 * Used at driver startup.
246 * Returns 0 on success or an -error on failure.
247 */
248int radeon_wb_init(struct radeon_device *rdev)
249{
250 int r;
251 void *wb_ptr; /* FreeBSD: to please GCC 4.2. */
252
253 if (rdev->wb.wb_obj == NULL) {
254 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
255 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
256 if (r) {
257 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
258 return r;
259 }
260 }
261 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
262 if (unlikely(r != 0)) {
263 radeon_wb_fini(rdev);
264 return r;
265 }
266 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
267 &rdev->wb.gpu_addr);
268 if (r) {
269 radeon_bo_unreserve(rdev->wb.wb_obj);
270 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
271 radeon_wb_fini(rdev);
272 return r;
273 }
274 wb_ptr = &rdev->wb.wb;
275 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr);
276 radeon_bo_unreserve(rdev->wb.wb_obj);
277 if (r) {
278 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
279 radeon_wb_fini(rdev);
280 return r;
281 }
282
283 /* clear wb memory */
284 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE);
285 /* disable event_write fences */
286 rdev->wb.use_event = false;
287 /* disabled via module param */
288 if (radeon_no_wb == 1) {
289 rdev->wb.enabled = false;
290 } else {
291 if (rdev->flags & RADEON_IS_AGP) {
292 /* often unreliable on AGP */
293 rdev->wb.enabled = false;
294 } else if (rdev->family < CHIP_R300) {
295 /* often unreliable on pre-r300 */
296 rdev->wb.enabled = false;
297 } else {
298 rdev->wb.enabled = true;
299 /* event_write fences are only available on r600+ */
300 if (rdev->family >= CHIP_R600) {
301 rdev->wb.use_event = true;
302 }
303 }
304 }
305 /* always use writeback/events on NI, APUs */
306 if (rdev->family >= CHIP_PALM) {
307 rdev->wb.enabled = true;
308 rdev->wb.use_event = true;
309 }
310
311 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
312
313 return 0;
314}
315
316/**
317 * radeon_vram_location - try to find VRAM location
318 * @rdev: radeon device structure holding all necessary informations
319 * @mc: memory controller structure holding memory informations
320 * @base: base address at which to put VRAM
321 *
322 * Function will place try to place VRAM at base address provided
323 * as parameter (which is so far either PCI aperture address or
324 * for IGP TOM base address).
325 *
326 * If there is not enough space to fit the unvisible VRAM in the 32bits
327 * address space then we limit the VRAM size to the aperture.
328 *
329 * If we are using AGP and if the AGP aperture doesn't allow us to have
330 * room for all the VRAM than we restrict the VRAM to the PCI aperture
331 * size and print a warning.
332 *
333 * This function will never fails, worst case are limiting VRAM.
334 *
335 * Note: GTT start, end, size should be initialized before calling this
336 * function on AGP platform.
337 *
338 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
339 * this shouldn't be a problem as we are using the PCI aperture as a reference.
340 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
341 * not IGP.
342 *
343 * Note: we use mc_vram_size as on some board we need to program the mc to
344 * cover the whole aperture even if VRAM size is inferior to aperture size
345 * Novell bug 204882 + along with lots of ubuntu ones
346 *
347 * Note: when limiting vram it's safe to overwritte real_vram_size because
348 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
349 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
350 * ones)
351 *
352 * Note: IGP TOM addr should be the same as the aperture addr, we don't
353 * explicitly check for that thought.
354 *
355 * FIXME: when reducing VRAM size align new size on power of 2.
356 */
357void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
358{
359 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
360
361 mc->vram_start = base;
362 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
363 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
364 mc->real_vram_size = mc->aper_size;
365 mc->mc_vram_size = mc->aper_size;
366 }
367 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
368 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
369 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
370 mc->real_vram_size = mc->aper_size;
371 mc->mc_vram_size = mc->aper_size;
372 }
373 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
374 if (limit && limit < mc->real_vram_size)
375 mc->real_vram_size = limit;
376 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
377 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
378 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
379}
380
381/**
382 * radeon_gtt_location - try to find GTT location
383 * @rdev: radeon device structure holding all necessary informations
384 * @mc: memory controller structure holding memory informations
385 *
386 * Function will place try to place GTT before or after VRAM.
387 *
388 * If GTT size is bigger than space left then we ajust GTT size.
389 * Thus function will never fails.
390 *
391 * FIXME: when reducing GTT size align new size on power of 2.
392 */
393void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
394{
395 u64 size_af, size_bf;
396
397 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
398 size_bf = mc->vram_start & ~mc->gtt_base_align;
399 if (size_bf > size_af) {
400 if (mc->gtt_size > size_bf) {
401 dev_warn(rdev->dev, "limiting GTT\n");
402 mc->gtt_size = size_bf;
403 }
404 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
405 } else {
406 if (mc->gtt_size > size_af) {
407 dev_warn(rdev->dev, "limiting GTT\n");
408 mc->gtt_size = size_af;
409 }
410 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
411 }
412 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
413 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
414 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end);
415}
416
417/*
418 * GPU helpers function.
419 */
420/**
421 * radeon_card_posted - check if the hw has already been initialized
422 *
423 * @rdev: radeon_device pointer
424 *
425 * Check if the asic has been initialized (all asics).
426 * Used at driver startup.
427 * Returns true if initialized or false if not.
428 */
429bool radeon_card_posted(struct radeon_device *rdev)
430{
431 uint32_t reg;
432
433#ifdef FREEBSD_WIP
434 if (efi_enabled(EFI_BOOT) &&
435 rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE)
436 return false;
437#endif /* FREEBSD_WIP */
438
439 /* first check CRTCs */
440 if (ASIC_IS_DCE41(rdev)) {
441 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
442 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
443 if (reg & EVERGREEN_CRTC_MASTER_EN)
444 return true;
445 } else if (ASIC_IS_DCE4(rdev)) {
446 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
451 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
452 if (reg & EVERGREEN_CRTC_MASTER_EN)
453 return true;
454 } else if (ASIC_IS_AVIVO(rdev)) {
455 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
456 RREG32(AVIVO_D2CRTC_CONTROL);
457 if (reg & AVIVO_CRTC_EN) {
458 return true;
459 }
460 } else {
461 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
462 RREG32(RADEON_CRTC2_GEN_CNTL);
463 if (reg & RADEON_CRTC_EN) {
464 return true;
465 }
466 }
467
468 /* then check MEM_SIZE, in case the crtcs are off */
469 if (rdev->family >= CHIP_R600)
470 reg = RREG32(R600_CONFIG_MEMSIZE);
471 else
472 reg = RREG32(RADEON_CONFIG_MEMSIZE);
473
474 if (reg)
475 return true;
476
477 return false;
478
479}
480
481/**
482 * radeon_update_bandwidth_info - update display bandwidth params
483 *
484 * @rdev: radeon_device pointer
485 *
486 * Used when sclk/mclk are switched or display modes are set.
487 * params are used to calculate display watermarks (all asics)
488 */
489void radeon_update_bandwidth_info(struct radeon_device *rdev)
490{
491 fixed20_12 a;
492 u32 sclk = rdev->pm.current_sclk;
493 u32 mclk = rdev->pm.current_mclk;
494
495 /* sclk/mclk in Mhz */
496 a.full = dfixed_const(100);
497 rdev->pm.sclk.full = dfixed_const(sclk);
498 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
499 rdev->pm.mclk.full = dfixed_const(mclk);
500 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
501
502 if (rdev->flags & RADEON_IS_IGP) {
503 a.full = dfixed_const(16);
504 /* core_bandwidth = sclk(Mhz) * 16 */
505 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
506 }
507}
508
509/**
510 * radeon_boot_test_post_card - check and possibly initialize the hw
511 *
512 * @rdev: radeon_device pointer
513 *
514 * Check if the asic is initialized and if not, attempt to initialize
515 * it (all asics).
516 * Returns true if initialized or false if not.
517 */
518bool radeon_boot_test_post_card(struct radeon_device *rdev)
519{
520 if (radeon_card_posted(rdev))
521 return true;
522
523 if (rdev->bios) {
524 DRM_INFO("GPU not posted. posting now...\n");
525 if (rdev->is_atom_bios)
526 atom_asic_init(rdev->mode_info.atom_context);
527 else
528 radeon_combios_asic_init(rdev->ddev);
529 return true;
530 } else {
531 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
532 return false;
533 }
534}
535
536/**
537 * radeon_dummy_page_init - init dummy page used by the driver
538 *
539 * @rdev: radeon_device pointer
540 *
541 * Allocate the dummy page used by the driver (all asics).
542 * This dummy page is used by the driver as a filler for gart entries
543 * when pages are taken out of the GART
544 * Returns 0 on success, -ENOMEM on failure.
545 */
546int radeon_dummy_page_init(struct radeon_device *rdev)
547{
548 if (rdev->dummy_page.dmah)
549 return 0;
550 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev,
551 PAGE_SIZE, PAGE_SIZE, BUS_SPACE_MAXADDR_32BIT);
552 if (rdev->dummy_page.dmah == NULL)
553 return -ENOMEM;
554 rdev->dummy_page.addr = rdev->dummy_page.dmah->busaddr;
555 return 0;
556}
557
558/**
559 * radeon_dummy_page_fini - free dummy page used by the driver
560 *
561 * @rdev: radeon_device pointer
562 *
563 * Frees the dummy page used by the driver (all asics).
564 */
565void radeon_dummy_page_fini(struct radeon_device *rdev)
566{
567 if (rdev->dummy_page.dmah == NULL)
568 return;
569 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah);
570 rdev->dummy_page.dmah = NULL;
571 rdev->dummy_page.addr = 0;
572}
573
574
575/* ATOM accessor methods */
576/*
577 * ATOM is an interpreted byte code stored in tables in the vbios. The
578 * driver registers callbacks to access registers and the interpreter
579 * in the driver parses the tables and executes then to program specific
580 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
581 * atombios.h, and atom.c
582 */
583
584/**
585 * cail_pll_read - read PLL register
586 *
587 * @info: atom card_info pointer
588 * @reg: PLL register offset
589 *
590 * Provides a PLL register accessor for the atom interpreter (r4xx+).
591 * Returns the value of the PLL register.
592 */
593static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
594{
595 struct radeon_device *rdev = info->dev->dev_private;
596 uint32_t r;
597
598 r = rdev->pll_rreg(rdev, reg);
599 return r;
600}
601
602/**
603 * cail_pll_write - write PLL register
604 *
605 * @info: atom card_info pointer
606 * @reg: PLL register offset
607 * @val: value to write to the pll register
608 *
609 * Provides a PLL register accessor for the atom interpreter (r4xx+).
610 */
611static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
612{
613 struct radeon_device *rdev = info->dev->dev_private;
614
615 rdev->pll_wreg(rdev, reg, val);
616}
617
618/**
619 * cail_mc_read - read MC (Memory Controller) register
620 *
621 * @info: atom card_info pointer
622 * @reg: MC register offset
623 *
624 * Provides an MC register accessor for the atom interpreter (r4xx+).
625 * Returns the value of the MC register.
626 */
627static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
628{
629 struct radeon_device *rdev = info->dev->dev_private;
630 uint32_t r;
631
632 r = rdev->mc_rreg(rdev, reg);
633 return r;
634}
635
636/**
637 * cail_mc_write - write MC (Memory Controller) register
638 *
639 * @info: atom card_info pointer
640 * @reg: MC register offset
641 * @val: value to write to the pll register
642 *
643 * Provides a MC register accessor for the atom interpreter (r4xx+).
644 */
645static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
646{
647 struct radeon_device *rdev = info->dev->dev_private;
648
649 rdev->mc_wreg(rdev, reg, val);
650}
651
652/**
653 * cail_reg_write - write MMIO register
654 *
655 * @info: atom card_info pointer
656 * @reg: MMIO register offset
657 * @val: value to write to the pll register
658 *
659 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
660 */
661static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
662{
663 struct radeon_device *rdev = info->dev->dev_private;
664
665 WREG32(reg*4, val);
666}
667
668/**
669 * cail_reg_read - read MMIO register
670 *
671 * @info: atom card_info pointer
672 * @reg: MMIO register offset
673 *
674 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
675 * Returns the value of the MMIO register.
676 */
677static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
678{
679 struct radeon_device *rdev = info->dev->dev_private;
680 uint32_t r;
681
682 r = RREG32(reg*4);
683 return r;
684}
685
686/**
687 * cail_ioreg_write - write IO register
688 *
689 * @info: atom card_info pointer
690 * @reg: IO register offset
691 * @val: value to write to the pll register
692 *
693 * Provides a IO register accessor for the atom interpreter (r4xx+).
694 */
695static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
696{
697 struct radeon_device *rdev = info->dev->dev_private;
698
699 WREG32_IO(reg*4, val);
700}
701
702/**
703 * cail_ioreg_read - read IO register
704 *
705 * @info: atom card_info pointer
706 * @reg: IO register offset
707 *
708 * Provides an IO register accessor for the atom interpreter (r4xx+).
709 * Returns the value of the IO register.
710 */
711static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
712{
713 struct radeon_device *rdev = info->dev->dev_private;
714 uint32_t r;
715
716 r = RREG32_IO(reg*4);
717 return r;
718}
719
720/**
721 * radeon_atombios_init - init the driver info and callbacks for atombios
722 *
723 * @rdev: radeon_device pointer
724 *
725 * Initializes the driver info and register access callbacks for the
726 * ATOM interpreter (r4xx+).
727 * Returns 0 on success, -ENOMEM on failure.
728 * Called at driver startup.
729 */
730int radeon_atombios_init(struct radeon_device *rdev)
731{
732 struct card_info *atom_card_info =
733 malloc(sizeof(struct card_info),
734 DRM_MEM_DRIVER, M_NOWAIT | M_ZERO);
735
736 if (!atom_card_info)
737 return -ENOMEM;
738
739 rdev->mode_info.atom_card_info = atom_card_info;
740 atom_card_info->dev = rdev->ddev;
741 atom_card_info->reg_read = cail_reg_read;
742 atom_card_info->reg_write = cail_reg_write;
743 /* needed for iio ops */
744 if (rdev->rio_mem) {
745 atom_card_info->ioreg_read = cail_ioreg_read;
746 atom_card_info->ioreg_write = cail_ioreg_write;
747 } else {
748 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
749 atom_card_info->ioreg_read = cail_reg_read;
750 atom_card_info->ioreg_write = cail_reg_write;
751 }
752 atom_card_info->mc_read = cail_mc_read;
753 atom_card_info->mc_write = cail_mc_write;
754 atom_card_info->pll_read = cail_pll_read;
755 atom_card_info->pll_write = cail_pll_write;
756
757 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
758 sx_init(&rdev->mode_info.atom_context->mutex,
759 "drm__radeon_device__mode_info__atom_context__mutex");
760 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
761 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
762 return 0;
763}
764
765/**
766 * radeon_atombios_fini - free the driver info and callbacks for atombios
767 *
768 * @rdev: radeon_device pointer
769 *
770 * Frees the driver info and register access callbacks for the ATOM
771 * interpreter (r4xx+).
772 * Called at driver shutdown.
773 */
774void radeon_atombios_fini(struct radeon_device *rdev)
775{
776 if (rdev->mode_info.atom_context) {
777 free(rdev->mode_info.atom_context->scratch, DRM_MEM_DRIVER);
778 atom_destroy(rdev->mode_info.atom_context);
779 }
780 free(rdev->mode_info.atom_card_info, DRM_MEM_DRIVER);
781}
782
783/* COMBIOS */
784/*
785 * COMBIOS is the bios format prior to ATOM. It provides
786 * command tables similar to ATOM, but doesn't have a unified
787 * parser. See radeon_combios.c
788 */
789
790/**
791 * radeon_combios_init - init the driver info for combios
792 *
793 * @rdev: radeon_device pointer
794 *
795 * Initializes the driver info for combios (r1xx-r3xx).
796 * Returns 0 on success.
797 * Called at driver startup.
798 */
799int radeon_combios_init(struct radeon_device *rdev)
800{
801 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
802 return 0;
803}
804
805/**
806 * radeon_combios_fini - free the driver info for combios
807 *
808 * @rdev: radeon_device pointer
809 *
810 * Frees the driver info for combios (r1xx-r3xx).
811 * Called at driver shutdown.
812 */
813void radeon_combios_fini(struct radeon_device *rdev)
814{
815}
816
817#ifdef FREEBSD_WIP
818/* if we get transitioned to only one device, take VGA back */
819/**
820 * radeon_vga_set_decode - enable/disable vga decode
821 *
822 * @cookie: radeon_device pointer
823 * @state: enable/disable vga decode
824 *
825 * Enable/disable vga decode (all asics).
826 * Returns VGA resource flags.
827 */
828static unsigned int radeon_vga_set_decode(void *cookie, bool state)
829{
830 struct radeon_device *rdev = cookie;
831 radeon_vga_set_state(rdev, state);
832 if (state)
833 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
834 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
835 else
836 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
837}
838#endif /* FREEBSD_WIP */
839
840/**
841 * radeon_check_pot_argument - check that argument is a power of two
842 *
843 * @arg: value to check
844 *
845 * Validates that a certain argument is a power of two (all asics).
846 * Returns true if argument is valid.
847 */
848static bool radeon_check_pot_argument(int arg)
849{
850 return (arg & (arg - 1)) == 0;
851}
852
853/**
854 * radeon_check_arguments - validate module params
855 *
856 * @rdev: radeon_device pointer
857 *
858 * Validates certain module parameters and updates
859 * the associated values used by the driver (all asics).
860 */
861static void radeon_check_arguments(struct radeon_device *rdev)
862{
863 /* vramlimit must be a power of two */
864 if (!radeon_check_pot_argument(radeon_vram_limit)) {
865 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
866 radeon_vram_limit);
867 radeon_vram_limit = 0;
868 }
869
870 /* gtt size must be power of two and greater or equal to 32M */
871 if (radeon_gart_size < 32) {
872 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
873 radeon_gart_size);
874 radeon_gart_size = 512;
875
876 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
877 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
878 radeon_gart_size);
879 radeon_gart_size = 512;
880 }
881 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
882
883 /* AGP mode can only be -1, 1, 2, 4, 8 */
884 switch (radeon_agpmode) {
885 case -1:
886 case 0:
887 case 1:
888 case 2:
889 case 4:
890 case 8:
891 break;
892 default:
893 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
894 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
895 radeon_agpmode = 0;
896 break;
897 }
898}
899
900/**
901 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
902 * needed for waking up.
903 *
904 * @pdev: pci dev pointer
905 */
906#ifdef FREEBSD_WIP
907static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
908{
909
910 /* 6600m in a macbook pro */
911 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
912 pdev->subsystem_device == 0x00e2) {
913 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
914 return true;
915 }
916
917 return false;
918}
919#endif /* FREEBSD_WIP */
920
921/**
922 * radeon_switcheroo_set_state - set switcheroo state
923 *
924 * @pdev: pci dev pointer
925 * @state: vga switcheroo state
926 *
927 * Callback for the switcheroo driver. Suspends or resumes the
928 * the asics before or after it is powered up using ACPI methods.
929 */
930#ifdef FREEBSD_WIP
931static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
932{
933 struct drm_device *dev = pci_get_drvdata(pdev);
934 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
935 if (state == VGA_SWITCHEROO_ON) {
936 unsigned d3_delay = dev->pdev->d3_delay;
937
938 printk(KERN_INFO "radeon: switched on\n");
939 /* don't suspend or resume card normally */
940 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
941
942 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
943 dev->pdev->d3_delay = 20;
944
945 radeon_resume_kms(dev);
946
947 dev->pdev->d3_delay = d3_delay;
948
949 dev->switch_power_state = DRM_SWITCH_POWER_ON;
950 drm_kms_helper_poll_enable(dev);
951 } else {
952 printk(KERN_INFO "radeon: switched off\n");
953 drm_kms_helper_poll_disable(dev);
954 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
955 radeon_suspend_kms(dev, pmm);
956 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
957 }
958}
959#endif /* FREEBSD_WIP */
960
961/**
962 * radeon_switcheroo_can_switch - see if switcheroo state can change
963 *
964 * @pdev: pci dev pointer
965 *
966 * Callback for the switcheroo driver. Check of the switcheroo
967 * state can be changed.
968 * Returns true if the state can be changed, false if not.
969 */
970#ifdef FREEBSD_WIP
971static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
972{
973 struct drm_device *dev = pci_get_drvdata(pdev);
974 bool can_switch;
975
976 spin_lock(&dev->count_lock);
977 can_switch = (dev->open_count == 0);
978 spin_unlock(&dev->count_lock);
979 return can_switch;
980}
981
982static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
983 .set_gpu_state = radeon_switcheroo_set_state,
984 .reprobe = NULL,
985 .can_switch = radeon_switcheroo_can_switch,
986};
987#endif /* FREEBSD_WIP */
988
989/**
990 * radeon_device_init - initialize the driver
991 *
992 * @rdev: radeon_device pointer
993 * @pdev: drm dev pointer
994 * @flags: driver flags
995 *
996 * Initializes the driver info and hw (all asics).
997 * Returns 0 for success or an error on failure.
998 * Called at driver startup.
999 */
1000int radeon_device_init(struct radeon_device *rdev,
1001 struct drm_device *ddev,
1002 uint32_t flags)
1003{
1004 int r, i;
1005 int dma_bits;
1006
1007 rdev->shutdown = false;
1008 rdev->dev = ddev->dev;
1009 rdev->ddev = ddev;
1010 rdev->flags = flags;
1011 rdev->family = flags & RADEON_FAMILY_MASK;
1012 rdev->is_atom_bios = false;
1013 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1014 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1015 rdev->accel_working = false;
1016 rdev->fictitious_range_registered = false;
1017 rdev->fictitious_agp_range_registered = false;
1018 /* set up ring ids */
1019 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1020 rdev->ring[i].idx = i;
1021 }
1022
1023 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1024 radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device,
1025 ddev->pci_subvendor, ddev->pci_subdevice);
1026
1027 /* mutex initialization are all done here so we
1028 * can recall function without having locking issues */
1029 sx_init(&rdev->ring_lock, "drm__radeon_device__ring_lock");
1030 sx_init(&rdev->dc_hw_i2c_mutex, "drm__radeon_device__dc_hw_i2c_mutex");
1031 atomic_set(&rdev->ih.lock, 0);
1032 sx_init(&rdev->gem.mutex, "drm__radeon_device__gem__mutex");
1033 sx_init(&rdev->pm.mutex, "drm__radeon_device__pm__mutex");
1034 sx_init(&rdev->gpu_clock_mutex, "drm__radeon_device__gpu_clock_mutex");
1035 sx_init(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock");
1036 sx_init(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock");
1037 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue);
1038 r = radeon_gem_init(rdev);
1039 if (r)
1040 return r;
1041 /* initialize vm here */
1042 sx_init(&rdev->vm_manager.lock, "drm__radeon_device__vm_manager__lock");
1043 /* Adjust VM size here.
1044 * Currently set to 4GB ((1 << 20) 4k pages).
1045 * Max GPUVM size for cayman and SI is 40 bits.
1046 */
1047 rdev->vm_manager.max_pfn = 1 << 20;
1048 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1049
1050 /* Set asic functions */
1051 r = radeon_asic_init(rdev);
1052 if (r)
1053 return r;
1054 radeon_check_arguments(rdev);
1055
1056 /* all of the newer IGP chips have an internal gart
1057 * However some rs4xx report as AGP, so remove that here.
1058 */
1059 if ((rdev->family >= CHIP_RS400) &&
1060 (rdev->flags & RADEON_IS_IGP)) {
1061 rdev->flags &= ~RADEON_IS_AGP;
1062 }
1063
1064 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1065 radeon_agp_disable(rdev);
1066 }
1067
1068 /* set DMA mask + need_dma32 flags.
1069 * PCIE - can handle 40-bits.
1070 * IGP - can handle 40-bits
1071 * AGP - generally dma32 is safest
1072 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1073 */
1074 rdev->need_dma32 = false;
1075 if (rdev->flags & RADEON_IS_AGP)
1076 rdev->need_dma32 = true;
1077 if ((rdev->flags & RADEON_IS_PCI) &&
1078 (rdev->family <= CHIP_RS740))
1079 rdev->need_dma32 = true;
1080
1081 dma_bits = rdev->need_dma32 ? 32 : 40;
1082#ifdef FREEBSD_WIP
1083 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1084 if (r) {
1085 rdev->need_dma32 = true;
1086 dma_bits = 32;
1087 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1088 }
1089 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1090 if (r) {
1091 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1092 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1093 }
1094#endif /* FREEBSD_WIP */
1095
1096 /* Registers mapping */
1097 /* TODO: block userspace mapping of io register */
1098 DRM_SPININIT(&rdev->mmio_idx_lock, "drm__radeon_device__mmio_idx_lock");
1099 rdev->rmmio_rid = PCIR_BAR(2);
1100 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY,
1101 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE);
1102 if (rdev->rmmio == NULL) {
1103 return -ENOMEM;
1104 }
1105 rdev->rmmio_base = rman_get_start(rdev->rmmio);
1106 rdev->rmmio_size = rman_get_size(rdev->rmmio);
1107 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1108 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1109
1110 /* io port mapping */
1111 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) {
1112 uint32_t data;
1113
1114 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4);
1115 if (PCI_BAR_IO(data)) {
1116 rdev->rio_rid = PCIR_BAR(i);
1117 rdev->rio_mem = bus_alloc_resource_any(rdev->dev,
1118 SYS_RES_IOPORT, &rdev->rio_rid,
1119 RF_ACTIVE | RF_SHAREABLE);
1120 break;
1121 }
1122 }
1123 if (rdev->rio_mem == NULL)
1124 DRM_ERROR("Unable to find PCI I/O BAR\n");
1125
1126 rdev->tq = taskqueue_create("radeonkms", M_WAITOK,
1127 taskqueue_thread_enqueue, &rdev->tq);
1128 taskqueue_start_threads(&rdev->tq, 1, PWAIT, "radeon taskq");
1129
1130#ifdef FREEBSD_WIP
1131 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1132 /* this will fail for cards that aren't VGA class devices, just
1133 * ignore it */
1134 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1135 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1136#endif /* FREEBSD_WIP */
1137
1138 r = radeon_init(rdev);
1139 if (r)
1140 return r;
1141
1142 r = radeon_ib_ring_tests(rdev);
1143 if (r)
1144 DRM_ERROR("ib ring test failed (%d).\n", r);
1145
1146 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1147 /* Acceleration not working on AGP card try again
1148 * with fallback to PCI or PCIE GART
1149 */
1150 radeon_asic_reset(rdev);
1151 radeon_fini(rdev);
1152 radeon_agp_disable(rdev);
1153 r = radeon_init(rdev);
1154 if (r)
1155 return r;
1156 }
1157
1158 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1159 __func__, (uintmax_t)rdev->mc.aper_base,
1160 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size);
1161 r = vm_phys_fictitious_reg_range(
1162 rdev->mc.aper_base,
1163 rdev->mc.aper_base + rdev->mc.visible_vram_size,
1164 VM_MEMATTR_WRITE_COMBINING);
1165 if (r != 0) {
1166 DRM_ERROR("Failed to register fictitious range "
1167 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base,
1168 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r);
1169 return (-r);
1170 }
1171 rdev->fictitious_range_registered = true;
1172#if __OS_HAS_AGP
1173 if (rdev->flags & RADEON_IS_AGP) {
1174 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1175 __func__, (uintmax_t)rdev->mc.agp_base,
1176 (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size);
1177 r = vm_phys_fictitious_reg_range(
1178 rdev->mc.agp_base,
1179 rdev->mc.agp_base + rdev->mc.gtt_size,
1180 VM_MEMATTR_WRITE_COMBINING);
1181 if (r != 0) {
1182 DRM_ERROR("Failed to register fictitious range "
1183 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.agp_base,
1184 (uintmax_t)rdev->mc.agp_base + rdev->mc.gtt_size, r);
1185 return (-r);
1186 }
1187 rdev->fictitious_agp_range_registered = true;
1188 }
1189#endif
1190
1191 if ((radeon_testing & 1)) {
1192 radeon_test_moves(rdev);
1193 }
1194 if ((radeon_testing & 2)) {
1195 radeon_test_syncing(rdev);
1196 }
1197 if (radeon_benchmarking) {
1198 radeon_benchmark(rdev, radeon_benchmarking);
1199 }
1200 return 0;
1201}
1202
1203#ifdef FREEBSD_WIP
1204static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1205#endif /* FREEBSD_WIP */
1206
1207/**
1208 * radeon_device_fini - tear down the driver
1209 *
1210 * @rdev: radeon_device pointer
1211 *
1212 * Tear down the driver info (all asics).
1213 * Called at driver shutdown.
1214 */
1215void radeon_device_fini(struct radeon_device *rdev)
1216{
1217 DRM_INFO("radeon: finishing device.\n");
1218 rdev->shutdown = true;
1219 /* evict vram memory */
1220 radeon_bo_evict_vram(rdev);
1221
1222 if (rdev->fictitious_range_registered) {
1223 vm_phys_fictitious_unreg_range(
1224 rdev->mc.aper_base,
1225 rdev->mc.aper_base + rdev->mc.visible_vram_size);
1226 }
1227#if __OS_HAS_AGP
1228 if (rdev->fictitious_agp_range_registered) {
1229 vm_phys_fictitious_unreg_range(
1230 rdev->mc.agp_base,
1231 rdev->mc.agp_base + rdev->mc.gtt_size);
1232 }
1233#endif
1234
1235 radeon_fini(rdev);
1236#ifdef FREEBSD_WIP
1237 vga_switcheroo_unregister_client(rdev->pdev);
1238 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1239#endif /* FREEBSD_WIP */
1240
1241 if (rdev->tq != NULL) {
1242 taskqueue_free(rdev->tq);
1243 rdev->tq = NULL;
1244 }
1245
1246 if (rdev->rio_mem)
1247 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid,
1248 rdev->rio_mem);
1249 rdev->rio_mem = NULL;
1250 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid,
1251 rdev->rmmio);
1252 rdev->rmmio = NULL;
1253#ifdef FREEBSD_WIP
1254 radeon_debugfs_remove_files(rdev);
1255#endif /* FREEBSD_WIP */
1256}
1257
1258
1259/*
1260 * Suspend & resume.
1261 */
1262/**
1263 * radeon_suspend_kms - initiate device suspend
1264 *
1265 * @pdev: drm dev pointer
1266 * @state: suspend state
1267 *
1268 * Puts the hw in the suspend state (all asics).
1269 * Returns 0 for success or an error on failure.
1270 * Called at driver suspend.
1271 */
1272int radeon_suspend_kms(struct drm_device *dev)
1273{
1274 struct radeon_device *rdev;
1275 struct drm_crtc *crtc;
1276 struct drm_connector *connector;
1277 int i, r;
1278 bool force_completion = false;
1279
1280 if (dev == NULL || dev->dev_private == NULL) {
1281 return -ENODEV;
1282 }
1283#ifdef FREEBSD_WIP
1284 if (state.event == PM_EVENT_PRETHAW) {
1285 return 0;
1286 }
1287#endif /* FREEBSD_WIP */
1288 rdev = dev->dev_private;
1289
1290 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1291 return 0;
1292
1293 drm_kms_helper_poll_disable(dev);
1294
1295 /* turn off display hw */
1296 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1297 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1298 }
1299
1300 /* unpin the front buffers */
1301 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1302 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1303 struct radeon_bo *robj;
1304
1305 if (rfb == NULL || rfb->obj == NULL) {
1306 continue;
1307 }
1308 robj = gem_to_radeon_bo(rfb->obj);
1309 /* don't unpin kernel fb objects */
1310 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1311 r = radeon_bo_reserve(robj, false);
1312 if (r == 0) {
1313 radeon_bo_unpin(robj);
1314 radeon_bo_unreserve(robj);
1315 }
1316 }
1317 }
1318 /* evict vram memory */
1319 radeon_bo_evict_vram(rdev);
1320
1321 sx_xlock(&rdev->ring_lock);
1322 /* wait for gpu to finish processing current batch */
1323 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1324 r = radeon_fence_wait_empty_locked(rdev, i);
1325 if (r) {
1326 /* delay GPU reset to resume */
1327 force_completion = true;
1328 }
1329 }
1330 if (force_completion) {
1331 radeon_fence_driver_force_completion(rdev);
1332 }
1333 sx_xunlock(&rdev->ring_lock);
1334
1335 radeon_save_bios_scratch_regs(rdev);
1336
1337 radeon_pm_suspend(rdev);
1338 radeon_suspend(rdev);
1339 radeon_hpd_fini(rdev);
1340 /* evict remaining vram memory */
1341 radeon_bo_evict_vram(rdev);
1342
1343 radeon_agp_suspend(rdev);
1344
1345#ifdef FREEBSD_WIP
1346 if (state.event == PM_EVENT_SUSPEND) {
1347 /* Shut down the device */
1348 pci_disable_device(dev->pdev);
1349 }
1350 console_lock();
1351#endif /* FREEBSD_WIP */
1352 radeon_fbdev_set_suspend(rdev, 1);
1353#ifdef FREEBSD_WIP
1354 console_unlock();
1355#endif /* FREEBSD_WIP */
1356 return 0;
1357}
1358
1359/**
1360 * radeon_resume_kms - initiate device resume
1361 *
1362 * @pdev: drm dev pointer
1363 *
1364 * Bring the hw back to operating state (all asics).
1365 * Returns 0 for success or an error on failure.
1366 * Called at driver resume.
1367 */
1368int radeon_resume_kms(struct drm_device *dev)
1369{
1370 struct drm_connector *connector;
1371 struct radeon_device *rdev = dev->dev_private;
1372 int r;
1373
1374 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1375 return 0;
1376
1377#ifdef FREEBSD_WIP
1378 console_lock();
1379 if (pci_enable_device(dev->pdev)) {
1380 console_unlock();
1381 return -1;
1382 }
1383#endif /* FREEBSD_WIP */
1384 /* resume AGP if in use */
1385 radeon_agp_resume(rdev);
1386 radeon_resume(rdev);
1387
1388 r = radeon_ib_ring_tests(rdev);
1389 if (r)
1390 DRM_ERROR("ib ring test failed (%d).\n", r);
1391
1392 radeon_pm_resume(rdev);
1393 radeon_restore_bios_scratch_regs(rdev);
1394
1395 radeon_fbdev_set_suspend(rdev, 0);
1396#ifdef FREEBSD_WIP
1397 console_unlock();
1398#endif /* FREEBSD_WIP */
1399
1400 /* init dig PHYs, disp eng pll */
1401 if (rdev->is_atom_bios) {
1402 radeon_atom_encoder_init(rdev);
1403 radeon_atom_disp_eng_pll_init(rdev);
1404 /* turn on the BL */
1405 if (rdev->mode_info.bl_encoder) {
1406 u8 bl_level = radeon_get_backlight_level(rdev,
1407 rdev->mode_info.bl_encoder);
1408 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1409 bl_level);
1410 }
1411 }
1412 /* reset hpd state */
1413 radeon_hpd_init(rdev);
1414 /* blat the mode back in */
1415 drm_helper_resume_force_mode(dev);
1416 /* turn on display hw */
1417 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1418 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1419 }
1420
1421 drm_kms_helper_poll_enable(dev);
1422 return 0;
1423}
1424
1425/**
1426 * radeon_gpu_reset - reset the asic
1427 *
1428 * @rdev: radeon device pointer
1429 *
1430 * Attempt the reset the GPU if it has hung (all asics).
1431 * Returns 0 for success or an error on failure.
1432 */
1433int radeon_gpu_reset(struct radeon_device *rdev)
1434{
1435 unsigned ring_sizes[RADEON_NUM_RINGS];
1436 uint32_t *ring_data[RADEON_NUM_RINGS];
1437
1438 bool saved = false;
1439
1440 int i, r;
1441 int resched;
1442
1443 sx_xlock(&rdev->exclusive_lock);
1444 radeon_save_bios_scratch_regs(rdev);
1445 /* block TTM */
1446 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1447 radeon_suspend(rdev);
1448
1449 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1450 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1451 &ring_data[i]);
1452 if (ring_sizes[i]) {
1453 saved = true;
1454 dev_info(rdev->dev, "Saved %d dwords of commands "
1455 "on ring %d.\n", ring_sizes[i], i);
1456 }
1457 }
1458
1459retry:
1460 r = radeon_asic_reset(rdev);
1461 if (!r) {
1462 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1463 radeon_resume(rdev);
1464 }
1465
1466 radeon_restore_bios_scratch_regs(rdev);
1467
1468 if (!r) {
1469 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1470 radeon_ring_restore(rdev, &rdev->ring[i],
1471 ring_sizes[i], ring_data[i]);
1472 ring_sizes[i] = 0;
1473 ring_data[i] = NULL;
1474 }
1475
1476 r = radeon_ib_ring_tests(rdev);
1477 if (r) {
1478 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1479 if (saved) {
1480 saved = false;
1481 radeon_suspend(rdev);
1482 goto retry;
1483 }
1484 }
1485 } else {
1486 radeon_fence_driver_force_completion(rdev);
1487 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1488 free(ring_data[i], DRM_MEM_DRIVER);
1489 }
1490 }
1491
1492 drm_helper_resume_force_mode(rdev->ddev);
1493
1494 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1495 if (r) {
1496 /* bad news, how to tell it to userspace ? */
1497 dev_info(rdev->dev, "GPU reset failed\n");
1498 }
1499
1500 sx_xunlock(&rdev->exclusive_lock);
1501 return r;
1502}
1503
1504
1505/*
1506 * Debugfs
1507 */
1508#ifdef FREEBSD_WIP
1509int radeon_debugfs_add_files(struct radeon_device *rdev,
1510 struct drm_info_list *files,
1511 unsigned nfiles)
1512{
1513 unsigned i;
1514
1515 for (i = 0; i < rdev->debugfs_count; i++) {
1516 if (rdev->debugfs[i].files == files) {
1517 /* Already registered */
1518 return 0;
1519 }
1520 }
1521
1522 i = rdev->debugfs_count + 1;
1523 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1524 DRM_ERROR("Reached maximum number of debugfs components.\n");
1525 DRM_ERROR("Report so we increase "
1526 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1527 return -EINVAL;
1528 }
1529 rdev->debugfs[rdev->debugfs_count].files = files;
1530 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1531 rdev->debugfs_count = i;
1532#if defined(CONFIG_DEBUG_FS)
1533 drm_debugfs_create_files(files, nfiles,
1534 rdev->ddev->control->debugfs_root,
1535 rdev->ddev->control);
1536 drm_debugfs_create_files(files, nfiles,
1537 rdev->ddev->primary->debugfs_root,
1538 rdev->ddev->primary);
1539#endif
1540 return 0;
1541}
1542
1543static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1544{
1545#if defined(CONFIG_DEBUG_FS)
1546 unsigned i;
1547
1548 for (i = 0; i < rdev->debugfs_count; i++) {
1549 drm_debugfs_remove_files(rdev->debugfs[i].files,
1550 rdev->debugfs[i].num_files,
1551 rdev->ddev->control);
1552 drm_debugfs_remove_files(rdev->debugfs[i].files,
1553 rdev->debugfs[i].num_files,
1554 rdev->ddev->primary);
1555 }
1556#endif
1557}
1558
1559#if defined(CONFIG_DEBUG_FS)
1560int radeon_debugfs_init(struct drm_minor *minor)
1561{
1562 return 0;
1563}
1564
1565void radeon_debugfs_cleanup(struct drm_minor *minor)
1566{
1567}
1568#endif /* FREEBSD_WIP */
1569#endif
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