| radeon_drv.h (113995) | radeon_drv.h (119098) |
|---|---|
| 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 13 unchanged lines hidden (view full) --- 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * | 1/* radeon_drv.h -- Private header for radeon driver -*- linux-c -*- 2 * 3 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All rights reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 13 unchanged lines hidden (view full) --- 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * |
| 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 113995 2003-04-25 01:18:47Z anholt $ | 30 * $FreeBSD: head/sys/dev/drm/radeon_drv.h 119098 2003-08-19 02:57:31Z anholt $ |
| 31 */ 32 33#ifndef __RADEON_DRV_H__ 34#define __RADEON_DRV_H__ 35 36#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) 37#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 38 --- 117 unchanged lines hidden (view full) --- 156} drm_radeon_buf_priv_t; 157 158 /* radeon_cp.c */ 159extern int radeon_cp_init( DRM_IOCTL_ARGS ); 160extern int radeon_cp_start( DRM_IOCTL_ARGS ); 161extern int radeon_cp_stop( DRM_IOCTL_ARGS ); 162extern int radeon_cp_reset( DRM_IOCTL_ARGS ); 163extern int radeon_cp_idle( DRM_IOCTL_ARGS ); | 31 */ 32 33#ifndef __RADEON_DRV_H__ 34#define __RADEON_DRV_H__ 35 36#define GET_RING_HEAD(dev_priv) DRM_READ32( (dev_priv)->ring_rptr, 0 ) 37#define SET_RING_HEAD(dev_priv,val) DRM_WRITE32( (dev_priv)->ring_rptr, 0, (val) ) 38 --- 117 unchanged lines hidden (view full) --- 156} drm_radeon_buf_priv_t; 157 158 /* radeon_cp.c */ 159extern int radeon_cp_init( DRM_IOCTL_ARGS ); 160extern int radeon_cp_start( DRM_IOCTL_ARGS ); 161extern int radeon_cp_stop( DRM_IOCTL_ARGS ); 162extern int radeon_cp_reset( DRM_IOCTL_ARGS ); 163extern int radeon_cp_idle( DRM_IOCTL_ARGS ); |
| 164extern int radeon_cp_resume( DRM_IOCTL_ARGS ); |
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| 164extern int radeon_engine_reset( DRM_IOCTL_ARGS ); 165extern int radeon_fullscreen( DRM_IOCTL_ARGS ); 166extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); 167 168extern void radeon_freelist_reset( drm_device_t *dev ); 169extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 170 171extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); --- 406 unchanged lines hidden (view full) --- 578#define RADEON_TXFORMAT_I8 0 579#define RADEON_TXFORMAT_AI88 1 580#define RADEON_TXFORMAT_RGB332 2 581#define RADEON_TXFORMAT_ARGB1555 3 582#define RADEON_TXFORMAT_RGB565 4 583#define RADEON_TXFORMAT_ARGB4444 5 584#define RADEON_TXFORMAT_ARGB8888 6 585#define RADEON_TXFORMAT_RGBA8888 7 | 165extern int radeon_engine_reset( DRM_IOCTL_ARGS ); 166extern int radeon_fullscreen( DRM_IOCTL_ARGS ); 167extern int radeon_cp_buffers( DRM_IOCTL_ARGS ); 168 169extern void radeon_freelist_reset( drm_device_t *dev ); 170extern drm_buf_t *radeon_freelist_get( drm_device_t *dev ); 171 172extern int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n ); --- 406 unchanged lines hidden (view full) --- 579#define RADEON_TXFORMAT_I8 0 580#define RADEON_TXFORMAT_AI88 1 581#define RADEON_TXFORMAT_RGB332 2 582#define RADEON_TXFORMAT_ARGB1555 3 583#define RADEON_TXFORMAT_RGB565 4 584#define RADEON_TXFORMAT_ARGB4444 5 585#define RADEON_TXFORMAT_ARGB8888 6 586#define RADEON_TXFORMAT_RGBA8888 7 |
| 587#define RADEON_TXFORMAT_Y8 8 |
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| 586#define RADEON_TXFORMAT_VYUY422 10 587#define RADEON_TXFORMAT_YVYU422 11 588#define RADEON_TXFORMAT_DXT1 12 589#define RADEON_TXFORMAT_DXT23 14 590#define RADEON_TXFORMAT_DXT45 15 591 592#define R200_PP_TXCBLEND_0 0x2f00 593#define R200_PP_TXCBLEND_1 0x2f10 --- 70 unchanged lines hidden (view full) --- 664#define R200_RE_SCISSOR_TL_1 0x1ce0 665#define R200_RE_SCISSOR_TL_2 0x1ce8 666#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 667#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 668#define R200_SE_VTX_STATE_CNTL 0x2180 669#define R200_RE_POINTSIZE 0x2648 670#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 671 | 588#define RADEON_TXFORMAT_VYUY422 10 589#define RADEON_TXFORMAT_YVYU422 11 590#define RADEON_TXFORMAT_DXT1 12 591#define RADEON_TXFORMAT_DXT23 14 592#define RADEON_TXFORMAT_DXT45 15 593 594#define R200_PP_TXCBLEND_0 0x2f00 595#define R200_PP_TXCBLEND_1 0x2f10 --- 70 unchanged lines hidden (view full) --- 666#define R200_RE_SCISSOR_TL_1 0x1ce0 667#define R200_RE_SCISSOR_TL_2 0x1ce8 668#define R200_RB3D_DEPTHXY_OFFSET 0x1d60 669#define R200_RE_AUX_SCISSOR_CNTL 0x26f0 670#define R200_SE_VTX_STATE_CNTL 0x2180 671#define R200_RE_POINTSIZE 0x2648 672#define R200_SE_TCL_INPUT_VTX_VECTOR_ADDR_0 0x2254 673 |
| 674#define RADEON_PP_TEX_SIZE_0 0x1d04 /* NPOT */ 675#define RADEON_PP_TEX_SIZE_1 0x1d0c 676#define RADEON_PP_TEX_SIZE_2 0x1d14 |
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| 672 | 677 |
| 678 |
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| 673#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 674#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 675#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 676#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 677#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 678#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 679#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 680#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b --- 168 unchanged lines hidden (view full) --- 849 ((dev_priv->ring.tail + _nr) & mask), \ 850 write, __LINE__); \ 851 } else \ 852 dev_priv->ring.tail = write; \ 853} while (0) 854 855#define COMMIT_RING() do { \ 856 /* Flush writes to ring */ \ | 679#define SE_VAP_CNTL__TCL_ENA_MASK 0x00000001 680#define SE_VAP_CNTL__FORCE_W_TO_ONE_MASK 0x00010000 681#define SE_VAP_CNTL__VF_MAX_VTX_NUM__SHIFT 0x00000012 682#define SE_VTE_CNTL__VTX_XY_FMT_MASK 0x00000100 683#define SE_VTE_CNTL__VTX_Z_FMT_MASK 0x00000200 684#define SE_VTX_FMT_0__VTX_Z0_PRESENT_MASK 0x00000001 685#define SE_VTX_FMT_0__VTX_W0_PRESENT_MASK 0x00000002 686#define SE_VTX_FMT_0__VTX_COLOR_0_FMT__SHIFT 0x0000000b --- 168 unchanged lines hidden (view full) --- 855 ((dev_priv->ring.tail + _nr) & mask), \ 856 write, __LINE__); \ 857 } else \ 858 dev_priv->ring.tail = write; \ 859} while (0) 860 861#define COMMIT_RING() do { \ 862 /* Flush writes to ring */ \ |
| 857 DRM_READMEMORYBARRIER( dev_priv->mmio ); \ | 863 DRM_MEMORYBARRIER(); \ |
| 858 GET_RING_HEAD( dev_priv ); \ 859 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 860 /* read from PCI bus to ensure correct posting */ \ 861 RADEON_READ( RADEON_CP_RB_RPTR ); \ 862} while (0) 863 864#define OUT_RING( x ) do { \ 865 if ( RADEON_VERBOSE ) { \ --- 37 unchanged lines hidden --- | 864 GET_RING_HEAD( dev_priv ); \ 865 RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail ); \ 866 /* read from PCI bus to ensure correct posting */ \ 867 RADEON_READ( RADEON_CP_RB_RPTR ); \ 868} while (0) 869 870#define OUT_RING( x ) do { \ 871 if ( RADEON_VERBOSE ) { \ --- 37 unchanged lines hidden --- |