| radeon_drm.h (113995) | radeon_drm.h (119098) |
|---|---|
| 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a --- 15 unchanged lines hidden (view full) --- 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 * | 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas. 6 * All rights reserved. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a --- 15 unchanged lines hidden (view full) --- 24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 25 * DEALINGS IN THE SOFTWARE. 26 * 27 * Authors: 28 * Kevin E. Martin <martin@valinux.com> 29 * Gareth Hughes <gareth@valinux.com> 30 * Keith Whitwell <keith@tungstengraphics.com> 31 * |
| 32 * $FreeBSD: head/sys/dev/drm/radeon_drm.h 113995 2003-04-25 01:18:47Z anholt $ | 32 * $FreeBSD: head/sys/dev/drm/radeon_drm.h 119098 2003-08-19 02:57:31Z anholt $ |
| 33 */ 34 35#ifndef __RADEON_DRM_H__ 36#define __RADEON_DRM_H__ 37 38/* WARNING: If you change any of these defines, make sure to change the 39 * defines in the X server file (radeon_sarea.h) 40 */ --- 97 unchanged lines hidden (view full) --- 138#define R200_EMIT_PP_CUBIC_FACES_2 65 139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 140#define R200_EMIT_PP_CUBIC_FACES_3 67 141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 142#define R200_EMIT_PP_CUBIC_FACES_4 69 143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 144#define R200_EMIT_PP_CUBIC_FACES_5 71 145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 | 33 */ 34 35#ifndef __RADEON_DRM_H__ 36#define __RADEON_DRM_H__ 37 38/* WARNING: If you change any of these defines, make sure to change the 39 * defines in the X server file (radeon_sarea.h) 40 */ --- 97 unchanged lines hidden (view full) --- 138#define R200_EMIT_PP_CUBIC_FACES_2 65 139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66 140#define R200_EMIT_PP_CUBIC_FACES_3 67 141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68 142#define R200_EMIT_PP_CUBIC_FACES_4 69 143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70 144#define R200_EMIT_PP_CUBIC_FACES_5 71 145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72 |
| 146#define RADEON_MAX_STATE_PACKETS 73 | 146#define RADEON_EMIT_PP_TEX_SIZE_0 73 147#define RADEON_EMIT_PP_TEX_SIZE_1 74 148#define RADEON_EMIT_PP_TEX_SIZE_2 75 149#define RADEON_MAX_STATE_PACKETS 76 |
| 147 148 149/* Commands understood by cmd_buffer ioctl. More can be added but 150 * obviously these can't be removed or changed: 151 */ 152#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 153#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 154#define RADEON_CMD_VECTORS 3 /* emit vector data */ --- 165 unchanged lines hidden (view full) --- 320 drm_radeon_context_regs_t context; 321 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 322 drm_radeon_context2_regs_t context2; 323 unsigned int dirty; 324} drm_radeon_state_t; 325 326 327typedef struct { | 150 151 152/* Commands understood by cmd_buffer ioctl. More can be added but 153 * obviously these can't be removed or changed: 154 */ 155#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */ 156#define RADEON_CMD_SCALARS 2 /* emit scalar data */ 157#define RADEON_CMD_VECTORS 3 /* emit vector data */ --- 165 unchanged lines hidden (view full) --- 323 drm_radeon_context_regs_t context; 324 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS]; 325 drm_radeon_context2_regs_t context2; 326 unsigned int dirty; 327} drm_radeon_state_t; 328 329 330typedef struct { |
| 328 unsigned char next, prev; 329 unsigned char in_use; 330 int age; 331} drm_radeon_tex_region_t; 332 333typedef struct { | |
| 334 /* The channel for communication of state information to the 335 * kernel on firing a vertex buffer with either of the 336 * obsoleted vertex/index ioctls. 337 */ 338 drm_radeon_context_regs_t context_state; 339 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 340 unsigned int dirty; 341 unsigned int vertsize; --- 5 unchanged lines hidden (view full) --- 347 unsigned int nbox; 348 349 /* Counters for client-side throttling of rendering clients. 350 */ 351 unsigned int last_frame; 352 unsigned int last_dispatch; 353 unsigned int last_clear; 354 | 331 /* The channel for communication of state information to the 332 * kernel on firing a vertex buffer with either of the 333 * obsoleted vertex/index ioctls. 334 */ 335 drm_radeon_context_regs_t context_state; 336 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS]; 337 unsigned int dirty; 338 unsigned int vertsize; --- 5 unchanged lines hidden (view full) --- 344 unsigned int nbox; 345 346 /* Counters for client-side throttling of rendering clients. 347 */ 348 unsigned int last_frame; 349 unsigned int last_dispatch; 350 unsigned int last_clear; 351 |
| 355 drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 356 int tex_age[RADEON_NR_TEX_HEAPS]; | 352 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1]; 353 unsigned int tex_age[RADEON_NR_TEX_HEAPS]; |
| 357 int ctx_owner; 358 int pfState; /* number of 3d windows (0,1,2ormore) */ 359 int pfCurrentPage; /* which buffer is being displayed? */ 360 int crtc2_base; /* CRTC2 frame offset */ 361} drm_radeon_sarea_t; 362 363 364/* WARNING: If you change any of these defines, make sure to change the --- 23 unchanged lines hidden (view full) --- 388#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t) 389#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t) 390#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52) 391#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t) 392#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t) 393#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t) 394#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t) 395#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t) | 354 int ctx_owner; 355 int pfState; /* number of 3d windows (0,1,2ormore) */ 356 int pfCurrentPage; /* which buffer is being displayed? */ 357 int crtc2_base; /* CRTC2 frame offset */ 358} drm_radeon_sarea_t; 359 360 361/* WARNING: If you change any of these defines, make sure to change the --- 23 unchanged lines hidden (view full) --- 385#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t) 386#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t) 387#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52) 388#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t) 389#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t) 390#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t) 391#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t) 392#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t) |
| 393/* added by Charl P. Botha - see radeon_cp.c for details */ 394#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(0x58) |
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| 396 397typedef struct drm_radeon_init { 398 enum { 399 RADEON_INIT_CP = 0x01, 400 RADEON_CLEANUP_CP = 0x02, 401 RADEON_INIT_R200_CP = 0x03 402 } func; 403 unsigned long sarea_priv_offset; --- 123 unchanged lines hidden (view full) --- 527 528/* 1.3: An ioctl to get parameters that aren't available to the 3d 529 * client any other way. 530 */ 531#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */ 532#define RADEON_PARAM_LAST_FRAME 2 533#define RADEON_PARAM_LAST_DISPATCH 3 534#define RADEON_PARAM_LAST_CLEAR 4 | 395 396typedef struct drm_radeon_init { 397 enum { 398 RADEON_INIT_CP = 0x01, 399 RADEON_CLEANUP_CP = 0x02, 400 RADEON_INIT_R200_CP = 0x03 401 } func; 402 unsigned long sarea_priv_offset; --- 123 unchanged lines hidden (view full) --- 526 527/* 1.3: An ioctl to get parameters that aren't available to the 3d 528 * client any other way. 529 */ 530#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */ 531#define RADEON_PARAM_LAST_FRAME 2 532#define RADEON_PARAM_LAST_DISPATCH 3 533#define RADEON_PARAM_LAST_CLEAR 4 |
| 534/* Added with DRM version 1.6. */ |
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| 535#define RADEON_PARAM_IRQ_NR 5 536#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ | 535#define RADEON_PARAM_IRQ_NR 5 536#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */ |
| 537/* Added with DRM version 1.8. */ |
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| 537#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 538#define RADEON_PARAM_STATUS_HANDLE 8 539#define RADEON_PARAM_SAREA_HANDLE 9 540#define RADEON_PARAM_AGP_TEX_HANDLE 10 541 542typedef struct drm_radeon_getparam { 543 int param; 544 int *value; --- 38 unchanged lines hidden --- | 538#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */ 539#define RADEON_PARAM_STATUS_HANDLE 8 540#define RADEON_PARAM_SAREA_HANDLE 9 541#define RADEON_PARAM_AGP_TEX_HANDLE 10 542 543typedef struct drm_radeon_getparam { 544 int param; 545 int *value; --- 38 unchanged lines hidden --- |