1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
| 1/* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * Copyright 2002 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Kevin E. Martin <martin@valinux.com>
29 * Gareth Hughes <gareth@valinux.com>
30 * Keith Whitwell <keith@tungstengraphics.com>
31 *
|
32 * $FreeBSD: head/sys/dev/drm/radeon_drm.h 113995 2003-04-25 01:18:47Z anholt $
| 32 * $FreeBSD: head/sys/dev/drm/radeon_drm.h 119098 2003-08-19 02:57:31Z anholt $
|
33 */
34
35#ifndef __RADEON_DRM_H__
36#define __RADEON_DRM_H__
37
38/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the X server file (radeon_sarea.h)
40 */
41#ifndef __RADEON_SAREA_DEFINES__
42#define __RADEON_SAREA_DEFINES__
43
44/* Old style state flags, required for sarea interface (1.1 and 1.2
45 * clears) and 1.2 drm_vertex2 ioctl.
46 */
47#define RADEON_UPLOAD_CONTEXT 0x00000001
48#define RADEON_UPLOAD_VERTFMT 0x00000002
49#define RADEON_UPLOAD_LINE 0x00000004
50#define RADEON_UPLOAD_BUMPMAP 0x00000008
51#define RADEON_UPLOAD_MASKS 0x00000010
52#define RADEON_UPLOAD_VIEWPORT 0x00000020
53#define RADEON_UPLOAD_SETUP 0x00000040
54#define RADEON_UPLOAD_TCL 0x00000080
55#define RADEON_UPLOAD_MISC 0x00000100
56#define RADEON_UPLOAD_TEX0 0x00000200
57#define RADEON_UPLOAD_TEX1 0x00000400
58#define RADEON_UPLOAD_TEX2 0x00000800
59#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
60#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
61#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
62#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
63#define RADEON_REQUIRE_QUIESCENCE 0x00010000
64#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
65#define RADEON_UPLOAD_ALL 0x003effff
66#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
67
68
69/* New style per-packet identifiers for use in cmd_buffer ioctl with
70 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
71 * state bits and the packet size:
72 */
73#define RADEON_EMIT_PP_MISC 0 /* context/7 */
74#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
75#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
76#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
77#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
78#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
79#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
80#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
81#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
82#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
83#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
84#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
85#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
87#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
89#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
90#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
91#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
92#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
93#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
94#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
95#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
96#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
97#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
98#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
99#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
100#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
101#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
102#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
103#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
104#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
105#define R200_EMIT_VAP_CTL 32 /* vap/1 */
106#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
107#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
108#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
109#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
110#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
111#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
112#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
113#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
114#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
115#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
116#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
117#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
118#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
119#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
120#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
121#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
122#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
123#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
124#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
125#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
126#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
127#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
128#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
129#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
130#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
131#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
132#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
133#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
134#define R200_EMIT_PP_CUBIC_FACES_0 61
135#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
136#define R200_EMIT_PP_CUBIC_FACES_1 63
137#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
138#define R200_EMIT_PP_CUBIC_FACES_2 65
139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
140#define R200_EMIT_PP_CUBIC_FACES_3 67
141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
142#define R200_EMIT_PP_CUBIC_FACES_4 69
143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
144#define R200_EMIT_PP_CUBIC_FACES_5 71
145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
| 33 */
34
35#ifndef __RADEON_DRM_H__
36#define __RADEON_DRM_H__
37
38/* WARNING: If you change any of these defines, make sure to change the
39 * defines in the X server file (radeon_sarea.h)
40 */
41#ifndef __RADEON_SAREA_DEFINES__
42#define __RADEON_SAREA_DEFINES__
43
44/* Old style state flags, required for sarea interface (1.1 and 1.2
45 * clears) and 1.2 drm_vertex2 ioctl.
46 */
47#define RADEON_UPLOAD_CONTEXT 0x00000001
48#define RADEON_UPLOAD_VERTFMT 0x00000002
49#define RADEON_UPLOAD_LINE 0x00000004
50#define RADEON_UPLOAD_BUMPMAP 0x00000008
51#define RADEON_UPLOAD_MASKS 0x00000010
52#define RADEON_UPLOAD_VIEWPORT 0x00000020
53#define RADEON_UPLOAD_SETUP 0x00000040
54#define RADEON_UPLOAD_TCL 0x00000080
55#define RADEON_UPLOAD_MISC 0x00000100
56#define RADEON_UPLOAD_TEX0 0x00000200
57#define RADEON_UPLOAD_TEX1 0x00000400
58#define RADEON_UPLOAD_TEX2 0x00000800
59#define RADEON_UPLOAD_TEX0IMAGES 0x00001000
60#define RADEON_UPLOAD_TEX1IMAGES 0x00002000
61#define RADEON_UPLOAD_TEX2IMAGES 0x00004000
62#define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
63#define RADEON_REQUIRE_QUIESCENCE 0x00010000
64#define RADEON_UPLOAD_ZBIAS 0x00020000 /* version 1.2 and newer */
65#define RADEON_UPLOAD_ALL 0x003effff
66#define RADEON_UPLOAD_CONTEXT_ALL 0x003e01ff
67
68
69/* New style per-packet identifiers for use in cmd_buffer ioctl with
70 * the RADEON_EMIT_PACKET command. Comments relate new packets to old
71 * state bits and the packet size:
72 */
73#define RADEON_EMIT_PP_MISC 0 /* context/7 */
74#define RADEON_EMIT_PP_CNTL 1 /* context/3 */
75#define RADEON_EMIT_RB3D_COLORPITCH 2 /* context/1 */
76#define RADEON_EMIT_RE_LINE_PATTERN 3 /* line/2 */
77#define RADEON_EMIT_SE_LINE_WIDTH 4 /* line/1 */
78#define RADEON_EMIT_PP_LUM_MATRIX 5 /* bumpmap/1 */
79#define RADEON_EMIT_PP_ROT_MATRIX_0 6 /* bumpmap/2 */
80#define RADEON_EMIT_RB3D_STENCILREFMASK 7 /* masks/3 */
81#define RADEON_EMIT_SE_VPORT_XSCALE 8 /* viewport/6 */
82#define RADEON_EMIT_SE_CNTL 9 /* setup/2 */
83#define RADEON_EMIT_SE_CNTL_STATUS 10 /* setup/1 */
84#define RADEON_EMIT_RE_MISC 11 /* misc/1 */
85#define RADEON_EMIT_PP_TXFILTER_0 12 /* tex0/6 */
86#define RADEON_EMIT_PP_BORDER_COLOR_0 13 /* tex0/1 */
87#define RADEON_EMIT_PP_TXFILTER_1 14 /* tex1/6 */
88#define RADEON_EMIT_PP_BORDER_COLOR_1 15 /* tex1/1 */
89#define RADEON_EMIT_PP_TXFILTER_2 16 /* tex2/6 */
90#define RADEON_EMIT_PP_BORDER_COLOR_2 17 /* tex2/1 */
91#define RADEON_EMIT_SE_ZBIAS_FACTOR 18 /* zbias/2 */
92#define RADEON_EMIT_SE_TCL_OUTPUT_VTX_FMT 19 /* tcl/11 */
93#define RADEON_EMIT_SE_TCL_MATERIAL_EMMISSIVE_RED 20 /* material/17 */
94#define R200_EMIT_PP_TXCBLEND_0 21 /* tex0/4 */
95#define R200_EMIT_PP_TXCBLEND_1 22 /* tex1/4 */
96#define R200_EMIT_PP_TXCBLEND_2 23 /* tex2/4 */
97#define R200_EMIT_PP_TXCBLEND_3 24 /* tex3/4 */
98#define R200_EMIT_PP_TXCBLEND_4 25 /* tex4/4 */
99#define R200_EMIT_PP_TXCBLEND_5 26 /* tex5/4 */
100#define R200_EMIT_PP_TXCBLEND_6 27 /* /4 */
101#define R200_EMIT_PP_TXCBLEND_7 28 /* /4 */
102#define R200_EMIT_TCL_LIGHT_MODEL_CTL_0 29 /* tcl/7 */
103#define R200_EMIT_TFACTOR_0 30 /* tf/7 */
104#define R200_EMIT_VTX_FMT_0 31 /* vtx/5 */
105#define R200_EMIT_VAP_CTL 32 /* vap/1 */
106#define R200_EMIT_MATRIX_SELECT_0 33 /* msl/5 */
107#define R200_EMIT_TEX_PROC_CTL_2 34 /* tcg/5 */
108#define R200_EMIT_TCL_UCP_VERT_BLEND_CTL 35 /* tcl/1 */
109#define R200_EMIT_PP_TXFILTER_0 36 /* tex0/6 */
110#define R200_EMIT_PP_TXFILTER_1 37 /* tex1/6 */
111#define R200_EMIT_PP_TXFILTER_2 38 /* tex2/6 */
112#define R200_EMIT_PP_TXFILTER_3 39 /* tex3/6 */
113#define R200_EMIT_PP_TXFILTER_4 40 /* tex4/6 */
114#define R200_EMIT_PP_TXFILTER_5 41 /* tex5/6 */
115#define R200_EMIT_PP_TXOFFSET_0 42 /* tex0/1 */
116#define R200_EMIT_PP_TXOFFSET_1 43 /* tex1/1 */
117#define R200_EMIT_PP_TXOFFSET_2 44 /* tex2/1 */
118#define R200_EMIT_PP_TXOFFSET_3 45 /* tex3/1 */
119#define R200_EMIT_PP_TXOFFSET_4 46 /* tex4/1 */
120#define R200_EMIT_PP_TXOFFSET_5 47 /* tex5/1 */
121#define R200_EMIT_VTE_CNTL 48 /* vte/1 */
122#define R200_EMIT_OUTPUT_VTX_COMP_SEL 49 /* vtx/1 */
123#define R200_EMIT_PP_TAM_DEBUG3 50 /* tam/1 */
124#define R200_EMIT_PP_CNTL_X 51 /* cst/1 */
125#define R200_EMIT_RB3D_DEPTHXY_OFFSET 52 /* cst/1 */
126#define R200_EMIT_RE_AUX_SCISSOR_CNTL 53 /* cst/1 */
127#define R200_EMIT_RE_SCISSOR_TL_0 54 /* cst/2 */
128#define R200_EMIT_RE_SCISSOR_TL_1 55 /* cst/2 */
129#define R200_EMIT_RE_SCISSOR_TL_2 56 /* cst/2 */
130#define R200_EMIT_SE_VAP_CNTL_STATUS 57 /* cst/1 */
131#define R200_EMIT_SE_VTX_STATE_CNTL 58 /* cst/1 */
132#define R200_EMIT_RE_POINTSIZE 59 /* cst/1 */
133#define R200_EMIT_TCL_INPUT_VTX_VECTOR_ADDR_0 60 /* cst/4 */
134#define R200_EMIT_PP_CUBIC_FACES_0 61
135#define R200_EMIT_PP_CUBIC_OFFSETS_0 62
136#define R200_EMIT_PP_CUBIC_FACES_1 63
137#define R200_EMIT_PP_CUBIC_OFFSETS_1 64
138#define R200_EMIT_PP_CUBIC_FACES_2 65
139#define R200_EMIT_PP_CUBIC_OFFSETS_2 66
140#define R200_EMIT_PP_CUBIC_FACES_3 67
141#define R200_EMIT_PP_CUBIC_OFFSETS_3 68
142#define R200_EMIT_PP_CUBIC_FACES_4 69
143#define R200_EMIT_PP_CUBIC_OFFSETS_4 70
144#define R200_EMIT_PP_CUBIC_FACES_5 71
145#define R200_EMIT_PP_CUBIC_OFFSETS_5 72
|
146#define RADEON_MAX_STATE_PACKETS 73
| 146#define RADEON_EMIT_PP_TEX_SIZE_0 73
147#define RADEON_EMIT_PP_TEX_SIZE_1 74
148#define RADEON_EMIT_PP_TEX_SIZE_2 75
149#define RADEON_MAX_STATE_PACKETS 76
|
147
148
149/* Commands understood by cmd_buffer ioctl. More can be added but
150 * obviously these can't be removed or changed:
151 */
152#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
153#define RADEON_CMD_SCALARS 2 /* emit scalar data */
154#define RADEON_CMD_VECTORS 3 /* emit vector data */
155#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
156#define RADEON_CMD_PACKET3 5 /* emit hw packet */
157#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
158#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
159#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
160 * doesn't make the cpu wait, just
161 * the graphics hardware */
162
163
164typedef union {
165 int i;
166 struct {
167 unsigned char cmd_type, pad0, pad1, pad2;
168 } header;
169 struct {
170 unsigned char cmd_type, packet_id, pad0, pad1;
171 } packet;
172 struct {
173 unsigned char cmd_type, offset, stride, count;
174 } scalars;
175 struct {
176 unsigned char cmd_type, offset, stride, count;
177 } vectors;
178 struct {
179 unsigned char cmd_type, buf_idx, pad0, pad1;
180 } dma;
181 struct {
182 unsigned char cmd_type, flags, pad0, pad1;
183 } wait;
184} drm_radeon_cmd_header_t;
185
186#define RADEON_WAIT_2D 0x1
187#define RADEON_WAIT_3D 0x2
188
189
190#define RADEON_FRONT 0x1
191#define RADEON_BACK 0x2
192#define RADEON_DEPTH 0x4
193#define RADEON_STENCIL 0x8
194
195/* Primitive types
196 */
197#define RADEON_POINTS 0x1
198#define RADEON_LINES 0x2
199#define RADEON_LINE_STRIP 0x3
200#define RADEON_TRIANGLES 0x4
201#define RADEON_TRIANGLE_FAN 0x5
202#define RADEON_TRIANGLE_STRIP 0x6
203
204/* Vertex/indirect buffer size
205 */
206#define RADEON_BUFFER_SIZE 65536
207
208/* Byte offsets for indirect buffer data
209 */
210#define RADEON_INDEX_PRIM_OFFSET 20
211
212#define RADEON_SCRATCH_REG_OFFSET 32
213
214#define RADEON_NR_SAREA_CLIPRECTS 12
215
216/* There are 2 heaps (local/AGP). Each region within a heap is a
217 * minimum of 64k, and there are at most 64 of them per heap.
218 */
219#define RADEON_LOCAL_TEX_HEAP 0
220#define RADEON_AGP_TEX_HEAP 1
221#define RADEON_NR_TEX_HEAPS 2
222#define RADEON_NR_TEX_REGIONS 64
223#define RADEON_LOG_TEX_GRANULARITY 16
224
225#define RADEON_MAX_TEXTURE_LEVELS 12
226#define RADEON_MAX_TEXTURE_UNITS 3
227
228#endif /* __RADEON_SAREA_DEFINES__ */
229
230typedef struct {
231 unsigned int red;
232 unsigned int green;
233 unsigned int blue;
234 unsigned int alpha;
235} radeon_color_regs_t;
236
237typedef struct {
238 /* Context state */
239 unsigned int pp_misc; /* 0x1c14 */
240 unsigned int pp_fog_color;
241 unsigned int re_solid_color;
242 unsigned int rb3d_blendcntl;
243 unsigned int rb3d_depthoffset;
244 unsigned int rb3d_depthpitch;
245 unsigned int rb3d_zstencilcntl;
246
247 unsigned int pp_cntl; /* 0x1c38 */
248 unsigned int rb3d_cntl;
249 unsigned int rb3d_coloroffset;
250 unsigned int re_width_height;
251 unsigned int rb3d_colorpitch;
252 unsigned int se_cntl;
253
254 /* Vertex format state */
255 unsigned int se_coord_fmt; /* 0x1c50 */
256
257 /* Line state */
258 unsigned int re_line_pattern; /* 0x1cd0 */
259 unsigned int re_line_state;
260
261 unsigned int se_line_width; /* 0x1db8 */
262
263 /* Bumpmap state */
264 unsigned int pp_lum_matrix; /* 0x1d00 */
265
266 unsigned int pp_rot_matrix_0; /* 0x1d58 */
267 unsigned int pp_rot_matrix_1;
268
269 /* Mask state */
270 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
271 unsigned int rb3d_ropcntl;
272 unsigned int rb3d_planemask;
273
274 /* Viewport state */
275 unsigned int se_vport_xscale; /* 0x1d98 */
276 unsigned int se_vport_xoffset;
277 unsigned int se_vport_yscale;
278 unsigned int se_vport_yoffset;
279 unsigned int se_vport_zscale;
280 unsigned int se_vport_zoffset;
281
282 /* Setup state */
283 unsigned int se_cntl_status; /* 0x2140 */
284
285 /* Misc state */
286 unsigned int re_top_left; /* 0x26c0 */
287 unsigned int re_misc;
288} drm_radeon_context_regs_t;
289
290typedef struct {
291 /* Zbias state */
292 unsigned int se_zbias_factor; /* 0x1dac */
293 unsigned int se_zbias_constant;
294} drm_radeon_context2_regs_t;
295
296
297/* Setup registers for each texture unit
298 */
299typedef struct {
300 unsigned int pp_txfilter;
301 unsigned int pp_txformat;
302 unsigned int pp_txoffset;
303 unsigned int pp_txcblend;
304 unsigned int pp_txablend;
305 unsigned int pp_tfactor;
306 unsigned int pp_border_color;
307} drm_radeon_texture_regs_t;
308
309typedef struct {
310 unsigned int start;
311 unsigned int finish;
312 unsigned int prim:8;
313 unsigned int stateidx:8;
314 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
315 unsigned int vc_format; /* vertex format */
316} drm_radeon_prim_t;
317
318
319typedef struct {
320 drm_radeon_context_regs_t context;
321 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
322 drm_radeon_context2_regs_t context2;
323 unsigned int dirty;
324} drm_radeon_state_t;
325
326
327typedef struct {
| 150
151
152/* Commands understood by cmd_buffer ioctl. More can be added but
153 * obviously these can't be removed or changed:
154 */
155#define RADEON_CMD_PACKET 1 /* emit one of the register packets above */
156#define RADEON_CMD_SCALARS 2 /* emit scalar data */
157#define RADEON_CMD_VECTORS 3 /* emit vector data */
158#define RADEON_CMD_DMA_DISCARD 4 /* discard current dma buf */
159#define RADEON_CMD_PACKET3 5 /* emit hw packet */
160#define RADEON_CMD_PACKET3_CLIP 6 /* emit hw packet wrapped in cliprects */
161#define RADEON_CMD_SCALARS2 7 /* r200 stopgap */
162#define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
163 * doesn't make the cpu wait, just
164 * the graphics hardware */
165
166
167typedef union {
168 int i;
169 struct {
170 unsigned char cmd_type, pad0, pad1, pad2;
171 } header;
172 struct {
173 unsigned char cmd_type, packet_id, pad0, pad1;
174 } packet;
175 struct {
176 unsigned char cmd_type, offset, stride, count;
177 } scalars;
178 struct {
179 unsigned char cmd_type, offset, stride, count;
180 } vectors;
181 struct {
182 unsigned char cmd_type, buf_idx, pad0, pad1;
183 } dma;
184 struct {
185 unsigned char cmd_type, flags, pad0, pad1;
186 } wait;
187} drm_radeon_cmd_header_t;
188
189#define RADEON_WAIT_2D 0x1
190#define RADEON_WAIT_3D 0x2
191
192
193#define RADEON_FRONT 0x1
194#define RADEON_BACK 0x2
195#define RADEON_DEPTH 0x4
196#define RADEON_STENCIL 0x8
197
198/* Primitive types
199 */
200#define RADEON_POINTS 0x1
201#define RADEON_LINES 0x2
202#define RADEON_LINE_STRIP 0x3
203#define RADEON_TRIANGLES 0x4
204#define RADEON_TRIANGLE_FAN 0x5
205#define RADEON_TRIANGLE_STRIP 0x6
206
207/* Vertex/indirect buffer size
208 */
209#define RADEON_BUFFER_SIZE 65536
210
211/* Byte offsets for indirect buffer data
212 */
213#define RADEON_INDEX_PRIM_OFFSET 20
214
215#define RADEON_SCRATCH_REG_OFFSET 32
216
217#define RADEON_NR_SAREA_CLIPRECTS 12
218
219/* There are 2 heaps (local/AGP). Each region within a heap is a
220 * minimum of 64k, and there are at most 64 of them per heap.
221 */
222#define RADEON_LOCAL_TEX_HEAP 0
223#define RADEON_AGP_TEX_HEAP 1
224#define RADEON_NR_TEX_HEAPS 2
225#define RADEON_NR_TEX_REGIONS 64
226#define RADEON_LOG_TEX_GRANULARITY 16
227
228#define RADEON_MAX_TEXTURE_LEVELS 12
229#define RADEON_MAX_TEXTURE_UNITS 3
230
231#endif /* __RADEON_SAREA_DEFINES__ */
232
233typedef struct {
234 unsigned int red;
235 unsigned int green;
236 unsigned int blue;
237 unsigned int alpha;
238} radeon_color_regs_t;
239
240typedef struct {
241 /* Context state */
242 unsigned int pp_misc; /* 0x1c14 */
243 unsigned int pp_fog_color;
244 unsigned int re_solid_color;
245 unsigned int rb3d_blendcntl;
246 unsigned int rb3d_depthoffset;
247 unsigned int rb3d_depthpitch;
248 unsigned int rb3d_zstencilcntl;
249
250 unsigned int pp_cntl; /* 0x1c38 */
251 unsigned int rb3d_cntl;
252 unsigned int rb3d_coloroffset;
253 unsigned int re_width_height;
254 unsigned int rb3d_colorpitch;
255 unsigned int se_cntl;
256
257 /* Vertex format state */
258 unsigned int se_coord_fmt; /* 0x1c50 */
259
260 /* Line state */
261 unsigned int re_line_pattern; /* 0x1cd0 */
262 unsigned int re_line_state;
263
264 unsigned int se_line_width; /* 0x1db8 */
265
266 /* Bumpmap state */
267 unsigned int pp_lum_matrix; /* 0x1d00 */
268
269 unsigned int pp_rot_matrix_0; /* 0x1d58 */
270 unsigned int pp_rot_matrix_1;
271
272 /* Mask state */
273 unsigned int rb3d_stencilrefmask; /* 0x1d7c */
274 unsigned int rb3d_ropcntl;
275 unsigned int rb3d_planemask;
276
277 /* Viewport state */
278 unsigned int se_vport_xscale; /* 0x1d98 */
279 unsigned int se_vport_xoffset;
280 unsigned int se_vport_yscale;
281 unsigned int se_vport_yoffset;
282 unsigned int se_vport_zscale;
283 unsigned int se_vport_zoffset;
284
285 /* Setup state */
286 unsigned int se_cntl_status; /* 0x2140 */
287
288 /* Misc state */
289 unsigned int re_top_left; /* 0x26c0 */
290 unsigned int re_misc;
291} drm_radeon_context_regs_t;
292
293typedef struct {
294 /* Zbias state */
295 unsigned int se_zbias_factor; /* 0x1dac */
296 unsigned int se_zbias_constant;
297} drm_radeon_context2_regs_t;
298
299
300/* Setup registers for each texture unit
301 */
302typedef struct {
303 unsigned int pp_txfilter;
304 unsigned int pp_txformat;
305 unsigned int pp_txoffset;
306 unsigned int pp_txcblend;
307 unsigned int pp_txablend;
308 unsigned int pp_tfactor;
309 unsigned int pp_border_color;
310} drm_radeon_texture_regs_t;
311
312typedef struct {
313 unsigned int start;
314 unsigned int finish;
315 unsigned int prim:8;
316 unsigned int stateidx:8;
317 unsigned int numverts:16; /* overloaded as offset/64 for elt prims */
318 unsigned int vc_format; /* vertex format */
319} drm_radeon_prim_t;
320
321
322typedef struct {
323 drm_radeon_context_regs_t context;
324 drm_radeon_texture_regs_t tex[RADEON_MAX_TEXTURE_UNITS];
325 drm_radeon_context2_regs_t context2;
326 unsigned int dirty;
327} drm_radeon_state_t;
328
329
330typedef struct {
|
328 unsigned char next, prev;
329 unsigned char in_use;
330 int age;
331} drm_radeon_tex_region_t;
332
333typedef struct {
| |
334 /* The channel for communication of state information to the
335 * kernel on firing a vertex buffer with either of the
336 * obsoleted vertex/index ioctls.
337 */
338 drm_radeon_context_regs_t context_state;
339 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
340 unsigned int dirty;
341 unsigned int vertsize;
342 unsigned int vc_format;
343
344 /* The current cliprects, or a subset thereof.
345 */
346 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
347 unsigned int nbox;
348
349 /* Counters for client-side throttling of rendering clients.
350 */
351 unsigned int last_frame;
352 unsigned int last_dispatch;
353 unsigned int last_clear;
354
| 331 /* The channel for communication of state information to the
332 * kernel on firing a vertex buffer with either of the
333 * obsoleted vertex/index ioctls.
334 */
335 drm_radeon_context_regs_t context_state;
336 drm_radeon_texture_regs_t tex_state[RADEON_MAX_TEXTURE_UNITS];
337 unsigned int dirty;
338 unsigned int vertsize;
339 unsigned int vc_format;
340
341 /* The current cliprects, or a subset thereof.
342 */
343 drm_clip_rect_t boxes[RADEON_NR_SAREA_CLIPRECTS];
344 unsigned int nbox;
345
346 /* Counters for client-side throttling of rendering clients.
347 */
348 unsigned int last_frame;
349 unsigned int last_dispatch;
350 unsigned int last_clear;
351
|
355 drm_radeon_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
356 int tex_age[RADEON_NR_TEX_HEAPS];
| 352 drm_tex_region_t tex_list[RADEON_NR_TEX_HEAPS][RADEON_NR_TEX_REGIONS+1];
353 unsigned int tex_age[RADEON_NR_TEX_HEAPS];
|
357 int ctx_owner;
358 int pfState; /* number of 3d windows (0,1,2ormore) */
359 int pfCurrentPage; /* which buffer is being displayed? */
360 int crtc2_base; /* CRTC2 frame offset */
361} drm_radeon_sarea_t;
362
363
364/* WARNING: If you change any of these defines, make sure to change the
365 * defines in the Xserver file (xf86drmRadeon.h)
366 *
367 * KW: actually it's illegal to change any of this (backwards compatibility).
368 */
369
370/* Radeon specific ioctls
371 * The device specific ioctl range is 0x40 to 0x79.
372 */
373#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
374#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
375#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
376#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
377#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
378#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
379#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
380#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
381#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
382#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
383#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
384#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
385#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
386#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
387#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex2_t)
388#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t)
389#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t)
390#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52)
391#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t)
392#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t)
393#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t)
394#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t)
395#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t)
| 354 int ctx_owner;
355 int pfState; /* number of 3d windows (0,1,2ormore) */
356 int pfCurrentPage; /* which buffer is being displayed? */
357 int crtc2_base; /* CRTC2 frame offset */
358} drm_radeon_sarea_t;
359
360
361/* WARNING: If you change any of these defines, make sure to change the
362 * defines in the Xserver file (xf86drmRadeon.h)
363 *
364 * KW: actually it's illegal to change any of this (backwards compatibility).
365 */
366
367/* Radeon specific ioctls
368 * The device specific ioctl range is 0x40 to 0x79.
369 */
370#define DRM_IOCTL_RADEON_CP_INIT DRM_IOW( 0x40, drm_radeon_init_t)
371#define DRM_IOCTL_RADEON_CP_START DRM_IO( 0x41)
372#define DRM_IOCTL_RADEON_CP_STOP DRM_IOW( 0x42, drm_radeon_cp_stop_t)
373#define DRM_IOCTL_RADEON_CP_RESET DRM_IO( 0x43)
374#define DRM_IOCTL_RADEON_CP_IDLE DRM_IO( 0x44)
375#define DRM_IOCTL_RADEON_RESET DRM_IO( 0x45)
376#define DRM_IOCTL_RADEON_FULLSCREEN DRM_IOW( 0x46, drm_radeon_fullscreen_t)
377#define DRM_IOCTL_RADEON_SWAP DRM_IO( 0x47)
378#define DRM_IOCTL_RADEON_CLEAR DRM_IOW( 0x48, drm_radeon_clear_t)
379#define DRM_IOCTL_RADEON_VERTEX DRM_IOW( 0x49, drm_radeon_vertex_t)
380#define DRM_IOCTL_RADEON_INDICES DRM_IOW( 0x4a, drm_radeon_indices_t)
381#define DRM_IOCTL_RADEON_STIPPLE DRM_IOW( 0x4c, drm_radeon_stipple_t)
382#define DRM_IOCTL_RADEON_INDIRECT DRM_IOWR(0x4d, drm_radeon_indirect_t)
383#define DRM_IOCTL_RADEON_TEXTURE DRM_IOWR(0x4e, drm_radeon_texture_t)
384#define DRM_IOCTL_RADEON_VERTEX2 DRM_IOW( 0x4f, drm_radeon_vertex2_t)
385#define DRM_IOCTL_RADEON_CMDBUF DRM_IOW( 0x50, drm_radeon_cmd_buffer_t)
386#define DRM_IOCTL_RADEON_GETPARAM DRM_IOWR(0x51, drm_radeon_getparam_t)
387#define DRM_IOCTL_RADEON_FLIP DRM_IO( 0x52)
388#define DRM_IOCTL_RADEON_ALLOC DRM_IOWR( 0x53, drm_radeon_mem_alloc_t)
389#define DRM_IOCTL_RADEON_FREE DRM_IOW( 0x54, drm_radeon_mem_free_t)
390#define DRM_IOCTL_RADEON_INIT_HEAP DRM_IOW( 0x55, drm_radeon_mem_init_heap_t)
391#define DRM_IOCTL_RADEON_IRQ_EMIT DRM_IOWR( 0x56, drm_radeon_irq_emit_t)
392#define DRM_IOCTL_RADEON_IRQ_WAIT DRM_IOW( 0x57, drm_radeon_irq_wait_t)
|
| 393/* added by Charl P. Botha - see radeon_cp.c for details */
394#define DRM_IOCTL_RADEON_CP_RESUME DRM_IO(0x58)
|
396
397typedef struct drm_radeon_init {
398 enum {
399 RADEON_INIT_CP = 0x01,
400 RADEON_CLEANUP_CP = 0x02,
401 RADEON_INIT_R200_CP = 0x03
402 } func;
403 unsigned long sarea_priv_offset;
404 int is_pci;
405 int cp_mode;
406 int agp_size;
407 int ring_size;
408 int usec_timeout;
409
410 unsigned int fb_bpp;
411 unsigned int front_offset, front_pitch;
412 unsigned int back_offset, back_pitch;
413 unsigned int depth_bpp;
414 unsigned int depth_offset, depth_pitch;
415
416 unsigned long fb_offset;
417 unsigned long mmio_offset;
418 unsigned long ring_offset;
419 unsigned long ring_rptr_offset;
420 unsigned long buffers_offset;
421 unsigned long agp_textures_offset;
422} drm_radeon_init_t;
423
424typedef struct drm_radeon_cp_stop {
425 int flush;
426 int idle;
427} drm_radeon_cp_stop_t;
428
429typedef struct drm_radeon_fullscreen {
430 enum {
431 RADEON_INIT_FULLSCREEN = 0x01,
432 RADEON_CLEANUP_FULLSCREEN = 0x02
433 } func;
434} drm_radeon_fullscreen_t;
435
436#define CLEAR_X1 0
437#define CLEAR_Y1 1
438#define CLEAR_X2 2
439#define CLEAR_Y2 3
440#define CLEAR_DEPTH 4
441
442typedef union drm_radeon_clear_rect {
443 float f[5];
444 unsigned int ui[5];
445} drm_radeon_clear_rect_t;
446
447typedef struct drm_radeon_clear {
448 unsigned int flags;
449 unsigned int clear_color;
450 unsigned int clear_depth;
451 unsigned int color_mask;
452 unsigned int depth_mask; /* misnamed field: should be stencil */
453 drm_radeon_clear_rect_t *depth_boxes;
454} drm_radeon_clear_t;
455
456typedef struct drm_radeon_vertex {
457 int prim;
458 int idx; /* Index of vertex buffer */
459 int count; /* Number of vertices in buffer */
460 int discard; /* Client finished with buffer? */
461} drm_radeon_vertex_t;
462
463typedef struct drm_radeon_indices {
464 int prim;
465 int idx;
466 int start;
467 int end;
468 int discard; /* Client finished with buffer? */
469} drm_radeon_indices_t;
470
471/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
472 * - allows multiple primitives and state changes in a single ioctl
473 * - supports driver change to emit native primitives
474 */
475typedef struct drm_radeon_vertex2 {
476 int idx; /* Index of vertex buffer */
477 int discard; /* Client finished with buffer? */
478 int nr_states;
479 drm_radeon_state_t *state;
480 int nr_prims;
481 drm_radeon_prim_t *prim;
482} drm_radeon_vertex2_t;
483
484/* v1.3 - obsoletes drm_radeon_vertex2
485 * - allows arbitarily large cliprect list
486 * - allows updating of tcl packet, vector and scalar state
487 * - allows memory-efficient description of state updates
488 * - allows state to be emitted without a primitive
489 * (for clears, ctx switches)
490 * - allows more than one dma buffer to be referenced per ioctl
491 * - supports tcl driver
492 * - may be extended in future versions with new cmd types, packets
493 */
494typedef struct drm_radeon_cmd_buffer {
495 int bufsz;
496 char *buf;
497 int nbox;
498 drm_clip_rect_t *boxes;
499} drm_radeon_cmd_buffer_t;
500
501typedef struct drm_radeon_tex_image {
502 unsigned int x, y; /* Blit coordinates */
503 unsigned int width, height;
504 const void *data;
505} drm_radeon_tex_image_t;
506
507typedef struct drm_radeon_texture {
508 int offset;
509 int pitch;
510 int format;
511 int width; /* Texture image coordinates */
512 int height;
513 drm_radeon_tex_image_t *image;
514} drm_radeon_texture_t;
515
516typedef struct drm_radeon_stipple {
517 unsigned int *mask;
518} drm_radeon_stipple_t;
519
520typedef struct drm_radeon_indirect {
521 int idx;
522 int start;
523 int end;
524 int discard;
525} drm_radeon_indirect_t;
526
527
528/* 1.3: An ioctl to get parameters that aren't available to the 3d
529 * client any other way.
530 */
531#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
532#define RADEON_PARAM_LAST_FRAME 2
533#define RADEON_PARAM_LAST_DISPATCH 3
534#define RADEON_PARAM_LAST_CLEAR 4
| 395
396typedef struct drm_radeon_init {
397 enum {
398 RADEON_INIT_CP = 0x01,
399 RADEON_CLEANUP_CP = 0x02,
400 RADEON_INIT_R200_CP = 0x03
401 } func;
402 unsigned long sarea_priv_offset;
403 int is_pci;
404 int cp_mode;
405 int agp_size;
406 int ring_size;
407 int usec_timeout;
408
409 unsigned int fb_bpp;
410 unsigned int front_offset, front_pitch;
411 unsigned int back_offset, back_pitch;
412 unsigned int depth_bpp;
413 unsigned int depth_offset, depth_pitch;
414
415 unsigned long fb_offset;
416 unsigned long mmio_offset;
417 unsigned long ring_offset;
418 unsigned long ring_rptr_offset;
419 unsigned long buffers_offset;
420 unsigned long agp_textures_offset;
421} drm_radeon_init_t;
422
423typedef struct drm_radeon_cp_stop {
424 int flush;
425 int idle;
426} drm_radeon_cp_stop_t;
427
428typedef struct drm_radeon_fullscreen {
429 enum {
430 RADEON_INIT_FULLSCREEN = 0x01,
431 RADEON_CLEANUP_FULLSCREEN = 0x02
432 } func;
433} drm_radeon_fullscreen_t;
434
435#define CLEAR_X1 0
436#define CLEAR_Y1 1
437#define CLEAR_X2 2
438#define CLEAR_Y2 3
439#define CLEAR_DEPTH 4
440
441typedef union drm_radeon_clear_rect {
442 float f[5];
443 unsigned int ui[5];
444} drm_radeon_clear_rect_t;
445
446typedef struct drm_radeon_clear {
447 unsigned int flags;
448 unsigned int clear_color;
449 unsigned int clear_depth;
450 unsigned int color_mask;
451 unsigned int depth_mask; /* misnamed field: should be stencil */
452 drm_radeon_clear_rect_t *depth_boxes;
453} drm_radeon_clear_t;
454
455typedef struct drm_radeon_vertex {
456 int prim;
457 int idx; /* Index of vertex buffer */
458 int count; /* Number of vertices in buffer */
459 int discard; /* Client finished with buffer? */
460} drm_radeon_vertex_t;
461
462typedef struct drm_radeon_indices {
463 int prim;
464 int idx;
465 int start;
466 int end;
467 int discard; /* Client finished with buffer? */
468} drm_radeon_indices_t;
469
470/* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
471 * - allows multiple primitives and state changes in a single ioctl
472 * - supports driver change to emit native primitives
473 */
474typedef struct drm_radeon_vertex2 {
475 int idx; /* Index of vertex buffer */
476 int discard; /* Client finished with buffer? */
477 int nr_states;
478 drm_radeon_state_t *state;
479 int nr_prims;
480 drm_radeon_prim_t *prim;
481} drm_radeon_vertex2_t;
482
483/* v1.3 - obsoletes drm_radeon_vertex2
484 * - allows arbitarily large cliprect list
485 * - allows updating of tcl packet, vector and scalar state
486 * - allows memory-efficient description of state updates
487 * - allows state to be emitted without a primitive
488 * (for clears, ctx switches)
489 * - allows more than one dma buffer to be referenced per ioctl
490 * - supports tcl driver
491 * - may be extended in future versions with new cmd types, packets
492 */
493typedef struct drm_radeon_cmd_buffer {
494 int bufsz;
495 char *buf;
496 int nbox;
497 drm_clip_rect_t *boxes;
498} drm_radeon_cmd_buffer_t;
499
500typedef struct drm_radeon_tex_image {
501 unsigned int x, y; /* Blit coordinates */
502 unsigned int width, height;
503 const void *data;
504} drm_radeon_tex_image_t;
505
506typedef struct drm_radeon_texture {
507 int offset;
508 int pitch;
509 int format;
510 int width; /* Texture image coordinates */
511 int height;
512 drm_radeon_tex_image_t *image;
513} drm_radeon_texture_t;
514
515typedef struct drm_radeon_stipple {
516 unsigned int *mask;
517} drm_radeon_stipple_t;
518
519typedef struct drm_radeon_indirect {
520 int idx;
521 int start;
522 int end;
523 int discard;
524} drm_radeon_indirect_t;
525
526
527/* 1.3: An ioctl to get parameters that aren't available to the 3d
528 * client any other way.
529 */
530#define RADEON_PARAM_AGP_BUFFER_OFFSET 1 /* card offset of 1st agp buffer */
531#define RADEON_PARAM_LAST_FRAME 2
532#define RADEON_PARAM_LAST_DISPATCH 3
533#define RADEON_PARAM_LAST_CLEAR 4
|
| 534/* Added with DRM version 1.6. */
|
535#define RADEON_PARAM_IRQ_NR 5
536#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
| 535#define RADEON_PARAM_IRQ_NR 5
536#define RADEON_PARAM_AGP_BASE 6 /* card offset of agp base */
|
| 537/* Added with DRM version 1.8. */
|
537#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
538#define RADEON_PARAM_STATUS_HANDLE 8
539#define RADEON_PARAM_SAREA_HANDLE 9
540#define RADEON_PARAM_AGP_TEX_HANDLE 10
541
542typedef struct drm_radeon_getparam {
543 int param;
544 int *value;
545} drm_radeon_getparam_t;
546
547/* 1.6: Set up a memory manager for regions of shared memory:
548 */
549#define RADEON_MEM_REGION_AGP 1
550#define RADEON_MEM_REGION_FB 2
551
552typedef struct drm_radeon_mem_alloc {
553 int region;
554 int alignment;
555 int size;
556 int *region_offset; /* offset from start of fb or agp */
557} drm_radeon_mem_alloc_t;
558
559typedef struct drm_radeon_mem_free {
560 int region;
561 int region_offset;
562} drm_radeon_mem_free_t;
563
564typedef struct drm_radeon_mem_init_heap {
565 int region;
566 int size;
567 int start;
568} drm_radeon_mem_init_heap_t;
569
570
571/* 1.6: Userspace can request & wait on irq's:
572 */
573typedef struct drm_radeon_irq_emit {
574 int *irq_seq;
575} drm_radeon_irq_emit_t;
576
577typedef struct drm_radeon_irq_wait {
578 int irq_seq;
579} drm_radeon_irq_wait_t;
580
581
582#endif
| 538#define RADEON_PARAM_REGISTER_HANDLE 7 /* for drmMap() */
539#define RADEON_PARAM_STATUS_HANDLE 8
540#define RADEON_PARAM_SAREA_HANDLE 9
541#define RADEON_PARAM_AGP_TEX_HANDLE 10
542
543typedef struct drm_radeon_getparam {
544 int param;
545 int *value;
546} drm_radeon_getparam_t;
547
548/* 1.6: Set up a memory manager for regions of shared memory:
549 */
550#define RADEON_MEM_REGION_AGP 1
551#define RADEON_MEM_REGION_FB 2
552
553typedef struct drm_radeon_mem_alloc {
554 int region;
555 int alignment;
556 int size;
557 int *region_offset; /* offset from start of fb or agp */
558} drm_radeon_mem_alloc_t;
559
560typedef struct drm_radeon_mem_free {
561 int region;
562 int region_offset;
563} drm_radeon_mem_free_t;
564
565typedef struct drm_radeon_mem_init_heap {
566 int region;
567 int size;
568 int start;
569} drm_radeon_mem_init_heap_t;
570
571
572/* 1.6: Userspace can request & wait on irq's:
573 */
574typedef struct drm_radeon_irq_emit {
575 int *irq_seq;
576} drm_radeon_irq_emit_t;
577
578typedef struct drm_radeon_irq_wait {
579 int irq_seq;
580} drm_radeon_irq_wait_t;
581
582
583#endif
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