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< * $FreeBSD: head/sys/dev/drm/radeon_cp.c 113995 2003-04-25 01:18:47Z anholt $
---
> * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119098 2003-08-19 02:57:31Z anholt $
909c909
< entry->busaddr[page_ofs],
---
> (unsigned long) entry->busaddr[page_ofs],
979a980,1006
> /* Enable or disable PCI GART on the chip */
> static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on )
> {
> u32 tmp = RADEON_READ( RADEON_AIC_CNTL );
>
> if ( on ) {
> RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN );
>
> /* set PCI GART page-table base address
> */
> RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
>
> /* set address range for PCI address translate
> */
> RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
> RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
> + dev_priv->agp_size - 1);
>
> /* Turn off AGP aperture -- is this required for PCIGART?
> */
> RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
> RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
> } else {
> RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN );
> }
> }
>
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< u32 tmp;
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> #if __REALLY_HAVE_AGP
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< DRM_IOREMAP( dev_priv->cp_ring );
< DRM_IOREMAP( dev_priv->ring_rptr );
< DRM_IOREMAP( dev_priv->buffers );
---
> DRM_IOREMAP( dev_priv->cp_ring, dev );
> DRM_IOREMAP( dev_priv->ring_rptr, dev );
> DRM_IOREMAP( dev_priv->buffers, dev );
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< } else {
---
> } else
> #endif
> {
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< #if __REALLY_HAVE_SG
< if ( dev_priv->is_pci ) {
---
> #if __REALLY_HAVE_AGP
> if ( !dev_priv->is_pci ) {
> /* Turn off PCI GART */
> radeon_set_pcigart( dev_priv, 0 );
> } else
> #endif
> {
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< /* Turn on PCI GART
< */
< tmp = RADEON_READ( RADEON_AIC_CNTL )
< | RADEON_PCIGART_TRANSLATE_EN;
< RADEON_WRITE( RADEON_AIC_CNTL, tmp );
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< /* set PCI GART page-table base address
< */
< RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
<
< /* set address range for PCI address translate
< */
< RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
< RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
< + dev_priv->agp_size - 1);
<
< /* Turn off AGP aperture -- is this required for PCIGART?
< */
< RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
< RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
< } else {
< #endif /* __REALLY_HAVE_SG */
< /* Turn off PCI GART
< */
< tmp = RADEON_READ( RADEON_AIC_CNTL )
< & ~RADEON_PCIGART_TRANSLATE_EN;
< RADEON_WRITE( RADEON_AIC_CNTL, tmp );
< #if __REALLY_HAVE_SG
---
> /* Turn on PCI GART */
> radeon_set_pcigart( dev_priv, 1 );
1253d1261
< #endif /* __REALLY_HAVE_SG */
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> #if _HAVE_DMA_IRQ
> /* Make sure interrupts are disabled here because the uninstall ioctl
> * may not have been called from userspace and after dev_private
> * is freed, it's too late.
> */
> if ( dev->irq ) DRM(irq_uninstall)(dev);
> #endif
>
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> #if __REALLY_HAVE_AGP
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< DRM_IOREMAPFREE( dev_priv->cp_ring );
---
> DRM_IOREMAPFREE( dev_priv->cp_ring, dev );
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< DRM_IOREMAPFREE( dev_priv->ring_rptr );
---
> DRM_IOREMAPFREE( dev_priv->ring_rptr, dev );
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< DRM_IOREMAPFREE( dev_priv->buffers );
< } else {
< #if __REALLY_HAVE_SG
---
> DRM_IOREMAPFREE( dev_priv->buffers, dev );
> } else
> #endif
> {
1287d1304
< #endif /* __REALLY_HAVE_SG */
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> /* This code will reinit the Radeon CP hardware after a resume from disc.
> * AFAIK, it would be very difficult to pickle the state at suspend time, so
> * here we make sure that all Radeon hardware initialisation is re-done without
> * affecting running applications.
> *
> * Charl P. Botha <http://cpbotha.net>
> */
> static int radeon_do_resume_cp( drm_device_t *dev )
> {
> drm_radeon_private_t *dev_priv = dev->dev_private;
>
> if ( !dev_priv ) {
> DRM_ERROR( "Called with no initialization\n" );
> return DRM_ERR( EINVAL );
> }
>
> DRM_DEBUG("Starting radeon_do_resume_cp()\n");
>
> #if __REALLY_HAVE_AGP
> if ( !dev_priv->is_pci ) {
> /* Turn off PCI GART */
> radeon_set_pcigart( dev_priv, 0 );
> } else
> #endif
> {
> /* Turn on PCI GART */
> radeon_set_pcigart( dev_priv, 1 );
> }
>
> radeon_cp_load_microcode( dev_priv );
> radeon_cp_init_ring_buffer( dev, dev_priv );
>
> radeon_do_engine_reset( dev );
>
> DRM_DEBUG("radeon_do_resume_cp() complete\n");
>
> return 0;
> }
>
>
1302a1360,1361
> LOCK_TEST_WITH_RETURN( dev, filp );
>
1450a1510,1519
> /* Added by Charl P. Botha to call radeon_do_resume_cp().
> */
> int radeon_cp_resume( DRM_IOCTL_ARGS )
> {
> DRM_DEVICE;
>
> return radeon_do_resume_cp(dev);
> }
>
>