radeon_cp.c (113995) | radeon_cp.c (119098) |
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1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 13 unchanged lines hidden (view full) --- 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * | 1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*- 2 * 3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas. 4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California. 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a 8 * copy of this software and associated documentation files (the "Software"), --- 13 unchanged lines hidden (view full) --- 22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 24 * DEALINGS IN THE SOFTWARE. 25 * 26 * Authors: 27 * Kevin E. Martin <martin@valinux.com> 28 * Gareth Hughes <gareth@valinux.com> 29 * |
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 113995 2003-04-25 01:18:47Z anholt $ | 30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 119098 2003-08-19 02:57:31Z anholt $ |
31 */ 32 33#include "dev/drm/radeon.h" 34#include "dev/drm/drmP.h" 35#include "dev/drm/drm.h" 36#include "dev/drm/radeon_drm.h" 37#include "dev/drm/radeon_drv.h" 38 --- 862 unchanged lines hidden (view full) --- 901 unsigned long tmp_ofs, page_ofs; 902 903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 904 page_ofs = tmp_ofs >> PAGE_SHIFT; 905 906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 907 entry->busaddr[page_ofs]); 908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", | 31 */ 32 33#include "dev/drm/radeon.h" 34#include "dev/drm/drmP.h" 35#include "dev/drm/drm.h" 36#include "dev/drm/radeon_drm.h" 37#include "dev/drm/radeon_drv.h" 38 --- 862 unchanged lines hidden (view full) --- 901 unsigned long tmp_ofs, page_ofs; 902 903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle; 904 page_ofs = tmp_ofs >> PAGE_SHIFT; 905 906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR, 907 entry->busaddr[page_ofs]); 908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n", |
909 entry->busaddr[page_ofs], | 909 (unsigned long) entry->busaddr[page_ofs], |
910 entry->handle + tmp_ofs ); 911 } 912 913 /* Initialize the scratch register pointer. This will cause 914 * the scratch register values to be written out to memory 915 * whenever they are updated. 916 * 917 * We simply put this behind the ring read pointer, this works --- 54 unchanged lines hidden (view full) --- 972 /* Sync everything up */ 973 RADEON_WRITE( RADEON_ISYNC_CNTL, 974 (RADEON_ISYNC_ANY2D_IDLE3D | 975 RADEON_ISYNC_ANY3D_IDLE2D | 976 RADEON_ISYNC_WAIT_IDLEGUI | 977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); 978} 979 | 910 entry->handle + tmp_ofs ); 911 } 912 913 /* Initialize the scratch register pointer. This will cause 914 * the scratch register values to be written out to memory 915 * whenever they are updated. 916 * 917 * We simply put this behind the ring read pointer, this works --- 54 unchanged lines hidden (view full) --- 972 /* Sync everything up */ 973 RADEON_WRITE( RADEON_ISYNC_CNTL, 974 (RADEON_ISYNC_ANY2D_IDLE3D | 975 RADEON_ISYNC_ANY3D_IDLE2D | 976 RADEON_ISYNC_WAIT_IDLEGUI | 977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) ); 978} 979 |
980/* Enable or disable PCI GART on the chip */ 981static void radeon_set_pcigart( drm_radeon_private_t *dev_priv, int on ) 982{ 983 u32 tmp = RADEON_READ( RADEON_AIC_CNTL ); 984 985 if ( on ) { 986 RADEON_WRITE( RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN ); 987 988 /* set PCI GART page-table base address 989 */ 990 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); 991 992 /* set address range for PCI address translate 993 */ 994 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start ); 995 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start 996 + dev_priv->agp_size - 1); 997 998 /* Turn off AGP aperture -- is this required for PCIGART? 999 */ 1000 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 1001 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1002 } else { 1003 RADEON_WRITE( RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN ); 1004 } 1005} 1006 |
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980static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) 981{ 982 drm_radeon_private_t *dev_priv; | 1007static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init ) 1008{ 1009 drm_radeon_private_t *dev_priv; |
983 u32 tmp; | |
984 DRM_DEBUG( "\n" ); 985 986 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); 987 if ( dev_priv == NULL ) 988 return DRM_ERR(ENOMEM); 989 990 memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); 991 --- 156 unchanged lines hidden (view full) --- 1148 return DRM_ERR(EINVAL); 1149 } 1150 } 1151 1152 dev_priv->sarea_priv = 1153 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + 1154 init->sarea_priv_offset); 1155 | 1010 DRM_DEBUG( "\n" ); 1011 1012 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER ); 1013 if ( dev_priv == NULL ) 1014 return DRM_ERR(ENOMEM); 1015 1016 memset( dev_priv, 0, sizeof(drm_radeon_private_t) ); 1017 --- 156 unchanged lines hidden (view full) --- 1174 return DRM_ERR(EINVAL); 1175 } 1176 } 1177 1178 dev_priv->sarea_priv = 1179 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle + 1180 init->sarea_priv_offset); 1181 |
1182#if __REALLY_HAVE_AGP |
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1156 if ( !dev_priv->is_pci ) { | 1183 if ( !dev_priv->is_pci ) { |
1157 DRM_IOREMAP( dev_priv->cp_ring ); 1158 DRM_IOREMAP( dev_priv->ring_rptr ); 1159 DRM_IOREMAP( dev_priv->buffers ); | 1184 DRM_IOREMAP( dev_priv->cp_ring, dev ); 1185 DRM_IOREMAP( dev_priv->ring_rptr, dev ); 1186 DRM_IOREMAP( dev_priv->buffers, dev ); |
1160 if(!dev_priv->cp_ring->handle || 1161 !dev_priv->ring_rptr->handle || 1162 !dev_priv->buffers->handle) { 1163 DRM_ERROR("could not find ioremap agp regions!\n"); 1164 dev->dev_private = (void *)dev_priv; 1165 radeon_do_cleanup_cp(dev); 1166 return DRM_ERR(EINVAL); 1167 } | 1187 if(!dev_priv->cp_ring->handle || 1188 !dev_priv->ring_rptr->handle || 1189 !dev_priv->buffers->handle) { 1190 DRM_ERROR("could not find ioremap agp regions!\n"); 1191 dev->dev_private = (void *)dev_priv; 1192 radeon_do_cleanup_cp(dev); 1193 return DRM_ERR(EINVAL); 1194 } |
1168 } else { | 1195 } else 1196#endif 1197 { |
1169 dev_priv->cp_ring->handle = 1170 (void *)dev_priv->cp_ring->offset; 1171 dev_priv->ring_rptr->handle = 1172 (void *)dev_priv->ring_rptr->offset; 1173 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; 1174 1175 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", 1176 dev_priv->cp_ring->handle ); --- 30 unchanged lines hidden (view full) --- 1207 dev_priv->ring.size = init->ring_size; 1208 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 1209 1210 dev_priv->ring.tail_mask = 1211 (dev_priv->ring.size / sizeof(u32)) - 1; 1212 1213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1214 | 1198 dev_priv->cp_ring->handle = 1199 (void *)dev_priv->cp_ring->offset; 1200 dev_priv->ring_rptr->handle = 1201 (void *)dev_priv->ring_rptr->offset; 1202 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset; 1203 1204 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n", 1205 dev_priv->cp_ring->handle ); --- 30 unchanged lines hidden (view full) --- 1236 dev_priv->ring.size = init->ring_size; 1237 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 ); 1238 1239 dev_priv->ring.tail_mask = 1240 (dev_priv->ring.size / sizeof(u32)) - 1; 1241 1242 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK; 1243 |
1215#if __REALLY_HAVE_SG 1216 if ( dev_priv->is_pci ) { | 1244#if __REALLY_HAVE_AGP 1245 if ( !dev_priv->is_pci ) { 1246 /* Turn off PCI GART */ 1247 radeon_set_pcigart( dev_priv, 0 ); 1248 } else 1249#endif 1250 { |
1217 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, 1218 &dev_priv->bus_pci_gart)) { 1219 DRM_ERROR( "failed to init PCI GART!\n" ); 1220 dev->dev_private = (void *)dev_priv; 1221 radeon_do_cleanup_cp(dev); 1222 return DRM_ERR(ENOMEM); 1223 } | 1251 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart, 1252 &dev_priv->bus_pci_gart)) { 1253 DRM_ERROR( "failed to init PCI GART!\n" ); 1254 dev->dev_private = (void *)dev_priv; 1255 radeon_do_cleanup_cp(dev); 1256 return DRM_ERR(ENOMEM); 1257 } |
1224 /* Turn on PCI GART 1225 */ 1226 tmp = RADEON_READ( RADEON_AIC_CNTL ) 1227 | RADEON_PCIGART_TRANSLATE_EN; 1228 RADEON_WRITE( RADEON_AIC_CNTL, tmp ); | |
1229 | 1258 |
1230 /* set PCI GART page-table base address 1231 */ 1232 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart ); 1233 1234 /* set address range for PCI address translate 1235 */ 1236 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start ); 1237 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start 1238 + dev_priv->agp_size - 1); 1239 1240 /* Turn off AGP aperture -- is this required for PCIGART? 1241 */ 1242 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */ 1243 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */ 1244 } else { 1245#endif /* __REALLY_HAVE_SG */ 1246 /* Turn off PCI GART 1247 */ 1248 tmp = RADEON_READ( RADEON_AIC_CNTL ) 1249 & ~RADEON_PCIGART_TRANSLATE_EN; 1250 RADEON_WRITE( RADEON_AIC_CNTL, tmp ); 1251#if __REALLY_HAVE_SG | 1259 /* Turn on PCI GART */ 1260 radeon_set_pcigart( dev_priv, 1 ); |
1252 } | 1261 } |
1253#endif /* __REALLY_HAVE_SG */ | |
1254 1255 radeon_cp_load_microcode( dev_priv ); 1256 radeon_cp_init_ring_buffer( dev, dev_priv ); 1257 1258 dev_priv->last_buf = 0; 1259 1260 dev->dev_private = (void *)dev_priv; 1261 1262 radeon_do_engine_reset( dev ); 1263 1264 return 0; 1265} 1266 1267int radeon_do_cleanup_cp( drm_device_t *dev ) 1268{ 1269 DRM_DEBUG( "\n" ); 1270 | 1262 1263 radeon_cp_load_microcode( dev_priv ); 1264 radeon_cp_init_ring_buffer( dev, dev_priv ); 1265 1266 dev_priv->last_buf = 0; 1267 1268 dev->dev_private = (void *)dev_priv; 1269 1270 radeon_do_engine_reset( dev ); 1271 1272 return 0; 1273} 1274 1275int radeon_do_cleanup_cp( drm_device_t *dev ) 1276{ 1277 DRM_DEBUG( "\n" ); 1278 |
1279#if _HAVE_DMA_IRQ 1280 /* Make sure interrupts are disabled here because the uninstall ioctl 1281 * may not have been called from userspace and after dev_private 1282 * is freed, it's too late. 1283 */ 1284 if ( dev->irq ) DRM(irq_uninstall)(dev); 1285#endif 1286 |
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1271 if ( dev->dev_private ) { 1272 drm_radeon_private_t *dev_priv = dev->dev_private; 1273 | 1287 if ( dev->dev_private ) { 1288 drm_radeon_private_t *dev_priv = dev->dev_private; 1289 |
1290#if __REALLY_HAVE_AGP |
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1274 if ( !dev_priv->is_pci ) { 1275 if ( dev_priv->cp_ring != NULL ) | 1291 if ( !dev_priv->is_pci ) { 1292 if ( dev_priv->cp_ring != NULL ) |
1276 DRM_IOREMAPFREE( dev_priv->cp_ring ); | 1293 DRM_IOREMAPFREE( dev_priv->cp_ring, dev ); |
1277 if ( dev_priv->ring_rptr != NULL ) | 1294 if ( dev_priv->ring_rptr != NULL ) |
1278 DRM_IOREMAPFREE( dev_priv->ring_rptr ); | 1295 DRM_IOREMAPFREE( dev_priv->ring_rptr, dev ); |
1279 if ( dev_priv->buffers != NULL ) | 1296 if ( dev_priv->buffers != NULL ) |
1280 DRM_IOREMAPFREE( dev_priv->buffers ); 1281 } else { 1282#if __REALLY_HAVE_SG | 1297 DRM_IOREMAPFREE( dev_priv->buffers, dev ); 1298 } else 1299#endif 1300 { |
1283 if (!DRM(ati_pcigart_cleanup)( dev, 1284 dev_priv->phys_pci_gart, 1285 dev_priv->bus_pci_gart )) 1286 DRM_ERROR( "failed to cleanup PCI GART!\n" ); | 1301 if (!DRM(ati_pcigart_cleanup)( dev, 1302 dev_priv->phys_pci_gart, 1303 dev_priv->bus_pci_gart )) 1304 DRM_ERROR( "failed to cleanup PCI GART!\n" ); |
1287#endif /* __REALLY_HAVE_SG */ | |
1288 } 1289 1290 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t), 1291 DRM_MEM_DRIVER ); 1292 dev->dev_private = NULL; 1293 } 1294 1295 return 0; 1296} 1297 | 1305 } 1306 1307 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t), 1308 DRM_MEM_DRIVER ); 1309 dev->dev_private = NULL; 1310 } 1311 1312 return 0; 1313} 1314 |
1315/* This code will reinit the Radeon CP hardware after a resume from disc. 1316 * AFAIK, it would be very difficult to pickle the state at suspend time, so 1317 * here we make sure that all Radeon hardware initialisation is re-done without 1318 * affecting running applications. 1319 * 1320 * Charl P. Botha <http://cpbotha.net> 1321 */ 1322static int radeon_do_resume_cp( drm_device_t *dev ) 1323{ 1324 drm_radeon_private_t *dev_priv = dev->dev_private; 1325 1326 if ( !dev_priv ) { 1327 DRM_ERROR( "Called with no initialization\n" ); 1328 return DRM_ERR( EINVAL ); 1329 } 1330 1331 DRM_DEBUG("Starting radeon_do_resume_cp()\n"); 1332 1333#if __REALLY_HAVE_AGP 1334 if ( !dev_priv->is_pci ) { 1335 /* Turn off PCI GART */ 1336 radeon_set_pcigart( dev_priv, 0 ); 1337 } else 1338#endif 1339 { 1340 /* Turn on PCI GART */ 1341 radeon_set_pcigart( dev_priv, 1 ); 1342 } 1343 1344 radeon_cp_load_microcode( dev_priv ); 1345 radeon_cp_init_ring_buffer( dev, dev_priv ); 1346 1347 radeon_do_engine_reset( dev ); 1348 1349 DRM_DEBUG("radeon_do_resume_cp() complete\n"); 1350 1351 return 0; 1352} 1353 1354 |
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1298int radeon_cp_init( DRM_IOCTL_ARGS ) 1299{ 1300 DRM_DEVICE; 1301 drm_radeon_init_t init; 1302 | 1355int radeon_cp_init( DRM_IOCTL_ARGS ) 1356{ 1357 DRM_DEVICE; 1358 drm_radeon_init_t init; 1359 |
1360 LOCK_TEST_WITH_RETURN( dev, filp ); 1361 |
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1303 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) ); 1304 1305 switch ( init.func ) { 1306 case RADEON_INIT_CP: 1307 case RADEON_INIT_R200_CP: 1308 return radeon_do_init_cp( dev, &init ); 1309 case RADEON_CLEANUP_CP: 1310 return radeon_do_cleanup_cp( dev ); --- 132 unchanged lines hidden (view full) --- 1443 drm_radeon_private_t *dev_priv = dev->dev_private; 1444 DRM_DEBUG( "\n" ); 1445 1446 LOCK_TEST_WITH_RETURN( dev, filp ); 1447 1448 return radeon_do_cp_idle( dev_priv ); 1449} 1450 | 1362 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) ); 1363 1364 switch ( init.func ) { 1365 case RADEON_INIT_CP: 1366 case RADEON_INIT_R200_CP: 1367 return radeon_do_init_cp( dev, &init ); 1368 case RADEON_CLEANUP_CP: 1369 return radeon_do_cleanup_cp( dev ); --- 132 unchanged lines hidden (view full) --- 1502 drm_radeon_private_t *dev_priv = dev->dev_private; 1503 DRM_DEBUG( "\n" ); 1504 1505 LOCK_TEST_WITH_RETURN( dev, filp ); 1506 1507 return radeon_do_cp_idle( dev_priv ); 1508} 1509 |
1510/* Added by Charl P. Botha to call radeon_do_resume_cp(). 1511 */ 1512int radeon_cp_resume( DRM_IOCTL_ARGS ) 1513{ 1514 DRM_DEVICE; 1515 1516 return radeon_do_resume_cp(dev); 1517} 1518 1519 |
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1451int radeon_engine_reset( DRM_IOCTL_ARGS ) 1452{ 1453 DRM_DEVICE; 1454 DRM_DEBUG( "\n" ); 1455 1456 LOCK_TEST_WITH_RETURN( dev, filp ); 1457 1458 return radeon_do_engine_reset( dev ); --- 220 unchanged lines hidden --- | 1520int radeon_engine_reset( DRM_IOCTL_ARGS ) 1521{ 1522 DRM_DEVICE; 1523 DRM_DEBUG( "\n" ); 1524 1525 LOCK_TEST_WITH_RETURN( dev, filp ); 1526 1527 return radeon_do_engine_reset( dev ); --- 220 unchanged lines hidden --- |