1/*-
2 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
3 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
4 * Copyright 2007 Advanced Micro Devices, Inc.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/drm/radeon_cp.c 190595 2009-03-31 17:52:05Z rnoland $");
33
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/drm_sarea.h"
37#include "dev/drm/radeon_drm.h"
38#include "dev/drm/radeon_drv.h"
39#include "dev/drm/r300_reg.h"
40
41#include "dev/drm/radeon_microcode.h"
42
43#define RADEON_FIFO_DEBUG 0
44
45static int radeon_do_cleanup_cp(struct drm_device * dev);
46static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
47
48u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
49{
50 u32 val;
51
52 if (dev_priv->flags & RADEON_IS_AGP) {
53 val = DRM_READ32(dev_priv->ring_rptr, off);
54 } else {
55 val = *(((volatile u32 *)
56 dev_priv->ring_rptr->handle) +
57 (off / sizeof(u32)));
58 val = le32_to_cpu(val);
59 }
60 return val;
61}
62
63u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
64{
65 if (dev_priv->writeback_works)
66 return radeon_read_ring_rptr(dev_priv, 0);
67 else {
68 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
69 return RADEON_READ(R600_CP_RB_RPTR);
70 else
71 return RADEON_READ(RADEON_CP_RB_RPTR);
72 }
73}
74
75void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
76{
77 if (dev_priv->flags & RADEON_IS_AGP)
78 DRM_WRITE32(dev_priv->ring_rptr, off, val);
79 else
80 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
81 (off / sizeof(u32))) = cpu_to_le32(val);
82}
83
84void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
85{
86 radeon_write_ring_rptr(dev_priv, 0, val);
87}
88
89u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
90{
91 if (dev_priv->writeback_works) {
92 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
93 return radeon_read_ring_rptr(dev_priv,
94 R600_SCRATCHOFF(index));
95 else
96 return radeon_read_ring_rptr(dev_priv,
97 RADEON_SCRATCHOFF(index));
98 } else {
99 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
100 return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
101 else
102 return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
103 }
104}
105
106u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
107{
108 u32 ret;
109
110 if (addr < 0x10000)
111 ret = DRM_READ32(dev_priv->mmio, addr);
112 else {
113 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
114 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
115 }
116
117 return ret;
118}
119
120static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
121{
122 u32 ret;
123 RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
124 ret = RADEON_READ(R520_MC_IND_DATA);
125 RADEON_WRITE(R520_MC_IND_INDEX, 0);
126 return ret;
127}
128
129static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
130{
131 u32 ret;
132 RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
133 ret = RADEON_READ(RS480_NB_MC_DATA);
134 RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
135 return ret;
136}
137
138static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
139{
140 u32 ret;
141 RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
142 ret = RADEON_READ(RS690_MC_DATA);
143 RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
144 return ret;
145}
146
147static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
148{
149 u32 ret;
150 RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
151 RS600_MC_IND_CITF_ARB0));
152 ret = RADEON_READ(RS600_MC_DATA);
153 return ret;
154}
155
156static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
157{
158 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
159 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
160 return RS690_READ_MCIND(dev_priv, addr);
161 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
162 return RS600_READ_MCIND(dev_priv, addr);
163 else
164 return RS480_READ_MCIND(dev_priv, addr);
165}
166
167u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
168{
169
170 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
171 return RADEON_READ(R700_MC_VM_FB_LOCATION);
172 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
173 return RADEON_READ(R600_MC_VM_FB_LOCATION);
174 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
175 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
176 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
177 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
178 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
179 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
180 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
181 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
182 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
183 else
184 return RADEON_READ(RADEON_MC_FB_LOCATION);
185}
186
187static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
188{
189 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
190 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
191 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
192 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
193 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
194 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
195 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
196 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
197 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
198 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
199 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
200 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
201 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
202 else
203 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
204}
205
206void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
207{
208 /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
209 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
210 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
211 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
212 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
213 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
214 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
215 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
216 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
217 else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
218 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
219 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
220 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
221 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
222 else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
223 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
224 else
225 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
226}
227
228void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
229{
230 u32 agp_base_hi = upper_32_bits(agp_base);
231 u32 agp_base_lo = agp_base & 0xffffffff;
232 u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
233
234 /* R6xx/R7xx must be aligned to a 4MB boundry */
235 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
236 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
237 else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
238 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
239 else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
240 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
241 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
242 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
243 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
244 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
245 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
246 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
247 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
248 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
249 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
250 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
251 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
252 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
253 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
254 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
255 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
256 } else {
257 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
258 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
259 RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
260 }
261}
262
263void radeon_enable_bm(struct drm_radeon_private *dev_priv)
264{
265 u32 tmp;
266 /* Turn on bus mastering */
267 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
268 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
269 /* rs600/rs690/rs740 */
270 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
271 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
272 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
273 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
274 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
275 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
276 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
277 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
278 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
279 } /* PCIE cards appears to not need this */
280}
281
282static int RADEON_READ_PLL(struct drm_device * dev, int addr)
283{
284 drm_radeon_private_t *dev_priv = dev->dev_private;
285
286 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
287 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
288}
289
290static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
291{
292 RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
293 return RADEON_READ(RADEON_PCIE_DATA);
294}
295
296#if RADEON_FIFO_DEBUG
297static void radeon_status(drm_radeon_private_t * dev_priv)
298{
299 printk("%s:\n", __func__);
300 printk("RBBM_STATUS = 0x%08x\n",
301 (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
302 printk("CP_RB_RTPR = 0x%08x\n",
303 (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
304 printk("CP_RB_WTPR = 0x%08x\n",
305 (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
306 printk("AIC_CNTL = 0x%08x\n",
307 (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
308 printk("AIC_STAT = 0x%08x\n",
309 (unsigned int)RADEON_READ(RADEON_AIC_STAT));
310 printk("AIC_PT_BASE = 0x%08x\n",
311 (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
312 printk("TLB_ADDR = 0x%08x\n",
313 (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
314 printk("TLB_DATA = 0x%08x\n",
315 (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
316}
317#endif
318
319/* ================================================================
320 * Engine, FIFO control
321 */
322
323static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
324{
325 u32 tmp;
326 int i;
327
328 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
329
330 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
331 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
332 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
333 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
334
335 for (i = 0; i < dev_priv->usec_timeout; i++) {
336 if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
337 & RADEON_RB3D_DC_BUSY)) {
338 return 0;
339 }
340 DRM_UDELAY(1);
341 }
342 } else {
343 /* don't flush or purge cache here or lockup */
344 return 0;
345 }
346
347#if RADEON_FIFO_DEBUG
348 DRM_ERROR("failed!\n");
349 radeon_status(dev_priv);
350#endif
351 return -EBUSY;
352}
353
354static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
355{
356 int i;
357
358 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
359
360 for (i = 0; i < dev_priv->usec_timeout; i++) {
361 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
362 & RADEON_RBBM_FIFOCNT_MASK);
363 if (slots >= entries)
364 return 0;
365 DRM_UDELAY(1);
366 }
367 DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
368 RADEON_READ(RADEON_RBBM_STATUS),
369 RADEON_READ(R300_VAP_CNTL_STATUS));
370
371#if RADEON_FIFO_DEBUG
372 DRM_ERROR("failed!\n");
373 radeon_status(dev_priv);
374#endif
375 return -EBUSY;
376}
377
378static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
379{
380 int i, ret;
381
382 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
383
384 ret = radeon_do_wait_for_fifo(dev_priv, 64);
385 if (ret)
386 return ret;
387
388 for (i = 0; i < dev_priv->usec_timeout; i++) {
389 if (!(RADEON_READ(RADEON_RBBM_STATUS)
390 & RADEON_RBBM_ACTIVE)) {
391 radeon_do_pixcache_flush(dev_priv);
392 return 0;
393 }
394 DRM_UDELAY(1);
395 }
396 DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
397 RADEON_READ(RADEON_RBBM_STATUS),
398 RADEON_READ(R300_VAP_CNTL_STATUS));
399
400#if RADEON_FIFO_DEBUG
401 DRM_ERROR("failed!\n");
402 radeon_status(dev_priv);
403#endif
404 return -EBUSY;
405}
406
407static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
408{
409 uint32_t gb_tile_config, gb_pipe_sel = 0;
410
411 /* RS4xx/RS6xx/R4xx/R5xx */
412 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
413 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
414 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
415 } else {
416 /* R3xx */
417 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
418 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
419 dev_priv->num_gb_pipes = 2;
420 } else {
421 /* R3Vxx */
422 dev_priv->num_gb_pipes = 1;
423 }
424 }
425 DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
426
427 gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
428
429 switch (dev_priv->num_gb_pipes) {
430 case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
431 case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
432 case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
433 default:
434 case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
435 }
436
437 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
438 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
439 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
440 }
441 RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
442 radeon_do_wait_for_idle(dev_priv);
443 RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
444 RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
445 R300_DC_AUTOFLUSH_ENABLE |
446 R300_DC_DC_DISABLE_IGNORE_PE));
447
448
449}
450
451/* ================================================================
452 * CP control, initialization
453 */
454
455/* Load the microcode for the CP */
456static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
457{
458 const u32 (*cp)[2];
459 int i;
460
461 DRM_DEBUG("\n");
462
463 radeon_do_wait_for_idle(dev_priv);
464
465 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
466 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
467 case CHIP_R100:
468 case CHIP_RV100:
469 case CHIP_RV200:
470 case CHIP_RS100:
471 case CHIP_RS200:
472 DRM_INFO("Loading R100 Microcode\n");
473 cp = R100_cp_microcode;
474 break;
475 case CHIP_R200:
476 case CHIP_RV250:
477 case CHIP_RV280:
478 case CHIP_RS300:
479 DRM_INFO("Loading R200 Microcode\n");
480 cp = R200_cp_microcode;
481 break;
482 case CHIP_R300:
483 case CHIP_R350:
484 case CHIP_RV350:
485 case CHIP_RV380:
486 case CHIP_RS400:
487 case CHIP_RS480:
488 DRM_INFO("Loading R300 Microcode\n");
489 cp = R300_cp_microcode;
490 break;
491 case CHIP_R420:
492 case CHIP_R423:
493 case CHIP_RV410:
494 DRM_INFO("Loading R400 Microcode\n");
495 cp = R420_cp_microcode;
496 break;
497 case CHIP_RS690:
498 case CHIP_RS740:
499 DRM_INFO("Loading RS690/RS740 Microcode\n");
500 cp = RS690_cp_microcode;
501 break;
502 case CHIP_RS600:
503 DRM_INFO("Loading RS600 Microcode\n");
504 cp = RS600_cp_microcode;
505 break;
506 case CHIP_RV515:
507 case CHIP_R520:
508 case CHIP_RV530:
509 case CHIP_R580:
510 case CHIP_RV560:
511 case CHIP_RV570:
512 DRM_INFO("Loading R500 Microcode\n");
513 cp = R520_cp_microcode;
514 break;
515 default:
516 return;
517 }
518
519 for (i = 0; i != 256; i++) {
520 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
521 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
522 }
523}
524
525/* Flush any pending commands to the CP. This should only be used just
526 * prior to a wait for idle, as it informs the engine that the command
527 * stream is ending.
528 */
529static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
530{
531 DRM_DEBUG("\n");
532#if 0
533 u32 tmp;
534
535 tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
536 RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
537#endif
538}
539
540/* Wait for the CP to go idle.
541 */
542int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
543{
544 RING_LOCALS;
545 DRM_DEBUG("\n");
546
547 BEGIN_RING(6);
548
549 RADEON_PURGE_CACHE();
550 RADEON_PURGE_ZCACHE();
551 RADEON_WAIT_UNTIL_IDLE();
552
553 ADVANCE_RING();
554 COMMIT_RING();
555
556 return radeon_do_wait_for_idle(dev_priv);
557}
558
559/* Start the Command Processor.
560 */
561static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
562{
563 RING_LOCALS;
564 DRM_DEBUG("\n");
565
566 radeon_do_wait_for_idle(dev_priv);
567
568 RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
569
570 dev_priv->cp_running = 1;
571
572 BEGIN_RING(8);
573 /* isync can only be written through cp on r5xx write it here */
574 OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
575 OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
576 RADEON_ISYNC_ANY3D_IDLE2D |
577 RADEON_ISYNC_WAIT_IDLEGUI |
578 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
579 RADEON_PURGE_CACHE();
580 RADEON_PURGE_ZCACHE();
581 RADEON_WAIT_UNTIL_IDLE();
582 ADVANCE_RING();
583 COMMIT_RING();
584
585 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
586}
587
588/* Reset the Command Processor. This will not flush any pending
589 * commands, so you must wait for the CP command stream to complete
590 * before calling this routine.
591 */
592static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
593{
594 u32 cur_read_ptr;
595 DRM_DEBUG("\n");
596
597 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
598 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
599 SET_RING_HEAD(dev_priv, cur_read_ptr);
600 dev_priv->ring.tail = cur_read_ptr;
601}
602
603/* Stop the Command Processor. This will not flush any pending
604 * commands, so you must flush the command stream and wait for the CP
605 * to go idle before calling this routine.
606 */
607static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
608{
609 DRM_DEBUG("\n");
610
611 RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
612
613 dev_priv->cp_running = 0;
614}
615
616/* Reset the engine. This will stop the CP if it is running.
617 */
618static int radeon_do_engine_reset(struct drm_device * dev)
619{
620 drm_radeon_private_t *dev_priv = dev->dev_private;
621 u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
622 DRM_DEBUG("\n");
623
624 radeon_do_pixcache_flush(dev_priv);
625
626 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
627 /* may need something similar for newer chips */
628 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
629 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
630
631 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
632 RADEON_FORCEON_MCLKA |
633 RADEON_FORCEON_MCLKB |
634 RADEON_FORCEON_YCLKA |
635 RADEON_FORCEON_YCLKB |
636 RADEON_FORCEON_MC |
637 RADEON_FORCEON_AIC));
638 }
639
640 rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
641
642 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
643 RADEON_SOFT_RESET_CP |
644 RADEON_SOFT_RESET_HI |
645 RADEON_SOFT_RESET_SE |
646 RADEON_SOFT_RESET_RE |
647 RADEON_SOFT_RESET_PP |
648 RADEON_SOFT_RESET_E2 |
649 RADEON_SOFT_RESET_RB));
650 RADEON_READ(RADEON_RBBM_SOFT_RESET);
651 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
652 ~(RADEON_SOFT_RESET_CP |
653 RADEON_SOFT_RESET_HI |
654 RADEON_SOFT_RESET_SE |
655 RADEON_SOFT_RESET_RE |
656 RADEON_SOFT_RESET_PP |
657 RADEON_SOFT_RESET_E2 |
658 RADEON_SOFT_RESET_RB)));
659 RADEON_READ(RADEON_RBBM_SOFT_RESET);
660
661 if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
662 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
663 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
664 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
665 }
666
667 /* setup the raster pipes */
668 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
669 radeon_init_pipes(dev_priv);
670
671 /* Reset the CP ring */
672 radeon_do_cp_reset(dev_priv);
673
674 /* The CP is no longer running after an engine reset */
675 dev_priv->cp_running = 0;
676
677 /* Reset any pending vertex, indirect buffers */
678 radeon_freelist_reset(dev);
679
680 return 0;
681}
682
683static void radeon_cp_init_ring_buffer(struct drm_device * dev,
684 drm_radeon_private_t *dev_priv,
685 struct drm_file *file_priv)
686{
687 u32 ring_start, cur_read_ptr;
688
689 /* Initialize the memory controller. With new memory map, the fb location
690 * is not changed, it should have been properly initialized already. Part
691 * of the problem is that the code below is bogus, assuming the GART is
692 * always appended to the fb which is not necessarily the case
693 */
694 if (!dev_priv->new_memmap)
695 radeon_write_fb_location(dev_priv,
696 ((dev_priv->gart_vm_start - 1) & 0xffff0000)
697 | (dev_priv->fb_location >> 16));
698
699#if __OS_HAS_AGP
700 if (dev_priv->flags & RADEON_IS_AGP) {
701 radeon_write_agp_base(dev_priv, dev->agp->base);
702
703 radeon_write_agp_location(dev_priv,
704 (((dev_priv->gart_vm_start - 1 +
705 dev_priv->gart_size) & 0xffff0000) |
706 (dev_priv->gart_vm_start >> 16)));
707
708 ring_start = (dev_priv->cp_ring->offset
709 - dev->agp->base
710 + dev_priv->gart_vm_start);
711 } else
712#endif
713 ring_start = (dev_priv->cp_ring->offset
714 - (unsigned long)dev->sg->virtual
715 + dev_priv->gart_vm_start);
716
717 RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
718
719 /* Set the write pointer delay */
720 RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
721
722 /* Initialize the ring buffer's read and write pointers */
723 cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
724 RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
725 SET_RING_HEAD(dev_priv, cur_read_ptr);
726 dev_priv->ring.tail = cur_read_ptr;
727
728#if __OS_HAS_AGP
729 if (dev_priv->flags & RADEON_IS_AGP) {
730 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
731 dev_priv->ring_rptr->offset
732 - dev->agp->base + dev_priv->gart_vm_start);
733 } else
734#endif
735 {
736 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
737 dev_priv->ring_rptr->offset
738 - ((unsigned long) dev->sg->virtual)
739 + dev_priv->gart_vm_start);
740 }
741
742 /* Set ring buffer size */
743#ifdef __BIG_ENDIAN
744 RADEON_WRITE(RADEON_CP_RB_CNTL,
745 RADEON_BUF_SWAP_32BIT |
746 (dev_priv->ring.fetch_size_l2ow << 18) |
747 (dev_priv->ring.rptr_update_l2qw << 8) |
748 dev_priv->ring.size_l2qw);
749#else
750 RADEON_WRITE(RADEON_CP_RB_CNTL,
751 (dev_priv->ring.fetch_size_l2ow << 18) |
752 (dev_priv->ring.rptr_update_l2qw << 8) |
753 dev_priv->ring.size_l2qw);
754#endif
755
756
757 /* Initialize the scratch register pointer. This will cause
758 * the scratch register values to be written out to memory
759 * whenever they are updated.
760 *
761 * We simply put this behind the ring read pointer, this works
762 * with PCI GART as well as (whatever kind of) AGP GART
763 */
764 RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
765 + RADEON_SCRATCH_REG_OFFSET);
766
767 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
768
769 radeon_enable_bm(dev_priv);
770
771 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
772 RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
773
774 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
775 RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
776
777 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
778 RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
779
780 /* reset sarea copies of these */
781 if (dev_priv->sarea_priv) {
782 dev_priv->sarea_priv->last_frame = 0;
783 dev_priv->sarea_priv->last_dispatch = 0;
784 dev_priv->sarea_priv->last_clear = 0;
785 }
786
787 radeon_do_wait_for_idle(dev_priv);
788
789 /* Sync everything up */
790 RADEON_WRITE(RADEON_ISYNC_CNTL,
791 (RADEON_ISYNC_ANY2D_IDLE3D |
792 RADEON_ISYNC_ANY3D_IDLE2D |
793 RADEON_ISYNC_WAIT_IDLEGUI |
794 RADEON_ISYNC_CPSCRATCH_IDLEGUI));
795
796}
797
798static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
799{
800 u32 tmp;
801
802 /* Start with assuming that writeback doesn't work */
803 dev_priv->writeback_works = 0;
804
805 /* Writeback doesn't seem to work everywhere, test it here and possibly
806 * enable it if it appears to work
807 */
808 radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
809
810 RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
811
812 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
813 u32 val;
814
815 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
816 if (val == 0xdeadbeef)
817 break;
818 DRM_UDELAY(1);
819 }
820
821 if (tmp < dev_priv->usec_timeout) {
822 dev_priv->writeback_works = 1;
823 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
824 } else {
825 dev_priv->writeback_works = 0;
826 DRM_INFO("writeback test failed\n");
827 }
828 if (radeon_no_wb == 1) {
829 dev_priv->writeback_works = 0;
830 DRM_INFO("writeback forced off\n");
831 }
832
833 if (!dev_priv->writeback_works) {
834 /* Disable writeback to avoid unnecessary bus master transfer */
835 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
836 RADEON_RB_NO_UPDATE);
837 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
838 }
839}
840
841/* Enable or disable IGP GART on the chip */
842static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
843{
844 u32 temp;
845
846 if (on) {
847 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
848 dev_priv->gart_vm_start,
849 (long)dev_priv->gart_info.bus_addr,
850 dev_priv->gart_size);
851
852 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
853 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
854 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
855 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
856 RS690_BLOCK_GFX_D3_EN));
857 else
858 IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
859
860 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
861 RS480_VA_SIZE_32MB));
862
863 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
864 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
865 RS480_TLB_ENABLE |
866 RS480_GTW_LAC_EN |
867 RS480_1LEVEL_GART));
868
869 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
870 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
871 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
872
873 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
874 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
875 RS480_REQ_TYPE_SNOOP_DIS));
876
877 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
878
879 dev_priv->gart_size = 32*1024*1024;
880 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
881 0xffff0000) | (dev_priv->gart_vm_start >> 16));
882
883 radeon_write_agp_location(dev_priv, temp);
884
885 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
886 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
887 RS480_VA_SIZE_32MB));
888
889 do {
890 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
891 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
892 break;
893 DRM_UDELAY(1);
894 } while (1);
895
896 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
897 RS480_GART_CACHE_INVALIDATE);
898
899 do {
900 temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
901 if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
902 break;
903 DRM_UDELAY(1);
904 } while (1);
905
906 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
907 } else {
908 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
909 }
910}
911
912/* Enable or disable IGP GART on the chip */
913static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
914{
915 u32 temp;
916 int i;
917
918 if (on) {
919 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
920 dev_priv->gart_vm_start,
921 (long)dev_priv->gart_info.bus_addr,
922 dev_priv->gart_size);
923
924 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
925 RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
926
927 for (i = 0; i < 19; i++)
928 IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
929 (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
930 RS600_SYSTEM_ACCESS_MODE_IN_SYS |
931 RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
932 RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
933 RS600_ENABLE_FRAGMENT_PROCESSING |
934 RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
935
936 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
937 RS600_PAGE_TABLE_TYPE_FLAT));
938
939 /* disable all other contexts */
940 for (i = 1; i < 8; i++)
941 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
942
943 /* setup the page table aperture */
944 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
945 dev_priv->gart_info.bus_addr);
946 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
947 dev_priv->gart_vm_start);
948 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
949 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
950 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
951
952 /* setup the system aperture */
953 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
954 dev_priv->gart_vm_start);
955 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
956 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
957
958 /* enable page tables */
959 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
960 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
961
962 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
963 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
964
965 /* invalidate the cache */
966 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
967
968 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
969 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
970 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
971
972 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
973 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
974 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
975
976 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
977 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
978 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
979
980 } else {
981 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
982 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
983 temp &= ~RS600_ENABLE_PAGE_TABLES;
984 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
985 }
986}
987
988static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
989{
990 u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
991 if (on) {
992
993 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
994 dev_priv->gart_vm_start,
995 (long)dev_priv->gart_info.bus_addr,
996 dev_priv->gart_size);
997 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
998 dev_priv->gart_vm_start);
999 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1000 dev_priv->gart_info.bus_addr);
1001 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1002 dev_priv->gart_vm_start);
1003 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1004 dev_priv->gart_vm_start +
1005 dev_priv->gart_size - 1);
1006
1007 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1008
1009 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1010 RADEON_PCIE_TX_GART_EN);
1011 } else {
1012 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1013 tmp & ~RADEON_PCIE_TX_GART_EN);
1014 }
1015}
1016
1017/* Enable or disable PCI GART on the chip */
1018static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1019{
1020 u32 tmp;
1021
1022 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1023 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1024 (dev_priv->flags & RADEON_IS_IGPGART)) {
1025 radeon_set_igpgart(dev_priv, on);
1026 return;
1027 }
1028
1029 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1030 rs600_set_igpgart(dev_priv, on);
1031 return;
1032 }
1033
1034 if (dev_priv->flags & RADEON_IS_PCIE) {
1035 radeon_set_pciegart(dev_priv, on);
1036 return;
1037 }
1038
1039 tmp = RADEON_READ(RADEON_AIC_CNTL);
1040
1041 if (on) {
1042 RADEON_WRITE(RADEON_AIC_CNTL,
1043 tmp | RADEON_PCIGART_TRANSLATE_EN);
1044
1045 /* set PCI GART page-table base address
1046 */
1047 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1048
1049 /* set address range for PCI address translate
1050 */
1051 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1052 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1053 + dev_priv->gart_size - 1);
1054
1055 /* Turn off AGP aperture -- is this required for PCI GART?
1056 */
1057 radeon_write_agp_location(dev_priv, 0xffffffc0);
1058 RADEON_WRITE(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */
1059 } else {
1060 RADEON_WRITE(RADEON_AIC_CNTL,
1061 tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1062 }
1063}
1064
1065static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1066{
1067 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1068 struct radeon_virt_surface *vp;
1069 int i;
1070
1071 for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1072 if (!dev_priv->virt_surfaces[i].file_priv ||
1073 dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1074 break;
1075 }
1076 if (i >= 2 * RADEON_MAX_SURFACES)
1077 return -ENOMEM;
1078 vp = &dev_priv->virt_surfaces[i];
1079
1080 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1081 struct radeon_surface *sp = &dev_priv->surfaces[i];
1082 if (sp->refcount)
1083 continue;
1084
1085 vp->surface_index = i;
1086 vp->lower = gart_info->bus_addr;
1087 vp->upper = vp->lower + gart_info->table_size;
1088 vp->flags = 0;
1089 vp->file_priv = PCIGART_FILE_PRIV;
1090
1091 sp->refcount = 1;
1092 sp->lower = vp->lower;
1093 sp->upper = vp->upper;
1094 sp->flags = 0;
1095
1096 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1097 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1098 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1099 return 0;
1100 }
1101
1102 return -ENOMEM;
1103}
1104
1105static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1106 struct drm_file *file_priv)
1107{
1108 drm_radeon_private_t *dev_priv = dev->dev_private;
1109
1110 DRM_DEBUG("\n");
1111
1112 /* if we require new memory map but we don't have it fail */
1113 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1114 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1115 radeon_do_cleanup_cp(dev);
1116 return -EINVAL;
1117 }
1118
1119 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1120 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1121 dev_priv->flags &= ~RADEON_IS_AGP;
1122 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1123 && !init->is_pci) {
1124 DRM_DEBUG("Restoring AGP flag\n");
1125 dev_priv->flags |= RADEON_IS_AGP;
1126 }
1127
1128 if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1129 DRM_ERROR("PCI GART memory not allocated!\n");
1130 radeon_do_cleanup_cp(dev);
1131 return -EINVAL;
1132 }
1133
1134 dev_priv->usec_timeout = init->usec_timeout;
1135 if (dev_priv->usec_timeout < 1 ||
1136 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1137 DRM_DEBUG("TIMEOUT problem!\n");
1138 radeon_do_cleanup_cp(dev);
1139 return -EINVAL;
1140 }
1141
1142 /* Enable vblank on CRTC1 for older X servers
1143 */
1144 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1145
1146 switch(init->func) {
1147 case RADEON_INIT_R200_CP:
1148 dev_priv->microcode_version = UCODE_R200;
1149 break;
1150 case RADEON_INIT_R300_CP:
1151 dev_priv->microcode_version = UCODE_R300;
1152 break;
1153 default:
1154 dev_priv->microcode_version = UCODE_R100;
1155 }
1156
1157 dev_priv->do_boxes = 0;
1158 dev_priv->cp_mode = init->cp_mode;
1159
1160 /* We don't support anything other than bus-mastering ring mode,
1161 * but the ring can be in either AGP or PCI space for the ring
1162 * read pointer.
1163 */
1164 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1165 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1166 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1167 radeon_do_cleanup_cp(dev);
1168 return -EINVAL;
1169 }
1170
1171 switch (init->fb_bpp) {
1172 case 16:
1173 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1174 break;
1175 case 32:
1176 default:
1177 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1178 break;
1179 }
1180 dev_priv->front_offset = init->front_offset;
1181 dev_priv->front_pitch = init->front_pitch;
1182 dev_priv->back_offset = init->back_offset;
1183 dev_priv->back_pitch = init->back_pitch;
1184
1185 switch (init->depth_bpp) {
1186 case 16:
1187 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1188 break;
1189 case 32:
1190 default:
1191 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1192 break;
1193 }
1194 dev_priv->depth_offset = init->depth_offset;
1195 dev_priv->depth_pitch = init->depth_pitch;
1196
1197 /* Hardware state for depth clears. Remove this if/when we no
1198 * longer clear the depth buffer with a 3D rectangle. Hard-code
1199 * all values to prevent unwanted 3D state from slipping through
1200 * and screwing with the clear operation.
1201 */
1202 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1203 (dev_priv->color_fmt << 10) |
1204 (dev_priv->microcode_version ==
1205 UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1206
1207 dev_priv->depth_clear.rb3d_zstencilcntl =
1208 (dev_priv->depth_fmt |
1209 RADEON_Z_TEST_ALWAYS |
1210 RADEON_STENCIL_TEST_ALWAYS |
1211 RADEON_STENCIL_S_FAIL_REPLACE |
1212 RADEON_STENCIL_ZPASS_REPLACE |
1213 RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1214
1215 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1216 RADEON_BFACE_SOLID |
1217 RADEON_FFACE_SOLID |
1218 RADEON_FLAT_SHADE_VTX_LAST |
1219 RADEON_DIFFUSE_SHADE_FLAT |
1220 RADEON_ALPHA_SHADE_FLAT |
1221 RADEON_SPECULAR_SHADE_FLAT |
1222 RADEON_FOG_SHADE_FLAT |
1223 RADEON_VTX_PIX_CENTER_OGL |
1224 RADEON_ROUND_MODE_TRUNC |
1225 RADEON_ROUND_PREC_8TH_PIX);
1226
1227
1228 dev_priv->ring_offset = init->ring_offset;
1229 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1230 dev_priv->buffers_offset = init->buffers_offset;
1231 dev_priv->gart_textures_offset = init->gart_textures_offset;
1232
1233 dev_priv->sarea = drm_getsarea(dev);
1234 if (!dev_priv->sarea) {
1235 DRM_ERROR("could not find sarea!\n");
1236 radeon_do_cleanup_cp(dev);
1237 return -EINVAL;
1238 }
1239
1240 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1241 if (!dev_priv->cp_ring) {
1242 DRM_ERROR("could not find cp ring region!\n");
1243 radeon_do_cleanup_cp(dev);
1244 return -EINVAL;
1245 }
1246 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1247 if (!dev_priv->ring_rptr) {
1248 DRM_ERROR("could not find ring read pointer!\n");
1249 radeon_do_cleanup_cp(dev);
1250 return -EINVAL;
1251 }
1252 dev->agp_buffer_token = init->buffers_offset;
1253 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1254 if (!dev->agp_buffer_map) {
1255 DRM_ERROR("could not find dma buffer region!\n");
1256 radeon_do_cleanup_cp(dev);
1257 return -EINVAL;
1258 }
1259
1260 if (init->gart_textures_offset) {
1261 dev_priv->gart_textures =
1262 drm_core_findmap(dev, init->gart_textures_offset);
1263 if (!dev_priv->gart_textures) {
1264 DRM_ERROR("could not find GART texture region!\n");
1265 radeon_do_cleanup_cp(dev);
1266 return -EINVAL;
1267 }
1268 }
1269
1270 dev_priv->sarea_priv =
1271 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1272 init->sarea_priv_offset);
1273
1274#if __OS_HAS_AGP
1275 if (dev_priv->flags & RADEON_IS_AGP) {
1276 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1277 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1278 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1279 if (!dev_priv->cp_ring->handle ||
1280 !dev_priv->ring_rptr->handle ||
1281 !dev->agp_buffer_map->handle) {
1282 DRM_ERROR("could not find ioremap agp regions!\n");
1283 radeon_do_cleanup_cp(dev);
1284 return -EINVAL;
1285 }
1286 } else
1287#endif
1288 {
1289 dev_priv->cp_ring->handle =
1290 (void *)(unsigned long)dev_priv->cp_ring->offset;
1291 dev_priv->ring_rptr->handle =
1292 (void *)(unsigned long)dev_priv->ring_rptr->offset;
1293 dev->agp_buffer_map->handle =
1294 (void *)(unsigned long)dev->agp_buffer_map->offset;
1295
1296 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1297 dev_priv->cp_ring->handle);
1298 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1299 dev_priv->ring_rptr->handle);
1300 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1301 dev->agp_buffer_map->handle);
1302 }
1303
1304 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1305 dev_priv->fb_size =
1306 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1307 - dev_priv->fb_location;
1308
1309 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1310 ((dev_priv->front_offset
1311 + dev_priv->fb_location) >> 10));
1312
1313 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1314 ((dev_priv->back_offset
1315 + dev_priv->fb_location) >> 10));
1316
1317 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1318 ((dev_priv->depth_offset
1319 + dev_priv->fb_location) >> 10));
1320
1321 dev_priv->gart_size = init->gart_size;
1322
1323 /* New let's set the memory map ... */
1324 if (dev_priv->new_memmap) {
1325 u32 base = 0;
1326
1327 DRM_INFO("Setting GART location based on new memory map\n");
1328
1329 /* If using AGP, try to locate the AGP aperture at the same
1330 * location in the card and on the bus, though we have to
1331 * align it down.
1332 */
1333#if __OS_HAS_AGP
1334 if (dev_priv->flags & RADEON_IS_AGP) {
1335 base = dev->agp->base;
1336 /* Check if valid */
1337 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1338 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1339 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1340 dev->agp->base);
1341 base = 0;
1342 }
1343 }
1344#endif
1345 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1346 if (base == 0) {
1347 base = dev_priv->fb_location + dev_priv->fb_size;
1348 if (base < dev_priv->fb_location ||
1349 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1350 base = dev_priv->fb_location
1351 - dev_priv->gart_size;
1352 }
1353 dev_priv->gart_vm_start = base & 0xffc00000u;
1354 if (dev_priv->gart_vm_start != base)
1355 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1356 base, dev_priv->gart_vm_start);
1357 } else {
1358 DRM_INFO("Setting GART location based on old memory map\n");
1359 dev_priv->gart_vm_start = dev_priv->fb_location +
1360 RADEON_READ(RADEON_CONFIG_APER_SIZE);
1361 }
1362
1363#if __OS_HAS_AGP
1364 if (dev_priv->flags & RADEON_IS_AGP)
1365 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1366 - dev->agp->base
1367 + dev_priv->gart_vm_start);
1368 else
1369#endif
1370 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1371 - (unsigned long)dev->sg->virtual
1372 + dev_priv->gart_vm_start);
1373
1374 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1375 DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1376 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1377 dev_priv->gart_buffers_offset);
1378
1379 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1380 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1381 + init->ring_size / sizeof(u32));
1382 dev_priv->ring.size = init->ring_size;
1383 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1384
1385 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1386 dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1387
1388 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1389 dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1390 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1391
1392 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1393
1394#if __OS_HAS_AGP
1395 if (dev_priv->flags & RADEON_IS_AGP) {
1396 /* Turn off PCI GART */
1397 radeon_set_pcigart(dev_priv, 0);
1398 } else
1399#endif
1400 {
1401 u32 sctrl;
1402 int ret;
1403
1404 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1405 /* if we have an offset set from userspace */
1406 if (dev_priv->pcigart_offset_set) {
1407 dev_priv->gart_info.bus_addr =
1408 dev_priv->pcigart_offset + dev_priv->fb_location;
1409 dev_priv->gart_info.mapping.offset =
1410 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1411 dev_priv->gart_info.mapping.size =
1412 dev_priv->gart_info.table_size;
1413
1414 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1415 dev_priv->gart_info.addr =
1416 dev_priv->gart_info.mapping.handle;
1417
1418 if (dev_priv->flags & RADEON_IS_PCIE)
1419 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1420 else
1421 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1422 dev_priv->gart_info.gart_table_location =
1423 DRM_ATI_GART_FB;
1424
1425 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1426 dev_priv->gart_info.addr,
1427 dev_priv->pcigart_offset);
1428 } else {
1429 if (dev_priv->flags & RADEON_IS_IGPGART)
1430 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1431 else
1432 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1433 dev_priv->gart_info.gart_table_location =
1434 DRM_ATI_GART_MAIN;
1435 dev_priv->gart_info.addr = NULL;
1436 dev_priv->gart_info.bus_addr = 0;
1437 if (dev_priv->flags & RADEON_IS_PCIE) {
1438 DRM_ERROR
1439 ("Cannot use PCI Express without GART in FB memory\n");
1440 radeon_do_cleanup_cp(dev);
1441 return -EINVAL;
1442 }
1443 }
1444
1445 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1446 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1447 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1448 ret = r600_page_table_init(dev);
1449 else
1450 ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1451 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1452
1453 if (!ret) {
1454 DRM_ERROR("failed to init PCI GART!\n");
1455 radeon_do_cleanup_cp(dev);
1456 return -ENOMEM;
1457 }
1458
1459 ret = radeon_setup_pcigart_surface(dev_priv);
1460 if (ret) {
1461 DRM_ERROR("failed to setup GART surface!\n");
1462 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1463 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1464 else
1465 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1466 radeon_do_cleanup_cp(dev);
1467 return ret;
1468 }
1469
1470 /* Turn on PCI GART */
1471 radeon_set_pcigart(dev_priv, 1);
1472 }
1473
1474 radeon_cp_load_microcode(dev_priv);
1475 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1476
1477 dev_priv->last_buf = 0;
1478
1479 radeon_do_engine_reset(dev);
1480 radeon_test_writeback(dev_priv);
1481
1482 return 0;
1483}
1484
1485static int radeon_do_cleanup_cp(struct drm_device * dev)
1486{
1487 drm_radeon_private_t *dev_priv = dev->dev_private;
1488 DRM_DEBUG("\n");
1489
1490 /* Make sure interrupts are disabled here because the uninstall ioctl
1491 * may not have been called from userspace and after dev_private
1492 * is freed, it's too late.
1493 */
1494 if (dev->irq_enabled)
1495 drm_irq_uninstall(dev);
1496
1497#if __OS_HAS_AGP
1498 if (dev_priv->flags & RADEON_IS_AGP) {
1499 if (dev_priv->cp_ring != NULL) {
1500 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1501 dev_priv->cp_ring = NULL;
1502 }
1503 if (dev_priv->ring_rptr != NULL) {
1504 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1505 dev_priv->ring_rptr = NULL;
1506 }
1507 if (dev->agp_buffer_map != NULL) {
1508 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1509 dev->agp_buffer_map = NULL;
1510 }
1511 } else
1512#endif
1513 {
1514
1515 if (dev_priv->gart_info.bus_addr) {
1516 /* Turn off PCI GART */
1517 radeon_set_pcigart(dev_priv, 0);
1518 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1519 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1520 else {
1521 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1522 DRM_ERROR("failed to cleanup PCI GART!\n");
1523 }
1524 }
1525
1526 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1527 {
1528 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1529 dev_priv->gart_info.addr = 0;
1530 }
1531 }
1532 /* only clear to the start of flags */
1533 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1534
1535 return 0;
1536}
1537
1538/* This code will reinit the Radeon CP hardware after a resume from disc.
1539 * AFAIK, it would be very difficult to pickle the state at suspend time, so
1540 * here we make sure that all Radeon hardware initialisation is re-done without
1541 * affecting running applications.
1542 *
1543 * Charl P. Botha <http://cpbotha.net>
1544 */
1545static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1546{
1547 drm_radeon_private_t *dev_priv = dev->dev_private;
1548
1549 if (!dev_priv) {
1550 DRM_ERROR("Called with no initialization\n");
1551 return -EINVAL;
1552 }
1553
1554 DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1555
1556#if __OS_HAS_AGP
1557 if (dev_priv->flags & RADEON_IS_AGP) {
1558 /* Turn off PCI GART */
1559 radeon_set_pcigart(dev_priv, 0);
1560 } else
1561#endif
1562 {
1563 /* Turn on PCI GART */
1564 radeon_set_pcigart(dev_priv, 1);
1565 }
1566
1567 radeon_cp_load_microcode(dev_priv);
1568 radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1569
1570 radeon_do_engine_reset(dev);
1571 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1572
1573 DRM_DEBUG("radeon_do_resume_cp() complete\n");
1574
1575 return 0;
1576}
1577
1578int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1579{
1580 drm_radeon_private_t *dev_priv = dev->dev_private;
1581 drm_radeon_init_t *init = data;
1582
1583 LOCK_TEST_WITH_RETURN(dev, file_priv);
1584
1585 if (init->func == RADEON_INIT_R300_CP)
1586 r300_init_reg_flags(dev);
1587
1588 switch (init->func) {
1589 case RADEON_INIT_CP:
1590 case RADEON_INIT_R200_CP:
1591 case RADEON_INIT_R300_CP:
1592 return radeon_do_init_cp(dev, init, file_priv);
1593 case RADEON_INIT_R600_CP:
1594 return r600_do_init_cp(dev, init, file_priv);
1595 case RADEON_CLEANUP_CP:
1596 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1597 return r600_do_cleanup_cp(dev);
1598 else
1599 return radeon_do_cleanup_cp(dev);
1600 }
1601
1602 return -EINVAL;
1603}
1604
1605int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1606{
1607 drm_radeon_private_t *dev_priv = dev->dev_private;
1608 DRM_DEBUG("\n");
1609
1610 LOCK_TEST_WITH_RETURN(dev, file_priv);
1611
1612 if (dev_priv->cp_running) {
1613 DRM_DEBUG("while CP running\n");
1614 return 0;
1615 }
1616 if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1617 DRM_DEBUG("called with bogus CP mode (%d)\n",
1618 dev_priv->cp_mode);
1619 return 0;
1620 }
1621
1622 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1623 r600_do_cp_start(dev_priv);
1624 else
1625 radeon_do_cp_start(dev_priv);
1626
1627 return 0;
1628}
1629
1630/* Stop the CP. The engine must have been idled before calling this
1631 * routine.
1632 */
1633int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1634{
1635 drm_radeon_private_t *dev_priv = dev->dev_private;
1636 drm_radeon_cp_stop_t *stop = data;
1637 int ret;
1638 DRM_DEBUG("\n");
1639
1640 LOCK_TEST_WITH_RETURN(dev, file_priv);
1641
1642 if (!dev_priv->cp_running)
1643 return 0;
1644
1645 /* Flush any pending CP commands. This ensures any outstanding
1646 * commands are exectuted by the engine before we turn it off.
1647 */
1648 if (stop->flush) {
1649 radeon_do_cp_flush(dev_priv);
1650 }
1651
1652 /* If we fail to make the engine go idle, we return an error
1653 * code so that the DRM ioctl wrapper can try again.
1654 */
1655 if (stop->idle) {
1656 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1657 ret = r600_do_cp_idle(dev_priv);
1658 else
1659 ret = radeon_do_cp_idle(dev_priv);
1660 if (ret)
1661 return ret;
1662 }
1663
1664 /* Finally, we can turn off the CP. If the engine isn't idle,
1665 * we will get some dropped triangles as they won't be fully
1666 * rendered before the CP is shut down.
1667 */
1668 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1669 r600_do_cp_stop(dev_priv);
1670 else
1671 radeon_do_cp_stop(dev_priv);
1672
1673 /* Reset the engine */
1674 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1675 r600_do_engine_reset(dev);
1676 else
1677 radeon_do_engine_reset(dev);
1678
1679 return 0;
1680}
1681
1682void radeon_do_release(struct drm_device * dev)
1683{
1684 drm_radeon_private_t *dev_priv = dev->dev_private;
1685 int i, ret;
1686
1687 if (dev_priv) {
1688 if (dev_priv->cp_running) {
1689 /* Stop the cp */
1690 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1691 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1692 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1693 mtx_sleep(&ret, &dev->dev_lock, 0,
1694 "rdnrel", 1);
1695 }
1696 } else {
1697 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1698 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1699 mtx_sleep(&ret, &dev->dev_lock, 0,
1700 "rdnrel", 1);
1701 }
1702 }
1703 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1704 r600_do_cp_stop(dev_priv);
1705 r600_do_engine_reset(dev);
1706 } else {
1707 radeon_do_cp_stop(dev_priv);
1708 radeon_do_engine_reset(dev);
1709 }
1710 }
1711
1712 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1713 /* Disable *all* interrupts */
1714 if (dev_priv->mmio) /* remove this after permanent addmaps */
1715 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1716
1717 if (dev_priv->mmio) { /* remove all surfaces */
1718 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1719 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1720 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1721 16 * i, 0);
1722 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1723 16 * i, 0);
1724 }
1725 }
1726 }
1727
1728 /* Free memory heap structures */
1729 radeon_mem_takedown(&(dev_priv->gart_heap));
1730 radeon_mem_takedown(&(dev_priv->fb_heap));
1731
1732 /* deallocate kernel resources */
1733 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1734 r600_do_cleanup_cp(dev);
1735 else
1736 radeon_do_cleanup_cp(dev);
1737 }
1738}
1739
1740/* Just reset the CP ring. Called as part of an X Server engine reset.
1741 */
1742int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1743{
1744 drm_radeon_private_t *dev_priv = dev->dev_private;
1745 DRM_DEBUG("\n");
1746
1747 LOCK_TEST_WITH_RETURN(dev, file_priv);
1748
1749 if (!dev_priv) {
1750 DRM_DEBUG("called before init done\n");
1751 return -EINVAL;
1752 }
1753
1754 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1755 r600_do_cp_reset(dev_priv);
1756 else
1757 radeon_do_cp_reset(dev_priv);
1758
1759 /* The CP is no longer running after an engine reset */
1760 dev_priv->cp_running = 0;
1761
1762 return 0;
1763}
1764
1765int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1766{
1767 drm_radeon_private_t *dev_priv = dev->dev_private;
1768 DRM_DEBUG("\n");
1769
1770 LOCK_TEST_WITH_RETURN(dev, file_priv);
1771
1772 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1773 return r600_do_cp_idle(dev_priv);
1774 else
1775 return radeon_do_cp_idle(dev_priv);
1776}
1777
1778/* Added by Charl P. Botha to call radeon_do_resume_cp().
1779 */
1780int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1781{
1782 drm_radeon_private_t *dev_priv = dev->dev_private;
1783 DRM_DEBUG("\n");
1784
1785 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1786 return r600_do_resume_cp(dev, file_priv);
1787 else
1788 return radeon_do_resume_cp(dev, file_priv);
1789}
1790
1791int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1792{
1793 drm_radeon_private_t *dev_priv = dev->dev_private;
1794 DRM_DEBUG("\n");
1795
1796 LOCK_TEST_WITH_RETURN(dev, file_priv);
1797
1798 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1799 return r600_do_engine_reset(dev);
1800 else
1801 return radeon_do_engine_reset(dev);
1802}
1803
1804/* ================================================================
1805 * Fullscreen mode
1806 */
1807
1808/* KW: Deprecated to say the least:
1809 */
1810int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1811{
1812 return 0;
1813}
1814
1815/* ================================================================
1816 * Freelist management
1817 */
1818
1819/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1820 * bufs until freelist code is used. Note this hides a problem with
1821 * the scratch register * (used to keep track of last buffer
1822 * completed) being written to before * the last buffer has actually
1823 * completed rendering.
1824 *
1825 * KW: It's also a good way to find free buffers quickly.
1826 *
1827 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1828 * sleep. However, bugs in older versions of radeon_accel.c mean that
1829 * we essentially have to do this, else old clients will break.
1830 *
1831 * However, it does leave open a potential deadlock where all the
1832 * buffers are held by other clients, which can't release them because
1833 * they can't get the lock.
1834 */
1835
1836struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1837{
1838 struct drm_device_dma *dma = dev->dma;
1839 drm_radeon_private_t *dev_priv = dev->dev_private;
1840 drm_radeon_buf_priv_t *buf_priv;
1841 struct drm_buf *buf;
1842 int i, t;
1843 int start;
1844
1845 if (++dev_priv->last_buf >= dma->buf_count)
1846 dev_priv->last_buf = 0;
1847
1848 start = dev_priv->last_buf;
1849
1850 for (t = 0; t < dev_priv->usec_timeout; t++) {
1851 u32 done_age = GET_SCRATCH(dev_priv, 1);
1852 DRM_DEBUG("done_age = %d\n", done_age);
1853 for (i = start; i < dma->buf_count; i++) {
1854 buf = dma->buflist[i];
1855 buf_priv = buf->dev_private;
1856 if (buf->file_priv == NULL || (buf->pending &&
1857 buf_priv->age <=
1858 done_age)) {
1859 dev_priv->stats.requested_bufs++;
1860 buf->pending = 0;
1861 return buf;
1862 }
1863 start = 0;
1864 }
1865
1866 if (t) {
1867 DRM_UDELAY(1);
1868 dev_priv->stats.freelist_loops++;
1869 }
1870 }
1871
1872 DRM_DEBUG("returning NULL!\n");
1873 return NULL;
1874}
1875
1876#if 0
1877struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1878{
1879 struct drm_device_dma *dma = dev->dma;
1880 drm_radeon_private_t *dev_priv = dev->dev_private;
1881 drm_radeon_buf_priv_t *buf_priv;
1882 struct drm_buf *buf;
1883 int i, t;
1884 int start;
1885 u32 done_age;
1886
1887 done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1888 if (++dev_priv->last_buf >= dma->buf_count)
1889 dev_priv->last_buf = 0;
1890
1891 start = dev_priv->last_buf;
1892 dev_priv->stats.freelist_loops++;
1893
1894 for (t = 0; t < 2; t++) {
1895 for (i = start; i < dma->buf_count; i++) {
1896 buf = dma->buflist[i];
1897 buf_priv = buf->dev_private;
1898 if (buf->file_priv == 0 || (buf->pending &&
1899 buf_priv->age <=
1900 done_age)) {
1901 dev_priv->stats.requested_bufs++;
1902 buf->pending = 0;
1903 return buf;
1904 }
1905 }
1906 start = 0;
1907 }
1908
1909 return NULL;
1910}
1911#endif
1912
1913void radeon_freelist_reset(struct drm_device * dev)
1914{
1915 struct drm_device_dma *dma = dev->dma;
1916 drm_radeon_private_t *dev_priv = dev->dev_private;
1917 int i;
1918
1919 dev_priv->last_buf = 0;
1920 for (i = 0; i < dma->buf_count; i++) {
1921 struct drm_buf *buf = dma->buflist[i];
1922 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1923 buf_priv->age = 0;
1924 }
1925}
1926
1927/* ================================================================
1928 * CP command submission
1929 */
1930
1931int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1932{
1933 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1934 int i;
1935 u32 last_head = GET_RING_HEAD(dev_priv);
1936
1937 for (i = 0; i < dev_priv->usec_timeout; i++) {
1938 u32 head = GET_RING_HEAD(dev_priv);
1939
1940 ring->space = (head - ring->tail) * sizeof(u32);
1941 if (ring->space <= 0)
1942 ring->space += ring->size;
1943 if (ring->space > n)
1944 return 0;
1945
1946 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1947
1948 if (head != last_head)
1949 i = 0;
1950 last_head = head;
1951
1952 DRM_UDELAY(1);
1953 }
1954
1955 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1956#if RADEON_FIFO_DEBUG
1957 radeon_status(dev_priv);
1958 DRM_ERROR("failed!\n");
1959#endif
1960 return -EBUSY;
1961}
1962
1963static int radeon_cp_get_buffers(struct drm_device *dev,
1964 struct drm_file *file_priv,
1965 struct drm_dma * d)
1966{
1967 int i;
1968 struct drm_buf *buf;
1969
1970 for (i = d->granted_count; i < d->request_count; i++) {
1971 buf = radeon_freelist_get(dev);
1972 if (!buf)
1973 return -EBUSY; /* NOTE: broken client */
1974
1975 buf->file_priv = file_priv;
1976
1977 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1978 sizeof(buf->idx)))
1979 return -EFAULT;
1980 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1981 sizeof(buf->total)))
1982 return -EFAULT;
1983
1984 d->granted_count++;
1985 }
1986 return 0;
1987}
1988
1989int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1990{
1991 struct drm_device_dma *dma = dev->dma;
1992 int ret = 0;
1993 struct drm_dma *d = data;
1994
1995 LOCK_TEST_WITH_RETURN(dev, file_priv);
1996
1997 /* Please don't send us buffers.
1998 */
1999 if (d->send_count != 0) {
2000 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2001 DRM_CURRENTPID, d->send_count);
2002 return -EINVAL;
2003 }
2004
2005 /* We'll send you buffers.
2006 */
2007 if (d->request_count < 0 || d->request_count > dma->buf_count) {
2008 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2009 DRM_CURRENTPID, d->request_count, dma->buf_count);
2010 return -EINVAL;
2011 }
2012
2013 d->granted_count = 0;
2014
2015 if (d->request_count) {
2016 ret = radeon_cp_get_buffers(dev, file_priv, d);
2017 }
2018
2019 return ret;
2020}
2021
2022int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2023{
2024 drm_radeon_private_t *dev_priv;
2025 int ret = 0;
2026
2027 dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2028 if (dev_priv == NULL)
2029 return -ENOMEM;
2030
2031 memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2032 dev->dev_private = (void *)dev_priv;
2033 dev_priv->flags = flags;
2034
2035 switch (flags & RADEON_FAMILY_MASK) {
2036 case CHIP_R100:
2037 case CHIP_RV200:
2038 case CHIP_R200:
2039 case CHIP_R300:
2040 case CHIP_R350:
2041 case CHIP_R420:
2042 case CHIP_R423:
2043 case CHIP_RV410:
2044 case CHIP_RV515:
2045 case CHIP_R520:
2046 case CHIP_RV570:
2047 case CHIP_R580:
2048 dev_priv->flags |= RADEON_HAS_HIERZ;
2049 break;
2050 default:
2051 /* all other chips have no hierarchical z buffer */
2052 break;
2053 }
2054
2055 if (drm_device_is_agp(dev))
2056 dev_priv->flags |= RADEON_IS_AGP;
2057 else if (drm_device_is_pcie(dev))
2058 dev_priv->flags |= RADEON_IS_PCIE;
2059 else
2060 dev_priv->flags |= RADEON_IS_PCI;
2061
2062 ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2063 drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2064 _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2065 if (ret != 0)
2066 return ret;
2067
2068 ret = drm_vblank_init(dev, 2);
2069 if (ret) {
2070 radeon_driver_unload(dev);
2071 return ret;
2072 }
2073
2074 DRM_DEBUG("%s card detected\n",
2075 ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2076 return ret;
2077}
2078
2079/* Create mappings for registers and framebuffer so userland doesn't necessarily
2080 * have to find them.
2081 */
2082int radeon_driver_firstopen(struct drm_device *dev)
2083{
2084 int ret;
2085 drm_local_map_t *map;
2086 drm_radeon_private_t *dev_priv = dev->dev_private;
2087
2088 dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2089
2090 dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2091 ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2092 drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2093 _DRM_WRITE_COMBINING, &map);
2094 if (ret != 0)
2095 return ret;
2096
2097 return 0;
2098}
2099
2100int radeon_driver_unload(struct drm_device *dev)
2101{
2102 drm_radeon_private_t *dev_priv = dev->dev_private;
2103
2104 DRM_DEBUG("\n");
2105
2106 drm_rmmap(dev, dev_priv->mmio);
2107
2108 drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2109
2110 dev->dev_private = NULL;
2111 return 0;
2112}
2113
2114void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2115{
2116 int i;
2117 u32 *ring;
2118 int tail_aligned;
2119
2120 /* check if the ring is padded out to 16-dword alignment */
2121
2122 tail_aligned = dev_priv->ring.tail & 0xf;
2123 if (tail_aligned) {
2124 int num_p2 = 16 - tail_aligned;
2125
2126 ring = dev_priv->ring.start;
2127 /* pad with some CP_PACKET2 */
2128 for (i = 0; i < num_p2; i++)
2129 ring[dev_priv->ring.tail + i] = CP_PACKET2();
2130
2131 dev_priv->ring.tail += i;
2132
2133 dev_priv->ring.space -= num_p2 * sizeof(u32);
2134 }
2135
2136 dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2137
2138 DRM_MEMORYBARRIER();
2139 GET_RING_HEAD( dev_priv );
2140
2141 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2142 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2143 /* read from PCI bus to ensure correct posting */
2144 RADEON_READ(R600_CP_RB_RPTR);
2145 } else {
2146 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2147 /* read from PCI bus to ensure correct posting */
2148 RADEON_READ(RADEON_CP_RB_RPTR);
2149 }
2150}