1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 113995 2003-04-25 01:18:47Z anholt $
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39#define RADEON_FIFO_DEBUG 0
40
41
42/* CP microcode (from ATI) */
43static u32 R200_cp_microcode[][2] = {
44 { 0x21007000, 0000000000 },
45 { 0x20007000, 0000000000 },
46 { 0x000000ab, 0x00000004 },
47 { 0x000000af, 0x00000004 },
48 { 0x66544a49, 0000000000 },
49 { 0x49494174, 0000000000 },
50 { 0x54517d83, 0000000000 },
51 { 0x498d8b64, 0000000000 },
52 { 0x49494949, 0000000000 },
53 { 0x49da493c, 0000000000 },
54 { 0x49989898, 0000000000 },
55 { 0xd34949d5, 0000000000 },
56 { 0x9dc90e11, 0000000000 },
57 { 0xce9b9b9b, 0000000000 },
58 { 0x000f0000, 0x00000016 },
59 { 0x352e232c, 0000000000 },
60 { 0x00000013, 0x00000004 },
61 { 0x000f0000, 0x00000016 },
62 { 0x352e272c, 0000000000 },
63 { 0x000f0001, 0x00000016 },
64 { 0x3239362f, 0000000000 },
65 { 0x000077ef, 0x00000002 },
66 { 0x00061000, 0x00000002 },
67 { 0x00000020, 0x0000001a },
68 { 0x00004000, 0x0000001e },
69 { 0x00061000, 0x00000002 },
70 { 0x00000020, 0x0000001a },
71 { 0x00004000, 0x0000001e },
72 { 0x00061000, 0x00000002 },
73 { 0x00000020, 0x0000001a },
74 { 0x00004000, 0x0000001e },
75 { 0x00000016, 0x00000004 },
76 { 0x0003802a, 0x00000002 },
77 { 0x040067e0, 0x00000002 },
78 { 0x00000016, 0x00000004 },
79 { 0x000077e0, 0x00000002 },
80 { 0x00065000, 0x00000002 },
81 { 0x000037e1, 0x00000002 },
82 { 0x040067e1, 0x00000006 },
83 { 0x000077e0, 0x00000002 },
84 { 0x000077e1, 0x00000002 },
85 { 0x000077e1, 0x00000006 },
86 { 0xffffffff, 0000000000 },
87 { 0x10000000, 0000000000 },
88 { 0x0003802a, 0x00000002 },
89 { 0x040067e0, 0x00000006 },
90 { 0x00007675, 0x00000002 },
91 { 0x00007676, 0x00000002 },
92 { 0x00007677, 0x00000002 },
93 { 0x00007678, 0x00000006 },
94 { 0x0003802b, 0x00000002 },
95 { 0x04002676, 0x00000002 },
96 { 0x00007677, 0x00000002 },
97 { 0x00007678, 0x00000006 },
98 { 0x0000002e, 0x00000018 },
99 { 0x0000002e, 0x00000018 },
100 { 0000000000, 0x00000006 },
101 { 0x0000002f, 0x00000018 },
102 { 0x0000002f, 0x00000018 },
103 { 0000000000, 0x00000006 },
104 { 0x01605000, 0x00000002 },
105 { 0x00065000, 0x00000002 },
106 { 0x00098000, 0x00000002 },
107 { 0x00061000, 0x00000002 },
108 { 0x64c0603d, 0x00000004 },
109 { 0x00080000, 0x00000016 },
110 { 0000000000, 0000000000 },
111 { 0x0400251d, 0x00000002 },
112 { 0x00007580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x04002580, 0x00000002 },
115 { 0x00067581, 0x00000002 },
116 { 0x00000046, 0x00000004 },
117 { 0x00005000, 0000000000 },
118 { 0x00061000, 0x00000002 },
119 { 0x0000750e, 0x00000002 },
120 { 0x00019000, 0x00000002 },
121 { 0x00011055, 0x00000014 },
122 { 0x00000055, 0x00000012 },
123 { 0x0400250f, 0x00000002 },
124 { 0x0000504a, 0x00000004 },
125 { 0x00007565, 0x00000002 },
126 { 0x00007566, 0x00000002 },
127 { 0x00000051, 0x00000004 },
128 { 0x01e655b4, 0x00000002 },
129 { 0x4401b0dc, 0x00000002 },
130 { 0x01c110dc, 0x00000002 },
131 { 0x2666705d, 0x00000018 },
132 { 0x040c2565, 0x00000002 },
133 { 0x0000005d, 0x00000018 },
134 { 0x04002564, 0x00000002 },
135 { 0x00007566, 0x00000002 },
136 { 0x00000054, 0x00000004 },
137 { 0x00401060, 0x00000008 },
138 { 0x00101000, 0x00000002 },
139 { 0x000d80ff, 0x00000002 },
140 { 0x00800063, 0x00000008 },
141 { 0x000f9000, 0x00000002 },
142 { 0x000e00ff, 0x00000002 },
143 { 0000000000, 0x00000006 },
144 { 0x00000080, 0x00000018 },
145 { 0x00000054, 0x00000004 },
146 { 0x00007576, 0x00000002 },
147 { 0x00065000, 0x00000002 },
148 { 0x00009000, 0x00000002 },
149 { 0x00041000, 0x00000002 },
150 { 0x0c00350e, 0x00000002 },
151 { 0x00049000, 0x00000002 },
152 { 0x00051000, 0x00000002 },
153 { 0x01e785f8, 0x00000002 },
154 { 0x00200000, 0x00000002 },
155 { 0x00600073, 0x0000000c },
156 { 0x00007563, 0x00000002 },
157 { 0x006075f0, 0x00000021 },
158 { 0x20007068, 0x00000004 },
159 { 0x00005068, 0x00000004 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600076, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000076, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x0020750f, 0x00000002 },
171 { 0x00600079, 0x00000004 },
172 { 0x00007570, 0x00000002 },
173 { 0x00007571, 0x00000002 },
174 { 0x00007572, 0x00000006 },
175 { 0x00005000, 0x00000002 },
176 { 0x00a05000, 0x00000002 },
177 { 0x00007568, 0x00000002 },
178 { 0x00061000, 0x00000002 },
179 { 0x00000084, 0x0000000c },
180 { 0x00058000, 0x00000002 },
181 { 0x0c607562, 0x00000002 },
182 { 0x00000086, 0x00000004 },
183 { 0x00600085, 0x00000004 },
184 { 0x400070dd, 0000000000 },
185 { 0x000380dd, 0x00000002 },
186 { 0x00000093, 0x0000001c },
187 { 0x00065095, 0x00000018 },
188 { 0x040025bb, 0x00000002 },
189 { 0x00061096, 0x00000018 },
190 { 0x040075bc, 0000000000 },
191 { 0x000075bb, 0x00000002 },
192 { 0x000075bc, 0000000000 },
193 { 0x00090000, 0x00000006 },
194 { 0x00090000, 0x00000002 },
195 { 0x000d8002, 0x00000006 },
196 { 0x00005000, 0x00000002 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x00007821, 0x00000002 },
200 { 0x00007800, 0000000000 },
201 { 0x01665000, 0x00000002 },
202 { 0x000a0000, 0x00000002 },
203 { 0x000671cc, 0x00000002 },
204 { 0x0286f1cd, 0x00000002 },
205 { 0x000000a3, 0x00000010 },
206 { 0x21007000, 0000000000 },
207 { 0x000000aa, 0x0000001c },
208 { 0x00065000, 0x00000002 },
209 { 0x000a0000, 0x00000002 },
210 { 0x00061000, 0x00000002 },
211 { 0x000b0000, 0x00000002 },
212 { 0x38067000, 0x00000002 },
213 { 0x000a00a6, 0x00000004 },
214 { 0x20007000, 0000000000 },
215 { 0x01200000, 0x00000002 },
216 { 0x20077000, 0x00000002 },
217 { 0x01200000, 0x00000002 },
218 { 0x20007000, 0000000000 },
219 { 0x00061000, 0x00000002 },
220 { 0x0120751b, 0x00000002 },
221 { 0x8040750a, 0x00000002 },
222 { 0x8040750b, 0x00000002 },
223 { 0x00110000, 0x00000002 },
224 { 0x000380dd, 0x00000002 },
225 { 0x000000bd, 0x0000001c },
226 { 0x00061096, 0x00000018 },
227 { 0x844075bd, 0x00000002 },
228 { 0x00061095, 0x00000018 },
229 { 0x840075bb, 0x00000002 },
230 { 0x00061096, 0x00000018 },
231 { 0x844075bc, 0x00000002 },
232 { 0x000000c0, 0x00000004 },
233 { 0x804075bd, 0x00000002 },
234 { 0x800075bb, 0x00000002 },
235 { 0x804075bc, 0x00000002 },
236 { 0x00108000, 0x00000002 },
237 { 0x01400000, 0x00000002 },
238 { 0x006000c4, 0x0000000c },
239 { 0x20c07000, 0x00000020 },
240 { 0x000000c6, 0x00000012 },
241 { 0x00800000, 0x00000006 },
242 { 0x0080751d, 0x00000006 },
243 { 0x000025bb, 0x00000002 },
244 { 0x000040c0, 0x00000004 },
245 { 0x0000775c, 0x00000002 },
246 { 0x00a05000, 0x00000002 },
247 { 0x00661000, 0x00000002 },
248 { 0x0460275d, 0x00000020 },
249 { 0x00004000, 0000000000 },
250 { 0x00007999, 0x00000002 },
251 { 0x00a05000, 0x00000002 },
252 { 0x00661000, 0x00000002 },
253 { 0x0460299b, 0x00000020 },
254 { 0x00004000, 0000000000 },
255 { 0x01e00830, 0x00000002 },
256 { 0x21007000, 0000000000 },
257 { 0x00005000, 0x00000002 },
258 { 0x00038042, 0x00000002 },
259 { 0x040025e0, 0x00000002 },
260 { 0x000075e1, 0000000000 },
261 { 0x00000001, 0000000000 },
262 { 0x000380d9, 0x00000002 },
263 { 0x04007394, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 { 0000000000, 0000000000 },
300};
301
302
303static u32 radeon_cp_microcode[][2] = {
304 { 0x21007000, 0000000000 },
305 { 0x20007000, 0000000000 },
306 { 0x000000b4, 0x00000004 },
307 { 0x000000b8, 0x00000004 },
308 { 0x6f5b4d4c, 0000000000 },
309 { 0x4c4c427f, 0000000000 },
310 { 0x5b568a92, 0000000000 },
311 { 0x4ca09c6d, 0000000000 },
312 { 0xad4c4c4c, 0000000000 },
313 { 0x4ce1af3d, 0000000000 },
314 { 0xd8afafaf, 0000000000 },
315 { 0xd64c4cdc, 0000000000 },
316 { 0x4cd10d10, 0000000000 },
317 { 0x000f0000, 0x00000016 },
318 { 0x362f242d, 0000000000 },
319 { 0x00000012, 0x00000004 },
320 { 0x000f0000, 0x00000016 },
321 { 0x362f282d, 0000000000 },
322 { 0x000380e7, 0x00000002 },
323 { 0x04002c97, 0x00000002 },
324 { 0x000f0001, 0x00000016 },
325 { 0x333a3730, 0000000000 },
326 { 0x000077ef, 0x00000002 },
327 { 0x00061000, 0x00000002 },
328 { 0x00000021, 0x0000001a },
329 { 0x00004000, 0x0000001e },
330 { 0x00061000, 0x00000002 },
331 { 0x00000021, 0x0000001a },
332 { 0x00004000, 0x0000001e },
333 { 0x00061000, 0x00000002 },
334 { 0x00000021, 0x0000001a },
335 { 0x00004000, 0x0000001e },
336 { 0x00000017, 0x00000004 },
337 { 0x0003802b, 0x00000002 },
338 { 0x040067e0, 0x00000002 },
339 { 0x00000017, 0x00000004 },
340 { 0x000077e0, 0x00000002 },
341 { 0x00065000, 0x00000002 },
342 { 0x000037e1, 0x00000002 },
343 { 0x040067e1, 0x00000006 },
344 { 0x000077e0, 0x00000002 },
345 { 0x000077e1, 0x00000002 },
346 { 0x000077e1, 0x00000006 },
347 { 0xffffffff, 0000000000 },
348 { 0x10000000, 0000000000 },
349 { 0x0003802b, 0x00000002 },
350 { 0x040067e0, 0x00000006 },
351 { 0x00007675, 0x00000002 },
352 { 0x00007676, 0x00000002 },
353 { 0x00007677, 0x00000002 },
354 { 0x00007678, 0x00000006 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002676, 0x00000002 },
357 { 0x00007677, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0000002f, 0x00000018 },
360 { 0x0000002f, 0x00000018 },
361 { 0000000000, 0x00000006 },
362 { 0x00000030, 0x00000018 },
363 { 0x00000030, 0x00000018 },
364 { 0000000000, 0x00000006 },
365 { 0x01605000, 0x00000002 },
366 { 0x00065000, 0x00000002 },
367 { 0x00098000, 0x00000002 },
368 { 0x00061000, 0x00000002 },
369 { 0x64c0603e, 0x00000004 },
370 { 0x000380e6, 0x00000002 },
371 { 0x040025c5, 0x00000002 },
372 { 0x00080000, 0x00000016 },
373 { 0000000000, 0000000000 },
374 { 0x0400251d, 0x00000002 },
375 { 0x00007580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x04002580, 0x00000002 },
378 { 0x00067581, 0x00000002 },
379 { 0x00000049, 0x00000004 },
380 { 0x00005000, 0000000000 },
381 { 0x000380e6, 0x00000002 },
382 { 0x040025c5, 0x00000002 },
383 { 0x00061000, 0x00000002 },
384 { 0x0000750e, 0x00000002 },
385 { 0x00019000, 0x00000002 },
386 { 0x00011055, 0x00000014 },
387 { 0x00000055, 0x00000012 },
388 { 0x0400250f, 0x00000002 },
389 { 0x0000504f, 0x00000004 },
390 { 0x000380e6, 0x00000002 },
391 { 0x040025c5, 0x00000002 },
392 { 0x00007565, 0x00000002 },
393 { 0x00007566, 0x00000002 },
394 { 0x00000058, 0x00000004 },
395 { 0x000380e6, 0x00000002 },
396 { 0x040025c5, 0x00000002 },
397 { 0x01e655b4, 0x00000002 },
398 { 0x4401b0e4, 0x00000002 },
399 { 0x01c110e4, 0x00000002 },
400 { 0x26667066, 0x00000018 },
401 { 0x040c2565, 0x00000002 },
402 { 0x00000066, 0x00000018 },
403 { 0x04002564, 0x00000002 },
404 { 0x00007566, 0x00000002 },
405 { 0x0000005d, 0x00000004 },
406 { 0x00401069, 0x00000008 },
407 { 0x00101000, 0x00000002 },
408 { 0x000d80ff, 0x00000002 },
409 { 0x0080006c, 0x00000008 },
410 { 0x000f9000, 0x00000002 },
411 { 0x000e00ff, 0x00000002 },
412 { 0000000000, 0x00000006 },
413 { 0x0000008f, 0x00000018 },
414 { 0x0000005b, 0x00000004 },
415 { 0x000380e6, 0x00000002 },
416 { 0x040025c5, 0x00000002 },
417 { 0x00007576, 0x00000002 },
418 { 0x00065000, 0x00000002 },
419 { 0x00009000, 0x00000002 },
420 { 0x00041000, 0x00000002 },
421 { 0x0c00350e, 0x00000002 },
422 { 0x00049000, 0x00000002 },
423 { 0x00051000, 0x00000002 },
424 { 0x01e785f8, 0x00000002 },
425 { 0x00200000, 0x00000002 },
426 { 0x0060007e, 0x0000000c },
427 { 0x00007563, 0x00000002 },
428 { 0x006075f0, 0x00000021 },
429 { 0x20007073, 0x00000004 },
430 { 0x00005073, 0x00000004 },
431 { 0x000380e6, 0x00000002 },
432 { 0x040025c5, 0x00000002 },
433 { 0x00007576, 0x00000002 },
434 { 0x00007577, 0x00000002 },
435 { 0x0000750e, 0x00000002 },
436 { 0x0000750f, 0x00000002 },
437 { 0x00a05000, 0x00000002 },
438 { 0x00600083, 0x0000000c },
439 { 0x006075f0, 0x00000021 },
440 { 0x000075f8, 0x00000002 },
441 { 0x00000083, 0x00000004 },
442 { 0x000a750e, 0x00000002 },
443 { 0x000380e6, 0x00000002 },
444 { 0x040025c5, 0x00000002 },
445 { 0x0020750f, 0x00000002 },
446 { 0x00600086, 0x00000004 },
447 { 0x00007570, 0x00000002 },
448 { 0x00007571, 0x00000002 },
449 { 0x00007572, 0x00000006 },
450 { 0x000380e6, 0x00000002 },
451 { 0x040025c5, 0x00000002 },
452 { 0x00005000, 0x00000002 },
453 { 0x00a05000, 0x00000002 },
454 { 0x00007568, 0x00000002 },
455 { 0x00061000, 0x00000002 },
456 { 0x00000095, 0x0000000c },
457 { 0x00058000, 0x00000002 },
458 { 0x0c607562, 0x00000002 },
459 { 0x00000097, 0x00000004 },
460 { 0x000380e6, 0x00000002 },
461 { 0x040025c5, 0x00000002 },
462 { 0x00600096, 0x00000004 },
463 { 0x400070e5, 0000000000 },
464 { 0x000380e6, 0x00000002 },
465 { 0x040025c5, 0x00000002 },
466 { 0x000380e5, 0x00000002 },
467 { 0x000000a8, 0x0000001c },
468 { 0x000650aa, 0x00000018 },
469 { 0x040025bb, 0x00000002 },
470 { 0x000610ab, 0x00000018 },
471 { 0x040075bc, 0000000000 },
472 { 0x000075bb, 0x00000002 },
473 { 0x000075bc, 0000000000 },
474 { 0x00090000, 0x00000006 },
475 { 0x00090000, 0x00000002 },
476 { 0x000d8002, 0x00000006 },
477 { 0x00007832, 0x00000002 },
478 { 0x00005000, 0x00000002 },
479 { 0x000380e7, 0x00000002 },
480 { 0x04002c97, 0x00000002 },
481 { 0x00007820, 0x00000002 },
482 { 0x00007821, 0x00000002 },
483 { 0x00007800, 0000000000 },
484 { 0x01200000, 0x00000002 },
485 { 0x20077000, 0x00000002 },
486 { 0x01200000, 0x00000002 },
487 { 0x20007000, 0x00000002 },
488 { 0x00061000, 0x00000002 },
489 { 0x0120751b, 0x00000002 },
490 { 0x8040750a, 0x00000002 },
491 { 0x8040750b, 0x00000002 },
492 { 0x00110000, 0x00000002 },
493 { 0x000380e5, 0x00000002 },
494 { 0x000000c6, 0x0000001c },
495 { 0x000610ab, 0x00000018 },
496 { 0x844075bd, 0x00000002 },
497 { 0x000610aa, 0x00000018 },
498 { 0x840075bb, 0x00000002 },
499 { 0x000610ab, 0x00000018 },
500 { 0x844075bc, 0x00000002 },
501 { 0x000000c9, 0x00000004 },
502 { 0x804075bd, 0x00000002 },
503 { 0x800075bb, 0x00000002 },
504 { 0x804075bc, 0x00000002 },
505 { 0x00108000, 0x00000002 },
506 { 0x01400000, 0x00000002 },
507 { 0x006000cd, 0x0000000c },
508 { 0x20c07000, 0x00000020 },
509 { 0x000000cf, 0x00000012 },
510 { 0x00800000, 0x00000006 },
511 { 0x0080751d, 0x00000006 },
512 { 0000000000, 0000000000 },
513 { 0x0000775c, 0x00000002 },
514 { 0x00a05000, 0x00000002 },
515 { 0x00661000, 0x00000002 },
516 { 0x0460275d, 0x00000020 },
517 { 0x00004000, 0000000000 },
518 { 0x01e00830, 0x00000002 },
519 { 0x21007000, 0000000000 },
520 { 0x6464614d, 0000000000 },
521 { 0x69687420, 0000000000 },
522 { 0x00000073, 0000000000 },
523 { 0000000000, 0000000000 },
524 { 0x00005000, 0x00000002 },
525 { 0x000380d0, 0x00000002 },
526 { 0x040025e0, 0x00000002 },
527 { 0x000075e1, 0000000000 },
528 { 0x00000001, 0000000000 },
529 { 0x000380e0, 0x00000002 },
530 { 0x04002394, 0x00000002 },
531 { 0x00005000, 0000000000 },
532 { 0000000000, 0000000000 },
533 { 0000000000, 0000000000 },
534 { 0x00000008, 0000000000 },
535 { 0x00000004, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 { 0000000000, 0000000000 },
560};
561
562
563int RADEON_READ_PLL(drm_device_t *dev, int addr)
564{
565 drm_radeon_private_t *dev_priv = dev->dev_private;
566
567 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
568 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
569}
570
571#if RADEON_FIFO_DEBUG
572static void radeon_status( drm_radeon_private_t *dev_priv )
573{
574 printk( "%s:\n", __FUNCTION__ );
575 printk( "RBBM_STATUS = 0x%08x\n",
576 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
577 printk( "CP_RB_RTPR = 0x%08x\n",
578 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
579 printk( "CP_RB_WTPR = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
581 printk( "AIC_CNTL = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
583 printk( "AIC_STAT = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
585 printk( "AIC_PT_BASE = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
587 printk( "TLB_ADDR = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
589 printk( "TLB_DATA = 0x%08x\n",
590 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
591}
592#endif
593
594
595/* ================================================================
596 * Engine, FIFO control
597 */
598
599static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
600{
601 u32 tmp;
602 int i;
603
604 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
605
606 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
607 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
608 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
609
610 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
611 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
612 & RADEON_RB2D_DC_BUSY) ) {
613 return 0;
614 }
615 DRM_UDELAY( 1 );
616 }
617
618#if RADEON_FIFO_DEBUG
619 DRM_ERROR( "failed!\n" );
620 radeon_status( dev_priv );
621#endif
622 return DRM_ERR(EBUSY);
623}
624
625static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
626 int entries )
627{
628 int i;
629
630 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
631
632 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
633 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
634 & RADEON_RBBM_FIFOCNT_MASK );
635 if ( slots >= entries ) return 0;
636 DRM_UDELAY( 1 );
637 }
638
639#if RADEON_FIFO_DEBUG
640 DRM_ERROR( "failed!\n" );
641 radeon_status( dev_priv );
642#endif
643 return DRM_ERR(EBUSY);
644}
645
646static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
647{
648 int i, ret;
649
650 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
651
652 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
653 if ( ret ) return ret;
654
655 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
656 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
657 & RADEON_RBBM_ACTIVE) ) {
658 radeon_do_pixcache_flush( dev_priv );
659 return 0;
660 }
661 DRM_UDELAY( 1 );
662 }
663
664#if RADEON_FIFO_DEBUG
665 DRM_ERROR( "failed!\n" );
666 radeon_status( dev_priv );
667#endif
668 return DRM_ERR(EBUSY);
669}
670
671
672/* ================================================================
673 * CP control, initialization
674 */
675
676/* Load the microcode for the CP */
677static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
678{
679 int i;
680 DRM_DEBUG( "\n" );
681
682 radeon_do_wait_for_idle( dev_priv );
683
684 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
685
686 if (dev_priv->is_r200)
687 {
688 DRM_INFO("Loading R200 Microcode\n");
689 for ( i = 0 ; i < 256 ; i++ )
690 {
691 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
692 R200_cp_microcode[i][1] );
693 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
694 R200_cp_microcode[i][0] );
695 }
696 }
697 else
698 {
699 for ( i = 0 ; i < 256 ; i++ ) {
700 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
701 radeon_cp_microcode[i][1] );
702 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
703 radeon_cp_microcode[i][0] );
704 }
705 }
706}
707
708/* Flush any pending commands to the CP. This should only be used just
709 * prior to a wait for idle, as it informs the engine that the command
710 * stream is ending.
711 */
712static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
713{
714 DRM_DEBUG( "\n" );
715#if 0
716 u32 tmp;
717
718 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
719 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
720#endif
721}
722
723/* Wait for the CP to go idle.
724 */
725int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
726{
727 RING_LOCALS;
728 DRM_DEBUG( "\n" );
729
730 BEGIN_RING( 6 );
731
732 RADEON_PURGE_CACHE();
733 RADEON_PURGE_ZCACHE();
734 RADEON_WAIT_UNTIL_IDLE();
735
736 ADVANCE_RING();
737 COMMIT_RING();
738
739 return radeon_do_wait_for_idle( dev_priv );
740}
741
742/* Start the Command Processor.
743 */
744static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
745{
746 RING_LOCALS;
747 DRM_DEBUG( "\n" );
748
749 radeon_do_wait_for_idle( dev_priv );
750
751 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
752
753 dev_priv->cp_running = 1;
754
755 BEGIN_RING( 6 );
756
757 RADEON_PURGE_CACHE();
758 RADEON_PURGE_ZCACHE();
759 RADEON_WAIT_UNTIL_IDLE();
760
761 ADVANCE_RING();
762 COMMIT_RING();
763}
764
765/* Reset the Command Processor. This will not flush any pending
766 * commands, so you must wait for the CP command stream to complete
767 * before calling this routine.
768 */
769static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
770{
771 u32 cur_read_ptr;
772 DRM_DEBUG( "\n" );
773
774 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
775 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
776 SET_RING_HEAD( dev_priv, cur_read_ptr );
777 dev_priv->ring.tail = cur_read_ptr;
778}
779
780/* Stop the Command Processor. This will not flush any pending
781 * commands, so you must flush the command stream and wait for the CP
782 * to go idle before calling this routine.
783 */
784static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
785{
786 DRM_DEBUG( "\n" );
787
788 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
789
790 dev_priv->cp_running = 0;
791}
792
793/* Reset the engine. This will stop the CP if it is running.
794 */
795static int radeon_do_engine_reset( drm_device_t *dev )
796{
797 drm_radeon_private_t *dev_priv = dev->dev_private;
798 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
799 DRM_DEBUG( "\n" );
800
801 radeon_do_pixcache_flush( dev_priv );
802
803 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
804 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
805
806 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
807 RADEON_FORCEON_MCLKA |
808 RADEON_FORCEON_MCLKB |
809 RADEON_FORCEON_YCLKA |
810 RADEON_FORCEON_YCLKB |
811 RADEON_FORCEON_MC |
812 RADEON_FORCEON_AIC ) );
813
814 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
815
816 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
817 RADEON_SOFT_RESET_CP |
818 RADEON_SOFT_RESET_HI |
819 RADEON_SOFT_RESET_SE |
820 RADEON_SOFT_RESET_RE |
821 RADEON_SOFT_RESET_PP |
822 RADEON_SOFT_RESET_E2 |
823 RADEON_SOFT_RESET_RB ) );
824 RADEON_READ( RADEON_RBBM_SOFT_RESET );
825 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
826 ~( RADEON_SOFT_RESET_CP |
827 RADEON_SOFT_RESET_HI |
828 RADEON_SOFT_RESET_SE |
829 RADEON_SOFT_RESET_RE |
830 RADEON_SOFT_RESET_PP |
831 RADEON_SOFT_RESET_E2 |
832 RADEON_SOFT_RESET_RB ) ) );
833 RADEON_READ( RADEON_RBBM_SOFT_RESET );
834
835
836 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
837 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
838 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
839
840 /* Reset the CP ring */
841 radeon_do_cp_reset( dev_priv );
842
843 /* The CP is no longer running after an engine reset */
844 dev_priv->cp_running = 0;
845
846 /* Reset any pending vertex, indirect buffers */
847 radeon_freelist_reset( dev );
848
849 return 0;
850}
851
852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
860 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
861
862 if ( !dev_priv->is_pci ) {
863 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
864 (((dev_priv->agp_vm_start - 1 +
865 dev_priv->agp_size) & 0xffff0000) |
866 (dev_priv->agp_vm_start >> 16)) );
867 }
868
869#if __REALLY_HAVE_AGP
870 if ( !dev_priv->is_pci )
871 ring_start = (dev_priv->cp_ring->offset
872 - dev->agp->base
873 + dev_priv->agp_vm_start);
874 else
875#endif
876 ring_start = (dev_priv->cp_ring->offset
877 - dev->sg->handle
878 + dev_priv->agp_vm_start);
879
880 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
881
882 /* Set the write pointer delay */
883 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
884
885 /* Initialize the ring buffer's read and write pointers */
886 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
887 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
888 SET_RING_HEAD( dev_priv, cur_read_ptr );
889 dev_priv->ring.tail = cur_read_ptr;
890
891#if __REALLY_HAVE_AGP
892 if ( !dev_priv->is_pci ) {
893 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
894 dev_priv->ring_rptr->offset
895 - dev->agp->base
896 + dev_priv->agp_vm_start);
897 } else
898#endif
899 {
900 drm_sg_mem_t *entry = dev->sg;
901 unsigned long tmp_ofs, page_ofs;
902
903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
904 page_ofs = tmp_ofs >> PAGE_SHIFT;
905
906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
907 entry->busaddr[page_ofs]);
908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
909 entry->busaddr[page_ofs],
910 entry->handle + tmp_ofs );
911 }
912
913 /* Initialize the scratch register pointer. This will cause
914 * the scratch register values to be written out to memory
915 * whenever they are updated.
916 *
917 * We simply put this behind the ring read pointer, this works
918 * with PCI GART as well as (whatever kind of) AGP GART
919 */
920 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
921 + RADEON_SCRATCH_REG_OFFSET );
922
923 dev_priv->scratch = ((__volatile__ u32 *)
924 dev_priv->ring_rptr->handle +
925 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
926
927 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
928
929 /* Writeback doesn't seem to work everywhere, test it first */
930 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
931 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
932
933 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
934 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
935 break;
936 DRM_UDELAY( 1 );
937 }
938
939 if ( tmp < dev_priv->usec_timeout ) {
940 dev_priv->writeback_works = 1;
941 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
942 } else {
943 dev_priv->writeback_works = 0;
944 DRM_DEBUG( "writeback test failed\n" );
945 }
946
947 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
948 RADEON_WRITE( RADEON_LAST_FRAME_REG,
949 dev_priv->sarea_priv->last_frame );
950
951 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
952 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
953 dev_priv->sarea_priv->last_dispatch );
954
955 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
956 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
957 dev_priv->sarea_priv->last_clear );
958
959 /* Set ring buffer size */
960#ifdef __BIG_ENDIAN
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
962#else
963 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
964#endif
965
966 radeon_do_wait_for_idle( dev_priv );
967
968 /* Turn on bus mastering */
969 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
970 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
971
972 /* Sync everything up */
973 RADEON_WRITE( RADEON_ISYNC_CNTL,
974 (RADEON_ISYNC_ANY2D_IDLE3D |
975 RADEON_ISYNC_ANY3D_IDLE2D |
976 RADEON_ISYNC_WAIT_IDLEGUI |
977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978}
979
980static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
981{
982 drm_radeon_private_t *dev_priv;
983 u32 tmp;
984 DRM_DEBUG( "\n" );
985
986 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
987 if ( dev_priv == NULL )
988 return DRM_ERR(ENOMEM);
989
990 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
991
992 dev_priv->is_pci = init->is_pci;
993
994 if ( dev_priv->is_pci && !dev->sg ) {
995 DRM_ERROR( "PCI GART memory not allocated!\n" );
996 dev->dev_private = (void *)dev_priv;
997 radeon_do_cleanup_cp(dev);
998 return DRM_ERR(EINVAL);
999 }
1000
1001 dev_priv->usec_timeout = init->usec_timeout;
1002 if ( dev_priv->usec_timeout < 1 ||
1003 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1004 DRM_DEBUG( "TIMEOUT problem!\n" );
1005 dev->dev_private = (void *)dev_priv;
1006 radeon_do_cleanup_cp(dev);
1007 return DRM_ERR(EINVAL);
1008 }
1009
1010 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1011 dev_priv->do_boxes = 0;
1012 dev_priv->cp_mode = init->cp_mode;
1013
1014 /* We don't support anything other than bus-mastering ring mode,
1015 * but the ring can be in either AGP or PCI space for the ring
1016 * read pointer.
1017 */
1018 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1019 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1020 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1021 dev->dev_private = (void *)dev_priv;
1022 radeon_do_cleanup_cp(dev);
1023 return DRM_ERR(EINVAL);
1024 }
1025
1026 switch ( init->fb_bpp ) {
1027 case 16:
1028 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1029 break;
1030 case 32:
1031 default:
1032 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1033 break;
1034 }
1035 dev_priv->front_offset = init->front_offset;
1036 dev_priv->front_pitch = init->front_pitch;
1037 dev_priv->back_offset = init->back_offset;
1038 dev_priv->back_pitch = init->back_pitch;
1039
1040 switch ( init->depth_bpp ) {
1041 case 16:
1042 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1043 break;
1044 case 32:
1045 default:
1046 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1047 break;
1048 }
1049 dev_priv->depth_offset = init->depth_offset;
1050 dev_priv->depth_pitch = init->depth_pitch;
1051
1052 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1053 (dev_priv->front_offset >> 10));
1054 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1055 (dev_priv->back_offset >> 10));
1056 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1057 (dev_priv->depth_offset >> 10));
1058
1059 /* Hardware state for depth clears. Remove this if/when we no
1060 * longer clear the depth buffer with a 3D rectangle. Hard-code
1061 * all values to prevent unwanted 3D state from slipping through
1062 * and screwing with the clear operation.
1063 */
1064 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1065 (dev_priv->color_fmt << 10) |
1066 (1<<15));
1067
1068 dev_priv->depth_clear.rb3d_zstencilcntl =
1069 (dev_priv->depth_fmt |
1070 RADEON_Z_TEST_ALWAYS |
1071 RADEON_STENCIL_TEST_ALWAYS |
1072 RADEON_STENCIL_S_FAIL_REPLACE |
1073 RADEON_STENCIL_ZPASS_REPLACE |
1074 RADEON_STENCIL_ZFAIL_REPLACE |
1075 RADEON_Z_WRITE_ENABLE);
1076
1077 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1078 RADEON_BFACE_SOLID |
1079 RADEON_FFACE_SOLID |
1080 RADEON_FLAT_SHADE_VTX_LAST |
1081 RADEON_DIFFUSE_SHADE_FLAT |
1082 RADEON_ALPHA_SHADE_FLAT |
1083 RADEON_SPECULAR_SHADE_FLAT |
1084 RADEON_FOG_SHADE_FLAT |
1085 RADEON_VTX_PIX_CENTER_OGL |
1086 RADEON_ROUND_MODE_TRUNC |
1087 RADEON_ROUND_PREC_8TH_PIX);
1088
1089 DRM_GETSAREA();
1090
1091 dev_priv->fb_offset = init->fb_offset;
1092 dev_priv->mmio_offset = init->mmio_offset;
1093 dev_priv->ring_offset = init->ring_offset;
1094 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1095 dev_priv->buffers_offset = init->buffers_offset;
1096 dev_priv->agp_textures_offset = init->agp_textures_offset;
1097
1098 if(!dev_priv->sarea) {
1099 DRM_ERROR("could not find sarea!\n");
1100 dev->dev_private = (void *)dev_priv;
1101 radeon_do_cleanup_cp(dev);
1102 return DRM_ERR(EINVAL);
1103 }
1104
1105 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1106 if(!dev_priv->fb) {
1107 DRM_ERROR("could not find framebuffer!\n");
1108 dev->dev_private = (void *)dev_priv;
1109 radeon_do_cleanup_cp(dev);
1110 return DRM_ERR(EINVAL);
1111 }
1112 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1113 if(!dev_priv->mmio) {
1114 DRM_ERROR("could not find mmio region!\n");
1115 dev->dev_private = (void *)dev_priv;
1116 radeon_do_cleanup_cp(dev);
1117 return DRM_ERR(EINVAL);
1118 }
1119 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1120 if(!dev_priv->cp_ring) {
1121 DRM_ERROR("could not find cp ring region!\n");
1122 dev->dev_private = (void *)dev_priv;
1123 radeon_do_cleanup_cp(dev);
1124 return DRM_ERR(EINVAL);
1125 }
1126 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1127 if(!dev_priv->ring_rptr) {
1128 DRM_ERROR("could not find ring read pointer!\n");
1129 dev->dev_private = (void *)dev_priv;
1130 radeon_do_cleanup_cp(dev);
1131 return DRM_ERR(EINVAL);
1132 }
1133 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1134 if(!dev_priv->buffers) {
1135 DRM_ERROR("could not find dma buffer region!\n");
1136 dev->dev_private = (void *)dev_priv;
1137 radeon_do_cleanup_cp(dev);
1138 return DRM_ERR(EINVAL);
1139 }
1140
1141 if ( !dev_priv->is_pci ) {
1142 DRM_FIND_MAP( dev_priv->agp_textures,
1143 init->agp_textures_offset );
1144 if(!dev_priv->agp_textures) {
1145 DRM_ERROR("could not find agp texture region!\n");
1146 dev->dev_private = (void *)dev_priv;
1147 radeon_do_cleanup_cp(dev);
1148 return DRM_ERR(EINVAL);
1149 }
1150 }
1151
1152 dev_priv->sarea_priv =
1153 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1154 init->sarea_priv_offset);
1155
1156 if ( !dev_priv->is_pci ) {
1157 DRM_IOREMAP( dev_priv->cp_ring );
1158 DRM_IOREMAP( dev_priv->ring_rptr );
1159 DRM_IOREMAP( dev_priv->buffers );
1160 if(!dev_priv->cp_ring->handle ||
1161 !dev_priv->ring_rptr->handle ||
1162 !dev_priv->buffers->handle) {
1163 DRM_ERROR("could not find ioremap agp regions!\n");
1164 dev->dev_private = (void *)dev_priv;
1165 radeon_do_cleanup_cp(dev);
1166 return DRM_ERR(EINVAL);
1167 }
1168 } else {
1169 dev_priv->cp_ring->handle =
1170 (void *)dev_priv->cp_ring->offset;
1171 dev_priv->ring_rptr->handle =
1172 (void *)dev_priv->ring_rptr->offset;
1173 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1174
1175 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1176 dev_priv->cp_ring->handle );
1177 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1178 dev_priv->ring_rptr->handle );
1179 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1180 dev_priv->buffers->handle );
1181 }
1182
1183
1184 dev_priv->agp_size = init->agp_size;
1185 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1186#if __REALLY_HAVE_AGP
1187 if ( !dev_priv->is_pci )
1188 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1189 - dev->agp->base
1190 + dev_priv->agp_vm_start);
1191 else
1192#endif
1193 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1194 - dev->sg->handle
1195 + dev_priv->agp_vm_start);
1196
1197 DRM_DEBUG( "dev_priv->agp_size %d\n",
1198 dev_priv->agp_size );
1199 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1200 dev_priv->agp_vm_start );
1201 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1202 dev_priv->agp_buffers_offset );
1203
1204 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1205 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1206 + init->ring_size / sizeof(u32));
1207 dev_priv->ring.size = init->ring_size;
1208 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1209
1210 dev_priv->ring.tail_mask =
1211 (dev_priv->ring.size / sizeof(u32)) - 1;
1212
1213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1214
1215#if __REALLY_HAVE_SG
1216 if ( dev_priv->is_pci ) {
1217 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1218 &dev_priv->bus_pci_gart)) {
1219 DRM_ERROR( "failed to init PCI GART!\n" );
1220 dev->dev_private = (void *)dev_priv;
1221 radeon_do_cleanup_cp(dev);
1222 return DRM_ERR(ENOMEM);
1223 }
1224 /* Turn on PCI GART
1225 */
1226 tmp = RADEON_READ( RADEON_AIC_CNTL )
1227 | RADEON_PCIGART_TRANSLATE_EN;
1228 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1229
1230 /* set PCI GART page-table base address
1231 */
1232 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1233
1234 /* set address range for PCI address translate
1235 */
1236 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1237 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1238 + dev_priv->agp_size - 1);
1239
1240 /* Turn off AGP aperture -- is this required for PCIGART?
1241 */
1242 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1243 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1244 } else {
1245#endif /* __REALLY_HAVE_SG */
1246 /* Turn off PCI GART
1247 */
1248 tmp = RADEON_READ( RADEON_AIC_CNTL )
1249 & ~RADEON_PCIGART_TRANSLATE_EN;
1250 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1251#if __REALLY_HAVE_SG
1252 }
1253#endif /* __REALLY_HAVE_SG */
1254
1255 radeon_cp_load_microcode( dev_priv );
1256 radeon_cp_init_ring_buffer( dev, dev_priv );
1257
1258 dev_priv->last_buf = 0;
1259
1260 dev->dev_private = (void *)dev_priv;
1261
1262 radeon_do_engine_reset( dev );
1263
1264 return 0;
1265}
1266
1267int radeon_do_cleanup_cp( drm_device_t *dev )
1268{
1269 DRM_DEBUG( "\n" );
1270
1271 if ( dev->dev_private ) {
1272 drm_radeon_private_t *dev_priv = dev->dev_private;
1273
1274 if ( !dev_priv->is_pci ) {
1275 if ( dev_priv->cp_ring != NULL )
1276 DRM_IOREMAPFREE( dev_priv->cp_ring );
1277 if ( dev_priv->ring_rptr != NULL )
1278 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1279 if ( dev_priv->buffers != NULL )
1280 DRM_IOREMAPFREE( dev_priv->buffers );
1281 } else {
1282#if __REALLY_HAVE_SG
1283 if (!DRM(ati_pcigart_cleanup)( dev,
1284 dev_priv->phys_pci_gart,
1285 dev_priv->bus_pci_gart ))
1286 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1287#endif /* __REALLY_HAVE_SG */
1288 }
1289
1290 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1291 DRM_MEM_DRIVER );
1292 dev->dev_private = NULL;
1293 }
1294
1295 return 0;
1296}
1297
1298int radeon_cp_init( DRM_IOCTL_ARGS )
1299{
1300 DRM_DEVICE;
1301 drm_radeon_init_t init;
1302
1303 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1304
1305 switch ( init.func ) {
1306 case RADEON_INIT_CP:
1307 case RADEON_INIT_R200_CP:
1308 return radeon_do_init_cp( dev, &init );
1309 case RADEON_CLEANUP_CP:
1310 return radeon_do_cleanup_cp( dev );
1311 }
1312
1313 return DRM_ERR(EINVAL);
1314}
1315
1316int radeon_cp_start( DRM_IOCTL_ARGS )
1317{
1318 DRM_DEVICE;
1319 drm_radeon_private_t *dev_priv = dev->dev_private;
1320 DRM_DEBUG( "\n" );
1321
1322 LOCK_TEST_WITH_RETURN( dev, filp );
1323
1324 if ( dev_priv->cp_running ) {
1325 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1326 return 0;
1327 }
1328 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1329 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1330 __FUNCTION__, dev_priv->cp_mode );
1331 return 0;
1332 }
1333
1334 radeon_do_cp_start( dev_priv );
1335
1336 return 0;
1337}
1338
1339/* Stop the CP. The engine must have been idled before calling this
1340 * routine.
1341 */
1342int radeon_cp_stop( DRM_IOCTL_ARGS )
1343{
1344 DRM_DEVICE;
1345 drm_radeon_private_t *dev_priv = dev->dev_private;
1346 drm_radeon_cp_stop_t stop;
1347 int ret;
1348 DRM_DEBUG( "\n" );
1349
1350 LOCK_TEST_WITH_RETURN( dev, filp );
1351
1352 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1353
1354 if (!dev_priv->cp_running)
1355 return 0;
1356
1357 /* Flush any pending CP commands. This ensures any outstanding
1358 * commands are exectuted by the engine before we turn it off.
1359 */
1360 if ( stop.flush ) {
1361 radeon_do_cp_flush( dev_priv );
1362 }
1363
1364 /* If we fail to make the engine go idle, we return an error
1365 * code so that the DRM ioctl wrapper can try again.
1366 */
1367 if ( stop.idle ) {
1368 ret = radeon_do_cp_idle( dev_priv );
1369 if ( ret ) return ret;
1370 }
1371
1372 /* Finally, we can turn off the CP. If the engine isn't idle,
1373 * we will get some dropped triangles as they won't be fully
1374 * rendered before the CP is shut down.
1375 */
1376 radeon_do_cp_stop( dev_priv );
1377
1378 /* Reset the engine */
1379 radeon_do_engine_reset( dev );
1380
1381 return 0;
1382}
1383
1384
1385void radeon_do_release( drm_device_t *dev )
1386{
1387 drm_radeon_private_t *dev_priv = dev->dev_private;
1388 int ret;
1389
1390 if (dev_priv) {
1391 if (dev_priv->cp_running) {
1392 /* Stop the cp */
1393 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1394 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1395#ifdef __linux__
1396 schedule();
1397#else
1398 tsleep(&ret, PZERO, "rdnrel", 1);
1399#endif
1400 }
1401 radeon_do_cp_stop( dev_priv );
1402 radeon_do_engine_reset( dev );
1403 }
1404
1405 /* Disable *all* interrupts */
1406 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1407
1408 /* Free memory heap structures */
1409 radeon_mem_takedown( &(dev_priv->agp_heap) );
1410 radeon_mem_takedown( &(dev_priv->fb_heap) );
1411
1412 /* deallocate kernel resources */
1413 radeon_do_cleanup_cp( dev );
1414 }
1415}
1416
1417/* Just reset the CP ring. Called as part of an X Server engine reset.
1418 */
1419int radeon_cp_reset( DRM_IOCTL_ARGS )
1420{
1421 DRM_DEVICE;
1422 drm_radeon_private_t *dev_priv = dev->dev_private;
1423 DRM_DEBUG( "\n" );
1424
1425 LOCK_TEST_WITH_RETURN( dev, filp );
1426
1427 if ( !dev_priv ) {
1428 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1429 return DRM_ERR(EINVAL);
1430 }
1431
1432 radeon_do_cp_reset( dev_priv );
1433
1434 /* The CP is no longer running after an engine reset */
1435 dev_priv->cp_running = 0;
1436
1437 return 0;
1438}
1439
1440int radeon_cp_idle( DRM_IOCTL_ARGS )
1441{
1442 DRM_DEVICE;
1443 drm_radeon_private_t *dev_priv = dev->dev_private;
1444 DRM_DEBUG( "\n" );
1445
1446 LOCK_TEST_WITH_RETURN( dev, filp );
1447
1448 return radeon_do_cp_idle( dev_priv );
1449}
1450
1451int radeon_engine_reset( DRM_IOCTL_ARGS )
1452{
1453 DRM_DEVICE;
1454 DRM_DEBUG( "\n" );
1455
1456 LOCK_TEST_WITH_RETURN( dev, filp );
1457
1458 return radeon_do_engine_reset( dev );
1459}
1460
1461
1462/* ================================================================
1463 * Fullscreen mode
1464 */
1465
1466/* KW: Deprecated to say the least:
1467 */
1468int radeon_fullscreen( DRM_IOCTL_ARGS )
1469{
1470 return 0;
1471}
1472
1473
1474/* ================================================================
1475 * Freelist management
1476 */
1477
1478/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1479 * bufs until freelist code is used. Note this hides a problem with
1480 * the scratch register * (used to keep track of last buffer
1481 * completed) being written to before * the last buffer has actually
1482 * completed rendering.
1483 *
1484 * KW: It's also a good way to find free buffers quickly.
1485 *
1486 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1487 * sleep. However, bugs in older versions of radeon_accel.c mean that
1488 * we essentially have to do this, else old clients will break.
1489 *
1490 * However, it does leave open a potential deadlock where all the
1491 * buffers are held by other clients, which can't release them because
1492 * they can't get the lock.
1493 */
1494
1495drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1496{
1497 drm_device_dma_t *dma = dev->dma;
1498 drm_radeon_private_t *dev_priv = dev->dev_private;
1499 drm_radeon_buf_priv_t *buf_priv;
1500 drm_buf_t *buf;
1501 int i, t;
1502 int start;
1503
1504 if ( ++dev_priv->last_buf >= dma->buf_count )
1505 dev_priv->last_buf = 0;
1506
1507 start = dev_priv->last_buf;
1508
1509 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1510 u32 done_age = GET_SCRATCH( 1 );
1511 DRM_DEBUG("done_age = %d\n",done_age);
1512 for ( i = start ; i < dma->buf_count ; i++ ) {
1513 buf = dma->buflist[i];
1514 buf_priv = buf->dev_private;
1515 if ( buf->filp == 0 || (buf->pending &&
1516 buf_priv->age <= done_age) ) {
1517 dev_priv->stats.requested_bufs++;
1518 buf->pending = 0;
1519 return buf;
1520 }
1521 start = 0;
1522 }
1523
1524 if (t) {
1525 DRM_UDELAY( 1 );
1526 dev_priv->stats.freelist_loops++;
1527 }
1528 }
1529
1530 DRM_DEBUG( "returning NULL!\n" );
1531 return NULL;
1532}
1533#if 0
1534drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1535{
1536 drm_device_dma_t *dma = dev->dma;
1537 drm_radeon_private_t *dev_priv = dev->dev_private;
1538 drm_radeon_buf_priv_t *buf_priv;
1539 drm_buf_t *buf;
1540 int i, t;
1541 int start;
1542 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1543
1544 if ( ++dev_priv->last_buf >= dma->buf_count )
1545 dev_priv->last_buf = 0;
1546
1547 start = dev_priv->last_buf;
1548 dev_priv->stats.freelist_loops++;
1549
1550 for ( t = 0 ; t < 2 ; t++ ) {
1551 for ( i = start ; i < dma->buf_count ; i++ ) {
1552 buf = dma->buflist[i];
1553 buf_priv = buf->dev_private;
1554 if ( buf->filp == 0 || (buf->pending &&
1555 buf_priv->age <= done_age) ) {
1556 dev_priv->stats.requested_bufs++;
1557 buf->pending = 0;
1558 return buf;
1559 }
1560 }
1561 start = 0;
1562 }
1563
1564 return NULL;
1565}
1566#endif
1567
1568void radeon_freelist_reset( drm_device_t *dev )
1569{
1570 drm_device_dma_t *dma = dev->dma;
1571 drm_radeon_private_t *dev_priv = dev->dev_private;
1572 int i;
1573
1574 dev_priv->last_buf = 0;
1575 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1576 drm_buf_t *buf = dma->buflist[i];
1577 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1578 buf_priv->age = 0;
1579 }
1580}
1581
1582
1583/* ================================================================
1584 * CP command submission
1585 */
1586
1587int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1588{
1589 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1590 int i;
1591 u32 last_head = GET_RING_HEAD( dev_priv );
1592
1593 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1594 u32 head = GET_RING_HEAD( dev_priv );
1595
1596 ring->space = (head - ring->tail) * sizeof(u32);
1597 if ( ring->space <= 0 )
1598 ring->space += ring->size;
1599 if ( ring->space > n )
1600 return 0;
1601
1602 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1603
1604 if (head != last_head)
1605 i = 0;
1606 last_head = head;
1607
1608 DRM_UDELAY( 1 );
1609 }
1610
1611 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1612#if RADEON_FIFO_DEBUG
1613 radeon_status( dev_priv );
1614 DRM_ERROR( "failed!\n" );
1615#endif
1616 return DRM_ERR(EBUSY);
1617}
1618
1619static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1620{
1621 int i;
1622 drm_buf_t *buf;
1623
1624 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1625 buf = radeon_freelist_get( dev );
1626 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1627
1628 buf->filp = filp;
1629
1630 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1631 sizeof(buf->idx) ) )
1632 return DRM_ERR(EFAULT);
1633 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1634 sizeof(buf->total) ) )
1635 return DRM_ERR(EFAULT);
1636
1637 d->granted_count++;
1638 }
1639 return 0;
1640}
1641
1642int radeon_cp_buffers( DRM_IOCTL_ARGS )
1643{
1644 DRM_DEVICE;
1645 drm_device_dma_t *dma = dev->dma;
1646 int ret = 0;
1647 drm_dma_t d;
1648
1649 LOCK_TEST_WITH_RETURN( dev, filp );
1650
1651 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1652
1653 /* Please don't send us buffers.
1654 */
1655 if ( d.send_count != 0 ) {
1656 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1657 DRM_CURRENTPID, d.send_count );
1658 return DRM_ERR(EINVAL);
1659 }
1660
1661 /* We'll send you buffers.
1662 */
1663 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1664 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1665 DRM_CURRENTPID, d.request_count, dma->buf_count );
1666 return DRM_ERR(EINVAL);
1667 }
1668
1669 d.granted_count = 0;
1670
1671 if ( d.request_count ) {
1672 ret = radeon_cp_get_buffers( filp, dev, &d );
1673 }
1674
1675 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1676
1677 return ret;
1678}
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),
9 * to deal in the Software without restriction, including without limitation
10 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
11 * and/or sell copies of the Software, and to permit persons to whom the
12 * Software is furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the next
15 * paragraph) shall be included in all copies or substantial portions of the
16 * Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 113995 2003-04-25 01:18:47Z anholt $
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38
39#define RADEON_FIFO_DEBUG 0
40
41
42/* CP microcode (from ATI) */
43static u32 R200_cp_microcode[][2] = {
44 { 0x21007000, 0000000000 },
45 { 0x20007000, 0000000000 },
46 { 0x000000ab, 0x00000004 },
47 { 0x000000af, 0x00000004 },
48 { 0x66544a49, 0000000000 },
49 { 0x49494174, 0000000000 },
50 { 0x54517d83, 0000000000 },
51 { 0x498d8b64, 0000000000 },
52 { 0x49494949, 0000000000 },
53 { 0x49da493c, 0000000000 },
54 { 0x49989898, 0000000000 },
55 { 0xd34949d5, 0000000000 },
56 { 0x9dc90e11, 0000000000 },
57 { 0xce9b9b9b, 0000000000 },
58 { 0x000f0000, 0x00000016 },
59 { 0x352e232c, 0000000000 },
60 { 0x00000013, 0x00000004 },
61 { 0x000f0000, 0x00000016 },
62 { 0x352e272c, 0000000000 },
63 { 0x000f0001, 0x00000016 },
64 { 0x3239362f, 0000000000 },
65 { 0x000077ef, 0x00000002 },
66 { 0x00061000, 0x00000002 },
67 { 0x00000020, 0x0000001a },
68 { 0x00004000, 0x0000001e },
69 { 0x00061000, 0x00000002 },
70 { 0x00000020, 0x0000001a },
71 { 0x00004000, 0x0000001e },
72 { 0x00061000, 0x00000002 },
73 { 0x00000020, 0x0000001a },
74 { 0x00004000, 0x0000001e },
75 { 0x00000016, 0x00000004 },
76 { 0x0003802a, 0x00000002 },
77 { 0x040067e0, 0x00000002 },
78 { 0x00000016, 0x00000004 },
79 { 0x000077e0, 0x00000002 },
80 { 0x00065000, 0x00000002 },
81 { 0x000037e1, 0x00000002 },
82 { 0x040067e1, 0x00000006 },
83 { 0x000077e0, 0x00000002 },
84 { 0x000077e1, 0x00000002 },
85 { 0x000077e1, 0x00000006 },
86 { 0xffffffff, 0000000000 },
87 { 0x10000000, 0000000000 },
88 { 0x0003802a, 0x00000002 },
89 { 0x040067e0, 0x00000006 },
90 { 0x00007675, 0x00000002 },
91 { 0x00007676, 0x00000002 },
92 { 0x00007677, 0x00000002 },
93 { 0x00007678, 0x00000006 },
94 { 0x0003802b, 0x00000002 },
95 { 0x04002676, 0x00000002 },
96 { 0x00007677, 0x00000002 },
97 { 0x00007678, 0x00000006 },
98 { 0x0000002e, 0x00000018 },
99 { 0x0000002e, 0x00000018 },
100 { 0000000000, 0x00000006 },
101 { 0x0000002f, 0x00000018 },
102 { 0x0000002f, 0x00000018 },
103 { 0000000000, 0x00000006 },
104 { 0x01605000, 0x00000002 },
105 { 0x00065000, 0x00000002 },
106 { 0x00098000, 0x00000002 },
107 { 0x00061000, 0x00000002 },
108 { 0x64c0603d, 0x00000004 },
109 { 0x00080000, 0x00000016 },
110 { 0000000000, 0000000000 },
111 { 0x0400251d, 0x00000002 },
112 { 0x00007580, 0x00000002 },
113 { 0x00067581, 0x00000002 },
114 { 0x04002580, 0x00000002 },
115 { 0x00067581, 0x00000002 },
116 { 0x00000046, 0x00000004 },
117 { 0x00005000, 0000000000 },
118 { 0x00061000, 0x00000002 },
119 { 0x0000750e, 0x00000002 },
120 { 0x00019000, 0x00000002 },
121 { 0x00011055, 0x00000014 },
122 { 0x00000055, 0x00000012 },
123 { 0x0400250f, 0x00000002 },
124 { 0x0000504a, 0x00000004 },
125 { 0x00007565, 0x00000002 },
126 { 0x00007566, 0x00000002 },
127 { 0x00000051, 0x00000004 },
128 { 0x01e655b4, 0x00000002 },
129 { 0x4401b0dc, 0x00000002 },
130 { 0x01c110dc, 0x00000002 },
131 { 0x2666705d, 0x00000018 },
132 { 0x040c2565, 0x00000002 },
133 { 0x0000005d, 0x00000018 },
134 { 0x04002564, 0x00000002 },
135 { 0x00007566, 0x00000002 },
136 { 0x00000054, 0x00000004 },
137 { 0x00401060, 0x00000008 },
138 { 0x00101000, 0x00000002 },
139 { 0x000d80ff, 0x00000002 },
140 { 0x00800063, 0x00000008 },
141 { 0x000f9000, 0x00000002 },
142 { 0x000e00ff, 0x00000002 },
143 { 0000000000, 0x00000006 },
144 { 0x00000080, 0x00000018 },
145 { 0x00000054, 0x00000004 },
146 { 0x00007576, 0x00000002 },
147 { 0x00065000, 0x00000002 },
148 { 0x00009000, 0x00000002 },
149 { 0x00041000, 0x00000002 },
150 { 0x0c00350e, 0x00000002 },
151 { 0x00049000, 0x00000002 },
152 { 0x00051000, 0x00000002 },
153 { 0x01e785f8, 0x00000002 },
154 { 0x00200000, 0x00000002 },
155 { 0x00600073, 0x0000000c },
156 { 0x00007563, 0x00000002 },
157 { 0x006075f0, 0x00000021 },
158 { 0x20007068, 0x00000004 },
159 { 0x00005068, 0x00000004 },
160 { 0x00007576, 0x00000002 },
161 { 0x00007577, 0x00000002 },
162 { 0x0000750e, 0x00000002 },
163 { 0x0000750f, 0x00000002 },
164 { 0x00a05000, 0x00000002 },
165 { 0x00600076, 0x0000000c },
166 { 0x006075f0, 0x00000021 },
167 { 0x000075f8, 0x00000002 },
168 { 0x00000076, 0x00000004 },
169 { 0x000a750e, 0x00000002 },
170 { 0x0020750f, 0x00000002 },
171 { 0x00600079, 0x00000004 },
172 { 0x00007570, 0x00000002 },
173 { 0x00007571, 0x00000002 },
174 { 0x00007572, 0x00000006 },
175 { 0x00005000, 0x00000002 },
176 { 0x00a05000, 0x00000002 },
177 { 0x00007568, 0x00000002 },
178 { 0x00061000, 0x00000002 },
179 { 0x00000084, 0x0000000c },
180 { 0x00058000, 0x00000002 },
181 { 0x0c607562, 0x00000002 },
182 { 0x00000086, 0x00000004 },
183 { 0x00600085, 0x00000004 },
184 { 0x400070dd, 0000000000 },
185 { 0x000380dd, 0x00000002 },
186 { 0x00000093, 0x0000001c },
187 { 0x00065095, 0x00000018 },
188 { 0x040025bb, 0x00000002 },
189 { 0x00061096, 0x00000018 },
190 { 0x040075bc, 0000000000 },
191 { 0x000075bb, 0x00000002 },
192 { 0x000075bc, 0000000000 },
193 { 0x00090000, 0x00000006 },
194 { 0x00090000, 0x00000002 },
195 { 0x000d8002, 0x00000006 },
196 { 0x00005000, 0x00000002 },
197 { 0x00007821, 0x00000002 },
198 { 0x00007800, 0000000000 },
199 { 0x00007821, 0x00000002 },
200 { 0x00007800, 0000000000 },
201 { 0x01665000, 0x00000002 },
202 { 0x000a0000, 0x00000002 },
203 { 0x000671cc, 0x00000002 },
204 { 0x0286f1cd, 0x00000002 },
205 { 0x000000a3, 0x00000010 },
206 { 0x21007000, 0000000000 },
207 { 0x000000aa, 0x0000001c },
208 { 0x00065000, 0x00000002 },
209 { 0x000a0000, 0x00000002 },
210 { 0x00061000, 0x00000002 },
211 { 0x000b0000, 0x00000002 },
212 { 0x38067000, 0x00000002 },
213 { 0x000a00a6, 0x00000004 },
214 { 0x20007000, 0000000000 },
215 { 0x01200000, 0x00000002 },
216 { 0x20077000, 0x00000002 },
217 { 0x01200000, 0x00000002 },
218 { 0x20007000, 0000000000 },
219 { 0x00061000, 0x00000002 },
220 { 0x0120751b, 0x00000002 },
221 { 0x8040750a, 0x00000002 },
222 { 0x8040750b, 0x00000002 },
223 { 0x00110000, 0x00000002 },
224 { 0x000380dd, 0x00000002 },
225 { 0x000000bd, 0x0000001c },
226 { 0x00061096, 0x00000018 },
227 { 0x844075bd, 0x00000002 },
228 { 0x00061095, 0x00000018 },
229 { 0x840075bb, 0x00000002 },
230 { 0x00061096, 0x00000018 },
231 { 0x844075bc, 0x00000002 },
232 { 0x000000c0, 0x00000004 },
233 { 0x804075bd, 0x00000002 },
234 { 0x800075bb, 0x00000002 },
235 { 0x804075bc, 0x00000002 },
236 { 0x00108000, 0x00000002 },
237 { 0x01400000, 0x00000002 },
238 { 0x006000c4, 0x0000000c },
239 { 0x20c07000, 0x00000020 },
240 { 0x000000c6, 0x00000012 },
241 { 0x00800000, 0x00000006 },
242 { 0x0080751d, 0x00000006 },
243 { 0x000025bb, 0x00000002 },
244 { 0x000040c0, 0x00000004 },
245 { 0x0000775c, 0x00000002 },
246 { 0x00a05000, 0x00000002 },
247 { 0x00661000, 0x00000002 },
248 { 0x0460275d, 0x00000020 },
249 { 0x00004000, 0000000000 },
250 { 0x00007999, 0x00000002 },
251 { 0x00a05000, 0x00000002 },
252 { 0x00661000, 0x00000002 },
253 { 0x0460299b, 0x00000020 },
254 { 0x00004000, 0000000000 },
255 { 0x01e00830, 0x00000002 },
256 { 0x21007000, 0000000000 },
257 { 0x00005000, 0x00000002 },
258 { 0x00038042, 0x00000002 },
259 { 0x040025e0, 0x00000002 },
260 { 0x000075e1, 0000000000 },
261 { 0x00000001, 0000000000 },
262 { 0x000380d9, 0x00000002 },
263 { 0x04007394, 0000000000 },
264 { 0000000000, 0000000000 },
265 { 0000000000, 0000000000 },
266 { 0000000000, 0000000000 },
267 { 0000000000, 0000000000 },
268 { 0000000000, 0000000000 },
269 { 0000000000, 0000000000 },
270 { 0000000000, 0000000000 },
271 { 0000000000, 0000000000 },
272 { 0000000000, 0000000000 },
273 { 0000000000, 0000000000 },
274 { 0000000000, 0000000000 },
275 { 0000000000, 0000000000 },
276 { 0000000000, 0000000000 },
277 { 0000000000, 0000000000 },
278 { 0000000000, 0000000000 },
279 { 0000000000, 0000000000 },
280 { 0000000000, 0000000000 },
281 { 0000000000, 0000000000 },
282 { 0000000000, 0000000000 },
283 { 0000000000, 0000000000 },
284 { 0000000000, 0000000000 },
285 { 0000000000, 0000000000 },
286 { 0000000000, 0000000000 },
287 { 0000000000, 0000000000 },
288 { 0000000000, 0000000000 },
289 { 0000000000, 0000000000 },
290 { 0000000000, 0000000000 },
291 { 0000000000, 0000000000 },
292 { 0000000000, 0000000000 },
293 { 0000000000, 0000000000 },
294 { 0000000000, 0000000000 },
295 { 0000000000, 0000000000 },
296 { 0000000000, 0000000000 },
297 { 0000000000, 0000000000 },
298 { 0000000000, 0000000000 },
299 { 0000000000, 0000000000 },
300};
301
302
303static u32 radeon_cp_microcode[][2] = {
304 { 0x21007000, 0000000000 },
305 { 0x20007000, 0000000000 },
306 { 0x000000b4, 0x00000004 },
307 { 0x000000b8, 0x00000004 },
308 { 0x6f5b4d4c, 0000000000 },
309 { 0x4c4c427f, 0000000000 },
310 { 0x5b568a92, 0000000000 },
311 { 0x4ca09c6d, 0000000000 },
312 { 0xad4c4c4c, 0000000000 },
313 { 0x4ce1af3d, 0000000000 },
314 { 0xd8afafaf, 0000000000 },
315 { 0xd64c4cdc, 0000000000 },
316 { 0x4cd10d10, 0000000000 },
317 { 0x000f0000, 0x00000016 },
318 { 0x362f242d, 0000000000 },
319 { 0x00000012, 0x00000004 },
320 { 0x000f0000, 0x00000016 },
321 { 0x362f282d, 0000000000 },
322 { 0x000380e7, 0x00000002 },
323 { 0x04002c97, 0x00000002 },
324 { 0x000f0001, 0x00000016 },
325 { 0x333a3730, 0000000000 },
326 { 0x000077ef, 0x00000002 },
327 { 0x00061000, 0x00000002 },
328 { 0x00000021, 0x0000001a },
329 { 0x00004000, 0x0000001e },
330 { 0x00061000, 0x00000002 },
331 { 0x00000021, 0x0000001a },
332 { 0x00004000, 0x0000001e },
333 { 0x00061000, 0x00000002 },
334 { 0x00000021, 0x0000001a },
335 { 0x00004000, 0x0000001e },
336 { 0x00000017, 0x00000004 },
337 { 0x0003802b, 0x00000002 },
338 { 0x040067e0, 0x00000002 },
339 { 0x00000017, 0x00000004 },
340 { 0x000077e0, 0x00000002 },
341 { 0x00065000, 0x00000002 },
342 { 0x000037e1, 0x00000002 },
343 { 0x040067e1, 0x00000006 },
344 { 0x000077e0, 0x00000002 },
345 { 0x000077e1, 0x00000002 },
346 { 0x000077e1, 0x00000006 },
347 { 0xffffffff, 0000000000 },
348 { 0x10000000, 0000000000 },
349 { 0x0003802b, 0x00000002 },
350 { 0x040067e0, 0x00000006 },
351 { 0x00007675, 0x00000002 },
352 { 0x00007676, 0x00000002 },
353 { 0x00007677, 0x00000002 },
354 { 0x00007678, 0x00000006 },
355 { 0x0003802c, 0x00000002 },
356 { 0x04002676, 0x00000002 },
357 { 0x00007677, 0x00000002 },
358 { 0x00007678, 0x00000006 },
359 { 0x0000002f, 0x00000018 },
360 { 0x0000002f, 0x00000018 },
361 { 0000000000, 0x00000006 },
362 { 0x00000030, 0x00000018 },
363 { 0x00000030, 0x00000018 },
364 { 0000000000, 0x00000006 },
365 { 0x01605000, 0x00000002 },
366 { 0x00065000, 0x00000002 },
367 { 0x00098000, 0x00000002 },
368 { 0x00061000, 0x00000002 },
369 { 0x64c0603e, 0x00000004 },
370 { 0x000380e6, 0x00000002 },
371 { 0x040025c5, 0x00000002 },
372 { 0x00080000, 0x00000016 },
373 { 0000000000, 0000000000 },
374 { 0x0400251d, 0x00000002 },
375 { 0x00007580, 0x00000002 },
376 { 0x00067581, 0x00000002 },
377 { 0x04002580, 0x00000002 },
378 { 0x00067581, 0x00000002 },
379 { 0x00000049, 0x00000004 },
380 { 0x00005000, 0000000000 },
381 { 0x000380e6, 0x00000002 },
382 { 0x040025c5, 0x00000002 },
383 { 0x00061000, 0x00000002 },
384 { 0x0000750e, 0x00000002 },
385 { 0x00019000, 0x00000002 },
386 { 0x00011055, 0x00000014 },
387 { 0x00000055, 0x00000012 },
388 { 0x0400250f, 0x00000002 },
389 { 0x0000504f, 0x00000004 },
390 { 0x000380e6, 0x00000002 },
391 { 0x040025c5, 0x00000002 },
392 { 0x00007565, 0x00000002 },
393 { 0x00007566, 0x00000002 },
394 { 0x00000058, 0x00000004 },
395 { 0x000380e6, 0x00000002 },
396 { 0x040025c5, 0x00000002 },
397 { 0x01e655b4, 0x00000002 },
398 { 0x4401b0e4, 0x00000002 },
399 { 0x01c110e4, 0x00000002 },
400 { 0x26667066, 0x00000018 },
401 { 0x040c2565, 0x00000002 },
402 { 0x00000066, 0x00000018 },
403 { 0x04002564, 0x00000002 },
404 { 0x00007566, 0x00000002 },
405 { 0x0000005d, 0x00000004 },
406 { 0x00401069, 0x00000008 },
407 { 0x00101000, 0x00000002 },
408 { 0x000d80ff, 0x00000002 },
409 { 0x0080006c, 0x00000008 },
410 { 0x000f9000, 0x00000002 },
411 { 0x000e00ff, 0x00000002 },
412 { 0000000000, 0x00000006 },
413 { 0x0000008f, 0x00000018 },
414 { 0x0000005b, 0x00000004 },
415 { 0x000380e6, 0x00000002 },
416 { 0x040025c5, 0x00000002 },
417 { 0x00007576, 0x00000002 },
418 { 0x00065000, 0x00000002 },
419 { 0x00009000, 0x00000002 },
420 { 0x00041000, 0x00000002 },
421 { 0x0c00350e, 0x00000002 },
422 { 0x00049000, 0x00000002 },
423 { 0x00051000, 0x00000002 },
424 { 0x01e785f8, 0x00000002 },
425 { 0x00200000, 0x00000002 },
426 { 0x0060007e, 0x0000000c },
427 { 0x00007563, 0x00000002 },
428 { 0x006075f0, 0x00000021 },
429 { 0x20007073, 0x00000004 },
430 { 0x00005073, 0x00000004 },
431 { 0x000380e6, 0x00000002 },
432 { 0x040025c5, 0x00000002 },
433 { 0x00007576, 0x00000002 },
434 { 0x00007577, 0x00000002 },
435 { 0x0000750e, 0x00000002 },
436 { 0x0000750f, 0x00000002 },
437 { 0x00a05000, 0x00000002 },
438 { 0x00600083, 0x0000000c },
439 { 0x006075f0, 0x00000021 },
440 { 0x000075f8, 0x00000002 },
441 { 0x00000083, 0x00000004 },
442 { 0x000a750e, 0x00000002 },
443 { 0x000380e6, 0x00000002 },
444 { 0x040025c5, 0x00000002 },
445 { 0x0020750f, 0x00000002 },
446 { 0x00600086, 0x00000004 },
447 { 0x00007570, 0x00000002 },
448 { 0x00007571, 0x00000002 },
449 { 0x00007572, 0x00000006 },
450 { 0x000380e6, 0x00000002 },
451 { 0x040025c5, 0x00000002 },
452 { 0x00005000, 0x00000002 },
453 { 0x00a05000, 0x00000002 },
454 { 0x00007568, 0x00000002 },
455 { 0x00061000, 0x00000002 },
456 { 0x00000095, 0x0000000c },
457 { 0x00058000, 0x00000002 },
458 { 0x0c607562, 0x00000002 },
459 { 0x00000097, 0x00000004 },
460 { 0x000380e6, 0x00000002 },
461 { 0x040025c5, 0x00000002 },
462 { 0x00600096, 0x00000004 },
463 { 0x400070e5, 0000000000 },
464 { 0x000380e6, 0x00000002 },
465 { 0x040025c5, 0x00000002 },
466 { 0x000380e5, 0x00000002 },
467 { 0x000000a8, 0x0000001c },
468 { 0x000650aa, 0x00000018 },
469 { 0x040025bb, 0x00000002 },
470 { 0x000610ab, 0x00000018 },
471 { 0x040075bc, 0000000000 },
472 { 0x000075bb, 0x00000002 },
473 { 0x000075bc, 0000000000 },
474 { 0x00090000, 0x00000006 },
475 { 0x00090000, 0x00000002 },
476 { 0x000d8002, 0x00000006 },
477 { 0x00007832, 0x00000002 },
478 { 0x00005000, 0x00000002 },
479 { 0x000380e7, 0x00000002 },
480 { 0x04002c97, 0x00000002 },
481 { 0x00007820, 0x00000002 },
482 { 0x00007821, 0x00000002 },
483 { 0x00007800, 0000000000 },
484 { 0x01200000, 0x00000002 },
485 { 0x20077000, 0x00000002 },
486 { 0x01200000, 0x00000002 },
487 { 0x20007000, 0x00000002 },
488 { 0x00061000, 0x00000002 },
489 { 0x0120751b, 0x00000002 },
490 { 0x8040750a, 0x00000002 },
491 { 0x8040750b, 0x00000002 },
492 { 0x00110000, 0x00000002 },
493 { 0x000380e5, 0x00000002 },
494 { 0x000000c6, 0x0000001c },
495 { 0x000610ab, 0x00000018 },
496 { 0x844075bd, 0x00000002 },
497 { 0x000610aa, 0x00000018 },
498 { 0x840075bb, 0x00000002 },
499 { 0x000610ab, 0x00000018 },
500 { 0x844075bc, 0x00000002 },
501 { 0x000000c9, 0x00000004 },
502 { 0x804075bd, 0x00000002 },
503 { 0x800075bb, 0x00000002 },
504 { 0x804075bc, 0x00000002 },
505 { 0x00108000, 0x00000002 },
506 { 0x01400000, 0x00000002 },
507 { 0x006000cd, 0x0000000c },
508 { 0x20c07000, 0x00000020 },
509 { 0x000000cf, 0x00000012 },
510 { 0x00800000, 0x00000006 },
511 { 0x0080751d, 0x00000006 },
512 { 0000000000, 0000000000 },
513 { 0x0000775c, 0x00000002 },
514 { 0x00a05000, 0x00000002 },
515 { 0x00661000, 0x00000002 },
516 { 0x0460275d, 0x00000020 },
517 { 0x00004000, 0000000000 },
518 { 0x01e00830, 0x00000002 },
519 { 0x21007000, 0000000000 },
520 { 0x6464614d, 0000000000 },
521 { 0x69687420, 0000000000 },
522 { 0x00000073, 0000000000 },
523 { 0000000000, 0000000000 },
524 { 0x00005000, 0x00000002 },
525 { 0x000380d0, 0x00000002 },
526 { 0x040025e0, 0x00000002 },
527 { 0x000075e1, 0000000000 },
528 { 0x00000001, 0000000000 },
529 { 0x000380e0, 0x00000002 },
530 { 0x04002394, 0x00000002 },
531 { 0x00005000, 0000000000 },
532 { 0000000000, 0000000000 },
533 { 0000000000, 0000000000 },
534 { 0x00000008, 0000000000 },
535 { 0x00000004, 0000000000 },
536 { 0000000000, 0000000000 },
537 { 0000000000, 0000000000 },
538 { 0000000000, 0000000000 },
539 { 0000000000, 0000000000 },
540 { 0000000000, 0000000000 },
541 { 0000000000, 0000000000 },
542 { 0000000000, 0000000000 },
543 { 0000000000, 0000000000 },
544 { 0000000000, 0000000000 },
545 { 0000000000, 0000000000 },
546 { 0000000000, 0000000000 },
547 { 0000000000, 0000000000 },
548 { 0000000000, 0000000000 },
549 { 0000000000, 0000000000 },
550 { 0000000000, 0000000000 },
551 { 0000000000, 0000000000 },
552 { 0000000000, 0000000000 },
553 { 0000000000, 0000000000 },
554 { 0000000000, 0000000000 },
555 { 0000000000, 0000000000 },
556 { 0000000000, 0000000000 },
557 { 0000000000, 0000000000 },
558 { 0000000000, 0000000000 },
559 { 0000000000, 0000000000 },
560};
561
562
563int RADEON_READ_PLL(drm_device_t *dev, int addr)
564{
565 drm_radeon_private_t *dev_priv = dev->dev_private;
566
567 RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
568 return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
569}
570
571#if RADEON_FIFO_DEBUG
572static void radeon_status( drm_radeon_private_t *dev_priv )
573{
574 printk( "%s:\n", __FUNCTION__ );
575 printk( "RBBM_STATUS = 0x%08x\n",
576 (unsigned int)RADEON_READ( RADEON_RBBM_STATUS ) );
577 printk( "CP_RB_RTPR = 0x%08x\n",
578 (unsigned int)RADEON_READ( RADEON_CP_RB_RPTR ) );
579 printk( "CP_RB_WTPR = 0x%08x\n",
580 (unsigned int)RADEON_READ( RADEON_CP_RB_WPTR ) );
581 printk( "AIC_CNTL = 0x%08x\n",
582 (unsigned int)RADEON_READ( RADEON_AIC_CNTL ) );
583 printk( "AIC_STAT = 0x%08x\n",
584 (unsigned int)RADEON_READ( RADEON_AIC_STAT ) );
585 printk( "AIC_PT_BASE = 0x%08x\n",
586 (unsigned int)RADEON_READ( RADEON_AIC_PT_BASE ) );
587 printk( "TLB_ADDR = 0x%08x\n",
588 (unsigned int)RADEON_READ( RADEON_AIC_TLB_ADDR ) );
589 printk( "TLB_DATA = 0x%08x\n",
590 (unsigned int)RADEON_READ( RADEON_AIC_TLB_DATA ) );
591}
592#endif
593
594
595/* ================================================================
596 * Engine, FIFO control
597 */
598
599static int radeon_do_pixcache_flush( drm_radeon_private_t *dev_priv )
600{
601 u32 tmp;
602 int i;
603
604 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
605
606 tmp = RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT );
607 tmp |= RADEON_RB2D_DC_FLUSH_ALL;
608 RADEON_WRITE( RADEON_RB2D_DSTCACHE_CTLSTAT, tmp );
609
610 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
611 if ( !(RADEON_READ( RADEON_RB2D_DSTCACHE_CTLSTAT )
612 & RADEON_RB2D_DC_BUSY) ) {
613 return 0;
614 }
615 DRM_UDELAY( 1 );
616 }
617
618#if RADEON_FIFO_DEBUG
619 DRM_ERROR( "failed!\n" );
620 radeon_status( dev_priv );
621#endif
622 return DRM_ERR(EBUSY);
623}
624
625static int radeon_do_wait_for_fifo( drm_radeon_private_t *dev_priv,
626 int entries )
627{
628 int i;
629
630 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
631
632 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
633 int slots = ( RADEON_READ( RADEON_RBBM_STATUS )
634 & RADEON_RBBM_FIFOCNT_MASK );
635 if ( slots >= entries ) return 0;
636 DRM_UDELAY( 1 );
637 }
638
639#if RADEON_FIFO_DEBUG
640 DRM_ERROR( "failed!\n" );
641 radeon_status( dev_priv );
642#endif
643 return DRM_ERR(EBUSY);
644}
645
646static int radeon_do_wait_for_idle( drm_radeon_private_t *dev_priv )
647{
648 int i, ret;
649
650 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
651
652 ret = radeon_do_wait_for_fifo( dev_priv, 64 );
653 if ( ret ) return ret;
654
655 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
656 if ( !(RADEON_READ( RADEON_RBBM_STATUS )
657 & RADEON_RBBM_ACTIVE) ) {
658 radeon_do_pixcache_flush( dev_priv );
659 return 0;
660 }
661 DRM_UDELAY( 1 );
662 }
663
664#if RADEON_FIFO_DEBUG
665 DRM_ERROR( "failed!\n" );
666 radeon_status( dev_priv );
667#endif
668 return DRM_ERR(EBUSY);
669}
670
671
672/* ================================================================
673 * CP control, initialization
674 */
675
676/* Load the microcode for the CP */
677static void radeon_cp_load_microcode( drm_radeon_private_t *dev_priv )
678{
679 int i;
680 DRM_DEBUG( "\n" );
681
682 radeon_do_wait_for_idle( dev_priv );
683
684 RADEON_WRITE( RADEON_CP_ME_RAM_ADDR, 0 );
685
686 if (dev_priv->is_r200)
687 {
688 DRM_INFO("Loading R200 Microcode\n");
689 for ( i = 0 ; i < 256 ; i++ )
690 {
691 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
692 R200_cp_microcode[i][1] );
693 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
694 R200_cp_microcode[i][0] );
695 }
696 }
697 else
698 {
699 for ( i = 0 ; i < 256 ; i++ ) {
700 RADEON_WRITE( RADEON_CP_ME_RAM_DATAH,
701 radeon_cp_microcode[i][1] );
702 RADEON_WRITE( RADEON_CP_ME_RAM_DATAL,
703 radeon_cp_microcode[i][0] );
704 }
705 }
706}
707
708/* Flush any pending commands to the CP. This should only be used just
709 * prior to a wait for idle, as it informs the engine that the command
710 * stream is ending.
711 */
712static void radeon_do_cp_flush( drm_radeon_private_t *dev_priv )
713{
714 DRM_DEBUG( "\n" );
715#if 0
716 u32 tmp;
717
718 tmp = RADEON_READ( RADEON_CP_RB_WPTR ) | (1 << 31);
719 RADEON_WRITE( RADEON_CP_RB_WPTR, tmp );
720#endif
721}
722
723/* Wait for the CP to go idle.
724 */
725int radeon_do_cp_idle( drm_radeon_private_t *dev_priv )
726{
727 RING_LOCALS;
728 DRM_DEBUG( "\n" );
729
730 BEGIN_RING( 6 );
731
732 RADEON_PURGE_CACHE();
733 RADEON_PURGE_ZCACHE();
734 RADEON_WAIT_UNTIL_IDLE();
735
736 ADVANCE_RING();
737 COMMIT_RING();
738
739 return radeon_do_wait_for_idle( dev_priv );
740}
741
742/* Start the Command Processor.
743 */
744static void radeon_do_cp_start( drm_radeon_private_t *dev_priv )
745{
746 RING_LOCALS;
747 DRM_DEBUG( "\n" );
748
749 radeon_do_wait_for_idle( dev_priv );
750
751 RADEON_WRITE( RADEON_CP_CSQ_CNTL, dev_priv->cp_mode );
752
753 dev_priv->cp_running = 1;
754
755 BEGIN_RING( 6 );
756
757 RADEON_PURGE_CACHE();
758 RADEON_PURGE_ZCACHE();
759 RADEON_WAIT_UNTIL_IDLE();
760
761 ADVANCE_RING();
762 COMMIT_RING();
763}
764
765/* Reset the Command Processor. This will not flush any pending
766 * commands, so you must wait for the CP command stream to complete
767 * before calling this routine.
768 */
769static void radeon_do_cp_reset( drm_radeon_private_t *dev_priv )
770{
771 u32 cur_read_ptr;
772 DRM_DEBUG( "\n" );
773
774 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
775 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
776 SET_RING_HEAD( dev_priv, cur_read_ptr );
777 dev_priv->ring.tail = cur_read_ptr;
778}
779
780/* Stop the Command Processor. This will not flush any pending
781 * commands, so you must flush the command stream and wait for the CP
782 * to go idle before calling this routine.
783 */
784static void radeon_do_cp_stop( drm_radeon_private_t *dev_priv )
785{
786 DRM_DEBUG( "\n" );
787
788 RADEON_WRITE( RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS );
789
790 dev_priv->cp_running = 0;
791}
792
793/* Reset the engine. This will stop the CP if it is running.
794 */
795static int radeon_do_engine_reset( drm_device_t *dev )
796{
797 drm_radeon_private_t *dev_priv = dev->dev_private;
798 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
799 DRM_DEBUG( "\n" );
800
801 radeon_do_pixcache_flush( dev_priv );
802
803 clock_cntl_index = RADEON_READ( RADEON_CLOCK_CNTL_INDEX );
804 mclk_cntl = RADEON_READ_PLL( dev, RADEON_MCLK_CNTL );
805
806 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, ( mclk_cntl |
807 RADEON_FORCEON_MCLKA |
808 RADEON_FORCEON_MCLKB |
809 RADEON_FORCEON_YCLKA |
810 RADEON_FORCEON_YCLKB |
811 RADEON_FORCEON_MC |
812 RADEON_FORCEON_AIC ) );
813
814 rbbm_soft_reset = RADEON_READ( RADEON_RBBM_SOFT_RESET );
815
816 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset |
817 RADEON_SOFT_RESET_CP |
818 RADEON_SOFT_RESET_HI |
819 RADEON_SOFT_RESET_SE |
820 RADEON_SOFT_RESET_RE |
821 RADEON_SOFT_RESET_PP |
822 RADEON_SOFT_RESET_E2 |
823 RADEON_SOFT_RESET_RB ) );
824 RADEON_READ( RADEON_RBBM_SOFT_RESET );
825 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, ( rbbm_soft_reset &
826 ~( RADEON_SOFT_RESET_CP |
827 RADEON_SOFT_RESET_HI |
828 RADEON_SOFT_RESET_SE |
829 RADEON_SOFT_RESET_RE |
830 RADEON_SOFT_RESET_PP |
831 RADEON_SOFT_RESET_E2 |
832 RADEON_SOFT_RESET_RB ) ) );
833 RADEON_READ( RADEON_RBBM_SOFT_RESET );
834
835
836 RADEON_WRITE_PLL( RADEON_MCLK_CNTL, mclk_cntl );
837 RADEON_WRITE( RADEON_CLOCK_CNTL_INDEX, clock_cntl_index );
838 RADEON_WRITE( RADEON_RBBM_SOFT_RESET, rbbm_soft_reset );
839
840 /* Reset the CP ring */
841 radeon_do_cp_reset( dev_priv );
842
843 /* The CP is no longer running after an engine reset */
844 dev_priv->cp_running = 0;
845
846 /* Reset any pending vertex, indirect buffers */
847 radeon_freelist_reset( dev );
848
849 return 0;
850}
851
852static void radeon_cp_init_ring_buffer( drm_device_t *dev,
853 drm_radeon_private_t *dev_priv )
854{
855 u32 ring_start, cur_read_ptr;
856 u32 tmp;
857
858 /* Initialize the memory controller */
859 RADEON_WRITE( RADEON_MC_FB_LOCATION,
860 (dev_priv->agp_vm_start - 1) & 0xffff0000 );
861
862 if ( !dev_priv->is_pci ) {
863 RADEON_WRITE( RADEON_MC_AGP_LOCATION,
864 (((dev_priv->agp_vm_start - 1 +
865 dev_priv->agp_size) & 0xffff0000) |
866 (dev_priv->agp_vm_start >> 16)) );
867 }
868
869#if __REALLY_HAVE_AGP
870 if ( !dev_priv->is_pci )
871 ring_start = (dev_priv->cp_ring->offset
872 - dev->agp->base
873 + dev_priv->agp_vm_start);
874 else
875#endif
876 ring_start = (dev_priv->cp_ring->offset
877 - dev->sg->handle
878 + dev_priv->agp_vm_start);
879
880 RADEON_WRITE( RADEON_CP_RB_BASE, ring_start );
881
882 /* Set the write pointer delay */
883 RADEON_WRITE( RADEON_CP_RB_WPTR_DELAY, 0 );
884
885 /* Initialize the ring buffer's read and write pointers */
886 cur_read_ptr = RADEON_READ( RADEON_CP_RB_RPTR );
887 RADEON_WRITE( RADEON_CP_RB_WPTR, cur_read_ptr );
888 SET_RING_HEAD( dev_priv, cur_read_ptr );
889 dev_priv->ring.tail = cur_read_ptr;
890
891#if __REALLY_HAVE_AGP
892 if ( !dev_priv->is_pci ) {
893 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
894 dev_priv->ring_rptr->offset
895 - dev->agp->base
896 + dev_priv->agp_vm_start);
897 } else
898#endif
899 {
900 drm_sg_mem_t *entry = dev->sg;
901 unsigned long tmp_ofs, page_ofs;
902
903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
904 page_ofs = tmp_ofs >> PAGE_SHIFT;
905
906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
907 entry->busaddr[page_ofs]);
908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
909 entry->busaddr[page_ofs],
910 entry->handle + tmp_ofs );
911 }
912
913 /* Initialize the scratch register pointer. This will cause
914 * the scratch register values to be written out to memory
915 * whenever they are updated.
916 *
917 * We simply put this behind the ring read pointer, this works
918 * with PCI GART as well as (whatever kind of) AGP GART
919 */
920 RADEON_WRITE( RADEON_SCRATCH_ADDR, RADEON_READ( RADEON_CP_RB_RPTR_ADDR )
921 + RADEON_SCRATCH_REG_OFFSET );
922
923 dev_priv->scratch = ((__volatile__ u32 *)
924 dev_priv->ring_rptr->handle +
925 (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
926
927 RADEON_WRITE( RADEON_SCRATCH_UMSK, 0x7 );
928
929 /* Writeback doesn't seem to work everywhere, test it first */
930 DRM_WRITE32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0 );
931 RADEON_WRITE( RADEON_SCRATCH_REG1, 0xdeadbeef );
932
933 for ( tmp = 0 ; tmp < dev_priv->usec_timeout ; tmp++ ) {
934 if ( DRM_READ32( dev_priv->ring_rptr, RADEON_SCRATCHOFF(1) ) == 0xdeadbeef )
935 break;
936 DRM_UDELAY( 1 );
937 }
938
939 if ( tmp < dev_priv->usec_timeout ) {
940 dev_priv->writeback_works = 1;
941 DRM_DEBUG( "writeback test succeeded, tmp=%d\n", tmp );
942 } else {
943 dev_priv->writeback_works = 0;
944 DRM_DEBUG( "writeback test failed\n" );
945 }
946
947 dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
948 RADEON_WRITE( RADEON_LAST_FRAME_REG,
949 dev_priv->sarea_priv->last_frame );
950
951 dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
952 RADEON_WRITE( RADEON_LAST_DISPATCH_REG,
953 dev_priv->sarea_priv->last_dispatch );
954
955 dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
956 RADEON_WRITE( RADEON_LAST_CLEAR_REG,
957 dev_priv->sarea_priv->last_clear );
958
959 /* Set ring buffer size */
960#ifdef __BIG_ENDIAN
961 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw | RADEON_BUF_SWAP_32BIT );
962#else
963 RADEON_WRITE( RADEON_CP_RB_CNTL, dev_priv->ring.size_l2qw );
964#endif
965
966 radeon_do_wait_for_idle( dev_priv );
967
968 /* Turn on bus mastering */
969 tmp = RADEON_READ( RADEON_BUS_CNTL ) & ~RADEON_BUS_MASTER_DIS;
970 RADEON_WRITE( RADEON_BUS_CNTL, tmp );
971
972 /* Sync everything up */
973 RADEON_WRITE( RADEON_ISYNC_CNTL,
974 (RADEON_ISYNC_ANY2D_IDLE3D |
975 RADEON_ISYNC_ANY3D_IDLE2D |
976 RADEON_ISYNC_WAIT_IDLEGUI |
977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978}
979
980static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
981{
982 drm_radeon_private_t *dev_priv;
983 u32 tmp;
984 DRM_DEBUG( "\n" );
985
986 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
987 if ( dev_priv == NULL )
988 return DRM_ERR(ENOMEM);
989
990 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
991
992 dev_priv->is_pci = init->is_pci;
993
994 if ( dev_priv->is_pci && !dev->sg ) {
995 DRM_ERROR( "PCI GART memory not allocated!\n" );
996 dev->dev_private = (void *)dev_priv;
997 radeon_do_cleanup_cp(dev);
998 return DRM_ERR(EINVAL);
999 }
1000
1001 dev_priv->usec_timeout = init->usec_timeout;
1002 if ( dev_priv->usec_timeout < 1 ||
1003 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT ) {
1004 DRM_DEBUG( "TIMEOUT problem!\n" );
1005 dev->dev_private = (void *)dev_priv;
1006 radeon_do_cleanup_cp(dev);
1007 return DRM_ERR(EINVAL);
1008 }
1009
1010 dev_priv->is_r200 = (init->func == RADEON_INIT_R200_CP);
1011 dev_priv->do_boxes = 0;
1012 dev_priv->cp_mode = init->cp_mode;
1013
1014 /* We don't support anything other than bus-mastering ring mode,
1015 * but the ring can be in either AGP or PCI space for the ring
1016 * read pointer.
1017 */
1018 if ( ( init->cp_mode != RADEON_CSQ_PRIBM_INDDIS ) &&
1019 ( init->cp_mode != RADEON_CSQ_PRIBM_INDBM ) ) {
1020 DRM_DEBUG( "BAD cp_mode (%x)!\n", init->cp_mode );
1021 dev->dev_private = (void *)dev_priv;
1022 radeon_do_cleanup_cp(dev);
1023 return DRM_ERR(EINVAL);
1024 }
1025
1026 switch ( init->fb_bpp ) {
1027 case 16:
1028 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1029 break;
1030 case 32:
1031 default:
1032 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1033 break;
1034 }
1035 dev_priv->front_offset = init->front_offset;
1036 dev_priv->front_pitch = init->front_pitch;
1037 dev_priv->back_offset = init->back_offset;
1038 dev_priv->back_pitch = init->back_pitch;
1039
1040 switch ( init->depth_bpp ) {
1041 case 16:
1042 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1043 break;
1044 case 32:
1045 default:
1046 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1047 break;
1048 }
1049 dev_priv->depth_offset = init->depth_offset;
1050 dev_priv->depth_pitch = init->depth_pitch;
1051
1052 dev_priv->front_pitch_offset = (((dev_priv->front_pitch/64) << 22) |
1053 (dev_priv->front_offset >> 10));
1054 dev_priv->back_pitch_offset = (((dev_priv->back_pitch/64) << 22) |
1055 (dev_priv->back_offset >> 10));
1056 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch/64) << 22) |
1057 (dev_priv->depth_offset >> 10));
1058
1059 /* Hardware state for depth clears. Remove this if/when we no
1060 * longer clear the depth buffer with a 3D rectangle. Hard-code
1061 * all values to prevent unwanted 3D state from slipping through
1062 * and screwing with the clear operation.
1063 */
1064 dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1065 (dev_priv->color_fmt << 10) |
1066 (1<<15));
1067
1068 dev_priv->depth_clear.rb3d_zstencilcntl =
1069 (dev_priv->depth_fmt |
1070 RADEON_Z_TEST_ALWAYS |
1071 RADEON_STENCIL_TEST_ALWAYS |
1072 RADEON_STENCIL_S_FAIL_REPLACE |
1073 RADEON_STENCIL_ZPASS_REPLACE |
1074 RADEON_STENCIL_ZFAIL_REPLACE |
1075 RADEON_Z_WRITE_ENABLE);
1076
1077 dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1078 RADEON_BFACE_SOLID |
1079 RADEON_FFACE_SOLID |
1080 RADEON_FLAT_SHADE_VTX_LAST |
1081 RADEON_DIFFUSE_SHADE_FLAT |
1082 RADEON_ALPHA_SHADE_FLAT |
1083 RADEON_SPECULAR_SHADE_FLAT |
1084 RADEON_FOG_SHADE_FLAT |
1085 RADEON_VTX_PIX_CENTER_OGL |
1086 RADEON_ROUND_MODE_TRUNC |
1087 RADEON_ROUND_PREC_8TH_PIX);
1088
1089 DRM_GETSAREA();
1090
1091 dev_priv->fb_offset = init->fb_offset;
1092 dev_priv->mmio_offset = init->mmio_offset;
1093 dev_priv->ring_offset = init->ring_offset;
1094 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1095 dev_priv->buffers_offset = init->buffers_offset;
1096 dev_priv->agp_textures_offset = init->agp_textures_offset;
1097
1098 if(!dev_priv->sarea) {
1099 DRM_ERROR("could not find sarea!\n");
1100 dev->dev_private = (void *)dev_priv;
1101 radeon_do_cleanup_cp(dev);
1102 return DRM_ERR(EINVAL);
1103 }
1104
1105 DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
1106 if(!dev_priv->fb) {
1107 DRM_ERROR("could not find framebuffer!\n");
1108 dev->dev_private = (void *)dev_priv;
1109 radeon_do_cleanup_cp(dev);
1110 return DRM_ERR(EINVAL);
1111 }
1112 DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
1113 if(!dev_priv->mmio) {
1114 DRM_ERROR("could not find mmio region!\n");
1115 dev->dev_private = (void *)dev_priv;
1116 radeon_do_cleanup_cp(dev);
1117 return DRM_ERR(EINVAL);
1118 }
1119 DRM_FIND_MAP( dev_priv->cp_ring, init->ring_offset );
1120 if(!dev_priv->cp_ring) {
1121 DRM_ERROR("could not find cp ring region!\n");
1122 dev->dev_private = (void *)dev_priv;
1123 radeon_do_cleanup_cp(dev);
1124 return DRM_ERR(EINVAL);
1125 }
1126 DRM_FIND_MAP( dev_priv->ring_rptr, init->ring_rptr_offset );
1127 if(!dev_priv->ring_rptr) {
1128 DRM_ERROR("could not find ring read pointer!\n");
1129 dev->dev_private = (void *)dev_priv;
1130 radeon_do_cleanup_cp(dev);
1131 return DRM_ERR(EINVAL);
1132 }
1133 DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
1134 if(!dev_priv->buffers) {
1135 DRM_ERROR("could not find dma buffer region!\n");
1136 dev->dev_private = (void *)dev_priv;
1137 radeon_do_cleanup_cp(dev);
1138 return DRM_ERR(EINVAL);
1139 }
1140
1141 if ( !dev_priv->is_pci ) {
1142 DRM_FIND_MAP( dev_priv->agp_textures,
1143 init->agp_textures_offset );
1144 if(!dev_priv->agp_textures) {
1145 DRM_ERROR("could not find agp texture region!\n");
1146 dev->dev_private = (void *)dev_priv;
1147 radeon_do_cleanup_cp(dev);
1148 return DRM_ERR(EINVAL);
1149 }
1150 }
1151
1152 dev_priv->sarea_priv =
1153 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1154 init->sarea_priv_offset);
1155
1156 if ( !dev_priv->is_pci ) {
1157 DRM_IOREMAP( dev_priv->cp_ring );
1158 DRM_IOREMAP( dev_priv->ring_rptr );
1159 DRM_IOREMAP( dev_priv->buffers );
1160 if(!dev_priv->cp_ring->handle ||
1161 !dev_priv->ring_rptr->handle ||
1162 !dev_priv->buffers->handle) {
1163 DRM_ERROR("could not find ioremap agp regions!\n");
1164 dev->dev_private = (void *)dev_priv;
1165 radeon_do_cleanup_cp(dev);
1166 return DRM_ERR(EINVAL);
1167 }
1168 } else {
1169 dev_priv->cp_ring->handle =
1170 (void *)dev_priv->cp_ring->offset;
1171 dev_priv->ring_rptr->handle =
1172 (void *)dev_priv->ring_rptr->offset;
1173 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1174
1175 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1176 dev_priv->cp_ring->handle );
1177 DRM_DEBUG( "dev_priv->ring_rptr->handle %p\n",
1178 dev_priv->ring_rptr->handle );
1179 DRM_DEBUG( "dev_priv->buffers->handle %p\n",
1180 dev_priv->buffers->handle );
1181 }
1182
1183
1184 dev_priv->agp_size = init->agp_size;
1185 dev_priv->agp_vm_start = RADEON_READ( RADEON_CONFIG_APER_SIZE );
1186#if __REALLY_HAVE_AGP
1187 if ( !dev_priv->is_pci )
1188 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1189 - dev->agp->base
1190 + dev_priv->agp_vm_start);
1191 else
1192#endif
1193 dev_priv->agp_buffers_offset = (dev_priv->buffers->offset
1194 - dev->sg->handle
1195 + dev_priv->agp_vm_start);
1196
1197 DRM_DEBUG( "dev_priv->agp_size %d\n",
1198 dev_priv->agp_size );
1199 DRM_DEBUG( "dev_priv->agp_vm_start 0x%x\n",
1200 dev_priv->agp_vm_start );
1201 DRM_DEBUG( "dev_priv->agp_buffers_offset 0x%lx\n",
1202 dev_priv->agp_buffers_offset );
1203
1204 dev_priv->ring.start = (u32 *)dev_priv->cp_ring->handle;
1205 dev_priv->ring.end = ((u32 *)dev_priv->cp_ring->handle
1206 + init->ring_size / sizeof(u32));
1207 dev_priv->ring.size = init->ring_size;
1208 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1209
1210 dev_priv->ring.tail_mask =
1211 (dev_priv->ring.size / sizeof(u32)) - 1;
1212
1213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1214
1215#if __REALLY_HAVE_SG
1216 if ( dev_priv->is_pci ) {
1217 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1218 &dev_priv->bus_pci_gart)) {
1219 DRM_ERROR( "failed to init PCI GART!\n" );
1220 dev->dev_private = (void *)dev_priv;
1221 radeon_do_cleanup_cp(dev);
1222 return DRM_ERR(ENOMEM);
1223 }
1224 /* Turn on PCI GART
1225 */
1226 tmp = RADEON_READ( RADEON_AIC_CNTL )
1227 | RADEON_PCIGART_TRANSLATE_EN;
1228 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1229
1230 /* set PCI GART page-table base address
1231 */
1232 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1233
1234 /* set address range for PCI address translate
1235 */
1236 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1237 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1238 + dev_priv->agp_size - 1);
1239
1240 /* Turn off AGP aperture -- is this required for PCIGART?
1241 */
1242 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1243 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1244 } else {
1245#endif /* __REALLY_HAVE_SG */
1246 /* Turn off PCI GART
1247 */
1248 tmp = RADEON_READ( RADEON_AIC_CNTL )
1249 & ~RADEON_PCIGART_TRANSLATE_EN;
1250 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1251#if __REALLY_HAVE_SG
1252 }
1253#endif /* __REALLY_HAVE_SG */
1254
1255 radeon_cp_load_microcode( dev_priv );
1256 radeon_cp_init_ring_buffer( dev, dev_priv );
1257
1258 dev_priv->last_buf = 0;
1259
1260 dev->dev_private = (void *)dev_priv;
1261
1262 radeon_do_engine_reset( dev );
1263
1264 return 0;
1265}
1266
1267int radeon_do_cleanup_cp( drm_device_t *dev )
1268{
1269 DRM_DEBUG( "\n" );
1270
1271 if ( dev->dev_private ) {
1272 drm_radeon_private_t *dev_priv = dev->dev_private;
1273
1274 if ( !dev_priv->is_pci ) {
1275 if ( dev_priv->cp_ring != NULL )
1276 DRM_IOREMAPFREE( dev_priv->cp_ring );
1277 if ( dev_priv->ring_rptr != NULL )
1278 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1279 if ( dev_priv->buffers != NULL )
1280 DRM_IOREMAPFREE( dev_priv->buffers );
1281 } else {
1282#if __REALLY_HAVE_SG
1283 if (!DRM(ati_pcigart_cleanup)( dev,
1284 dev_priv->phys_pci_gart,
1285 dev_priv->bus_pci_gart ))
1286 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1287#endif /* __REALLY_HAVE_SG */
1288 }
1289
1290 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1291 DRM_MEM_DRIVER );
1292 dev->dev_private = NULL;
1293 }
1294
1295 return 0;
1296}
1297
1298int radeon_cp_init( DRM_IOCTL_ARGS )
1299{
1300 DRM_DEVICE;
1301 drm_radeon_init_t init;
1302
1303 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1304
1305 switch ( init.func ) {
1306 case RADEON_INIT_CP:
1307 case RADEON_INIT_R200_CP:
1308 return radeon_do_init_cp( dev, &init );
1309 case RADEON_CLEANUP_CP:
1310 return radeon_do_cleanup_cp( dev );
1311 }
1312
1313 return DRM_ERR(EINVAL);
1314}
1315
1316int radeon_cp_start( DRM_IOCTL_ARGS )
1317{
1318 DRM_DEVICE;
1319 drm_radeon_private_t *dev_priv = dev->dev_private;
1320 DRM_DEBUG( "\n" );
1321
1322 LOCK_TEST_WITH_RETURN( dev, filp );
1323
1324 if ( dev_priv->cp_running ) {
1325 DRM_DEBUG( "%s while CP running\n", __FUNCTION__ );
1326 return 0;
1327 }
1328 if ( dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS ) {
1329 DRM_DEBUG( "%s called with bogus CP mode (%d)\n",
1330 __FUNCTION__, dev_priv->cp_mode );
1331 return 0;
1332 }
1333
1334 radeon_do_cp_start( dev_priv );
1335
1336 return 0;
1337}
1338
1339/* Stop the CP. The engine must have been idled before calling this
1340 * routine.
1341 */
1342int radeon_cp_stop( DRM_IOCTL_ARGS )
1343{
1344 DRM_DEVICE;
1345 drm_radeon_private_t *dev_priv = dev->dev_private;
1346 drm_radeon_cp_stop_t stop;
1347 int ret;
1348 DRM_DEBUG( "\n" );
1349
1350 LOCK_TEST_WITH_RETURN( dev, filp );
1351
1352 DRM_COPY_FROM_USER_IOCTL( stop, (drm_radeon_cp_stop_t *)data, sizeof(stop) );
1353
1354 if (!dev_priv->cp_running)
1355 return 0;
1356
1357 /* Flush any pending CP commands. This ensures any outstanding
1358 * commands are exectuted by the engine before we turn it off.
1359 */
1360 if ( stop.flush ) {
1361 radeon_do_cp_flush( dev_priv );
1362 }
1363
1364 /* If we fail to make the engine go idle, we return an error
1365 * code so that the DRM ioctl wrapper can try again.
1366 */
1367 if ( stop.idle ) {
1368 ret = radeon_do_cp_idle( dev_priv );
1369 if ( ret ) return ret;
1370 }
1371
1372 /* Finally, we can turn off the CP. If the engine isn't idle,
1373 * we will get some dropped triangles as they won't be fully
1374 * rendered before the CP is shut down.
1375 */
1376 radeon_do_cp_stop( dev_priv );
1377
1378 /* Reset the engine */
1379 radeon_do_engine_reset( dev );
1380
1381 return 0;
1382}
1383
1384
1385void radeon_do_release( drm_device_t *dev )
1386{
1387 drm_radeon_private_t *dev_priv = dev->dev_private;
1388 int ret;
1389
1390 if (dev_priv) {
1391 if (dev_priv->cp_running) {
1392 /* Stop the cp */
1393 while ((ret = radeon_do_cp_idle( dev_priv )) != 0) {
1394 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1395#ifdef __linux__
1396 schedule();
1397#else
1398 tsleep(&ret, PZERO, "rdnrel", 1);
1399#endif
1400 }
1401 radeon_do_cp_stop( dev_priv );
1402 radeon_do_engine_reset( dev );
1403 }
1404
1405 /* Disable *all* interrupts */
1406 RADEON_WRITE( RADEON_GEN_INT_CNTL, 0 );
1407
1408 /* Free memory heap structures */
1409 radeon_mem_takedown( &(dev_priv->agp_heap) );
1410 radeon_mem_takedown( &(dev_priv->fb_heap) );
1411
1412 /* deallocate kernel resources */
1413 radeon_do_cleanup_cp( dev );
1414 }
1415}
1416
1417/* Just reset the CP ring. Called as part of an X Server engine reset.
1418 */
1419int radeon_cp_reset( DRM_IOCTL_ARGS )
1420{
1421 DRM_DEVICE;
1422 drm_radeon_private_t *dev_priv = dev->dev_private;
1423 DRM_DEBUG( "\n" );
1424
1425 LOCK_TEST_WITH_RETURN( dev, filp );
1426
1427 if ( !dev_priv ) {
1428 DRM_DEBUG( "%s called before init done\n", __FUNCTION__ );
1429 return DRM_ERR(EINVAL);
1430 }
1431
1432 radeon_do_cp_reset( dev_priv );
1433
1434 /* The CP is no longer running after an engine reset */
1435 dev_priv->cp_running = 0;
1436
1437 return 0;
1438}
1439
1440int radeon_cp_idle( DRM_IOCTL_ARGS )
1441{
1442 DRM_DEVICE;
1443 drm_radeon_private_t *dev_priv = dev->dev_private;
1444 DRM_DEBUG( "\n" );
1445
1446 LOCK_TEST_WITH_RETURN( dev, filp );
1447
1448 return radeon_do_cp_idle( dev_priv );
1449}
1450
1451int radeon_engine_reset( DRM_IOCTL_ARGS )
1452{
1453 DRM_DEVICE;
1454 DRM_DEBUG( "\n" );
1455
1456 LOCK_TEST_WITH_RETURN( dev, filp );
1457
1458 return radeon_do_engine_reset( dev );
1459}
1460
1461
1462/* ================================================================
1463 * Fullscreen mode
1464 */
1465
1466/* KW: Deprecated to say the least:
1467 */
1468int radeon_fullscreen( DRM_IOCTL_ARGS )
1469{
1470 return 0;
1471}
1472
1473
1474/* ================================================================
1475 * Freelist management
1476 */
1477
1478/* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1479 * bufs until freelist code is used. Note this hides a problem with
1480 * the scratch register * (used to keep track of last buffer
1481 * completed) being written to before * the last buffer has actually
1482 * completed rendering.
1483 *
1484 * KW: It's also a good way to find free buffers quickly.
1485 *
1486 * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1487 * sleep. However, bugs in older versions of radeon_accel.c mean that
1488 * we essentially have to do this, else old clients will break.
1489 *
1490 * However, it does leave open a potential deadlock where all the
1491 * buffers are held by other clients, which can't release them because
1492 * they can't get the lock.
1493 */
1494
1495drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1496{
1497 drm_device_dma_t *dma = dev->dma;
1498 drm_radeon_private_t *dev_priv = dev->dev_private;
1499 drm_radeon_buf_priv_t *buf_priv;
1500 drm_buf_t *buf;
1501 int i, t;
1502 int start;
1503
1504 if ( ++dev_priv->last_buf >= dma->buf_count )
1505 dev_priv->last_buf = 0;
1506
1507 start = dev_priv->last_buf;
1508
1509 for ( t = 0 ; t < dev_priv->usec_timeout ; t++ ) {
1510 u32 done_age = GET_SCRATCH( 1 );
1511 DRM_DEBUG("done_age = %d\n",done_age);
1512 for ( i = start ; i < dma->buf_count ; i++ ) {
1513 buf = dma->buflist[i];
1514 buf_priv = buf->dev_private;
1515 if ( buf->filp == 0 || (buf->pending &&
1516 buf_priv->age <= done_age) ) {
1517 dev_priv->stats.requested_bufs++;
1518 buf->pending = 0;
1519 return buf;
1520 }
1521 start = 0;
1522 }
1523
1524 if (t) {
1525 DRM_UDELAY( 1 );
1526 dev_priv->stats.freelist_loops++;
1527 }
1528 }
1529
1530 DRM_DEBUG( "returning NULL!\n" );
1531 return NULL;
1532}
1533#if 0
1534drm_buf_t *radeon_freelist_get( drm_device_t *dev )
1535{
1536 drm_device_dma_t *dma = dev->dma;
1537 drm_radeon_private_t *dev_priv = dev->dev_private;
1538 drm_radeon_buf_priv_t *buf_priv;
1539 drm_buf_t *buf;
1540 int i, t;
1541 int start;
1542 u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1543
1544 if ( ++dev_priv->last_buf >= dma->buf_count )
1545 dev_priv->last_buf = 0;
1546
1547 start = dev_priv->last_buf;
1548 dev_priv->stats.freelist_loops++;
1549
1550 for ( t = 0 ; t < 2 ; t++ ) {
1551 for ( i = start ; i < dma->buf_count ; i++ ) {
1552 buf = dma->buflist[i];
1553 buf_priv = buf->dev_private;
1554 if ( buf->filp == 0 || (buf->pending &&
1555 buf_priv->age <= done_age) ) {
1556 dev_priv->stats.requested_bufs++;
1557 buf->pending = 0;
1558 return buf;
1559 }
1560 }
1561 start = 0;
1562 }
1563
1564 return NULL;
1565}
1566#endif
1567
1568void radeon_freelist_reset( drm_device_t *dev )
1569{
1570 drm_device_dma_t *dma = dev->dma;
1571 drm_radeon_private_t *dev_priv = dev->dev_private;
1572 int i;
1573
1574 dev_priv->last_buf = 0;
1575 for ( i = 0 ; i < dma->buf_count ; i++ ) {
1576 drm_buf_t *buf = dma->buflist[i];
1577 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1578 buf_priv->age = 0;
1579 }
1580}
1581
1582
1583/* ================================================================
1584 * CP command submission
1585 */
1586
1587int radeon_wait_ring( drm_radeon_private_t *dev_priv, int n )
1588{
1589 drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1590 int i;
1591 u32 last_head = GET_RING_HEAD( dev_priv );
1592
1593 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) {
1594 u32 head = GET_RING_HEAD( dev_priv );
1595
1596 ring->space = (head - ring->tail) * sizeof(u32);
1597 if ( ring->space <= 0 )
1598 ring->space += ring->size;
1599 if ( ring->space > n )
1600 return 0;
1601
1602 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1603
1604 if (head != last_head)
1605 i = 0;
1606 last_head = head;
1607
1608 DRM_UDELAY( 1 );
1609 }
1610
1611 /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1612#if RADEON_FIFO_DEBUG
1613 radeon_status( dev_priv );
1614 DRM_ERROR( "failed!\n" );
1615#endif
1616 return DRM_ERR(EBUSY);
1617}
1618
1619static int radeon_cp_get_buffers( DRMFILE filp, drm_device_t *dev, drm_dma_t *d )
1620{
1621 int i;
1622 drm_buf_t *buf;
1623
1624 for ( i = d->granted_count ; i < d->request_count ; i++ ) {
1625 buf = radeon_freelist_get( dev );
1626 if ( !buf ) return DRM_ERR(EBUSY); /* NOTE: broken client */
1627
1628 buf->filp = filp;
1629
1630 if ( DRM_COPY_TO_USER( &d->request_indices[i], &buf->idx,
1631 sizeof(buf->idx) ) )
1632 return DRM_ERR(EFAULT);
1633 if ( DRM_COPY_TO_USER( &d->request_sizes[i], &buf->total,
1634 sizeof(buf->total) ) )
1635 return DRM_ERR(EFAULT);
1636
1637 d->granted_count++;
1638 }
1639 return 0;
1640}
1641
1642int radeon_cp_buffers( DRM_IOCTL_ARGS )
1643{
1644 DRM_DEVICE;
1645 drm_device_dma_t *dma = dev->dma;
1646 int ret = 0;
1647 drm_dma_t d;
1648
1649 LOCK_TEST_WITH_RETURN( dev, filp );
1650
1651 DRM_COPY_FROM_USER_IOCTL( d, (drm_dma_t *)data, sizeof(d) );
1652
1653 /* Please don't send us buffers.
1654 */
1655 if ( d.send_count != 0 ) {
1656 DRM_ERROR( "Process %d trying to send %d buffers via drmDMA\n",
1657 DRM_CURRENTPID, d.send_count );
1658 return DRM_ERR(EINVAL);
1659 }
1660
1661 /* We'll send you buffers.
1662 */
1663 if ( d.request_count < 0 || d.request_count > dma->buf_count ) {
1664 DRM_ERROR( "Process %d trying to get %d buffers (of %d max)\n",
1665 DRM_CURRENTPID, d.request_count, dma->buf_count );
1666 return DRM_ERR(EINVAL);
1667 }
1668
1669 d.granted_count = 0;
1670
1671 if ( d.request_count ) {
1672 ret = radeon_cp_get_buffers( filp, dev, &d );
1673 }
1674
1675 DRM_COPY_TO_USER_IOCTL( (drm_dma_t *)data, d, sizeof(d) );
1676
1677 return ret;
1678}