1/* radeon_cp.c -- CP support for Radeon -*- linux-c -*-
2 *
3 * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4 * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5 * All Rights Reserved.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the "Software"),

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22 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
24 * DEALINGS IN THE SOFTWARE.
25 *
26 * Authors:
27 * Kevin E. Martin <martin@valinux.com>
28 * Gareth Hughes <gareth@valinux.com>
29 *
30 * $FreeBSD: head/sys/dev/drm/radeon_cp.c 113995 2003-04-25 01:18:47Z anholt $
31 */
32
33#include "dev/drm/radeon.h"
34#include "dev/drm/drmP.h"
35#include "dev/drm/drm.h"
36#include "dev/drm/radeon_drm.h"
37#include "dev/drm/radeon_drv.h"
38

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901 unsigned long tmp_ofs, page_ofs;
902
903 tmp_ofs = dev_priv->ring_rptr->offset - dev->sg->handle;
904 page_ofs = tmp_ofs >> PAGE_SHIFT;
905
906 RADEON_WRITE( RADEON_CP_RB_RPTR_ADDR,
907 entry->busaddr[page_ofs]);
908 DRM_DEBUG( "ring rptr: offset=0x%08lx handle=0x%08lx\n",
909 entry->busaddr[page_ofs],
910 entry->handle + tmp_ofs );
911 }
912
913 /* Initialize the scratch register pointer. This will cause
914 * the scratch register values to be written out to memory
915 * whenever they are updated.
916 *
917 * We simply put this behind the ring read pointer, this works

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972 /* Sync everything up */
973 RADEON_WRITE( RADEON_ISYNC_CNTL,
974 (RADEON_ISYNC_ANY2D_IDLE3D |
975 RADEON_ISYNC_ANY3D_IDLE2D |
976 RADEON_ISYNC_WAIT_IDLEGUI |
977 RADEON_ISYNC_CPSCRATCH_IDLEGUI) );
978}
979
980static int radeon_do_init_cp( drm_device_t *dev, drm_radeon_init_t *init )
981{
982 drm_radeon_private_t *dev_priv;
983 u32 tmp;
984 DRM_DEBUG( "\n" );
985
986 dev_priv = DRM(alloc)( sizeof(drm_radeon_private_t), DRM_MEM_DRIVER );
987 if ( dev_priv == NULL )
988 return DRM_ERR(ENOMEM);
989
990 memset( dev_priv, 0, sizeof(drm_radeon_private_t) );
991

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1148 return DRM_ERR(EINVAL);
1149 }
1150 }
1151
1152 dev_priv->sarea_priv =
1153 (drm_radeon_sarea_t *)((u8 *)dev_priv->sarea->handle +
1154 init->sarea_priv_offset);
1155
1156 if ( !dev_priv->is_pci ) {
1157 DRM_IOREMAP( dev_priv->cp_ring );
1158 DRM_IOREMAP( dev_priv->ring_rptr );
1159 DRM_IOREMAP( dev_priv->buffers );
1160 if(!dev_priv->cp_ring->handle ||
1161 !dev_priv->ring_rptr->handle ||
1162 !dev_priv->buffers->handle) {
1163 DRM_ERROR("could not find ioremap agp regions!\n");
1164 dev->dev_private = (void *)dev_priv;
1165 radeon_do_cleanup_cp(dev);
1166 return DRM_ERR(EINVAL);
1167 }
1168 } else {
1169 dev_priv->cp_ring->handle =
1170 (void *)dev_priv->cp_ring->offset;
1171 dev_priv->ring_rptr->handle =
1172 (void *)dev_priv->ring_rptr->offset;
1173 dev_priv->buffers->handle = (void *)dev_priv->buffers->offset;
1174
1175 DRM_DEBUG( "dev_priv->cp_ring->handle %p\n",
1176 dev_priv->cp_ring->handle );

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1207 dev_priv->ring.size = init->ring_size;
1208 dev_priv->ring.size_l2qw = DRM(order)( init->ring_size / 8 );
1209
1210 dev_priv->ring.tail_mask =
1211 (dev_priv->ring.size / sizeof(u32)) - 1;
1212
1213 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1214
1215#if __REALLY_HAVE_SG
1216 if ( dev_priv->is_pci ) {
1217 if (!DRM(ati_pcigart_init)( dev, &dev_priv->phys_pci_gart,
1218 &dev_priv->bus_pci_gart)) {
1219 DRM_ERROR( "failed to init PCI GART!\n" );
1220 dev->dev_private = (void *)dev_priv;
1221 radeon_do_cleanup_cp(dev);
1222 return DRM_ERR(ENOMEM);
1223 }
1224 /* Turn on PCI GART
1225 */
1226 tmp = RADEON_READ( RADEON_AIC_CNTL )
1227 | RADEON_PCIGART_TRANSLATE_EN;
1228 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1229
1230 /* set PCI GART page-table base address
1231 */
1232 RADEON_WRITE( RADEON_AIC_PT_BASE, dev_priv->bus_pci_gart );
1233
1234 /* set address range for PCI address translate
1235 */
1236 RADEON_WRITE( RADEON_AIC_LO_ADDR, dev_priv->agp_vm_start );
1237 RADEON_WRITE( RADEON_AIC_HI_ADDR, dev_priv->agp_vm_start
1238 + dev_priv->agp_size - 1);
1239
1240 /* Turn off AGP aperture -- is this required for PCIGART?
1241 */
1242 RADEON_WRITE( RADEON_MC_AGP_LOCATION, 0xffffffc0 ); /* ?? */
1243 RADEON_WRITE( RADEON_AGP_COMMAND, 0 ); /* clear AGP_COMMAND */
1244 } else {
1245#endif /* __REALLY_HAVE_SG */
1246 /* Turn off PCI GART
1247 */
1248 tmp = RADEON_READ( RADEON_AIC_CNTL )
1249 & ~RADEON_PCIGART_TRANSLATE_EN;
1250 RADEON_WRITE( RADEON_AIC_CNTL, tmp );
1251#if __REALLY_HAVE_SG
1252 }
1253#endif /* __REALLY_HAVE_SG */
1254
1255 radeon_cp_load_microcode( dev_priv );
1256 radeon_cp_init_ring_buffer( dev, dev_priv );
1257
1258 dev_priv->last_buf = 0;
1259
1260 dev->dev_private = (void *)dev_priv;
1261
1262 radeon_do_engine_reset( dev );
1263
1264 return 0;
1265}
1266
1267int radeon_do_cleanup_cp( drm_device_t *dev )
1268{
1269 DRM_DEBUG( "\n" );
1270
1271 if ( dev->dev_private ) {
1272 drm_radeon_private_t *dev_priv = dev->dev_private;
1273
1274 if ( !dev_priv->is_pci ) {
1275 if ( dev_priv->cp_ring != NULL )
1276 DRM_IOREMAPFREE( dev_priv->cp_ring );
1277 if ( dev_priv->ring_rptr != NULL )
1278 DRM_IOREMAPFREE( dev_priv->ring_rptr );
1279 if ( dev_priv->buffers != NULL )
1280 DRM_IOREMAPFREE( dev_priv->buffers );
1281 } else {
1282#if __REALLY_HAVE_SG
1283 if (!DRM(ati_pcigart_cleanup)( dev,
1284 dev_priv->phys_pci_gart,
1285 dev_priv->bus_pci_gart ))
1286 DRM_ERROR( "failed to cleanup PCI GART!\n" );
1287#endif /* __REALLY_HAVE_SG */
1288 }
1289
1290 DRM(free)( dev->dev_private, sizeof(drm_radeon_private_t),
1291 DRM_MEM_DRIVER );
1292 dev->dev_private = NULL;
1293 }
1294
1295 return 0;
1296}
1297
1298int radeon_cp_init( DRM_IOCTL_ARGS )
1299{
1300 DRM_DEVICE;
1301 drm_radeon_init_t init;
1302
1303 DRM_COPY_FROM_USER_IOCTL( init, (drm_radeon_init_t *)data, sizeof(init) );
1304
1305 switch ( init.func ) {
1306 case RADEON_INIT_CP:
1307 case RADEON_INIT_R200_CP:
1308 return radeon_do_init_cp( dev, &init );
1309 case RADEON_CLEANUP_CP:
1310 return radeon_do_cleanup_cp( dev );

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1443 drm_radeon_private_t *dev_priv = dev->dev_private;
1444 DRM_DEBUG( "\n" );
1445
1446 LOCK_TEST_WITH_RETURN( dev, filp );
1447
1448 return radeon_do_cp_idle( dev_priv );
1449}
1450
1451int radeon_engine_reset( DRM_IOCTL_ARGS )
1452{
1453 DRM_DEVICE;
1454 DRM_DEBUG( "\n" );
1455
1456 LOCK_TEST_WITH_RETURN( dev, filp );
1457
1458 return radeon_do_engine_reset( dev );

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