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r600_cp.c (190595) r600_cp.c (190674)
1/*-
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

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22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include <sys/cdefs.h>
1/*-
2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,

--- 13 unchanged lines hidden (view full) ---

22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
27 */
28
29#include <sys/cdefs.h>
30__FBSDID("$FreeBSD: head/sys/dev/drm/r600_cp.c 190595 2009-03-31 17:52:05Z rnoland $");
30__FBSDID("$FreeBSD: head/sys/dev/drm/r600_cp.c 190674 2009-04-03 19:21:39Z rnoland $");
31
32#include "dev/drm/drmP.h"
33#include "dev/drm/drm.h"
34#include "dev/drm/radeon_drm.h"
35#include "dev/drm/radeon_drv.h"
36
37#include "dev/drm/r600_microcode.h"
38

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281
282/* load r600 microcode */
283static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
284{
285 const u32 (*cp)[3];
286 const u32 *pfp;
287 int i;
288
31
32#include "dev/drm/drmP.h"
33#include "dev/drm/drm.h"
34#include "dev/drm/radeon_drm.h"
35#include "dev/drm/radeon_drv.h"
36
37#include "dev/drm/r600_microcode.h"
38

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281
282/* load r600 microcode */
283static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
284{
285 const u32 (*cp)[3];
286 const u32 *pfp;
287 int i;
288
289 r600_do_cp_stop(dev_priv);
290
291 RADEON_WRITE(R600_CP_RB_CNTL,
292 R600_RB_NO_UPDATE |
293 R600_RB_BLKSZ(15) |
294 R600_RB_BUFSZ(3));
295
296 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
297 RADEON_READ(R600_GRBM_SOFT_RESET);
298 DRM_UDELAY(15000);
299 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
300
301 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
302
303 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
304 case CHIP_R600:
305 DRM_INFO("Loading R600 Microcode\n");
306 cp = R600_cp_microcode;
307 pfp = R600_pfp_microcode;
308 break;
309 case CHIP_RV610:
310 DRM_INFO("Loading RV610 Microcode\n");

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332 pfp = RV670_pfp_microcode;
333 break;
334 case CHIP_RS780:
335 DRM_INFO("Loading RS780 Microcode\n");
336 cp = RS780_cp_microcode;
337 pfp = RS780_pfp_microcode;
338 break;
339 default:
289 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
290 case CHIP_R600:
291 DRM_INFO("Loading R600 Microcode\n");
292 cp = R600_cp_microcode;
293 pfp = R600_pfp_microcode;
294 break;
295 case CHIP_RV610:
296 DRM_INFO("Loading RV610 Microcode\n");

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318 pfp = RV670_pfp_microcode;
319 break;
320 case CHIP_RS780:
321 DRM_INFO("Loading RS780 Microcode\n");
322 cp = RS780_cp_microcode;
323 pfp = RS780_pfp_microcode;
324 break;
325 default:
340 goto no_microcode;
326 return;
341 }
342
327 }
328
343 for (i = 0; i != PM4_UCODE_SIZE; i++) {
329 r600_do_cp_stop(dev_priv);
330
331 RADEON_WRITE(R600_CP_RB_CNTL,
332 R600_RB_NO_UPDATE |
333 R600_RB_BLKSZ(15) |
334 R600_RB_BUFSZ(3));
335
336 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
337 RADEON_READ(R600_GRBM_SOFT_RESET);
338 DRM_UDELAY(15000);
339 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
340
341 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
342
343 for (i = 0; i < PM4_UCODE_SIZE; i++) {
344 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
345 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
346 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
347 }
348
349 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
344 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
345 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
346 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
347 }
348
349 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
350 for (i = 0; i != PFP_UCODE_SIZE; i++)
350 for (i = 0; i < PFP_UCODE_SIZE; i++)
351 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
351 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
352no_microcode:;
353
354 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
355 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
356 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
357}
358
359static void r700_vm_init(struct drm_device *dev)
360{

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410
411/* load r600 microcode */
412static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
413{
414 const u32 *pfp;
415 const u32 *cp;
416 int i;
417
352
353 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
354 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
355 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
356}
357
358static void r700_vm_init(struct drm_device *dev)
359{

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409
410/* load r600 microcode */
411static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
412{
413 const u32 *pfp;
414 const u32 *cp;
415 int i;
416
418 r600_do_cp_stop(dev_priv);
419
420 RADEON_WRITE(R600_CP_RB_CNTL,
421 R600_RB_NO_UPDATE |
422 (15 << 8) |
423 (3 << 0));
424
425 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
426 RADEON_READ(R600_GRBM_SOFT_RESET);
427 DRM_UDELAY(15000);
428 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
429
430 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
431 case CHIP_RV770:
417 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
418 case CHIP_RV770:
432 DRM_INFO("Loading RV770 Microcode\n");
419 DRM_INFO("Loading RV770/RV790 Microcode\n");
433 pfp = RV770_pfp_microcode;
434 cp = RV770_cp_microcode;
435 break;
436 case CHIP_RV730:
437 DRM_INFO("Loading RV730 Microcode\n");
438 pfp = RV730_pfp_microcode;
439 cp = RV730_cp_microcode;
440 break;
441 case CHIP_RV710:
442 DRM_INFO("Loading RV710 Microcode\n");
443 pfp = RV710_pfp_microcode;
444 cp = RV710_cp_microcode;
445 break;
446 default:
420 pfp = RV770_pfp_microcode;
421 cp = RV770_cp_microcode;
422 break;
423 case CHIP_RV730:
424 DRM_INFO("Loading RV730 Microcode\n");
425 pfp = RV730_pfp_microcode;
426 cp = RV730_cp_microcode;
427 break;
428 case CHIP_RV710:
429 DRM_INFO("Loading RV710 Microcode\n");
430 pfp = RV710_pfp_microcode;
431 cp = RV710_cp_microcode;
432 break;
433 default:
447 goto no_microcode;
434 return;
448 }
449
435 }
436
437 r600_do_cp_stop(dev_priv);
438
439 RADEON_WRITE(R600_CP_RB_CNTL,
440 R600_RB_NO_UPDATE |
441 (15 << 8) |
442 (3 << 0));
443
444 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
445 RADEON_READ(R600_GRBM_SOFT_RESET);
446 DRM_UDELAY(15000);
447 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
448
450 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
449 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
451 for (i = 0; i != R700_PFP_UCODE_SIZE; i++)
450 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
452 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
453 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
454
455 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
451 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
452 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
453
454 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
456 for (i = 0; i != R700_PM4_UCODE_SIZE; i++)
455 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
457 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
458 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
456 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
457 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
459no_microcode:;
460
461 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
462 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
463 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
464}
465
466static void r600_test_writeback(drm_radeon_private_t *dev_priv)
467{

--- 1728 unchanged lines hidden --- 		458
459 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
460 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
461 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
462}
463
464static void r600_test_writeback(drm_radeon_private_t *dev_priv)
465{

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