1/* r128_drv.h -- Private header for r128 driver -*- linux-c -*-
2 * Created: Mon Dec 13 09:51:11 1999 by faith@precisioninsight.com
3 *
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6 * All rights reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Rickard E. (Rik) Faith <faith@valinux.com>
29 * Kevin E. Martin <martin@valinux.com>
30 * Gareth Hughes <gareth@valinux.com>
31 * Michel D�nzer <daenzerm@student.ethz.ch>
32 *
|
33 * $FreeBSD: head/sys/dev/drm/r128_drv.h 113995 2003-04-25 01:18:47Z anholt $
|
| 33 * $FreeBSD: head/sys/dev/drm/r128_drv.h 119098 2003-08-19 02:57:31Z anholt $ |
34 */
35
36#ifndef __R128_DRV_H__
37#define __R128_DRV_H__
38
39#define GET_RING_HEAD(ring) DRM_READ32( (ring)->ring_rptr, 0 ) /* (ring)->head */
40#define SET_RING_HEAD(ring,val) DRM_WRITE32( (ring)->ring_rptr, 0, (val) ) /* (ring)->head */
41
42typedef struct drm_r128_freelist {
43 unsigned int age;
44 drm_buf_t *buf;
45 struct drm_r128_freelist *next;
46 struct drm_r128_freelist *prev;
47} drm_r128_freelist_t;
48
49typedef struct drm_r128_ring_buffer {
50 u32 *start;
51 u32 *end;
52 int size;
53 int size_l2qw;
54
55 volatile u32 *head;
56 u32 tail;
57 u32 tail_mask;
58 int space;
59
60 int high_mark;
61 drm_local_map_t *ring_rptr;
62} drm_r128_ring_buffer_t;
63
64typedef struct drm_r128_private {
65 drm_r128_ring_buffer_t ring;
66 drm_r128_sarea_t *sarea_priv;
67
68 int cce_mode;
69 int cce_fifo_size;
70 int cce_running;
71
72 drm_r128_freelist_t *head;
73 drm_r128_freelist_t *tail;
74
75 int usec_timeout;
76 int is_pci;
77 unsigned long phys_pci_gart;
78 dma_addr_t bus_pci_gart;
79 unsigned long cce_buffers_offset;
80
81 atomic_t idle_count;
82
83 int page_flipping;
84 int current_page;
85 u32 crtc_offset;
86 u32 crtc_offset_cntl;
87
88 u32 color_fmt;
89 unsigned int front_offset;
90 unsigned int front_pitch;
91 unsigned int back_offset;
92 unsigned int back_pitch;
93
94 u32 depth_fmt;
95 unsigned int depth_offset;
96 unsigned int depth_pitch;
97 unsigned int span_offset;
98
99 u32 front_pitch_offset_c;
100 u32 back_pitch_offset_c;
101 u32 depth_pitch_offset_c;
102 u32 span_pitch_offset_c;
103
104 drm_local_map_t *sarea;
105 drm_local_map_t *fb;
106 drm_local_map_t *mmio;
107 drm_local_map_t *cce_ring;
108 drm_local_map_t *ring_rptr;
109 drm_local_map_t *buffers;
110 drm_local_map_t *agp_textures;
111} drm_r128_private_t;
112
113typedef struct drm_r128_buf_priv {
114 u32 age;
115 int prim;
116 int discard;
117 int dispatched;
118 drm_r128_freelist_t *list_entry;
119} drm_r128_buf_priv_t;
120
121 /* r128_cce.c */
122extern int r128_cce_init( DRM_IOCTL_ARGS );
123extern int r128_cce_start( DRM_IOCTL_ARGS );
124extern int r128_cce_stop( DRM_IOCTL_ARGS );
125extern int r128_cce_reset( DRM_IOCTL_ARGS );
126extern int r128_cce_idle( DRM_IOCTL_ARGS );
127extern int r128_engine_reset( DRM_IOCTL_ARGS );
128extern int r128_fullscreen( DRM_IOCTL_ARGS );
129extern int r128_cce_buffers( DRM_IOCTL_ARGS );
130extern int r128_getparam( DRM_IOCTL_ARGS );
131
132extern void r128_freelist_reset( drm_device_t *dev );
133extern drm_buf_t *r128_freelist_get( drm_device_t *dev );
134
135extern int r128_wait_ring( drm_r128_private_t *dev_priv, int n );
136
137static __inline__ void
138r128_update_ring_snapshot( drm_r128_ring_buffer_t *ring )
139{
140 ring->space = (GET_RING_HEAD( ring ) - ring->tail) * sizeof(u32);
141 if ( ring->space <= 0 )
142 ring->space += ring->size;
143}
144
145extern int r128_do_cce_idle( drm_r128_private_t *dev_priv );
146extern int r128_do_cleanup_cce( drm_device_t *dev );
147extern int r128_do_cleanup_pageflip( drm_device_t *dev );
148
149 /* r128_state.c */
150extern int r128_cce_clear( DRM_IOCTL_ARGS );
151extern int r128_cce_swap( DRM_IOCTL_ARGS );
|
| 152extern int r128_cce_flip( DRM_IOCTL_ARGS ); |
153extern int r128_cce_vertex( DRM_IOCTL_ARGS );
154extern int r128_cce_indices( DRM_IOCTL_ARGS );
155extern int r128_cce_blit( DRM_IOCTL_ARGS );
156extern int r128_cce_depth( DRM_IOCTL_ARGS );
157extern int r128_cce_stipple( DRM_IOCTL_ARGS );
158extern int r128_cce_indirect( DRM_IOCTL_ARGS );
159
160
161/* Register definitions, register access macros and drmAddMap constants
162 * for Rage 128 kernel driver.
163 */
164
165#define R128_AUX_SC_CNTL 0x1660
166# define R128_AUX1_SC_EN (1 << 0)
167# define R128_AUX1_SC_MODE_OR (0 << 1)
168# define R128_AUX1_SC_MODE_NAND (1 << 1)
169# define R128_AUX2_SC_EN (1 << 2)
170# define R128_AUX2_SC_MODE_OR (0 << 3)
171# define R128_AUX2_SC_MODE_NAND (1 << 3)
172# define R128_AUX3_SC_EN (1 << 4)
173# define R128_AUX3_SC_MODE_OR (0 << 5)
174# define R128_AUX3_SC_MODE_NAND (1 << 5)
175#define R128_AUX1_SC_LEFT 0x1664
176#define R128_AUX1_SC_RIGHT 0x1668
177#define R128_AUX1_SC_TOP 0x166c
178#define R128_AUX1_SC_BOTTOM 0x1670
179#define R128_AUX2_SC_LEFT 0x1674
180#define R128_AUX2_SC_RIGHT 0x1678
181#define R128_AUX2_SC_TOP 0x167c
182#define R128_AUX2_SC_BOTTOM 0x1680
183#define R128_AUX3_SC_LEFT 0x1684
184#define R128_AUX3_SC_RIGHT 0x1688
185#define R128_AUX3_SC_TOP 0x168c
186#define R128_AUX3_SC_BOTTOM 0x1690
187
188#define R128_BRUSH_DATA0 0x1480
189#define R128_BUS_CNTL 0x0030
190# define R128_BUS_MASTER_DIS (1 << 6)
191
192#define R128_CLOCK_CNTL_INDEX 0x0008
193#define R128_CLOCK_CNTL_DATA 0x000c
194# define R128_PLL_WR_EN (1 << 7)
195#define R128_CONSTANT_COLOR_C 0x1d34
196#define R128_CRTC_OFFSET 0x0224
197#define R128_CRTC_OFFSET_CNTL 0x0228
198# define R128_CRTC_OFFSET_FLIP_CNTL (1 << 16)
199
200#define R128_DP_GUI_MASTER_CNTL 0x146c
201# define R128_GMC_SRC_PITCH_OFFSET_CNTL (1 << 0)
202# define R128_GMC_DST_PITCH_OFFSET_CNTL (1 << 1)
203# define R128_GMC_BRUSH_SOLID_COLOR (13 << 4)
204# define R128_GMC_BRUSH_NONE (15 << 4)
205# define R128_GMC_DST_16BPP (4 << 8)
206# define R128_GMC_DST_24BPP (5 << 8)
207# define R128_GMC_DST_32BPP (6 << 8)
208# define R128_GMC_DST_DATATYPE_SHIFT 8
209# define R128_GMC_SRC_DATATYPE_COLOR (3 << 12)
210# define R128_DP_SRC_SOURCE_MEMORY (2 << 24)
211# define R128_DP_SRC_SOURCE_HOST_DATA (3 << 24)
212# define R128_GMC_CLR_CMP_CNTL_DIS (1 << 28)
213# define R128_GMC_AUX_CLIP_DIS (1 << 29)
214# define R128_GMC_WR_MSK_DIS (1 << 30)
215# define R128_ROP3_S 0x00cc0000
216# define R128_ROP3_P 0x00f00000
217#define R128_DP_WRITE_MASK 0x16cc
218#define R128_DST_PITCH_OFFSET_C 0x1c80
219# define R128_DST_TILE (1 << 31)
220
221#define R128_GEN_INT_CNTL 0x0040
222# define R128_CRTC_VBLANK_INT_EN (1 << 0)
223#define R128_GEN_INT_STATUS 0x0044
224# define R128_CRTC_VBLANK_INT (1 << 0)
225# define R128_CRTC_VBLANK_INT_AK (1 << 0)
226#define R128_GEN_RESET_CNTL 0x00f0
227# define R128_SOFT_RESET_GUI (1 << 0)
228
229#define R128_GUI_SCRATCH_REG0 0x15e0
230#define R128_GUI_SCRATCH_REG1 0x15e4
231#define R128_GUI_SCRATCH_REG2 0x15e8
232#define R128_GUI_SCRATCH_REG3 0x15ec
233#define R128_GUI_SCRATCH_REG4 0x15f0
234#define R128_GUI_SCRATCH_REG5 0x15f4
235
236#define R128_GUI_STAT 0x1740
237# define R128_GUI_FIFOCNT_MASK 0x0fff
238# define R128_GUI_ACTIVE (1 << 31)
239
240#define R128_MCLK_CNTL 0x000f
241# define R128_FORCE_GCP (1 << 16)
242# define R128_FORCE_PIPE3D_CP (1 << 17)
243# define R128_FORCE_RCP (1 << 18)
244
245#define R128_PC_GUI_CTLSTAT 0x1748
246#define R128_PC_NGUI_CTLSTAT 0x0184
247# define R128_PC_FLUSH_GUI (3 << 0)
248# define R128_PC_RI_GUI (1 << 2)
249# define R128_PC_FLUSH_ALL 0x00ff
250# define R128_PC_BUSY (1 << 31)
251
252#define R128_PCI_GART_PAGE 0x017c
253#define R128_PRIM_TEX_CNTL_C 0x1cb0
254
255#define R128_SCALE_3D_CNTL 0x1a00
256#define R128_SEC_TEX_CNTL_C 0x1d00
257#define R128_SEC_TEXTURE_BORDER_COLOR_C 0x1d3c
258#define R128_SETUP_CNTL 0x1bc4
259#define R128_STEN_REF_MASK_C 0x1d40
260
261#define R128_TEX_CNTL_C 0x1c9c
262# define R128_TEX_CACHE_FLUSH (1 << 23)
263
264#define R128_WAIT_UNTIL 0x1720
265# define R128_EVENT_CRTC_OFFSET (1 << 0)
266#define R128_WINDOW_XY_OFFSET 0x1bcc
267
268
269/* CCE registers
270 */
271#define R128_PM4_BUFFER_OFFSET 0x0700
272#define R128_PM4_BUFFER_CNTL 0x0704
273# define R128_PM4_MASK (15 << 28)
274# define R128_PM4_NONPM4 (0 << 28)
275# define R128_PM4_192PIO (1 << 28)
276# define R128_PM4_192BM (2 << 28)
277# define R128_PM4_128PIO_64INDBM (3 << 28)
278# define R128_PM4_128BM_64INDBM (4 << 28)
279# define R128_PM4_64PIO_128INDBM (5 << 28)
280# define R128_PM4_64BM_128INDBM (6 << 28)
281# define R128_PM4_64PIO_64VCBM_64INDBM (7 << 28)
282# define R128_PM4_64BM_64VCBM_64INDBM (8 << 28)
283# define R128_PM4_64PIO_64VCPIO_64INDPIO (15 << 28)
284
285#define R128_PM4_BUFFER_WM_CNTL 0x0708
286# define R128_WMA_SHIFT 0
287# define R128_WMB_SHIFT 8
288# define R128_WMC_SHIFT 16
289# define R128_WB_WM_SHIFT 24
290
291#define R128_PM4_BUFFER_DL_RPTR_ADDR 0x070c
292#define R128_PM4_BUFFER_DL_RPTR 0x0710
293#define R128_PM4_BUFFER_DL_WPTR 0x0714
294# define R128_PM4_BUFFER_DL_DONE (1 << 31)
295
296#define R128_PM4_VC_FPU_SETUP 0x071c
297
298#define R128_PM4_IW_INDOFF 0x0738
299#define R128_PM4_IW_INDSIZE 0x073c
300
301#define R128_PM4_STAT 0x07b8
302# define R128_PM4_FIFOCNT_MASK 0x0fff
303# define R128_PM4_BUSY (1 << 16)
304# define R128_PM4_GUI_ACTIVE (1 << 31)
305
306#define R128_PM4_MICROCODE_ADDR 0x07d4
307#define R128_PM4_MICROCODE_RADDR 0x07d8
308#define R128_PM4_MICROCODE_DATAH 0x07dc
309#define R128_PM4_MICROCODE_DATAL 0x07e0
310
311#define R128_PM4_BUFFER_ADDR 0x07f0
312#define R128_PM4_MICRO_CNTL 0x07fc
313# define R128_PM4_MICRO_FREERUN (1 << 30)
314
315#define R128_PM4_FIFO_DATA_EVEN 0x1000
316#define R128_PM4_FIFO_DATA_ODD 0x1004
317
318
319/* CCE command packets
320 */
321#define R128_CCE_PACKET0 0x00000000
322#define R128_CCE_PACKET1 0x40000000
323#define R128_CCE_PACKET2 0x80000000
324#define R128_CCE_PACKET3 0xC0000000
325# define R128_CNTL_HOSTDATA_BLT 0x00009400
326# define R128_CNTL_PAINT_MULTI 0x00009A00
327# define R128_CNTL_BITBLT_MULTI 0x00009B00
328# define R128_3D_RNDR_GEN_INDX_PRIM 0x00002300
329
330#define R128_CCE_PACKET_MASK 0xC0000000
331#define R128_CCE_PACKET_COUNT_MASK 0x3fff0000
332#define R128_CCE_PACKET0_REG_MASK 0x000007ff
333#define R128_CCE_PACKET1_REG0_MASK 0x000007ff
334#define R128_CCE_PACKET1_REG1_MASK 0x003ff800
335
336#define R128_CCE_VC_CNTL_PRIM_TYPE_NONE 0x00000000
337#define R128_CCE_VC_CNTL_PRIM_TYPE_POINT 0x00000001
338#define R128_CCE_VC_CNTL_PRIM_TYPE_LINE 0x00000002
339#define R128_CCE_VC_CNTL_PRIM_TYPE_POLY_LINE 0x00000003
340#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004
341#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005
342#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006
343#define R128_CCE_VC_CNTL_PRIM_TYPE_TRI_TYPE2 0x00000007
344#define R128_CCE_VC_CNTL_PRIM_WALK_IND 0x00000010
345#define R128_CCE_VC_CNTL_PRIM_WALK_LIST 0x00000020
346#define R128_CCE_VC_CNTL_PRIM_WALK_RING 0x00000030
347#define R128_CCE_VC_CNTL_NUM_SHIFT 16
348
|
349#define R128_DATATYPE_VQ 0
350#define R128_DATATYPE_CI4 1 |
351#define R128_DATATYPE_CI8 2
352#define R128_DATATYPE_ARGB1555 3
353#define R128_DATATYPE_RGB565 4
354#define R128_DATATYPE_RGB888 5
355#define R128_DATATYPE_ARGB8888 6
356#define R128_DATATYPE_RGB332 7
|
| 357#define R128_DATATYPE_Y8 8 |
358#define R128_DATATYPE_RGB8 9
|
359#define R128_DATATYPE_CI16 10
360#define R128_DATATYPE_YVYU422 11
361#define R128_DATATYPE_VYUY422 12
362#define R128_DATATYPE_AYUV444 14 |
363#define R128_DATATYPE_ARGB4444 15
364
365/* Constants */
366#define R128_AGP_OFFSET 0x02000000
367
368#define R128_WATERMARK_L 16
369#define R128_WATERMARK_M 8
370#define R128_WATERMARK_N 8
371#define R128_WATERMARK_K 128
372
373#define R128_MAX_USEC_TIMEOUT 100000 /* 100 ms */
374
375#define R128_LAST_FRAME_REG R128_GUI_SCRATCH_REG0
376#define R128_LAST_DISPATCH_REG R128_GUI_SCRATCH_REG1
377#define R128_MAX_VB_AGE 0x7fffffff
378#define R128_MAX_VB_VERTS (0xffff)
379
380#define R128_RING_HIGH_MARK 128
381
382#define R128_PERFORMANCE_BOXES 0
383
384#define R128_READ(reg) DRM_READ32( dev_priv->mmio, (reg) )
385#define R128_WRITE(reg,val) DRM_WRITE32( dev_priv->mmio, (reg), (val) )
386#define R128_READ8(reg) DRM_READ8( dev_priv->mmio, (reg) )
387#define R128_WRITE8(reg,val) DRM_WRITE8( dev_priv->mmio, (reg), (val) )
388
389#define R128_WRITE_PLL(addr,val) \
390do { \
391 R128_WRITE8(R128_CLOCK_CNTL_INDEX, \
392 ((addr) & 0x1f) | R128_PLL_WR_EN); \
393 R128_WRITE(R128_CLOCK_CNTL_DATA, (val)); \
394} while (0)
395
396extern int R128_READ_PLL(drm_device_t *dev, int addr);
397
398
399#define CCE_PACKET0( reg, n ) (R128_CCE_PACKET0 | \
400 ((n) << 16) | ((reg) >> 2))
401#define CCE_PACKET1( reg0, reg1 ) (R128_CCE_PACKET1 | \
402 (((reg1) >> 2) << 11) | ((reg0) >> 2))
403#define CCE_PACKET2() (R128_CCE_PACKET2)
404#define CCE_PACKET3( pkt, n ) (R128_CCE_PACKET3 | \
405 (pkt) | ((n) << 16))
406
407
408/* ================================================================
409 * Misc helper macros
410 */
411
412#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
413do { \
414 drm_r128_ring_buffer_t *ring = &dev_priv->ring; int i; \
415 if ( ring->space < ring->high_mark ) { \
416 for ( i = 0 ; i < dev_priv->usec_timeout ; i++ ) { \
417 r128_update_ring_snapshot( ring ); \
418 if ( ring->space >= ring->high_mark ) \
419 goto __ring_space_done; \
420 DRM_UDELAY(1); \
421 } \
422 DRM_ERROR( "ring space check failed!\n" ); \
423 return DRM_ERR(EBUSY); \
424 } \
425 __ring_space_done: \
426 ; \
427} while (0)
428
429#define VB_AGE_TEST_WITH_RETURN( dev_priv ) \
430do { \
431 drm_r128_sarea_t *sarea_priv = dev_priv->sarea_priv; \
432 if ( sarea_priv->last_dispatch >= R128_MAX_VB_AGE ) { \
433 int __ret = r128_do_cce_idle( dev_priv ); \
434 if ( __ret ) return __ret; \
435 sarea_priv->last_dispatch = 0; \
436 r128_freelist_reset( dev ); \
437 } \
438} while (0)
439
440#define R128_WAIT_UNTIL_PAGE_FLIPPED() do { \
441 OUT_RING( CCE_PACKET0( R128_WAIT_UNTIL, 0 ) ); \
442 OUT_RING( R128_EVENT_CRTC_OFFSET ); \
443} while (0)
444
445
446/* ================================================================
447 * Ring control
448 */
449
450#if defined(__powerpc__)
451#define r128_flush_write_combine() (void) GET_RING_HEAD( &dev_priv->ring )
452#else
|
445#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER(dev_priv->ring_rptr)
|
| 453#define r128_flush_write_combine() DRM_WRITEMEMORYBARRIER() |
454#endif
455
456
457#define R128_VERBOSE 0
458
459#define RING_LOCALS \
460 int write; unsigned int tail_mask; volatile u32 *ring;
461
462#define BEGIN_RING( n ) do { \
463 if ( R128_VERBOSE ) { \
464 DRM_INFO( "BEGIN_RING( %d ) in %s\n", \
465 (n), __FUNCTION__ ); \
466 } \
467 if ( dev_priv->ring.space <= (n) * sizeof(u32) ) { \
468 r128_wait_ring( dev_priv, (n) * sizeof(u32) ); \
469 } \
470 dev_priv->ring.space -= (n) * sizeof(u32); \
471 ring = dev_priv->ring.start; \
472 write = dev_priv->ring.tail; \
473 tail_mask = dev_priv->ring.tail_mask; \
474} while (0)
475
476/* You can set this to zero if you want. If the card locks up, you'll
477 * need to keep this set. It works around a bug in early revs of the
478 * Rage 128 chipset, where the CCE would read 32 dwords past the end of
479 * the ring buffer before wrapping around.
480 */
481#define R128_BROKEN_CCE 1
482
483#define ADVANCE_RING() do { \
484 if ( R128_VERBOSE ) { \
485 DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
486 write, dev_priv->ring.tail ); \
487 } \
488 if ( R128_BROKEN_CCE && write < 32 ) { \
489 memcpy( dev_priv->ring.end, \
490 dev_priv->ring.start, \
491 write * sizeof(u32) ); \
492 } \
493 r128_flush_write_combine(); \
494 dev_priv->ring.tail = write; \
495 R128_WRITE( R128_PM4_BUFFER_DL_WPTR, write ); \
496} while (0)
497
498#define OUT_RING( x ) do { \
499 if ( R128_VERBOSE ) { \
500 DRM_INFO( " OUT_RING( 0x%08x ) at 0x%x\n", \
501 (unsigned int)(x), write ); \
502 } \
503 ring[write++] = cpu_to_le32( x ); \
504 write &= tail_mask; \
505} while (0)
506
507#endif /* __R128_DRV_H__ */
|