| dcphy.c (95722) | dcphy.c (96026) |
|---|---|
| 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * | 1/* 2 * Copyright (c) 1997, 1998, 1999 3 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright --- 15 unchanged lines hidden (view full) --- 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * |
| 32 * $FreeBSD: head/sys/dev/dc/dcphy.c 95722 2002-04-29 13:07:38Z phk $ | 32 * $FreeBSD: head/sys/dev/dc/dcphy.c 96026 2002-05-04 11:00:30Z phk $ |
| 33 */ 34 35/* 36 * Pseudo-driver for internal NWAY support on DEC 21143 and workalike 37 * controllers. Technically we're abusing the miibus code to handle 38 * media selection and NWAY support here since there is no MII 39 * interface. However the logical operations are roughly the same, 40 * and the alternative is to create a fake MII interface in the driver, --- 27 unchanged lines hidden (view full) --- 68#include <pci/pcivar.h> 69 70#include <pci/if_dcreg.h> 71 72#include "miibus_if.h" 73 74#if !defined(lint) 75static const char rcsid[] = | 33 */ 34 35/* 36 * Pseudo-driver for internal NWAY support on DEC 21143 and workalike 37 * controllers. Technically we're abusing the miibus code to handle 38 * media selection and NWAY support here since there is no MII 39 * interface. However the logical operations are roughly the same, 40 * and the alternative is to create a fake MII interface in the driver, --- 27 unchanged lines hidden (view full) --- 68#include <pci/pcivar.h> 69 70#include <pci/if_dcreg.h> 71 72#include "miibus_if.h" 73 74#if !defined(lint) 75static const char rcsid[] = |
| 76 "$FreeBSD: head/sys/dev/dc/dcphy.c 95722 2002-04-29 13:07:38Z phk $"; | 76 "$FreeBSD: head/sys/dev/dc/dcphy.c 96026 2002-05-04 11:00:30Z phk $"; |
| 77#endif 78 79#define DC_SETBIT(sc, reg, x) \ 80 CSR_WRITE_4(sc, reg, \ 81 CSR_READ_4(sc, reg) | x) 82 83#define DC_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, \ --- 28 unchanged lines hidden (view full) --- 113 sizeof(struct mii_softc) 114}; 115 116DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0); 117 118static int dcphy_service(struct mii_softc *, struct mii_data *, int); 119static void dcphy_status(struct mii_softc *); 120static void dcphy_reset(struct mii_softc *); | 77#endif 78 79#define DC_SETBIT(sc, reg, x) \ 80 CSR_WRITE_4(sc, reg, \ 81 CSR_READ_4(sc, reg) | x) 82 83#define DC_CLRBIT(sc, reg, x) \ 84 CSR_WRITE_4(sc, reg, \ --- 28 unchanged lines hidden (view full) --- 113 sizeof(struct mii_softc) 114}; 115 116DRIVER_MODULE(dcphy, miibus, dcphy_driver, dcphy_devclass, 0, 0); 117 118static int dcphy_service(struct mii_softc *, struct mii_data *, int); 119static void dcphy_status(struct mii_softc *); 120static void dcphy_reset(struct mii_softc *); |
| 121static int dcphy_auto(struct mii_softc *, int); | 121static int dcphy_auto(struct mii_softc *); |
| 122 123static int dcphy_probe(dev) 124 device_t dev; 125{ 126 struct mii_attach_args *ma; 127 128 ma = device_get_ivars(dev); 129 --- 115 unchanged lines hidden (view full) --- 245 mii->mii_media_active = IFM_NONE; 246 mode = CSR_READ_4(dc_sc, DC_NETCFG); 247 mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL| 248 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL); 249 250 switch (IFM_SUBTYPE(ife->ifm_media)) { 251 case IFM_AUTO: 252 /*dcphy_reset(sc);*/ | 122 123static int dcphy_probe(dev) 124 device_t dev; 125{ 126 struct mii_attach_args *ma; 127 128 ma = device_get_ivars(dev); 129 --- 115 unchanged lines hidden (view full) --- 245 mii->mii_media_active = IFM_NONE; 246 mode = CSR_READ_4(dc_sc, DC_NETCFG); 247 mode &= ~(DC_NETCFG_FULLDUPLEX|DC_NETCFG_PORTSEL| 248 DC_NETCFG_PCS|DC_NETCFG_SCRAMBLER|DC_NETCFG_SPEEDSEL); 249 250 switch (IFM_SUBTYPE(ife->ifm_media)) { 251 case IFM_AUTO: 252 /*dcphy_reset(sc);*/ |
| 253 sc->mii_flags &= ~MIIF_DOINGAUTO; 254 (void) dcphy_auto(sc, 0); | 253 (void) dcphy_auto(sc); |
| 255 break; 256 case IFM_100_T4: 257 /* 258 * XXX Not supported as a manual setting right now. 259 */ 260 return (EINVAL); 261 case IFM_100_TX: 262 dcphy_reset(sc); --- 61 unchanged lines hidden (view full) --- 324 * that only happens in dcphy_status(). Without this, 325 * successful autonegotation is never recognised on 326 * these chips. 327 */ 328 if (++sc->mii_ticks != 50) 329 break; 330 331 sc->mii_ticks = 0; | 254 break; 255 case IFM_100_T4: 256 /* 257 * XXX Not supported as a manual setting right now. 258 */ 259 return (EINVAL); 260 case IFM_100_TX: 261 dcphy_reset(sc); --- 61 unchanged lines hidden (view full) --- 323 * that only happens in dcphy_status(). Without this, 324 * successful autonegotation is never recognised on 325 * these chips. 326 */ 327 if (++sc->mii_ticks != 50) 328 break; 329 330 sc->mii_ticks = 0; |
| 332 /*if (DC_IS_INTEL(dc_sc))*/ 333 sc->mii_flags &= ~MIIF_DOINGAUTO; 334 dcphy_auto(sc, 0); | 331 dcphy_auto(sc); |
| 335 336 break; 337 } 338 339 /* Update the media status. */ 340 dcphy_status(sc); 341 342 /* Callback if something changed. */ --- 81 unchanged lines hidden (view full) --- 424 mii->mii_media_active |= IFM_100_TX; 425 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) 426 mii->mii_media_active |= IFM_FDX; 427 428 return; 429} 430 431static int | 332 333 break; 334 } 335 336 /* Update the media status. */ 337 dcphy_status(sc); 338 339 /* Callback if something changed. */ --- 81 unchanged lines hidden (view full) --- 421 mii->mii_media_active |= IFM_100_TX; 422 if (CSR_READ_4(dc_sc, DC_NETCFG) & DC_NETCFG_FULLDUPLEX) 423 mii->mii_media_active |= IFM_FDX; 424 425 return; 426} 427 428static int |
| 432dcphy_auto(mii, waitfor) | 429dcphy_auto(mii) |
| 433 struct mii_softc *mii; | 430 struct mii_softc *mii; |
| 434 int waitfor; | |
| 435{ | 431{ |
| 436 int i; | |
| 437 struct dc_softc *sc; 438 439 sc = mii->mii_pdata->mii_ifp->if_softc; 440 | 432 struct dc_softc *sc; 433 434 sc = mii->mii_pdata->mii_ifp->if_softc; 435 |
| 441 if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) { 442 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 443 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 444 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 445 if (mii->mii_capabilities & BMSR_100TXHDX) 446 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); 447 else 448 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); 449 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 450 DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 451 DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE); 452 } | 436 DC_CLRBIT(sc, DC_NETCFG, DC_NETCFG_PORTSEL); 437 DC_SETBIT(sc, DC_NETCFG, DC_NETCFG_FULLDUPLEX); 438 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 439 if (mii->mii_capabilities & BMSR_100TXHDX) 440 CSR_WRITE_4(sc, DC_10BTCTRL, 0x3FFFF); 441 else 442 CSR_WRITE_4(sc, DC_10BTCTRL, 0xFFFF); 443 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 444 DC_SETBIT(sc, DC_10BTCTRL, DC_TCTL_AUTONEGENBL); 445 DC_SETBIT(sc, DC_10BTSTAT, DC_ASTAT_TXDISABLE); |
| 453 | 446 |
| 454 if (waitfor) { 455 /* Wait 500ms for it to complete. */ 456 for (i = 0; i < 500; i++) { 457 if ((CSR_READ_4(sc, DC_10BTSTAT) & DC_TSTAT_ANEGSTAT) 458 == DC_ASTAT_AUTONEGCMP) 459 return(0); 460 DELAY(1000); 461 } 462 /* 463 * Don't need to worry about clearing MIIF_DOINGAUTO. 464 * If that's set, a timeout is pending, and it will 465 * clear the flag. 466 */ 467 return(EIO); 468 } 469 470 /* 471 * Just let it finish asynchronously. This is for the benefit of 472 * the tick handler driving autonegotiation. Don't want 500ms 473 * delays all the time while the system is running! 474 */ 475 if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) 476 mii->mii_flags |= MIIF_DOINGAUTO; 477 | |
| 478 return(EJUSTRETURN); 479} 480 481static void 482dcphy_reset(mii) 483 struct mii_softc *mii; 484{ 485 struct dc_softc *sc; 486 487 sc = mii->mii_pdata->mii_ifp->if_softc; 488 489 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 490 DELAY(1000); 491 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 492 493 return; 494} 495 | 447 return(EJUSTRETURN); 448} 449 450static void 451dcphy_reset(mii) 452 struct mii_softc *mii; 453{ 454 struct dc_softc *sc; 455 456 sc = mii->mii_pdata->mii_ifp->if_softc; 457 458 DC_CLRBIT(sc, DC_SIARESET, DC_SIA_RESET); 459 DELAY(1000); 460 DC_SETBIT(sc, DC_SIARESET, DC_SIA_RESET); 461 462 return; 463} 464 |