| cy.c (88088) | cy.c (88900) |
|---|---|
| 1/*- 2 * cyclades cyclom-y serial driver 3 * Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993 4 * 5 * Copyright (c) 1993 Andrew Herbert. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 13 unchanged lines hidden (view full) --- 22 * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 25 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 26 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 27 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * | 1/*- 2 * cyclades cyclom-y serial driver 3 * Andrew Herbert <andrew@werple.apana.org.au>, 17 August 1993 4 * 5 * Copyright (c) 1993 Andrew Herbert. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without --- 13 unchanged lines hidden (view full) --- 22 * NO EVENT SHALL I BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 23 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 24 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 25 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 26 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 27 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/dev/cy/cy.c 88088 2001-12-18 00:27:18Z jhb $ | 30 * $FreeBSD: head/sys/dev/cy/cy.c 88900 2002-01-05 08:47:13Z jhb $ |
| 31 */ 32 33#include "opt_compat.h" 34#include "cy.h" 35 36/* 37 * TODO: 38 * Atomic COR change. --- 1137 unchanged lines hidden (view full) --- 1176 if (serv_type & CD1400_RIVR_EXCEPTION) { 1177 ++com->recv_exception; 1178 line_status = cd_inb(iobase, CD1400_RDSR, cy_align); 1179 /* break/unnattached error bits or real input? */ 1180 recv_data = cd_inb(iobase, CD1400_RDSR, cy_align); 1181#ifndef SOFT_HOTCHAR 1182 if (line_status & CD1400_RDSR_SPECIAL 1183 && com->hotchar != 0) | 31 */ 32 33#include "opt_compat.h" 34#include "cy.h" 35 36/* 37 * TODO: 38 * Atomic COR change. --- 1137 unchanged lines hidden (view full) --- 1176 if (serv_type & CD1400_RIVR_EXCEPTION) { 1177 ++com->recv_exception; 1178 line_status = cd_inb(iobase, CD1400_RDSR, cy_align); 1179 /* break/unnattached error bits or real input? */ 1180 recv_data = cd_inb(iobase, CD1400_RDSR, cy_align); 1181#ifndef SOFT_HOTCHAR 1182 if (line_status & CD1400_RDSR_SPECIAL 1183 && com->hotchar != 0) |
| 1184 swi_sched(sio_ih, SWI_NOSWITCH); | 1184 swi_sched(sio_ih, 0); |
| 1185 1186#endif 1187#if 1 /* XXX "intelligent" PFO error handling would break O error handling */ 1188 if (line_status & (LSR_PE|LSR_FE|LSR_BI)) { 1189 /* 1190 Don't store PE if IGNPAR and BI if IGNBRK, 1191 this hack allows "raw" tty optimization 1192 works even if IGN* is set. --- 11 unchanged lines hidden (view full) --- 1204 || ((line_status & LSR_PE) 1205 && (com->tp->t_iflag & INPCK)))) 1206 recv_data = 0; 1207 } 1208#endif /* 1 */ 1209 ++com->bytes_in; 1210#ifdef SOFT_HOTCHAR 1211 if (com->hotchar != 0 && recv_data == com->hotchar) | 1185 1186#endif 1187#if 1 /* XXX "intelligent" PFO error handling would break O error handling */ 1188 if (line_status & (LSR_PE|LSR_FE|LSR_BI)) { 1189 /* 1190 Don't store PE if IGNPAR and BI if IGNBRK, 1191 this hack allows "raw" tty optimization 1192 works even if IGN* is set. --- 11 unchanged lines hidden (view full) --- 1204 || ((line_status & LSR_PE) 1205 && (com->tp->t_iflag & INPCK)))) 1206 recv_data = 0; 1207 } 1208#endif /* 1 */ 1209 ++com->bytes_in; 1210#ifdef SOFT_HOTCHAR 1211 if (com->hotchar != 0 && recv_data == com->hotchar) |
| 1212 swi_sched(sio_ih, SWI_NOSWITCH); | 1212 swi_sched(sio_ih, 0); |
| 1213#endif 1214 ioptr = com->iptr; 1215 if (ioptr >= com->ibufend) 1216 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1217 else { 1218 if (com->do_timestamp) 1219 microtime(&com->timestamp); 1220 ++com_events; --- 33 unchanged lines hidden (view full) --- 1254 do { 1255 recv_data = cd_inb(iobase, 1256 CD1400_RDSR, 1257 cy_align); 1258#ifdef SOFT_HOTCHAR 1259 if (com->hotchar != 0 1260 && recv_data 1261 == com->hotchar) | 1213#endif 1214 ioptr = com->iptr; 1215 if (ioptr >= com->ibufend) 1216 CE_RECORD(com, CE_INTERRUPT_BUF_OVERFLOW); 1217 else { 1218 if (com->do_timestamp) 1219 microtime(&com->timestamp); 1220 ++com_events; --- 33 unchanged lines hidden (view full) --- 1254 do { 1255 recv_data = cd_inb(iobase, 1256 CD1400_RDSR, 1257 cy_align); 1258#ifdef SOFT_HOTCHAR 1259 if (com->hotchar != 0 1260 && recv_data 1261 == com->hotchar) |
| 1262 swi_sched(sio_ih, SWI_NOSWITCH); | 1262 swi_sched(sio_ih, 0); |
| 1263#endif 1264 ioptr[0] = recv_data; 1265 ioptr[com->ierroff] = 0; 1266 ++ioptr; 1267 } while (--ifree != 0); 1268 } 1269 com->delta_error_counts 1270 [CE_INTERRUPT_BUF_OVERFLOW] += count; 1271 do { 1272 recv_data = cd_inb(iobase, CD1400_RDSR, 1273 cy_align); 1274#ifdef SOFT_HOTCHAR 1275 if (com->hotchar != 0 1276 && recv_data == com->hotchar) | 1263#endif 1264 ioptr[0] = recv_data; 1265 ioptr[com->ierroff] = 0; 1266 ++ioptr; 1267 } while (--ifree != 0); 1268 } 1269 com->delta_error_counts 1270 [CE_INTERRUPT_BUF_OVERFLOW] += count; 1271 do { 1272 recv_data = cd_inb(iobase, CD1400_RDSR, 1273 cy_align); 1274#ifdef SOFT_HOTCHAR 1275 if (com->hotchar != 0 1276 && recv_data == com->hotchar) |
| 1277 swi_sched(sio_ih, SWI_NOSWITCH); | 1277 swi_sched(sio_ih, 0); |
| 1278#endif 1279 } while (--count != 0); 1280 } else { 1281 if (com->do_timestamp) 1282 microtime(&com->timestamp); 1283 if (ioptr <= com->ihighwater 1284 && ioptr + count > com->ihighwater 1285 && com->state & CS_RTS_IFLOW) --- 8 unchanged lines hidden (view full) --- 1294#endif 1295 com_events += count; 1296 do { 1297 recv_data = cd_inb(iobase, CD1400_RDSR, 1298 cy_align); 1299#ifdef SOFT_HOTCHAR 1300 if (com->hotchar != 0 1301 && recv_data == com->hotchar) | 1278#endif 1279 } while (--count != 0); 1280 } else { 1281 if (com->do_timestamp) 1282 microtime(&com->timestamp); 1283 if (ioptr <= com->ihighwater 1284 && ioptr + count > com->ihighwater 1285 && com->state & CS_RTS_IFLOW) --- 8 unchanged lines hidden (view full) --- 1294#endif 1295 com_events += count; 1296 do { 1297 recv_data = cd_inb(iobase, CD1400_RDSR, 1298 cy_align); 1299#ifdef SOFT_HOTCHAR 1300 if (com->hotchar != 0 1301 && recv_data == com->hotchar) |
| 1302 swi_sched(sio_ih, SWI_NOSWITCH); | 1302 swi_sched(sio_ih, 0); |
| 1303#endif 1304 ioptr[0] = recv_data; 1305 ioptr[com->ierroff] = 0; 1306 ++ioptr; 1307 } while (--count != 0); 1308 } 1309 com->iptr = ioptr; 1310 } --- 48 unchanged lines hidden (view full) --- 1359 * that we don't use the delta bits anywhere. Some 1360 * UARTs mess them up, and it's easy to remember the 1361 * previous bits and calculate the delta. 1362 */ 1363 com->last_modem_status = modem_status; 1364 if (!(com->state & CS_CHECKMSR)) { 1365 com_events += LOTS_OF_EVENTS; 1366 com->state |= CS_CHECKMSR; | 1303#endif 1304 ioptr[0] = recv_data; 1305 ioptr[com->ierroff] = 0; 1306 ++ioptr; 1307 } while (--count != 0); 1308 } 1309 com->iptr = ioptr; 1310 } --- 48 unchanged lines hidden (view full) --- 1359 * that we don't use the delta bits anywhere. Some 1360 * UARTs mess them up, and it's easy to remember the 1361 * previous bits and calculate the delta. 1362 */ 1363 com->last_modem_status = modem_status; 1364 if (!(com->state & CS_CHECKMSR)) { 1365 com_events += LOTS_OF_EVENTS; 1366 com->state |= CS_CHECKMSR; |
| 1367 swi_sched(sio_ih, SWI_NOSWITCH); | 1367 swi_sched(sio_ih, 0); |
| 1368 } 1369 1370#ifdef SOFT_CTS_OFLOW 1371 /* handle CTS change immediately for crisp flow ctl */ 1372 if (com->state & CS_CTS_OFLOW) { 1373 if (modem_status & MSR_CTS) { 1374 com->state |= CS_ODEVREADY; 1375 if (com->state >= (CS_BUSY | CS_TTGO --- 114 unchanged lines hidden (view full) --- 1490 */ 1491 cd_outb(iobase, CD1400_COR2, cy_align, 1492 com->cor[1] 1493 &= ~CD1400_COR2_ETC); 1494 com->etc = ETC_BREAK_ENDED; 1495 if (!(com->state & CS_ODONE)) { 1496 com_events += LOTS_OF_EVENTS; 1497 com->state |= CS_ODONE; | 1368 } 1369 1370#ifdef SOFT_CTS_OFLOW 1371 /* handle CTS change immediately for crisp flow ctl */ 1372 if (com->state & CS_CTS_OFLOW) { 1373 if (modem_status & MSR_CTS) { 1374 com->state |= CS_ODEVREADY; 1375 if (com->state >= (CS_BUSY | CS_TTGO --- 114 unchanged lines hidden (view full) --- 1490 */ 1491 cd_outb(iobase, CD1400_COR2, cy_align, 1492 com->cor[1] 1493 &= ~CD1400_COR2_ETC); 1494 com->etc = ETC_BREAK_ENDED; 1495 if (!(com->state & CS_ODONE)) { 1496 com_events += LOTS_OF_EVENTS; 1497 com->state |= CS_ODONE; |
| 1498 swi_sched(sio_ih, SWI_NOSWITCH); | 1498 swi_sched(sio_ih, 0); |
| 1499 } 1500 break; 1501 case ETC_BREAK_ENDED: 1502 /* 1503 * Shouldn't get here. Hope again. 1504 */ 1505 break; 1506 } 1507 } 1508 if (com->intr_enable & CD1400_SRER_TXMPTY) { 1509 if (!(com->extra_state & CSE_ODONE)) { 1510 com_events += LOTS_OF_EVENTS; 1511 com->extra_state |= CSE_ODONE; | 1499 } 1500 break; 1501 case ETC_BREAK_ENDED: 1502 /* 1503 * Shouldn't get here. Hope again. 1504 */ 1505 break; 1506 } 1507 } 1508 if (com->intr_enable & CD1400_SRER_TXMPTY) { 1509 if (!(com->extra_state & CSE_ODONE)) { 1510 com_events += LOTS_OF_EVENTS; 1511 com->extra_state |= CSE_ODONE; |
| 1512 swi_sched(sio_ih, SWI_NOSWITCH); | 1512 swi_sched(sio_ih, 0); |
| 1513 } 1514 cd_outb(iobase, CD1400_SRER, cy_align, 1515 com->intr_enable 1516 &= ~CD1400_SRER_TXMPTY); 1517 goto terminate_tx_service; 1518 } 1519 if (com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1520 u_char *ioptr; --- 41 unchanged lines hidden (view full) --- 1562 & ~CD1400_SRER_TXRDY) 1563 | CD1400_SRER_TXMPTY); 1564 } 1565 if (!(com->state & CS_ODONE)) { 1566 com_events += LOTS_OF_EVENTS; 1567 com->state |= CS_ODONE; 1568 1569 /* handle at high level ASAP */ | 1513 } 1514 cd_outb(iobase, CD1400_SRER, cy_align, 1515 com->intr_enable 1516 &= ~CD1400_SRER_TXMPTY); 1517 goto terminate_tx_service; 1518 } 1519 if (com->state >= (CS_BUSY | CS_TTGO | CS_ODEVREADY)) { 1520 u_char *ioptr; --- 41 unchanged lines hidden (view full) --- 1562 & ~CD1400_SRER_TXRDY) 1563 | CD1400_SRER_TXMPTY); 1564 } 1565 if (!(com->state & CS_ODONE)) { 1566 com_events += LOTS_OF_EVENTS; 1567 com->state |= CS_ODONE; 1568 1569 /* handle at high level ASAP */ |
| 1570 swi_sched(sio_ih, SWI_NOSWITCH); | 1570 swi_sched(sio_ih, 0); |
| 1571 } 1572 } 1573 } 1574 1575 /* terminate service context */ 1576terminate_tx_service: 1577#ifdef PollMode 1578 cd_outb(iobase, CD1400_TIR, cy_align, 1579 save_tir 1580 & ~(CD1400_TIR_RDIREQ | CD1400_TIR_RBUSY)); 1581#else 1582 cd_outb(iobase, CD1400_EOSRR, cy_align, 0); 1583#endif 1584 } 1585 } 1586 1587 /* ensure an edge for the next interrupt */ 1588 cy_outb(cy_iobase, CY_CLEAR_INTR, cy_align, 0); 1589 | 1571 } 1572 } 1573 } 1574 1575 /* terminate service context */ 1576terminate_tx_service: 1577#ifdef PollMode 1578 cd_outb(iobase, CD1400_TIR, cy_align, 1579 save_tir 1580 & ~(CD1400_TIR_RDIREQ | CD1400_TIR_RBUSY)); 1581#else 1582 cd_outb(iobase, CD1400_EOSRR, cy_align, 0); 1583#endif 1584 } 1585 } 1586 1587 /* ensure an edge for the next interrupt */ 1588 cy_outb(cy_iobase, CY_CLEAR_INTR, cy_align, 0); 1589 |
| 1590 swi_sched(sio_ih, SWI_NOSWITCH); | 1590 swi_sched(sio_ih, 0); |
| 1591 1592 COM_UNLOCK(); 1593} 1594 1595#if 0 1596static void 1597siointr1(com) 1598 struct com_s *com; --- 1365 unchanged lines hidden --- | 1591 1592 COM_UNLOCK(); 1593} 1594 1595#if 0 1596static void 1597siointr1(com) 1598 struct com_s *com; --- 1365 unchanged lines hidden --- |