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1/*
2 * Copyright (c) 2009-2013 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
29 * SOFTWARE.
30 *
31 * $FreeBSD: head/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h 256694 2013-10-17 18:37:25Z np $
31 * $FreeBSD: head/sys/dev/cxgbe/iw_cxgbe/iw_cxgbe.h 273135 2014-10-15 13:40:29Z hselasky $
32 */
33#ifndef __IW_CXGB4_H__
34#define __IW_CXGB4_H__
35
36#include <linux/list.h>
37#include <linux/spinlock.h>
38#include <linux/idr.h>
39#include <linux/completion.h>
40#include <linux/netdevice.h>
41#include <linux/sched.h>
42#include <linux/pci.h>
43#include <linux/dma-mapping.h>
44#include <linux/inet.h>
44#include <linux/wait.h>
45#include <linux/kref.h>
46#include <linux/timer.h>
47#include <linux/io.h>
48
49#include <asm/byteorder.h>
50
51#include <netinet/in.h>
52#include <netinet/toecore.h>
53
54#include <rdma/ib_verbs.h>
55#include <rdma/iw_cm.h>
56
57#undef prefetch
58
59#include "common/common.h"
60#include "common/t4_msg.h"
61#include "common/t4_regs.h"
62#include "common/t4_tcb.h"
63#include "t4_l2t.h"
64
65#define DRV_NAME "iw_cxgbe"
66#define MOD DRV_NAME ":"
67#define KTR_IW_CXGBE KTR_SPARE3
68
69extern int c4iw_debug;
70#define PDBG(fmt, args...) \
71do { \
72 if (c4iw_debug) \
73 printf(MOD fmt, ## args); \
74} while (0)
75
76#include "t4.h"
77
78static inline void *cplhdr(struct mbuf *m)
79{
80 return mtod(m, void*);
81}
82
83#define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
84#define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
85
86#define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
87#define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
88
89struct c4iw_id_table {
90 u32 flags;
91 u32 start; /* logical minimal id */
92 u32 last; /* hint for find */
93 u32 max;
94 spinlock_t lock;
95 unsigned long *table;
96};
97
98struct c4iw_resource {
99 struct c4iw_id_table tpt_table;
100 struct c4iw_id_table qid_table;
101 struct c4iw_id_table pdid_table;
102};
103
104struct c4iw_qid_list {
105 struct list_head entry;
106 u32 qid;
107};
108
109struct c4iw_dev_ucontext {
110 struct list_head qpids;
111 struct list_head cqids;
112 struct mutex lock;
113};
114
115enum c4iw_rdev_flags {
116 T4_FATAL_ERROR = (1<<0),
117};
118
119struct c4iw_stat {
120 u64 total;
121 u64 cur;
122 u64 max;
123 u64 fail;
124};
125
126struct c4iw_stats {
127 struct mutex lock;
128 struct c4iw_stat qid;
129 struct c4iw_stat pd;
130 struct c4iw_stat stag;
131 struct c4iw_stat pbl;
132 struct c4iw_stat rqt;
133 u64 db_full;
134 u64 db_empty;
135 u64 db_drop;
136 u64 db_state_transitions;
137};
138
139struct c4iw_rdev {
140 struct adapter *adap;
141 struct c4iw_resource resource;
142 unsigned long qpshift;
143 u32 qpmask;
144 unsigned long cqshift;
145 u32 cqmask;
146 struct c4iw_dev_ucontext uctx;
147 struct gen_pool *pbl_pool;
148 struct gen_pool *rqt_pool;
149 u32 flags;
150 struct c4iw_stats stats;
151};
152
153static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
154{
155 return rdev->flags & T4_FATAL_ERROR;
156}
157
158static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
159{
160 return min((int)T4_MAX_NUM_STAG, (int)(rdev->adap->vres.stag.size >> 5));
161}
162
163#define C4IW_WR_TO (10*HZ)
164
165struct c4iw_wr_wait {
166 int ret;
167 atomic_t completion;
168};
169
170static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
171{
172 wr_waitp->ret = 0;
173 atomic_set(&wr_waitp->completion, 0);
174}
175
176static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
177{
178 wr_waitp->ret = ret;
179 atomic_set(&wr_waitp->completion, 1);
180 wakeup(wr_waitp);
181}
182
183static inline int
184c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
185 u32 hwtid, u32 qpid, const char *func)
186{
187 struct adapter *sc = rdev->adap;
188 unsigned to = C4IW_WR_TO;
189
190 while (!atomic_read(&wr_waitp->completion)) {
191 tsleep(wr_waitp, 0, "c4iw_wait", to);
192 if (SIGPENDING(curthread)) {
193 printf("%s - Device %s not responding - "
194 "tid %u qpid %u\n", func,
195 device_get_nameunit(sc->dev), hwtid, qpid);
196 if (c4iw_fatal_error(rdev)) {
197 wr_waitp->ret = -EIO;
198 break;
199 }
200 to = to << 2;
201 }
202 }
203 if (wr_waitp->ret)
204 CTR4(KTR_IW_CXGBE, "%s: FW reply %d tid %u qpid %u",
205 device_get_nameunit(sc->dev), wr_waitp->ret, hwtid, qpid);
206 return (wr_waitp->ret);
207}
208
209enum db_state {
210 NORMAL = 0,
211 FLOW_CONTROL = 1,
212 RECOVERY = 2
213};
214
215struct c4iw_dev {
216 struct ib_device ibdev;
217 struct c4iw_rdev rdev;
218 u32 device_cap_flags;
219 struct idr cqidr;
220 struct idr qpidr;
221 struct idr mmidr;
222 spinlock_t lock;
223 struct dentry *debugfs_root;
224 enum db_state db_state;
225 int qpcnt;
226};
227
228static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
229{
230 return container_of(ibdev, struct c4iw_dev, ibdev);
231}
232
233static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
234{
235 return container_of(rdev, struct c4iw_dev, rdev);
236}
237
238static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
239{
240 return idr_find(&rhp->cqidr, cqid);
241}
242
243static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
244{
245 return idr_find(&rhp->qpidr, qpid);
246}
247
248static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
249{
250 return idr_find(&rhp->mmidr, mmid);
251}
252
253static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
254 void *handle, u32 id, int lock)
255{
256 int ret;
257 int newid;
258
259 do {
260 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
261 return -ENOMEM;
262 if (lock)
263 spin_lock_irq(&rhp->lock);
264 ret = idr_get_new_above(idr, handle, id, &newid);
265 BUG_ON(!ret && newid != id);
266 if (lock)
267 spin_unlock_irq(&rhp->lock);
268 } while (ret == -EAGAIN);
269
270 return ret;
271}
272
273static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
274 void *handle, u32 id)
275{
276 return _insert_handle(rhp, idr, handle, id, 1);
277}
278
279static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
280 void *handle, u32 id)
281{
282 return _insert_handle(rhp, idr, handle, id, 0);
283}
284
285static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
286 u32 id, int lock)
287{
288 if (lock)
289 spin_lock_irq(&rhp->lock);
290 idr_remove(idr, id);
291 if (lock)
292 spin_unlock_irq(&rhp->lock);
293}
294
295static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
296{
297 _remove_handle(rhp, idr, id, 1);
298}
299
300static inline void remove_handle_nolock(struct c4iw_dev *rhp,
301 struct idr *idr, u32 id)
302{
303 _remove_handle(rhp, idr, id, 0);
304}
305
306struct c4iw_pd {
307 struct ib_pd ibpd;
308 u32 pdid;
309 struct c4iw_dev *rhp;
310};
311
312static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
313{
314 return container_of(ibpd, struct c4iw_pd, ibpd);
315}
316
317struct tpt_attributes {
318 u64 len;
319 u64 va_fbo;
320 enum fw_ri_mem_perms perms;
321 u32 stag;
322 u32 pdid;
323 u32 qpid;
324 u32 pbl_addr;
325 u32 pbl_size;
326 u32 state:1;
327 u32 type:2;
328 u32 rsvd:1;
329 u32 remote_invaliate_disable:1;
330 u32 zbva:1;
331 u32 mw_bind_enable:1;
332 u32 page_size:5;
333};
334
335struct c4iw_mr {
336 struct ib_mr ibmr;
337 struct ib_umem *umem;
338 struct c4iw_dev *rhp;
339 u64 kva;
340 struct tpt_attributes attr;
341};
342
343static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
344{
345 return container_of(ibmr, struct c4iw_mr, ibmr);
346}
347
348struct c4iw_mw {
349 struct ib_mw ibmw;
350 struct c4iw_dev *rhp;
351 u64 kva;
352 struct tpt_attributes attr;
353};
354
355static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
356{
357 return container_of(ibmw, struct c4iw_mw, ibmw);
358}
359
360struct c4iw_fr_page_list {
361 struct ib_fast_reg_page_list ibpl;
362 DECLARE_PCI_UNMAP_ADDR(mapping);
363 dma_addr_t dma_addr;
364 struct c4iw_dev *dev;
365 int size;
366};
367
368static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
369 struct ib_fast_reg_page_list *ibpl)
370{
371 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
372}
373
374struct c4iw_cq {
375 struct ib_cq ibcq;
376 struct c4iw_dev *rhp;
377 struct t4_cq cq;
378 spinlock_t lock;
379 spinlock_t comp_handler_lock;
380 atomic_t refcnt;
381 wait_queue_head_t wait;
382};
383
384static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
385{
386 return container_of(ibcq, struct c4iw_cq, ibcq);
387}
388
389struct c4iw_mpa_attributes {
390 u8 initiator;
391 u8 recv_marker_enabled;
392 u8 xmit_marker_enabled;
393 u8 crc_enabled;
394 u8 enhanced_rdma_conn;
395 u8 version;
396 u8 p2p_type;
397};
398
399struct c4iw_qp_attributes {
400 u32 scq;
401 u32 rcq;
402 u32 sq_num_entries;
403 u32 rq_num_entries;
404 u32 sq_max_sges;
405 u32 sq_max_sges_rdma_write;
406 u32 rq_max_sges;
407 u32 state;
408 u8 enable_rdma_read;
409 u8 enable_rdma_write;
410 u8 enable_bind;
411 u8 enable_mmid0_fastreg;
412 u32 max_ord;
413 u32 max_ird;
414 u32 pd;
415 u32 next_state;
416 char terminate_buffer[52];
417 u32 terminate_msg_len;
418 u8 is_terminate_local;
419 struct c4iw_mpa_attributes mpa_attr;
420 struct c4iw_ep *llp_stream_handle;
421 u8 layer_etype;
422 u8 ecode;
423 u16 sq_db_inc;
424 u16 rq_db_inc;
425};
426
427struct c4iw_qp {
428 struct ib_qp ibqp;
429 struct c4iw_dev *rhp;
430 struct c4iw_ep *ep;
431 struct c4iw_qp_attributes attr;
432 struct t4_wq wq;
433 spinlock_t lock;
434 struct mutex mutex;
435 atomic_t refcnt;
436 wait_queue_head_t wait;
437 struct timer_list timer;
438};
439
440static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
441{
442 return container_of(ibqp, struct c4iw_qp, ibqp);
443}
444
445struct c4iw_ucontext {
446 struct ib_ucontext ibucontext;
447 struct c4iw_dev_ucontext uctx;
448 u32 key;
449 spinlock_t mmap_lock;
450 struct list_head mmaps;
451};
452
453static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
454{
455 return container_of(c, struct c4iw_ucontext, ibucontext);
456}
457
458struct c4iw_mm_entry {
459 struct list_head entry;
460 u64 addr;
461 u32 key;
462 unsigned len;
463};
464
465static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
466 u32 key, unsigned len)
467{
468 struct list_head *pos, *nxt;
469 struct c4iw_mm_entry *mm;
470
471 spin_lock(&ucontext->mmap_lock);
472 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
473
474 mm = list_entry(pos, struct c4iw_mm_entry, entry);
475 if (mm->key == key && mm->len == len) {
476 list_del_init(&mm->entry);
477 spin_unlock(&ucontext->mmap_lock);
478 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
479 __func__, key, (unsigned long long) mm->addr,
480 mm->len);
481 return mm;
482 }
483 }
484 spin_unlock(&ucontext->mmap_lock);
485 return NULL;
486}
487
488static inline void insert_mmap(struct c4iw_ucontext *ucontext,
489 struct c4iw_mm_entry *mm)
490{
491 spin_lock(&ucontext->mmap_lock);
492 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
493 (unsigned long long) mm->addr, mm->len);
494 list_add_tail(&mm->entry, &ucontext->mmaps);
495 spin_unlock(&ucontext->mmap_lock);
496}
497
498enum c4iw_qp_attr_mask {
499 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
500 C4IW_QP_ATTR_SQ_DB = 1<<1,
501 C4IW_QP_ATTR_RQ_DB = 1<<2,
502 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
503 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
504 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
505 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
506 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
507 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
508 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
509 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
510 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
511 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
512 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
513 C4IW_QP_ATTR_MAX_ORD |
514 C4IW_QP_ATTR_MAX_IRD |
515 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
516 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
517 C4IW_QP_ATTR_MPA_ATTR |
518 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
519};
520
521int c4iw_modify_qp(struct c4iw_dev *rhp,
522 struct c4iw_qp *qhp,
523 enum c4iw_qp_attr_mask mask,
524 struct c4iw_qp_attributes *attrs,
525 int internal);
526
527enum c4iw_qp_state {
528 C4IW_QP_STATE_IDLE,
529 C4IW_QP_STATE_RTS,
530 C4IW_QP_STATE_ERROR,
531 C4IW_QP_STATE_TERMINATE,
532 C4IW_QP_STATE_CLOSING,
533 C4IW_QP_STATE_TOT
534};
535
536static inline int c4iw_convert_state(enum ib_qp_state ib_state)
537{
538 switch (ib_state) {
539 case IB_QPS_RESET:
540 case IB_QPS_INIT:
541 return C4IW_QP_STATE_IDLE;
542 case IB_QPS_RTS:
543 return C4IW_QP_STATE_RTS;
544 case IB_QPS_SQD:
545 return C4IW_QP_STATE_CLOSING;
546 case IB_QPS_SQE:
547 return C4IW_QP_STATE_TERMINATE;
548 case IB_QPS_ERR:
549 return C4IW_QP_STATE_ERROR;
550 default:
551 return -1;
552 }
553}
554
555static inline int to_ib_qp_state(int c4iw_qp_state)
556{
557 switch (c4iw_qp_state) {
558 case C4IW_QP_STATE_IDLE:
559 return IB_QPS_INIT;
560 case C4IW_QP_STATE_RTS:
561 return IB_QPS_RTS;
562 case C4IW_QP_STATE_CLOSING:
563 return IB_QPS_SQD;
564 case C4IW_QP_STATE_TERMINATE:
565 return IB_QPS_SQE;
566 case C4IW_QP_STATE_ERROR:
567 return IB_QPS_ERR;
568 }
569 return IB_QPS_ERR;
570}
571
572static inline u32 c4iw_ib_to_tpt_access(int a)
573{
574 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
575 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
576 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
577 FW_RI_MEM_ACCESS_LOCAL_READ;
578}
579
580static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
581{
582 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
583 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
584}
585
586enum c4iw_mmid_state {
587 C4IW_STAG_STATE_VALID,
588 C4IW_STAG_STATE_INVALID
589};
590
591#define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
592
593#define MPA_KEY_REQ "MPA ID Req Frame"
594#define MPA_KEY_REP "MPA ID Rep Frame"
595
596#define MPA_MAX_PRIVATE_DATA 256
597#define MPA_ENHANCED_RDMA_CONN 0x10
598#define MPA_REJECT 0x20
599#define MPA_CRC 0x40
600#define MPA_MARKERS 0x80
601#define MPA_FLAGS_MASK 0xE0
602
603#define MPA_V2_PEER2PEER_MODEL 0x8000
604#define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
605#define MPA_V2_RDMA_WRITE_RTR 0x8000
606#define MPA_V2_RDMA_READ_RTR 0x4000
607#define MPA_V2_IRD_ORD_MASK 0x3FFF
608
609/* Fixme: Use atomic_read for kref.count as same as Linux */
610#define c4iw_put_ep(ep) { \
611 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
612 __func__, __LINE__, ep, (ep)->kref.count); \
613 WARN_ON((ep)->kref.count < 1); \
614 kref_put(&((ep)->kref), _c4iw_free_ep); \
615}
616
617/* Fixme: Use atomic_read for kref.count as same as Linux */
618#define c4iw_get_ep(ep) { \
619 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
620 __func__, __LINE__, ep, (ep)->kref.count); \
621 kref_get(&((ep)->kref)); \
622}
623
624void _c4iw_free_ep(struct kref *kref);
625
626struct mpa_message {
627 u8 key[16];
628 u8 flags;
629 u8 revision;
630 __be16 private_data_size;
631 u8 private_data[0];
632};
633
634struct mpa_v2_conn_params {
635 __be16 ird;
636 __be16 ord;
637};
638
639struct terminate_message {
640 u8 layer_etype;
641 u8 ecode;
642 __be16 hdrct_rsvd;
643 u8 len_hdrs[0];
644};
645
646#define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
647
648enum c4iw_layers_types {
649 LAYER_RDMAP = 0x00,
650 LAYER_DDP = 0x10,
651 LAYER_MPA = 0x20,
652 RDMAP_LOCAL_CATA = 0x00,
653 RDMAP_REMOTE_PROT = 0x01,
654 RDMAP_REMOTE_OP = 0x02,
655 DDP_LOCAL_CATA = 0x00,
656 DDP_TAGGED_ERR = 0x01,
657 DDP_UNTAGGED_ERR = 0x02,
658 DDP_LLP = 0x03
659};
660
661enum c4iw_rdma_ecodes {
662 RDMAP_INV_STAG = 0x00,
663 RDMAP_BASE_BOUNDS = 0x01,
664 RDMAP_ACC_VIOL = 0x02,
665 RDMAP_STAG_NOT_ASSOC = 0x03,
666 RDMAP_TO_WRAP = 0x04,
667 RDMAP_INV_VERS = 0x05,
668 RDMAP_INV_OPCODE = 0x06,
669 RDMAP_STREAM_CATA = 0x07,
670 RDMAP_GLOBAL_CATA = 0x08,
671 RDMAP_CANT_INV_STAG = 0x09,
672 RDMAP_UNSPECIFIED = 0xff
673};
674
675enum c4iw_ddp_ecodes {
676 DDPT_INV_STAG = 0x00,
677 DDPT_BASE_BOUNDS = 0x01,
678 DDPT_STAG_NOT_ASSOC = 0x02,
679 DDPT_TO_WRAP = 0x03,
680 DDPT_INV_VERS = 0x04,
681 DDPU_INV_QN = 0x01,
682 DDPU_INV_MSN_NOBUF = 0x02,
683 DDPU_INV_MSN_RANGE = 0x03,
684 DDPU_INV_MO = 0x04,
685 DDPU_MSG_TOOBIG = 0x05,
686 DDPU_INV_VERS = 0x06
687};
688
689enum c4iw_mpa_ecodes {
690 MPA_CRC_ERR = 0x02,
691 MPA_MARKER_ERR = 0x03,
692 MPA_LOCAL_CATA = 0x05,
693 MPA_INSUFF_IRD = 0x06,
694 MPA_NOMATCH_RTR = 0x07,
695};
696
697enum c4iw_ep_state {
698 IDLE = 0,
699 LISTEN,
700 CONNECTING,
701 MPA_REQ_WAIT,
702 MPA_REQ_SENT,
703 MPA_REQ_RCVD,
704 MPA_REP_SENT,
705 FPDU_MODE,
706 ABORTING,
707 CLOSING,
708 MORIBUND,
709 DEAD,
710};
711
712enum c4iw_ep_flags {
713 PEER_ABORT_IN_PROGRESS = 0,
714 ABORT_REQ_IN_PROGRESS = 1,
715 RELEASE_RESOURCES = 2,
716 CLOSE_SENT = 3,
717 TIMEOUT = 4
718};
719
720enum c4iw_ep_history {
721 ACT_OPEN_REQ = 0,
722 ACT_OFLD_CONN = 1,
723 ACT_OPEN_RPL = 2,
724 ACT_ESTAB = 3,
725 PASS_ACCEPT_REQ = 4,
726 PASS_ESTAB = 5,
727 ABORT_UPCALL = 6,
728 ESTAB_UPCALL = 7,
729 CLOSE_UPCALL = 8,
730 ULP_ACCEPT = 9,
731 ULP_REJECT = 10,
732 TIMEDOUT = 11,
733 PEER_ABORT = 12,
734 PEER_CLOSE = 13,
735 CONNREQ_UPCALL = 14,
736 ABORT_CONN = 15,
737 DISCONN_UPCALL = 16,
738 EP_DISC_CLOSE = 17,
739 EP_DISC_ABORT = 18,
740 CONN_RPL_UPCALL = 19,
741 ACT_RETRY_NOMEM = 20,
742 ACT_RETRY_INUSE = 21
743};
744
745struct c4iw_ep_common {
746 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
747 struct iw_cm_id *cm_id;
748 struct c4iw_qp *qp;
749 struct c4iw_dev *dev;
750 enum c4iw_ep_state state;
751 struct kref kref;
752 struct mutex mutex;
753 struct sockaddr_in local_addr;
754 struct sockaddr_in remote_addr;
755 struct c4iw_wr_wait wr_wait;
756 unsigned long flags;
757 unsigned long history;
758 int rpl_err;
759 int rpl_done;
760 struct thread *thread;
761 struct socket *so;
762};
763
764struct c4iw_listen_ep {
765 struct c4iw_ep_common com;
766 unsigned int stid;
767 int backlog;
768};
769
770struct c4iw_ep {
771 struct c4iw_ep_common com;
772 struct c4iw_ep *parent_ep;
773 struct timer_list timer;
774 struct list_head entry;
775 unsigned int atid;
776 u32 hwtid;
777 u32 snd_seq;
778 u32 rcv_seq;
779 struct l2t_entry *l2t;
780 struct dst_entry *dst;
781 struct c4iw_mpa_attributes mpa_attr;
782 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
783 unsigned int mpa_pkt_len;
784 u32 ird;
785 u32 ord;
786 u32 smac_idx;
787 u32 tx_chan;
788 u32 mtu;
789 u16 mss;
790 u16 emss;
791 u16 plen;
792 u16 rss_qid;
793 u16 txq_idx;
794 u16 ctrlq_idx;
795 u8 tos;
796 u8 retry_with_mpa_v1;
797 u8 tried_with_mpa_v1;
798};
799
800static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
801{
802 return cm_id->provider_data;
803}
804
805static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
806{
807 return cm_id->provider_data;
808}
809
810static inline int compute_wscale(int win)
811{
812 int wscale = 0;
813
814 while (wscale < 14 && (65535<<wscale) < win)
815 wscale++;
816 return wscale;
817}
818
819u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
820void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
821int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
822 u32 reserved, u32 flags);
823void c4iw_id_table_free(struct c4iw_id_table *alloc);
824
825typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
826
827int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
828 struct l2t_entry *l2t);
829u32 c4iw_get_resource(struct c4iw_id_table *id_table);
830void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
831int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
832int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
833int c4iw_pblpool_create(struct c4iw_rdev *rdev);
834int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
835void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
836void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
837void c4iw_destroy_resource(struct c4iw_resource *rscp);
838int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
839int c4iw_register_device(struct c4iw_dev *dev);
840void c4iw_unregister_device(struct c4iw_dev *dev);
841int __init c4iw_cm_init(void);
842void __exit c4iw_cm_term(void);
843void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
844 struct c4iw_dev_ucontext *uctx);
845void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
846 struct c4iw_dev_ucontext *uctx);
847int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
848int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
849 struct ib_send_wr **bad_wr);
850int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
851 struct ib_recv_wr **bad_wr);
852int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
853 struct ib_mw_bind *mw_bind);
854int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
855int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog);
856int c4iw_destroy_listen(struct iw_cm_id *cm_id);
857int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
858int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
859void c4iw_qp_add_ref(struct ib_qp *qp);
860void c4iw_qp_rem_ref(struct ib_qp *qp);
861void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
862struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
863 struct ib_device *device,
864 int page_list_len);
865struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
866int c4iw_dealloc_mw(struct ib_mw *mw);
867struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
868struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
869 virt, int acc, struct ib_udata *udata, int mr_id);
870struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
871struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
872 struct ib_phys_buf *buffer_list,
873 int num_phys_buf,
874 int acc,
875 u64 *iova_start);
876int c4iw_reregister_phys_mem(struct ib_mr *mr,
877 int mr_rereg_mask,
878 struct ib_pd *pd,
879 struct ib_phys_buf *buffer_list,
880 int num_phys_buf,
881 int acc, u64 *iova_start);
882int c4iw_dereg_mr(struct ib_mr *ib_mr);
883int c4iw_destroy_cq(struct ib_cq *ib_cq);
884struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
885 int vector,
886 struct ib_ucontext *ib_context,
887 struct ib_udata *udata);
888int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
889int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
890int c4iw_destroy_qp(struct ib_qp *ib_qp);
891struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
892 struct ib_qp_init_attr *attrs,
893 struct ib_udata *udata);
894int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
895 int attr_mask, struct ib_udata *udata);
896int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
897 int attr_mask, struct ib_qp_init_attr *init_attr);
898struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
899u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
900void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
901u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
902void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
903int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
904void c4iw_flush_hw_cq(struct t4_cq *cq);
905void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
906void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
907int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
908int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
909int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
910int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
911u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
912int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
913u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
914void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
915 struct c4iw_dev_ucontext *uctx);
916u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
917void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
918 struct c4iw_dev_ucontext *uctx);
919void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
920
921extern struct cxgb4_client t4c_client;
922extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
923extern int c4iw_max_read_depth;
924
925#include <sys/blist.h>
926struct gen_pool {
927 blist_t gen_list;
928 daddr_t gen_base;
929 int gen_chunk_shift;
930 struct mutex gen_lock;
931};
932
933static __inline struct gen_pool *
934gen_pool_create(daddr_t base, u_int chunk_shift, u_int len)
935{
936 struct gen_pool *gp;
937
938 gp = malloc(sizeof(struct gen_pool), M_DEVBUF, M_NOWAIT);
939 if (gp == NULL)
940 return (NULL);
941
942 memset(gp, 0, sizeof(struct gen_pool));
943 gp->gen_list = blist_create(len >> chunk_shift, M_NOWAIT);
944 if (gp->gen_list == NULL) {
945 free(gp, M_DEVBUF);
946 return (NULL);
947 }
948 blist_free(gp->gen_list, 0, len >> chunk_shift);
949 gp->gen_base = base;
950 gp->gen_chunk_shift = chunk_shift;
951 //mutex_init(&gp->gen_lock, "genpool", NULL, MTX_DUPOK|MTX_DEF);
952 mutex_init(&gp->gen_lock);
953
954 return (gp);
955}
956
957static __inline unsigned long
958gen_pool_alloc(struct gen_pool *gp, int size)
959{
960 int chunks;
961 daddr_t blkno;
962
963 chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift;
964 mutex_lock(&gp->gen_lock);
965 blkno = blist_alloc(gp->gen_list, chunks);
966 mutex_unlock(&gp->gen_lock);
967
968 if (blkno == SWAPBLK_NONE)
969 return (0);
970
971 return (gp->gen_base + ((1 << gp->gen_chunk_shift) * blkno));
972}
973
974static __inline void
975gen_pool_free(struct gen_pool *gp, daddr_t address, int size)
976{
977 int chunks;
978 daddr_t blkno;
979
980 chunks = (size + (1<<gp->gen_chunk_shift) - 1) >> gp->gen_chunk_shift;
981 blkno = (address - gp->gen_base) / (1 << gp->gen_chunk_shift);
982 mutex_lock(&gp->gen_lock);
983 blist_free(gp->gen_list, blkno, chunks);
984 mutex_unlock(&gp->gen_lock);
985}
986
987static __inline void
988gen_pool_destroy(struct gen_pool *gp)
989{
990 blist_destroy(gp->gen_list);
991 free(gp, M_DEVBUF);
992}
993
994#if defined(__i386__) || defined(__amd64__)
995#define L1_CACHE_BYTES 128
996#else
997#define L1_CACHE_BYTES 32
998#endif
999
1000static inline
1001int idr_for_each(struct idr *idp,
1002 int (*fn)(int id, void *p, void *data), void *data)
1003{
1004 int n, id, max, error = 0;
1005 struct idr_layer *p;
1006 struct idr_layer *pa[MAX_LEVEL];
1007 struct idr_layer **paa = &pa[0];
1008
1009 n = idp->layers * IDR_BITS;
1010 p = idp->top;
1011 max = 1 << n;
1012
1013 id = 0;
1014 while (id < max) {
1015 while (n > 0 && p) {
1016 n -= IDR_BITS;
1017 *paa++ = p;
1018 p = p->ary[(id >> n) & IDR_MASK];
1019 }
1020
1021 if (p) {
1022 error = fn(id, (void *)p, data);
1023 if (error)
1024 break;
1025 }
1026
1027 id += 1 << n;
1028 while (n < fls(id)) {
1029 n += IDR_BITS;
1030 p = *--paa;
1031 }
1032 }
1033
1034 return error;
1035}
1036
1037void c4iw_cm_init_cpl(struct adapter *);
1038void c4iw_cm_term_cpl(struct adapter *);
1039
1040void your_reg_device(struct c4iw_dev *dev);
1041
1042#define SGE_CTRLQ_NUM 0
1043
1044extern int spg_creds;/* Status Page size in credit units(1 unit = 64) */
1045#endif