4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
| 4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
15
16THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26POSSIBILITY OF SUCH DAMAGE.
27
|
29
30***************************************************************************/
31#ifndef __CHIOCTL_H__
32#define __CHIOCTL_H__
33
34/*
35 * Ioctl commands specific to this driver.
36 */
37enum {
38 CH_SETREG = 0x40,
39 CH_GETREG,
40 CH_SETTPI,
41 CH_GETTPI,
42 CH_DEVUP,
43 CH_GETMTUTAB,
44 CH_SETMTUTAB,
45 CH_GETMTU,
46 CH_SET_PM,
47 CH_GET_PM,
48 CH_GET_TCAM,
49 CH_SET_TCAM,
50 CH_GET_TCB,
51 CH_READ_TCAM_WORD,
52 CH_GET_MEM,
53 CH_GET_SGE_CONTEXT,
54 CH_GET_SGE_DESC,
55 CH_LOAD_FW,
56 CH_GET_PROTO,
57 CH_SET_PROTO,
58 CH_SET_TRACE_FILTER,
59 CH_SET_QSET_PARAMS,
60 CH_GET_QSET_PARAMS,
61 CH_SET_QSET_NUM,
62 CH_GET_QSET_NUM,
63 CH_SET_PKTSCHED,
64 CH_IFCONF_GETREGS,
65 CH_GETMIIREGS,
66 CH_SETMIIREGS,
67 CH_SET_FILTER,
68 CH_SET_HW_SCHED,
69 CH_DEL_FILTER,
70};
71
72struct ch_reg {
73 uint32_t addr;
74 uint32_t val;
75};
76
77struct ch_cntxt {
78 uint32_t cntxt_type;
79 uint32_t cntxt_id;
80 uint32_t data[4];
81};
82
83/* context types */
84enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
85
86struct ch_desc {
87 uint32_t cmd;
88 uint32_t queue_num;
89 uint32_t idx;
90 uint32_t size;
91 uint8_t data[128];
92};
93
94struct ch_mem_range {
95 uint32_t cmd;
96 uint32_t mem_id;
97 uint32_t addr;
98 uint32_t len;
99 uint32_t version;
100 uint8_t *buf;
101};
102
103struct ch_qset_params {
104 uint32_t qset_idx;
105 int32_t txq_size[3];
106 int32_t rspq_size;
107 int32_t fl_size[2];
108 int32_t intr_lat;
109 int32_t polling;
110 int32_t lro;
111 int32_t cong_thres;
112 int32_t vector;
113 int32_t qnum;
114};
115
116struct ch_pktsched_params {
117 uint32_t cmd;
118 uint8_t sched;
119 uint8_t idx;
120 uint8_t min;
121 uint8_t max;
122 uint8_t binding;
123};
124
125struct ch_hw_sched {
126 uint32_t cmd;
127 uint8_t sched;
128 int8_t mode;
129 int8_t channel;
130 int32_t kbps; /* rate in Kbps */
131 int32_t class_ipg; /* tenths of nanoseconds */
132 uint32_t flow_ipg; /* usec */
133};
134
135struct ch_filter_tuple {
136 uint32_t sip;
137 uint32_t dip;
138 uint16_t sport;
139 uint16_t dport;
140 uint16_t vlan:12;
141 uint16_t vlan_prio:3;
142};
143
144struct ch_filter {
145 uint32_t cmd;
146 uint32_t filter_id;
147 struct ch_filter_tuple val;
148 struct ch_filter_tuple mask;
149 uint16_t mac_addr_idx;
150 uint8_t mac_hit:1;
151 uint8_t proto:2;
152
153 uint8_t want_filter_id:1; /* report filter TID instead of RSS hash */
154 uint8_t pass:1; /* whether to pass or drop packets */
155 uint8_t rss:1; /* use RSS or specified qset */
156 uint8_t qset;
157};
158
159#ifndef TCB_SIZE
160# define TCB_SIZE 128
161#endif
162
163/* TCB size in 32-bit words */
164#define TCB_WORDS (TCB_SIZE / 4)
165
166enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */
167
168struct ch_mtus {
169 uint32_t cmd;
170 uint32_t nmtus;
171 uint16_t mtus[NMTUS];
172};
173
174struct ch_pm {
175 uint32_t cmd;
176 uint32_t tx_pg_sz;
177 uint32_t tx_num_pg;
178 uint32_t rx_pg_sz;
179 uint32_t rx_num_pg;
180 uint32_t pm_total;
181};
182
183struct ch_tcam {
184 uint32_t cmd;
185 uint32_t tcam_size;
186 uint32_t nservers;
187 uint32_t nroutes;
188 uint32_t nfilters;
189};
190
191struct ch_tcb {
192 uint32_t cmd;
193 uint32_t tcb_index;
194 uint32_t tcb_data[TCB_WORDS];
195};
196
197struct ch_tcam_word {
198 uint32_t cmd;
199 uint32_t addr;
200 uint32_t buf[3];
201};
202
203struct ch_trace {
204 uint32_t cmd;
205 uint32_t sip;
206 uint32_t sip_mask;
207 uint32_t dip;
208 uint32_t dip_mask;
209 uint16_t sport;
210 uint16_t sport_mask;
211 uint16_t dport;
212 uint16_t dport_mask;
213 uint32_t vlan:12,
214 vlan_mask:12,
215 intf:4,
216 intf_mask:4;
217 uint8_t proto;
218 uint8_t proto_mask;
219 uint8_t invert_match:1,
220 config_tx:1,
221 config_rx:1,
222 trace_tx:1,
223 trace_rx:1;
224};
225
226#define REGDUMP_SIZE (4 * 1024)
227
228struct ifconf_regs {
229 uint32_t version;
230 uint32_t len; /* bytes */
231 uint8_t *data;
232};
233
234struct mii_data {
235 uint32_t phy_id;
236 uint32_t reg_num;
237 uint32_t val_in;
238 uint32_t val_out;
239};
240
241#define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg)
242#define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg)
243#define CHELSIO_READ_TCAM_WORD _IOR('f', CH_READ_TCAM_WORD, struct ch_tcam)
244#define CHELSIO_GET_MEM _IOWR('f', CH_GET_MEM, struct ch_mem_range)
245#define CHELSIO_GET_SGE_CONTEXT _IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt)
246#define CHELSIO_GET_SGE_DESC _IOWR('f', CH_GET_SGE_DESC, struct ch_desc)
247#define CHELSIO_GET_QSET_PARAMS _IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params)
248#define CHELSIO_SET_QSET_PARAMS _IOW('f', CH_SET_QSET_PARAMS, struct ch_qset_params)
249#define CHELSIO_GET_QSET_NUM _IOWR('f', CH_GET_QSET_NUM, struct ch_reg)
250#define CHELSIO_SET_QSET_NUM _IOW('f', CH_SET_QSET_NUM, struct ch_reg)
251#define CHELSIO_GETMTUTAB _IOR('f', CH_GET_QSET_NUM, struct ch_mtus)
252#define CHELSIO_SETMTUTAB _IOW('f', CH_SET_QSET_NUM, struct ch_mtus)
253
254
255#define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace)
256#define CHELSIO_SET_PKTSCHED _IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params)
257#define CHELSIO_IFCONF_GETREGS _IOWR('f', CH_IFCONF_GETREGS, struct ifconf_regs)
258#define SIOCGMIIREG _IOWR('f', CH_GETMIIREGS, struct mii_data)
259#define SIOCSMIIREG _IOWR('f', CH_SETMIIREGS, struct mii_data)
260#define CHELSIO_SET_HW_SCHED _IOWR('f', CH_SET_HW_SCHED, struct ch_hw_sched)
261#define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter)
262#define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter)
263#define CHELSIO_DEVUP _IO('f', CH_DEVUP)
264
265#define CHELSIO_GET_TCB _IOWR('f', CH_GET_TCB, struct ch_tcb)
266#endif
| 29
30***************************************************************************/
31#ifndef __CHIOCTL_H__
32#define __CHIOCTL_H__
33
34/*
35 * Ioctl commands specific to this driver.
36 */
37enum {
38 CH_SETREG = 0x40,
39 CH_GETREG,
40 CH_SETTPI,
41 CH_GETTPI,
42 CH_DEVUP,
43 CH_GETMTUTAB,
44 CH_SETMTUTAB,
45 CH_GETMTU,
46 CH_SET_PM,
47 CH_GET_PM,
48 CH_GET_TCAM,
49 CH_SET_TCAM,
50 CH_GET_TCB,
51 CH_READ_TCAM_WORD,
52 CH_GET_MEM,
53 CH_GET_SGE_CONTEXT,
54 CH_GET_SGE_DESC,
55 CH_LOAD_FW,
56 CH_GET_PROTO,
57 CH_SET_PROTO,
58 CH_SET_TRACE_FILTER,
59 CH_SET_QSET_PARAMS,
60 CH_GET_QSET_PARAMS,
61 CH_SET_QSET_NUM,
62 CH_GET_QSET_NUM,
63 CH_SET_PKTSCHED,
64 CH_IFCONF_GETREGS,
65 CH_GETMIIREGS,
66 CH_SETMIIREGS,
67 CH_SET_FILTER,
68 CH_SET_HW_SCHED,
69 CH_DEL_FILTER,
70};
71
72struct ch_reg {
73 uint32_t addr;
74 uint32_t val;
75};
76
77struct ch_cntxt {
78 uint32_t cntxt_type;
79 uint32_t cntxt_id;
80 uint32_t data[4];
81};
82
83/* context types */
84enum { CNTXT_TYPE_EGRESS, CNTXT_TYPE_FL, CNTXT_TYPE_RSP, CNTXT_TYPE_CQ };
85
86struct ch_desc {
87 uint32_t cmd;
88 uint32_t queue_num;
89 uint32_t idx;
90 uint32_t size;
91 uint8_t data[128];
92};
93
94struct ch_mem_range {
95 uint32_t cmd;
96 uint32_t mem_id;
97 uint32_t addr;
98 uint32_t len;
99 uint32_t version;
100 uint8_t *buf;
101};
102
103struct ch_qset_params {
104 uint32_t qset_idx;
105 int32_t txq_size[3];
106 int32_t rspq_size;
107 int32_t fl_size[2];
108 int32_t intr_lat;
109 int32_t polling;
110 int32_t lro;
111 int32_t cong_thres;
112 int32_t vector;
113 int32_t qnum;
114};
115
116struct ch_pktsched_params {
117 uint32_t cmd;
118 uint8_t sched;
119 uint8_t idx;
120 uint8_t min;
121 uint8_t max;
122 uint8_t binding;
123};
124
125struct ch_hw_sched {
126 uint32_t cmd;
127 uint8_t sched;
128 int8_t mode;
129 int8_t channel;
130 int32_t kbps; /* rate in Kbps */
131 int32_t class_ipg; /* tenths of nanoseconds */
132 uint32_t flow_ipg; /* usec */
133};
134
135struct ch_filter_tuple {
136 uint32_t sip;
137 uint32_t dip;
138 uint16_t sport;
139 uint16_t dport;
140 uint16_t vlan:12;
141 uint16_t vlan_prio:3;
142};
143
144struct ch_filter {
145 uint32_t cmd;
146 uint32_t filter_id;
147 struct ch_filter_tuple val;
148 struct ch_filter_tuple mask;
149 uint16_t mac_addr_idx;
150 uint8_t mac_hit:1;
151 uint8_t proto:2;
152
153 uint8_t want_filter_id:1; /* report filter TID instead of RSS hash */
154 uint8_t pass:1; /* whether to pass or drop packets */
155 uint8_t rss:1; /* use RSS or specified qset */
156 uint8_t qset;
157};
158
159#ifndef TCB_SIZE
160# define TCB_SIZE 128
161#endif
162
163/* TCB size in 32-bit words */
164#define TCB_WORDS (TCB_SIZE / 4)
165
166enum { MEM_CM, MEM_PMRX, MEM_PMTX }; /* ch_mem_range.mem_id values */
167
168struct ch_mtus {
169 uint32_t cmd;
170 uint32_t nmtus;
171 uint16_t mtus[NMTUS];
172};
173
174struct ch_pm {
175 uint32_t cmd;
176 uint32_t tx_pg_sz;
177 uint32_t tx_num_pg;
178 uint32_t rx_pg_sz;
179 uint32_t rx_num_pg;
180 uint32_t pm_total;
181};
182
183struct ch_tcam {
184 uint32_t cmd;
185 uint32_t tcam_size;
186 uint32_t nservers;
187 uint32_t nroutes;
188 uint32_t nfilters;
189};
190
191struct ch_tcb {
192 uint32_t cmd;
193 uint32_t tcb_index;
194 uint32_t tcb_data[TCB_WORDS];
195};
196
197struct ch_tcam_word {
198 uint32_t cmd;
199 uint32_t addr;
200 uint32_t buf[3];
201};
202
203struct ch_trace {
204 uint32_t cmd;
205 uint32_t sip;
206 uint32_t sip_mask;
207 uint32_t dip;
208 uint32_t dip_mask;
209 uint16_t sport;
210 uint16_t sport_mask;
211 uint16_t dport;
212 uint16_t dport_mask;
213 uint32_t vlan:12,
214 vlan_mask:12,
215 intf:4,
216 intf_mask:4;
217 uint8_t proto;
218 uint8_t proto_mask;
219 uint8_t invert_match:1,
220 config_tx:1,
221 config_rx:1,
222 trace_tx:1,
223 trace_rx:1;
224};
225
226#define REGDUMP_SIZE (4 * 1024)
227
228struct ifconf_regs {
229 uint32_t version;
230 uint32_t len; /* bytes */
231 uint8_t *data;
232};
233
234struct mii_data {
235 uint32_t phy_id;
236 uint32_t reg_num;
237 uint32_t val_in;
238 uint32_t val_out;
239};
240
241#define CHELSIO_SETREG _IOW('f', CH_SETREG, struct ch_reg)
242#define CHELSIO_GETREG _IOWR('f', CH_GETREG, struct ch_reg)
243#define CHELSIO_READ_TCAM_WORD _IOR('f', CH_READ_TCAM_WORD, struct ch_tcam)
244#define CHELSIO_GET_MEM _IOWR('f', CH_GET_MEM, struct ch_mem_range)
245#define CHELSIO_GET_SGE_CONTEXT _IOWR('f', CH_GET_SGE_CONTEXT, struct ch_cntxt)
246#define CHELSIO_GET_SGE_DESC _IOWR('f', CH_GET_SGE_DESC, struct ch_desc)
247#define CHELSIO_GET_QSET_PARAMS _IOWR('f', CH_GET_QSET_PARAMS, struct ch_qset_params)
248#define CHELSIO_SET_QSET_PARAMS _IOW('f', CH_SET_QSET_PARAMS, struct ch_qset_params)
249#define CHELSIO_GET_QSET_NUM _IOWR('f', CH_GET_QSET_NUM, struct ch_reg)
250#define CHELSIO_SET_QSET_NUM _IOW('f', CH_SET_QSET_NUM, struct ch_reg)
251#define CHELSIO_GETMTUTAB _IOR('f', CH_GET_QSET_NUM, struct ch_mtus)
252#define CHELSIO_SETMTUTAB _IOW('f', CH_SET_QSET_NUM, struct ch_mtus)
253
254
255#define CHELSIO_SET_TRACE_FILTER _IOW('f', CH_SET_TRACE_FILTER, struct ch_trace)
256#define CHELSIO_SET_PKTSCHED _IOW('f', CH_SET_PKTSCHED, struct ch_pktsched_params)
257#define CHELSIO_IFCONF_GETREGS _IOWR('f', CH_IFCONF_GETREGS, struct ifconf_regs)
258#define SIOCGMIIREG _IOWR('f', CH_GETMIIREGS, struct mii_data)
259#define SIOCSMIIREG _IOWR('f', CH_SETMIIREGS, struct mii_data)
260#define CHELSIO_SET_HW_SCHED _IOWR('f', CH_SET_HW_SCHED, struct ch_hw_sched)
261#define CHELSIO_SET_FILTER _IOW('f', CH_SET_FILTER, struct ch_filter)
262#define CHELSIO_DEL_FILTER _IOW('f', CH_DEL_FILTER, struct ch_filter)
263#define CHELSIO_DEVUP _IO('f', CH_DEVUP)
264
265#define CHELSIO_GET_TCB _IOWR('f', CH_GET_TCB, struct ch_tcb)
266#endif
|