1/**************************************************************************
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Chelsio Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32$FreeBSD: head/sys/dev/cxgb/common/cxgb_tcb.h 167514 2007-03-14 02:37:44Z kmacy $
33
34***************************************************************************/
35
36/* This file is automatically generated --- do not edit */
37
38#ifndef _TCB_DEFS_H
39#define _TCB_DEFS_H
40
41#define W_TCB_T_STATE 0
42#define S_TCB_T_STATE 0
43#define M_TCB_T_STATE 0xfULL
44#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE)
45
46#define W_TCB_TIMER 0
47#define S_TCB_TIMER 4
48#define M_TCB_TIMER 0x1ULL
49#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER)
50
51#define W_TCB_DACK_TIMER 0
52#define S_TCB_DACK_TIMER 5
53#define M_TCB_DACK_TIMER 0x1ULL
54#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER)
55
56#define W_TCB_DEL_FLAG 0
57#define S_TCB_DEL_FLAG 6
58#define M_TCB_DEL_FLAG 0x1ULL
59#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG)
60
61#define W_TCB_L2T_IX 0
62#define S_TCB_L2T_IX 7
63#define M_TCB_L2T_IX 0x7ffULL
64#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX)
65
66#define W_TCB_SMAC_SEL 0
67#define S_TCB_SMAC_SEL 18
68#define M_TCB_SMAC_SEL 0x3ULL
69#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL)
70
71#define W_TCB_TOS 0
72#define S_TCB_TOS 20
73#define M_TCB_TOS 0x3fULL
74#define V_TCB_TOS(x) ((x) << S_TCB_TOS)
75
76#define W_TCB_MAX_RT 0
77#define S_TCB_MAX_RT 26
78#define M_TCB_MAX_RT 0xfULL
79#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT)
80
81#define W_TCB_T_RXTSHIFT 0
82#define S_TCB_T_RXTSHIFT 30
83#define M_TCB_T_RXTSHIFT 0xfULL
84#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT)
85
86#define W_TCB_T_DUPACKS 1
87#define S_TCB_T_DUPACKS 2
88#define M_TCB_T_DUPACKS 0xfULL
89#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS)
90
91#define W_TCB_T_MAXSEG 1
92#define S_TCB_T_MAXSEG 6
93#define M_TCB_T_MAXSEG 0xfULL
94#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG)
95
96#define W_TCB_T_FLAGS1 1
97#define S_TCB_T_FLAGS1 10
98#define M_TCB_T_FLAGS1 0xffffffffULL
99#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1)
100
101#define W_TCB_T_FLAGS2 2
102#define S_TCB_T_FLAGS2 10
103#define M_TCB_T_FLAGS2 0x7fULL
104#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2)
105
106#define W_TCB_SND_SCALE 2
107#define S_TCB_SND_SCALE 17
108#define M_TCB_SND_SCALE 0xfULL
109#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE)
110
111#define W_TCB_RCV_SCALE 2
112#define S_TCB_RCV_SCALE 21
113#define M_TCB_RCV_SCALE 0xfULL
114#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE)
115
116#define W_TCB_SND_UNA_RAW 2
117#define S_TCB_SND_UNA_RAW 25
118#define M_TCB_SND_UNA_RAW 0x7ffffffULL
119#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW)
120
121#define W_TCB_SND_NXT_RAW 3
122#define S_TCB_SND_NXT_RAW 20
123#define M_TCB_SND_NXT_RAW 0x7ffffffULL
124#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW)
125
126#define W_TCB_RCV_NXT 4
127#define S_TCB_RCV_NXT 15
128#define M_TCB_RCV_NXT 0xffffffffULL
129#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT)
130
131#define W_TCB_RCV_ADV 5
132#define S_TCB_RCV_ADV 15
133#define M_TCB_RCV_ADV 0xffffULL
134#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV)
135
136#define W_TCB_SND_MAX_RAW 5
137#define S_TCB_SND_MAX_RAW 31
138#define M_TCB_SND_MAX_RAW 0x7ffffffULL
139#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW)
140
141#define W_TCB_SND_CWND 6
142#define S_TCB_SND_CWND 26
143#define M_TCB_SND_CWND 0x7ffffffULL
144#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND)
145
146#define W_TCB_SND_SSTHRESH 7
147#define S_TCB_SND_SSTHRESH 21
148#define M_TCB_SND_SSTHRESH 0x7ffffffULL
149#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH)
150
151#define W_TCB_T_RTT_TS_RECENT_AGE 8
152#define S_TCB_T_RTT_TS_RECENT_AGE 16
153#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL
154#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE)
155
156#define W_TCB_T_RTSEQ_RECENT 9
157#define S_TCB_T_RTSEQ_RECENT 16
158#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL
159#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT)
160
161#define W_TCB_T_SRTT 10
162#define S_TCB_T_SRTT 16
163#define M_TCB_T_SRTT 0xffffULL
164#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT)
165
166#define W_TCB_T_RTTVAR 11
167#define S_TCB_T_RTTVAR 0
168#define M_TCB_T_RTTVAR 0xffffULL
169#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR)
170
171#define W_TCB_TS_LAST_ACK_SENT_RAW 11
172#define S_TCB_TS_LAST_ACK_SENT_RAW 16
173#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL
174#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW)
175
176#define W_TCB_DIP 12
177#define S_TCB_DIP 11
178#define M_TCB_DIP 0xffffffffULL
179#define V_TCB_DIP(x) ((x) << S_TCB_DIP)
180
181#define W_TCB_SIP 13
182#define S_TCB_SIP 11
183#define M_TCB_SIP 0xffffffffULL
184#define V_TCB_SIP(x) ((x) << S_TCB_SIP)
185
186#define W_TCB_DP 14
187#define S_TCB_DP 11
188#define M_TCB_DP 0xffffULL
189#define V_TCB_DP(x) ((x) << S_TCB_DP)
190
191#define W_TCB_SP 14
192#define S_TCB_SP 27
193#define M_TCB_SP 0xffffULL
194#define V_TCB_SP(x) ((x) << S_TCB_SP)
195
196#define W_TCB_TIMESTAMP 15
197#define S_TCB_TIMESTAMP 11
198#define M_TCB_TIMESTAMP 0xffffffffULL
199#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP)
200
201#define W_TCB_TIMESTAMP_OFFSET 16
202#define S_TCB_TIMESTAMP_OFFSET 11
203#define M_TCB_TIMESTAMP_OFFSET 0xfULL
204#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET)
205
206#define W_TCB_TX_MAX 16
207#define S_TCB_TX_MAX 15
208#define M_TCB_TX_MAX 0xffffffffULL
209#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX)
210
211#define W_TCB_TX_HDR_PTR_RAW 17
212#define S_TCB_TX_HDR_PTR_RAW 15
213#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL
214#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW)
215
216#define W_TCB_TX_LAST_PTR_RAW 18
217#define S_TCB_TX_LAST_PTR_RAW 0
218#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL
219#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW)
220
221#define W_TCB_TX_COMPACT 18
222#define S_TCB_TX_COMPACT 17
223#define M_TCB_TX_COMPACT 0x1ULL
224#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT)
225
226#define W_TCB_RX_COMPACT 18
227#define S_TCB_RX_COMPACT 18
228#define M_TCB_RX_COMPACT 0x1ULL
229#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT)
230
231#define W_TCB_RCV_WND 18
232#define S_TCB_RCV_WND 19
233#define M_TCB_RCV_WND 0x7ffffffULL
234#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND)
235
236#define W_TCB_RX_HDR_OFFSET 19
237#define S_TCB_RX_HDR_OFFSET 14
238#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL
239#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET)
240
241#define W_TCB_RX_FRAG0_START_IDX_RAW 20
242#define S_TCB_RX_FRAG0_START_IDX_RAW 9
243#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL
244#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW)
245
246#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21
247#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4
248#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL
249#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
250
251#define W_TCB_RX_FRAG0_LEN 21
252#define S_TCB_RX_FRAG0_LEN 31
253#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL
254#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN)
255
256#define W_TCB_RX_FRAG1_LEN 22
257#define S_TCB_RX_FRAG1_LEN 26
258#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL
259#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN)
260
261#define W_TCB_NEWRENO_RECOVER 23
262#define S_TCB_NEWRENO_RECOVER 21
263#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL
264#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER)
265
266#define W_TCB_PDU_HAVE_LEN 24
267#define S_TCB_PDU_HAVE_LEN 16
268#define M_TCB_PDU_HAVE_LEN 0x1ULL
269#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN)
270
271#define W_TCB_PDU_LEN 24
272#define S_TCB_PDU_LEN 17
273#define M_TCB_PDU_LEN 0xffffULL
274#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN)
275
276#define W_TCB_RX_QUIESCE 25
277#define S_TCB_RX_QUIESCE 1
278#define M_TCB_RX_QUIESCE 0x1ULL
279#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE)
280
281#define W_TCB_RX_PTR_RAW 25
282#define S_TCB_RX_PTR_RAW 2
283#define M_TCB_RX_PTR_RAW 0x1ffffULL
284#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW)
285
286#define W_TCB_CPU_NO 25
287#define S_TCB_CPU_NO 19
288#define M_TCB_CPU_NO 0x7fULL
289#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO)
290
291#define W_TCB_ULP_TYPE 25
292#define S_TCB_ULP_TYPE 26
293#define M_TCB_ULP_TYPE 0xfULL
294#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE)
295
296#define W_TCB_RX_FRAG1_PTR_RAW 25
297#define S_TCB_RX_FRAG1_PTR_RAW 30
298#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL
299#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW)
300
301#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26
302#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15
303#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL
304#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
305
306#define W_TCB_RX_FRAG2_PTR_RAW 27
307#define S_TCB_RX_FRAG2_PTR_RAW 10
308#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL
309#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW)
310
311#define W_TCB_RX_FRAG2_LEN_RAW 27
312#define S_TCB_RX_FRAG2_LEN_RAW 27
313#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL
314#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW)
315
316#define W_TCB_RX_FRAG3_PTR_RAW 28
317#define S_TCB_RX_FRAG3_PTR_RAW 22
318#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL
319#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW)
320
321#define W_TCB_RX_FRAG3_LEN_RAW 29
322#define S_TCB_RX_FRAG3_LEN_RAW 7
323#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL
324#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW)
325
326#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30
327#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2
328#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL
329#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
330
331#define W_TCB_PDU_HDR_LEN 30
332#define S_TCB_PDU_HDR_LEN 29
333#define M_TCB_PDU_HDR_LEN 0xffULL
334#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
335
336#define W_TCB_SLUSH1 31
337#define S_TCB_SLUSH1 5
338#define M_TCB_SLUSH1 0x7ffffULL
339#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1)
340
341#define W_TCB_ULP_RAW 31
342#define S_TCB_ULP_RAW 24
343#define M_TCB_ULP_RAW 0xffULL
344#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW)
345
346#define W_TCB_DDP_RDMAP_VERSION 25
347#define S_TCB_DDP_RDMAP_VERSION 30
348#define M_TCB_DDP_RDMAP_VERSION 0x1ULL
349#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION)
350
351#define W_TCB_MARKER_ENABLE_RX 25
352#define S_TCB_MARKER_ENABLE_RX 31
353#define M_TCB_MARKER_ENABLE_RX 0x1ULL
354#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX)
355
356#define W_TCB_MARKER_ENABLE_TX 26
357#define S_TCB_MARKER_ENABLE_TX 0
358#define M_TCB_MARKER_ENABLE_TX 0x1ULL
359#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX)
360
361#define W_TCB_CRC_ENABLE 26
362#define S_TCB_CRC_ENABLE 1
363#define M_TCB_CRC_ENABLE 0x1ULL
364#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE)
365
366#define W_TCB_IRS_ULP 26
367#define S_TCB_IRS_ULP 2
368#define M_TCB_IRS_ULP 0x1ffULL
369#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP)
370
371#define W_TCB_ISS_ULP 26
372#define S_TCB_ISS_ULP 11
373#define M_TCB_ISS_ULP 0x1ffULL
374#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP)
375
376#define W_TCB_TX_PDU_LEN 26
377#define S_TCB_TX_PDU_LEN 20
378#define M_TCB_TX_PDU_LEN 0x3fffULL
379#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN)
380
381#define W_TCB_TX_PDU_OUT 27
382#define S_TCB_TX_PDU_OUT 2
383#define M_TCB_TX_PDU_OUT 0x1ULL
384#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT)
385
386#define W_TCB_CQ_IDX_SQ 27
387#define S_TCB_CQ_IDX_SQ 3
388#define M_TCB_CQ_IDX_SQ 0xffffULL
389#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ)
390
391#define W_TCB_CQ_IDX_RQ 27
392#define S_TCB_CQ_IDX_RQ 19
393#define M_TCB_CQ_IDX_RQ 0xffffULL
394#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ)
395
396#define W_TCB_QP_ID 28
397#define S_TCB_QP_ID 3
398#define M_TCB_QP_ID 0xffffULL
399#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID)
400
401#define W_TCB_PD_ID 28
402#define S_TCB_PD_ID 19
403#define M_TCB_PD_ID 0xffffULL
404#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID)
405
406#define W_TCB_STAG 29
407#define S_TCB_STAG 3
408#define M_TCB_STAG 0xffffffffULL
409#define V_TCB_STAG(x) ((x) << S_TCB_STAG)
410
411#define W_TCB_RQ_START 30
412#define S_TCB_RQ_START 3
413#define M_TCB_RQ_START 0x3ffffffULL
414#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START)
415
416#define W_TCB_RQ_MSN 30
417#define S_TCB_RQ_MSN 29
418#define M_TCB_RQ_MSN 0x3ffULL
419#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN)
420
421#define W_TCB_RQ_MAX_OFFSET 31
422#define S_TCB_RQ_MAX_OFFSET 7
423#define M_TCB_RQ_MAX_OFFSET 0xfULL
424#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET)
425
426#define W_TCB_RQ_WRITE_PTR 31
427#define S_TCB_RQ_WRITE_PTR 11
428#define M_TCB_RQ_WRITE_PTR 0x3ffULL
429#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR)
430
431#define W_TCB_INB_WRITE_PERM 31
432#define S_TCB_INB_WRITE_PERM 21
433#define M_TCB_INB_WRITE_PERM 0x1ULL
434#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM)
435
436#define W_TCB_INB_READ_PERM 31
437#define S_TCB_INB_READ_PERM 22
438#define M_TCB_INB_READ_PERM 0x1ULL
439#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM)
440
441#define W_TCB_ORD_L_BIT_VLD 31
442#define S_TCB_ORD_L_BIT_VLD 23
443#define M_TCB_ORD_L_BIT_VLD 0x1ULL
444#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD)
445
446#define W_TCB_RDMAP_OPCODE 31
447#define S_TCB_RDMAP_OPCODE 24
448#define M_TCB_RDMAP_OPCODE 0xfULL
449#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE)
450
451#define W_TCB_TX_FLUSH 31
452#define S_TCB_TX_FLUSH 28
453#define M_TCB_TX_FLUSH 0x1ULL
454#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH)
455
456#define W_TCB_TX_OOS_RXMT 31
457#define S_TCB_TX_OOS_RXMT 29
458#define M_TCB_TX_OOS_RXMT 0x1ULL
459#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT)
460
461#define W_TCB_TX_OOS_TXMT 31
462#define S_TCB_TX_OOS_TXMT 30
463#define M_TCB_TX_OOS_TXMT 0x1ULL
464#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT)
465
466#define W_TCB_SLUSH_AUX2 31
467#define S_TCB_SLUSH_AUX2 31
468#define M_TCB_SLUSH_AUX2 0x1ULL
469#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2)
470
471#define W_TCB_RX_FRAG1_PTR_RAW2 25
472#define S_TCB_RX_FRAG1_PTR_RAW2 30
473#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL
474#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2)
475
476#define W_TCB_RX_DDP_FLAGS 26
477#define S_TCB_RX_DDP_FLAGS 15
478#define M_TCB_RX_DDP_FLAGS 0xffffULL
479#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS)
480
481#define W_TCB_SLUSH_AUX3 26
482#define S_TCB_SLUSH_AUX3 31
483#define M_TCB_SLUSH_AUX3 0x1ffULL
484#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3)
485
486#define W_TCB_RX_DDP_BUF0_OFFSET 27
487#define S_TCB_RX_DDP_BUF0_OFFSET 8
488#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL
489#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET)
490
491#define W_TCB_RX_DDP_BUF0_LEN 27
492#define S_TCB_RX_DDP_BUF0_LEN 30
493#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL
494#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN)
495
496#define W_TCB_RX_DDP_BUF1_OFFSET 28
497#define S_TCB_RX_DDP_BUF1_OFFSET 20
498#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL
499#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET)
500
501#define W_TCB_RX_DDP_BUF1_LEN 29
502#define S_TCB_RX_DDP_BUF1_LEN 10
503#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL
504#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN)
505
506#define W_TCB_RX_DDP_BUF0_TAG 30
507#define S_TCB_RX_DDP_BUF0_TAG 0
508#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL
509#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG)
510
511#define W_TCB_RX_DDP_BUF1_TAG 31
512#define S_TCB_RX_DDP_BUF1_TAG 0
513#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL
514#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
515
516#define S_TF_DACK 10
517#define V_TF_DACK(x) ((x) << S_TF_DACK)
518
519#define S_TF_NAGLE 11
520#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
521
522#define S_TF_RECV_SCALE 12
523#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE)
524
525#define S_TF_RECV_TSTMP 13
526#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP)
527
528#define S_TF_RECV_SACK 14
529#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK)
530
531#define S_TF_TURBO 15
532#define V_TF_TURBO(x) ((x) << S_TF_TURBO)
533
534#define S_TF_KEEPALIVE 16
535#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
536
537#define S_TF_TCAM_BYPASS 17
538#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS)
539
540#define S_TF_CORE_FIN 18
541#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN)
542
543#define S_TF_CORE_MORE 19
544#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE)
545
546#define S_TF_MIGRATING 20
547#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
548
549#define S_TF_ACTIVE_OPEN 21
550#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN)
551
552#define S_TF_ASK_MODE 22
553#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE)
554
555#define S_TF_NON_OFFLOAD 23
556#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
557
558#define S_TF_MOD_SCHD 24
559#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD)
560
561#define S_TF_MOD_SCHD_REASON0 25
562#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0)
563
564#define S_TF_MOD_SCHD_REASON1 26
565#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1)
566
567#define S_TF_MOD_SCHD_RX 27
568#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX)
569
570#define S_TF_CORE_PUSH 28
571#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH)
572
573#define S_TF_RCV_COALESCE_ENABLE 29
574#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE)
575
576#define S_TF_RCV_COALESCE_PUSH 30
577#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH)
578
579#define S_TF_RCV_COALESCE_LAST_PSH 31
580#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH)
581
582#define S_TF_RCV_COALESCE_HEARTBEAT 32
583#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT)
584
585#define S_TF_LOCK_TID 33
586#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID)
587
588#define S_TF_DACK_MSS 34
589#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
590
591#define S_TF_CCTRL_SEL0 35
592#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0)
593
594#define S_TF_CCTRL_SEL1 36
595#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1)
596
597#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37
598#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY)
599
600#define S_TF_TX_PACE_AUTO 38
601#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO)
602
603#define S_TF_PEER_FIN_HELD 39
604#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD)
605
606#define S_TF_CORE_URG 40
607#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG)
608
609#define S_TF_RDMA_ERROR 41
610#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR)
611
612#define S_TF_SSWS_DISABLED 42
613#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
614
615#define S_TF_DUPACK_COUNT_ODD 43
616#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD)
617
618#define S_TF_TX_CHANNEL 44
619#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL)
620
621#define S_TF_RX_CHANNEL 45
622#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
623
624#define S_TF_TX_PACE_FIXED 46
625#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED)
626
627#define S_TF_RDMA_FLM_ERROR 47
628#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR)
629
630#define S_TF_RX_FLOW_CONTROL_DISABLE 48
631#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
632
633#define S_TF_DDP_INDICATE_OUT 15
634#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT)
635
636#define S_TF_DDP_ACTIVE_BUF 16
637#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF)
638
639#define S_TF_DDP_BUF0_VALID 17
640#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID)
641
642#define S_TF_DDP_BUF1_VALID 18
643#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID)
644
645#define S_TF_DDP_BUF0_INDICATE 19
646#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE)
647
648#define S_TF_DDP_BUF1_INDICATE 20
649#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE)
650
651#define S_TF_DDP_PUSH_DISABLE_0 21
652#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0)
653
654#define S_TF_DDP_PUSH_DISABLE_1 22
655#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1)
656
657#define S_TF_DDP_OFF 23
658#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF)
659
660#define S_TF_DDP_WAIT_FRAG 24
661#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG)
662
663#define S_TF_DDP_BUF_INF 25
664#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF)
665
666#define S_TF_DDP_RX2TX 26
667#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX)
668
669#define S_TF_DDP_BUF0_FLUSH 27
670#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH)
671
672#define S_TF_DDP_BUF1_FLUSH 28
673#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH)
674
675#define S_TF_DDP_PSH_NO_INVALIDATE 29
676#define V_TF_DDP_PSH_NO_INVALIDATE(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE)
677
678#endif /* _TCB_DEFS_H */
2
3Copyright (c) 2007, Chelsio Inc.
4All rights reserved.
5
6Redistribution and use in source and binary forms, with or without
7modification, are permitted provided that the following conditions are met:
8
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
11
12 2. Redistributions in binary form must reproduce the above copyright
13 notice, this list of conditions and the following disclaimer in the
14 documentation and/or other materials provided with the distribution.
15
16 3. Neither the name of the Chelsio Corporation nor the names of its
17 contributors may be used to endorse or promote products derived from
18 this software without specific prior written permission.
19
20THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30POSSIBILITY OF SUCH DAMAGE.
31
32$FreeBSD: head/sys/dev/cxgb/common/cxgb_tcb.h 167514 2007-03-14 02:37:44Z kmacy $
33
34***************************************************************************/
35
36/* This file is automatically generated --- do not edit */
37
38#ifndef _TCB_DEFS_H
39#define _TCB_DEFS_H
40
41#define W_TCB_T_STATE 0
42#define S_TCB_T_STATE 0
43#define M_TCB_T_STATE 0xfULL
44#define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE)
45
46#define W_TCB_TIMER 0
47#define S_TCB_TIMER 4
48#define M_TCB_TIMER 0x1ULL
49#define V_TCB_TIMER(x) ((x) << S_TCB_TIMER)
50
51#define W_TCB_DACK_TIMER 0
52#define S_TCB_DACK_TIMER 5
53#define M_TCB_DACK_TIMER 0x1ULL
54#define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER)
55
56#define W_TCB_DEL_FLAG 0
57#define S_TCB_DEL_FLAG 6
58#define M_TCB_DEL_FLAG 0x1ULL
59#define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG)
60
61#define W_TCB_L2T_IX 0
62#define S_TCB_L2T_IX 7
63#define M_TCB_L2T_IX 0x7ffULL
64#define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX)
65
66#define W_TCB_SMAC_SEL 0
67#define S_TCB_SMAC_SEL 18
68#define M_TCB_SMAC_SEL 0x3ULL
69#define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL)
70
71#define W_TCB_TOS 0
72#define S_TCB_TOS 20
73#define M_TCB_TOS 0x3fULL
74#define V_TCB_TOS(x) ((x) << S_TCB_TOS)
75
76#define W_TCB_MAX_RT 0
77#define S_TCB_MAX_RT 26
78#define M_TCB_MAX_RT 0xfULL
79#define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT)
80
81#define W_TCB_T_RXTSHIFT 0
82#define S_TCB_T_RXTSHIFT 30
83#define M_TCB_T_RXTSHIFT 0xfULL
84#define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT)
85
86#define W_TCB_T_DUPACKS 1
87#define S_TCB_T_DUPACKS 2
88#define M_TCB_T_DUPACKS 0xfULL
89#define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS)
90
91#define W_TCB_T_MAXSEG 1
92#define S_TCB_T_MAXSEG 6
93#define M_TCB_T_MAXSEG 0xfULL
94#define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG)
95
96#define W_TCB_T_FLAGS1 1
97#define S_TCB_T_FLAGS1 10
98#define M_TCB_T_FLAGS1 0xffffffffULL
99#define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1)
100
101#define W_TCB_T_FLAGS2 2
102#define S_TCB_T_FLAGS2 10
103#define M_TCB_T_FLAGS2 0x7fULL
104#define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2)
105
106#define W_TCB_SND_SCALE 2
107#define S_TCB_SND_SCALE 17
108#define M_TCB_SND_SCALE 0xfULL
109#define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE)
110
111#define W_TCB_RCV_SCALE 2
112#define S_TCB_RCV_SCALE 21
113#define M_TCB_RCV_SCALE 0xfULL
114#define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE)
115
116#define W_TCB_SND_UNA_RAW 2
117#define S_TCB_SND_UNA_RAW 25
118#define M_TCB_SND_UNA_RAW 0x7ffffffULL
119#define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW)
120
121#define W_TCB_SND_NXT_RAW 3
122#define S_TCB_SND_NXT_RAW 20
123#define M_TCB_SND_NXT_RAW 0x7ffffffULL
124#define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW)
125
126#define W_TCB_RCV_NXT 4
127#define S_TCB_RCV_NXT 15
128#define M_TCB_RCV_NXT 0xffffffffULL
129#define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT)
130
131#define W_TCB_RCV_ADV 5
132#define S_TCB_RCV_ADV 15
133#define M_TCB_RCV_ADV 0xffffULL
134#define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV)
135
136#define W_TCB_SND_MAX_RAW 5
137#define S_TCB_SND_MAX_RAW 31
138#define M_TCB_SND_MAX_RAW 0x7ffffffULL
139#define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW)
140
141#define W_TCB_SND_CWND 6
142#define S_TCB_SND_CWND 26
143#define M_TCB_SND_CWND 0x7ffffffULL
144#define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND)
145
146#define W_TCB_SND_SSTHRESH 7
147#define S_TCB_SND_SSTHRESH 21
148#define M_TCB_SND_SSTHRESH 0x7ffffffULL
149#define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH)
150
151#define W_TCB_T_RTT_TS_RECENT_AGE 8
152#define S_TCB_T_RTT_TS_RECENT_AGE 16
153#define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL
154#define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE)
155
156#define W_TCB_T_RTSEQ_RECENT 9
157#define S_TCB_T_RTSEQ_RECENT 16
158#define M_TCB_T_RTSEQ_RECENT 0xffffffffULL
159#define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT)
160
161#define W_TCB_T_SRTT 10
162#define S_TCB_T_SRTT 16
163#define M_TCB_T_SRTT 0xffffULL
164#define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT)
165
166#define W_TCB_T_RTTVAR 11
167#define S_TCB_T_RTTVAR 0
168#define M_TCB_T_RTTVAR 0xffffULL
169#define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR)
170
171#define W_TCB_TS_LAST_ACK_SENT_RAW 11
172#define S_TCB_TS_LAST_ACK_SENT_RAW 16
173#define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL
174#define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW)
175
176#define W_TCB_DIP 12
177#define S_TCB_DIP 11
178#define M_TCB_DIP 0xffffffffULL
179#define V_TCB_DIP(x) ((x) << S_TCB_DIP)
180
181#define W_TCB_SIP 13
182#define S_TCB_SIP 11
183#define M_TCB_SIP 0xffffffffULL
184#define V_TCB_SIP(x) ((x) << S_TCB_SIP)
185
186#define W_TCB_DP 14
187#define S_TCB_DP 11
188#define M_TCB_DP 0xffffULL
189#define V_TCB_DP(x) ((x) << S_TCB_DP)
190
191#define W_TCB_SP 14
192#define S_TCB_SP 27
193#define M_TCB_SP 0xffffULL
194#define V_TCB_SP(x) ((x) << S_TCB_SP)
195
196#define W_TCB_TIMESTAMP 15
197#define S_TCB_TIMESTAMP 11
198#define M_TCB_TIMESTAMP 0xffffffffULL
199#define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP)
200
201#define W_TCB_TIMESTAMP_OFFSET 16
202#define S_TCB_TIMESTAMP_OFFSET 11
203#define M_TCB_TIMESTAMP_OFFSET 0xfULL
204#define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET)
205
206#define W_TCB_TX_MAX 16
207#define S_TCB_TX_MAX 15
208#define M_TCB_TX_MAX 0xffffffffULL
209#define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX)
210
211#define W_TCB_TX_HDR_PTR_RAW 17
212#define S_TCB_TX_HDR_PTR_RAW 15
213#define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL
214#define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW)
215
216#define W_TCB_TX_LAST_PTR_RAW 18
217#define S_TCB_TX_LAST_PTR_RAW 0
218#define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL
219#define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW)
220
221#define W_TCB_TX_COMPACT 18
222#define S_TCB_TX_COMPACT 17
223#define M_TCB_TX_COMPACT 0x1ULL
224#define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT)
225
226#define W_TCB_RX_COMPACT 18
227#define S_TCB_RX_COMPACT 18
228#define M_TCB_RX_COMPACT 0x1ULL
229#define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT)
230
231#define W_TCB_RCV_WND 18
232#define S_TCB_RCV_WND 19
233#define M_TCB_RCV_WND 0x7ffffffULL
234#define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND)
235
236#define W_TCB_RX_HDR_OFFSET 19
237#define S_TCB_RX_HDR_OFFSET 14
238#define M_TCB_RX_HDR_OFFSET 0x7ffffffULL
239#define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET)
240
241#define W_TCB_RX_FRAG0_START_IDX_RAW 20
242#define S_TCB_RX_FRAG0_START_IDX_RAW 9
243#define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL
244#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW)
245
246#define W_TCB_RX_FRAG1_START_IDX_OFFSET 21
247#define S_TCB_RX_FRAG1_START_IDX_OFFSET 4
248#define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL
249#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
250
251#define W_TCB_RX_FRAG0_LEN 21
252#define S_TCB_RX_FRAG0_LEN 31
253#define M_TCB_RX_FRAG0_LEN 0x7ffffffULL
254#define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN)
255
256#define W_TCB_RX_FRAG1_LEN 22
257#define S_TCB_RX_FRAG1_LEN 26
258#define M_TCB_RX_FRAG1_LEN 0x7ffffffULL
259#define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN)
260
261#define W_TCB_NEWRENO_RECOVER 23
262#define S_TCB_NEWRENO_RECOVER 21
263#define M_TCB_NEWRENO_RECOVER 0x7ffffffULL
264#define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER)
265
266#define W_TCB_PDU_HAVE_LEN 24
267#define S_TCB_PDU_HAVE_LEN 16
268#define M_TCB_PDU_HAVE_LEN 0x1ULL
269#define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN)
270
271#define W_TCB_PDU_LEN 24
272#define S_TCB_PDU_LEN 17
273#define M_TCB_PDU_LEN 0xffffULL
274#define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN)
275
276#define W_TCB_RX_QUIESCE 25
277#define S_TCB_RX_QUIESCE 1
278#define M_TCB_RX_QUIESCE 0x1ULL
279#define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE)
280
281#define W_TCB_RX_PTR_RAW 25
282#define S_TCB_RX_PTR_RAW 2
283#define M_TCB_RX_PTR_RAW 0x1ffffULL
284#define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW)
285
286#define W_TCB_CPU_NO 25
287#define S_TCB_CPU_NO 19
288#define M_TCB_CPU_NO 0x7fULL
289#define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO)
290
291#define W_TCB_ULP_TYPE 25
292#define S_TCB_ULP_TYPE 26
293#define M_TCB_ULP_TYPE 0xfULL
294#define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE)
295
296#define W_TCB_RX_FRAG1_PTR_RAW 25
297#define S_TCB_RX_FRAG1_PTR_RAW 30
298#define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL
299#define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW)
300
301#define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26
302#define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15
303#define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL
304#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
305
306#define W_TCB_RX_FRAG2_PTR_RAW 27
307#define S_TCB_RX_FRAG2_PTR_RAW 10
308#define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL
309#define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW)
310
311#define W_TCB_RX_FRAG2_LEN_RAW 27
312#define S_TCB_RX_FRAG2_LEN_RAW 27
313#define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL
314#define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW)
315
316#define W_TCB_RX_FRAG3_PTR_RAW 28
317#define S_TCB_RX_FRAG3_PTR_RAW 22
318#define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL
319#define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW)
320
321#define W_TCB_RX_FRAG3_LEN_RAW 29
322#define S_TCB_RX_FRAG3_LEN_RAW 7
323#define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL
324#define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW)
325
326#define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30
327#define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2
328#define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL
329#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
330
331#define W_TCB_PDU_HDR_LEN 30
332#define S_TCB_PDU_HDR_LEN 29
333#define M_TCB_PDU_HDR_LEN 0xffULL
334#define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN)
335
336#define W_TCB_SLUSH1 31
337#define S_TCB_SLUSH1 5
338#define M_TCB_SLUSH1 0x7ffffULL
339#define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1)
340
341#define W_TCB_ULP_RAW 31
342#define S_TCB_ULP_RAW 24
343#define M_TCB_ULP_RAW 0xffULL
344#define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW)
345
346#define W_TCB_DDP_RDMAP_VERSION 25
347#define S_TCB_DDP_RDMAP_VERSION 30
348#define M_TCB_DDP_RDMAP_VERSION 0x1ULL
349#define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION)
350
351#define W_TCB_MARKER_ENABLE_RX 25
352#define S_TCB_MARKER_ENABLE_RX 31
353#define M_TCB_MARKER_ENABLE_RX 0x1ULL
354#define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX)
355
356#define W_TCB_MARKER_ENABLE_TX 26
357#define S_TCB_MARKER_ENABLE_TX 0
358#define M_TCB_MARKER_ENABLE_TX 0x1ULL
359#define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX)
360
361#define W_TCB_CRC_ENABLE 26
362#define S_TCB_CRC_ENABLE 1
363#define M_TCB_CRC_ENABLE 0x1ULL
364#define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE)
365
366#define W_TCB_IRS_ULP 26
367#define S_TCB_IRS_ULP 2
368#define M_TCB_IRS_ULP 0x1ffULL
369#define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP)
370
371#define W_TCB_ISS_ULP 26
372#define S_TCB_ISS_ULP 11
373#define M_TCB_ISS_ULP 0x1ffULL
374#define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP)
375
376#define W_TCB_TX_PDU_LEN 26
377#define S_TCB_TX_PDU_LEN 20
378#define M_TCB_TX_PDU_LEN 0x3fffULL
379#define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN)
380
381#define W_TCB_TX_PDU_OUT 27
382#define S_TCB_TX_PDU_OUT 2
383#define M_TCB_TX_PDU_OUT 0x1ULL
384#define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT)
385
386#define W_TCB_CQ_IDX_SQ 27
387#define S_TCB_CQ_IDX_SQ 3
388#define M_TCB_CQ_IDX_SQ 0xffffULL
389#define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ)
390
391#define W_TCB_CQ_IDX_RQ 27
392#define S_TCB_CQ_IDX_RQ 19
393#define M_TCB_CQ_IDX_RQ 0xffffULL
394#define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ)
395
396#define W_TCB_QP_ID 28
397#define S_TCB_QP_ID 3
398#define M_TCB_QP_ID 0xffffULL
399#define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID)
400
401#define W_TCB_PD_ID 28
402#define S_TCB_PD_ID 19
403#define M_TCB_PD_ID 0xffffULL
404#define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID)
405
406#define W_TCB_STAG 29
407#define S_TCB_STAG 3
408#define M_TCB_STAG 0xffffffffULL
409#define V_TCB_STAG(x) ((x) << S_TCB_STAG)
410
411#define W_TCB_RQ_START 30
412#define S_TCB_RQ_START 3
413#define M_TCB_RQ_START 0x3ffffffULL
414#define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START)
415
416#define W_TCB_RQ_MSN 30
417#define S_TCB_RQ_MSN 29
418#define M_TCB_RQ_MSN 0x3ffULL
419#define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN)
420
421#define W_TCB_RQ_MAX_OFFSET 31
422#define S_TCB_RQ_MAX_OFFSET 7
423#define M_TCB_RQ_MAX_OFFSET 0xfULL
424#define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET)
425
426#define W_TCB_RQ_WRITE_PTR 31
427#define S_TCB_RQ_WRITE_PTR 11
428#define M_TCB_RQ_WRITE_PTR 0x3ffULL
429#define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR)
430
431#define W_TCB_INB_WRITE_PERM 31
432#define S_TCB_INB_WRITE_PERM 21
433#define M_TCB_INB_WRITE_PERM 0x1ULL
434#define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM)
435
436#define W_TCB_INB_READ_PERM 31
437#define S_TCB_INB_READ_PERM 22
438#define M_TCB_INB_READ_PERM 0x1ULL
439#define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM)
440
441#define W_TCB_ORD_L_BIT_VLD 31
442#define S_TCB_ORD_L_BIT_VLD 23
443#define M_TCB_ORD_L_BIT_VLD 0x1ULL
444#define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD)
445
446#define W_TCB_RDMAP_OPCODE 31
447#define S_TCB_RDMAP_OPCODE 24
448#define M_TCB_RDMAP_OPCODE 0xfULL
449#define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE)
450
451#define W_TCB_TX_FLUSH 31
452#define S_TCB_TX_FLUSH 28
453#define M_TCB_TX_FLUSH 0x1ULL
454#define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH)
455
456#define W_TCB_TX_OOS_RXMT 31
457#define S_TCB_TX_OOS_RXMT 29
458#define M_TCB_TX_OOS_RXMT 0x1ULL
459#define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT)
460
461#define W_TCB_TX_OOS_TXMT 31
462#define S_TCB_TX_OOS_TXMT 30
463#define M_TCB_TX_OOS_TXMT 0x1ULL
464#define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT)
465
466#define W_TCB_SLUSH_AUX2 31
467#define S_TCB_SLUSH_AUX2 31
468#define M_TCB_SLUSH_AUX2 0x1ULL
469#define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2)
470
471#define W_TCB_RX_FRAG1_PTR_RAW2 25
472#define S_TCB_RX_FRAG1_PTR_RAW2 30
473#define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL
474#define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2)
475
476#define W_TCB_RX_DDP_FLAGS 26
477#define S_TCB_RX_DDP_FLAGS 15
478#define M_TCB_RX_DDP_FLAGS 0xffffULL
479#define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS)
480
481#define W_TCB_SLUSH_AUX3 26
482#define S_TCB_SLUSH_AUX3 31
483#define M_TCB_SLUSH_AUX3 0x1ffULL
484#define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3)
485
486#define W_TCB_RX_DDP_BUF0_OFFSET 27
487#define S_TCB_RX_DDP_BUF0_OFFSET 8
488#define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL
489#define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET)
490
491#define W_TCB_RX_DDP_BUF0_LEN 27
492#define S_TCB_RX_DDP_BUF0_LEN 30
493#define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL
494#define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN)
495
496#define W_TCB_RX_DDP_BUF1_OFFSET 28
497#define S_TCB_RX_DDP_BUF1_OFFSET 20
498#define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL
499#define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET)
500
501#define W_TCB_RX_DDP_BUF1_LEN 29
502#define S_TCB_RX_DDP_BUF1_LEN 10
503#define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL
504#define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN)
505
506#define W_TCB_RX_DDP_BUF0_TAG 30
507#define S_TCB_RX_DDP_BUF0_TAG 0
508#define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL
509#define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG)
510
511#define W_TCB_RX_DDP_BUF1_TAG 31
512#define S_TCB_RX_DDP_BUF1_TAG 0
513#define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL
514#define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG)
515
516#define S_TF_DACK 10
517#define V_TF_DACK(x) ((x) << S_TF_DACK)
518
519#define S_TF_NAGLE 11
520#define V_TF_NAGLE(x) ((x) << S_TF_NAGLE)
521
522#define S_TF_RECV_SCALE 12
523#define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE)
524
525#define S_TF_RECV_TSTMP 13
526#define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP)
527
528#define S_TF_RECV_SACK 14
529#define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK)
530
531#define S_TF_TURBO 15
532#define V_TF_TURBO(x) ((x) << S_TF_TURBO)
533
534#define S_TF_KEEPALIVE 16
535#define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE)
536
537#define S_TF_TCAM_BYPASS 17
538#define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS)
539
540#define S_TF_CORE_FIN 18
541#define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN)
542
543#define S_TF_CORE_MORE 19
544#define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE)
545
546#define S_TF_MIGRATING 20
547#define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING)
548
549#define S_TF_ACTIVE_OPEN 21
550#define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN)
551
552#define S_TF_ASK_MODE 22
553#define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE)
554
555#define S_TF_NON_OFFLOAD 23
556#define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD)
557
558#define S_TF_MOD_SCHD 24
559#define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD)
560
561#define S_TF_MOD_SCHD_REASON0 25
562#define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0)
563
564#define S_TF_MOD_SCHD_REASON1 26
565#define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1)
566
567#define S_TF_MOD_SCHD_RX 27
568#define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX)
569
570#define S_TF_CORE_PUSH 28
571#define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH)
572
573#define S_TF_RCV_COALESCE_ENABLE 29
574#define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE)
575
576#define S_TF_RCV_COALESCE_PUSH 30
577#define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH)
578
579#define S_TF_RCV_COALESCE_LAST_PSH 31
580#define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH)
581
582#define S_TF_RCV_COALESCE_HEARTBEAT 32
583#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT)
584
585#define S_TF_LOCK_TID 33
586#define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID)
587
588#define S_TF_DACK_MSS 34
589#define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS)
590
591#define S_TF_CCTRL_SEL0 35
592#define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0)
593
594#define S_TF_CCTRL_SEL1 36
595#define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1)
596
597#define S_TF_TCP_NEWRENO_FAST_RECOVERY 37
598#define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY)
599
600#define S_TF_TX_PACE_AUTO 38
601#define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO)
602
603#define S_TF_PEER_FIN_HELD 39
604#define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD)
605
606#define S_TF_CORE_URG 40
607#define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG)
608
609#define S_TF_RDMA_ERROR 41
610#define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR)
611
612#define S_TF_SSWS_DISABLED 42
613#define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED)
614
615#define S_TF_DUPACK_COUNT_ODD 43
616#define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD)
617
618#define S_TF_TX_CHANNEL 44
619#define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL)
620
621#define S_TF_RX_CHANNEL 45
622#define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL)
623
624#define S_TF_TX_PACE_FIXED 46
625#define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED)
626
627#define S_TF_RDMA_FLM_ERROR 47
628#define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR)
629
630#define S_TF_RX_FLOW_CONTROL_DISABLE 48
631#define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE)
632
633#define S_TF_DDP_INDICATE_OUT 15
634#define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT)
635
636#define S_TF_DDP_ACTIVE_BUF 16
637#define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF)
638
639#define S_TF_DDP_BUF0_VALID 17
640#define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID)
641
642#define S_TF_DDP_BUF1_VALID 18
643#define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID)
644
645#define S_TF_DDP_BUF0_INDICATE 19
646#define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE)
647
648#define S_TF_DDP_BUF1_INDICATE 20
649#define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE)
650
651#define S_TF_DDP_PUSH_DISABLE_0 21
652#define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0)
653
654#define S_TF_DDP_PUSH_DISABLE_1 22
655#define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1)
656
657#define S_TF_DDP_OFF 23
658#define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF)
659
660#define S_TF_DDP_WAIT_FRAG 24
661#define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG)
662
663#define S_TF_DDP_BUF_INF 25
664#define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF)
665
666#define S_TF_DDP_RX2TX 26
667#define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX)
668
669#define S_TF_DDP_BUF0_FLUSH 27
670#define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH)
671
672#define S_TF_DDP_BUF1_FLUSH 28
673#define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH)
674
675#define S_TF_DDP_PSH_NO_INVALIDATE 29
676#define V_TF_DDP_PSH_NO_INVALIDATE(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE)
677
678#endif /* _TCB_DEFS_H */