1/*-
2 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
25 */
26
27#include <sys/cdefs.h>
28__FBSDID("$FreeBSD: head/sys/dev/bxe/ecore_hsi.h 298955 2016-05-03 03:41:25Z pfg $");
29
30#ifndef ECORE_HSI_H
31#define ECORE_HSI_H
32
33#define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e
34
35struct license_key {
36 uint32_t reserved[6];
37
38 uint32_t max_iscsi_conn;
39#define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF
40#define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0
41#define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000
42#define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16
43
44 uint32_t reserved_a;
45
46 uint32_t max_fcoe_conn;
47#define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF
48#define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0
49#define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000
50#define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16
51
52 uint32_t reserved_b[4];
53};
54
55typedef struct license_key license_key_t;
56
57
58/****************************************************************************
59 * Shared HW configuration *
60 ****************************************************************************/
61#define PIN_CFG_NA 0x00000000
62#define PIN_CFG_GPIO0_P0 0x00000001
63#define PIN_CFG_GPIO1_P0 0x00000002
64#define PIN_CFG_GPIO2_P0 0x00000003
65#define PIN_CFG_GPIO3_P0 0x00000004
66#define PIN_CFG_GPIO0_P1 0x00000005
67#define PIN_CFG_GPIO1_P1 0x00000006
68#define PIN_CFG_GPIO2_P1 0x00000007
69#define PIN_CFG_GPIO3_P1 0x00000008
70#define PIN_CFG_EPIO0 0x00000009
71#define PIN_CFG_EPIO1 0x0000000a
72#define PIN_CFG_EPIO2 0x0000000b
73#define PIN_CFG_EPIO3 0x0000000c
74#define PIN_CFG_EPIO4 0x0000000d
75#define PIN_CFG_EPIO5 0x0000000e
76#define PIN_CFG_EPIO6 0x0000000f
77#define PIN_CFG_EPIO7 0x00000010
78#define PIN_CFG_EPIO8 0x00000011
79#define PIN_CFG_EPIO9 0x00000012
80#define PIN_CFG_EPIO10 0x00000013
81#define PIN_CFG_EPIO11 0x00000014
82#define PIN_CFG_EPIO12 0x00000015
83#define PIN_CFG_EPIO13 0x00000016
84#define PIN_CFG_EPIO14 0x00000017
85#define PIN_CFG_EPIO15 0x00000018
86#define PIN_CFG_EPIO16 0x00000019
87#define PIN_CFG_EPIO17 0x0000001a
88#define PIN_CFG_EPIO18 0x0000001b
89#define PIN_CFG_EPIO19 0x0000001c
90#define PIN_CFG_EPIO20 0x0000001d
91#define PIN_CFG_EPIO21 0x0000001e
92#define PIN_CFG_EPIO22 0x0000001f
93#define PIN_CFG_EPIO23 0x00000020
94#define PIN_CFG_EPIO24 0x00000021
95#define PIN_CFG_EPIO25 0x00000022
96#define PIN_CFG_EPIO26 0x00000023
97#define PIN_CFG_EPIO27 0x00000024
98#define PIN_CFG_EPIO28 0x00000025
99#define PIN_CFG_EPIO29 0x00000026
100#define PIN_CFG_EPIO30 0x00000027
101#define PIN_CFG_EPIO31 0x00000028
102
103/* EPIO definition */
104#define EPIO_CFG_NA 0x00000000
105#define EPIO_CFG_EPIO0 0x00000001
106#define EPIO_CFG_EPIO1 0x00000002
107#define EPIO_CFG_EPIO2 0x00000003
108#define EPIO_CFG_EPIO3 0x00000004
109#define EPIO_CFG_EPIO4 0x00000005
110#define EPIO_CFG_EPIO5 0x00000006
111#define EPIO_CFG_EPIO6 0x00000007
112#define EPIO_CFG_EPIO7 0x00000008
113#define EPIO_CFG_EPIO8 0x00000009
114#define EPIO_CFG_EPIO9 0x0000000a
115#define EPIO_CFG_EPIO10 0x0000000b
116#define EPIO_CFG_EPIO11 0x0000000c
117#define EPIO_CFG_EPIO12 0x0000000d
118#define EPIO_CFG_EPIO13 0x0000000e
119#define EPIO_CFG_EPIO14 0x0000000f
120#define EPIO_CFG_EPIO15 0x00000010
121#define EPIO_CFG_EPIO16 0x00000011
122#define EPIO_CFG_EPIO17 0x00000012
123#define EPIO_CFG_EPIO18 0x00000013
124#define EPIO_CFG_EPIO19 0x00000014
125#define EPIO_CFG_EPIO20 0x00000015
126#define EPIO_CFG_EPIO21 0x00000016
127#define EPIO_CFG_EPIO22 0x00000017
128#define EPIO_CFG_EPIO23 0x00000018
129#define EPIO_CFG_EPIO24 0x00000019
130#define EPIO_CFG_EPIO25 0x0000001a
131#define EPIO_CFG_EPIO26 0x0000001b
132#define EPIO_CFG_EPIO27 0x0000001c
133#define EPIO_CFG_EPIO28 0x0000001d
134#define EPIO_CFG_EPIO29 0x0000001e
135#define EPIO_CFG_EPIO30 0x0000001f
136#define EPIO_CFG_EPIO31 0x00000020
137
138struct mac_addr {
139 uint32_t upper;
140 uint32_t lower;
141};
142
143
144struct shared_hw_cfg { /* NVRAM Offset */
145 /* Up to 16 bytes of NULL-terminated string */
146 uint8_t part_num[16]; /* 0x104 */
147
148 uint32_t config; /* 0x114 */
149 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001
150 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0
151 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000
152 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001
153
154 #define SHARED_HW_CFG_PORT_SWAP 0x00000004
155
156 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008
157
158 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000
159 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010
160
161 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700
162 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8
163 /* Whatever MFW found in NVM
164 (if multiple found, priority order is: NC-SI, UMP, IPMI) */
165 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000
166 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100
167 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200
168 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300
169 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI
170 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
171 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400
172 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI
173 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
174 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500
175 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP
176 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */
177 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600
178
179 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For
180 backwards compatibility, value of 0 is disabling this feature.
181 That means that though 0 is a valid value, it cannot be
182 configured. */
183 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000
184 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12
185
186 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000
187 #define SHARED_HW_CFG_LED_MODE_SHIFT 16
188 #define SHARED_HW_CFG_LED_MAC1 0x00000000
189 #define SHARED_HW_CFG_LED_PHY1 0x00010000
190 #define SHARED_HW_CFG_LED_PHY2 0x00020000
191 #define SHARED_HW_CFG_LED_PHY3 0x00030000
192 #define SHARED_HW_CFG_LED_MAC2 0x00040000
193 #define SHARED_HW_CFG_LED_PHY4 0x00050000
194 #define SHARED_HW_CFG_LED_PHY5 0x00060000
195 #define SHARED_HW_CFG_LED_PHY6 0x00070000
196 #define SHARED_HW_CFG_LED_MAC3 0x00080000
197 #define SHARED_HW_CFG_LED_PHY7 0x00090000
198 #define SHARED_HW_CFG_LED_PHY9 0x000a0000
199 #define SHARED_HW_CFG_LED_PHY11 0x000b0000
200 #define SHARED_HW_CFG_LED_MAC4 0x000c0000
201 #define SHARED_HW_CFG_LED_PHY8 0x000d0000
202 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000
203 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000
204
205 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000
206 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000
207 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000
208
209 #define SHARED_HW_CFG_ATC_MASK 0x80000000
210 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000
211 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000
212
213 uint32_t config2; /* 0x118 */
214
215 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100
216 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8
217 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000
218 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100
219
220 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000
221 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000
222 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000
223
224 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000
225
226
227 /* Output low when PERST is asserted */
228 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000
229 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000
230 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000
231
232 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000
233 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16
234 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000
235 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000
236 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000
237 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000
238
239 /* The fan failure mechanism is usually related to the PHY type
240 since the power consumption of the board is determined by the PHY.
241 Currently, fan is required for most designs with SFX7101, BCM8727
242 and BCM8481. If a fan is not required for a board which uses one
243 of those PHYs, this field should be set to "Disabled". If a fan is
244 required for a different PHY type, this option should be set to
245 "Enabled". The fan failure indication is expected on SPIO5 */
246 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000
247 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19
248 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000
249 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000
250 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000
251
252 /* ASPM Power Management support */
253 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000
254 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21
255 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000
256 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000
257 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000
258 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000
259
260 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register
261 tl_control_0 (register 0x2800) */
262 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000
263 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000
264 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000
265
266
267 /* Set the MDC/MDIO access for the first external phy */
268 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000
269 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26
270 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000
271 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000
272 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000
273 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000
274 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000
275
276 /* Set the MDC/MDIO access for the second external phy */
277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000
278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29
279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000
280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000
281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000
282 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000
283 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000
284
285 /* Max number of PF MSIX vectors */
286 uint32_t config_3; /* 0x11C */
287 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F
288 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0
289
290 /* This field extends the mf mode chosen in nvm cfg #73 (as we ran
291 out of bits) */
292 #define SHARED_HW_CFG_EXTENDED_MF_MODE_MASK 0x00000F00
293 #define SHARED_HW_CFG_EXTENDED_MF_MODE_SHIFT 8
294 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR1_DOT_5 0x00000000
295 #define SHARED_HW_CFG_EXTENDED_MF_MODE_NPAR2_DOT_0 0x00000100
296
297 uint32_t ump_nc_si_config; /* 0x120 */
298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003
299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0
300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000
301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001
302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000
303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002
304
305 /* Reserved bits: 226-230 */
306
307 /* The output pin template BSC_SEL which selects the I2C for this
308 port in the I2C Mux */
309 uint32_t board; /* 0x124 */
310 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F
311 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0
312
313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0
314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6
315 /* Use the PIN_CFG_XXX defines on top */
316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000
317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16
318
319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000
320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24
321
322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000
323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28
324
325 uint32_t wc_lane_config; /* 0x128 */
326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0
328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b
329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4
330 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8
331 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827
332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b
333 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4
334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
335 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
337 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
338
339 /* TX lane Polarity swap */
340 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000
341 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000
342 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000
343 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000
344 /* TX lane Polarity swap */
345 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000
346 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000
347 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000
348 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000
349
350 /* Selects the port layout of the board */
351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000
352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24
353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000
354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000
355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000
356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000
357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000
358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000
359 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01_SIG 0x06000000
360};
361
362
363/****************************************************************************
364 * Port HW configuration *
365 ****************************************************************************/
366struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */
367
368 uint32_t pci_id;
369 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF
370 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0
371
372 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000
373 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16
374
375 uint32_t pci_sub_id;
376 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF
377 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0
378
379 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000
380 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16
381
382 uint32_t power_dissipated;
383 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF
384 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0
385 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00
386 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8
387 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000
388 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16
389 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000
390 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24
391
392 uint32_t power_consumed;
393 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF
394 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0
395 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00
396 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8
397 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000
398 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16
399 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000
400 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24
401
402 uint32_t mac_upper;
403 uint32_t mac_lower; /* 0x140 */
404 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF
405 #define PORT_HW_CFG_UPPERMAC_SHIFT 0
406
407
408 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */
409 uint32_t iscsi_mac_lower;
410
411 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */
412 uint32_t rdma_mac_lower;
413
414 uint32_t serdes_config;
415 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF
416 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0
417
418 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000
419 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16
420
421
422 /* Default values: 2P-64, 4P-32 */
423 uint32_t reserved;
424
425 uint32_t vf_config; /* 0x15C */
426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000
427 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16
428
429 uint32_t mf_pci_id; /* 0x160 */
430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF
431 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0
432
433 /* Controls the TX laser of the SFP+ module */
434 uint32_t sfp_ctrl; /* 0x164 */
435 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF
436 #define PORT_HW_CFG_TX_LASER_SHIFT 0
437 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000
438 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001
439 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002
440 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003
441 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004
442
443 /* Controls the fault module LED of the SFP+ */
444 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00
445 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8
446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000
447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100
448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200
449 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300
450 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400
451
452 /* The output pin TX_DIS that controls the TX laser of the SFP+
453 module. Use the PIN_CFG_XXX defines on top */
454 uint32_t e3_sfp_ctrl; /* 0x168 */
455 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF
456 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0
457
458 /* The output pin for SFPP_TYPE which turns on the Fault module LED */
459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00
460 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8
461
462 /* The input pin MOD_ABS that indicates whether SFP+ module is
463 present or not. Use the PIN_CFG_XXX defines on top */
464 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000
465 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16
466
467 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+
468 module. Use the PIN_CFG_XXX defines on top */
469 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000
470 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24
471
472 /*
473 * The input pin which signals module transmit fault. Use the
474 * PIN_CFG_XXX defines on top
475 */
476 uint32_t e3_cmn_pin_cfg; /* 0x16C */
477 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF
478 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0
479
480 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on
481 top */
482 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00
483 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8
484
485 /*
486 * The output pin which powers down the PHY. Use the PIN_CFG_XXX
487 * defines on top
488 */
489 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000
490 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16
491
492 /* The output pin values BSC_SEL which selects the I2C for this port
493 in the I2C Mux */
494 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000
495 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000
496
497
498 /*
499 * The input pin I_FAULT which indicate over-current has occurred.
500 * Use the PIN_CFG_XXX defines on top
501 */
502 uint32_t e3_cmn_pin_cfg1; /* 0x170 */
503 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF
504 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0
505
506 /* pause on host ring */
507 uint32_t generic_features; /* 0x174 */
508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001
509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0
510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000
511 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001
512
513 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2
514 * LOM recommended and tested value is 0xBEB2. Using a different
515 * value means using a value not tested by BRCM
516 */
517 uint32_t sfi_tap_values; /* 0x178 */
518 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF
519 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0
520
521 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested
522 * value is 0x2. LOM recommended and tested value is 0x2. Using a
523 * different value means using a value not tested by BRCM
524 */
525 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000
526 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16
527 /* Set non-default values for TXFIR in SFP mode. */
528 #define PORT_HW_CFG_TX_DRV_IFIR_MASK 0x00F00000
529 #define PORT_HW_CFG_TX_DRV_IFIR_SHIFT 20
530
531 /* Set non-default values for IPREDRIVER in SFP mode. */
532 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK 0x0F000000
533 #define PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT 24
534
535 /* Set non-default values for POST2 in SFP mode. */
536 #define PORT_HW_CFG_TX_DRV_POST2_MASK 0xF0000000
537 #define PORT_HW_CFG_TX_DRV_POST2_SHIFT 28
538
539 uint32_t reserved0[5]; /* 0x17c */
540
541 uint32_t aeu_int_mask; /* 0x190 */
542
543 uint32_t media_type; /* 0x194 */
544 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF
545 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0
546
547 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00
548 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8
549
550 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000
551 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16
552
553 /* 4 times 16 bits for all 4 lanes. In case external PHY is present
554 (not direct mode), those values will not take effect on the 4 XGXS
555 lanes. For some external PHYs (such as 8706 and 8726) the values
556 will be used to configure the external PHY in those cases, not
557 all 4 values are needed. */
558 uint16_t xgxs_config_rx[4]; /* 0x198 */
559 uint16_t xgxs_config_tx[4]; /* 0x1A0 */
560
561
562 /* For storing FCOE mac on shared memory */
563 uint32_t fcoe_fip_mac_upper;
564 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff
565 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0
566 uint32_t fcoe_fip_mac_lower;
567
568 uint32_t fcoe_wwn_port_name_upper;
569 uint32_t fcoe_wwn_port_name_lower;
570
571 uint32_t fcoe_wwn_node_name_upper;
572 uint32_t fcoe_wwn_node_name_lower;
573
574 /* wwpn for npiv enabled */
575 uint32_t wwpn_for_npiv_config; /* 0x1C0 */
576 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001
577 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0
578 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000
579 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001
580
581 /* wwpn for npiv valid addresses */
582 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */
583 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF
584 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0
585
586 struct mac_addr wwpn_for_niv_macs[16];
587
588 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */
589 uint32_t Reserved1[14];
590
591 uint32_t pf_allocation; /* 0x280 */
592 /* number of vfs per PF, if 0 - sriov disabled */
593 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF
594 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0
595
596 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default),
597 84833 only */
598 uint32_t xgbt_phy_cfg; /* 0x284 */
599 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF
600 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0
601
602 uint32_t default_cfg; /* 0x288 */
603 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003
604 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0
605 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000
606 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001
607 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002
608 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003
609
610 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C
611 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2
612 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000
613 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004
614 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008
615 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c
616
617 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030
618 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4
619 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000
620 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010
621 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020
622 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030
623
624 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0
625 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6
626 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000
627 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040
628 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080
629 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0
630
631 /* When KR link is required to be set to force which is not
632 KR-compliant, this parameter determine what is the trigger for it.
633 When GPIO is selected, low input will force the speed. Currently
634 default speed is 1G. In the future, it may be widen to select the
635 forced speed in with another parameter. Note when force-1G is
636 enabled, it override option 56: Link Speed option. */
637 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00
638 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8
639 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000
640 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100
641 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200
642 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300
643 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400
644 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500
645 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600
646 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700
647 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800
648 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900
649 /* Enable to determine with which GPIO to reset the external phy */
650 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000
651 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16
652 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000
653 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000
654 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000
655 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000
656 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000
657 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000
658 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000
659 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000
660 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000
661
662 /* Enable BAM on KR */
663 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000
664 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20
665 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000
666 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000
667
668 /* Enable Common Mode Sense */
669 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000
670 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21
671 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000
672 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000
673
674 /* Determine the Serdes electrical interface */
675 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000
676 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24
677 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000
678 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000
679 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000
680 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000
681 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000
682 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000
683
684 /* SFP+ main TAP and post TAP volumes */
685 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000
686 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28
687 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000
688 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000
689 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000
690 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000
691 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000
692 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000
693
694 uint32_t speed_capability_mask2; /* 0x28C */
695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF
696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0
697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001
698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002
699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004
700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008
701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010
702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020
703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040
704 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080
705
706 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000
707 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16
708 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000
709 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000
710 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000
711 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000
712 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000
713 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000
714 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000
715 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000
716
717
718 /* In the case where two media types (e.g. copper and fiber) are
719 present and electrically active at the same time, PHY Selection
720 will determine which of the two PHYs will be designated as the
721 Active PHY and used for a connection to the network. */
722 uint32_t multi_phy_config; /* 0x290 */
723 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007
724 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0
725 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000
726 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001
727 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002
728 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003
729 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004
730
731 /* When enabled, all second phy nvram parameters will be swapped
732 with the first phy parameters */
733 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008
734 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3
735 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000
736 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008
737
738
739 /* Address of the second external phy */
740 uint32_t external_phy_config2; /* 0x294 */
741 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF
742 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0
743
744 /* The second XGXS external PHY type */
745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00
746 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8
747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000
748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100
749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200
750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300
751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400
752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500
753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600
754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700
755 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800
756 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900
757 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00
758 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00
759 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00
760 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00
761 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00
762 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00
763 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000
764 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100
765 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84858 0x00001200
766 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00
767 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00
768
769
770 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as
771 8706, 8726 and 8727) not all 4 values are needed. */
772 uint16_t xgxs_config2_rx[4]; /* 0x296 */
773 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */
774
775 uint32_t lane_config;
776 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF
777 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0
778 /* AN and forced */
779 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b
780 /* forced only */
781 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4
782 /* forced only */
783 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8
784 /* forced only */
785 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4
786 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF
787 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0
788 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00
789 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8
790 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000
791 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14
792
793 /* Indicate whether to swap the external phy polarity */
794 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000
795 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000
796 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000
797
798
799 uint32_t external_phy_config;
800 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF
801 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0
802
803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00
804 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8
805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000
806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100
807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200
808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300
809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400
810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500
811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600
812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700
813 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800
814 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900
815 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00
816 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00
817 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00
818 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00
819 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00
820 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00
821 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000
822 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100
823 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858 0x00001200
824 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00
825 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00
826 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00
827
828 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000
829 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16
830
831 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000
832 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24
833 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000
834 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000
835 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000
836 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000
837
838 uint32_t speed_capability_mask;
839 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF
840 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0
841 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001
842 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002
843 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004
844 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008
845 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010
846 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020
847 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040
848 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080
849 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000
850
851 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000
852 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16
853 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000
854 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000
855 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000
856 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000
857 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000
858 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000
859 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000
860 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000
861 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000
862
863 /* A place to hold the original MAC address as a backup */
864 uint32_t backup_mac_upper; /* 0x2B4 */
865 uint32_t backup_mac_lower; /* 0x2B8 */
866
867};
868
869
870/****************************************************************************
871 * Shared Feature configuration *
872 ****************************************************************************/
873struct shared_feat_cfg { /* NVRAM Offset */
874
875 uint32_t config; /* 0x450 */
876 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001
877
878 /* Use NVRAM values instead of HW default values */
879 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \
880 0x00000002
881 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \
882 0x00000000
883 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \
884 0x00000002
885
886 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008
887 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000
888 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008
889
890 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030
891 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4
892
893 /* Override the OTP back to single function mode. When using GPIO,
894 high means only SF, 0 is according to CLP configuration */
895 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700
896 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8
897 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000
898 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100
899 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200
900 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300
901 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400
902 #define SHARED_FEAT_CFG_FORCE_SF_MODE_BD_MODE 0x00000500
903 #define SHARED_FEAT_CFG_FORCE_SF_MODE_UFP_MODE 0x00000600
904 #define SHARED_FEAT_CFG_FORCE_SF_MODE_EXTENDED_MODE 0x00000700
905
906 /* Act as if the FCoE license is invalid */
907 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000
908
909 /* Force FLR capability to all ports */
910 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000
911
912 /* Act as if the iSCSI license is invalid */
913 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000
914 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14
915 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000
916 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000
917
918 /* The interval in seconds between sending LLDP packets. Set to zero
919 to disable the feature */
920 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000
921 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16
922
923 /* The assigned device type ID for LLDP usage */
924 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000
925 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24
926
927};
928
929
930/****************************************************************************
931 * Port Feature configuration *
932 ****************************************************************************/
933struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */
934
935 uint32_t config;
936 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F
937 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0
938 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000
939 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001
940 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002
941 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003
942 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004
943 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005
944 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006
945 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007
946 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008
947 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009
948 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a
949 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b
950 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c
951 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d
952 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e
953 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f
954 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0
955 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4
956 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000
957 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010
958 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020
959 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030
960 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040
961 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050
962 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060
963 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070
964 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080
965 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090
966 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0
967 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0
968 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0
969 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0
970 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0
971 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0
972
973 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100
974 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000
975 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100
976
977 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200
978 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9
979 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000
980 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200
981
982 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00
983 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10
984 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000
985 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400
986 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800
987 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00
988
989 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000
990 #define PORT_FEATURE_EN_SIZE_SHIFT 24
991 #define PORT_FEATURE_WOL_ENABLED 0x01000000
992 #define PORT_FEATURE_MBA_ENABLED 0x02000000
993 #define PORT_FEATURE_MFW_ENABLED 0x04000000
994
995 /* Advertise expansion ROM even if MBA is disabled */
996 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000
997 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000
998 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000
999
1000 /* Check the optic vendor via i2c against a list of approved modules
1001 in a separate nvram image */
1002 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000
1003 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29
1004 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \
1005 0x00000000
1006 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \
1007 0x20000000
1008 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000
1009 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000
1010
1011 uint32_t wol_config;
1012 /* Default is used when driver sets to "auto" mode */
1013 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010
1014
1015 uint32_t mba_config;
1016 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007
1017 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0
1018 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000
1019 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001
1020 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002
1021 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003
1022 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004
1023 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007
1024
1025 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038
1026 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3
1027
1028 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400
1029 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800
1030 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000
1031 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800
1032
1033 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000
1034 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12
1035 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000
1036 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000
1037 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000
1038 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000
1039 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000
1040 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000
1041 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000
1042 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000
1043 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000
1044 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000
1045 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000
1046 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000
1047 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000
1048 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000
1049 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000
1050 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000
1051 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000
1052 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20
1053 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000
1054 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24
1055 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000
1056 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000
1057 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000
1058 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000
1059 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000
1060 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26
1061 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000
1062 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000
1063 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000
1064 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000
1065 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000
1066 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000
1067 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000
1068 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000
1069 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000
1070
1071 uint32_t Reserved0; /* 0x460 */
1072
1073 uint32_t mba_vlan_cfg;
1074 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF
1075 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0
1076 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000
1077 #define PORT_FEATUTE_BOFM_CFGD_EN 0x00020000
1078 #define PORT_FEATURE_BOFM_CFGD_FTGT 0x00040000
1079 #define PORT_FEATURE_BOFM_CFGD_VEN 0x00080000
1080
1081 uint32_t Reserved1;
1082 uint32_t smbus_config;
1083 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe
1084 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1
1085
1086 uint32_t vf_config;
1087 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F
1088 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0
1089 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000
1090 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001
1091 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002
1092 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003
1093 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004
1094 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005
1095 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006
1096 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007
1097 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008
1098 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009
1099 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a
1100 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b
1101 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c
1102 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d
1103 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e
1104 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f
1105
1106 uint32_t link_config; /* Used as HW defaults for the driver */
1107
1108 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700
1109 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8
1110 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000
1111 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100
1112 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200
1113 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300
1114 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400
1115 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500
1116 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600
1117 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700
1118
1119 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000
1120 #define PORT_FEATURE_LINK_SPEED_SHIFT 16
1121 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000
1122 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00010000
1123 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00020000
1124 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000
1125 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000
1126 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000
1127 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000
1128 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000
1129 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000
1130
1131 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000
1132 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24
1133 /* (forced) low speed switch (< 10G) */
1134 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000
1135 /* (forced) high speed switch (>= 10G) */
1136 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000
1137 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000
1138 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000
1139
1140
1141 /* The default for MCP link configuration,
1142 uses the same defines as link_config */
1143 uint32_t mfw_wol_link_cfg;
1144
1145 /* The default for the driver of the second external phy,
1146 uses the same defines as link_config */
1147 uint32_t link_config2; /* 0x47C */
1148
1149 /* The default for MCP of the second external phy,
1150 uses the same defines as link_config */
1151 uint32_t mfw_wol_link_cfg2; /* 0x480 */
1152
1153
1154 /* EEE power saving mode */
1155 uint32_t eee_power_mode; /* 0x484 */
1156 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF
1157 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0
1158 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000
1159 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001
1160 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002
1161 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003
1162
1163
1164 uint32_t Reserved2[16]; /* 0x48C */
1165};
1166
1167/****************************************************************************
1168 * Device Information *
1169 ****************************************************************************/
1170struct shm_dev_info { /* size */
1171
1172 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */
1173
1174 struct shared_hw_cfg shared_hw_config; /* 40 */
1175
1176 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */
1177
1178 struct shared_feat_cfg shared_feature_config; /* 4 */
1179
1180 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */
1181
1182};
1183
1184struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */
1185
1186 /* Threshold in celcius to start using the fan */
1187 uint32_t temperature_monitor1; /* 0x4000 */
1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F
1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0
1190
1191 /* Threshold in celcius to shut down the board */
1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00
1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8
1194
1195 /* EPIO of fan temperature status */
1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000
1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16
1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000
1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000
1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000
1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000
1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000
1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000
1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000
1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000
1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000
1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000
1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000
1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000
1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000
1211 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000
1212 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000
1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000
1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000
1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000
1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000
1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000
1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000
1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000
1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000
1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000
1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000
1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000
1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000
1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000
1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000
1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000
1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000
1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000
1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000
1231
1232 /* EPIO of shut down temperature status */
1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000
1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24
1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000
1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000
1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000
1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000
1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000
1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000
1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000
1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000
1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000
1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000
1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000
1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000
1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000
1248 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000
1249 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000
1250 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000
1251 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000
1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000
1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000
1254 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000
1255 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000
1256 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000
1257 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000
1258 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000
1259 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000
1260 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000
1261 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000
1262 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000
1263 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000
1264 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000
1265 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000
1266 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000
1267 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000
1268
1269
1270 /* EPIO of shut down temperature status */
1271 uint32_t temperature_monitor2; /* 0x4004 */
1272 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF
1273 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0
1274
1275 /* Sensor interface - Disabled / BSC / In the future - SMBUS */
1276 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_MASK 0x00030000
1277 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_SHIFT 16
1278 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_DISABLED 0x00000000
1279 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_INTERFACE_BSC 0x00010000
1280
1281 /* On Board Sensor Address */
1282 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_MASK 0x03FC0000
1283 #define EXTENDED_DEV_INFO_SHARED_CFG_SENSOR_ADDR_SHIFT 18
1284
1285 /* MFW flavor to be used */
1286 uint32_t mfw_cfg; /* 0x4008 */
1287 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF
1288 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0
1289 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000
1290 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001
1291
1292 /* Should NIC data query remain enabled upon last drv unload */
1293 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100
1294 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8
1295 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000
1296 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100
1297
1298 /* Prevent OCBB feature */
1299 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_MASK 0x00000200
1300 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_SHIFT 9
1301 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_DISABLED 0x00000000
1302 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_PREVENT_ENABLED 0x00000200
1303
1304 /* Enable DCi support */
1305 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_MASK 0x00000400
1306 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_SHIFT 10
1307 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_DISABLED 0x00000000
1308 #define EXTENDED_DEV_INFO_SHARED_CFG_DCI_SUPPORT_ENABLED 0x00000400
1309
1310 /* Reserved bits: 75-76 */
1311
1312 /* Hide DCBX feature in CCM/BACS menus */
1313 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000
1314 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16
1315 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000
1316 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000
1317
1318 uint32_t smbus_config; /* 0x400C */
1319 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF
1320 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0
1321
1322 /* Switching regulator loop gain */
1323 uint32_t board_cfg; /* 0x4010 */
1324 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F
1325 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0
1326 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000
1327 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008
1328 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009
1329 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a
1330 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b
1331 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c
1332 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d
1333 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e
1334 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f
1335
1336 /* whether shadow swim feature is supported */
1337 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100
1338 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8
1339 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000
1340 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100
1341
1342 /* whether to show/hide SRIOV menu in CCM */
1343 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200
1344 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9
1345 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000
1346 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200
1347
1348 /* Overide PCIE revision ID when enabled the,
1349 revision ID will set to B1=='0x11' */
1350 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_MASK 0x00000400
1351 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_SHIFT 10
1352 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_DISABLED 0x00000000
1353 #define EXTENDED_DEV_INFO_SHARED_CFG_OVR_REV_ID_ENABLED 0x00000400
1354
1355 /* Bypass slicer offset tuning */
1356 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_MASK 0x00000800
1357 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_SHIFT 11
1358 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_DISABLED 0x00000000
1359 #define EXTENDED_DEV_INFO_SHARED_CFG_BYPASS_SLICER_ENABLED 0x00000800
1360 /* Control Revision ID */
1361 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_MASK 0x00003000
1362 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_SHIFT 12
1363 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_PRESERVE 0x00000000
1364 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_ACTUAL 0x00001000
1365 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B0 0x00002000
1366 #define EXTENDED_DEV_INFO_SHARED_CFG_REV_ID_CTRL_FORCE_B1 0x00003000
1367 /* Threshold in celcius for max continuous operation */
1368 uint32_t temperature_report; /* 0x4014 */
1369 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F
1370 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0
1371
1372 /* Threshold in celcius for sensor caution */
1373 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00
1374 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8
1375
1376 /* wwn node prefix to be used (unless value is 0) */
1377 uint32_t wwn_prefix; /* 0x4018 */
1378 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF
1379 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0
1380
1381 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00
1382 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8
1383
1384 /* wwn port prefix to be used (unless value is 0) */
1385 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000
1386 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16
1387
1388 /* wwn port prefix to be used (unless value is 0) */
1389 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000
1390 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24
1391
1392 /* General debug nvm cfg */
1393 uint32_t dbg_cfg_flags; /* 0x401C */
1394 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF
1395 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0
1396 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001
1397 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002
1398 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004
1399 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008
1400 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010
1401 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020
1402 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040
1403 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080
1404 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100
1405 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200
1406 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400
1407 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800
1408 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000
1409 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000
1410 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000
1411 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000
1412 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000
1413 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000
1414 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000
1415 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000
1416
1417 /* Override Rx signal detect threshold when enabled the threshold
1418 * will be set staticaly
1419 */
1420 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_MASK 0x00100000
1421 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_SHIFT 20
1422 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_DISABLED 0x00000000
1423 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_RX_SIG_ENABLED 0x00100000
1424
1425 /* Debug signet rx threshold */
1426 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */
1427 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007
1428 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0
1429
1430 /* Enable IFFE feature */
1431 uint32_t iffe_features; /* 0x4024 */
1432 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001
1433 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0
1434 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000
1435 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001
1436
1437 /* Allowable port enablement (bitmask for ports 3-1) */
1438 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E
1439 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1
1440
1441 /* Allow iSCSI offload override */
1442 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010
1443 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4
1444 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000
1445 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010
1446
1447 /* Allow FCoE offload override */
1448 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020
1449 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5
1450 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000
1451 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020
1452
1453 /* Tie to adaptor */
1454 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000
1455 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15
1456 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000
1457 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000
1458
1459 /* Currently enabled port(s) (bitmask for ports 3-1) */
1460 uint32_t current_iffe_mask; /* 0x4028 */
1461 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E
1462 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1
1463
1464 /* Current iSCSI offload */
1465 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010
1466 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4
1467 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000
1468 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010
1469
1470 /* Current FCoE offload */
1471 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020
1472 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5
1473 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000
1474 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020
1475
1476 /* FW set this pin to "0" (assert) these signal if either of its MAC
1477 * or PHY specific threshold values is exceeded.
1478 * Values are standard GPIO/EPIO pins.
1479 */
1480 uint32_t threshold_pin; /* 0x402C */
1481 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF
1482 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0
1483 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00
1484 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8
1485 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000
1486 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16
1487
1488 /* MAC die temperature threshold in Celsius. */
1489 uint32_t mac_threshold_val; /* 0x4030 */
1490 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF
1491 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0
1492 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00
1493 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8
1494 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000
1495 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16
1496
1497 /* PHY die temperature threshold in Celsius. */
1498 uint32_t phy_threshold_val; /* 0x4034 */
1499 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF
1500 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0
1501 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00
1502 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8
1503 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000
1504 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16
1505
1506 /* External pins to communicate with host.
1507 * Values are standard GPIO/EPIO pins.
1508 */
1509 uint32_t host_pin; /* 0x4038 */
1510 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF
1511 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0
1512 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00
1513 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8
1514 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000
1515 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16
1516 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000
1517 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24
1518
1519 /* Manufacture kit version */
1520 uint32_t manufacture_ver; /* 0x403C */
1521
1522 /* Manufacture timestamp */
1523 uint32_t manufacture_data; /* 0x4040 */
1524
1525 /* Number of ISCSI/FCOE cfg images */
1526 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_MASK 0x00040000
1527 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_SHIFT18
1528 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_2 0x00000000
1529 #define EXTENDED_DEV_INFO_SHARED_CFG_NUM_ISCSI_FCOE_CFGS_4 0x00040000
1530
1531 /* MCP crash dump trigger */
1532 uint32_t mcp_crash_dump; /* 0x4044 */
1533 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_MASK 0x7FFFFFFF
1534 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_SHIFT 0
1535 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_DISABLED 0x00000000
1536 #define EXTENDED_DEV_INFO_SHARED_CFG_CRASH_DUMP_ENABLED 0x00000001
1537
1538 /* MBI version */
1539 uint32_t mbi_version; /* 0x4048 */
1540
1541 /* MBI date */
1542 uint32_t mbi_date; /* 0x404C */
1543};
1544
1545
1546#if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
1547 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition."
1548#endif
1549
1550#define FUNC_0 0
1551#define FUNC_1 1
1552#define FUNC_2 2
1553#define FUNC_3 3
1554#define FUNC_4 4
1555#define FUNC_5 5
1556#define FUNC_6 6
1557#define FUNC_7 7
1558#define E1_FUNC_MAX 2
1559#define E1H_FUNC_MAX 8
1560#define E2_FUNC_MAX 4 /* per path */
1561
1562#define VN_0 0
1563#define VN_1 1
1564#define VN_2 2
1565#define VN_3 3
1566#define E1VN_MAX 1
1567#define E1HVN_MAX 4
1568
1569#define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */
1570/* This value (in milliseconds) determines the frequency of the driver
1571 * issuing the PULSE message code. The firmware monitors this periodic
1572 * pulse to determine when to switch to an OS-absent mode. */
1573#define DRV_PULSE_PERIOD_MS 250
1574
1575/* This value (in milliseconds) determines how long the driver should
1576 * wait for an acknowledgement from the firmware before timing out. Once
1577 * the firmware has timed out, the driver will assume there is no firmware
1578 * running and there won't be any firmware-driver synchronization during a
1579 * driver reset. */
1580#define FW_ACK_TIME_OUT_MS 5000
1581
1582#define FW_ACK_POLL_TIME_MS 1
1583
1584#define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS)
1585
1586#define MFW_TRACE_SIGNATURE 0x54524342
1587
1588/****************************************************************************
1589 * Driver <-> FW Mailbox *
1590 ****************************************************************************/
1591struct drv_port_mb {
1592
1593 uint32_t link_status;
1594 /* Driver should update this field on any link change event */
1595
1596 #define LINK_STATUS_NONE (0<<0)
1597 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001
1598 #define LINK_STATUS_LINK_UP 0x00000001
1599 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E
1600 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1)
1601 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1)
1602 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1)
1603 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1)
1604 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1)
1605 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1)
1606 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1)
1607 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1)
1608 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1)
1609 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1)
1610 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1)
1611 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1)
1612 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1)
1613 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1)
1614 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1)
1615 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1)
1616
1617 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020
1618 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020
1619
1620 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040
1621 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080
1622 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080
1623
1624 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200
1625 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400
1626 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800
1627 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000
1628 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000
1629 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000
1630 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000
1631
1632 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000
1633 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000
1634
1635 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000
1636 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000
1637
1638 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000
1639 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18)
1640 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18)
1641 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18)
1642 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18)
1643
1644 #define LINK_STATUS_SERDES_LINK 0x00100000
1645
1646 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000
1647 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000
1648 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000
1649 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000
1650
1651 #define LINK_STATUS_PFC_ENABLED 0x20000000
1652
1653 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000
1654 #define LINK_STATUS_SFP_TX_FAULT 0x80000000
1655
1656 uint32_t port_stx;
1657
1658 uint32_t stat_nig_timer;
1659
1660 /* MCP firmware does not use this field */
1661 uint32_t ext_phy_fw_version;
1662
1663};
1664
1665
1666struct drv_func_mb {
1667
1668 uint32_t drv_mb_header;
1669 #define DRV_MSG_CODE_MASK 0xffff0000
1670 #define DRV_MSG_CODE_LOAD_REQ 0x10000000
1671 #define DRV_MSG_CODE_LOAD_DONE 0x11000000
1672 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000
1673 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000
1674 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000
1675 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000
1676 #define DRV_MSG_CODE_DCC_OK 0x30000000
1677 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000
1678 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000
1679 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000
1680 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000
1681 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000
1682 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000
1683 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000
1684 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000
1685 #define DRV_MSG_CODE_OEM_OK 0x00010000
1686 #define DRV_MSG_CODE_OEM_FAILURE 0x00020000
1687 #define DRV_MSG_CODE_OEM_UPDATE_SVID_OK 0x00030000
1688 #define DRV_MSG_CODE_OEM_UPDATE_SVID_FAILURE 0x00040000
1689
1690 /*
1691 * The optic module verification command requires bootcode
1692 * v5.0.6 or later, te specific optic module verification command
1693 * requires bootcode v5.2.12 or later
1694 */
1695 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000
1696 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006
1697 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000
1698 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234
1699 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000
1700 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002
1701 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014
1702 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201
1703 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201
1704 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209
1705
1706 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000
1707 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000
1708 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401
1709
1710 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000
1711
1712 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000
1713 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000
1714 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000
1715 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000
1716 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000
1717
1718 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000
1719 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000
1720
1721 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000
1722
1723 #define DRV_MSG_CODE_RMMOD 0xdb000000
1724 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f
1725
1726 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000
1727 #define REQ_BC_VER_4_SET_MF_BW 0x00060202
1728 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000
1729
1730 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000
1731
1732 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000
1733 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213
1734
1735 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000
1736 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000
1737 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1738 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1739
1740 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000
1741 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000
1742
1743 #define DRV_MSG_CODE_UFP_CONFIG_ACK 0xe4000000
1744
1745 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff
1746
1747 #define DRV_MSG_CODE_CONFIG_CHANGE 0xC1000000
1748
1749 uint32_t drv_mb_param;
1750 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000
1751 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000
1752
1753 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001
1754 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002
1755
1756 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a
1757 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000
1758
1759 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001
1760 #define DRV_MSG_CODE_ISCSI_PERS_IMAGE_REQ 0x00000002
1761 #define DRV_MSG_CODE_VPD_IMAGE_REQ 0x00000003
1762
1763 #define DRV_MSG_CODE_CONFIG_CHANGE_MTU_SIZE 0x00000001
1764 #define DRV_MSG_CODE_CONFIG_CHANGE_MAC_ADD 0x00000002
1765 #define DRV_MSG_CODE_CONFIG_CHANGE_WOL_ENA 0x00000003
1766 #define DRV_MSG_CODE_CONFIG_CHANGE_ISCI_BOOT 0x00000004
1767 #define DRV_MSG_CODE_CONFIG_CHANGE_FCOE_BOOT 0x00000005
1768
1769 uint32_t fw_mb_header;
1770 #define FW_MSG_CODE_MASK 0xffff0000
1771 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000
1772 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000
1773 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000
1774 /* Load common chip is supported from bc 6.0.0 */
1775 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000
1776 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000
1777
1778 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000
1779 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000
1780 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000
1781 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000
1782 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000
1783 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000
1784 #define FW_MSG_CODE_DCC_DONE 0x30100000
1785 #define FW_MSG_CODE_LLDP_DONE 0x40100000
1786 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000
1787 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000
1788 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000
1789 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000
1790 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000
1791 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000
1792 #define FW_MSG_CODE_NO_KEY 0x80f00000
1793 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000
1794 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000
1795 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000
1796 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000
1797 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000
1798 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000
1799 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000
1800 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000
1801 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000
1802 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000
1803 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000
1804
1805 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000
1806 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000
1807 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000
1808 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000
1809 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000
1810
1811 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000
1812 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000
1813
1814 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000
1815
1816 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000
1817
1818 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000
1819 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000
1820
1821 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000
1822
1823 #define FW_MSG_CODE_FLR_ACK 0x02000000
1824 #define FW_MSG_CODE_FLR_NACK 0x02100000
1825
1826 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000
1827 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000
1828 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000
1829 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000
1830
1831 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000
1832 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000
1833
1834 #define FW_MSG_CODE_OEM_ACK 0x00010000
1835 #define DRV_MSG_CODE_OEM_UPDATE_SVID_ACK 0x00020000
1836
1837 #define FW_MSG_CODE_CONFIG_CHANGE_DONE 0xC2000000
1838
1839 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff
1840
1841 uint32_t fw_mb_param;
1842
1843 #define FW_PARAM_INVALID_IMG 0xffffffff
1844
1845 uint32_t drv_pulse_mb;
1846 #define DRV_PULSE_SEQ_MASK 0x00007fff
1847 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000
1848 /*
1849 * The system time is in the format of
1850 * (year-2001)*12*32 + month*32 + day.
1851 */
1852 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000
1853 /*
1854 * Indicate to the firmware not to go into the
1855 * OS-absent when it is not getting driver pulse.
1856 * This is used for debugging as well for PXE(MBA).
1857 */
1858
1859 uint32_t mcp_pulse_mb;
1860 #define MCP_PULSE_SEQ_MASK 0x00007fff
1861 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000
1862 /* Indicates to the driver not to assert due to lack
1863 * of MCP response */
1864 #define MCP_EVENT_MASK 0xffff0000
1865 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000
1866
1867 uint32_t iscsi_boot_signature;
1868 uint32_t iscsi_boot_block_offset;
1869
1870 uint32_t drv_status;
1871 #define DRV_STATUS_PMF 0x00000001
1872 #define DRV_STATUS_VF_DISABLED 0x00000002
1873 #define DRV_STATUS_SET_MF_BW 0x00000004
1874 #define DRV_STATUS_LINK_EVENT 0x00000008
1875
1876 #define DRV_STATUS_OEM_EVENT_MASK 0x00000070
1877 #define DRV_STATUS_OEM_DISABLE_ENABLE_PF 0x00000010
1878 #define DRV_STATUS_OEM_BANDWIDTH_ALLOCATION 0x00000020
1879 #define DRV_STATUS_OEM_FC_NPIV_UPDATE 0x00000040
1880
1881 #define DRV_STATUS_OEM_UPDATE_SVID 0x00000080
1882
1883 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00
1884 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100
1885 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200
1886 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400
1887 #define DRV_STATUS_DCC_RESERVED1 0x00000800
1888 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000
1889 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000
1890
1891 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000
1892 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000
1893 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000
1894 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000
1895 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000
1896 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000
1897 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000
1898
1899 #define DRV_STATUS_DRV_INFO_REQ 0x04000000
1900
1901 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000
1902
1903 uint32_t virt_mac_upper;
1904 #define VIRT_MAC_SIGN_MASK 0xffff0000
1905 #define VIRT_MAC_SIGNATURE 0x564d0000
1906 uint32_t virt_mac_lower;
1907
1908};
1909
1910
1911/****************************************************************************
1912 * Management firmware state *
1913 ****************************************************************************/
1914/* Allocate 440 bytes for management firmware */
1915#define MGMTFW_STATE_WORD_SIZE 110
1916
1917struct mgmtfw_state {
1918 uint32_t opaque[MGMTFW_STATE_WORD_SIZE];
1919};
1920
1921
1922/****************************************************************************
1923 * Multi-Function configuration *
1924 ****************************************************************************/
1925struct shared_mf_cfg {
1926
1927 uint32_t clp_mb;
1928 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000
1929 /* set by CLP */
1930 #define SHARED_MF_CLP_EXIT 0x00000001
1931 /* set by MCP */
1932 #define SHARED_MF_CLP_EXIT_DONE 0x00010000
1933
1934};
1935
1936struct port_mf_cfg {
1937
1938 uint32_t dynamic_cfg; /* device control channel */
1939 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1940 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0
1941 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK
1942
1943 uint32_t reserved[1];
1944
1945};
1946
1947struct func_mf_cfg {
1948
1949 uint32_t config;
1950 /* E/R/I/D */
1951 /* function 0 of each port cannot be hidden */
1952 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001
1953
1954 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006
1955 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000
1956 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002
1957 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004
1958 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006
1959 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \
1960 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA
1961
1962 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008
1963 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010
1964
1965 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060
1966 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000
1967 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020
1968 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040
1969
1970 /* PRI */
1971 /* 0 - low priority, 3 - high priority */
1972 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300
1973 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8
1974 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000
1975
1976 /* MINBW, MAXBW */
1977 /* value range - 0..100, increments in 100Mbps */
1978 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000
1979 #define FUNC_MF_CFG_MIN_BW_SHIFT 16
1980 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000
1981 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000
1982 #define FUNC_MF_CFG_MAX_BW_SHIFT 24
1983 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000
1984
1985 uint32_t mac_upper; /* MAC */
1986 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff
1987 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0
1988 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK
1989 uint32_t mac_lower;
1990 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff
1991
1992 uint32_t e1hov_tag; /* VNI */
1993 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff
1994 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0
1995 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK
1996
1997 /* afex default VLAN ID - 12 bits */
1998 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000
1999 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16
2000
2001 uint32_t afex_config;
2002 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff
2003 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0
2004 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00
2005 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8
2006 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100
2007 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000
2008 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16
2009
2010 uint32_t pf_allocation;
2011 /* number of vfs in function, if 0 - sriov disabled */
2012 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF
2013 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0
2014};
2015
2016enum mf_cfg_afex_vlan_mode {
2017 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0,
2018 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE,
2019 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE
2020};
2021
2022/* This structure is not applicable and should not be accessed on 57711 */
2023struct func_ext_cfg {
2024 uint32_t func_cfg;
2025 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F
2026 #define MACP_FUNC_CFG_FLAGS_SHIFT 0
2027 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001
2028 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002
2029 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004
2030 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008
2031 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080
2032
2033 uint32_t iscsi_mac_addr_upper;
2034 uint32_t iscsi_mac_addr_lower;
2035
2036 uint32_t fcoe_mac_addr_upper;
2037 uint32_t fcoe_mac_addr_lower;
2038
2039 uint32_t fcoe_wwn_port_name_upper;
2040 uint32_t fcoe_wwn_port_name_lower;
2041
2042 uint32_t fcoe_wwn_node_name_upper;
2043 uint32_t fcoe_wwn_node_name_lower;
2044
2045 uint32_t preserve_data;
2046 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0)
2047 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1)
2048 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2)
2049 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3)
2050 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4)
2051 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5)
2052};
2053
2054struct mf_cfg {
2055
2056 struct shared_mf_cfg shared_mf_config; /* 0x4 */
2057 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX];
2058 /* 0x10*2=0x20 */
2059 /* for all chips, there are 8 mf functions */
2060 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */
2061 /*
2062 * Extended configuration per function - this array does not exist and
2063 * should not be accessed on 57711
2064 */
2065 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/
2066}; /* 0x224 */
2067
2068/****************************************************************************
2069 * Shared Memory Region *
2070 ****************************************************************************/
2071struct shmem_region { /* SharedMem Offset (size) */
2072
2073 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */
2074 #define SHR_MEM_FORMAT_REV_MASK 0xff000000
2075 #define SHR_MEM_FORMAT_REV_ID ('A'<<24)
2076 /* validity bits */
2077 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000
2078 #define SHR_MEM_VALIDITY_MB 0x00200000
2079 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000
2080 #define SHR_MEM_VALIDITY_RESERVED 0x00000007
2081 /* One licensing bit should be set */
2082 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038
2083 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008
2084 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010
2085 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020
2086 /* Active MFW */
2087 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000
2088 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0
2089 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040
2090 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080
2091 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0
2092 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0
2093
2094 struct shm_dev_info dev_info; /* 0x8 (0x438) */
2095
2096 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */
2097
2098 /* FW information (for internal FW use) */
2099 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */
2100 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */
2101
2102 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */
2103
2104
2105#ifdef BMAPI
2106 /* This is a variable length array */
2107 /* the number of function depends on the chip type */
2108 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
2109#else
2110 /* the number of function depends on the chip type */
2111 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */
2112#endif /* BMAPI */
2113
2114}; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */
2115
2116/****************************************************************************
2117 * Shared Memory 2 Region *
2118 ****************************************************************************/
2119/* The fw_flr_ack is actually built in the following way: */
2120/* 8 bit: PF ack */
2121/* 64 bit: VF ack */
2122/* 8 bit: ios_dis_ack */
2123/* In order to maintain endianity in the mailbox hsi, we want to keep using */
2124/* uint32_t. The fw must have the VF right after the PF since this is how it */
2125/* access arrays(it expects always the VF to reside after the PF, and that */
2126/* makes the calculation much easier for it. ) */
2127/* In order to answer both limitations, and keep the struct small, the code */
2128/* will abuse the structure defined here to achieve the actual partition */
2129/* above */
2130/****************************************************************************/
2131struct fw_flr_ack {
2132 uint32_t pf_ack;
2133 uint32_t vf_ack;
2134 uint32_t iov_dis_ack;
2135};
2136
2137struct fw_flr_mb {
2138 uint32_t aggint;
2139 uint32_t opgen_addr;
2140 struct fw_flr_ack ack;
2141};
2142
2143struct eee_remote_vals {
2144 uint32_t tx_tw;
2145 uint32_t rx_tw;
2146};
2147
2148/**** SUPPORT FOR SHMEM ARRRAYS ***
2149 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to
2150 * define arrays with storage types smaller then unsigned dwords.
2151 * The macros below add generic support for SHMEM arrays with numeric elements
2152 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword
2153 * array with individual bit-filed elements accessed using shifts and masks.
2154 *
2155 */
2156
2157/* eb is the bitwidth of a single element */
2158#define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1)
2159#define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb)))
2160
2161/* the bit-position macro allows the used to flip the order of the arrays
2162 * elements on a per byte or word boundary.
2163 *
2164 * example: an array with 8 entries each 4 bit wide. This array will fit into
2165 * a single dword. The diagrmas below show the array order of the nibbles.
2166 *
2167 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering:
2168 *
2169 * | | | |
2170 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 |
2171 * | | | |
2172 *
2173 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte:
2174 *
2175 * | | | |
2176 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 |
2177 * | | | |
2178 *
2179 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word:
2180 *
2181 * | | | |
2182 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 |
2183 * | | | |
2184 */
2185#define SHMEM_ARRAY_BITPOS(i, eb, fb) \
2186 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \
2187 (((i)%((fb)/(eb))) * (eb)))
2188
2189#define SHMEM_ARRAY_GET(a, i, eb, fb) \
2190 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \
2191 SHMEM_ARRAY_MASK(eb))
2192
2193#define SHMEM_ARRAY_SET(a, i, eb, fb, val) \
2194do { \
2195 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \
2196 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2197 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \
2198 SHMEM_ARRAY_BITPOS(i, eb, fb)); \
2199} while (0)
2200
2201
2202/****START OF DCBX STRUCTURES DECLARATIONS****/
2203#define DCBX_MAX_NUM_PRI_PG_ENTRIES 8
2204#define DCBX_PRI_PG_BITWIDTH 4
2205#define DCBX_PRI_PG_FBITS 8
2206#define DCBX_PRI_PG_GET(a, i) \
2207 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS)
2208#define DCBX_PRI_PG_SET(a, i, val) \
2209 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val)
2210#define DCBX_MAX_NUM_PG_BW_ENTRIES 8
2211#define DCBX_BW_PG_BITWIDTH 8
2212#define DCBX_PG_BW_GET(a, i) \
2213 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH)
2214#define DCBX_PG_BW_SET(a, i, val) \
2215 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val)
2216#define DCBX_STRICT_PRI_PG 15
2217#define DCBX_MAX_APP_PROTOCOL 16
2218#define DCBX_MAX_APP_LOCAL 32
2219#define FCOE_APP_IDX 0
2220#define ISCSI_APP_IDX 1
2221#define PREDEFINED_APP_IDX_MAX 2
2222
2223
2224/* Big/Little endian have the same representation. */
2225struct dcbx_ets_feature {
2226 /*
2227 * For Admin MIB - is this feature supported by the
2228 * driver | For Local MIB - should this feature be enabled.
2229 */
2230 uint32_t enabled;
2231 uint32_t pg_bw_tbl[2];
2232 uint32_t pri_pg_tbl[1];
2233};
2234
2235/* Driver structure in LE */
2236struct dcbx_pfc_feature {
2237#ifdef __BIG_ENDIAN
2238 uint8_t pri_en_bitmap;
2239 #define DCBX_PFC_PRI_0 0x01
2240 #define DCBX_PFC_PRI_1 0x02
2241 #define DCBX_PFC_PRI_2 0x04
2242 #define DCBX_PFC_PRI_3 0x08
2243 #define DCBX_PFC_PRI_4 0x10
2244 #define DCBX_PFC_PRI_5 0x20
2245 #define DCBX_PFC_PRI_6 0x40
2246 #define DCBX_PFC_PRI_7 0x80
2247 uint8_t pfc_caps;
2248 uint8_t reserved;
2249 uint8_t enabled;
2250#elif defined(__LITTLE_ENDIAN)
2251 uint8_t enabled;
2252 uint8_t reserved;
2253 uint8_t pfc_caps;
2254 uint8_t pri_en_bitmap;
2255 #define DCBX_PFC_PRI_0 0x01
2256 #define DCBX_PFC_PRI_1 0x02
2257 #define DCBX_PFC_PRI_2 0x04
2258 #define DCBX_PFC_PRI_3 0x08
2259 #define DCBX_PFC_PRI_4 0x10
2260 #define DCBX_PFC_PRI_5 0x20
2261 #define DCBX_PFC_PRI_6 0x40
2262 #define DCBX_PFC_PRI_7 0x80
2263#endif
2264};
2265
2266struct dcbx_app_priority_entry {
2267#ifdef __BIG_ENDIAN
2268 uint16_t app_id;
2269 uint8_t pri_bitmap;
2270 uint8_t appBitfield;
2271 #define DCBX_APP_ENTRY_VALID 0x01
2272 #define DCBX_APP_ENTRY_SF_MASK 0x30
2273 #define DCBX_APP_ENTRY_SF_SHIFT 4
2274 #define DCBX_APP_SF_ETH_TYPE 0x10
2275 #define DCBX_APP_SF_PORT 0x20
2276 #define DCBX_APP_PRI_0 0x01
2277 #define DCBX_APP_PRI_1 0x02
2278 #define DCBX_APP_PRI_2 0x04
2279 #define DCBX_APP_PRI_3 0x08
2280 #define DCBX_APP_PRI_4 0x10
2281 #define DCBX_APP_PRI_5 0x20
2282 #define DCBX_APP_PRI_6 0x40
2283 #define DCBX_APP_PRI_7 0x80
2284#elif defined(__LITTLE_ENDIAN)
2285 uint8_t appBitfield;
2286 #define DCBX_APP_ENTRY_VALID 0x01
2287 #define DCBX_APP_ENTRY_SF_MASK 0x30
2288 #define DCBX_APP_ENTRY_SF_SHIFT 4
2289 #define DCBX_APP_SF_ETH_TYPE 0x10
2290 #define DCBX_APP_SF_PORT 0x20
2291 uint8_t pri_bitmap;
2292 uint16_t app_id;
2293#endif
2294};
2295
2296
2297/* FW structure in BE */
2298struct dcbx_app_priority_feature {
2299#ifdef __BIG_ENDIAN
2300 uint8_t reserved;
2301 uint8_t default_pri;
2302 uint8_t tc_supported;
2303 uint8_t enabled;
2304#elif defined(__LITTLE_ENDIAN)
2305 uint8_t enabled;
2306 uint8_t tc_supported;
2307 uint8_t default_pri;
2308 uint8_t reserved;
2309#endif
2310 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL];
2311};
2312
2313/* FW structure in BE */
2314struct dcbx_features {
2315 /* PG feature */
2316 struct dcbx_ets_feature ets;
2317 /* PFC feature */
2318 struct dcbx_pfc_feature pfc;
2319 /* APP feature */
2320 struct dcbx_app_priority_feature app;
2321};
2322
2323/* LLDP protocol parameters */
2324/* FW structure in BE */
2325struct lldp_params {
2326#ifdef __BIG_ENDIAN
2327 uint8_t msg_fast_tx_interval;
2328 uint8_t msg_tx_hold;
2329 uint8_t msg_tx_interval;
2330 uint8_t admin_status;
2331 #define LLDP_TX_ONLY 0x01
2332 #define LLDP_RX_ONLY 0x02
2333 #define LLDP_TX_RX 0x03
2334 #define LLDP_DISABLED 0x04
2335 uint8_t reserved1;
2336 uint8_t tx_fast;
2337 uint8_t tx_crd_max;
2338 uint8_t tx_crd;
2339#elif defined(__LITTLE_ENDIAN)
2340 uint8_t admin_status;
2341 #define LLDP_TX_ONLY 0x01
2342 #define LLDP_RX_ONLY 0x02
2343 #define LLDP_TX_RX 0x03
2344 #define LLDP_DISABLED 0x04
2345 uint8_t msg_tx_interval;
2346 uint8_t msg_tx_hold;
2347 uint8_t msg_fast_tx_interval;
2348 uint8_t tx_crd;
2349 uint8_t tx_crd_max;
2350 uint8_t tx_fast;
2351 uint8_t reserved1;
2352#endif
2353 #define REM_CHASSIS_ID_STAT_LEN 4
2354 #define REM_PORT_ID_STAT_LEN 4
2355 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */
2356 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN];
2357 /* Holds remote Port ID TLV header, subtype and 9B of payload. */
2358 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN];
2359};
2360
2361struct lldp_dcbx_stat {
2362 #define LOCAL_CHASSIS_ID_STAT_LEN 2
2363 #define LOCAL_PORT_ID_STAT_LEN 2
2364 /* Holds local Chassis ID 8B payload of constant subtype 4. */
2365 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN];
2366 /* Holds local Port ID 8B payload of constant subtype 3. */
2367 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN];
2368 /* Number of DCBX frames transmitted. */
2369 uint32_t num_tx_dcbx_pkts;
2370 /* Number of DCBX frames received. */
2371 uint32_t num_rx_dcbx_pkts;
2372};
2373
2374/* ADMIN MIB - DCBX local machine default configuration. */
2375struct lldp_admin_mib {
2376 uint32_t ver_cfg_flags;
2377 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001
2378 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002
2379 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004
2380 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008
2381 #define DCBX_ETS_RECO_VALID 0x00000010
2382 #define DCBX_ETS_WILLING 0x00000020
2383 #define DCBX_PFC_WILLING 0x00000040
2384 #define DCBX_APP_WILLING 0x00000080
2385 #define DCBX_VERSION_CEE 0x00000100
2386 #define DCBX_VERSION_IEEE 0x00000200
2387 #define DCBX_DCBX_ENABLED 0x00000400
2388 #define DCBX_CEE_VERSION_MASK 0x0000f000
2389 #define DCBX_CEE_VERSION_SHIFT 12
2390 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000
2391 #define DCBX_CEE_MAX_VERSION_SHIFT 16
2392 struct dcbx_features features;
2393};
2394
2395/* REMOTE MIB - remote machine DCBX configuration. */
2396struct lldp_remote_mib {
2397 uint32_t prefix_seq_num;
2398 uint32_t flags;
2399 #define DCBX_ETS_TLV_RX 0x00000001
2400 #define DCBX_PFC_TLV_RX 0x00000002
2401 #define DCBX_APP_TLV_RX 0x00000004
2402 #define DCBX_ETS_RX_ERROR 0x00000010
2403 #define DCBX_PFC_RX_ERROR 0x00000020
2404 #define DCBX_APP_RX_ERROR 0x00000040
2405 #define DCBX_ETS_REM_WILLING 0x00000100
2406 #define DCBX_PFC_REM_WILLING 0x00000200
2407 #define DCBX_APP_REM_WILLING 0x00000400
2408 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000
2409 #define DCBX_REMOTE_MIB_VALID 0x00002000
2410 struct dcbx_features features;
2411 uint32_t suffix_seq_num;
2412};
2413
2414/* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */
2415struct lldp_local_mib {
2416 uint32_t prefix_seq_num;
2417 /* Indicates if there is mismatch with negotiation results. */
2418 uint32_t error;
2419 #define DCBX_LOCAL_ETS_ERROR 0x00000001
2420 #define DCBX_LOCAL_PFC_ERROR 0x00000002
2421 #define DCBX_LOCAL_APP_ERROR 0x00000004
2422 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010
2423 #define DCBX_LOCAL_APP_MISMATCH 0x00000020
2424 #define DCBX_REMOTE_MIB_ERROR 0x00000040
2425 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080
2426 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100
2427 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200
2428 struct dcbx_features features;
2429 uint32_t suffix_seq_num;
2430};
2431
2432struct lldp_local_mib_ext {
2433 uint32_t prefix_seq_num;
2434 /* APP TLV extension - 16 more entries for negotiation results*/
2435 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL];
2436 uint32_t suffix_seq_num;
2437};
2438/***END OF DCBX STRUCTURES DECLARATIONS***/
2439
2440/***********************************************************/
2441/* Elink section */
2442/***********************************************************/
2443#define SHMEM_LINK_CONFIG_SIZE 2
2444struct shmem_lfa {
2445 uint32_t req_duplex;
2446 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff
2447 #define REQ_DUPLEX_PHY0_SHIFT 0
2448 #define REQ_DUPLEX_PHY1_MASK 0xffff0000
2449 #define REQ_DUPLEX_PHY1_SHIFT 16
2450 uint32_t req_flow_ctrl;
2451 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff
2452 #define REQ_FLOW_CTRL_PHY0_SHIFT 0
2453 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000
2454 #define REQ_FLOW_CTRL_PHY1_SHIFT 16
2455 uint32_t req_line_speed; /* Also determine AutoNeg */
2456 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff
2457 #define REQ_LINE_SPD_PHY0_SHIFT 0
2458 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000
2459 #define REQ_LINE_SPD_PHY1_SHIFT 16
2460 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE];
2461 uint32_t additional_config;
2462 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff
2463 #define REQ_FC_AUTO_ADV0_SHIFT 0
2464 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000
2465 uint32_t lfa_sts;
2466 #define LFA_LINK_FLAP_REASON_OFFSET 0
2467 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff
2468 #define LFA_LINK_DOWN 0x1
2469 #define LFA_LOOPBACK_ENABLED 0x2
2470 #define LFA_DUPLEX_MISMATCH 0x3
2471 #define LFA_MFW_IS_TOO_OLD 0x4
2472 #define LFA_LINK_SPEED_MISMATCH 0x5
2473 #define LFA_FLOW_CTRL_MISMATCH 0x6
2474 #define LFA_SPEED_CAP_MISMATCH 0x7
2475 #define LFA_DCC_LFA_DISABLED 0x8
2476 #define LFA_EEE_MISMATCH 0x9
2477
2478 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8
2479 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00
2480
2481 #define LINK_FLAP_COUNT_OFFSET 16
2482 #define LINK_FLAP_COUNT_MASK 0x00ff0000
2483
2484 #define LFA_FLAGS_MASK 0xff000000
2485 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24)
2486
2487};
2488
2489/*
2490Used to suppoert NSCI get OS driver version
2491On driver load the version value will be set
2492On driver unload driver value of 0x0 will be set
2493*/
2494struct os_drv_ver{
2495 #define DRV_VER_NOT_LOADED 0
2496 /*personalites orrder is importent */
2497 #define DRV_PERS_ETHERNET 0
2498 #define DRV_PERS_ISCSI 1
2499 #define DRV_PERS_FCOE 2
2500 /*shmem2 struct is constatnt can't add more personalites here*/
2501 #define MAX_DRV_PERS 3
2502 uint32_t versions[MAX_DRV_PERS];
2503};
2504
2505#define OEM_I2C_UUID_STR_ADDR 0x9f
2506#define OEM_I2C_CARD_SKU_STR_ADDR 0x3c
2507#define OEM_I2C_CARD_FN_STR_ADDR 0x48
2508#define OEM_I2C_CARD_NAME_STR_ADDR 0x10e
2509
2510#define OEM_I2C_UUID_STR_LEN 16
2511#define OEM_I2C_CARD_SKU_STR_LEN 12
2512#define OEM_I2C_CARD_FN_STR_LEN 12
2513#define OEM_I2C_CARD_NAME_STR_LEN 128
2514#define OEM_I2C_CARD_VERSION_STR_LEN 36
2515
2516struct oem_i2c_data_t {
2517 uint32_t size;
2518 uint8_t uuid[OEM_I2C_UUID_STR_LEN];
2519 uint8_t card_sku[OEM_I2C_CARD_SKU_STR_LEN];
2520 uint8_t card_name[OEM_I2C_CARD_NAME_STR_LEN];
2521 uint8_t card_ver[OEM_I2C_CARD_VERSION_STR_LEN];
2522 uint8_t card_fn[OEM_I2C_CARD_FN_STR_LEN];
2523};
2524
2525enum curr_cfg_method_e {
2526 CURR_CFG_MET_NONE = 0, /* default config */
2527 CURR_CFG_MET_OS = 1,
2528 CURR_CFG_MET_VENDOR_SPEC = 2,/* e.g. Option ROM, NPAR, O/S Cfg Utils */
2529 CURR_CFG_MET_HP_OTHER = 3,
2530 CURR_CFG_MET_VC_CLP = 4, /* C-Class SM-CLP */
2531 CURR_CFG_MET_HP_CNU = 5, /* Converged Network Utility */
2532 CURR_CFG_MET_HP_DCI = 6, /* DCi (BD) changes */
2533};
2534
2535#define FC_NPIV_WWPN_SIZE 8
2536#define FC_NPIV_WWNN_SIZE 8
2537struct bdn_npiv_settings {
2538 uint8_t npiv_wwpn[FC_NPIV_WWPN_SIZE];
2539 uint8_t npiv_wwnn[FC_NPIV_WWNN_SIZE];
2540};
2541
2542struct bdn_fc_npiv_cfg {
2543 /* hdr used internally by the MFW */
2544 uint32_t hdr;
2545 uint32_t num_of_npiv;
2546};
2547
2548#define MAX_NUMBER_NPIV 64
2549struct bdn_fc_npiv_tbl {
2550 struct bdn_fc_npiv_cfg fc_npiv_cfg;
2551 struct bdn_npiv_settings settings[MAX_NUMBER_NPIV];
2552};
2553
2554struct mdump_driver_info {
2555 uint32_t epoc;
2556 uint32_t drv_ver;
2557 uint32_t fw_ver;
2558
2559 uint32_t valid_dump;
2560 #define FIRST_DUMP_VALID (1 << 0)
2561 #define SECOND_DUMP_VALID (1 << 1)
2562
2563 uint32_t flags;
2564 #define ENABLE_ALL_TRIGGERS (0x7fffffff)
2565 #define TRIGGER_MDUMP_ONCE (1 << 31)
2566};
2567
2568struct shmem2_region {
2569
2570 uint32_t size; /* 0x0000 */
2571
2572 uint32_t dcc_support; /* 0x0004 */
2573 #define SHMEM_DCC_SUPPORT_NONE 0x00000000
2574 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001
2575 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004
2576 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008
2577 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040
2578 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080
2579
2580 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */
2581 /*
2582 * For backwards compatibility, if the mf_cfg_addr does not exist
2583 * (the size filed is smaller than 0xc) the mf_cfg resides at the
2584 * end of struct shmem_region
2585 */
2586 uint32_t mf_cfg_addr; /* 0x0010 */
2587 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000
2588
2589 struct fw_flr_mb flr_mb; /* 0x0014 */
2590 uint32_t dcbx_lldp_params_offset; /* 0x0028 */
2591 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000
2592 uint32_t dcbx_neg_res_offset; /* 0x002c */
2593 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000
2594 uint32_t dcbx_remote_mib_offset; /* 0x0030 */
2595 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000
2596 /*
2597 * The other shmemX_base_addr holds the other path's shmem address
2598 * required for example in case of common phy init, or for path1 to know
2599 * the address of mcp debug trace which is located in offset from shmem
2600 * of path0
2601 */
2602 uint32_t other_shmem_base_addr; /* 0x0034 */
2603 uint32_t other_shmem2_base_addr; /* 0x0038 */
2604 /*
2605 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs
2606 * which were disabled/flred
2607 */
2608 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */
2609
2610 /*
2611 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled
2612 * VFs
2613 */
2614 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */
2615
2616 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */
2617 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000
2618
2619 /*
2620 * edebug_driver_if field is used to transfer messages between edebug
2621 * app to the driver through shmem2.
2622 *
2623 * message format:
2624 * bits 0-2 - function number / instance of driver to perform request
2625 * bits 3-5 - op code / is_ack?
2626 * bits 6-63 - data
2627 */
2628 uint32_t edebug_driver_if[2]; /* 0x0068 */
2629 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1
2630 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2
2631 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3
2632
2633 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */
2634
2635 /* afex support of that driver */
2636 uint32_t afex_driver_support; /* 0x0074 */
2637 #define SHMEM_AFEX_VERSION_MASK 0x100f
2638 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001
2639 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000
2640
2641 /* driver receives addr in scratchpad to which it should respond */
2642 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX];
2643
2644 /*
2645 * generic params from MCP to driver (value depends on the msg sent
2646 * to driver
2647 */
2648 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */
2649 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */
2650
2651 uint32_t swim_base_addr; /* 0x00a8 */
2652 uint32_t swim_funcs; /* 0x00ac */
2653 uint32_t swim_main_cb; /* 0x00b0 */
2654
2655 /*
2656 * bitmap notifying which VIF profiles stored in nvram are enabled by
2657 * switch
2658 */
2659 uint32_t afex_profiles_enabled[2]; /* 0x00b4 */
2660
2661 /* generic flags controlled by the driver */
2662 uint32_t drv_flags; /* 0x00bc */
2663 #define DRV_FLAGS_DCB_CONFIGURED 0x0
2664 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1
2665 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2
2666
2667 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \
2668 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \
2669 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED))
2670 /* Port offset*/
2671 #define DRV_FLAGS_P0_OFFSET 0
2672 #define DRV_FLAGS_P1_OFFSET 16
2673 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \
2674 DRV_FLAGS_P0_OFFSET : \
2675 DRV_FLAGS_P1_OFFSET)
2676
2677 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \
2678 DRV_FLAGS_GET_PORT_OFFSET(_port))
2679
2680 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \
2681 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port)))
2682
2683 /* pointer to extended dev_info shared data copied from nvm image */
2684 uint32_t extended_dev_info_shared_addr; /* 0x00c0 */
2685 uint32_t ncsi_oem_data_addr; /* 0x00c4 */
2686
2687 uint32_t sensor_data_addr; /* 0x00c8 */
2688 uint32_t buffer_block_addr; /* 0x00cc */
2689 uint32_t sensor_data_req_update_interval; /* 0x00d0 */
2690 uint32_t temperature_in_half_celsius; /* 0x00d4 */
2691 uint32_t glob_struct_in_host; /* 0x00d8 */
2692
2693 uint32_t dcbx_neg_res_ext_offset; /* 0x00dc */
2694 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000
2695
2696 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; /* 0x00e0 */
2697 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001
2698 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002
2699 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004
2700 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008
2701 #define DRV_FLAGS_MTU_MASK 0xffff0000
2702 #define DRV_FLAGS_MTU_SHIFT 16
2703
2704 uint32_t extended_dev_info_shared_cfg_size; /* 0x00f0 */
2705
2706 uint32_t dcbx_en[PORT_MAX]; /* 0x00f4 */
2707
2708 /* The offset points to the multi threaded meta structure */
2709 uint32_t multi_thread_data_offset; /* 0x00fc */
2710
2711 /* address of DMAable host address holding values from the drivers */
2712 uint32_t drv_info_host_addr_lo; /* 0x0100 */
2713 uint32_t drv_info_host_addr_hi; /* 0x0104 */
2714
2715 /* general values written by the MFW (such as current version) */
2716 uint32_t drv_info_control; /* 0x0108 */
2717 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff
2718 #define DRV_INFO_CONTROL_VER_SHIFT 0
2719 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00
2720 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8
2721 uint32_t ibft_host_addr; /* initialized by option ROM */ /* 0x010c */
2722
2723 struct eee_remote_vals eee_remote_vals[PORT_MAX]; /* 0x0110 */
2724 uint32_t pf_allocation[E2_FUNC_MAX]; /* 0x0120 */
2725 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */
2726 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0
2727
2728 /* the status of EEE auto-negotiation
2729 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31.
2730 * bits 19:16 the supported modes for EEE.
2731 * bits 23:20 the speeds advertised for EEE.
2732 * bits 27:24 the speeds the Link partner advertised for EEE.
2733 * The supported/adv. modes in bits 27:19 originate from the
2734 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed).
2735 * bit 28 when 1'b1 EEE was requested.
2736 * bit 29 when 1'b1 tx lpi was requested.
2737 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff
2738 * 30:29 are 2'b11.
2739 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as
2740 * value. When 1'b1 those bits contains a value times 16 microseconds.
2741 */
2742 uint32_t eee_status[PORT_MAX]; /* 0x0130 */
2743 #define SHMEM_EEE_TIMER_MASK 0x0000ffff
2744 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000
2745 #define SHMEM_EEE_SUPPORTED_SHIFT 16
2746 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000
2747 #define SHMEM_EEE_100M_ADV (1<<0)
2748 #define SHMEM_EEE_1G_ADV (1<<1)
2749 #define SHMEM_EEE_10G_ADV (1<<2)
2750 #define SHMEM_EEE_ADV_STATUS_SHIFT 20
2751 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000
2752 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24
2753 #define SHMEM_EEE_REQUESTED_BIT 0x10000000
2754 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000
2755 #define SHMEM_EEE_ACTIVE_BIT 0x40000000
2756 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000
2757
2758 uint32_t sizeof_port_stats; /* 0x0138 */
2759
2760 /* Link Flap Avoidance */
2761 uint32_t lfa_host_addr[PORT_MAX]; /* 0x013c */
2762
2763 /* External PHY temperature in deg C. */
2764 uint32_t extphy_temps_in_celsius; /* 0x0144 */
2765 #define EXTPHY1_TEMP_MASK 0x0000ffff
2766 #define EXTPHY1_TEMP_SHIFT 0
2767 #define ON_BOARD_TEMP_MASK 0xffff0000
2768 #define ON_BOARD_TEMP_SHIFT 16
2769
2770 uint32_t ocdata_info_addr; /* Offset 0x148 */
2771 uint32_t drv_func_info_addr; /* Offset 0x14C */
2772 uint32_t drv_func_info_size; /* Offset 0x150 */
2773 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */
2774 #define LINK_ATTR_SYNC_KR2_ENABLE 0x00000001
2775 #define LINK_ATTR_84858 0x00000002
2776 #define LINK_SFP_EEPROM_COMP_CODE_MASK 0x0000ff00
2777 #define LINK_SFP_EEPROM_COMP_CODE_SHIFT 8
2778 #define LINK_SFP_EEPROM_COMP_CODE_SR 0x00001000
2779 #define LINK_SFP_EEPROM_COMP_CODE_LR 0x00002000
2780 #define LINK_SFP_EEPROM_COMP_CODE_LRM 0x00004000
2781
2782 uint32_t ibft_host_addr_hi; /* Initialize by uEFI ROM Offset 0x158 */
2783 uint32_t fcode_ver; /* Offset 0x15c */
2784 uint32_t link_change_count[PORT_MAX]; /* Offset 0x160-0x164 */
2785 #define LINK_CHANGE_COUNT_MASK 0xff /* Offset 0x168 */
2786 /* driver version for each personality*/
2787 struct os_drv_ver func_os_drv_ver[E2_FUNC_MAX]; /* Offset 0x16c */
2788
2789 /* Flag to the driver that PF's drv_info_host_addr buffer was read */
2790 uint32_t mfw_drv_indication; /* Offset 0x19c */
2791
2792 /* We use inidcation for each PF (0..3) */
2793 #define MFW_DRV_IND_READ_DONE_OFFSET(_pf_) (1 << _pf_)
2794
2795 union { /* For various OEMs */ /* Offset 0x1a0 */
2796 uint8_t storage_boot_prog[E2_FUNC_MAX];
2797 #define STORAGE_BOOT_PROG_MASK 0x000000FF
2798 #define STORAGE_BOOT_PROG_NONE 0x00000000
2799 #define STORAGE_BOOT_PROG_ISCSI_IP_ACQUIRED 0x00000002
2800 #define STORAGE_BOOT_PROG_FCOE_FABRIC_LOGIN_SUCCESS 0x00000002
2801 #define STORAGE_BOOT_PROG_TARGET_FOUND 0x00000004
2802 #define STORAGE_BOOT_PROG_ISCSI_CHAP_SUCCESS 0x00000008
2803 #define STORAGE_BOOT_PROG_FCOE_LUN_FOUND 0x00000008
2804 #define STORAGE_BOOT_PROG_LOGGED_INTO_TGT 0x00000010
2805 #define STORAGE_BOOT_PROG_IMG_DOWNLOADED 0x00000020
2806 #define STORAGE_BOOT_PROG_OS_HANDOFF 0x00000040
2807 #define STORAGE_BOOT_PROG_COMPLETED 0x00000080
2808
2809 uint32_t oem_i2c_data_addr;
2810 }u;
2811
2812 /* 9 entires for the C2S PCP map for each inner VLAN PCP + 1 default */
2813 /* For PCP values 0-3 use the map lower */
2814 /* 0xFF000000 - PCP 0, 0x00FF0000 - PCP 1,
2815 * 0x0000FF00 - PCP 2, 0x000000FF PCP 3
2816 */
2817 uint32_t c2s_pcp_map_lower[E2_FUNC_MAX]; /* 0x1a4 */
2818
2819 /* For PCP values 4-7 use the map upper */
2820 /* 0xFF000000 - PCP 4, 0x00FF0000 - PCP 5,
2821 * 0x0000FF00 - PCP 6, 0x000000FF PCP 7
2822 */
2823 uint32_t c2s_pcp_map_upper[E2_FUNC_MAX]; /* 0x1b4 */
2824
2825 /* For PCP default value get the MSB byte of the map default */
2826 uint32_t c2s_pcp_map_default[E2_FUNC_MAX]; /* 0x1c4 */
2827
2828 /* FC_NPIV table offset in NVRAM */
2829 uint32_t fc_npiv_nvram_tbl_addr[PORT_MAX]; /* 0x1d4 */
2830
2831 /* Shows last method that changed configuration of this device */
2832 enum curr_cfg_method_e curr_cfg; /* 0x1dc */
2833
2834 /* Storm FW version, shold be kept in the format 0xMMmmbbdd:
2835 * MM - Major, mm - Minor, bb - Build ,dd - Drop
2836 */
2837 uint32_t netproc_fw_ver; /* 0x1e0 */
2838
2839 /* Option ROM SMASH CLP version */
2840 uint32_t clp_ver; /* 0x1e4 */
2841
2842 uint32_t pcie_bus_num; /* 0x1e8 */
2843
2844 uint32_t sriov_switch_mode; /* 0x1ec */
2845 #define SRIOV_SWITCH_MODE_NONE 0x0
2846 #define SRIOV_SWITCH_MODE_VEB 0x1
2847 #define SRIOV_SWITCH_MODE_VEPA 0x2
2848
2849 uint8_t rsrv2[E2_FUNC_MAX]; /* 0x1f0 */
2850
2851 uint32_t img_inv_table_addr; /* Address to INV_TABLE_P */ /* 0x1f4 */
2852
2853 uint32_t mtu_size[E2_FUNC_MAX]; /* 0x1f8 */
2854
2855 uint32_t os_driver_state[E2_FUNC_MAX]; /* 0x208 */
2856 #define OS_DRIVER_STATE_NOT_LOADED 0 /* not installed */
2857 #define OS_DRIVER_STATE_LOADING 1 /* transition state */
2858 #define OS_DRIVER_STATE_DISABLED 2 /* installed but disabled */
2859 #define OS_DRIVER_STATE_ACTIVE 3 /* installed and active */
2860
2861 /* mini dump driver info */
2862 struct mdump_driver_info drv_info; /* 0x218 */
2863
2864 /* 0x22c */
2865};
2866
2867
2868struct emac_stats {
2869 uint32_t rx_stat_ifhcinoctets;
2870 uint32_t rx_stat_ifhcinbadoctets;
2871 uint32_t rx_stat_etherstatsfragments;
2872 uint32_t rx_stat_ifhcinucastpkts;
2873 uint32_t rx_stat_ifhcinmulticastpkts;
2874 uint32_t rx_stat_ifhcinbroadcastpkts;
2875 uint32_t rx_stat_dot3statsfcserrors;
2876 uint32_t rx_stat_dot3statsalignmenterrors;
2877 uint32_t rx_stat_dot3statscarriersenseerrors;
2878 uint32_t rx_stat_xonpauseframesreceived;
2879 uint32_t rx_stat_xoffpauseframesreceived;
2880 uint32_t rx_stat_maccontrolframesreceived;
2881 uint32_t rx_stat_xoffstateentered;
2882 uint32_t rx_stat_dot3statsframestoolong;
2883 uint32_t rx_stat_etherstatsjabbers;
2884 uint32_t rx_stat_etherstatsundersizepkts;
2885 uint32_t rx_stat_etherstatspkts64octets;
2886 uint32_t rx_stat_etherstatspkts65octetsto127octets;
2887 uint32_t rx_stat_etherstatspkts128octetsto255octets;
2888 uint32_t rx_stat_etherstatspkts256octetsto511octets;
2889 uint32_t rx_stat_etherstatspkts512octetsto1023octets;
2890 uint32_t rx_stat_etherstatspkts1024octetsto1522octets;
2891 uint32_t rx_stat_etherstatspktsover1522octets;
2892
2893 uint32_t rx_stat_falsecarriererrors;
2894
2895 uint32_t tx_stat_ifhcoutoctets;
2896 uint32_t tx_stat_ifhcoutbadoctets;
2897 uint32_t tx_stat_etherstatscollisions;
2898 uint32_t tx_stat_outxonsent;
2899 uint32_t tx_stat_outxoffsent;
2900 uint32_t tx_stat_flowcontroldone;
2901 uint32_t tx_stat_dot3statssinglecollisionframes;
2902 uint32_t tx_stat_dot3statsmultiplecollisionframes;
2903 uint32_t tx_stat_dot3statsdeferredtransmissions;
2904 uint32_t tx_stat_dot3statsexcessivecollisions;
2905 uint32_t tx_stat_dot3statslatecollisions;
2906 uint32_t tx_stat_ifhcoutucastpkts;
2907 uint32_t tx_stat_ifhcoutmulticastpkts;
2908 uint32_t tx_stat_ifhcoutbroadcastpkts;
2909 uint32_t tx_stat_etherstatspkts64octets;
2910 uint32_t tx_stat_etherstatspkts65octetsto127octets;
2911 uint32_t tx_stat_etherstatspkts128octetsto255octets;
2912 uint32_t tx_stat_etherstatspkts256octetsto511octets;
2913 uint32_t tx_stat_etherstatspkts512octetsto1023octets;
2914 uint32_t tx_stat_etherstatspkts1024octetsto1522octets;
2915 uint32_t tx_stat_etherstatspktsover1522octets;
2916 uint32_t tx_stat_dot3statsinternalmactransmiterrors;
2917};
2918
2919
2920struct bmac1_stats {
2921 uint32_t tx_stat_gtpkt_lo;
2922 uint32_t tx_stat_gtpkt_hi;
2923 uint32_t tx_stat_gtxpf_lo;
2924 uint32_t tx_stat_gtxpf_hi;
2925 uint32_t tx_stat_gtfcs_lo;
2926 uint32_t tx_stat_gtfcs_hi;
2927 uint32_t tx_stat_gtmca_lo;
2928 uint32_t tx_stat_gtmca_hi;
2929 uint32_t tx_stat_gtbca_lo;
2930 uint32_t tx_stat_gtbca_hi;
2931 uint32_t tx_stat_gtfrg_lo;
2932 uint32_t tx_stat_gtfrg_hi;
2933 uint32_t tx_stat_gtovr_lo;
2934 uint32_t tx_stat_gtovr_hi;
2935 uint32_t tx_stat_gt64_lo;
2936 uint32_t tx_stat_gt64_hi;
2937 uint32_t tx_stat_gt127_lo;
2938 uint32_t tx_stat_gt127_hi;
2939 uint32_t tx_stat_gt255_lo;
2940 uint32_t tx_stat_gt255_hi;
2941 uint32_t tx_stat_gt511_lo;
2942 uint32_t tx_stat_gt511_hi;
2943 uint32_t tx_stat_gt1023_lo;
2944 uint32_t tx_stat_gt1023_hi;
2945 uint32_t tx_stat_gt1518_lo;
2946 uint32_t tx_stat_gt1518_hi;
2947 uint32_t tx_stat_gt2047_lo;
2948 uint32_t tx_stat_gt2047_hi;
2949 uint32_t tx_stat_gt4095_lo;
2950 uint32_t tx_stat_gt4095_hi;
2951 uint32_t tx_stat_gt9216_lo;
2952 uint32_t tx_stat_gt9216_hi;
2953 uint32_t tx_stat_gt16383_lo;
2954 uint32_t tx_stat_gt16383_hi;
2955 uint32_t tx_stat_gtmax_lo;
2956 uint32_t tx_stat_gtmax_hi;
2957 uint32_t tx_stat_gtufl_lo;
2958 uint32_t tx_stat_gtufl_hi;
2959 uint32_t tx_stat_gterr_lo;
2960 uint32_t tx_stat_gterr_hi;
2961 uint32_t tx_stat_gtbyt_lo;
2962 uint32_t tx_stat_gtbyt_hi;
2963
2964 uint32_t rx_stat_gr64_lo;
2965 uint32_t rx_stat_gr64_hi;
2966 uint32_t rx_stat_gr127_lo;
2967 uint32_t rx_stat_gr127_hi;
2968 uint32_t rx_stat_gr255_lo;
2969 uint32_t rx_stat_gr255_hi;
2970 uint32_t rx_stat_gr511_lo;
2971 uint32_t rx_stat_gr511_hi;
2972 uint32_t rx_stat_gr1023_lo;
2973 uint32_t rx_stat_gr1023_hi;
2974 uint32_t rx_stat_gr1518_lo;
2975 uint32_t rx_stat_gr1518_hi;
2976 uint32_t rx_stat_gr2047_lo;
2977 uint32_t rx_stat_gr2047_hi;
2978 uint32_t rx_stat_gr4095_lo;
2979 uint32_t rx_stat_gr4095_hi;
2980 uint32_t rx_stat_gr9216_lo;
2981 uint32_t rx_stat_gr9216_hi;
2982 uint32_t rx_stat_gr16383_lo;
2983 uint32_t rx_stat_gr16383_hi;
2984 uint32_t rx_stat_grmax_lo;
2985 uint32_t rx_stat_grmax_hi;
2986 uint32_t rx_stat_grpkt_lo;
2987 uint32_t rx_stat_grpkt_hi;
2988 uint32_t rx_stat_grfcs_lo;
2989 uint32_t rx_stat_grfcs_hi;
2990 uint32_t rx_stat_grmca_lo;
2991 uint32_t rx_stat_grmca_hi;
2992 uint32_t rx_stat_grbca_lo;
2993 uint32_t rx_stat_grbca_hi;
2994 uint32_t rx_stat_grxcf_lo;
2995 uint32_t rx_stat_grxcf_hi;
2996 uint32_t rx_stat_grxpf_lo;
2997 uint32_t rx_stat_grxpf_hi;
2998 uint32_t rx_stat_grxuo_lo;
2999 uint32_t rx_stat_grxuo_hi;
3000 uint32_t rx_stat_grjbr_lo;
3001 uint32_t rx_stat_grjbr_hi;
3002 uint32_t rx_stat_grovr_lo;
3003 uint32_t rx_stat_grovr_hi;
3004 uint32_t rx_stat_grflr_lo;
3005 uint32_t rx_stat_grflr_hi;
3006 uint32_t rx_stat_grmeg_lo;
3007 uint32_t rx_stat_grmeg_hi;
3008 uint32_t rx_stat_grmeb_lo;
3009 uint32_t rx_stat_grmeb_hi;
3010 uint32_t rx_stat_grbyt_lo;
3011 uint32_t rx_stat_grbyt_hi;
3012 uint32_t rx_stat_grund_lo;
3013 uint32_t rx_stat_grund_hi;
3014 uint32_t rx_stat_grfrg_lo;
3015 uint32_t rx_stat_grfrg_hi;
3016 uint32_t rx_stat_grerb_lo;
3017 uint32_t rx_stat_grerb_hi;
3018 uint32_t rx_stat_grfre_lo;
3019 uint32_t rx_stat_grfre_hi;
3020 uint32_t rx_stat_gripj_lo;
3021 uint32_t rx_stat_gripj_hi;
3022};
3023
3024struct bmac2_stats {
3025 uint32_t tx_stat_gtpk_lo; /* gtpok */
3026 uint32_t tx_stat_gtpk_hi; /* gtpok */
3027 uint32_t tx_stat_gtxpf_lo; /* gtpf */
3028 uint32_t tx_stat_gtxpf_hi; /* gtpf */
3029 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */
3030 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */
3031 uint32_t tx_stat_gtfcs_lo;
3032 uint32_t tx_stat_gtfcs_hi;
3033 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */
3034 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */
3035 uint32_t tx_stat_gtmca_lo;
3036 uint32_t tx_stat_gtmca_hi;
3037 uint32_t tx_stat_gtbca_lo;
3038 uint32_t tx_stat_gtbca_hi;
3039 uint32_t tx_stat_gtovr_lo;
3040 uint32_t tx_stat_gtovr_hi;
3041 uint32_t tx_stat_gtfrg_lo;
3042 uint32_t tx_stat_gtfrg_hi;
3043 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */
3044 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */
3045 uint32_t tx_stat_gt64_lo;
3046 uint32_t tx_stat_gt64_hi;
3047 uint32_t tx_stat_gt127_lo;
3048 uint32_t tx_stat_gt127_hi;
3049 uint32_t tx_stat_gt255_lo;
3050 uint32_t tx_stat_gt255_hi;
3051 uint32_t tx_stat_gt511_lo;
3052 uint32_t tx_stat_gt511_hi;
3053 uint32_t tx_stat_gt1023_lo;
3054 uint32_t tx_stat_gt1023_hi;
3055 uint32_t tx_stat_gt1518_lo;
3056 uint32_t tx_stat_gt1518_hi;
3057 uint32_t tx_stat_gt2047_lo;
3058 uint32_t tx_stat_gt2047_hi;
3059 uint32_t tx_stat_gt4095_lo;
3060 uint32_t tx_stat_gt4095_hi;
3061 uint32_t tx_stat_gt9216_lo;
3062 uint32_t tx_stat_gt9216_hi;
3063 uint32_t tx_stat_gt16383_lo;
3064 uint32_t tx_stat_gt16383_hi;
3065 uint32_t tx_stat_gtmax_lo;
3066 uint32_t tx_stat_gtmax_hi;
3067 uint32_t tx_stat_gtufl_lo;
3068 uint32_t tx_stat_gtufl_hi;
3069 uint32_t tx_stat_gterr_lo;
3070 uint32_t tx_stat_gterr_hi;
3071 uint32_t tx_stat_gtbyt_lo;
3072 uint32_t tx_stat_gtbyt_hi;
3073
3074 uint32_t rx_stat_gr64_lo;
3075 uint32_t rx_stat_gr64_hi;
3076 uint32_t rx_stat_gr127_lo;
3077 uint32_t rx_stat_gr127_hi;
3078 uint32_t rx_stat_gr255_lo;
3079 uint32_t rx_stat_gr255_hi;
3080 uint32_t rx_stat_gr511_lo;
3081 uint32_t rx_stat_gr511_hi;
3082 uint32_t rx_stat_gr1023_lo;
3083 uint32_t rx_stat_gr1023_hi;
3084 uint32_t rx_stat_gr1518_lo;
3085 uint32_t rx_stat_gr1518_hi;
3086 uint32_t rx_stat_gr2047_lo;
3087 uint32_t rx_stat_gr2047_hi;
3088 uint32_t rx_stat_gr4095_lo;
3089 uint32_t rx_stat_gr4095_hi;
3090 uint32_t rx_stat_gr9216_lo;
3091 uint32_t rx_stat_gr9216_hi;
3092 uint32_t rx_stat_gr16383_lo;
3093 uint32_t rx_stat_gr16383_hi;
3094 uint32_t rx_stat_grmax_lo;
3095 uint32_t rx_stat_grmax_hi;
3096 uint32_t rx_stat_grpkt_lo;
3097 uint32_t rx_stat_grpkt_hi;
3098 uint32_t rx_stat_grfcs_lo;
3099 uint32_t rx_stat_grfcs_hi;
3100 uint32_t rx_stat_gruca_lo;
3101 uint32_t rx_stat_gruca_hi;
3102 uint32_t rx_stat_grmca_lo;
3103 uint32_t rx_stat_grmca_hi;
3104 uint32_t rx_stat_grbca_lo;
3105 uint32_t rx_stat_grbca_hi;
3106 uint32_t rx_stat_grxpf_lo; /* grpf */
3107 uint32_t rx_stat_grxpf_hi; /* grpf */
3108 uint32_t rx_stat_grpp_lo;
3109 uint32_t rx_stat_grpp_hi;
3110 uint32_t rx_stat_grxuo_lo; /* gruo */
3111 uint32_t rx_stat_grxuo_hi; /* gruo */
3112 uint32_t rx_stat_grjbr_lo;
3113 uint32_t rx_stat_grjbr_hi;
3114 uint32_t rx_stat_grovr_lo;
3115 uint32_t rx_stat_grovr_hi;
3116 uint32_t rx_stat_grxcf_lo; /* grcf */
3117 uint32_t rx_stat_grxcf_hi; /* grcf */
3118 uint32_t rx_stat_grflr_lo;
3119 uint32_t rx_stat_grflr_hi;
3120 uint32_t rx_stat_grpok_lo;
3121 uint32_t rx_stat_grpok_hi;
3122 uint32_t rx_stat_grmeg_lo;
3123 uint32_t rx_stat_grmeg_hi;
3124 uint32_t rx_stat_grmeb_lo;
3125 uint32_t rx_stat_grmeb_hi;
3126 uint32_t rx_stat_grbyt_lo;
3127 uint32_t rx_stat_grbyt_hi;
3128 uint32_t rx_stat_grund_lo;
3129 uint32_t rx_stat_grund_hi;
3130 uint32_t rx_stat_grfrg_lo;
3131 uint32_t rx_stat_grfrg_hi;
3132 uint32_t rx_stat_grerb_lo; /* grerrbyt */
3133 uint32_t rx_stat_grerb_hi; /* grerrbyt */
3134 uint32_t rx_stat_grfre_lo; /* grfrerr */
3135 uint32_t rx_stat_grfre_hi; /* grfrerr */
3136 uint32_t rx_stat_gripj_lo;
3137 uint32_t rx_stat_gripj_hi;
3138};
3139
3140struct mstat_stats {
3141 struct {
3142 /* OTE MSTAT on E3 has a bug where this register's contents are
3143 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp
3144 */
3145 uint32_t tx_gtxpok_lo;
3146 uint32_t tx_gtxpok_hi;
3147 uint32_t tx_gtxpf_lo;
3148 uint32_t tx_gtxpf_hi;
3149 uint32_t tx_gtxpp_lo;
3150 uint32_t tx_gtxpp_hi;
3151 uint32_t tx_gtfcs_lo;
3152 uint32_t tx_gtfcs_hi;
3153 uint32_t tx_gtuca_lo;
3154 uint32_t tx_gtuca_hi;
3155 uint32_t tx_gtmca_lo;
3156 uint32_t tx_gtmca_hi;
3157 uint32_t tx_gtgca_lo;
3158 uint32_t tx_gtgca_hi;
3159 uint32_t tx_gtpkt_lo;
3160 uint32_t tx_gtpkt_hi;
3161 uint32_t tx_gt64_lo;
3162 uint32_t tx_gt64_hi;
3163 uint32_t tx_gt127_lo;
3164 uint32_t tx_gt127_hi;
3165 uint32_t tx_gt255_lo;
3166 uint32_t tx_gt255_hi;
3167 uint32_t tx_gt511_lo;
3168 uint32_t tx_gt511_hi;
3169 uint32_t tx_gt1023_lo;
3170 uint32_t tx_gt1023_hi;
3171 uint32_t tx_gt1518_lo;
3172 uint32_t tx_gt1518_hi;
3173 uint32_t tx_gt2047_lo;
3174 uint32_t tx_gt2047_hi;
3175 uint32_t tx_gt4095_lo;
3176 uint32_t tx_gt4095_hi;
3177 uint32_t tx_gt9216_lo;
3178 uint32_t tx_gt9216_hi;
3179 uint32_t tx_gt16383_lo;
3180 uint32_t tx_gt16383_hi;
3181 uint32_t tx_gtufl_lo;
3182 uint32_t tx_gtufl_hi;
3183 uint32_t tx_gterr_lo;
3184 uint32_t tx_gterr_hi;
3185 uint32_t tx_gtbyt_lo;
3186 uint32_t tx_gtbyt_hi;
3187 uint32_t tx_collisions_lo;
3188 uint32_t tx_collisions_hi;
3189 uint32_t tx_singlecollision_lo;
3190 uint32_t tx_singlecollision_hi;
3191 uint32_t tx_multiplecollisions_lo;
3192 uint32_t tx_multiplecollisions_hi;
3193 uint32_t tx_deferred_lo;
3194 uint32_t tx_deferred_hi;
3195 uint32_t tx_excessivecollisions_lo;
3196 uint32_t tx_excessivecollisions_hi;
3197 uint32_t tx_latecollisions_lo;
3198 uint32_t tx_latecollisions_hi;
3199 } stats_tx;
3200
3201 struct {
3202 uint32_t rx_gr64_lo;
3203 uint32_t rx_gr64_hi;
3204 uint32_t rx_gr127_lo;
3205 uint32_t rx_gr127_hi;
3206 uint32_t rx_gr255_lo;
3207 uint32_t rx_gr255_hi;
3208 uint32_t rx_gr511_lo;
3209 uint32_t rx_gr511_hi;
3210 uint32_t rx_gr1023_lo;
3211 uint32_t rx_gr1023_hi;
3212 uint32_t rx_gr1518_lo;
3213 uint32_t rx_gr1518_hi;
3214 uint32_t rx_gr2047_lo;
3215 uint32_t rx_gr2047_hi;
3216 uint32_t rx_gr4095_lo;
3217 uint32_t rx_gr4095_hi;
3218 uint32_t rx_gr9216_lo;
3219 uint32_t rx_gr9216_hi;
3220 uint32_t rx_gr16383_lo;
3221 uint32_t rx_gr16383_hi;
3222 uint32_t rx_grpkt_lo;
3223 uint32_t rx_grpkt_hi;
3224 uint32_t rx_grfcs_lo;
3225 uint32_t rx_grfcs_hi;
3226 uint32_t rx_gruca_lo;
3227 uint32_t rx_gruca_hi;
3228 uint32_t rx_grmca_lo;
3229 uint32_t rx_grmca_hi;
3230 uint32_t rx_grbca_lo;
3231 uint32_t rx_grbca_hi;
3232 uint32_t rx_grxpf_lo;
3233 uint32_t rx_grxpf_hi;
3234 uint32_t rx_grxpp_lo;
3235 uint32_t rx_grxpp_hi;
3236 uint32_t rx_grxuo_lo;
3237 uint32_t rx_grxuo_hi;
3238 uint32_t rx_grovr_lo;
3239 uint32_t rx_grovr_hi;
3240 uint32_t rx_grxcf_lo;
3241 uint32_t rx_grxcf_hi;
3242 uint32_t rx_grflr_lo;
3243 uint32_t rx_grflr_hi;
3244 uint32_t rx_grpok_lo;
3245 uint32_t rx_grpok_hi;
3246 uint32_t rx_grbyt_lo;
3247 uint32_t rx_grbyt_hi;
3248 uint32_t rx_grund_lo;
3249 uint32_t rx_grund_hi;
3250 uint32_t rx_grfrg_lo;
3251 uint32_t rx_grfrg_hi;
3252 uint32_t rx_grerb_lo;
3253 uint32_t rx_grerb_hi;
3254 uint32_t rx_grfre_lo;
3255 uint32_t rx_grfre_hi;
3256
3257 uint32_t rx_alignmenterrors_lo;
3258 uint32_t rx_alignmenterrors_hi;
3259 uint32_t rx_falsecarrier_lo;
3260 uint32_t rx_falsecarrier_hi;
3261 uint32_t rx_llfcmsgcnt_lo;
3262 uint32_t rx_llfcmsgcnt_hi;
3263 } stats_rx;
3264};
3265
3266union mac_stats {
3267 struct emac_stats emac_stats;
3268 struct bmac1_stats bmac1_stats;
3269 struct bmac2_stats bmac2_stats;
3270 struct mstat_stats mstat_stats;
3271};
3272
3273
3274struct mac_stx {
3275 /* in_bad_octets */
3276 uint32_t rx_stat_ifhcinbadoctets_hi;
3277 uint32_t rx_stat_ifhcinbadoctets_lo;
3278
3279 /* out_bad_octets */
3280 uint32_t tx_stat_ifhcoutbadoctets_hi;
3281 uint32_t tx_stat_ifhcoutbadoctets_lo;
3282
3283 /* crc_receive_errors */
3284 uint32_t rx_stat_dot3statsfcserrors_hi;
3285 uint32_t rx_stat_dot3statsfcserrors_lo;
3286 /* alignment_errors */
3287 uint32_t rx_stat_dot3statsalignmenterrors_hi;
3288 uint32_t rx_stat_dot3statsalignmenterrors_lo;
3289 /* carrier_sense_errors */
3290 uint32_t rx_stat_dot3statscarriersenseerrors_hi;
3291 uint32_t rx_stat_dot3statscarriersenseerrors_lo;
3292 /* false_carrier_detections */
3293 uint32_t rx_stat_falsecarriererrors_hi;
3294 uint32_t rx_stat_falsecarriererrors_lo;
3295
3296 /* runt_packets_received */
3297 uint32_t rx_stat_etherstatsundersizepkts_hi;
3298 uint32_t rx_stat_etherstatsundersizepkts_lo;
3299 /* jabber_packets_received */
3300 uint32_t rx_stat_dot3statsframestoolong_hi;
3301 uint32_t rx_stat_dot3statsframestoolong_lo;
3302
3303 /* error_runt_packets_received */
3304 uint32_t rx_stat_etherstatsfragments_hi;
3305 uint32_t rx_stat_etherstatsfragments_lo;
3306 /* error_jabber_packets_received */
3307 uint32_t rx_stat_etherstatsjabbers_hi;
3308 uint32_t rx_stat_etherstatsjabbers_lo;
3309
3310 /* control_frames_received */
3311 uint32_t rx_stat_maccontrolframesreceived_hi;
3312 uint32_t rx_stat_maccontrolframesreceived_lo;
3313 uint32_t rx_stat_mac_xpf_hi;
3314 uint32_t rx_stat_mac_xpf_lo;
3315 uint32_t rx_stat_mac_xcf_hi;
3316 uint32_t rx_stat_mac_xcf_lo;
3317
3318 /* xoff_state_entered */
3319 uint32_t rx_stat_xoffstateentered_hi;
3320 uint32_t rx_stat_xoffstateentered_lo;
3321 /* pause_xon_frames_received */
3322 uint32_t rx_stat_xonpauseframesreceived_hi;
3323 uint32_t rx_stat_xonpauseframesreceived_lo;
3324 /* pause_xoff_frames_received */
3325 uint32_t rx_stat_xoffpauseframesreceived_hi;
3326 uint32_t rx_stat_xoffpauseframesreceived_lo;
3327 /* pause_xon_frames_transmitted */
3328 uint32_t tx_stat_outxonsent_hi;
3329 uint32_t tx_stat_outxonsent_lo;
3330 /* pause_xoff_frames_transmitted */
3331 uint32_t tx_stat_outxoffsent_hi;
3332 uint32_t tx_stat_outxoffsent_lo;
3333 /* flow_control_done */
3334 uint32_t tx_stat_flowcontroldone_hi;
3335 uint32_t tx_stat_flowcontroldone_lo;
3336
3337 /* ether_stats_collisions */
3338 uint32_t tx_stat_etherstatscollisions_hi;
3339 uint32_t tx_stat_etherstatscollisions_lo;
3340 /* single_collision_transmit_frames */
3341 uint32_t tx_stat_dot3statssinglecollisionframes_hi;
3342 uint32_t tx_stat_dot3statssinglecollisionframes_lo;
3343 /* multiple_collision_transmit_frames */
3344 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi;
3345 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo;
3346 /* deferred_transmissions */
3347 uint32_t tx_stat_dot3statsdeferredtransmissions_hi;
3348 uint32_t tx_stat_dot3statsdeferredtransmissions_lo;
3349 /* excessive_collision_frames */
3350 uint32_t tx_stat_dot3statsexcessivecollisions_hi;
3351 uint32_t tx_stat_dot3statsexcessivecollisions_lo;
3352 /* late_collision_frames */
3353 uint32_t tx_stat_dot3statslatecollisions_hi;
3354 uint32_t tx_stat_dot3statslatecollisions_lo;
3355
3356 /* frames_transmitted_64_bytes */
3357 uint32_t tx_stat_etherstatspkts64octets_hi;
3358 uint32_t tx_stat_etherstatspkts64octets_lo;
3359 /* frames_transmitted_65_127_bytes */
3360 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi;
3361 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo;
3362 /* frames_transmitted_128_255_bytes */
3363 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi;
3364 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo;
3365 /* frames_transmitted_256_511_bytes */
3366 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi;
3367 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo;
3368 /* frames_transmitted_512_1023_bytes */
3369 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi;
3370 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo;
3371 /* frames_transmitted_1024_1522_bytes */
3372 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi;
3373 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo;
3374 /* frames_transmitted_1523_9022_bytes */
3375 uint32_t tx_stat_etherstatspktsover1522octets_hi;
3376 uint32_t tx_stat_etherstatspktsover1522octets_lo;
3377 uint32_t tx_stat_mac_2047_hi;
3378 uint32_t tx_stat_mac_2047_lo;
3379 uint32_t tx_stat_mac_4095_hi;
3380 uint32_t tx_stat_mac_4095_lo;
3381 uint32_t tx_stat_mac_9216_hi;
3382 uint32_t tx_stat_mac_9216_lo;
3383 uint32_t tx_stat_mac_16383_hi;
3384 uint32_t tx_stat_mac_16383_lo;
3385
3386 /* internal_mac_transmit_errors */
3387 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi;
3388 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo;
3389
3390 /* if_out_discards */
3391 uint32_t tx_stat_mac_ufl_hi;
3392 uint32_t tx_stat_mac_ufl_lo;
3393};
3394
3395
3396#define MAC_STX_IDX_MAX 2
3397
3398struct host_port_stats {
3399 uint32_t host_port_stats_counter;
3400
3401 struct mac_stx mac_stx[MAC_STX_IDX_MAX];
3402
3403 uint32_t brb_drop_hi;
3404 uint32_t brb_drop_lo;
3405
3406 uint32_t not_used; /* obsolete as of MFW 7.2.1 */
3407
3408 uint32_t pfc_frames_tx_hi;
3409 uint32_t pfc_frames_tx_lo;
3410 uint32_t pfc_frames_rx_hi;
3411 uint32_t pfc_frames_rx_lo;
3412
3413 uint32_t eee_lpi_count_hi;
3414 uint32_t eee_lpi_count_lo;
3415};
3416
3417
3418struct host_func_stats {
3419 uint32_t host_func_stats_start;
3420
3421 uint32_t total_bytes_received_hi;
3422 uint32_t total_bytes_received_lo;
3423
3424 uint32_t total_bytes_transmitted_hi;
3425 uint32_t total_bytes_transmitted_lo;
3426
3427 uint32_t total_unicast_packets_received_hi;
3428 uint32_t total_unicast_packets_received_lo;
3429
3430 uint32_t total_multicast_packets_received_hi;
3431 uint32_t total_multicast_packets_received_lo;
3432
3433 uint32_t total_broadcast_packets_received_hi;
3434 uint32_t total_broadcast_packets_received_lo;
3435
3436 uint32_t total_unicast_packets_transmitted_hi;
3437 uint32_t total_unicast_packets_transmitted_lo;
3438
3439 uint32_t total_multicast_packets_transmitted_hi;
3440 uint32_t total_multicast_packets_transmitted_lo;
3441
3442 uint32_t total_broadcast_packets_transmitted_hi;
3443 uint32_t total_broadcast_packets_transmitted_lo;
3444
3445 uint32_t valid_bytes_received_hi;
3446 uint32_t valid_bytes_received_lo;
3447
3448 uint32_t host_func_stats_end;
3449};
3450
3451/* VIC definitions */
3452#define VICSTATST_UIF_INDEX 2
3453
3454/*
3455 * stats collected for afex.
3456 * NOTE: structure is exactly as expected to be received by the switch.
3457 * order must remain exactly as is unless protocol changes !
3458 */
3459struct afex_stats {
3460 uint32_t tx_unicast_frames_hi;
3461 uint32_t tx_unicast_frames_lo;
3462 uint32_t tx_unicast_bytes_hi;
3463 uint32_t tx_unicast_bytes_lo;
3464 uint32_t tx_multicast_frames_hi;
3465 uint32_t tx_multicast_frames_lo;
3466 uint32_t tx_multicast_bytes_hi;
3467 uint32_t tx_multicast_bytes_lo;
3468 uint32_t tx_broadcast_frames_hi;
3469 uint32_t tx_broadcast_frames_lo;
3470 uint32_t tx_broadcast_bytes_hi;
3471 uint32_t tx_broadcast_bytes_lo;
3472 uint32_t tx_frames_discarded_hi;
3473 uint32_t tx_frames_discarded_lo;
3474 uint32_t tx_frames_dropped_hi;
3475 uint32_t tx_frames_dropped_lo;
3476
3477 uint32_t rx_unicast_frames_hi;
3478 uint32_t rx_unicast_frames_lo;
3479 uint32_t rx_unicast_bytes_hi;
3480 uint32_t rx_unicast_bytes_lo;
3481 uint32_t rx_multicast_frames_hi;
3482 uint32_t rx_multicast_frames_lo;
3483 uint32_t rx_multicast_bytes_hi;
3484 uint32_t rx_multicast_bytes_lo;
3485 uint32_t rx_broadcast_frames_hi;
3486 uint32_t rx_broadcast_frames_lo;
3487 uint32_t rx_broadcast_bytes_hi;
3488 uint32_t rx_broadcast_bytes_lo;
3489 uint32_t rx_frames_discarded_hi;
3490 uint32_t rx_frames_discarded_lo;
3491 uint32_t rx_frames_dropped_hi;
3492 uint32_t rx_frames_dropped_lo;
3493};
3494
3495/* To maintain backward compatibility between FW and drivers, new elements */
3496/* should be added to the end of the structure. */
3497
3498/* Per Port Statistics */
3499struct port_info {
3500 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */
3501 uint32_t enabled; /* 0 =Disabled, 1= Enabled */
3502 uint32_t link_speed; /* multiplier of 100Mb */
3503 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */
3504 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/
3505 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */
3506 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */
3507 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI.
3508 This is flagged by Consumer as an error. */
3509 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */
3510 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */
3511 uint32_t rx_mcast_lo; /* RX Multicast Packets */
3512 uint32_t rx_mcast_hi; /* RX Multicast Packets */
3513 uint32_t rx_bcast_lo; /* RX Broadcast Packets */
3514 uint32_t rx_bcast_hi; /* RX Broadcast Packets */
3515 uint32_t tx_uncast_lo; /* TX Unicast Packets */
3516 uint32_t tx_uncast_hi; /* TX Unicast Packets */
3517 uint32_t tx_mcast_lo; /* TX Multicast Packets */
3518 uint32_t tx_mcast_hi; /* TX Multicast Packets */
3519 uint32_t tx_bcast_lo; /* TX Broadcast Packets */
3520 uint32_t tx_bcast_hi; /* TX Broadcast Packets */
3521 uint32_t tx_errors; /* TX Errors */
3522 uint32_t tx_discards; /* TX Discards */
3523 uint32_t rx_frames_lo; /* RX Frames received */
3524 uint32_t rx_frames_hi; /* RX Frames received */
3525 uint32_t rx_bytes_lo; /* RX Bytes received */
3526 uint32_t rx_bytes_hi; /* RX Bytes received */
3527 uint32_t tx_frames_lo; /* TX Frames sent */
3528 uint32_t tx_frames_hi; /* TX Frames sent */
3529 uint32_t tx_bytes_lo; /* TX Bytes sent */
3530 uint32_t tx_bytes_hi; /* TX Bytes sent */
3531 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled.
3532 1:1 bit for link good,
3533 2:1 Set if link changed between last poll. */
3534 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */
3535 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */
3536 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */
3537 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */
3538};
3539
3540
3541#define BCM_5710_FW_MAJOR_VERSION 7
3542#define BCM_5710_FW_MINOR_VERSION 13
3543#define BCM_5710_FW_REVISION_VERSION 1
3544#define BCM_5710_FW_ENGINEERING_VERSION 0
3545#define BCM_5710_FW_COMPILE_FLAGS 1
3546
3547
3548/*
3549 * attention bits $$KEEP_ENDIANNESS$$
3550 */
3551struct atten_sp_status_block
3552{
3553 uint32_t attn_bits /* 16 bit of attention signal lines */;
3554 uint32_t attn_bits_ack /* 16 bit of attention signal ack */;
3555 uint8_t status_block_id /* status block id */;
3556 uint8_t reserved0 /* resreved for padding */;
3557 uint16_t attn_bits_index /* attention bits running index */;
3558 uint32_t reserved1 /* resreved for padding */;
3559};
3560
3561
3562/*
3563 * The eth aggregative context of Cstorm
3564 */
3565struct cstorm_eth_ag_context
3566{
3567 uint32_t __reserved0[10];
3568};
3569
3570
3571/*
3572 * The iscsi aggregative context of Cstorm
3573 */
3574struct cstorm_iscsi_ag_context
3575{
3576 uint32_t agg_vars1;
3577 #define CSTORM_ISCSI_AG_CONTEXT_STATE (0xFF<<0) /* BitField agg_vars1Various aggregative variables The state of the connection */
3578 #define CSTORM_ISCSI_AG_CONTEXT_STATE_SHIFT 0
3579 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<8) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
3580 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 8
3581 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<9) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
3582 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 9
3583 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<10) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
3584 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 10
3585 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<11) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
3586 #define __CSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 11
3587 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN (0x1<<12) /* BitField agg_vars1Various aggregative variables ULP Rx SE counter flag enable */
3588 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_SE_CF_EN_SHIFT 12
3589 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN (0x1<<13) /* BitField agg_vars1Various aggregative variables ULP Rx invalidate counter flag enable */
3590 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED_ULP_RX_INV_CF_EN_SHIFT 13
3591 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF (0x3<<14) /* BitField agg_vars1Various aggregative variables Aux 4 counter flag */
3592 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_SHIFT 14
3593 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66 (0x3<<16) /* BitField agg_vars1Various aggregative variables The connection QOS */
3594 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED66_SHIFT 16
3595 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN (0x1<<18) /* BitField agg_vars1Various aggregative variables Enable decision rule for fin_received_cf */
3596 #define __CSTORM_ISCSI_AG_CONTEXT_FIN_RECEIVED_CF_EN_SHIFT 18
3597 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<19) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 1 */
3598 #define __CSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 19
3599 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN (0x1<<20) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 2 */
3600 #define __CSTORM_ISCSI_AG_CONTEXT_AUX2_CF_EN_SHIFT 20
3601 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<21) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 3 */
3602 #define __CSTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 21
3603 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN (0x1<<22) /* BitField agg_vars1Various aggregative variables Enable decision rule for auxiliary counter flag 4 */
3604 #define __CSTORM_ISCSI_AG_CONTEXT_AUX4_CF_EN_SHIFT 22
3605 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE (0x7<<23) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ, 3-GT, 4-GE, 5-LS, 6-LE */
3606 #define __CSTORM_ISCSI_AG_CONTEXT_REL_SEQ_RULE_SHIFT 23
3607 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE (0x3<<26) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
3608 #define CSTORM_ISCSI_AG_CONTEXT_HQ_PROD_RULE_SHIFT 26
3609 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52 (0x3<<28) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
3610 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED52_SHIFT 28
3611 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53 (0x3<<30) /* BitField agg_vars1Various aggregative variables 0-NOP, 1-EQ, 2-NEQ */
3612 #define __CSTORM_ISCSI_AG_CONTEXT_RESERVED53_SHIFT 30
3613#if defined(__BIG_ENDIAN)
3614 uint8_t __aux1_th /* Aux1 threhsold for the decision */;
3615 uint8_t __aux1_val /* Aux1 aggregation value */;
3616 uint16_t __agg_vars2 /* Various aggregative variables*/;
3617#elif defined(__LITTLE_ENDIAN)
3618 uint16_t __agg_vars2 /* Various aggregative variables*/;
3619 uint8_t __aux1_val /* Aux1 aggregation value */;
3620 uint8_t __aux1_th /* Aux1 threhsold for the decision */;
3621#endif
3622 uint32_t rel_seq /* The sequence to release */;
3623 uint32_t rel_seq_th /* The threshold for the released sequence */;
3624#if defined(__BIG_ENDIAN)
3625 uint16_t hq_cons /* The HQ Consumer */;
3626 uint16_t hq_prod /* The HQ producer */;
3627#elif defined(__LITTLE_ENDIAN)
3628 uint16_t hq_prod /* The HQ producer */;
3629 uint16_t hq_cons /* The HQ Consumer */;
3630#endif
3631#if defined(__BIG_ENDIAN)
3632 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */;
3633 uint8_t __reserved61 /* General flags */;
3634 uint8_t __reserved60 /* ORQ consumer updated by the completor */;
3635 uint8_t __reserved59 /* ORQ ULP Rx consumer */;
3636#elif defined(__LITTLE_ENDIAN)
3637 uint8_t __reserved59 /* ORQ ULP Rx consumer */;
3638 uint8_t __reserved60 /* ORQ consumer updated by the completor */;
3639 uint8_t __reserved61 /* General flags */;
3640 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */;
3641#endif
3642#if defined(__BIG_ENDIAN)
3643 uint16_t __reserved64 /* RQ consumer kept by the completor */;
3644 uint16_t cq_u_prod /* Ustorm producer of CQ */;
3645#elif defined(__LITTLE_ENDIAN)
3646 uint16_t cq_u_prod /* Ustorm producer of CQ */;
3647 uint16_t __reserved64 /* RQ consumer kept by the completor */;
3648#endif
3649 uint32_t __cq_u_prod1 /* Ustorm producer of CQ 1 */;
3650#if defined(__BIG_ENDIAN)
3651 uint16_t __agg_vars3 /* Various aggregative variables*/;
3652 uint16_t cq_u_pend /* Ustorm pending completions of CQ */;
3653#elif defined(__LITTLE_ENDIAN)
3654 uint16_t cq_u_pend /* Ustorm pending completions of CQ */;
3655 uint16_t __agg_vars3 /* Various aggregative variables*/;
3656#endif
3657#if defined(__BIG_ENDIAN)
3658 uint16_t __aux2_th /* Aux2 threhsold for the decision */;
3659 uint16_t aux2_val /* Aux2 aggregation value */;
3660#elif defined(__LITTLE_ENDIAN)
3661 uint16_t aux2_val /* Aux2 aggregation value */;
3662 uint16_t __aux2_th /* Aux2 threhsold for the decision */;
3663#endif
3664};
3665
3666
3667/*
3668 * The toe aggregative context of Cstorm
3669 */
3670struct cstorm_toe_ag_context
3671{
3672 uint32_t __agg_vars1 /* Various aggregative variables*/;
3673#if defined(__BIG_ENDIAN)
3674 uint8_t __aux1_th /* Aux1 threhsold for the decision */;
3675 uint8_t __aux1_val /* Aux1 aggregation value */;
3676 uint16_t __agg_vars2 /* Various aggregative variables*/;
3677#elif defined(__LITTLE_ENDIAN)
3678 uint16_t __agg_vars2 /* Various aggregative variables*/;
3679 uint8_t __aux1_val /* Aux1 aggregation value */;
3680 uint8_t __aux1_th /* Aux1 threhsold for the decision */;
3681#endif
3682 uint32_t rel_seq /* The sequence to release */;
3683 uint32_t __rel_seq_threshold /* The threshold for the released sequence */;
3684#if defined(__BIG_ENDIAN)
3685 uint16_t __reserved58 /* The HQ Consumer */;
3686 uint16_t bd_prod /* The HQ producer */;
3687#elif defined(__LITTLE_ENDIAN)
3688 uint16_t bd_prod /* The HQ producer */;
3689 uint16_t __reserved58 /* The HQ Consumer */;
3690#endif
3691#if defined(__BIG_ENDIAN)
3692 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */;
3693 uint8_t __reserved61 /* General flags */;
3694 uint8_t __reserved60 /* ORQ consumer updated by the completor */;
3695 uint8_t __completion_opcode /* ORQ ULP Rx consumer */;
3696#elif defined(__LITTLE_ENDIAN)
3697 uint8_t __completion_opcode /* ORQ ULP Rx consumer */;
3698 uint8_t __reserved60 /* ORQ consumer updated by the completor */;
3699 uint8_t __reserved61 /* General flags */;
3700 uint8_t __reserved62 /* Mask value for the decision algorithm of the general flags */;
3701#endif
3702#if defined(__BIG_ENDIAN)
3703 uint16_t __reserved64 /* RQ consumer kept by the completor */;
3704 uint16_t __reserved63 /* RQ consumer updated by the ULP RX */;
3705#elif defined(__LITTLE_ENDIAN)
3706 uint16_t __reserved63 /* RQ consumer updated by the ULP RX */;
3707 uint16_t __reserved64 /* RQ consumer kept by the completor */;
3708#endif
3709 uint32_t snd_max /* The ACK sequence number received in the last completed DDP */;
3710#if defined(__BIG_ENDIAN)
3711 uint16_t __agg_vars3 /* Various aggregative variables*/;
3712 uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the the USTORM encountered */;
3713#elif defined(__LITTLE_ENDIAN)
3714 uint16_t __reserved67 /* A counter for the number of RQ WQEs with invalidate the the USTORM encountered */;
3715 uint16_t __agg_vars3 /* Various aggregative variables*/;
3716#endif
3717#if defined(__BIG_ENDIAN)
3718 uint16_t __aux2_th /* Aux2 threhsold for the decision */;
3719 uint16_t __aux2_val /* Aux2 aggregation value */;
3720#elif defined(__LITTLE_ENDIAN)
3721 uint16_t __aux2_val /* Aux2 aggregation value */;
3722 uint16_t __aux2_th /* Aux2 threhsold for the decision */;
3723#endif
3724};
3725
3726
3727/*
3728 * dmae command structure
3729 */
3730struct dmae_cmd
3731{
3732 uint32_t opcode;
3733 #define DMAE_CMD_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */
3734 #define DMAE_CMD_SRC_SHIFT 0
3735 #define DMAE_CMD_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */
3736 #define DMAE_CMD_DST_SHIFT 1
3737 #define DMAE_CMD_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */
3738 #define DMAE_CMD_C_DST_SHIFT 3
3739 #define DMAE_CMD_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */
3740 #define DMAE_CMD_C_TYPE_ENABLE_SHIFT 4
3741 #define DMAE_CMD_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */
3742 #define DMAE_CMD_C_TYPE_CRC_ENABLE_SHIFT 5
3743 #define DMAE_CMD_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */
3744 #define DMAE_CMD_C_TYPE_CRC_OFFSET_SHIFT 6
3745 #define DMAE_CMD_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */
3746 #define DMAE_CMD_ENDIANITY_SHIFT 9
3747 #define DMAE_CMD_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */
3748 #define DMAE_CMD_PORT_SHIFT 11
3749 #define DMAE_CMD_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */
3750 #define DMAE_CMD_CRC_RESET_SHIFT 12
3751 #define DMAE_CMD_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */
3752 #define DMAE_CMD_SRC_RESET_SHIFT 13
3753 #define DMAE_CMD_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */
3754 #define DMAE_CMD_DST_RESET_SHIFT 14
3755 #define DMAE_CMD_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */
3756 #define DMAE_CMD_E1HVN_SHIFT 15
3757 #define DMAE_CMD_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */
3758 #define DMAE_CMD_DST_VN_SHIFT 17
3759 #define DMAE_CMD_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */
3760 #define DMAE_CMD_C_FUNC_SHIFT 19
3761 #define DMAE_CMD_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */
3762 #define DMAE_CMD_ERR_POLICY_SHIFT 20
3763 #define DMAE_CMD_RESERVED0 (0x3FF<<22) /* BitField opcode */
3764 #define DMAE_CMD_RESERVED0_SHIFT 22
3765 uint32_t src_addr_lo /* source address low/grc address */;
3766 uint32_t src_addr_hi /* source address hi */;
3767 uint32_t dst_addr_lo /* dest address low/grc address */;
3768 uint32_t dst_addr_hi /* dest address hi */;
3769#if defined(__BIG_ENDIAN)
3770 uint16_t opcode_iov;
3771 #define DMAE_CMD_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
3772 #define DMAE_CMD_SRC_VFID_SHIFT 0
3773 #define DMAE_CMD_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
3774 #define DMAE_CMD_SRC_VFPF_SHIFT 6
3775 #define DMAE_CMD_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3776 #define DMAE_CMD_RESERVED1_SHIFT 7
3777 #define DMAE_CMD_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
3778 #define DMAE_CMD_DST_VFID_SHIFT 8
3779 #define DMAE_CMD_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
3780 #define DMAE_CMD_DST_VFPF_SHIFT 14
3781 #define DMAE_CMD_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3782 #define DMAE_CMD_RESERVED2_SHIFT 15
3783 uint16_t len /* copy length */;
3784#elif defined(__LITTLE_ENDIAN)
3785 uint16_t len /* copy length */;
3786 uint16_t opcode_iov;
3787 #define DMAE_CMD_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */
3788 #define DMAE_CMD_SRC_VFID_SHIFT 0
3789 #define DMAE_CMD_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */
3790 #define DMAE_CMD_SRC_VFPF_SHIFT 6
3791 #define DMAE_CMD_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3792 #define DMAE_CMD_RESERVED1_SHIFT 7
3793 #define DMAE_CMD_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */
3794 #define DMAE_CMD_DST_VFID_SHIFT 8
3795 #define DMAE_CMD_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */
3796 #define DMAE_CMD_DST_VFPF_SHIFT 14
3797 #define DMAE_CMD_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */
3798 #define DMAE_CMD_RESERVED2_SHIFT 15
3799#endif
3800 uint32_t comp_addr_lo /* completion address low/grc address */;
3801 uint32_t comp_addr_hi /* completion address hi */;
3802 uint32_t comp_val /* value to write to completion address */;
3803 uint32_t crc32 /* crc32 result */;
3804 uint32_t crc32_c /* crc32_c result */;
3805#if defined(__BIG_ENDIAN)
3806 uint16_t crc16_c /* crc16_c result */;
3807 uint16_t crc16 /* crc16 result */;
3808#elif defined(__LITTLE_ENDIAN)
3809 uint16_t crc16 /* crc16 result */;
3810 uint16_t crc16_c /* crc16_c result */;
3811#endif
3812#if defined(__BIG_ENDIAN)
3813 uint16_t reserved3;
3814 uint16_t crc_t10 /* crc_t10 result */;
3815#elif defined(__LITTLE_ENDIAN)
3816 uint16_t crc_t10 /* crc_t10 result */;
3817 uint16_t reserved3;
3818#endif
3819#if defined(__BIG_ENDIAN)
3820 uint16_t xsum8 /* checksum8 result */;
3821 uint16_t xsum16 /* checksum16 result */;
3822#elif defined(__LITTLE_ENDIAN)
3823 uint16_t xsum16 /* checksum16 result */;
3824 uint16_t xsum8 /* checksum8 result */;
3825#endif
3826};
3827
3828
3829/*
3830 * common data for all protocols
3831 */
3832struct doorbell_hdr_t
3833{
3834 uint8_t data;
3835 #define DOORBELL_HDR_T_RX (0x1<<0) /* BitField data 1 for rx doorbell, 0 for tx doorbell */
3836 #define DOORBELL_HDR_T_RX_SHIFT 0
3837 #define DOORBELL_HDR_T_DB_TYPE (0x1<<1) /* BitField data 0 for normal doorbell, 1 for advertise wnd doorbell */
3838 #define DOORBELL_HDR_T_DB_TYPE_SHIFT 1
3839 #define DOORBELL_HDR_T_DPM_SIZE (0x3<<2) /* BitField data rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */
3840 #define DOORBELL_HDR_T_DPM_SIZE_SHIFT 2
3841 #define DOORBELL_HDR_T_CONN_TYPE (0xF<<4) /* BitField data connection type */
3842 #define DOORBELL_HDR_T_CONN_TYPE_SHIFT 4
3843};
3844
3845/*
3846 * Ethernet doorbell
3847 */
3848struct eth_tx_doorbell
3849{
3850#if defined(__BIG_ENDIAN)
3851 uint16_t npackets /* number of data bytes that were added in the doorbell */;
3852 uint8_t params;
3853 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
3854 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3855 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
3856 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3857 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
3858 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3859 struct doorbell_hdr_t hdr;
3860#elif defined(__LITTLE_ENDIAN)
3861 struct doorbell_hdr_t hdr;
3862 uint8_t params;
3863 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
3864 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0
3865 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
3866 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
3867 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
3868 #define ETH_TX_DOORBELL_SPARE_SHIFT 7
3869 uint16_t npackets /* number of data bytes that were added in the doorbell */;
3870#endif
3871};
3872
3873
3874/*
3875 * 3 lines. status block $$KEEP_ENDIANNESS$$
3876 */
3877struct hc_status_block_e1x
3878{
3879 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */;
3880 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
3881 uint32_t rsrv[11];
3882};
3883
3884/*
3885 * host status block
3886 */
3887struct host_hc_status_block_e1x
3888{
3889 struct hc_status_block_e1x sb /* fast path indices */;
3890};
3891
3892
3893/*
3894 * 3 lines. status block $$KEEP_ENDIANNESS$$
3895 */
3896struct hc_status_block_e2
3897{
3898 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */;
3899 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */;
3900 uint32_t reserved[11];
3901};
3902
3903/*
3904 * host status block
3905 */
3906struct host_hc_status_block_e2
3907{
3908 struct hc_status_block_e2 sb /* fast path indices */;
3909};
3910
3911
3912/*
3913 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$
3914 */
3915struct hc_sp_status_block
3916{
3917 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */;
3918 uint16_t running_index /* Status Block running index */;
3919 uint16_t rsrv;
3920 uint32_t rsrv1;
3921};
3922
3923/*
3924 * host status block
3925 */
3926struct host_sp_status_block
3927{
3928 struct atten_sp_status_block atten_status_block /* attention bits section */;
3929 struct hc_sp_status_block sp_sb /* slow path indices */;
3930};
3931
3932
3933/*
3934 * IGU driver acknowledgment register
3935 */
3936struct igu_ack_register
3937{
3938#if defined(__BIG_ENDIAN)
3939 uint16_t sb_id_and_flags;
3940 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
3941 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3942 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3943 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3944 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
3945 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3946 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3947 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3948 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
3949 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3950 uint16_t status_block_index /* status block index acknowledgement */;
3951#elif defined(__LITTLE_ENDIAN)
3952 uint16_t status_block_index /* status block index acknowledgement */;
3953 uint16_t sb_id_and_flags;
3954 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */
3955 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0
3956 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3957 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5
3958 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */
3959 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8
3960 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3961 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9
3962 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */
3963 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11
3964#endif
3965};
3966
3967
3968/*
3969 * IGU driver acknowledgement register
3970 */
3971struct igu_backward_compatible
3972{
3973 uint32_t sb_id_and_flags;
3974 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */
3975 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0
3976 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */
3977 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16
3978 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */
3979 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21
3980 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */
3981 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24
3982 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */
3983 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25
3984 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */
3985 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27
3986 uint32_t reserved_2;
3987};
3988
3989
3990/*
3991 * IGU driver acknowledgement register
3992 */
3993struct igu_regular
3994{
3995 uint32_t sb_id_and_flags;
3996 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */
3997 #define IGU_REGULAR_SB_INDEX_SHIFT 0
3998 #define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */
3999 #define IGU_REGULAR_RESERVED0_SHIFT 20
4000 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */
4001 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21
4002 #define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */
4003 #define IGU_REGULAR_BUPDATE_SHIFT 24
4004 #define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */
4005 #define IGU_REGULAR_ENABLE_INT_SHIFT 25
4006 #define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */
4007 #define IGU_REGULAR_RESERVED_1_SHIFT 27
4008 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */
4009 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28
4010 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */
4011 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30
4012 #define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */
4013 #define IGU_REGULAR_BCLEANUP_SHIFT 31
4014 uint32_t reserved_2;
4015};
4016
4017/*
4018 * IGU driver acknowledgement register
4019 */
4020union igu_consprod_reg
4021{
4022 struct igu_regular regular;
4023 struct igu_backward_compatible backward_compatible;
4024};
4025
4026
4027/*
4028 * Igu control commands
4029 */
4030enum igu_ctrl_cmd
4031{
4032 IGU_CTRL_CMD_TYPE_RD,
4033 IGU_CTRL_CMD_TYPE_WR,
4034 MAX_IGU_CTRL_CMD};
4035
4036
4037/*
4038 * Control register for the IGU command register
4039 */
4040struct igu_ctrl_reg
4041{
4042 uint32_t ctrl_data;
4043 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */
4044 #define IGU_CTRL_REG_ADDRESS_SHIFT 0
4045 #define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */
4046 #define IGU_CTRL_REG_FID_SHIFT 12
4047 #define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */
4048 #define IGU_CTRL_REG_RESERVED_SHIFT 19
4049 #define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */
4050 #define IGU_CTRL_REG_TYPE_SHIFT 20
4051 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */
4052 #define IGU_CTRL_REG_UNUSED_SHIFT 21
4053};
4054
4055
4056/*
4057 * Igu interrupt command
4058 */
4059enum igu_int_cmd
4060{
4061 IGU_INT_ENABLE,
4062 IGU_INT_DISABLE,
4063 IGU_INT_NOP,
4064 IGU_INT_NOP2,
4065 MAX_IGU_INT_CMD};
4066
4067
4068/*
4069 * Igu segments
4070 */
4071enum igu_seg_access
4072{
4073 IGU_SEG_ACCESS_NORM,
4074 IGU_SEG_ACCESS_DEF,
4075 IGU_SEG_ACCESS_ATTN,
4076 MAX_IGU_SEG_ACCESS};
4077
4078
4079/*
4080 * iscsi doorbell
4081 */
4082struct iscsi_tx_doorbell
4083{
4084#if defined(__BIG_ENDIAN)
4085 uint16_t reserved /* number of data bytes that were added in the doorbell */;
4086 uint8_t params;
4087 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
4088 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4089 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
4090 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
4091 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
4092 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
4093 struct doorbell_hdr_t hdr;
4094#elif defined(__LITTLE_ENDIAN)
4095 struct doorbell_hdr_t hdr;
4096 uint8_t params;
4097 #define ISCSI_TX_DOORBELL_NUM_WQES (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
4098 #define ISCSI_TX_DOORBELL_NUM_WQES_SHIFT 0
4099 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
4100 #define ISCSI_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6
4101 #define ISCSI_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */
4102 #define ISCSI_TX_DOORBELL_SPARE_SHIFT 7
4103 uint16_t reserved /* number of data bytes that were added in the doorbell */;
4104#endif
4105};
4106
4107
4108/*
4109 * Parser parsing flags field
4110 */
4111struct parsing_flags
4112{
4113 uint16_t flags;
4114 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */
4115 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0
4116 #define PARSING_FLAGS_INNER_VLAN_EXIST (0x1<<1) /* BitField flagscontext flags 0 or 1 */
4117 #define PARSING_FLAGS_INNER_VLAN_EXIST_SHIFT 1
4118 #define PARSING_FLAGS_OUTER_VLAN_EXIST (0x1<<2) /* BitField flagscontext flags 0 or 1 */
4119 #define PARSING_FLAGS_OUTER_VLAN_EXIST_SHIFT 2
4120 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */
4121 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3
4122 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */
4123 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5
4124 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */
4125 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6
4126 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */
4127 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7
4128 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */
4129 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9
4130 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */
4131 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10
4132 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */
4133 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11
4134 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */
4135 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12
4136 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */
4137 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13
4138 #define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */
4139 #define PARSING_FLAGS_RESERVED0_SHIFT 14
4140};
4141
4142
4143/*
4144 * Parsing flags for TCP ACK type
4145 */
4146enum prs_flags_ack_type
4147{
4148 PRS_FLAG_PUREACK_PIGGY,
4149 PRS_FLAG_PUREACK_PURE,
4150 MAX_PRS_FLAGS_ACK_TYPE};
4151
4152
4153/*
4154 * Parsing flags for Ethernet address type
4155 */
4156enum prs_flags_eth_addr_type
4157{
4158 PRS_FLAG_ETHTYPE_NON_UNICAST,
4159 PRS_FLAG_ETHTYPE_UNICAST,
4160 MAX_PRS_FLAGS_ETH_ADDR_TYPE};
4161
4162
4163/*
4164 * Parsing flags for over-ethernet protocol
4165 */
4166enum prs_flags_over_eth
4167{
4168 PRS_FLAG_OVERETH_UNKNOWN,
4169 PRS_FLAG_OVERETH_IPV4,
4170 PRS_FLAG_OVERETH_IPV6,
4171 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN,
4172 MAX_PRS_FLAGS_OVER_ETH};
4173
4174
4175/*
4176 * Parsing flags for over-IP protocol
4177 */
4178enum prs_flags_over_ip
4179{
4180 PRS_FLAG_OVERIP_UNKNOWN,
4181 PRS_FLAG_OVERIP_TCP,
4182 PRS_FLAG_OVERIP_UDP,
4183 MAX_PRS_FLAGS_OVER_IP};
4184
4185
4186/*
4187 * SDM operation gen command (generate aggregative interrupt)
4188 */
4189struct sdm_op_gen
4190{
4191 uint32_t command;
4192 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */
4193 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0
4194 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */
4195 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5
4196 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */
4197 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8
4198 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */
4199 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16
4200 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */
4201 #define SDM_OP_GEN_RESERVED_SHIFT 17
4202};
4203
4204
4205/*
4206 * Timers connection context
4207 */
4208struct timers_block_context
4209{
4210 uint32_t __client0 /* data of client 0 of the timers block*/;
4211 uint32_t __client1 /* data of client 1 of the timers block*/;
4212 uint32_t __client2 /* data of client 2 of the timers block*/;
4213 uint32_t flags;
4214 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */
4215 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0
4216 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */
4217 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2
4218 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */
4219 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3
4220};
4221
4222
4223/*
4224 * advertise window doorbell
4225 */
4226struct toe_adv_wnd_doorbell
4227{
4228#if defined(__BIG_ENDIAN)
4229 uint16_t wnd_sz_lsb /* Less significant bits of advertise window update value */;
4230 uint8_t wnd_sz_msb /* Most significant bits of advertise window update value */;
4231 struct doorbell_hdr_t hdr /* See description of the appropriate type */;
4232#elif defined(__LITTLE_ENDIAN)
4233 struct doorbell_hdr_t hdr /* See description of the appropriate type */;
4234 uint8_t wnd_sz_msb /* Most significant bits of advertise window update value */;
4235 uint16_t wnd_sz_lsb /* Less significant bits of advertise window update value */;
4236#endif
4237};
4238
4239
4240/*
4241 * toe rx BDs update doorbell
4242 */
4243struct toe_rx_bds_doorbell
4244{
4245#if defined(__BIG_ENDIAN)
4246 uint16_t nbds /* BDs update value */;
4247 uint8_t params;
4248 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* BitField params reserved */
4249 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4250 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params BDs update doorbell opcode (2) */
4251 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
4252 struct doorbell_hdr_t hdr;
4253#elif defined(__LITTLE_ENDIAN)
4254 struct doorbell_hdr_t hdr;
4255 uint8_t params;
4256 #define TOE_RX_BDS_DOORBELL_RESERVED (0x1F<<0) /* BitField params reserved */
4257 #define TOE_RX_BDS_DOORBELL_RESERVED_SHIFT 0
4258 #define TOE_RX_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params BDs update doorbell opcode (2) */
4259 #define TOE_RX_BDS_DOORBELL_OPCODE_SHIFT 5
4260 uint16_t nbds /* BDs update value */;
4261#endif
4262};
4263
4264
4265/*
4266 * toe rx bytes and BDs update doorbell
4267 */
4268struct toe_rx_bytes_and_bds_doorbell
4269{
4270#if defined(__BIG_ENDIAN)
4271 uint16_t nbytes /* nbytes */;
4272 uint8_t params;
4273 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* BitField params producer delta from the last doorbell */
4274 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4275 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes and BDs update doorbell opcode (1) */
4276 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
4277 struct doorbell_hdr_t hdr;
4278#elif defined(__LITTLE_ENDIAN)
4279 struct doorbell_hdr_t hdr;
4280 uint8_t params;
4281 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS (0x1F<<0) /* BitField params producer delta from the last doorbell */
4282 #define TOE_RX_BYTES_AND_BDS_DOORBELL_NBDS_SHIFT 0
4283 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes and BDs update doorbell opcode (1) */
4284 #define TOE_RX_BYTES_AND_BDS_DOORBELL_OPCODE_SHIFT 5
4285 uint16_t nbytes /* nbytes */;
4286#endif
4287};
4288
4289
4290/*
4291 * toe rx bytes doorbell
4292 */
4293struct toe_rx_byte_doorbell
4294{
4295#if defined(__BIG_ENDIAN)
4296 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4297 uint8_t params;
4298 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */
4299 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4300 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes doorbell opcode (0) */
4301 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
4302 struct doorbell_hdr_t hdr;
4303#elif defined(__LITTLE_ENDIAN)
4304 struct doorbell_hdr_t hdr;
4305 uint8_t params;
4306 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */
4307 #define TOE_RX_BYTE_DOORBELL_NBYTES_MSB_SHIFT 0
4308 #define TOE_RX_BYTE_DOORBELL_OPCODE (0x7<<5) /* BitField params rx bytes doorbell opcode (0) */
4309 #define TOE_RX_BYTE_DOORBELL_OPCODE_SHIFT 5
4310 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4311#endif
4312};
4313
4314
4315/*
4316 * toe rx consume GRQ doorbell
4317 */
4318struct toe_rx_grq_doorbell
4319{
4320#if defined(__BIG_ENDIAN)
4321 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4322 uint8_t params;
4323 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */
4324 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4325 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* BitField params rx GRQ doorbell opcode (4) */
4326 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
4327 struct doorbell_hdr_t hdr;
4328#elif defined(__LITTLE_ENDIAN)
4329 struct doorbell_hdr_t hdr;
4330 uint8_t params;
4331 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB (0x1F<<0) /* BitField params bits [20:16] of nbytes */
4332 #define TOE_RX_GRQ_DOORBELL_NBYTES_MSB_SHIFT 0
4333 #define TOE_RX_GRQ_DOORBELL_OPCODE (0x7<<5) /* BitField params rx GRQ doorbell opcode (4) */
4334 #define TOE_RX_GRQ_DOORBELL_OPCODE_SHIFT 5
4335 uint16_t nbytes_lsb /* bits [0:15] of nbytes */;
4336#endif
4337};
4338
4339
4340/*
4341 * toe doorbell
4342 */
4343struct toe_tx_doorbell
4344{
4345#if defined(__BIG_ENDIAN)
4346 uint16_t nbytes /* number of data bytes that were added in the doorbell */;
4347 uint8_t params;
4348 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
4349 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4350 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
4351 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
4352 #define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* BitField params doorbell queue spare flag */
4353 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7
4354 struct doorbell_hdr_t hdr;
4355#elif defined(__LITTLE_ENDIAN)
4356 struct doorbell_hdr_t hdr;
4357 uint8_t params;
4358 #define TOE_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */
4359 #define TOE_TX_DOORBELL_NUM_BDS_SHIFT 0
4360 #define TOE_TX_DOORBELL_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */
4361 #define TOE_TX_DOORBELL_TX_FIN_FLAG_SHIFT 6
4362 #define TOE_TX_DOORBELL_FLUSH (0x1<<7) /* BitField params doorbell queue spare flag */
4363 #define TOE_TX_DOORBELL_FLUSH_SHIFT 7
4364 uint16_t nbytes /* number of data bytes that were added in the doorbell */;
4365#endif
4366};
4367
4368
4369/*
4370 * The eth aggregative context of Tstorm
4371 */
4372struct tstorm_eth_ag_context
4373{
4374 uint32_t __reserved0[14];
4375};
4376
4377
4378/*
4379 * The fcoe extra aggregative context section of Tstorm
4380 */
4381struct tstorm_fcoe_extra_ag_context_section
4382{
4383 uint32_t __agg_val1 /* aggregated value 1 */;
4384#if defined(__BIG_ENDIAN)
4385 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4386 uint8_t __agg_val3 /* aggregated value 3 */;
4387 uint16_t __agg_val2 /* aggregated value 2 */;
4388#elif defined(__LITTLE_ENDIAN)
4389 uint16_t __agg_val2 /* aggregated value 2 */;
4390 uint8_t __agg_val3 /* aggregated value 3 */;
4391 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4392#endif
4393#if defined(__BIG_ENDIAN)
4394 uint16_t __agg_val5;
4395 uint8_t __agg_val6;
4396 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4397#elif defined(__LITTLE_ENDIAN)
4398 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4399 uint8_t __agg_val6;
4400 uint16_t __agg_val5;
4401#endif
4402 uint32_t __lcq_prod /* Next sequence number to transmit, given by Tx */;
4403 uint32_t rtt_seq /* Rtt recording sequence number */;
4404 uint32_t rtt_time /* Rtt recording real time clock */;
4405 uint32_t __reserved66;
4406 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */;
4407 uint32_t tcp_agg_vars1;
4408 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */
4409 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4410 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */
4411 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4412 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */
4413 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4414 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */
4415 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4416 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */
4417 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4418 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */
4419 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4420 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */
4421 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4422 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */
4423 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_LCQ_SND_EN_SHIFT 9
4424 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */
4425 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4426 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */
4427 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4428 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */
4429 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4430 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */
4431 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4432 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */
4433 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4434 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */
4435 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4436 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */
4437 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4438 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */
4439 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4440 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */
4441 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4442 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */
4443 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4444 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */
4445 #define __TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4446 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */
4447 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4448 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */
4449 #define TSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4450 uint32_t snd_max /* Maximum sequence number that was ever transmitted */;
4451 uint32_t __lcq_cons /* Last ACK sequence number sent by the Tx */;
4452 uint32_t __reserved2;
4453};
4454
4455/*
4456 * The fcoe aggregative context of Tstorm
4457 */
4458struct tstorm_fcoe_ag_context
4459{
4460#if defined(__BIG_ENDIAN)
4461 uint16_t ulp_credit;
4462 uint8_t agg_vars1;
4463 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4464 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4465 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4466 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4467 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4468 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4469 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4470 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4471 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4472 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
4473 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4474 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4475 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4476 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4477 uint8_t state /* The state of the connection */;
4478#elif defined(__LITTLE_ENDIAN)
4479 uint8_t state /* The state of the connection */;
4480 uint8_t agg_vars1;
4481 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4482 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4483 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4484 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4485 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4486 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4487 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4488 #define TSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4489 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4490 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_SHIFT 4
4491 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4492 #define __TSTORM_FCOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4493 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4494 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4495 uint16_t ulp_credit;
4496#endif
4497#if defined(__BIG_ENDIAN)
4498 uint16_t __agg_val4;
4499 uint16_t agg_vars2;
4500 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4501 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4502 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4503 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4504 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4505 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4506 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4507 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4508 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4509 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4510 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4511 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4512 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4513 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4514 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4515 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
4516 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4517 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
4518 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4519 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
4520 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4521 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4522 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4523 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4524#elif defined(__LITTLE_ENDIAN)
4525 uint16_t agg_vars2;
4526 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4527 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4528 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4529 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4530 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4531 #define __TSTORM_FCOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4532 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4533 #define __TSTORM_FCOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4534 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4535 #define __TSTORM_FCOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4536 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4537 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4538 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4539 #define __TSTORM_FCOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4540 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4541 #define __TSTORM_FCOE_AG_CONTEXT_QUEUE0_FLUSH_CF_EN_SHIFT 11
4542 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4543 #define TSTORM_FCOE_AG_CONTEXT_AUX4_CF_EN_SHIFT 12
4544 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4545 #define TSTORM_FCOE_AG_CONTEXT_AUX5_CF_EN_SHIFT 13
4546 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4547 #define TSTORM_FCOE_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4548 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4549 #define TSTORM_FCOE_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4550 uint16_t __agg_val4;
4551#endif
4552 struct tstorm_fcoe_extra_ag_context_section __extra_section /* Extra context section */;
4553};
4554
4555
4556/*
4557 * The iscsi aggregative context section of Tstorm
4558 */
4559struct tstorm_iscsi_tcp_ag_context_section
4560{
4561 uint32_t __agg_val1 /* aggregated value 1 */;
4562#if defined(__BIG_ENDIAN)
4563 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4564 uint8_t __agg_val3 /* aggregated value 3 */;
4565 uint16_t __agg_val2 /* aggregated value 2 */;
4566#elif defined(__LITTLE_ENDIAN)
4567 uint16_t __agg_val2 /* aggregated value 2 */;
4568 uint8_t __agg_val3 /* aggregated value 3 */;
4569 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4570#endif
4571#if defined(__BIG_ENDIAN)
4572 uint16_t __agg_val5;
4573 uint8_t __agg_val6;
4574 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4575#elif defined(__LITTLE_ENDIAN)
4576 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4577 uint8_t __agg_val6;
4578 uint16_t __agg_val5;
4579#endif
4580 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */;
4581 uint32_t rtt_seq /* Rtt recording sequence number */;
4582 uint32_t rtt_time /* Rtt recording real time clock */;
4583 uint32_t wnd_right_edge_local;
4584 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */;
4585 uint32_t tcp_agg_vars1;
4586 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */
4587 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4588 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */
4589 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4590 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */
4591 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4592 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */
4593 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4594 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */
4595 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4596 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */
4597 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4598 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */
4599 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4600 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */
4601 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4602 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */
4603 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4604 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */
4605 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4606 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */
4607 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4608 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */
4609 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4610 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */
4611 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4612 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */
4613 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4614 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */
4615 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4616 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */
4617 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4618 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */
4619 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4620 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */
4621 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4622 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */
4623 #define __TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4624 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */
4625 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4626 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */
4627 #define TSTORM_ISCSI_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4628 uint32_t snd_max /* Maximum sequence number that was ever transmitted */;
4629 uint32_t snd_una /* Last ACK sequence number sent by the Tx */;
4630 uint32_t __reserved2;
4631};
4632
4633/*
4634 * The iscsi aggregative context of Tstorm
4635 */
4636struct tstorm_iscsi_ag_context
4637{
4638#if defined(__BIG_ENDIAN)
4639 uint16_t ulp_credit;
4640 uint8_t agg_vars1;
4641 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4642 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4643 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4644 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4645 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4646 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4647 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4648 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4649 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4650 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4651 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4652 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4653 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4654 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
4655 uint8_t state /* The state of the connection */;
4656#elif defined(__LITTLE_ENDIAN)
4657 uint8_t state /* The state of the connection */;
4658 uint8_t agg_vars1;
4659 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4660 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4661 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4662 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
4663 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4664 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
4665 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4666 #define TSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
4667 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4668 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4669 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4670 #define __TSTORM_ISCSI_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4671 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4672 #define __TSTORM_ISCSI_AG_CONTEXT_ACK_ON_FIN_SENT_FLAG_SHIFT 7
4673 uint16_t ulp_credit;
4674#endif
4675#if defined(__BIG_ENDIAN)
4676 uint16_t __agg_val4;
4677 uint16_t agg_vars2;
4678 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4679 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4680 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4681 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
4682 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4683 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
4684 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4685 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
4686 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4687 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
4688 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4689 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
4690 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4691 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4692 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4693 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4694 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4695 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
4696 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4697 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
4698 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4699 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4700 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4701 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4702#elif defined(__LITTLE_ENDIAN)
4703 uint16_t agg_vars2;
4704 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4705 #define __TSTORM_ISCSI_AG_CONTEXT_MSL_TIMER_SET_FLAG_SHIFT 0
4706 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4707 #define __TSTORM_ISCSI_AG_CONTEXT_FIN_SENT_FIRST_FLAG_SHIFT 1
4708 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4709 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_SHIFT 2
4710 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4711 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_SHIFT 4
4712 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4713 #define __TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_SHIFT 6
4714 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4715 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_SHIFT 8
4716 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4717 #define __TSTORM_ISCSI_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4718 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4719 #define __TSTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4720 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4721 #define __TSTORM_ISCSI_AG_CONTEXT_RST_SENT_CF_EN_SHIFT 12
4722 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4723 #define __TSTORM_ISCSI_AG_CONTEXT_WAKEUP_CALL_CF_EN_SHIFT 13
4724 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4725 #define TSTORM_ISCSI_AG_CONTEXT_AUX6_CF_EN_SHIFT 14
4726 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4727 #define TSTORM_ISCSI_AG_CONTEXT_AUX7_CF_EN_SHIFT 15
4728 uint16_t __agg_val4;
4729#endif
4730 struct tstorm_iscsi_tcp_ag_context_section tcp /* TCP context section, shared in TOE and iSCSI */;
4731};
4732
4733
4734/*
4735 * The tcp aggregative context section of Tstorm
4736 */
4737struct tstorm_tcp_tcp_ag_context_section
4738{
4739 uint32_t __agg_val1 /* aggregated value 1 */;
4740#if defined(__BIG_ENDIAN)
4741 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4742 uint8_t __agg_val3 /* aggregated value 3 */;
4743 uint16_t __agg_val2 /* aggregated value 2 */;
4744#elif defined(__LITTLE_ENDIAN)
4745 uint16_t __agg_val2 /* aggregated value 2 */;
4746 uint8_t __agg_val3 /* aggregated value 3 */;
4747 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4748#endif
4749#if defined(__BIG_ENDIAN)
4750 uint16_t __agg_val5;
4751 uint8_t __agg_val6;
4752 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4753#elif defined(__LITTLE_ENDIAN)
4754 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4755 uint8_t __agg_val6;
4756 uint16_t __agg_val5;
4757#endif
4758 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */;
4759 uint32_t rtt_seq /* Rtt recording sequence number */;
4760 uint32_t rtt_time /* Rtt recording real time clock */;
4761 uint32_t __reserved66;
4762 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */;
4763 uint32_t tcp_agg_vars1;
4764 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */
4765 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4766 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */
4767 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4768 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */
4769 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_SHIFT 2
4770 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */
4771 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4772 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */
4773 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_WND_UPD_CF_EN_SHIFT 6
4774 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */
4775 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4776 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */
4777 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4778 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */
4779 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4780 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */
4781 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 10
4782 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */
4783 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_FLAG_SHIFT 11
4784 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */
4785 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_EN_SHIFT 12
4786 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */
4787 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_EN_SHIFT 13
4788 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */
4789 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_CF_SHIFT 14
4790 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */
4791 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX2_CF_SHIFT 16
4792 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */
4793 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4794 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */
4795 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4796 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */
4797 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4798 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */
4799 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4800 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */
4801 #define __TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4802 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */
4803 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4804 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */
4805 #define TSTORM_TCP_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4806 uint32_t snd_max /* Maximum sequence number that was ever transmitted */;
4807 uint32_t snd_una /* Last ACK sequence number sent by the Tx */;
4808 uint32_t __reserved2;
4809};
4810
4811
4812/*
4813 * The toe aggregative context section of Tstorm
4814 */
4815struct tstorm_toe_tcp_ag_context_section
4816{
4817 uint32_t __agg_val1 /* aggregated value 1 */;
4818#if defined(__BIG_ENDIAN)
4819 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4820 uint8_t __agg_val3 /* aggregated value 3 */;
4821 uint16_t __agg_val2 /* aggregated value 2 */;
4822#elif defined(__LITTLE_ENDIAN)
4823 uint16_t __agg_val2 /* aggregated value 2 */;
4824 uint8_t __agg_val3 /* aggregated value 3 */;
4825 uint8_t __tcp_agg_vars2 /* Various aggregative variables*/;
4826#endif
4827#if defined(__BIG_ENDIAN)
4828 uint16_t __agg_val5;
4829 uint8_t __agg_val6;
4830 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4831#elif defined(__LITTLE_ENDIAN)
4832 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
4833 uint8_t __agg_val6;
4834 uint16_t __agg_val5;
4835#endif
4836 uint32_t snd_nxt /* Next sequence number to transmit, given by Tx */;
4837 uint32_t rtt_seq /* Rtt recording sequence number */;
4838 uint32_t rtt_time /* Rtt recording real time clock */;
4839 uint32_t __reserved66;
4840 uint32_t wnd_right_edge /* The right edge of the receive window. Updated by the XSTORM when a segment with ACK is transmitted */;
4841 uint32_t tcp_agg_vars1;
4842 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<0) /* BitField tcp_agg_vars1Various aggregative variables Sticky bit that is set when FIN is sent and remains set */
4843 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 0
4844 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG (0x1<<1) /* BitField tcp_agg_vars1Various aggregative variables The Tx indicates that it sent a FIN packet */
4845 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_LAST_PACKET_FIN_FLAG_SHIFT 1
4846 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52 (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables Counter flag to indicate a window update */
4847 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED52_SHIFT 2
4848 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables Indicates that a timeout expired */
4849 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_SHIFT 4
4850 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the WndUpd counter flag */
4851 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_WND_UPD_CF_EN_SHIFT 6
4852 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Enable the decision rule that considers the Timeout counter flag */
4853 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TIMEOUT_CF_EN_SHIFT 7
4854 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN (0x1<<8) /* BitField tcp_agg_vars1Various aggregative variables If 1 then the Rxmit sequence decision rule is enabled */
4855 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_SEQ_EN_SHIFT 8
4856 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN (0x1<<9) /* BitField tcp_agg_vars1Various aggregative variables If set then the SendNext decision rule is enabled */
4857 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_SND_NXT_EN_SHIFT 9
4858 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE (0x1<<10) /* BitField tcp_agg_vars1Various aggregative variables */
4859 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_NEWRTTSAMPLE_SHIFT 10
4860 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55 (0x1<<11) /* BitField tcp_agg_vars1Various aggregative variables */
4861 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED55_SHIFT 11
4862 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN (0x1<<12) /* BitField tcp_agg_vars1Various aggregative variables */
4863 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX1_CF_EN_SHIFT 12
4864 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN (0x1<<13) /* BitField tcp_agg_vars1Various aggregative variables */
4865 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED_AUX2_CF_EN_SHIFT 13
4866 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56 (0x3<<14) /* BitField tcp_agg_vars1Various aggregative variables */
4867 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED56_SHIFT 14
4868 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57 (0x3<<16) /* BitField tcp_agg_vars1Various aggregative variables */
4869 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED57_SHIFT 16
4870 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED (0x1<<18) /* BitField tcp_agg_vars1Various aggregative variables Indicates that Tx has more to send, but has not enough window to send it */
4871 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_BLOCKED_SHIFT 18
4872 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<19) /* BitField tcp_agg_vars1Various aggregative variables */
4873 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 19
4874 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN (0x1<<20) /* BitField tcp_agg_vars1Various aggregative variables */
4875 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_EN_SHIFT 20
4876 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN (0x1<<21) /* BitField tcp_agg_vars1Various aggregative variables */
4877 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_EN_SHIFT 21
4878 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1 (0x3<<22) /* BitField tcp_agg_vars1Various aggregative variables */
4879 #define __TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED1_SHIFT 22
4880 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ (0xF<<24) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or goto SS comand sent */
4881 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_PEND_SEQ_SHIFT 24
4882 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ (0xF<<28) /* BitField tcp_agg_vars1Various aggregative variables The sequence of the last fast retransmit or Goto SS command performed by the XSTORM */
4883 #define TSTORM_TOE_TCP_AG_CONTEXT_SECTION_RETRANSMIT_DONE_SEQ_SHIFT 28
4884 uint32_t snd_max /* Maximum sequence number that was ever transmitted */;
4885 uint32_t snd_una /* Last ACK sequence number sent by the Tx */;
4886 uint32_t __reserved2;
4887};
4888
4889/*
4890 * The toe aggregative context of Tstorm
4891 */
4892struct tstorm_toe_ag_context
4893{
4894#if defined(__BIG_ENDIAN)
4895 uint16_t reserved54;
4896 uint8_t agg_vars1;
4897 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4898 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4899 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4900 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
4901 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4902 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
4903 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4904 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
4905 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4906 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4907 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4908 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4909 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4910 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4911 uint8_t __state /* The state of the connection */;
4912#elif defined(__LITTLE_ENDIAN)
4913 uint8_t __state /* The state of the connection */;
4914 uint8_t agg_vars1;
4915 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
4916 #define TSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
4917 #define TSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
4918 #define TSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 1
4919 #define TSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
4920 #define TSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 2
4921 #define TSTORM_TOE_AG_CONTEXT_RESERVED53 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
4922 #define TSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 3
4923 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF (0x3<<4) /* BitField agg_vars1Various aggregative variables */
4924 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_SHIFT 4
4925 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables */
4926 #define __TSTORM_TOE_AG_CONTEXT_AUX3_FLAG_SHIFT 6
4927 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG (0x1<<7) /* BitField agg_vars1Various aggregative variables */
4928 #define __TSTORM_TOE_AG_CONTEXT_AUX4_FLAG_SHIFT 7
4929 uint16_t reserved54;
4930#endif
4931#if defined(__BIG_ENDIAN)
4932 uint16_t __agg_val4;
4933 uint16_t agg_vars2;
4934 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4935 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4936 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4937 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4938 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4939 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4940 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4941 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4942 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4943 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4944 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4945 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4946 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4947 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4948 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4949 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4950 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4951 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
4952 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4953 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
4954 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4955 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
4956 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4957 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
4958#elif defined(__LITTLE_ENDIAN)
4959 uint16_t agg_vars2;
4960 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG (0x1<<0) /* BitField agg_vars2Various aggregative variables */
4961 #define __TSTORM_TOE_AG_CONTEXT_AUX5_FLAG_SHIFT 0
4962 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG (0x1<<1) /* BitField agg_vars2Various aggregative variables */
4963 #define __TSTORM_TOE_AG_CONTEXT_AUX6_FLAG_SHIFT 1
4964 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF (0x3<<2) /* BitField agg_vars2Various aggregative variables */
4965 #define __TSTORM_TOE_AG_CONTEXT_AUX4_CF_SHIFT 2
4966 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF (0x3<<4) /* BitField agg_vars2Various aggregative variables */
4967 #define __TSTORM_TOE_AG_CONTEXT_AUX5_CF_SHIFT 4
4968 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF (0x3<<6) /* BitField agg_vars2Various aggregative variables */
4969 #define __TSTORM_TOE_AG_CONTEXT_AUX6_CF_SHIFT 6
4970 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF (0x3<<8) /* BitField agg_vars2Various aggregative variables */
4971 #define __TSTORM_TOE_AG_CONTEXT_AUX7_CF_SHIFT 8
4972 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG (0x1<<10) /* BitField agg_vars2Various aggregative variables */
4973 #define __TSTORM_TOE_AG_CONTEXT_AUX7_FLAG_SHIFT 10
4974 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<11) /* BitField agg_vars2Various aggregative variables */
4975 #define __TSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 11
4976 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN (0x1<<12) /* BitField agg_vars2Various aggregative variables */
4977 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX4_CF_EN_SHIFT 12
4978 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN (0x1<<13) /* BitField agg_vars2Various aggregative variables */
4979 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX5_CF_EN_SHIFT 13
4980 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN (0x1<<14) /* BitField agg_vars2Various aggregative variables */
4981 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX6_CF_EN_SHIFT 14
4982 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN (0x1<<15) /* BitField agg_vars2Various aggregative variables */
4983 #define TSTORM_TOE_AG_CONTEXT_RESERVED_AUX7_CF_EN_SHIFT 15
4984 uint16_t __agg_val4;
4985#endif
4986 struct tstorm_toe_tcp_ag_context_section tcp /* TCP context section, shared in TOE and iSCSI */;
4987};
4988
4989
4990/*
4991 * The eth aggregative context of Ustorm
4992 */
4993struct ustorm_eth_ag_context
4994{
4995 uint32_t __reserved0;
4996#if defined(__BIG_ENDIAN)
4997 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
4998 uint8_t __reserved2;
4999 uint16_t __reserved1;
5000#elif defined(__LITTLE_ENDIAN)
5001 uint16_t __reserved1;
5002 uint8_t __reserved2;
5003 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5004#endif
5005 uint32_t __reserved3[6];
5006};
5007
5008
5009/*
5010 * The fcoe aggregative context of Ustorm
5011 */
5012struct ustorm_fcoe_ag_context
5013{
5014#if defined(__BIG_ENDIAN)
5015 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5016 uint8_t agg_vars2;
5017 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */
5018 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5019 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */
5020 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
5021 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5022 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5023 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */
5024 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5025 uint8_t agg_vars1;
5026 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */
5027 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5028 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */
5029 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5030 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */
5031 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5032 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */
5033 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5034 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */
5035 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
5036 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */
5037 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5038 uint8_t state /* The state of the connection */;
5039#elif defined(__LITTLE_ENDIAN)
5040 uint8_t state /* The state of the connection */;
5041 uint8_t agg_vars1;
5042 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */
5043 #define __USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5044 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */
5045 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5046 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */
5047 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5048 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */
5049 #define USTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5050 #define USTORM_FCOE_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */
5051 #define USTORM_FCOE_AG_CONTEXT_INV_CF_SHIFT 4
5052 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */
5053 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5054 uint8_t agg_vars2;
5055 #define USTORM_FCOE_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */
5056 #define USTORM_FCOE_AG_CONTEXT_TX_CF_SHIFT 0
5057 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */
5058 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_SHIFT 2
5059 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5060 #define USTORM_FCOE_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5061 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */
5062 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5063 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5064#endif
5065#if defined(__BIG_ENDIAN)
5066 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5067 uint8_t agg_misc2;
5068 uint16_t pbf_tx_seq_ack /* Sequence number of the last sequence transmitted by PBF. */;
5069#elif defined(__LITTLE_ENDIAN)
5070 uint16_t pbf_tx_seq_ack /* Sequence number of the last sequence transmitted by PBF. */;
5071 uint8_t agg_misc2;
5072 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5073#endif
5074 uint32_t agg_misc4;
5075#if defined(__BIG_ENDIAN)
5076 uint8_t agg_val3_th;
5077 uint8_t agg_val3;
5078 uint16_t agg_misc3;
5079#elif defined(__LITTLE_ENDIAN)
5080 uint16_t agg_misc3;
5081 uint8_t agg_val3;
5082 uint8_t agg_val3_th;
5083#endif
5084 uint32_t expired_task_id /* Timer expiration task id */;
5085 uint32_t agg_misc4_th;
5086#if defined(__BIG_ENDIAN)
5087 uint16_t cq_prod /* CQ producer updated by FW */;
5088 uint16_t cq_cons /* CQ consumer updated by driver via doorbell */;
5089#elif defined(__LITTLE_ENDIAN)
5090 uint16_t cq_cons /* CQ consumer updated by driver via doorbell */;
5091 uint16_t cq_prod /* CQ producer updated by FW */;
5092#endif
5093#if defined(__BIG_ENDIAN)
5094 uint16_t __reserved2;
5095 uint8_t decision_rules;
5096 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5097 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5098 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5099 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5100 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules CQ negative arm indication updated via doorbell */
5101 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
5102 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5103 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
5104 uint8_t decision_rule_enable_bits;
5105 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5106 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5107 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5108 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5109 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5110 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
5111 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5112 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5113 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5114 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
5115 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */
5116 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
5117 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5118 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5119 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5120 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5121#elif defined(__LITTLE_ENDIAN)
5122 uint8_t decision_rule_enable_bits;
5123 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5124 #define __USTORM_FCOE_AG_CONTEXT_RESERVED_INV_CF_EN_SHIFT 0
5125 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5126 #define USTORM_FCOE_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5127 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5128 #define USTORM_FCOE_AG_CONTEXT_TX_CF_EN_SHIFT 2
5129 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5130 #define __USTORM_FCOE_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5131 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5132 #define __USTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 4
5133 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */
5134 #define __USTORM_FCOE_AG_CONTEXT_QUEUE0_CF_EN_SHIFT 5
5135 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5136 #define __USTORM_FCOE_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5137 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5138 #define __USTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5139 uint8_t decision_rules;
5140 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5141 #define USTORM_FCOE_AG_CONTEXT_CQ_DEC_RULE_SHIFT 0
5142 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5143 #define __USTORM_FCOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5144 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules CQ negative arm indication updated via doorbell */
5145 #define USTORM_FCOE_AG_CONTEXT_CQ_ARM_N_FLAG_SHIFT 6
5146 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5147 #define __USTORM_FCOE_AG_CONTEXT_RESERVED1_SHIFT 7
5148 uint16_t __reserved2;
5149#endif
5150};
5151
5152
5153/*
5154 * The iscsi aggregative context of Ustorm
5155 */
5156struct ustorm_iscsi_ag_context
5157{
5158#if defined(__BIG_ENDIAN)
5159 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5160 uint8_t agg_vars2;
5161 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */
5162 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5163 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */
5164 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
5165 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5166 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5167 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */
5168 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5169 uint8_t agg_vars1;
5170 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */
5171 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5172 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */
5173 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5174 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */
5175 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5176 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */
5177 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5178 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */
5179 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
5180 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */
5181 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5182 uint8_t state /* The state of the connection */;
5183#elif defined(__LITTLE_ENDIAN)
5184 uint8_t state /* The state of the connection */;
5185 uint8_t agg_vars1;
5186 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 0 */
5187 #define __USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5188 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 1 */
5189 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5190 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 2 */
5191 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5192 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1various aggregation variables The connection is currently registered to the QM with queue index 3 */
5193 #define USTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5194 #define USTORM_ISCSI_AG_CONTEXT_INV_CF (0x3<<4) /* BitField agg_vars1various aggregation variables Indicates a valid invalidate request. Set by the CMP STORM. */
5195 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_SHIFT 4
5196 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF (0x3<<6) /* BitField agg_vars1various aggregation variables Set when a message was received from the CMP STORM. For future use. */
5197 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_SHIFT 6
5198 uint8_t agg_vars2;
5199 #define USTORM_ISCSI_AG_CONTEXT_TX_CF (0x3<<0) /* BitField agg_vars2various aggregation variables Set when a message was received from the Tx STORM. For future use. */
5200 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_SHIFT 0
5201 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF (0x3<<2) /* BitField agg_vars2various aggregation variables Set when a message was received from the Timer. */
5202 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_SHIFT 2
5203 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE (0x7<<4) /* BitField agg_vars2various aggregation variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5204 #define USTORM_ISCSI_AG_CONTEXT_AGG_MISC4_RULE_SHIFT 4
5205 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK (0x1<<7) /* BitField agg_vars2various aggregation variables Used to mask the decision rule of AggVal2. Used in iSCSI. Should be 0 in all other protocols */
5206 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_MASK_SHIFT 7
5207 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5208#endif
5209#if defined(__BIG_ENDIAN)
5210 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5211 uint8_t agg_misc2;
5212 uint16_t __cq_local_comp_itt_val /* The local completion ITT to complete. Set by the CMP STORM RO for USTORM. */;
5213#elif defined(__LITTLE_ENDIAN)
5214 uint16_t __cq_local_comp_itt_val /* The local completion ITT to complete. Set by the CMP STORM RO for USTORM. */;
5215 uint8_t agg_misc2;
5216 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5217#endif
5218 uint32_t agg_misc4;
5219#if defined(__BIG_ENDIAN)
5220 uint8_t agg_val3_th;
5221 uint8_t agg_val3;
5222 uint16_t agg_misc3;
5223#elif defined(__LITTLE_ENDIAN)
5224 uint16_t agg_misc3;
5225 uint8_t agg_val3;
5226 uint8_t agg_val3_th;
5227#endif
5228 uint32_t agg_val1;
5229 uint32_t agg_misc4_th;
5230#if defined(__BIG_ENDIAN)
5231 uint16_t agg_val2_th;
5232 uint16_t agg_val2;
5233#elif defined(__LITTLE_ENDIAN)
5234 uint16_t agg_val2;
5235 uint16_t agg_val2_th;
5236#endif
5237#if defined(__BIG_ENDIAN)
5238 uint16_t __reserved2;
5239 uint8_t decision_rules;
5240 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5241 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5242 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5243 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5244 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */
5245 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5246 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5247 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
5248 uint8_t decision_rule_enable_bits;
5249 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5250 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5251 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5252 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5253 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5254 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
5255 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5256 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5257 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The local completion counter flag enable. Enabled by USTORM at the beginning. */
5258 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
5259 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */
5260 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
5261 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5262 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5263 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5264 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5265#elif defined(__LITTLE_ENDIAN)
5266 uint8_t decision_rule_enable_bits;
5267 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN (0x1<<0) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5268 #define USTORM_ISCSI_AG_CONTEXT_INV_CF_EN_SHIFT 0
5269 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN (0x1<<1) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5270 #define USTORM_ISCSI_AG_CONTEXT_COMPLETION_CF_EN_SHIFT 1
5271 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN (0x1<<2) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5272 #define USTORM_ISCSI_AG_CONTEXT_TX_CF_EN_SHIFT 2
5273 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN (0x1<<3) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5274 #define __USTORM_ISCSI_AG_CONTEXT_TIMER_CF_EN_SHIFT 3
5275 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN (0x1<<4) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The local completion counter flag enable. Enabled by USTORM at the beginning. */
5276 #define __USTORM_ISCSI_AG_CONTEXT_CQ_LOCAL_COMP_CF_EN_SHIFT 4
5277 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN (0x1<<5) /* BitField decision_rule_enable_bitsEnable bits for various decision rules The flush queues counter flag en. */
5278 #define __USTORM_ISCSI_AG_CONTEXT_QUEUES_FLUSH_Q0_CF_EN_SHIFT 5
5279 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN (0x1<<6) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5280 #define __USTORM_ISCSI_AG_CONTEXT_AUX3_CF_EN_SHIFT 6
5281 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField decision_rule_enable_bitsEnable bits for various decision rules */
5282 #define __USTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5283 uint8_t decision_rules;
5284 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5285 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5286 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5287 #define __USTORM_ISCSI_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5288 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */
5289 #define USTORM_ISCSI_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5290 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5291 #define __USTORM_ISCSI_AG_CONTEXT_RESERVED1_SHIFT 7
5292 uint16_t __reserved2;
5293#endif
5294};
5295
5296
5297/*
5298 * The toe aggregative context of Ustorm
5299 */
5300struct ustorm_toe_ag_context
5301{
5302#if defined(__BIG_ENDIAN)
5303 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5304 uint8_t __agg_vars2 /* various aggregation variables*/;
5305 uint8_t __agg_vars1 /* various aggregation variables*/;
5306 uint8_t __state /* The state of the connection */;
5307#elif defined(__LITTLE_ENDIAN)
5308 uint8_t __state /* The state of the connection */;
5309 uint8_t __agg_vars1 /* various aggregation variables*/;
5310 uint8_t __agg_vars2 /* various aggregation variables*/;
5311 uint8_t __aux_counter_flags /* auxiliary counter flags*/;
5312#endif
5313#if defined(__BIG_ENDIAN)
5314 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5315 uint8_t __agg_misc2;
5316 uint16_t __agg_misc1;
5317#elif defined(__LITTLE_ENDIAN)
5318 uint16_t __agg_misc1;
5319 uint8_t __agg_misc2;
5320 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */;
5321#endif
5322 uint32_t __agg_misc4;
5323#if defined(__BIG_ENDIAN)
5324 uint8_t __agg_val3_th;
5325 uint8_t __agg_val3;
5326 uint16_t __agg_misc3;
5327#elif defined(__LITTLE_ENDIAN)
5328 uint16_t __agg_misc3;
5329 uint8_t __agg_val3;
5330 uint8_t __agg_val3_th;
5331#endif
5332 uint32_t driver_doorbell_info_ptr_lo /* the host pointer that consist the struct of info updated */;
5333 uint32_t driver_doorbell_info_ptr_hi /* the host pointer that consist the struct of info updated */;
5334#if defined(__BIG_ENDIAN)
5335 uint16_t __agg_val2_th;
5336 uint16_t rq_prod /* The RQ producer */;
5337#elif defined(__LITTLE_ENDIAN)
5338 uint16_t rq_prod /* The RQ producer */;
5339 uint16_t __agg_val2_th;
5340#endif
5341#if defined(__BIG_ENDIAN)
5342 uint16_t __reserved2;
5343 uint8_t decision_rules;
5344 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5345 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5346 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5347 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5348 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */
5349 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5350 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5351 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
5352 uint8_t __decision_rule_enable_bits /* Enable bits for various decision rules*/;
5353#elif defined(__LITTLE_ENDIAN)
5354 uint8_t __decision_rule_enable_bits /* Enable bits for various decision rules*/;
5355 uint8_t decision_rules;
5356 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE (0x7<<0) /* BitField decision_rulesVarious decision rules */
5357 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL2_RULE_SHIFT 0
5358 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE (0x7<<3) /* BitField decision_rulesVarious decision rules */
5359 #define __USTORM_TOE_AG_CONTEXT_AGG_VAL3_RULE_SHIFT 3
5360 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG (0x1<<6) /* BitField decision_rulesVarious decision rules */
5361 #define USTORM_TOE_AG_CONTEXT_AGG_VAL2_ARM_N_FLAG_SHIFT 6
5362 #define __USTORM_TOE_AG_CONTEXT_RESERVED1 (0x1<<7) /* BitField decision_rulesVarious decision rules */
5363 #define __USTORM_TOE_AG_CONTEXT_RESERVED1_SHIFT 7
5364 uint16_t __reserved2;
5365#endif
5366};
5367
5368
5369/*
5370 * The eth aggregative context of Xstorm
5371 */
5372struct xstorm_eth_ag_context
5373{
5374 uint32_t reserved0;
5375#if defined(__BIG_ENDIAN)
5376 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
5377 uint8_t reserved2;
5378 uint16_t reserved1;
5379#elif defined(__LITTLE_ENDIAN)
5380 uint16_t reserved1;
5381 uint8_t reserved2;
5382 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
5383#endif
5384 uint32_t reserved3[30];
5385};
5386
5387
5388/*
5389 * The fcoe aggregative context section of Xstorm
5390 */
5391struct xstorm_fcoe_extra_ag_context_section
5392{
5393#if defined(__BIG_ENDIAN)
5394 uint8_t tcp_agg_vars1;
5395 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
5396 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5397 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
5398 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5399 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
5400 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5401 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
5402 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
5403 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
5404 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
5405 uint8_t __reserved_da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
5406 uint16_t __mtu /* MSS used for nagle algorithm and for transmission */;
5407#elif defined(__LITTLE_ENDIAN)
5408 uint16_t __mtu /* MSS used for nagle algorithm and for transmission */;
5409 uint8_t __reserved_da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
5410 uint8_t tcp_agg_vars1;
5411 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51 (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
5412 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED51_SHIFT 0
5413 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
5414 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5415 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
5416 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5417 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
5418 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_CLEAR_DA_TIMER_EN_SHIFT 6
5419 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
5420 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_DA_EXPIRATION_FLAG_SHIFT 7
5421#endif
5422 uint32_t snd_nxt /* The current sequence number to send */;
5423 uint32_t __xfrqe_bd_addr_lo /* The Current transmission window in bytes */;
5424 uint32_t __xfrqe_bd_addr_hi /* The current Send UNA sequence number */;
5425 uint32_t __xfrqe_data1 /* The current local advertised window to FE. */;
5426#if defined(__BIG_ENDIAN)
5427 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
5428 uint8_t __tx_dest /* aggregated value 8 */;
5429 uint16_t tcp_agg_vars2;
5430 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
5431 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5432 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
5433 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
5434 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
5435 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
5436 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
5437 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5438 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
5439 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5440 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
5441 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
5442 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
5443 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
5444 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
5445 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5446 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
5447 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
5448 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
5449 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5450 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
5451 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5452 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
5453 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5454 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
5455 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5456#elif defined(__LITTLE_ENDIAN)
5457 uint16_t tcp_agg_vars2;
5458 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57 (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
5459 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED57_SHIFT 0
5460 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58 (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
5461 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED58_SHIFT 1
5462 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59 (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
5463 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED59_SHIFT 2
5464 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
5465 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5466 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
5467 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5468 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60 (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
5469 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED60_SHIFT 5
5470 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
5471 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_ACK_TO_FE_UPDATED_EN_SHIFT 6
5472 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
5473 #define XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5474 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
5475 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_RESERVED_TX_FIN_FLAG_EN_SHIFT 8
5476 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
5477 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5478 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
5479 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5480 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
5481 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5482 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
5483 #define __XSTORM_FCOE_EXTRA_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5484 uint8_t __tx_dest /* aggregated value 8 */;
5485 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
5486#endif
5487 uint32_t __sq_base_addr_lo /* The low page address which the SQ resides in host memory */;
5488 uint32_t __sq_base_addr_hi /* The high page address which the SQ resides in host memory */;
5489 uint32_t __xfrq_base_addr_lo /* The low page address which the XFRQ resides in host memory */;
5490 uint32_t __xfrq_base_addr_hi /* The high page address which the XFRQ resides in host memory */;
5491#if defined(__BIG_ENDIAN)
5492 uint16_t __xfrq_cons /* The XFRQ consumer */;
5493 uint16_t __xfrq_prod /* The XFRQ producer, updated by Ustorm */;
5494#elif defined(__LITTLE_ENDIAN)
5495 uint16_t __xfrq_prod /* The XFRQ producer, updated by Ustorm */;
5496 uint16_t __xfrq_cons /* The XFRQ consumer */;
5497#endif
5498#if defined(__BIG_ENDIAN)
5499 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
5500 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
5501 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
5502 uint8_t __reserved_force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
5503#elif defined(__LITTLE_ENDIAN)
5504 uint8_t __reserved_force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
5505 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
5506 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
5507 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
5508#endif
5509 uint32_t __tcp_agg_vars6 /* Various aggregative variables*/;
5510#if defined(__BIG_ENDIAN)
5511 uint16_t __xfrqe_mng /* Misc aggregated variable 6 */;
5512 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
5513#elif defined(__LITTLE_ENDIAN)
5514 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
5515 uint16_t __xfrqe_mng /* Misc aggregated variable 6 */;
5516#endif
5517 uint32_t __xfrqe_data0 /* aggregated value 10 */;
5518 uint32_t __agg_val10_th /* aggregated value 10 - threshold */;
5519#if defined(__BIG_ENDIAN)
5520 uint16_t __reserved3;
5521 uint8_t __reserved2;
5522 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
5523#elif defined(__LITTLE_ENDIAN)
5524 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
5525 uint8_t __reserved2;
5526 uint16_t __reserved3;
5527#endif
5528};
5529
5530/*
5531 * The fcoe aggregative context of Xstorm
5532 */
5533struct xstorm_fcoe_ag_context
5534{
5535#if defined(__BIG_ENDIAN)
5536 uint16_t agg_val1 /* aggregated value 1 */;
5537 uint8_t agg_vars1;
5538 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
5539 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5540 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
5541 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5542 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
5543 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
5544 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
5545 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
5546 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
5547 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5548 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
5549 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
5550 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */
5551 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5552 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
5553 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
5554 uint8_t __state /* The state of the connection */;
5555#elif defined(__LITTLE_ENDIAN)
5556 uint8_t __state /* The state of the connection */;
5557 uint8_t agg_vars1;
5558 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
5559 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5560 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
5561 #define __XSTORM_FCOE_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5562 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
5563 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED51_SHIFT 2
5564 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
5565 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED52_SHIFT 3
5566 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
5567 #define __XSTORM_FCOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5568 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
5569 #define XSTORM_FCOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
5570 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */
5571 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5572 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
5573 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED_UNA_GT_NXT_EN_SHIFT 7
5574 uint16_t agg_val1 /* aggregated value 1 */;
5575#endif
5576#if defined(__BIG_ENDIAN)
5577 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
5578 uint8_t __agg_vars4 /* Various aggregative variables*/;
5579 uint8_t agg_vars3;
5580 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
5581 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5582 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
5583 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
5584 uint8_t agg_vars2;
5585 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
5586 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5587 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
5588 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
5589 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
5590 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
5591 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
5592 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
5593 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5594 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
5595 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
5596 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5597#elif defined(__LITTLE_ENDIAN)
5598 uint8_t agg_vars2;
5599 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
5600 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_SHIFT 0
5601 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
5602 #define __XSTORM_FCOE_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
5603 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
5604 #define __XSTORM_FCOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
5605 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
5606 #define __XSTORM_FCOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
5607 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5608 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE1_SHIFT 5
5609 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
5610 #define __XSTORM_FCOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
5611 uint8_t agg_vars3;
5612 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
5613 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
5614 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
5615 #define __XSTORM_FCOE_AG_CONTEXT_AUX19_CF_SHIFT 6
5616 uint8_t __agg_vars4 /* Various aggregative variables*/;
5617 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
5618#endif
5619 uint32_t more_to_send /* The number of bytes left to send */;
5620#if defined(__BIG_ENDIAN)
5621 uint16_t agg_vars5;
5622 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5623 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5624 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
5625 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
5626 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
5627 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
5628 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5629 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
5630 uint16_t sq_cons /* The SQ consumer updated by Xstorm after consuming aother WQE */;
5631#elif defined(__LITTLE_ENDIAN)
5632 uint16_t sq_cons /* The SQ consumer updated by Xstorm after consuming aother WQE */;
5633 uint16_t agg_vars5;
5634 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5635 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE5_SHIFT 0
5636 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
5637 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
5638 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
5639 #define XSTORM_FCOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
5640 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5641 #define __XSTORM_FCOE_AG_CONTEXT_CONFQ_DEC_RULE_SHIFT 14
5642#endif
5643 struct xstorm_fcoe_extra_ag_context_section __extra_section /* Extra context section */;
5644#if defined(__BIG_ENDIAN)
5645 uint16_t agg_vars7;
5646 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5647 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5648 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */
5649 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
5650 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 18 */
5651 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
5652 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5653 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
5654 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */
5655 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
5656 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */
5657 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
5658 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */
5659 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
5660 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */
5661 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
5662 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */
5663 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
5664 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */
5665 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
5666 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */
5667 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
5668 uint8_t agg_val3_th /* Aggregated value 3 - threshold */;
5669 uint8_t agg_vars6;
5670 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5671 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5672 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5673 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
5674 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5675 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
5676#elif defined(__LITTLE_ENDIAN)
5677 uint8_t agg_vars6;
5678 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5679 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE6_SHIFT 0
5680 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5681 #define __XSTORM_FCOE_AG_CONTEXT_XFRQ_DEC_RULE_SHIFT 3
5682 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5683 #define __XSTORM_FCOE_AG_CONTEXT_SQ_DEC_RULE_SHIFT 6
5684 uint8_t agg_val3_th /* Aggregated value 3 - threshold */;
5685 uint16_t agg_vars7;
5686 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
5687 #define __XSTORM_FCOE_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
5688 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */
5689 #define __XSTORM_FCOE_AG_CONTEXT_AUX13_FLAG_SHIFT 3
5690 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 18 */
5691 #define __XSTORM_FCOE_AG_CONTEXT_QUEUE0_CF_SHIFT 4
5692 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */
5693 #define XSTORM_FCOE_AG_CONTEXT_DECISION_RULE3_SHIFT 6
5694 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */
5695 #define XSTORM_FCOE_AG_CONTEXT_AUX1_CF_SHIFT 8
5696 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62 (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */
5697 #define __XSTORM_FCOE_AG_CONTEXT_RESERVED62_SHIFT 10
5698 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */
5699 #define __XSTORM_FCOE_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
5700 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */
5701 #define __XSTORM_FCOE_AG_CONTEXT_AUX10_FLAG_SHIFT 12
5702 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */
5703 #define __XSTORM_FCOE_AG_CONTEXT_AUX11_FLAG_SHIFT 13
5704 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */
5705 #define __XSTORM_FCOE_AG_CONTEXT_AUX12_FLAG_SHIFT 14
5706 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */
5707 #define __XSTORM_FCOE_AG_CONTEXT_AUX2_FLAG_SHIFT 15
5708#endif
5709#if defined(__BIG_ENDIAN)
5710 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
5711 uint16_t __agg_val11 /* aggregated value 11 */;
5712#elif defined(__LITTLE_ENDIAN)
5713 uint16_t __agg_val11 /* aggregated value 11 */;
5714 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
5715#endif
5716#if defined(__BIG_ENDIAN)
5717 uint8_t __reserved1;
5718 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
5719 uint16_t __agg_val9 /* aggregated value 9 */;
5720#elif defined(__LITTLE_ENDIAN)
5721 uint16_t __agg_val9 /* aggregated value 9 */;
5722 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
5723 uint8_t __reserved1;
5724#endif
5725#if defined(__BIG_ENDIAN)
5726 uint16_t confq_cons /* CONFQ Consumer */;
5727 uint16_t confq_prod /* CONFQ Producer, updated by Ustorm - AggVal2 */;
5728#elif defined(__LITTLE_ENDIAN)
5729 uint16_t confq_prod /* CONFQ Producer, updated by Ustorm - AggVal2 */;
5730 uint16_t confq_cons /* CONFQ Consumer */;
5731#endif
5732 uint32_t agg_varint8_t;
5733 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */
5734 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC2_SHIFT 0
5735 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */
5736 #define XSTORM_FCOE_AG_CONTEXT_AGG_MISC3_SHIFT 24
5737#if defined(__BIG_ENDIAN)
5738 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */;
5739 uint16_t sq_prod /* The SQ Producer updated by Xstorm after reading a bunch of WQEs into the context */;
5740#elif defined(__LITTLE_ENDIAN)
5741 uint16_t sq_prod /* The SQ Producer updated by Xstorm after reading a bunch of WQEs into the context */;
5742 uint16_t __cache_wqe_db /* Misc aggregated variable 0 */;
5743#endif
5744#if defined(__BIG_ENDIAN)
5745 uint8_t agg_val3 /* Aggregated value 3 */;
5746 uint8_t agg_val6 /* Aggregated value 6 */;
5747 uint8_t agg_val5_th /* Aggregated value 5 - threshold */;
5748 uint8_t agg_val5 /* Aggregated value 5 */;
5749#elif defined(__LITTLE_ENDIAN)
5750 uint8_t agg_val5 /* Aggregated value 5 */;
5751 uint8_t agg_val5_th /* Aggregated value 5 - threshold */;
5752 uint8_t agg_val6 /* Aggregated value 6 */;
5753 uint8_t agg_val3 /* Aggregated value 3 */;
5754#endif
5755#if defined(__BIG_ENDIAN)
5756 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
5757 uint16_t agg_limit1 /* aggregated limit 1 */;
5758#elif defined(__LITTLE_ENDIAN)
5759 uint16_t agg_limit1 /* aggregated limit 1 */;
5760 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
5761#endif
5762 uint32_t completion_seq /* The sequence number of the start completion point (BD) */;
5763 uint32_t confq_pbl_base_lo /* The CONFQ PBL base low address resides in host memory */;
5764 uint32_t confq_pbl_base_hi /* The CONFQ PBL base hihj address resides in host memory */;
5765};
5766
5767
5768/*
5769 * The tcp aggregative context section of Xstorm
5770 */
5771struct xstorm_tcp_tcp_ag_context_section
5772{
5773#if defined(__BIG_ENDIAN)
5774 uint8_t tcp_agg_vars1;
5775 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
5776 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5777 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
5778 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5779 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
5780 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5781 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
5782 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
5783 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
5784 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
5785 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
5786 uint16_t mss /* MSS used for nagle algorithm and for transmission */;
5787#elif defined(__LITTLE_ENDIAN)
5788 uint16_t mss /* MSS used for nagle algorithm and for transmission */;
5789 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
5790 uint8_t tcp_agg_vars1;
5791 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
5792 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
5793 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
5794 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
5795 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
5796 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
5797 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
5798 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
5799 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
5800 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
5801#endif
5802 uint32_t snd_nxt /* The current sequence number to send */;
5803 uint32_t tx_wnd /* The Current transmission window in bytes */;
5804 uint32_t snd_una /* The current Send UNA sequence number */;
5805 uint32_t local_adv_wnd /* The current local advertised window to FE. */;
5806#if defined(__BIG_ENDIAN)
5807 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
5808 uint8_t __tx_dest /* aggregated value 8 */;
5809 uint16_t tcp_agg_vars2;
5810 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
5811 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5812 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
5813 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
5814 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
5815 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
5816 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
5817 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5818 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
5819 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5820 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
5821 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
5822 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
5823 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
5824 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
5825 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5826 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
5827 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
5828 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
5829 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5830 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
5831 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5832 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
5833 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5834 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
5835 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5836#elif defined(__LITTLE_ENDIAN)
5837 uint16_t tcp_agg_vars2;
5838 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
5839 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
5840 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
5841 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
5842 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
5843 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
5844 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
5845 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
5846 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
5847 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
5848 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
5849 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
5850 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
5851 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
5852 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
5853 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
5854 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
5855 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
5856 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
5857 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
5858 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
5859 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
5860 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
5861 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
5862 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
5863 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
5864 uint8_t __tx_dest /* aggregated value 8 */;
5865 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
5866#endif
5867 uint32_t ack_to_far_end /* The ACK sequence to send to far end */;
5868 uint32_t rto_timer /* The RTO timer value */;
5869 uint32_t ka_timer /* The KA timer value */;
5870 uint32_t ts_to_echo /* The time stamp value to echo to far end */;
5871#if defined(__BIG_ENDIAN)
5872 uint16_t __agg_val7_th /* aggregated value 7 - threshold */;
5873 uint16_t __agg_val7 /* aggregated value 7 */;
5874#elif defined(__LITTLE_ENDIAN)
5875 uint16_t __agg_val7 /* aggregated value 7 */;
5876 uint16_t __agg_val7_th /* aggregated value 7 - threshold */;
5877#endif
5878#if defined(__BIG_ENDIAN)
5879 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
5880 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
5881 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
5882 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
5883#elif defined(__LITTLE_ENDIAN)
5884 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
5885 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
5886 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
5887 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
5888#endif
5889 uint32_t tcp_agg_vars6;
5890 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */
5891 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
5892 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */
5893 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
5894 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */
5895 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
5896 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */
5897 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
5898 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */
5899 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
5900 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */
5901 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
5902 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */
5903 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
5904 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */
5905 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
5906 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */
5907 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
5908 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */
5909 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
5910 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */
5911 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
5912 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */
5913 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
5914 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */
5915 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
5916 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */
5917 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
5918 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */
5919 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
5920 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */
5921 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
5922 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */
5923 #define XSTORM_TCP_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
5924 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */
5925 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
5926 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */
5927 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
5928 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */
5929 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
5930 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */
5931 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
5932 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */
5933 #define __XSTORM_TCP_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
5934#if defined(__BIG_ENDIAN)
5935 uint16_t __agg_misc6 /* Misc aggregated variable 6 */;
5936 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
5937#elif defined(__LITTLE_ENDIAN)
5938 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
5939 uint16_t __agg_misc6 /* Misc aggregated variable 6 */;
5940#endif
5941 uint32_t __agg_val10 /* aggregated value 10 */;
5942 uint32_t __agg_val10_th /* aggregated value 10 - threshold */;
5943#if defined(__BIG_ENDIAN)
5944 uint16_t __reserved3;
5945 uint8_t __reserved2;
5946 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
5947#elif defined(__LITTLE_ENDIAN)
5948 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
5949 uint8_t __reserved2;
5950 uint16_t __reserved3;
5951#endif
5952};
5953
5954/*
5955 * The iscsi aggregative context of Xstorm
5956 */
5957struct xstorm_iscsi_ag_context
5958{
5959#if defined(__BIG_ENDIAN)
5960 uint16_t agg_val1 /* aggregated value 1 */;
5961 uint8_t agg_vars1;
5962 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
5963 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5964 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
5965 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5966 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
5967 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5968 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
5969 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5970 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
5971 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5972 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
5973 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
5974 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */
5975 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5976 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
5977 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
5978 uint8_t state /* The state of the connection */;
5979#elif defined(__LITTLE_ENDIAN)
5980 uint8_t state /* The state of the connection */;
5981 uint8_t agg_vars1;
5982 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
5983 #define __XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
5984 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
5985 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM1_SHIFT 1
5986 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
5987 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM2_SHIFT 2
5988 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
5989 #define XSTORM_ISCSI_AG_CONTEXT_EXISTS_IN_QM3_SHIFT 3
5990 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
5991 #define __XSTORM_ISCSI_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
5992 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
5993 #define XSTORM_ISCSI_AG_CONTEXT_NAGLE_EN_SHIFT 5
5994 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables Used for future indication by the Driver on a doorbell */
5995 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_SHIFT 6
5996 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
5997 #define __XSTORM_ISCSI_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
5998 uint16_t agg_val1 /* aggregated value 1 */;
5999#endif
6000#if defined(__BIG_ENDIAN)
6001 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
6002 uint8_t __agg_vars4 /* Various aggregative variables*/;
6003 uint8_t agg_vars3;
6004 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
6005 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6006 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
6007 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
6008 uint8_t agg_vars2;
6009 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
6010 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6011 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
6012 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
6013 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
6014 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6015 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
6016 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6017 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6018 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
6019 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
6020 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6021#elif defined(__LITTLE_ENDIAN)
6022 uint8_t agg_vars2;
6023 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
6024 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_SHIFT 0
6025 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
6026 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_SPARE_FLAG_EN_SHIFT 2
6027 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
6028 #define __XSTORM_ISCSI_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6029 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
6030 #define __XSTORM_ISCSI_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6031 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6032 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE1_SHIFT 5
6033 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
6034 #define __XSTORM_ISCSI_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6035 uint8_t agg_vars3;
6036 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
6037 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6038 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
6039 #define __XSTORM_ISCSI_AG_CONTEXT_RX_TS_EN_CF_SHIFT 6
6040 uint8_t __agg_vars4 /* Various aggregative variables*/;
6041 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
6042#endif
6043 uint32_t more_to_send /* The number of bytes left to send */;
6044#if defined(__BIG_ENDIAN)
6045 uint16_t agg_vars5;
6046 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6047 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6048 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
6049 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6050 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
6051 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6052 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6053 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
6054 uint16_t sq_cons /* aggregated value 4 - threshold */;
6055#elif defined(__LITTLE_ENDIAN)
6056 uint16_t sq_cons /* aggregated value 4 - threshold */;
6057 uint16_t agg_vars5;
6058 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6059 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE5_SHIFT 0
6060 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
6061 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6062 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
6063 #define XSTORM_ISCSI_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6064 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6065 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE2_SHIFT 14
6066#endif
6067 struct xstorm_tcp_tcp_ag_context_section tcp /* TCP context section, shared in TOE and ISCSI */;
6068#if defined(__BIG_ENDIAN)
6069 uint16_t agg_vars7;
6070 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6071 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6072 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */
6073 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
6074 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables Sync Tstorm and Xstorm */
6075 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
6076 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6077 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
6078 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */
6079 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
6080 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */
6081 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
6082 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */
6083 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
6084 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */
6085 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
6086 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */
6087 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
6088 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */
6089 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
6090 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */
6091 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
6092 uint8_t agg_val3_th /* Aggregated value 3 - threshold */;
6093 uint8_t agg_vars6;
6094 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6095 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6096 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6097 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
6098 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6099 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
6100#elif defined(__LITTLE_ENDIAN)
6101 uint8_t agg_vars6;
6102 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6 (0x7<<0) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6103 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE6_SHIFT 0
6104 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7 (0x7<<3) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6105 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE7_SHIFT 3
6106 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4 (0x3<<6) /* BitField agg_vars6Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6107 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE4_SHIFT 6
6108 uint8_t agg_val3_th /* Aggregated value 3 - threshold */;
6109 uint16_t agg_vars7;
6110 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE (0x7<<0) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ,3-GT_CYC,4-GT_ABS,5-LT_CYC,6-LT_ABS */
6111 #define __XSTORM_ISCSI_AG_CONTEXT_AGG_VAL11_DECISION_RULE_SHIFT 0
6112 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG (0x1<<3) /* BitField agg_vars7Various aggregative variables auxiliary flag 13 */
6113 #define __XSTORM_ISCSI_AG_CONTEXT_AUX13_FLAG_SHIFT 3
6114 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF (0x3<<4) /* BitField agg_vars7Various aggregative variables Sync Tstorm and Xstorm */
6115 #define __XSTORM_ISCSI_AG_CONTEXT_STORMS_SYNC_CF_SHIFT 4
6116 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3 (0x3<<6) /* BitField agg_vars7Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6117 #define XSTORM_ISCSI_AG_CONTEXT_DECISION_RULE3_SHIFT 6
6118 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF (0x3<<8) /* BitField agg_vars7Various aggregative variables auxiliary counter flag 1 */
6119 #define XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_SHIFT 8
6120 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK (0x1<<10) /* BitField agg_vars7Various aggregative variables Mask the check of the completion sequence on retransmit */
6121 #define __XSTORM_ISCSI_AG_CONTEXT_COMPLETION_SEQ_DECISION_MASK_SHIFT 10
6122 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN (0x1<<11) /* BitField agg_vars7Various aggregative variables Enable decision rules based on aux1_cf */
6123 #define __XSTORM_ISCSI_AG_CONTEXT_AUX1_CF_EN_SHIFT 11
6124 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG (0x1<<12) /* BitField agg_vars7Various aggregative variables auxiliary flag 10 */
6125 #define __XSTORM_ISCSI_AG_CONTEXT_AUX10_FLAG_SHIFT 12
6126 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG (0x1<<13) /* BitField agg_vars7Various aggregative variables auxiliary flag 11 */
6127 #define __XSTORM_ISCSI_AG_CONTEXT_AUX11_FLAG_SHIFT 13
6128 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG (0x1<<14) /* BitField agg_vars7Various aggregative variables auxiliary flag 12 */
6129 #define __XSTORM_ISCSI_AG_CONTEXT_AUX12_FLAG_SHIFT 14
6130 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN (0x1<<15) /* BitField agg_vars7Various aggregative variables auxiliary flag 2 */
6131 #define __XSTORM_ISCSI_AG_CONTEXT_RX_WND_SCL_EN_SHIFT 15
6132#endif
6133#if defined(__BIG_ENDIAN)
6134 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
6135 uint16_t __gen_data /* Used for Iscsi. In connection establishment, it uses as rxMss, and in connection termination, it uses as command Id: 1=L5CM_TX_ACK_ON_FIN_CMD 2=L5CM_SET_MSL_TIMER_CMD 3=L5CM_TX_RST_CMD */;
6136#elif defined(__LITTLE_ENDIAN)
6137 uint16_t __gen_data /* Used for Iscsi. In connection establishment, it uses as rxMss, and in connection termination, it uses as command Id: 1=L5CM_TX_ACK_ON_FIN_CMD 2=L5CM_SET_MSL_TIMER_CMD 3=L5CM_TX_RST_CMD */;
6138 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
6139#endif
6140#if defined(__BIG_ENDIAN)
6141 uint8_t __reserved1;
6142 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
6143 uint16_t __agg_val9 /* aggregated value 9 */;
6144#elif defined(__LITTLE_ENDIAN)
6145 uint16_t __agg_val9 /* aggregated value 9 */;
6146 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
6147 uint8_t __reserved1;
6148#endif
6149#if defined(__BIG_ENDIAN)
6150 uint16_t hq_prod /* The HQ producer threashold to compare the HQ consumer, which is the current HQ producer +1 - AggVal2Th */;
6151 uint16_t hq_cons /* HQ Consumer, updated by Cstorm - AggVal2 */;
6152#elif defined(__LITTLE_ENDIAN)
6153 uint16_t hq_cons /* HQ Consumer, updated by Cstorm - AggVal2 */;
6154 uint16_t hq_prod /* The HQ producer threashold to compare the HQ consumer, which is the current HQ producer +1 - AggVal2Th */;
6155#endif
6156 uint32_t agg_varint8_t;
6157 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2 (0xFFFFFF<<0) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 2 */
6158 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC2_SHIFT 0
6159 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3 (0xFF<<24) /* BitField agg_varint8_tVarious aggregative variables Misc aggregated variable 3 */
6160 #define XSTORM_ISCSI_AG_CONTEXT_AGG_MISC3_SHIFT 24
6161#if defined(__BIG_ENDIAN)
6162 uint16_t r2tq_prod /* Misc aggregated variable 0 */;
6163 uint16_t sq_prod /* SQ Producer */;
6164#elif defined(__LITTLE_ENDIAN)
6165 uint16_t sq_prod /* SQ Producer */;
6166 uint16_t r2tq_prod /* Misc aggregated variable 0 */;
6167#endif
6168#if defined(__BIG_ENDIAN)
6169 uint8_t agg_val3 /* Aggregated value 3 */;
6170 uint8_t agg_val6 /* Aggregated value 6 */;
6171 uint8_t agg_val5_th /* Aggregated value 5 - threshold */;
6172 uint8_t agg_val5 /* Aggregated value 5 */;
6173#elif defined(__LITTLE_ENDIAN)
6174 uint8_t agg_val5 /* Aggregated value 5 */;
6175 uint8_t agg_val5_th /* Aggregated value 5 - threshold */;
6176 uint8_t agg_val6 /* Aggregated value 6 */;
6177 uint8_t agg_val3 /* Aggregated value 3 */;
6178#endif
6179#if defined(__BIG_ENDIAN)
6180 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
6181 uint16_t agg_limit1 /* aggregated limit 1 */;
6182#elif defined(__LITTLE_ENDIAN)
6183 uint16_t agg_limit1 /* aggregated limit 1 */;
6184 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
6185#endif
6186 uint32_t hq_cons_tcp_seq /* TCP sequence of the HQ BD pointed by hq_cons */;
6187 uint32_t exp_stat_sn /* expected status SN, updated by Ustorm */;
6188 uint32_t rst_seq_num /* spare aggregated variable 5 */;
6189};
6190
6191
6192/*
6193 * The toe aggregative context section of Xstorm
6194 */
6195struct xstorm_toe_tcp_ag_context_section
6196{
6197#if defined(__BIG_ENDIAN)
6198 uint8_t tcp_agg_vars1;
6199 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
6200 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6201 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
6202 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
6203 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
6204 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
6205 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
6206 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
6207 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
6208 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
6209 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
6210 uint16_t mss /* MSS used for nagle algorithm and for transmission */;
6211#elif defined(__LITTLE_ENDIAN)
6212 uint16_t mss /* MSS used for nagle algorithm and for transmission */;
6213 uint8_t __da_cnt /* Counts the number of ACK requests received from the TSTORM with no registration to QM. */;
6214 uint8_t tcp_agg_vars1;
6215 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF (0x3<<0) /* BitField tcp_agg_vars1Various aggregative variables Counter flag used to rewind the DA timer */
6216 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_DA_TIMER_CF_SHIFT 0
6217 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED (0x3<<2) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 2 */
6218 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_SHIFT 2
6219 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF (0x3<<4) /* BitField tcp_agg_vars1Various aggregative variables auxiliary counter flag 3 */
6220 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_SHIFT 4
6221 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN (0x1<<6) /* BitField tcp_agg_vars1Various aggregative variables If set enables sending clear commands as port of the DA decision rules */
6222 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CLEAR_DA_TIMER_EN_SHIFT 6
6223 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG (0x1<<7) /* BitField tcp_agg_vars1Various aggregative variables Indicates that there was a delayed ack timer expiration */
6224 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_EXPIRATION_FLAG_SHIFT 7
6225#endif
6226 uint32_t snd_nxt /* The current sequence number to send */;
6227 uint32_t tx_wnd /* The Current transmission window in bytes */;
6228 uint32_t snd_una /* The current Send UNA sequence number */;
6229 uint32_t local_adv_wnd /* The current local advertised window to FE. */;
6230#if defined(__BIG_ENDIAN)
6231 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
6232 uint8_t __tx_dest /* aggregated value 8 */;
6233 uint16_t tcp_agg_vars2;
6234 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
6235 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6236 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
6237 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
6238 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
6239 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
6240 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
6241 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
6242 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
6243 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
6244 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
6245 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
6246 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
6247 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
6248 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
6249 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
6250 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
6251 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
6252 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
6253 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
6254 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
6255 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
6256 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
6257 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
6258 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
6259 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
6260#elif defined(__LITTLE_ENDIAN)
6261 uint16_t tcp_agg_vars2;
6262 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG (0x1<<0) /* BitField tcp_agg_vars2Various aggregative variables Used in TOE to indicate that FIN is sent on a BD to bypass the naggle rule */
6263 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_SHIFT 0
6264 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED (0x1<<1) /* BitField tcp_agg_vars2Various aggregative variables Enables the tx window based decision */
6265 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_UNBLOCKED_SHIFT 1
6266 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE (0x1<<2) /* BitField tcp_agg_vars2Various aggregative variables The DA Timer status. If set indicates that the delayed ACK timer is active. */
6267 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_TIMER_ACTIVE_SHIFT 2
6268 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG (0x1<<3) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 3 */
6269 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX3_FLAG_SHIFT 3
6270 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG (0x1<<4) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 4 */
6271 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX4_FLAG_SHIFT 4
6272 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE (0x1<<5) /* BitField tcp_agg_vars2Various aggregative variables Enable DA for the specific connection */
6273 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DA_ENABLE_SHIFT 5
6274 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN (0x1<<6) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux2_cf */
6275 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ACK_TO_FE_UPDATED_EN_SHIFT 6
6276 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN (0x1<<7) /* BitField tcp_agg_vars2Various aggregative variables Enable decision rules based on aux3_cf */
6277 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SIDEBAND_SENT_CF_EN_SHIFT 7
6278 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN (0x1<<8) /* BitField tcp_agg_vars2Various aggregative variables Enable Decision rule based on tx_fin_flag */
6279 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_FIN_FLAG_EN_SHIFT 8
6280 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG (0x1<<9) /* BitField tcp_agg_vars2Various aggregative variables auxiliary flag 1 */
6281 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX1_FLAG_SHIFT 9
6282 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF (0x3<<10) /* BitField tcp_agg_vars2Various aggregative variables counter flag for setting the rto timer */
6283 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_SET_RTO_CF_SHIFT 10
6284 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF (0x3<<12) /* BitField tcp_agg_vars2Various aggregative variables timestamp was updated counter flag */
6285 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_UPDATED_CF_SHIFT 12
6286 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF (0x3<<14) /* BitField tcp_agg_vars2Various aggregative variables auxiliary counter flag 8 */
6287 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_SHIFT 14
6288 uint8_t __tx_dest /* aggregated value 8 */;
6289 uint8_t __agg_val8_th /* aggregated value 8 - threshold */;
6290#endif
6291 uint32_t ack_to_far_end /* The ACK sequence to send to far end */;
6292 uint32_t rto_timer /* The RTO timer value */;
6293 uint32_t ka_timer /* The KA timer value */;
6294 uint32_t ts_to_echo /* The time stamp value to echo to far end */;
6295#if defined(__BIG_ENDIAN)
6296 uint16_t __agg_val7_th /* aggregated value 7 - threshold */;
6297 uint16_t __agg_val7 /* aggregated value 7 */;
6298#elif defined(__LITTLE_ENDIAN)
6299 uint16_t __agg_val7 /* aggregated value 7 */;
6300 uint16_t __agg_val7_th /* aggregated value 7 - threshold */;
6301#endif
6302#if defined(__BIG_ENDIAN)
6303 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
6304 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
6305 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
6306 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
6307#elif defined(__LITTLE_ENDIAN)
6308 uint8_t __force_pure_ack_cnt /* The number of force ACK commands arrived from the TSTORM */;
6309 uint8_t __tcp_agg_vars3 /* Various aggregative variables*/;
6310 uint8_t __tcp_agg_vars4 /* Various aggregative variables*/;
6311 uint8_t __tcp_agg_vars5 /* Various aggregative variables*/;
6312#endif
6313 uint32_t tcp_agg_vars6;
6314 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN (0x1<<0) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux7_cf */
6315 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TS_TO_ECHO_CF_EN_SHIFT 0
6316 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN (0x1<<1) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux8_cf */
6317 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TX_DEST_UPDATED_CF_EN_SHIFT 1
6318 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN (0x1<<2) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux9_cf */
6319 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_EN_SHIFT 2
6320 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN (0x1<<3) /* BitField tcp_agg_vars6Various aggregative variables Enable decision rules based on aux10_cf */
6321 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_EN_SHIFT 3
6322 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG (0x1<<4) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 6 */
6323 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX6_FLAG_SHIFT 4
6324 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG (0x1<<5) /* BitField tcp_agg_vars6Various aggregative variables auxiliary flag 7 */
6325 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX7_FLAG_SHIFT 5
6326 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF (0x3<<6) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 5 */
6327 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX5_CF_SHIFT 6
6328 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF (0x3<<8) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 9 */
6329 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX9_CF_SHIFT 8
6330 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF (0x3<<10) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 10 */
6331 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX10_CF_SHIFT 10
6332 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF (0x3<<12) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 11 */
6333 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX11_CF_SHIFT 12
6334 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF (0x3<<14) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 12 */
6335 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX12_CF_SHIFT 14
6336 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF (0x3<<16) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 13 */
6337 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX13_CF_SHIFT 16
6338 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF (0x3<<18) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 14 */
6339 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX14_CF_SHIFT 18
6340 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF (0x3<<20) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 15 */
6341 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX15_CF_SHIFT 20
6342 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF (0x3<<22) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 16 */
6343 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX16_CF_SHIFT 22
6344 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF (0x3<<24) /* BitField tcp_agg_vars6Various aggregative variables auxiliary counter flag 17 */
6345 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_AUX17_CF_SHIFT 24
6346 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG (0x1<<26) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */
6347 #define XSTORM_TOE_TCP_AG_CONTEXT_SECTION_ECE_FLAG_SHIFT 26
6348 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71 (0x1<<27) /* BitField tcp_agg_vars6Various aggregative variables Can be also used as general purpose if ECN is not used */
6349 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_RESERVED71_SHIFT 27
6350 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY (0x1<<28) /* BitField tcp_agg_vars6Various aggregative variables This flag is set if the Force ACK count is set by the TSTORM. On QM output it is cleared. */
6351 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_FORCE_PURE_ACK_CNT_DIRTY_SHIFT 28
6352 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG (0x1<<29) /* BitField tcp_agg_vars6Various aggregative variables Indicates that the connection is in autostop mode */
6353 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_TCP_AUTO_STOP_FLAG_SHIFT 29
6354 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG (0x1<<30) /* BitField tcp_agg_vars6Various aggregative variables This bit uses like a one shot that the TSTORM fires and the XSTORM arms. Used to allow a single TS update for each transmission */
6355 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_DO_TS_UPDATE_FLAG_SHIFT 30
6356 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG (0x1<<31) /* BitField tcp_agg_vars6Various aggregative variables This bit is set by the TSTORM when need to cancel precious fast retransmit */
6357 #define __XSTORM_TOE_TCP_AG_CONTEXT_SECTION_CANCEL_RETRANSMIT_FLAG_SHIFT 31
6358#if defined(__BIG_ENDIAN)
6359 uint16_t __agg_misc6 /* Misc aggregated variable 6 */;
6360 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
6361#elif defined(__LITTLE_ENDIAN)
6362 uint16_t __tcp_agg_vars7 /* Various aggregative variables*/;
6363 uint16_t __agg_misc6 /* Misc aggregated variable 6 */;
6364#endif
6365 uint32_t __agg_val10 /* aggregated value 10 */;
6366 uint32_t __agg_val10_th /* aggregated value 10 - threshold */;
6367#if defined(__BIG_ENDIAN)
6368 uint16_t __reserved3;
6369 uint8_t __reserved2;
6370 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
6371#elif defined(__LITTLE_ENDIAN)
6372 uint8_t __da_only_cnt /* counts delayed acks and not window updates */;
6373 uint8_t __reserved2;
6374 uint16_t __reserved3;
6375#endif
6376};
6377
6378/*
6379 * The toe aggregative context of Xstorm
6380 */
6381struct xstorm_toe_ag_context
6382{
6383#if defined(__BIG_ENDIAN)
6384 uint16_t agg_val1 /* aggregated value 1 */;
6385 uint8_t agg_vars1;
6386 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
6387 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6388 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
6389 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
6390 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
6391 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
6392 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
6393 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
6394 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
6395 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
6396 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
6397 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
6398 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables used to indicate last doorbell for specific connection */
6399 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
6400 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
6401 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
6402 uint8_t __state /* The state of the connection */;
6403#elif defined(__LITTLE_ENDIAN)
6404 uint8_t __state /* The state of the connection */;
6405 uint8_t agg_vars1;
6406 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0 (0x1<<0) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 0 */
6407 #define __XSTORM_TOE_AG_CONTEXT_EXISTS_IN_QM0_SHIFT 0
6408 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50 (0x1<<1) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 1 */
6409 #define __XSTORM_TOE_AG_CONTEXT_RESERVED50_SHIFT 1
6410 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51 (0x1<<2) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 2 */
6411 #define __XSTORM_TOE_AG_CONTEXT_RESERVED51_SHIFT 2
6412 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52 (0x1<<3) /* BitField agg_vars1Various aggregative variables The connection is currently registered to the QM with queue index 3 */
6413 #define __XSTORM_TOE_AG_CONTEXT_RESERVED52_SHIFT 3
6414 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN (0x1<<4) /* BitField agg_vars1Various aggregative variables Enables the decision rule of more_to_Send > 0 */
6415 #define __XSTORM_TOE_AG_CONTEXT_MORE_TO_SEND_EN_SHIFT 4
6416 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN (0x1<<5) /* BitField agg_vars1Various aggregative variables Enables the nagle decision */
6417 #define XSTORM_TOE_AG_CONTEXT_NAGLE_EN_SHIFT 5
6418 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG (0x1<<6) /* BitField agg_vars1Various aggregative variables used to indicate last doorbell for specific connection */
6419 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_SHIFT 6
6420 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN (0x1<<7) /* BitField agg_vars1Various aggregative variables Enable decision rules based on equality between snd_una and snd_nxt */
6421 #define __XSTORM_TOE_AG_CONTEXT_UNA_GT_NXT_EN_SHIFT 7
6422 uint16_t agg_val1 /* aggregated value 1 */;
6423#endif
6424#if defined(__BIG_ENDIAN)
6425 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
6426 uint8_t __agg_vars4 /* Various aggregative variables*/;
6427 uint8_t agg_vars3;
6428 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
6429 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6430 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
6431 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
6432 uint8_t agg_vars2;
6433 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
6434 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6435 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
6436 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
6437 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
6438 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6439 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
6440 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6441 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6442 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
6443 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
6444 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6445#elif defined(__LITTLE_ENDIAN)
6446 uint8_t agg_vars2;
6447 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF (0x3<<0) /* BitField agg_vars2Various aggregative variables auxiliary counter flag 4 */
6448 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_SHIFT 0
6449 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN (0x1<<2) /* BitField agg_vars2Various aggregative variables Enable decision rule based on dq_spare_flag */
6450 #define __XSTORM_TOE_AG_CONTEXT_DQ_FLUSH_FLAG_EN_SHIFT 2
6451 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG (0x1<<3) /* BitField agg_vars2Various aggregative variables auxiliary flag 8 */
6452 #define __XSTORM_TOE_AG_CONTEXT_AUX8_FLAG_SHIFT 3
6453 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG (0x1<<4) /* BitField agg_vars2Various aggregative variables auxiliary flag 9 */
6454 #define __XSTORM_TOE_AG_CONTEXT_AUX9_FLAG_SHIFT 4
6455 #define XSTORM_TOE_AG_CONTEXT_RESERVED53 (0x3<<5) /* BitField agg_vars2Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6456 #define XSTORM_TOE_AG_CONTEXT_RESERVED53_SHIFT 5
6457 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN (0x1<<7) /* BitField agg_vars2Various aggregative variables Enable decision rules based on aux4_cf */
6458 #define __XSTORM_TOE_AG_CONTEXT_DQ_CF_EN_SHIFT 7
6459 uint8_t agg_vars3;
6460 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2 (0x3F<<0) /* BitField agg_vars3Various aggregative variables The physical queue number of queue index 2 */
6461 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM2_SHIFT 0
6462 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF (0x3<<6) /* BitField agg_vars3Various aggregative variables auxiliary counter flag 19 */
6463 #define __XSTORM_TOE_AG_CONTEXT_QUEUES_FLUSH_Q1_CF_SHIFT 6
6464 uint8_t __agg_vars4 /* Various aggregative variables*/;
6465 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */;
6466#endif
6467 uint32_t more_to_send /* The number of bytes left to send */;
6468#if defined(__BIG_ENDIAN)
6469 uint16_t agg_vars5;
6470 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6471 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6472 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
6473 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6474 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
6475 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6476 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6477 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
6478 uint16_t __agg_val4_th /* aggregated value 4 - threshold */;
6479#elif defined(__LITTLE_ENDIAN)
6480 uint16_t __agg_val4_th /* aggregated value 4 - threshold */;
6481 uint16_t agg_vars5;
6482 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54 (0x3<<0) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6483 #define __XSTORM_TOE_AG_CONTEXT_RESERVED54_SHIFT 0
6484 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0 (0x3F<<2) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 0 */
6485 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM0_SHIFT 2
6486 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1 (0x3F<<8) /* BitField agg_vars5Various aggregative variables The physical queue number of queue index 1 */
6487 #define XSTORM_TOE_AG_CONTEXT_PHYSICAL_QUEUE_NUM1_SHIFT 8
6488 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56 (0x3<<14) /* BitField agg_vars5Various aggregative variables 0-NOP,1-EQ,2-NEQ */
6489 #define __XSTORM_TOE_AG_CONTEXT_RESERVED56_SHIFT 14
6490#endif
6491 struct xstorm_toe_tcp_ag_context_section tcp /* TCP context section, shared in TOE and ISCSI */;
6492#if defined(__BIG_ENDIAN)
6493 uint16_t __agg_vars7 /* Various aggregative variables*/;
6494 uint8_t __agg_val3_th /* Aggregated value 3 - threshold */;
6495 uint8_t __agg_vars6 /* Various aggregative variables*/;
6496#elif defined(__LITTLE_ENDIAN)
6497 uint8_t __agg_vars6 /* Various aggregative variables*/;
6498 uint8_t __agg_val3_th /* Aggregated value 3 - threshold */;
6499 uint16_t __agg_vars7 /* Various aggregative variables*/;
6500#endif
6501#if defined(__BIG_ENDIAN)
6502 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
6503 uint16_t __agg_val11 /* aggregated value 11 */;
6504#elif defined(__LITTLE_ENDIAN)
6505 uint16_t __agg_val11 /* aggregated value 11 */;
6506 uint16_t __agg_val11_th /* aggregated value 11 - threshold */;
6507#endif
6508#if defined(__BIG_ENDIAN)
6509 uint8_t __reserved1;
6510 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
6511 uint16_t __agg_val9 /* aggregated value 9 */;
6512#elif defined(__LITTLE_ENDIAN)
6513 uint16_t __agg_val9 /* aggregated value 9 */;
6514 uint8_t __agg_val6_th /* aggregated value 6 - threshold */;
6515 uint8_t __reserved1;
6516#endif
6517#if defined(__BIG_ENDIAN)
6518 uint16_t __agg_val2_th /* Aggregated value 2 - threshold */;
6519 uint16_t cmp_bd_cons /* BD Consumer from the Completor */;
6520#elif defined(__LITTLE_ENDIAN)
6521 uint16_t cmp_bd_cons /* BD Consumer from the Completor */;
6522 uint16_t __agg_val2_th /* Aggregated value 2 - threshold */;
6523#endif
6524 uint32_t __agg_varint8_t /* Various aggregative variables*/;
6525#if defined(__BIG_ENDIAN)
6526 uint16_t __agg_misc0 /* Misc aggregated variable 0 */;
6527 uint16_t __agg_val4 /* aggregated value 4 */;
6528#elif defined(__LITTLE_ENDIAN)
6529 uint16_t __agg_val4 /* aggregated value 4 */;
6530 uint16_t __agg_misc0 /* Misc aggregated variable 0 */;
6531#endif
6532#if defined(__BIG_ENDIAN)
6533 uint8_t __agg_val3 /* Aggregated value 3 */;
6534 uint8_t __agg_val6 /* Aggregated value 6 */;
6535 uint8_t __agg_val5_th /* Aggregated value 5 - threshold */;
6536 uint8_t __agg_val5 /* Aggregated value 5 */;
6537#elif defined(__LITTLE_ENDIAN)
6538 uint8_t __agg_val5 /* Aggregated value 5 */;
6539 uint8_t __agg_val5_th /* Aggregated value 5 - threshold */;
6540 uint8_t __agg_val6 /* Aggregated value 6 */;
6541 uint8_t __agg_val3 /* Aggregated value 3 */;
6542#endif
6543#if defined(__BIG_ENDIAN)
6544 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
6545 uint16_t __bd_ind_max_val /* modulo value for bd_prod */;
6546#elif defined(__LITTLE_ENDIAN)
6547 uint16_t __bd_ind_max_val /* modulo value for bd_prod */;
6548 uint16_t __agg_misc1 /* Spare value for aggregation. NOTE: this value is used in the retransmit decision rule if CmpSeqDecMask is 0. In that case it is intended to be CmpBdSize. */;
6549#endif
6550 uint32_t cmp_bd_start_seq /* The sequence number of the start completion point (BD) */;
6551 uint32_t cmp_bd_page_0_to_31 /* Misc aggregated variable 4 */;
6552 uint32_t cmp_bd_page_32_to_63 /* spare aggregated variable 5 */;
6553};
6554
6555
6556/*
6557 * doorbell message sent to the chip
6558 */
6559struct doorbell
6560{
6561#if defined(__BIG_ENDIAN)
6562 uint16_t zero_fill2 /* driver must zero this field! */;
6563 uint8_t zero_fill1 /* driver must zero this field! */;
6564 struct doorbell_hdr_t header;
6565#elif defined(__LITTLE_ENDIAN)
6566 struct doorbell_hdr_t header;
6567 uint8_t zero_fill1 /* driver must zero this field! */;
6568 uint16_t zero_fill2 /* driver must zero this field! */;
6569#endif
6570};
6571
6572
6573/*
6574 * doorbell message sent to the chip
6575 */
6576struct doorbell_set_prod
6577{
6578#if defined(__BIG_ENDIAN)
6579 uint16_t prod /* Producer index to be set */;
6580 uint8_t zero_fill1 /* driver must zero this field! */;
6581 struct doorbell_hdr_t header;
6582#elif defined(__LITTLE_ENDIAN)
6583 struct doorbell_hdr_t header;
6584 uint8_t zero_fill1 /* driver must zero this field! */;
6585 uint16_t prod /* Producer index to be set */;
6586#endif
6587};
6588
6589
6590struct regpair_native_t
6591{
6592 uint32_t lo /* low word for reg-pair */;
6593 uint32_t hi /* high word for reg-pair */;
6594};
6595
6596
6597struct regpair_t
6598{
6599 uint32_t lo /* low word for reg-pair */;
6600 uint32_t hi /* high word for reg-pair */;
6601};
6602
6603
6604/*
6605 * Classify rule opcodes in E2/E3
6606 */
6607enum classify_rule
6608{
6609 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */,
6610 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */,
6611 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */,
6612 CLASSIFY_RULE_OPCODE_IMAC_VNI /* Add/remove an Inner MAC-VNI pair entry */,
6613 MAX_CLASSIFY_RULE};
6614
6615
6616/*
6617 * Classify rule types in E2/E3
6618 */
6619enum classify_rule_action_type
6620{
6621 CLASSIFY_RULE_REMOVE,
6622 CLASSIFY_RULE_ADD,
6623 MAX_CLASSIFY_RULE_ACTION_TYPE};
6624
6625
6626/*
6627 * client init ramrod data $$KEEP_ENDIANNESS$$
6628 */
6629struct client_init_general_data
6630{
6631 uint8_t client_id /* client_id */;
6632 uint8_t statistics_counter_id /* statistics counter id */;
6633 uint8_t statistics_en_flg /* statistics en flg */;
6634 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */;
6635 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
6636 uint8_t sp_client_id /* the slow path rings client Id. */;
6637 uint16_t mtu /* Host MTU from client config */;
6638 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */;
6639 uint8_t func_id /* PCI function ID (0-71) */;
6640 uint8_t cos /* The connection cos, if applicable */;
6641 uint8_t traffic_type;
6642 uint8_t fp_hsi_ver /* Hsi version */;
6643 uint8_t reserved0[3];
6644};
6645
6646
6647/*
6648 * client init rx data $$KEEP_ENDIANNESS$$
6649 */
6650struct client_init_rx_data
6651{
6652 uint8_t tpa_en;
6653 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */
6654 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0
6655 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */
6656 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1
6657 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */
6658 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2
6659 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */
6660 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3
6661 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */;
6662 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */;
6663 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */;
6664 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */;
6665 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
6666 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */;
6667 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */;
6668 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */;
6669 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */;
6670 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */;
6671 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */;
6672 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */;
6673 uint8_t status_block_id /* rx status block id */;
6674 uint8_t rx_sb_index_number /* status block indices */;
6675 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
6676 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
6677 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
6678 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */;
6679 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
6680 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */;
6681 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */;
6682 struct regpair_t bd_page_base /* BD page base address at the host */;
6683 struct regpair_t sge_page_base /* SGE page base address at the host */;
6684 struct regpair_t cqe_page_base /* Completion queue base address */;
6685 uint8_t is_leading_rss;
6686 uint8_t is_approx_mcast;
6687 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
6688 uint16_t state;
6689 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */
6690 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0
6691 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */
6692 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1
6693 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */
6694 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2
6695 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */
6696 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3
6697 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */
6698 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4
6699 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */
6700 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5
6701 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */
6702 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6
6703 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */
6704 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7
6705 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */;
6706 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */;
6707 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */;
6708 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */;
6709 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
6710 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
6711 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */;
6712 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
6713 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
6714 uint8_t handle_ptp_pkts_flg /* If set, this client handles PTP Packets */;
6715 uint8_t reserved6[3];
6716 uint32_t reserved7;
6717};
6718
6719/*
6720 * client init tx data $$KEEP_ENDIANNESS$$
6721 */
6722struct client_init_tx_data
6723{
6724 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */;
6725 uint8_t tx_status_block_id /* the number of status block to update */;
6726 uint8_t tx_sb_index_number /* the index to use inside the status block */;
6727 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */;
6728 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */;
6729 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */;
6730 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
6731 struct regpair_t tx_bd_page_base /* BD page base address at the host for TxBdCons */;
6732 uint16_t state;
6733 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */
6734 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0
6735 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */
6736 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1
6737 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */
6738 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2
6739 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */
6740 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3
6741 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */
6742 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4
6743 uint8_t default_vlan_flg /* is default vlan valid for this client. */;
6744 uint8_t force_default_pri_flg /* if set, force default priority */;
6745 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */;
6746 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */;
6747 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */;
6748 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */;
6749};
6750
6751/*
6752 * client init ramrod data $$KEEP_ENDIANNESS$$
6753 */
6754struct client_init_ramrod_data
6755{
6756 struct client_init_general_data general /* client init general data */;
6757 struct client_init_rx_data rx /* client init rx data */;
6758 struct client_init_tx_data tx /* client init tx data */;
6759};
6760
6761
6762/*
6763 * client update ramrod data $$KEEP_ENDIANNESS$$
6764 */
6765struct client_update_ramrod_data
6766{
6767 uint8_t client_id /* the client to update */;
6768 uint8_t func_id /* PCI function ID this client belongs to (0-71) */;
6769 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */;
6770 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */;
6771 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */;
6772 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */;
6773 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */;
6774 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */;
6775 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */;
6776 uint8_t activate_change_flg /* If set, activate_flg will be checked */;
6777 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */;
6778 uint8_t default_vlan_enable_flg;
6779 uint8_t default_vlan_change_flg;
6780 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */;
6781 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */;
6782 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */;
6783 uint8_t silent_vlan_change_flg;
6784 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */;
6785 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */;
6786 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */;
6787 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */;
6788 uint8_t handle_ptp_pkts_flg /* If set, this client handles PTP Packets */;
6789 uint8_t handle_ptp_pkts_change_flg /* If set, handle_ptp_pkts_flg will be updated. */;
6790 uint16_t reserved1;
6791 uint32_t echo /* echo value to be sent to driver on event ring */;
6792};
6793
6794
6795/*
6796 * The eth storm context of Cstorm
6797 */
6798struct cstorm_eth_st_context
6799{
6800 uint32_t __reserved0[4];
6801};
6802
6803
6804struct double_regpair
6805{
6806 uint32_t regpair0_lo /* low word for reg-pair0 */;
6807 uint32_t regpair0_hi /* high word for reg-pair0 */;
6808 uint32_t regpair1_lo /* low word for reg-pair1 */;
6809 uint32_t regpair1_hi /* high word for reg-pair1 */;
6810};
6811
6812
6813/*
6814 * 2nd parse bd type used in ethernet tx BDs
6815 */
6816enum eth_2nd_parse_bd_type
6817{
6818 ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
6819 MAX_ETH_2ND_PARSE_BD_TYPE};
6820
6821
6822/*
6823 * Ethernet address typesm used in ethernet tx BDs
6824 */
6825enum eth_addr_type
6826{
6827 UNKNOWN_ADDRESS,
6828 UNICAST_ADDRESS,
6829 MULTICAST_ADDRESS,
6830 BROADCAST_ADDRESS,
6831 MAX_ETH_ADDR_TYPE};
6832
6833
6834/*
6835 * $$KEEP_ENDIANNESS$$
6836 */
6837struct eth_classify_cmd_header
6838{
6839 uint8_t cmd_general_data;
6840 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
6841 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0
6842 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
6843 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1
6844 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR/IMAC_VNI (use enum classify_rule) */
6845 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2
6846 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */
6847 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4
6848 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */
6849 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5
6850 uint8_t func_id /* the function id */;
6851 uint8_t client_id;
6852 uint8_t reserved1;
6853};
6854
6855
6856/*
6857 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$
6858 */
6859struct eth_classify_header
6860{
6861 uint8_t rule_cnt /* number of rules in classification config ramrod */;
6862 uint8_t reserved0;
6863 uint16_t reserved1;
6864 uint32_t echo /* echo value to be sent to driver on event ring */;
6865};
6866
6867
6868/*
6869 * Command for adding/removing a Inner-MAC/VNI classification rule $$KEEP_ENDIANNESS$$
6870 */
6871struct eth_classify_imac_vni_cmd
6872{
6873 struct eth_classify_cmd_header header;
6874 uint32_t vni;
6875 uint16_t imac_lsb;
6876 uint16_t imac_mid;
6877 uint16_t imac_msb;
6878 uint16_t reserved1;
6879};
6880
6881
6882/*
6883 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$
6884 */
6885struct eth_classify_mac_cmd
6886{
6887 struct eth_classify_cmd_header header;
6888 uint16_t reserved0;
6889 uint16_t inner_mac;
6890 uint16_t mac_lsb;
6891 uint16_t mac_mid;
6892 uint16_t mac_msb;
6893 uint16_t reserved1;
6894};
6895
6896
6897/*
6898 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$
6899 */
6900struct eth_classify_pair_cmd
6901{
6902 struct eth_classify_cmd_header header;
6903 uint16_t reserved0;
6904 uint16_t inner_mac;
6905 uint16_t mac_lsb;
6906 uint16_t mac_mid;
6907 uint16_t mac_msb;
6908 uint16_t vlan;
6909};
6910
6911
6912/*
6913 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$
6914 */
6915struct eth_classify_vlan_cmd
6916{
6917 struct eth_classify_cmd_header header;
6918 uint32_t reserved0;
6919 uint32_t reserved1;
6920 uint16_t reserved2;
6921 uint16_t vlan;
6922};
6923
6924/*
6925 * union for eth classification rule $$KEEP_ENDIANNESS$$
6926 */
6927union eth_classify_rule_cmd
6928{
6929 struct eth_classify_mac_cmd mac;
6930 struct eth_classify_vlan_cmd vlan;
6931 struct eth_classify_pair_cmd pair;
6932 struct eth_classify_imac_vni_cmd imac_vni;
6933};
6934
6935/*
6936 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
6937 */
6938struct eth_classify_rules_ramrod_data
6939{
6940 struct eth_classify_header header;
6941 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
6942};
6943
6944
6945/*
6946 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$
6947 */
6948struct eth_common_ramrod_data
6949{
6950 uint32_t client_id /* id of this client. (5 bits are used) */;
6951 uint32_t reserved1;
6952};
6953
6954
6955/*
6956 * The eth storm context of Ustorm
6957 */
6958struct ustorm_eth_st_context
6959{
6960 uint32_t reserved0[52];
6961};
6962
6963/*
6964 * The eth storm context of Tstorm
6965 */
6966struct tstorm_eth_st_context
6967{
6968 uint32_t __reserved0[28];
6969};
6970
6971/*
6972 * The eth storm context of Xstorm
6973 */
6974struct xstorm_eth_st_context
6975{
6976 uint32_t reserved0[60];
6977};
6978
6979/*
6980 * Ethernet connection context
6981 */
6982struct eth_context
6983{
6984 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */;
6985 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */;
6986 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */;
6987 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */;
6988 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */;
6989 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */;
6990 struct timers_block_context timers_context /* Timers block context */;
6991 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */;
6992 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */;
6993};
6994
6995
6996/*
6997 * union for sgl and raw data.
6998 */
6999union eth_sgl_or_raw_data
7000{
7001 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */;
7002 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */;
7003};
7004
7005/*
7006 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$
7007 */
7008struct eth_end_agg_rx_cqe
7009{
7010 uint8_t type_error_flags;
7011 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
7012 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0
7013 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
7014 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2
7015 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */
7016 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3
7017 uint8_t reserved1;
7018 uint8_t queue_index /* The aggregation queue index of this packet */;
7019 uint8_t reserved2;
7020 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */;
7021 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */;
7022 uint16_t pkt_len /* Packet length */;
7023 uint8_t pure_ack_count /* Number of pure acks coalesced. */;
7024 uint8_t reserved3;
7025 uint16_t reserved4;
7026 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
7027 uint32_t padding[8];
7028};
7029
7030
7031/*
7032 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$
7033 */
7034struct eth_fast_path_rx_cqe
7035{
7036 uint8_t type_error_flags;
7037 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */
7038 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0
7039 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */
7040 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2
7041 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */
7042 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3
7043 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */
7044 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
7045 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */
7046 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
7047 #define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6) /* BitField type_error_flags Is a PTP Timesync Packet */
7048 #define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
7049 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7) /* BitField type_error_flags */
7050 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
7051 uint8_t status_flags;
7052 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */
7053 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
7054 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */
7055 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3
7056 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */
7057 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4
7058 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */
7059 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5
7060 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */
7061 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6
7062 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */
7063 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7
7064 uint8_t queue_index /* The aggregation queue index of this packet */;
7065 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */;
7066 uint32_t rss_hash_result /* RSS toeplitz hash result */;
7067 uint16_t vlan_tag /* Ethernet VLAN tag field */;
7068 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */;
7069 uint16_t len_on_bd /* Number of bytes placed on the BD */;
7070 struct parsing_flags pars_flags;
7071 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */;
7072 uint8_t tunn_type /* packet tunneling type */;
7073 uint8_t tunn_inner_hdrs_offset /* Offset to Inner Headers (for tunn_type != TUNN_TYPE_NONE) */;
7074 uint16_t reserved1;
7075 uint32_t tunn_tenant_id /* Tenant ID (for tunn_type != TUNN_TYPE_NONE */;
7076 uint32_t padding[5];
7077 uint32_t marker /* Used internally by the driver */;
7078};
7079
7080
7081/*
7082 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$
7083 */
7084struct eth_filter_rules_cmd
7085{
7086 uint8_t cmd_general_data;
7087 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
7088 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0
7089 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
7090 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1
7091 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */
7092 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2
7093 uint8_t func_id /* the function id */;
7094 uint8_t client_id /* the client id */;
7095 uint8_t reserved1;
7096 uint16_t state;
7097 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */
7098 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0
7099 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */
7100 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1
7101 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */
7102 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2
7103 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */
7104 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3
7105 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */
7106 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4
7107 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */
7108 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5
7109 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */
7110 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6
7111 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */
7112 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7
7113 uint16_t reserved3;
7114 struct regpair_t reserved4;
7115};
7116
7117
7118/*
7119 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$
7120 */
7121struct eth_filter_rules_ramrod_data
7122{
7123 struct eth_classify_header header;
7124 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
7125};
7126
7127
7128/*
7129 * Hsi version
7130 */
7131enum eth_fp_hsi_ver
7132{
7133 ETH_FP_HSI_VER_0 /* Hsi which does not support tunnelling */,
7134 ETH_FP_HSI_VER_1 /* Hsi does support tunnelling */,
7135 ETH_FP_HSI_VER_2 /* Hsi which supports tunneling and UFP */,
7136 MAX_ETH_FP_HSI_VER};
7137
7138
7139/*
7140 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$
7141 */
7142struct eth_general_rules_ramrod_data
7143{
7144 struct eth_classify_header header;
7145 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT];
7146};
7147
7148
7149/*
7150 * The data for Halt ramrod
7151 */
7152struct eth_halt_ramrod_data
7153{
7154 uint32_t client_id /* id of this client. (5 bits are used) */;
7155 uint32_t reserved0;
7156};
7157
7158
7159/*
7160 * destination and source mac address.
7161 */
7162struct eth_mac_addresses
7163{
7164#if defined(__BIG_ENDIAN)
7165 uint16_t dst_mid /* destination mac address 16 middle bits */;
7166 uint16_t dst_lo /* destination mac address 16 low bits */;
7167#elif defined(__LITTLE_ENDIAN)
7168 uint16_t dst_lo /* destination mac address 16 low bits */;
7169 uint16_t dst_mid /* destination mac address 16 middle bits */;
7170#endif
7171#if defined(__BIG_ENDIAN)
7172 uint16_t src_lo /* source mac address 16 low bits */;
7173 uint16_t dst_hi /* destination mac address 16 high bits */;
7174#elif defined(__LITTLE_ENDIAN)
7175 uint16_t dst_hi /* destination mac address 16 high bits */;
7176 uint16_t src_lo /* source mac address 16 low bits */;
7177#endif
7178#if defined(__BIG_ENDIAN)
7179 uint16_t src_hi /* source mac address 16 high bits */;
7180 uint16_t src_mid /* source mac address 16 middle bits */;
7181#elif defined(__LITTLE_ENDIAN)
7182 uint16_t src_mid /* source mac address 16 middle bits */;
7183 uint16_t src_hi /* source mac address 16 high bits */;
7184#endif
7185};
7186
7187
7188/*
7189 * tunneling related data. $$KEEP_ENDIANNESS$$
7190 */
7191struct eth_tunnel_data
7192{
7193 uint16_t dst_lo /* destination mac address 16 low bits */;
7194 uint16_t dst_mid /* destination mac address 16 middle bits */;
7195 uint16_t dst_hi /* destination mac address 16 high bits */;
7196 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */;
7197 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */;
7198 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */;
7199 uint8_t flags;
7200 #define ETH_TUNNEL_DATA_IPV6_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */
7201 #define ETH_TUNNEL_DATA_IPV6_OUTER_SHIFT 0
7202 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */
7203 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
7204};
7205
7206/*
7207 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1).
7208 */
7209union eth_mac_addr_or_tunnel_data
7210{
7211 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */;
7212 struct eth_tunnel_data tunnel_data /* tunneling related data. */;
7213};
7214
7215
7216/*
7217 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$
7218 */
7219struct eth_multicast_rules_cmd
7220{
7221 uint8_t cmd_general_data;
7222 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */
7223 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0
7224 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */
7225 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1
7226 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */
7227 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2
7228 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */
7229 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3
7230 uint8_t func_id /* the function id */;
7231 uint8_t bin_id /* the bin to add this function to (0-255) */;
7232 uint8_t engine_id /* the approximate multicast engine id */;
7233 uint32_t reserved2;
7234 struct regpair_t reserved3;
7235};
7236
7237
7238/*
7239 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$
7240 */
7241struct eth_multicast_rules_ramrod_data
7242{
7243 struct eth_classify_header header;
7244 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT];
7245};
7246
7247
7248/*
7249 * Place holder for ramrods protocol specific data
7250 */
7251struct ramrod_data
7252{
7253 uint32_t data_lo;
7254 uint32_t data_hi;
7255};
7256
7257/*
7258 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits)
7259 */
7260union eth_ramrod_data
7261{
7262 struct ramrod_data general;
7263};
7264
7265
7266/*
7267 * RSS toeplitz hash type, as reported in CQE
7268 */
7269enum eth_rss_hash_type
7270{
7271 DEFAULT_HASH_TYPE,
7272 IPV4_HASH_TYPE,
7273 TCP_IPV4_HASH_TYPE,
7274 IPV6_HASH_TYPE,
7275 TCP_IPV6_HASH_TYPE,
7276 VLAN_PRI_HASH_TYPE,
7277 E1HOV_PRI_HASH_TYPE,
7278 DSCP_HASH_TYPE,
7279 MAX_ETH_RSS_HASH_TYPE};
7280
7281
7282/*
7283 * Ethernet RSS mode
7284 */
7285enum eth_rss_mode
7286{
7287 ETH_RSS_MODE_DISABLED,
7288 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */,
7289 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS for VXLAN packets) */,
7290 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field (E1/E1h Only) */,
7291 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field (E1/E1h Only) */,
7292 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field (E1/E1h Only) */,
7293 MAX_ETH_RSS_MODE};
7294
7295
7296/*
7297 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$
7298 */
7299struct eth_rss_update_ramrod_data
7300{
7301 uint8_t rss_engine_id;
7302 uint8_t rss_mode /* The RSS mode for this function */;
7303 uint16_t capabilities;
7304 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tuple capability */
7305 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
7306 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for TCP */
7307 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
7308 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for UDP */
7309 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
7310 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tuple capability for VXLAN Tunnels */
7311 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
7312 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tuple capability */
7313 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
7314 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for TCP */
7315 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
7316 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for UDP */
7317 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
7318 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tuple capability for VXLAN Tunnels */
7319 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
7320 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY (0x1<<8) /* BitField capabilitiesFunction RSS capabilities configuration of Tunnel Inner Headers capability. */
7321 #define ETH_RSS_UPDATE_RAMROD_DATA_TUNN_INNER_HDRS_CAPABILITY_SHIFT 8
7322 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<9) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */
7323 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 9
7324 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0x3F<<10) /* BitField capabilitiesFunction RSS capabilities */
7325 #define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 10
7326 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
7327 uint8_t reserved3;
7328 uint16_t reserved4;
7329 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */;
7330 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */;
7331 uint32_t echo;
7332 uint32_t reserved5;
7333};
7334
7335
7336/*
7337 * The eth Rx Buffer Descriptor
7338 */
7339struct eth_rx_bd
7340{
7341 uint32_t addr_lo /* Single continuous buffer low pointer */;
7342 uint32_t addr_hi /* Single continuous buffer high pointer */;
7343};
7344
7345
7346struct eth_rx_bd_next_page
7347{
7348 uint32_t addr_lo /* Next page low pointer */;
7349 uint32_t addr_hi /* Next page high pointer */;
7350 uint8_t reserved[8];
7351};
7352
7353
7354/*
7355 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$
7356 */
7357struct common_ramrod_eth_rx_cqe
7358{
7359 uint8_t ramrod_type;
7360 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */
7361 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0
7362 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */
7363 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2
7364 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */
7365 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3
7366 uint8_t conn_type /* only 3 bits are used */;
7367 uint16_t reserved1 /* protocol specific data */;
7368 uint32_t conn_and_cmd_data;
7369 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
7370 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0
7371 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */
7372 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24
7373 struct ramrod_data protocol_data /* protocol specific data */;
7374 uint32_t echo;
7375 uint32_t reserved2[11];
7376};
7377
7378/*
7379 * Rx Last CQE in page (in ETH)
7380 */
7381struct eth_rx_cqe_next_page
7382{
7383 uint32_t addr_lo /* Next page low pointer */;
7384 uint32_t addr_hi /* Next page high pointer */;
7385 uint32_t reserved[14];
7386};
7387
7388/*
7389 * union for all eth rx cqe types (fix their sizes)
7390 */
7391union eth_rx_cqe
7392{
7393 struct eth_fast_path_rx_cqe fast_path_cqe;
7394 struct common_ramrod_eth_rx_cqe ramrod_cqe;
7395 struct eth_rx_cqe_next_page next_page_cqe;
7396 struct eth_end_agg_rx_cqe end_agg_cqe;
7397};
7398
7399
7400/*
7401 * Values for RX ETH CQE type field
7402 */
7403enum eth_rx_cqe_type
7404{
7405 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */,
7406 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */,
7407 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */,
7408 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */,
7409 MAX_ETH_RX_CQE_TYPE};
7410
7411
7412/*
7413 * Type of SGL/Raw field in ETH RX fast path CQE
7414 */
7415enum eth_rx_fp_sel
7416{
7417 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */,
7418 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */,
7419 MAX_ETH_RX_FP_SEL};
7420
7421
7422/*
7423 * The eth Rx SGE Descriptor
7424 */
7425struct eth_rx_sge
7426{
7427 uint32_t addr_lo /* Single continuous buffer low pointer */;
7428 uint32_t addr_hi /* Single continuous buffer high pointer */;
7429};
7430
7431
7432/*
7433 * common data for all protocols $$KEEP_ENDIANNESS$$
7434 */
7435struct spe_hdr_t
7436{
7437 uint32_t conn_and_cmd_data;
7438 #define SPE_HDR_T_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */
7439 #define SPE_HDR_T_CID_SHIFT 0
7440 #define SPE_HDR_T_CMD_ID (0xFFUL<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */
7441 #define SPE_HDR_T_CMD_ID_SHIFT 24
7442 uint16_t type;
7443 #define SPE_HDR_T_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */
7444 #define SPE_HDR_T_CONN_TYPE_SHIFT 0
7445 #define SPE_HDR_T_FUNCTION_ID (0xFF<<8) /* BitField type */
7446 #define SPE_HDR_T_FUNCTION_ID_SHIFT 8
7447 uint16_t reserved1;
7448};
7449
7450/*
7451 * specific data for ethernet slow path element
7452 */
7453union eth_specific_data
7454{
7455 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
7456 struct regpair_t client_update_ramrod_data /* The address of the data for client update ramrod */;
7457 struct regpair_t client_init_ramrod_init_data /* The data for client setup ramrod */;
7458 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */;
7459 struct regpair_t update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */;
7460 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */;
7461 struct regpair_t classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */;
7462 struct regpair_t filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */;
7463 struct regpair_t mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */;
7464};
7465
7466/*
7467 * Ethernet slow path element
7468 */
7469struct eth_spe
7470{
7471 struct spe_hdr_t hdr /* common data for all protocols */;
7472 union eth_specific_data data /* data specific to ethernet protocol */;
7473};
7474
7475
7476/*
7477 * Ethernet command ID for slow path elements
7478 */
7479enum eth_spqe_cmd_id
7480{
7481 RAMROD_CMD_ID_ETH_UNUSED,
7482 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */,
7483 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */,
7484 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */,
7485 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */,
7486 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */,
7487 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */,
7488 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */,
7489 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */,
7490 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
7491 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
7492 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
7493 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */,
7494 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */,
7495 MAX_ETH_SPQE_CMD_ID};
7496
7497
7498/*
7499 * eth tpa update command
7500 */
7501enum eth_tpa_update_command
7502{
7503 TPA_UPDATE_NONE_COMMAND /* nop command */,
7504 TPA_UPDATE_ENABLE_COMMAND /* enable command */,
7505 TPA_UPDATE_DISABLE_COMMAND /* disable command */,
7506 MAX_ETH_TPA_UPDATE_COMMAND};
7507
7508
7509/*
7510 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header
7511 */
7512enum eth_tunnel_lso_inc_ip_id
7513{
7514 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */,
7515 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */,
7516 MAX_ETH_TUNNEL_LSO_INC_IP_ID};
7517
7518
7519/*
7520 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD.
7521 */
7522enum eth_tunnel_non_lso_csum_location
7523{
7524 CSUM_ON_PKT /* checksum is on the packet. */,
7525 CSUM_ON_BD /* checksum is on the BD. */,
7526 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION};
7527
7528
7529/*
7530 * Packet Tunneling Type
7531 */
7532enum eth_tunn_type
7533{
7534 TUNN_TYPE_NONE,
7535 TUNN_TYPE_VXLAN,
7536 TUNN_TYPE_L2_GRE /* Ethernet over GRE */,
7537 TUNN_TYPE_IPV4_GRE /* IPv4 over GRE */,
7538 TUNN_TYPE_IPV6_GRE /* IPv6 over GRE */,
7539 TUNN_TYPE_L2_GENEVE /* Ethernet over GENEVE */,
7540 TUNN_TYPE_IPV4_GENEVE /* IPv4 over GENEVE */,
7541 TUNN_TYPE_IPV6_GENEVE /* IPv6 over GENEVE */,
7542 MAX_ETH_TUNN_TYPE};
7543
7544
7545/*
7546 * Tx regular BD structure $$KEEP_ENDIANNESS$$
7547 */
7548struct eth_tx_bd
7549{
7550 uint32_t addr_lo /* Single continuous buffer low pointer */;
7551 uint32_t addr_hi /* Single continuous buffer high pointer */;
7552 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */;
7553 uint16_t nbytes /* Size of the data represented by the BD */;
7554 uint8_t reserved[4] /* keeps same size as other eth tx bd types */;
7555};
7556
7557
7558/*
7559 * structure for easy accessibility to assembler
7560 */
7561struct eth_tx_bd_flags
7562{
7563 uint8_t as_bitfield;
7564 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */
7565 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0
7566 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */
7567 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1
7568 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */
7569 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2
7570 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */
7571 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4
7572 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */
7573 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5
7574 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */
7575 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6
7576 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */
7577 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7
7578};
7579
7580/*
7581 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$
7582 */
7583struct eth_tx_start_bd
7584{
7585 uint32_t addr_lo /* Single continuous buffer low pointer */;
7586 uint32_t addr_hi /* Single continuous buffer high pointer */;
7587 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */;
7588 uint16_t nbytes /* Size of the data represented by the BD */;
7589 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */;
7590 struct eth_tx_bd_flags bd_flags;
7591 uint8_t general_data;
7592 #define ETH_TX_START_BD_HDR_NBDS (0x7<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */
7593 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
7594 #define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3) /* BitField general_data If set, do not add any additional tags to the packet including MF Tags, Default VLAN or VLAN for the sake of DCB */
7595 #define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
7596 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */
7597 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
7598 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */
7599 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5
7600 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */
7601 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7
7602};
7603
7604/*
7605 * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$
7606 */
7607struct eth_tx_parse_bd_e1x
7608{
7609 uint16_t global_data;
7610 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */
7611 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0
7612 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */
7613 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4
7614 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */
7615 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6
7616 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */
7617 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7
7618 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
7619 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8
7620 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */
7621 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9
7622 uint8_t tcp_flags;
7623 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
7624 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0
7625 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
7626 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1
7627 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
7628 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2
7629 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
7630 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3
7631 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
7632 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4
7633 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
7634 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5
7635 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
7636 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6
7637 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
7638 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7
7639 uint8_t ip_hlen_w /* IP header length in WORDs */;
7640 uint16_t total_hlen_w /* IP+TCP+ETH */;
7641 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */;
7642 uint16_t lso_mss /* for LSO mode */;
7643 uint16_t ip_id /* for LSO mode */;
7644 uint32_t tcp_send_seq /* for LSO mode */;
7645};
7646
7647/*
7648 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$
7649 */
7650struct eth_tx_parse_bd_e2
7651{
7652 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */;
7653 uint32_t parsing_data;
7654 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */
7655 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0
7656 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */
7657 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11
7658 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */
7659 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15
7660 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */
7661 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16
7662 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */
7663 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30
7664};
7665
7666/*
7667 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$
7668 */
7669struct eth_tx_parse_2nd_bd
7670{
7671 uint16_t global_data;
7672 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */
7673 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
7674 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */
7675 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
7676 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */
7677 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
7678 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */
7679 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6
7680 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */
7681 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
7682 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */
7683 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
7684 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */
7685 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
7686 uint8_t bd_type;
7687 #define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0) /* BitField bd_type Type of bd (use enum eth_2nd_parse_bd_type) */
7688 #define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
7689 #define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4) /* BitField bd_type */
7690 #define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
7691 uint8_t reserved3;
7692 uint8_t tcp_flags;
7693 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */
7694 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
7695 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */
7696 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1
7697 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */
7698 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2
7699 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */
7700 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3
7701 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */
7702 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4
7703 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */
7704 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5
7705 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */
7706 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
7707 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */
7708 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
7709 uint8_t reserved4;
7710 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */;
7711 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */;
7712 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */;
7713 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */;
7714 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */;
7715};
7716
7717/*
7718 * The last BD in the BD memory will hold a pointer to the next BD memory
7719 */
7720struct eth_tx_next_bd
7721{
7722 uint32_t addr_lo /* Single continuous buffer low pointer */;
7723 uint32_t addr_hi /* Single continuous buffer high pointer */;
7724 uint8_t reserved[8] /* keeps same size as other eth tx bd types */;
7725};
7726
7727/*
7728 * union for 4 Bd types
7729 */
7730union eth_tx_bd_types
7731{
7732 struct eth_tx_start_bd start_bd /* the first bd in a packets */;
7733 struct eth_tx_bd reg_bd /* the common bd */;
7734 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */;
7735 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */;
7736 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */;
7737 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */;
7738};
7739
7740/*
7741 * array of 13 bds as appears in the eth xstorm context
7742 */
7743struct eth_tx_bds_array
7744{
7745 union eth_tx_bd_types bds[13];
7746};
7747
7748
7749/*
7750 * VLAN mode on TX BDs
7751 */
7752enum eth_tx_vlan_type
7753{
7754 X_ETH_NO_VLAN,
7755 X_ETH_OUTBAND_VLAN,
7756 X_ETH_INBAND_VLAN,
7757 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */,
7758 MAX_ETH_TX_VLAN_TYPE};
7759
7760
7761/*
7762 * Ethernet VLAN filtering mode in E1x
7763 */
7764enum eth_vlan_filter_mode
7765{
7766 ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */,
7767 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */,
7768 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */,
7769 MAX_ETH_VLAN_FILTER_MODE};
7770
7771
7772/*
7773 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$
7774 */
7775struct mac_configuration_hdr
7776{
7777 uint8_t length /* number of entries valid in this command (6 bits) */;
7778 uint8_t offset /* offset of the first entry in the list */;
7779 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */;
7780 uint32_t echo /* echo value to be sent to driver on event ring */;
7781};
7782
7783/*
7784 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$
7785 */
7786struct mac_configuration_entry
7787{
7788 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
7789 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
7790 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */;
7791 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */;
7792 uint8_t pf_id /* The pf id, for multi function mode */;
7793 uint8_t flags;
7794 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */
7795 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0
7796 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */
7797 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1
7798 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */
7799 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2
7800 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */
7801 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4
7802 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */
7803 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5
7804 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */
7805 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6
7806 uint16_t reserved0;
7807 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */;
7808};
7809
7810/*
7811 * MAC filtering configuration command
7812 */
7813struct mac_configuration_cmd
7814{
7815 struct mac_configuration_hdr hdr /* header */;
7816 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */;
7817};
7818
7819
7820/*
7821 * Set-MAC command type (in E1x)
7822 */
7823enum set_mac_action_type
7824{
7825 T_ETH_MAC_COMMAND_INVALIDATE,
7826 T_ETH_MAC_COMMAND_SET,
7827 MAX_SET_MAC_ACTION_TYPE};
7828
7829
7830/*
7831 * Ethernet TPA Modes
7832 */
7833enum tpa_mode
7834{
7835 TPA_LRO /* LRO mode TPA */,
7836 TPA_GRO /* GRO mode TPA */,
7837 MAX_TPA_MODE};
7838
7839
7840/*
7841 * tpa update ramrod data $$KEEP_ENDIANNESS$$
7842 */
7843struct tpa_update_ramrod_data
7844{
7845 uint8_t update_ipv4 /* none, enable or disable */;
7846 uint8_t update_ipv6 /* none, enable or disable */;
7847 uint8_t client_id /* client init flow control data */;
7848 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */;
7849 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */;
7850 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */;
7851 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */;
7852 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */;
7853 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */;
7854 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */;
7855 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */;
7856 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */;
7857 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */;
7858 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */;
7859};
7860
7861
7862/*
7863 * approximate-match multicast filtering for E1H per function in Tstorm
7864 */
7865struct tstorm_eth_approximate_match_multicast_filtering
7866{
7867 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */;
7868};
7869
7870
7871/*
7872 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$
7873 */
7874struct tstorm_eth_function_common_config
7875{
7876 uint16_t config_flags;
7877 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
7878 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0
7879 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */
7880 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1
7881 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */
7882 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2
7883 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */
7884 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3
7885 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */
7886 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4
7887 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */
7888 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7
7889 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */
7890 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8
7891 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */;
7892 uint8_t reserved1;
7893 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */;
7894};
7895
7896
7897/*
7898 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$
7899 */
7900struct tstorm_eth_mac_filter_config
7901{
7902 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */;
7903 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */;
7904 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */;
7905 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */;
7906 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */;
7907 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */;
7908 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */;
7909};
7910
7911
7912/*
7913 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$
7914 */
7915struct tx_queue_init_ramrod_data
7916{
7917 struct client_init_general_data general /* client init general data */;
7918 struct client_init_tx_data tx /* client init tx data */;
7919};
7920
7921
7922/*
7923 * Three RX producers for ETH
7924 */
7925struct ustorm_eth_rx_producers
7926{
7927#if defined(__BIG_ENDIAN)
7928 uint16_t bd_prod /* Producer of the RX BD ring */;
7929 uint16_t cqe_prod /* Producer of the RX CQE ring */;
7930#elif defined(__LITTLE_ENDIAN)
7931 uint16_t cqe_prod /* Producer of the RX CQE ring */;
7932 uint16_t bd_prod /* Producer of the RX BD ring */;
7933#endif
7934#if defined(__BIG_ENDIAN)
7935 uint16_t reserved;
7936 uint16_t sge_prod /* Producer of the RX SGE ring */;
7937#elif defined(__LITTLE_ENDIAN)
7938 uint16_t sge_prod /* Producer of the RX SGE ring */;
7939 uint16_t reserved;
7940#endif
7941};
7942
7943
7944/*
7945 * ABTS info $$KEEP_ENDIANNESS$$
7946 */
7947struct fcoe_abts_info
7948{
7949 uint16_t aborted_task_id /* Task ID to be aborted */;
7950 uint16_t reserved0;
7951 uint32_t reserved1;
7952};
7953
7954
7955/*
7956 * Fixed size structure in order to plant it in Union structure $$KEEP_ENDIANNESS$$
7957 */
7958struct fcoe_abts_rsp_union
7959{
7960 uint8_t r_ctl /* Only R_CTL part of the FC header in ABTS ACC or BA_RJT messages is placed */;
7961 uint8_t rsrv[3];
7962 uint32_t abts_rsp_payload[7] /* The payload of the ABTS ACC (12B) or the BA_RJT (4B) */;
7963};
7964
7965
7966/*
7967 * 4 regs size $$KEEP_ENDIANNESS$$
7968 */
7969struct fcoe_bd_ctx
7970{
7971 uint32_t buf_addr_hi /* Higher buffer host address */;
7972 uint32_t buf_addr_lo /* Lower buffer host address */;
7973 uint16_t buf_len /* Buffer length (in bytes) */;
7974 uint16_t rsrv0;
7975 uint16_t flags /* BD flags */;
7976 uint16_t rsrv1;
7977};
7978
7979
7980/*
7981 * FCoE cached sges context $$KEEP_ENDIANNESS$$
7982 */
7983struct fcoe_cached_sge_ctx
7984{
7985 struct regpair_t cur_buf_addr /* Current buffer address (in initialization it is the first cached buffer) */;
7986 uint16_t cur_buf_rem /* Remaining data in current buffer (in bytes) */;
7987 uint16_t second_buf_rem /* Remaining data in second buffer (in bytes) */;
7988 struct regpair_t second_buf_addr /* Second cached buffer address */;
7989};
7990
7991
7992/*
7993 * Cleanup info $$KEEP_ENDIANNESS$$
7994 */
7995struct fcoe_cleanup_info
7996{
7997 uint16_t cleaned_task_id /* Task ID to be cleaned */;
7998 uint16_t rolled_tx_seq_cnt /* Tx sequence count */;
7999 uint32_t rolled_tx_data_offset /* Tx data offset */;
8000};
8001
8002
8003/*
8004 * Fcp RSP flags $$KEEP_ENDIANNESS$$
8005 */
8006struct fcoe_fcp_rsp_flags
8007{
8008 uint8_t flags;
8009 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID (0x1<<0) /* BitField flags */
8010 #define FCOE_FCP_RSP_FLAGS_FCP_RSP_LEN_VALID_SHIFT 0
8011 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID (0x1<<1) /* BitField flags */
8012 #define FCOE_FCP_RSP_FLAGS_FCP_SNS_LEN_VALID_SHIFT 1
8013 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER (0x1<<2) /* BitField flags */
8014 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_OVER_SHIFT 2
8015 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER (0x1<<3) /* BitField flags */
8016 #define FCOE_FCP_RSP_FLAGS_FCP_RESID_UNDER_SHIFT 3
8017 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ (0x1<<4) /* BitField flags */
8018 #define FCOE_FCP_RSP_FLAGS_FCP_CONF_REQ_SHIFT 4
8019 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS (0x7<<5) /* BitField flags */
8020 #define FCOE_FCP_RSP_FLAGS_FCP_BIDI_FLAGS_SHIFT 5
8021};
8022
8023/*
8024 * Fcp RSP payload $$KEEP_ENDIANNESS$$
8025 */
8026struct fcoe_fcp_rsp_payload
8027{
8028 struct regpair_t reserved0;
8029 uint32_t fcp_resid;
8030 uint8_t scsi_status_code;
8031 struct fcoe_fcp_rsp_flags fcp_flags;
8032 uint16_t retry_delay_timer;
8033 uint32_t fcp_rsp_len;
8034 uint32_t fcp_sns_len;
8035};
8036
8037/*
8038 * Fixed size structure in order to plant it in Union structure $$KEEP_ENDIANNESS$$
8039 */
8040struct fcoe_fcp_rsp_union
8041{
8042 struct fcoe_fcp_rsp_payload payload;
8043 struct regpair_t reserved0;
8044};
8045
8046/*
8047 * FC header $$KEEP_ENDIANNESS$$
8048 */
8049struct fcoe_fc_hdr
8050{
8051 uint8_t s_id[3];
8052 uint8_t cs_ctl;
8053 uint8_t d_id[3];
8054 uint8_t r_ctl;
8055 uint16_t seq_cnt;
8056 uint8_t df_ctl;
8057 uint8_t seq_id;
8058 uint8_t f_ctl[3];
8059 uint8_t type;
8060 uint32_t parameters;
8061 uint16_t rx_id;
8062 uint16_t ox_id;
8063};
8064
8065/*
8066 * FC header union $$KEEP_ENDIANNESS$$
8067 */
8068struct fcoe_mp_rsp_union
8069{
8070 struct fcoe_fc_hdr fc_hdr /* FC header copied into task context (middle path flows) */;
8071 uint32_t mp_payload_len /* Length of the MP payload that was placed */;
8072 uint32_t rsrv;
8073};
8074
8075/*
8076 * Completion information $$KEEP_ENDIANNESS$$
8077 */
8078union fcoe_comp_flow_info
8079{
8080 struct fcoe_fcp_rsp_union fcp_rsp /* FCP_RSP payload */;
8081 struct fcoe_abts_rsp_union abts_rsp /* ABTS ACC R_CTL part of the FC header ABTS ACC or BA_RJT payload frame */;
8082 struct fcoe_mp_rsp_union mp_rsp /* FC header copied into task context (middle path flows) */;
8083 uint32_t opaque[8];
8084};
8085
8086
8087/*
8088 * External ABTS info $$KEEP_ENDIANNESS$$
8089 */
8090struct fcoe_ext_abts_info
8091{
8092 uint32_t rsrv0[6];
8093 struct fcoe_abts_info ctx /* ABTS information. Initialized by Xstorm */;
8094};
8095
8096
8097/*
8098 * External cleanup info $$KEEP_ENDIANNESS$$
8099 */
8100struct fcoe_ext_cleanup_info
8101{
8102 uint32_t rsrv0[6];
8103 struct fcoe_cleanup_info ctx /* Cleanup information */;
8104};
8105
8106
8107/*
8108 * Fcoe FW Tx sequence context $$KEEP_ENDIANNESS$$
8109 */
8110struct fcoe_fw_tx_seq_ctx
8111{
8112 uint32_t data_offset /* The amount of data transmitted so far (equal to FCP_DATA PARAMETER field) */;
8113 uint16_t seq_cnt /* The last SEQ_CNT transmitted */;
8114 uint16_t rsrv0;
8115};
8116
8117/*
8118 * Fcoe external FW Tx sequence context $$KEEP_ENDIANNESS$$
8119 */
8120struct fcoe_ext_fw_tx_seq_ctx
8121{
8122 uint32_t rsrv0[6];
8123 struct fcoe_fw_tx_seq_ctx ctx /* TX sequence context */;
8124};
8125
8126
8127/*
8128 * FCoE multiple sges context $$KEEP_ENDIANNESS$$
8129 */
8130struct fcoe_mul_sges_ctx
8131{
8132 struct regpair_t cur_sge_addr /* Current BD address */;
8133 uint16_t cur_sge_off /* Offset in current BD (in bytes) */;
8134 uint8_t cur_sge_idx /* Current BD index in BD list */;
8135 uint8_t sgl_size /* Total number of BDs */;
8136};
8137
8138/*
8139 * FCoE external multiple sges context $$KEEP_ENDIANNESS$$
8140 */
8141struct fcoe_ext_mul_sges_ctx
8142{
8143 struct fcoe_mul_sges_ctx mul_sgl /* SGL context */;
8144 struct regpair_t rsrv0;
8145};
8146
8147
8148/*
8149 * FCP CMD payload $$KEEP_ENDIANNESS$$
8150 */
8151struct fcoe_fcp_cmd_payload
8152{
8153 uint32_t opaque[8];
8154};
8155
8156
8157/*
8158 * Fcp xfr rdy payload $$KEEP_ENDIANNESS$$
8159 */
8160struct fcoe_fcp_xfr_rdy_payload
8161{
8162 uint32_t burst_len;
8163 uint32_t data_ro;
8164};
8165
8166
8167/*
8168 * FC frame $$KEEP_ENDIANNESS$$
8169 */
8170struct fcoe_fc_frame
8171{
8172 struct fcoe_fc_hdr fc_hdr;
8173 uint32_t reserved0[2];
8174};
8175
8176
8177/*
8178 * FCoE KCQ CQE parameters $$KEEP_ENDIANNESS$$
8179 */
8180union fcoe_kcqe_params
8181{
8182 uint32_t reserved0[4];
8183};
8184
8185/*
8186 * FCoE KCQ CQE $$KEEP_ENDIANNESS$$
8187 */
8188struct fcoe_kcqe
8189{
8190 uint32_t fcoe_conn_id /* Drivers connection ID (only 16 bits are used) */;
8191 uint32_t completion_status /* 0=command completed successfully, 1=command failed */;
8192 uint32_t fcoe_conn_context_id /* Context ID of the FCoE connection */;
8193 union fcoe_kcqe_params params /* command-specific parameters */;
8194 uint16_t qe_self_seq /* Self identifying sequence number */;
8195 uint8_t op_code /* FCoE KCQ opcode */;
8196 uint8_t flags;
8197 #define FCOE_KCQE_RESERVED0 (0x7<<0) /* BitField flags */
8198 #define FCOE_KCQE_RESERVED0_SHIFT 0
8199 #define FCOE_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */
8200 #define FCOE_KCQE_RAMROD_COMPLETION_SHIFT 3
8201 #define FCOE_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI,FCoE) */
8202 #define FCOE_KCQE_LAYER_CODE_SHIFT 4
8203 #define FCOE_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */
8204 #define FCOE_KCQE_LINKED_WITH_NEXT_SHIFT 7
8205};
8206
8207
8208/*
8209 * FCoE KWQE header $$KEEP_ENDIANNESS$$
8210 */
8211struct fcoe_kwqe_header
8212{
8213 uint8_t op_code /* FCoE KWQE opcode */;
8214 uint8_t flags;
8215 #define FCOE_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */
8216 #define FCOE_KWQE_HEADER_RESERVED0_SHIFT 0
8217 #define FCOE_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5) */
8218 #define FCOE_KWQE_HEADER_LAYER_CODE_SHIFT 4
8219 #define FCOE_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */
8220 #define FCOE_KWQE_HEADER_RESERVED1_SHIFT 7
8221};
8222
8223/*
8224 * FCoE firmware init request 1 $$KEEP_ENDIANNESS$$
8225 */
8226struct fcoe_kwqe_init1
8227{
8228 uint16_t num_tasks /* Number of tasks in global task list */;
8229 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8230 uint32_t task_list_pbl_addr_lo /* Lower 32-bit of Task List page table */;
8231 uint32_t task_list_pbl_addr_hi /* Higher 32-bit of Task List page table */;
8232 uint32_t dummy_buffer_addr_lo /* Lower 32-bit of dummy buffer */;
8233 uint32_t dummy_buffer_addr_hi /* Higher 32-bit of dummy buffer */;
8234 uint16_t sq_num_wqes /* Number of entries in the Send Queue */;
8235 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */;
8236 uint16_t rq_buffer_log_size /* Log of the size of a single buffer (entry) in the RQ */;
8237 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */;
8238 uint16_t mtu /* Max transmission unit */;
8239 uint8_t num_sessions_log /* Log of the number of sessions */;
8240 uint8_t flags;
8241 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE (0xF<<0) /* BitField flags log of page size value */
8242 #define FCOE_KWQE_INIT1_LOG_PAGE_SIZE_SHIFT 0
8243 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC (0x7<<4) /* BitField flags */
8244 #define FCOE_KWQE_INIT1_LOG_CACHED_PBES_PER_FUNC_SHIFT 4
8245 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED (0x1<<7) /* BitField flags Special MF mode where classification failure indication from HW is allowed */
8246 #define FCOE_KWQE_INIT1_CLASSIFY_FAILED_ALLOWED_SHIFT 7
8247};
8248
8249/*
8250 * FCoE firmware init request 2 $$KEEP_ENDIANNESS$$
8251 */
8252struct fcoe_kwqe_init2
8253{
8254 uint8_t hsi_major_version /* Implies on a change broken previous HSI */;
8255 uint8_t hsi_minor_version /* Implies on a change which does not broken previous HSI */;
8256 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8257 uint32_t hash_tbl_pbl_addr_lo /* Lower 32-bit of Hash table PBL */;
8258 uint32_t hash_tbl_pbl_addr_hi /* Higher 32-bit of Hash table PBL */;
8259 uint32_t t2_hash_tbl_addr_lo /* Lower 32-bit of T2 Hash table */;
8260 uint32_t t2_hash_tbl_addr_hi /* Higher 32-bit of T2 Hash table */;
8261 uint32_t t2_ptr_hash_tbl_addr_lo /* Lower 32-bit of T2 ptr Hash table */;
8262 uint32_t t2_ptr_hash_tbl_addr_hi /* Higher 32-bit of T2 ptr Hash table */;
8263 uint32_t free_list_count /* T2 free list count */;
8264};
8265
8266/*
8267 * FCoE firmware init request 3 $$KEEP_ENDIANNESS$$
8268 */
8269struct fcoe_kwqe_init3
8270{
8271 uint16_t reserved0;
8272 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8273 uint32_t error_bit_map_lo /* 32 lower bits of error bitmap: 1=error, 0=warning */;
8274 uint32_t error_bit_map_hi /* 32 upper bits of error bitmap: 1=error, 0=warning */;
8275 uint8_t perf_config /* 0= no performance acceleration, 1=cached connection, 2=cached tasks, 3=both */;
8276 uint8_t reserved21[3];
8277 uint32_t reserved2[4];
8278};
8279
8280/*
8281 * FCoE connection offload request 1 $$KEEP_ENDIANNESS$$
8282 */
8283struct fcoe_kwqe_conn_offload1
8284{
8285 uint16_t fcoe_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */;
8286 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8287 uint32_t sq_addr_lo /* Lower 32-bit of SQ */;
8288 uint32_t sq_addr_hi /* Higher 32-bit of SQ */;
8289 uint32_t rq_pbl_addr_lo /* Lower 32-bit of RQ page table */;
8290 uint32_t rq_pbl_addr_hi /* Higher 32-bit of RQ page table */;
8291 uint32_t rq_first_pbe_addr_lo /* Lower 32-bit of first RQ pbe */;
8292 uint32_t rq_first_pbe_addr_hi /* Higher 32-bit of first RQ pbe */;
8293 uint16_t rq_prod /* Initial RQ producer */;
8294 uint16_t reserved0;
8295};
8296
8297/*
8298 * FCoE connection offload request 2 $$KEEP_ENDIANNESS$$
8299 */
8300struct fcoe_kwqe_conn_offload2
8301{
8302 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */;
8303 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8304 uint32_t cq_addr_lo /* Lower 32-bit of CQ */;
8305 uint32_t cq_addr_hi /* Higher 32-bit of CQ */;
8306 uint32_t xferq_addr_lo /* Lower 32-bit of XFERQ */;
8307 uint32_t xferq_addr_hi /* Higher 32-bit of XFERQ */;
8308 uint32_t conn_db_addr_lo /* Lower 32-bit of Conn DB (RQ prod and CQ arm bit) */;
8309 uint32_t conn_db_addr_hi /* Higher 32-bit of Conn DB (RQ prod and CQ arm bit) */;
8310 uint32_t reserved1;
8311};
8312
8313/*
8314 * FCoE connection offload request 3 $$KEEP_ENDIANNESS$$
8315 */
8316struct fcoe_kwqe_conn_offload3
8317{
8318 uint16_t vlan_tag;
8319 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID (0xFFF<<0) /* BitField vlan_tag Vlan id */
8320 #define FCOE_KWQE_CONN_OFFLOAD3_VLAN_ID_SHIFT 0
8321 #define FCOE_KWQE_CONN_OFFLOAD3_CFI (0x1<<12) /* BitField vlan_tag Canonical format indicator */
8322 #define FCOE_KWQE_CONN_OFFLOAD3_CFI_SHIFT 12
8323 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY (0x7<<13) /* BitField vlan_tag Vlan priority */
8324 #define FCOE_KWQE_CONN_OFFLOAD3_PRIORITY_SHIFT 13
8325 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8326 uint8_t s_id[3] /* Source ID, received during FLOGI */;
8327 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */;
8328 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */;
8329 uint8_t flags;
8330 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */
8331 #define FCOE_KWQE_CONN_OFFLOAD3_B_MUL_N_PORT_IDS_SHIFT 0
8332 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */
8333 #define FCOE_KWQE_CONN_OFFLOAD3_B_E_D_TOV_RES_SHIFT 1
8334 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */
8335 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONT_INCR_SEQ_CNT_SHIFT 2
8336 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */
8337 #define FCOE_KWQE_CONN_OFFLOAD3_B_CONF_REQ_SHIFT 3
8338 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */
8339 #define FCOE_KWQE_CONN_OFFLOAD3_B_REC_VALID_SHIFT 4
8340 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID (0x1<<5) /* BitField flags Class 2 valid, received during PLOGI */
8341 #define FCOE_KWQE_CONN_OFFLOAD3_B_C2_VALID_SHIFT 5
8342 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0 (0x1<<6) /* BitField flags ACK_0 capability supporting by target, received furing PLOGI */
8343 #define FCOE_KWQE_CONN_OFFLOAD3_B_ACK_0_SHIFT 6
8344 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG (0x1<<7) /* BitField flags Is inner vlan exist */
8345 #define FCOE_KWQE_CONN_OFFLOAD3_B_VLAN_FLAG_SHIFT 7
8346 uint32_t reserved;
8347 uint32_t confq_first_pbe_addr_lo /* The first page used when handling CONFQ - low address */;
8348 uint32_t confq_first_pbe_addr_hi /* The first page used when handling CONFQ - high address */;
8349 uint16_t tx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by target, received during PLOGI */;
8350 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */;
8351 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */;
8352 uint8_t rx_max_conc_seqs_c3 /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */;
8353 uint8_t rx_open_seqs_exch_c3 /* Maximum Open Sequences per Exchange for Class 3 supported by us, sent during PLOGI */;
8354};
8355
8356/*
8357 * FCoE connection offload request 4 $$KEEP_ENDIANNESS$$
8358 */
8359struct fcoe_kwqe_conn_offload4
8360{
8361 uint8_t e_d_tov_timer_val /* E_D_TOV timer value in milliseconds/20, negotiated in PLOGI */;
8362 uint8_t reserved2;
8363 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8364 uint8_t src_mac_addr_lo[2] /* Lower 16-bit of source MAC address */;
8365 uint8_t src_mac_addr_mid[2] /* Mid 16-bit of source MAC address */;
8366 uint8_t src_mac_addr_hi[2] /* Higher 16-bit of source MAC address */;
8367 uint8_t dst_mac_addr_hi[2] /* Higher 16-bit of destination MAC address */;
8368 uint8_t dst_mac_addr_lo[2] /* Lower 16-bit destination MAC address */;
8369 uint8_t dst_mac_addr_mid[2] /* Mid 16-bit destination MAC address */;
8370 uint32_t lcq_addr_lo /* Lower 32-bit of LCQ */;
8371 uint32_t lcq_addr_hi /* Higher 32-bit of LCQ */;
8372 uint32_t confq_pbl_base_addr_lo /* CONFQ PBL low address */;
8373 uint32_t confq_pbl_base_addr_hi /* CONFQ PBL high address */;
8374};
8375
8376/*
8377 * FCoE connection enable request $$KEEP_ENDIANNESS$$
8378 */
8379struct fcoe_kwqe_conn_enable_disable
8380{
8381 uint16_t reserved0;
8382 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8383 uint8_t src_mac_addr_lo[2] /* Lower 16-bit of source MAC address (HBAs MAC address) */;
8384 uint8_t src_mac_addr_mid[2] /* Mid 16-bit of source MAC address (HBAs MAC address) */;
8385 uint8_t src_mac_addr_hi[2] /* Higher 16-bit of source MAC address (HBAs MAC address) */;
8386 uint16_t vlan_tag;
8387 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID (0xFFF<<0) /* BitField vlan_tagVlan tag Vlan id */
8388 #define FCOE_KWQE_CONN_ENABLE_DISABLE_VLAN_ID_SHIFT 0
8389 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI (0x1<<12) /* BitField vlan_tagVlan tag Canonical format indicator */
8390 #define FCOE_KWQE_CONN_ENABLE_DISABLE_CFI_SHIFT 12
8391 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY (0x7<<13) /* BitField vlan_tagVlan tag Vlan priority */
8392 #define FCOE_KWQE_CONN_ENABLE_DISABLE_PRIORITY_SHIFT 13
8393 uint8_t dst_mac_addr_lo[2] /* Lower 16-bit of destination MAC address (FCFs MAC address) */;
8394 uint8_t dst_mac_addr_mid[2] /* Mid 16-bit of destination MAC address (FCFs MAC address) */;
8395 uint8_t dst_mac_addr_hi[2] /* Higher 16-bit of destination MAC address (FCFs MAC address) */;
8396 uint16_t reserved1;
8397 uint8_t s_id[3] /* Source ID, received during FLOGI */;
8398 uint8_t vlan_flag /* Vlan flag */;
8399 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */;
8400 uint8_t reserved3;
8401 uint32_t context_id /* Context ID (cid) of the connection */;
8402 uint32_t conn_id /* FCoE Connection ID */;
8403 uint32_t reserved4;
8404};
8405
8406/*
8407 * FCoE connection destroy request $$KEEP_ENDIANNESS$$
8408 */
8409struct fcoe_kwqe_conn_destroy
8410{
8411 uint16_t reserved0;
8412 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8413 uint32_t context_id /* Context ID (cid) of the connection */;
8414 uint32_t conn_id /* FCoE Connection ID */;
8415 uint32_t reserved1[5];
8416};
8417
8418/*
8419 * FCoe destroy request $$KEEP_ENDIANNESS$$
8420 */
8421struct fcoe_kwqe_destroy
8422{
8423 uint16_t reserved0;
8424 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8425 uint32_t reserved1[7];
8426};
8427
8428/*
8429 * FCoe statistics request $$KEEP_ENDIANNESS$$
8430 */
8431struct fcoe_kwqe_stat
8432{
8433 uint16_t reserved0;
8434 struct fcoe_kwqe_header hdr /* KWQ WQE header */;
8435 uint32_t stat_params_addr_lo /* Statistics host address */;
8436 uint32_t stat_params_addr_hi /* Statistics host address */;
8437 uint32_t reserved1[5];
8438};
8439
8440/*
8441 * FCoE KWQ WQE $$KEEP_ENDIANNESS$$
8442 */
8443union fcoe_kwqe
8444{
8445 struct fcoe_kwqe_init1 init1;
8446 struct fcoe_kwqe_init2 init2;
8447 struct fcoe_kwqe_init3 init3;
8448 struct fcoe_kwqe_conn_offload1 conn_offload1;
8449 struct fcoe_kwqe_conn_offload2 conn_offload2;
8450 struct fcoe_kwqe_conn_offload3 conn_offload3;
8451 struct fcoe_kwqe_conn_offload4 conn_offload4;
8452 struct fcoe_kwqe_conn_enable_disable conn_enable_disable;
8453 struct fcoe_kwqe_conn_destroy conn_destroy;
8454 struct fcoe_kwqe_destroy destroy;
8455 struct fcoe_kwqe_stat statistics;
8456};
8457
8458
8459/*
8460 * TX SGL context $$KEEP_ENDIANNESS$$
8461 */
8462union fcoe_sgl_union_ctx
8463{
8464 struct fcoe_cached_sge_ctx cached_sge /* Cached SGEs context */;
8465 struct fcoe_ext_mul_sges_ctx sgl /* SGL context */;
8466 uint32_t opaque[5];
8467};
8468
8469/*
8470 * Data-In/ELS/BLS information $$KEEP_ENDIANNESS$$
8471 */
8472struct fcoe_read_flow_info
8473{
8474 union fcoe_sgl_union_ctx sgl_ctx /* The SGL that would be used for data placement (20 bytes) */;
8475 uint32_t rsrv0[3];
8476};
8477
8478
8479/*
8480 * Fcoe stat context $$KEEP_ENDIANNESS$$
8481 */
8482struct fcoe_s_stat_ctx
8483{
8484 uint8_t flags;
8485 #define FCOE_S_STAT_CTX_ACTIVE (0x1<<0) /* BitField flags Active Sequence indication (0 - not avtive; 1 - active) */
8486 #define FCOE_S_STAT_CTX_ACTIVE_SHIFT 0
8487 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND (0x1<<1) /* BitField flags Abort Sequence requested indication */
8488 #define FCOE_S_STAT_CTX_ACK_ABORT_SEQ_COND_SHIFT 1
8489 #define FCOE_S_STAT_CTX_ABTS_PERFORMED (0x1<<2) /* BitField flags ABTS (on Sequence) protocol complete indication (0 - not completed; 1 -completed by Recipient) */
8490 #define FCOE_S_STAT_CTX_ABTS_PERFORMED_SHIFT 2
8491 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT (0x1<<3) /* BitField flags E_D_TOV timeout indication */
8492 #define FCOE_S_STAT_CTX_SEQ_TIMEOUT_SHIFT 3
8493 #define FCOE_S_STAT_CTX_P_RJT (0x1<<4) /* BitField flags P_RJT transmitted indication */
8494 #define FCOE_S_STAT_CTX_P_RJT_SHIFT 4
8495 #define FCOE_S_STAT_CTX_ACK_EOFT (0x1<<5) /* BitField flags ACK (EOFt) transmitted indication (0 - not tranmitted; 1 - transmitted) */
8496 #define FCOE_S_STAT_CTX_ACK_EOFT_SHIFT 5
8497 #define FCOE_S_STAT_CTX_RSRV1 (0x3<<6) /* BitField flags */
8498 #define FCOE_S_STAT_CTX_RSRV1_SHIFT 6
8499};
8500
8501/*
8502 * Fcoe rx seq context $$KEEP_ENDIANNESS$$
8503 */
8504struct fcoe_rx_seq_ctx
8505{
8506 uint8_t seq_id /* The Sequence ID */;
8507 struct fcoe_s_stat_ctx s_stat /* The Sequence status */;
8508 uint16_t seq_cnt /* The lowest SEQ_CNT received for the Sequence */;
8509 uint32_t low_exp_ro /* Report on the offset at the beginning of the Sequence */;
8510 uint32_t high_exp_ro /* The highest expected relative offset. The next buffer offset to be received in case of XFER_RDY or in FCP_DATA */;
8511};
8512
8513
8514/*
8515 * FCoE RX statistics parameters section#0 $$KEEP_ENDIANNESS$$
8516 */
8517struct fcoe_rx_stat_params_section0
8518{
8519 uint32_t fcoe_rx_pkt_cnt /* Number of FCoE packets that were legally received */;
8520 uint32_t fcoe_rx_byte_cnt /* Number of FCoE bytes that were legally received */;
8521};
8522
8523
8524/*
8525 * FCoE RX statistics parameters section#1 $$KEEP_ENDIANNESS$$
8526 */
8527struct fcoe_rx_stat_params_section1
8528{
8529 uint32_t fcoe_ver_cnt /* Number of packets with wrong FCoE version */;
8530 uint32_t fcoe_rx_drop_pkt_cnt /* Number of FCoE packets that were dropped */;
8531};
8532
8533
8534/*
8535 * FCoE RX statistics parameters section#2 $$KEEP_ENDIANNESS$$
8536 */
8537struct fcoe_rx_stat_params_section2
8538{
8539 uint32_t fc_crc_cnt /* Number of packets with FC CRC error */;
8540 uint32_t eofa_del_cnt /* Number of packets with EOFa delimiter */;
8541 uint32_t miss_frame_cnt /* Number of missing packets */;
8542 uint32_t seq_timeout_cnt /* Number of sequence timeout expirations (E_D_TOV) */;
8543 uint32_t drop_seq_cnt /* Number of Sequences that were sropped */;
8544 uint32_t fcoe_rx_drop_pkt_cnt /* Number of FCoE packets that were dropped */;
8545 uint32_t fcp_rx_pkt_cnt /* Number of FCP packets that were legally received */;
8546 uint32_t reserved0;
8547};
8548
8549
8550/*
8551 * Fcoe rx_wr union context $$KEEP_ENDIANNESS$$
8552 */
8553union fcoe_rx_wr_union_ctx
8554{
8555 struct fcoe_read_flow_info read_info /* Data-In/ELS/BLS information */;
8556 union fcoe_comp_flow_info comp_info /* Completion information */;
8557 uint32_t opaque[8];
8558};
8559
8560
8561/*
8562 * FCoE SQ element $$KEEP_ENDIANNESS$$
8563 */
8564struct fcoe_sqe
8565{
8566 uint16_t wqe;
8567 #define FCOE_SQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */
8568 #define FCOE_SQE_TASK_ID_SHIFT 0
8569 #define FCOE_SQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */
8570 #define FCOE_SQE_TOGGLE_BIT_SHIFT 15
8571};
8572
8573
8574/*
8575 * FCoE TX statistics parameters $$KEEP_ENDIANNESS$$
8576 */
8577struct fcoe_tx_stat_params
8578{
8579 uint32_t fcoe_tx_pkt_cnt /* Number of transmitted FCoE packets */;
8580 uint32_t fcoe_tx_byte_cnt /* Number of transmitted FCoE bytes */;
8581 uint32_t fcp_tx_pkt_cnt /* Number of transmitted FCP packets */;
8582 uint32_t reserved0;
8583};
8584
8585/*
8586 * FCoE statistics parameters $$KEEP_ENDIANNESS$$
8587 */
8588struct fcoe_statistics_params
8589{
8590 struct fcoe_tx_stat_params tx_stat /* FCoE TX statistics parameters */;
8591 struct fcoe_rx_stat_params_section0 rx_stat0 /* FCoE RX statistics parameters section#0 */;
8592 struct fcoe_rx_stat_params_section1 rx_stat1 /* FCoE RX statistics parameters section#1 */;
8593 struct fcoe_rx_stat_params_section2 rx_stat2 /* FCoE RX statistics parameters section#2 */;
8594};
8595
8596
8597/*
8598 * 14 regs $$KEEP_ENDIANNESS$$
8599 */
8600struct fcoe_tce_tx_only
8601{
8602 union fcoe_sgl_union_ctx sgl_ctx /* TX SGL context */;
8603 uint32_t rsrv0;
8604};
8605
8606/*
8607 * 32 bytes (8 regs) used for TX only purposes $$KEEP_ENDIANNESS$$
8608 */
8609union fcoe_tx_wr_rx_rd_union_ctx
8610{
8611 struct fcoe_fc_frame tx_frame /* Middle-path/ABTS/Data-Out information */;
8612 struct fcoe_fcp_cmd_payload fcp_cmd /* FCP_CMD payload */;
8613 struct fcoe_ext_cleanup_info cleanup /* Task ID to be cleaned */;
8614 struct fcoe_ext_abts_info abts /* Task ID to be aborted */;
8615 struct fcoe_ext_fw_tx_seq_ctx tx_seq /* TX sequence information */;
8616 uint32_t opaque[8];
8617};
8618
8619/*
8620 * tce_tx_wr_rx_rd_const $$KEEP_ENDIANNESS$$
8621 */
8622struct fcoe_tce_tx_wr_rx_rd_const
8623{
8624 uint8_t init_flags;
8625 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE (0x7<<0) /* BitField init_flags Task type - Write / Read / Middle / Unsolicited / ABTS / Cleanup */
8626 #define FCOE_TCE_TX_WR_RX_RD_CONST_TASK_TYPE_SHIFT 0
8627 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE (0x1<<3) /* BitField init_flags Tape/Disk device indication */
8628 #define FCOE_TCE_TX_WR_RX_RD_CONST_DEV_TYPE_SHIFT 3
8629 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE (0x1<<4) /* BitField init_flags Class 3/2 indication */
8630 #define FCOE_TCE_TX_WR_RX_RD_CONST_CLASS_TYPE_SHIFT 4
8631 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE (0x3<<5) /* BitField init_flags Num of cached sge (0 - not cached sge) */
8632 #define FCOE_TCE_TX_WR_RX_RD_CONST_CACHED_SGE_SHIFT 5
8633 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV (0x1<<7) /* BitField init_flags Support REC_TOV flag, for FW use only */
8634 #define FCOE_TCE_TX_WR_RX_RD_CONST_SUPPORT_REC_TOV_SHIFT 7
8635 uint8_t tx_flags;
8636 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID (0x1<<0) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Indication of TX valid task */
8637 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_VALID_SHIFT 0
8638 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE (0xF<<1) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write The TX state of the task */
8639 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_STATE_SHIFT 1
8640 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1 (0x1<<5) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write */
8641 #define FCOE_TCE_TX_WR_RX_RD_CONST_RSRV1_SHIFT 5
8642 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT (0x1<<6) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write TX Sequence initiative indication */
8643 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_SEQ_INIT_SHIFT 6
8644 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS (0x1<<7) /* BitField tx_flagsBoth TX and RX processing could read but only the TX could write Compelted full tranmission of this task */
8645 #define FCOE_TCE_TX_WR_RX_RD_CONST_TX_COMP_TRNS_SHIFT 7
8646 uint16_t rsrv3;
8647 uint32_t verify_tx_seq /* Sequence counter snapshot in order to verify target did not send FCP_RSP before the actual transmission of PBF from the SGL */;
8648};
8649
8650/*
8651 * tce_tx_wr_rx_rd $$KEEP_ENDIANNESS$$
8652 */
8653struct fcoe_tce_tx_wr_rx_rd
8654{
8655 union fcoe_tx_wr_rx_rd_union_ctx union_ctx /* 32 (8 regs) bytes used for TX only purposes */;
8656 struct fcoe_tce_tx_wr_rx_rd_const const_ctx /* Constant TX_WR_RX_RD */;
8657};
8658
8659/*
8660 * tce_rx_wr_tx_rd_const $$KEEP_ENDIANNESS$$
8661 */
8662struct fcoe_tce_rx_wr_tx_rd_const
8663{
8664 uint32_t data_2_trns /* The maximum amount of data that would be transferred in this task */;
8665 uint32_t init_flags;
8666 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID (0xFFFFFF<<0) /* BitField init_flags The CID of the connection (used by the CHIP) */
8667 #define FCOE_TCE_RX_WR_TX_RD_CONST_CID_SHIFT 0
8668 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0 (0xFF<<24) /* BitField init_flags */
8669 #define FCOE_TCE_RX_WR_TX_RD_CONST_RSRV0_SHIFT 24
8670};
8671
8672/*
8673 * tce_rx_wr_tx_rd_var $$KEEP_ENDIANNESS$$
8674 */
8675struct fcoe_tce_rx_wr_tx_rd_var
8676{
8677 uint16_t rx_flags;
8678 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1 (0xF<<0) /* BitField rx_flags */
8679 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV1_SHIFT 0
8680 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE (0x7<<4) /* BitField rx_flags The number of RQ WQEs that were consumed (for sense data only) */
8681 #define FCOE_TCE_RX_WR_TX_RD_VAR_NUM_RQ_WQE_SHIFT 4
8682 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ (0x1<<7) /* BitField rx_flags Confirmation request indication */
8683 #define FCOE_TCE_RX_WR_TX_RD_VAR_CONF_REQ_SHIFT 7
8684 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE (0xF<<8) /* BitField rx_flags The RX state of the task */
8685 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_STATE_SHIFT 8
8686 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME (0x1<<12) /* BitField rx_flags Indication on expecting to receive the first frame from target */
8687 #define FCOE_TCE_RX_WR_TX_RD_VAR_EXP_FIRST_FRAME_SHIFT 12
8688 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT (0x1<<13) /* BitField rx_flags RX Sequence initiative indication */
8689 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_SEQ_INIT_SHIFT 13
8690 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2 (0x1<<14) /* BitField rx_flags */
8691 #define FCOE_TCE_RX_WR_TX_RD_VAR_RSRV2_SHIFT 14
8692 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID (0x1<<15) /* BitField rx_flags Indication of RX valid task */
8693 #define FCOE_TCE_RX_WR_TX_RD_VAR_RX_VALID_SHIFT 15
8694 uint16_t rx_id /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */;
8695 struct fcoe_fcp_xfr_rdy_payload fcp_xfr_rdy /* Data-In/ELS/BLS information */;
8696};
8697
8698/*
8699 * tce_rx_wr_tx_rd $$KEEP_ENDIANNESS$$
8700 */
8701struct fcoe_tce_rx_wr_tx_rd
8702{
8703 struct fcoe_tce_rx_wr_tx_rd_const const_ctx /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */;
8704 struct fcoe_tce_rx_wr_tx_rd_var var_ctx /* The RX_ID read from incoming frame and to be used in subsequent transmitting frames */;
8705};
8706
8707/*
8708 * tce_rx_only $$KEEP_ENDIANNESS$$
8709 */
8710struct fcoe_tce_rx_only
8711{
8712 struct fcoe_rx_seq_ctx rx_seq_ctx /* The context of current receiving Sequence */;
8713 union fcoe_rx_wr_union_ctx union_ctx /* Read flow info/ Completion flow info */;
8714};
8715
8716/*
8717 * task_ctx_entry $$KEEP_ENDIANNESS$$
8718 */
8719struct fcoe_task_ctx_entry
8720{
8721 struct fcoe_tce_tx_only txwr_only /* TX processing shall be the only one to read/write to this section */;
8722 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX shall read from this section */;
8723 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd /* RX processing shall write and TX shall read from this section */;
8724 struct fcoe_tce_rx_only rxwr_only /* RX processing shall be the only one to read/write to this section */;
8725};
8726
8727
8728/*
8729 * FCoE XFRQ element $$KEEP_ENDIANNESS$$
8730 */
8731struct fcoe_xfrqe
8732{
8733 uint16_t wqe;
8734 #define FCOE_XFRQE_TASK_ID (0x7FFF<<0) /* BitField wqe The task ID (OX_ID) to be processed */
8735 #define FCOE_XFRQE_TASK_ID_SHIFT 0
8736 #define FCOE_XFRQE_TOGGLE_BIT (0x1<<15) /* BitField wqe Toggle bit updated by the driver */
8737 #define FCOE_XFRQE_TOGGLE_BIT_SHIFT 15
8738};
8739
8740
8741/*
8742 * Cached SGEs $$KEEP_ENDIANNESS$$
8743 */
8744struct common_fcoe_sgl
8745{
8746 struct fcoe_bd_ctx sge[3];
8747};
8748
8749
8750/*
8751 * FCoE SQ\XFRQ element
8752 */
8753struct fcoe_cached_wqe
8754{
8755 struct fcoe_sqe sqe /* SQ WQE */;
8756 struct fcoe_xfrqe xfrqe /* XFRQ WQE */;
8757};
8758
8759
8760/*
8761 * FCoE connection enable\disable params passed by driver to FW in FCoE enable ramrod $$KEEP_ENDIANNESS$$
8762 */
8763struct fcoe_conn_enable_disable_ramrod_params
8764{
8765 struct fcoe_kwqe_conn_enable_disable enable_disable_kwqe;
8766};
8767
8768
8769/*
8770 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod $$KEEP_ENDIANNESS$$
8771 */
8772struct fcoe_conn_offload_ramrod_params
8773{
8774 struct fcoe_kwqe_conn_offload1 offload_kwqe1;
8775 struct fcoe_kwqe_conn_offload2 offload_kwqe2;
8776 struct fcoe_kwqe_conn_offload3 offload_kwqe3;
8777 struct fcoe_kwqe_conn_offload4 offload_kwqe4;
8778};
8779
8780
8781struct ustorm_fcoe_mng_ctx
8782{
8783#if defined(__BIG_ENDIAN)
8784 uint8_t mid_seq_proc_flag /* Middle Sequence received processing */;
8785 uint8_t tce_in_cam_flag /* TCE in CAM indication */;
8786 uint8_t tce_on_ior_flag /* TCE on IOR indication (TCE on IORs but not necessarily in CAM) */;
8787 uint8_t en_cached_tce_flag /* TCE cached functionality enabled indication */;
8788#elif defined(__LITTLE_ENDIAN)
8789 uint8_t en_cached_tce_flag /* TCE cached functionality enabled indication */;
8790 uint8_t tce_on_ior_flag /* TCE on IOR indication (TCE on IORs but not necessarily in CAM) */;
8791 uint8_t tce_in_cam_flag /* TCE in CAM indication */;
8792 uint8_t mid_seq_proc_flag /* Middle Sequence received processing */;
8793#endif
8794#if defined(__BIG_ENDIAN)
8795 uint8_t tce_cam_addr /* CAM address of task context */;
8796 uint8_t cached_conn_flag /* Cached locked connection indication */;
8797 uint16_t rsrv0;
8798#elif defined(__LITTLE_ENDIAN)
8799 uint16_t rsrv0;
8800 uint8_t cached_conn_flag /* Cached locked connection indication */;
8801 uint8_t tce_cam_addr /* CAM address of task context */;
8802#endif
8803#if defined(__BIG_ENDIAN)
8804 uint16_t dma_tce_ram_addr /* RAM address of task context when executing DMA operations (read/write) */;
8805 uint16_t tce_ram_addr /* RAM address of task context (might be in cached table or in scratchpad) */;
8806#elif defined(__LITTLE_ENDIAN)
8807 uint16_t tce_ram_addr /* RAM address of task context (might be in cached table or in scratchpad) */;
8808 uint16_t dma_tce_ram_addr /* RAM address of task context when executing DMA operations (read/write) */;
8809#endif
8810#if defined(__BIG_ENDIAN)
8811 uint16_t ox_id /* Last OX_ID that has been used */;
8812 uint16_t wr_done_seq /* Last task write done in the specific connection */;
8813#elif defined(__LITTLE_ENDIAN)
8814 uint16_t wr_done_seq /* Last task write done in the specific connection */;
8815 uint16_t ox_id /* Last OX_ID that has been used */;
8816#endif
8817 struct regpair_t task_addr /* Last task address in used */;
8818};
8819
8820/*
8821 * Parameters initialized during offloaded according to FLOGI/PLOGI/PRLI and used in FCoE context section
8822 */
8823struct ustorm_fcoe_params
8824{
8825#if defined(__BIG_ENDIAN)
8826 uint16_t fcoe_conn_id /* The connection ID that would be used by driver to identify the conneciton */;
8827 uint16_t flags;
8828 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */
8829 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8830 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */
8831 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
8832 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */
8833 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
8834 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */
8835 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
8836 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */
8837 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
8838 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* BitField flags CQ toggle bit */
8839 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
8840 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* BitField flags XFRQ toggle bit */
8841 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
8842 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* BitField flags CONFQ toggle bit */
8843 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
8844 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* BitField flags */
8845 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
8846#elif defined(__LITTLE_ENDIAN)
8847 uint16_t flags;
8848 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS (0x1<<0) /* BitField flags Supporting multiple N_Port IDs indication, received during FLOGI */
8849 #define USTORM_FCOE_PARAMS_B_MUL_N_PORT_IDS_SHIFT 0
8850 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES (0x1<<1) /* BitField flags E_D_TOV resolution (0 - msec, 1 - nsec), negotiated in PLOGI */
8851 #define USTORM_FCOE_PARAMS_B_E_D_TOV_RES_SHIFT 1
8852 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT (0x1<<2) /* BitField flags Continuously increasing SEQ_CNT indication, received during PLOGI */
8853 #define USTORM_FCOE_PARAMS_B_CONT_INCR_SEQ_CNT_SHIFT 2
8854 #define USTORM_FCOE_PARAMS_B_CONF_REQ (0x1<<3) /* BitField flags Confirmation request supported */
8855 #define USTORM_FCOE_PARAMS_B_CONF_REQ_SHIFT 3
8856 #define USTORM_FCOE_PARAMS_B_REC_VALID (0x1<<4) /* BitField flags REC allowed */
8857 #define USTORM_FCOE_PARAMS_B_REC_VALID_SHIFT 4
8858 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT (0x1<<5) /* BitField flags CQ toggle bit */
8859 #define USTORM_FCOE_PARAMS_B_CQ_TOGGLE_BIT_SHIFT 5
8860 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT (0x1<<6) /* BitField flags XFRQ toggle bit */
8861 #define USTORM_FCOE_PARAMS_B_XFRQ_TOGGLE_BIT_SHIFT 6
8862 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT (0x1<<7) /* BitField flags CONFQ toggle bit */
8863 #define USTORM_FCOE_PARAMS_B_CONFQ_TOGGLE_BIT_SHIFT 7
8864 #define USTORM_FCOE_PARAMS_RSRV0 (0xFF<<8) /* BitField flags */
8865 #define USTORM_FCOE_PARAMS_RSRV0_SHIFT 8
8866 uint16_t fcoe_conn_id /* The connection ID that would be used by driver to identify the conneciton */;
8867#endif
8868#if defined(__BIG_ENDIAN)
8869 uint8_t hc_csdm_byte_en /* Host coalescing Cstorm RAM address byte enable */;
8870 uint8_t func_id /* Function id */;
8871 uint8_t port_id /* Port id */;
8872 uint8_t vnic_id /* Vnic id */;
8873#elif defined(__LITTLE_ENDIAN)
8874 uint8_t vnic_id /* Vnic id */;
8875 uint8_t port_id /* Port id */;
8876 uint8_t func_id /* Function id */;
8877 uint8_t hc_csdm_byte_en /* Host coalescing Cstorm RAM address byte enable */;
8878#endif
8879#if defined(__BIG_ENDIAN)
8880 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */;
8881 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */;
8882#elif defined(__LITTLE_ENDIAN)
8883 uint16_t rx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by us, sent during FLOGI/PLOGI */;
8884 uint16_t rx_total_conc_seqs /* Total concurrent Sequences for all Classes supported by us, sent during PLOGI */;
8885#endif
8886#if defined(__BIG_ENDIAN)
8887 uint8_t task_pbe_idx_off /* The first PBE for this specific task list in RAM */;
8888 uint8_t task_in_page_log_size /* Number of tasks in page (log 2) */;
8889 uint16_t rx_max_conc_seqs /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */;
8890#elif defined(__LITTLE_ENDIAN)
8891 uint16_t rx_max_conc_seqs /* Maximum Concurrent Sequences for Class 3 supported by us, sent during PLOGI */;
8892 uint8_t task_in_page_log_size /* Number of tasks in page (log 2) */;
8893 uint8_t task_pbe_idx_off /* The first PBE for this specific task list in RAM */;
8894#endif
8895};
8896
8897/*
8898 * FCoE 16-bits index structure
8899 */
8900struct fcoe_idx16_fields
8901{
8902 uint16_t fields;
8903 #define FCOE_IDX16_FIELDS_IDX (0x7FFF<<0) /* BitField fields */
8904 #define FCOE_IDX16_FIELDS_IDX_SHIFT 0
8905 #define FCOE_IDX16_FIELDS_MSB (0x1<<15) /* BitField fields */
8906 #define FCOE_IDX16_FIELDS_MSB_SHIFT 15
8907};
8908
8909/*
8910 * FCoE 16-bits index union
8911 */
8912union fcoe_idx16_field_union
8913{
8914 struct fcoe_idx16_fields fields /* Parameters field */;
8915 uint16_t val /* Global value */;
8916};
8917
8918/*
8919 * Parameters required for placement according to SGL
8920 */
8921struct ustorm_fcoe_data_place_mng
8922{
8923#if defined(__BIG_ENDIAN)
8924 uint16_t sge_off;
8925 uint8_t num_sges /* Number of SGEs left to be used on context */;
8926 uint8_t sge_idx /* 0xFF value indicated loading SGL */;
8927#elif defined(__LITTLE_ENDIAN)
8928 uint8_t sge_idx /* 0xFF value indicated loading SGL */;
8929 uint8_t num_sges /* Number of SGEs left to be used on context */;
8930 uint16_t sge_off;
8931#endif
8932};
8933
8934/*
8935 * Parameters required for placement according to SGL
8936 */
8937struct ustorm_fcoe_data_place
8938{
8939 struct ustorm_fcoe_data_place_mng cached_mng /* 0xFF value indicated loading SGL */;
8940 struct fcoe_bd_ctx cached_sge[2];
8941};
8942
8943/*
8944 * TX processing shall write and RX processing shall read from this section
8945 */
8946union fcoe_u_tce_tx_wr_rx_rd_union
8947{
8948 struct fcoe_abts_info abts /* ABTS information */;
8949 struct fcoe_cleanup_info cleanup /* Cleanup information */;
8950 struct fcoe_fw_tx_seq_ctx tx_seq_ctx /* TX sequence context */;
8951 uint32_t opaque[2];
8952};
8953
8954/*
8955 * TX processing shall write and RX processing shall read from this section
8956 */
8957struct fcoe_u_tce_tx_wr_rx_rd
8958{
8959 union fcoe_u_tce_tx_wr_rx_rd_union union_ctx /* FW DATA_OUT/CLEANUP information */;
8960 struct fcoe_tce_tx_wr_rx_rd_const const_ctx /* TX processing shall write and RX shall read from this section */;
8961};
8962
8963struct ustorm_fcoe_tce
8964{
8965 struct fcoe_u_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX shall read from this section */;
8966 struct fcoe_tce_rx_wr_tx_rd rxwr_txrd /* RX processing shall write and TX shall read from this section */;
8967 struct fcoe_tce_rx_only rxwr /* RX processing shall be the only one to read/write to this section */;
8968};
8969
8970struct ustorm_fcoe_cache_ctx
8971{
8972 uint32_t rsrv0;
8973 struct ustorm_fcoe_data_place data_place;
8974 struct ustorm_fcoe_tce tce /* Task context */;
8975};
8976
8977/*
8978 * Ustorm FCoE Storm Context
8979 */
8980struct ustorm_fcoe_st_context
8981{
8982 struct ustorm_fcoe_mng_ctx mng_ctx /* Managing the processing of the flow */;
8983 struct ustorm_fcoe_params fcoe_params /* Align to 128 bytes */;
8984 struct regpair_t cq_base_addr /* CQ current page host address */;
8985 struct regpair_t rq_pbl_base /* PBL host address for RQ */;
8986 struct regpair_t rq_cur_page_addr /* RQ current page host address */;
8987 struct regpair_t confq_pbl_base_addr /* Base address of the CONFQ page list */;
8988 struct regpair_t conn_db_base /* Connection data base address in host memory where RQ producer and CQ arm bit reside in */;
8989 struct regpair_t xfrq_base_addr /* XFRQ base host address */;
8990 struct regpair_t lcq_base_addr /* LCQ base host address */;
8991#if defined(__BIG_ENDIAN)
8992 union fcoe_idx16_field_union rq_cons /* RQ consumer advance for each RQ WQE consuming */;
8993 union fcoe_idx16_field_union rq_prod /* RQ producer update by driver and read by FW (should be initialized to RQ size) */;
8994#elif defined(__LITTLE_ENDIAN)
8995 union fcoe_idx16_field_union rq_prod /* RQ producer update by driver and read by FW (should be initialized to RQ size) */;
8996 union fcoe_idx16_field_union rq_cons /* RQ consumer advance for each RQ WQE consuming */;
8997#endif
8998#if defined(__BIG_ENDIAN)
8999 uint16_t xfrq_prod /* XFRQ producer (No consumer is needed since Q can not be overloaded) */;
9000 uint16_t cq_cons /* CQ consumer copy of last update from driver (Q can not be overloaded) */;
9001#elif defined(__LITTLE_ENDIAN)
9002 uint16_t cq_cons /* CQ consumer copy of last update from driver (Q can not be overloaded) */;
9003 uint16_t xfrq_prod /* XFRQ producer (No consumer is needed since Q can not be overloaded) */;
9004#endif
9005#if defined(__BIG_ENDIAN)
9006 uint16_t lcq_cons /* lcq consumer */;
9007 uint16_t hc_cram_address /* Host coalescing Cstorm RAM address */;
9008#elif defined(__LITTLE_ENDIAN)
9009 uint16_t hc_cram_address /* Host coalescing Cstorm RAM address */;
9010 uint16_t lcq_cons /* lcq consumer */;
9011#endif
9012#if defined(__BIG_ENDIAN)
9013 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */;
9014 uint16_t confq_prod /* CONFQ producer */;
9015#elif defined(__LITTLE_ENDIAN)
9016 uint16_t confq_prod /* CONFQ producer */;
9017 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */;
9018#endif
9019#if defined(__BIG_ENDIAN)
9020 uint8_t hc_csdm_agg_int /* Host coalescing CSDM aggregative interrupts */;
9021 uint8_t rsrv2;
9022 uint8_t available_rqes /* Available RQEs */;
9023 uint8_t sp_q_flush_cnt /* The remain number of queues to be flushed (in QM) */;
9024#elif defined(__LITTLE_ENDIAN)
9025 uint8_t sp_q_flush_cnt /* The remain number of queues to be flushed (in QM) */;
9026 uint8_t available_rqes /* Available RQEs */;
9027 uint8_t rsrv2;
9028 uint8_t hc_csdm_agg_int /* Host coalescing CSDM aggregative interrupts */;
9029#endif
9030#if defined(__BIG_ENDIAN)
9031 uint16_t num_pend_tasks /* Number of pending tasks */;
9032 uint16_t pbf_ack_ram_addr /* PBF TX sequence ACK ram address */;
9033#elif defined(__LITTLE_ENDIAN)
9034 uint16_t pbf_ack_ram_addr /* PBF TX sequence ACK ram address */;
9035 uint16_t num_pend_tasks /* Number of pending tasks */;
9036#endif
9037 struct ustorm_fcoe_cache_ctx cache_ctx /* Cached context */;
9038};
9039
9040/*
9041 * The FCoE non-aggregative context of Tstorm
9042 */
9043struct tstorm_fcoe_st_context
9044{
9045 struct regpair_t reserved0;
9046 struct regpair_t reserved1;
9047};
9048
9049/*
9050 * Ethernet context section
9051 */
9052struct xstorm_fcoe_eth_context_section
9053{
9054#if defined(__BIG_ENDIAN)
9055 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
9056 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
9057 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
9058 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
9059#elif defined(__LITTLE_ENDIAN)
9060 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
9061 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
9062 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
9063 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
9064#endif
9065#if defined(__BIG_ENDIAN)
9066 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
9067 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
9068 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
9069 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
9070#elif defined(__LITTLE_ENDIAN)
9071 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
9072 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
9073 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
9074 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
9075#endif
9076#if defined(__BIG_ENDIAN)
9077 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */;
9078 uint16_t params;
9079 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField params part of PBF Header Builder Command */
9080 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9081 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField params Canonical format indicator, part of PBF Header Builder Command */
9082 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
9083 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField params part of PBF Header Builder Command */
9084 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
9085#elif defined(__LITTLE_ENDIAN)
9086 uint16_t params;
9087 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField params part of PBF Header Builder Command */
9088 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
9089 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField params Canonical format indicator, part of PBF Header Builder Command */
9090 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_CFI_SHIFT 12
9091 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField params part of PBF Header Builder Command */
9092 #define XSTORM_FCOE_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
9093 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */;
9094#endif
9095#if defined(__BIG_ENDIAN)
9096 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
9097 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
9098 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
9099 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
9100#elif defined(__LITTLE_ENDIAN)
9101 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
9102 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
9103 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
9104 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
9105#endif
9106};
9107
9108/*
9109 * Flags used in FCoE context section - 1 byte
9110 */
9111struct xstorm_fcoe_context_flags
9112{
9113 uint8_t flags;
9114 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q (0x3<<0) /* BitField flags The current queue in process */
9115 #define XSTORM_FCOE_CONTEXT_FLAGS_B_PROC_Q_SHIFT 0
9116 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ (0x1<<2) /* BitField flags Middle of Sequence indication */
9117 #define XSTORM_FCOE_CONTEXT_FLAGS_B_MID_SEQ_SHIFT 2
9118 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ (0x1<<3) /* BitField flags Indicates whether the SQ is blocked since we are in the middle of ABTS/Cleanup procedure */
9119 #define XSTORM_FCOE_CONTEXT_FLAGS_B_BLOCK_SQ_SHIFT 3
9120 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT (0x1<<4) /* BitField flags REC support */
9121 #define XSTORM_FCOE_CONTEXT_FLAGS_B_REC_SUPPORT_SHIFT 4
9122 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE (0x1<<5) /* BitField flags SQ toggle bit */
9123 #define XSTORM_FCOE_CONTEXT_FLAGS_B_SQ_TOGGLE_SHIFT 5
9124 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE (0x1<<6) /* BitField flags XFRQ toggle bit */
9125 #define XSTORM_FCOE_CONTEXT_FLAGS_B_XFRQ_TOGGLE_SHIFT 6
9126 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN (0x1<<7) /* BitField flags Are we using VNTag inner vlan - in this case we have to read it on every VNTag version change */
9127 #define XSTORM_FCOE_CONTEXT_FLAGS_B_VNTAG_VLAN_SHIFT 7
9128};
9129
9130struct xstorm_fcoe_tce
9131{
9132 struct fcoe_tce_tx_only txwr /* TX processing shall be the only one to read/write to this section */;
9133 struct fcoe_tce_tx_wr_rx_rd txwr_rxrd /* TX processing shall write and RX processing shall read from this section */;
9134};
9135
9136/*
9137 * FCP_DATA parameters required for transmission
9138 */
9139struct xstorm_fcoe_fcp_data
9140{
9141 uint32_t io_rem /* IO remainder */;
9142#if defined(__BIG_ENDIAN)
9143 uint16_t cached_sge_off;
9144 uint8_t cached_num_sges /* Number of SGEs on context */;
9145 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */;
9146#elif defined(__LITTLE_ENDIAN)
9147 uint8_t cached_sge_idx /* 0xFF value indicated loading SGL */;
9148 uint8_t cached_num_sges /* Number of SGEs on context */;
9149 uint16_t cached_sge_off;
9150#endif
9151 uint32_t buf_addr_hi_0 /* Higher buffer host address */;
9152 uint32_t buf_addr_lo_0 /* Lower buffer host address */;
9153#if defined(__BIG_ENDIAN)
9154 uint16_t num_of_pending_tasks /* Num of pending tasks */;
9155 uint16_t buf_len_0 /* Buffer length (in bytes) */;
9156#elif defined(__LITTLE_ENDIAN)
9157 uint16_t buf_len_0 /* Buffer length (in bytes) */;
9158 uint16_t num_of_pending_tasks /* Num of pending tasks */;
9159#endif
9160 uint32_t buf_addr_hi_1 /* Higher buffer host address */;
9161 uint32_t buf_addr_lo_1 /* Lower buffer host address */;
9162#if defined(__BIG_ENDIAN)
9163 uint16_t task_pbe_idx_off /* Task pbe index offset */;
9164 uint16_t buf_len_1 /* Buffer length (in bytes) */;
9165#elif defined(__LITTLE_ENDIAN)
9166 uint16_t buf_len_1 /* Buffer length (in bytes) */;
9167 uint16_t task_pbe_idx_off /* Task pbe index offset */;
9168#endif
9169 uint32_t buf_addr_hi_2 /* Higher buffer host address */;
9170 uint32_t buf_addr_lo_2 /* Lower buffer host address */;
9171#if defined(__BIG_ENDIAN)
9172 uint16_t ox_id /* OX_ID */;
9173 uint16_t buf_len_2 /* Buffer length (in bytes) */;
9174#elif defined(__LITTLE_ENDIAN)
9175 uint16_t buf_len_2 /* Buffer length (in bytes) */;
9176 uint16_t ox_id /* OX_ID */;
9177#endif
9178};
9179
9180/*
9181 * Continuation of Flags used in FCoE context section - 1 byte
9182 */
9183struct xstorm_fcoe_context_flags_cont
9184{
9185 uint8_t flags;
9186 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE (0x1<<0) /* BitField flags CONFQ toggle bit */
9187 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_B_CONFQ_TOGGLE_SHIFT 0
9188 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG (0x1<<1) /* BitField flags Is any inner vlan exist */
9189 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_VLAN_FLAG_SHIFT 1
9190 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED (0x3F<<2) /* BitField flags */
9191 #define XSTORM_FCOE_CONTEXT_FLAGS_CONT_RESERVED_SHIFT 2
9192};
9193
9194/*
9195 * vlan configuration
9196 */
9197struct xstorm_fcoe_vlan_conf
9198{
9199 uint8_t vlan_conf;
9200 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY (0x7<<0) /* BitField vlan_conf Original inner vlan priority */
9201 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_PRIORITY_SHIFT 0
9202 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG (0x1<<3) /* BitField vlan_conf Original inner vlan flag */
9203 #define XSTORM_FCOE_VLAN_CONF_INNER_VLAN_FLAG_SHIFT 3
9204 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY (0x7<<4) /* BitField vlan_conf Original outer vlan priority */
9205 #define XSTORM_FCOE_VLAN_CONF_OUTER_VLAN_PRIORITY_SHIFT 4
9206 #define XSTORM_FCOE_VLAN_CONF_RESERVED (0x1<<7) /* BitField vlan_conf */
9207 #define XSTORM_FCOE_VLAN_CONF_RESERVED_SHIFT 7
9208};
9209
9210/*
9211 * FCoE 16-bits vlan structure
9212 */
9213struct fcoe_vlan_fields
9214{
9215 uint16_t fields;
9216 #define FCOE_VLAN_FIELDS_VID (0xFFF<<0) /* BitField fields */
9217 #define FCOE_VLAN_FIELDS_VID_SHIFT 0
9218 #define FCOE_VLAN_FIELDS_CLI (0x1<<12) /* BitField fields */
9219 #define FCOE_VLAN_FIELDS_CLI_SHIFT 12
9220 #define FCOE_VLAN_FIELDS_PRI (0x7<<13) /* BitField fields */
9221 #define FCOE_VLAN_FIELDS_PRI_SHIFT 13
9222};
9223
9224/*
9225 * FCoE 16-bits vlan union
9226 */
9227union fcoe_vlan_field_union
9228{
9229 struct fcoe_vlan_fields fields /* Parameters field */;
9230 uint16_t val /* Global value */;
9231};
9232
9233/*
9234 * FCoE 16-bits vlan, vif union
9235 */
9236union fcoe_vlan_vif_field_union
9237{
9238 union fcoe_vlan_field_union vlan /* Vlan */;
9239 uint16_t vif /* VIF */;
9240};
9241
9242/*
9243 * FCoE context section
9244 */
9245struct xstorm_fcoe_context_section
9246{
9247#if defined(__BIG_ENDIAN)
9248 uint8_t cs_ctl /* cs ctl */;
9249 uint8_t s_id[3] /* Source ID, received during FLOGI */;
9250#elif defined(__LITTLE_ENDIAN)
9251 uint8_t s_id[3] /* Source ID, received during FLOGI */;
9252 uint8_t cs_ctl /* cs ctl */;
9253#endif
9254#if defined(__BIG_ENDIAN)
9255 uint8_t rctl /* rctl */;
9256 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */;
9257#elif defined(__LITTLE_ENDIAN)
9258 uint8_t d_id[3] /* Destination ID, received after inquiry of the fabric network */;
9259 uint8_t rctl /* rctl */;
9260#endif
9261#if defined(__BIG_ENDIAN)
9262 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */;
9263 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */;
9264#elif defined(__LITTLE_ENDIAN)
9265 uint16_t tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */;
9266 uint16_t sq_xfrq_lcq_confq_size /* SQ/XFRQ/LCQ/CONFQ size */;
9267#endif
9268 uint32_t lcq_prod /* LCQ producer value */;
9269#if defined(__BIG_ENDIAN)
9270 uint8_t port_id /* Port ID */;
9271 uint8_t func_id /* Function ID */;
9272 uint8_t seq_id /* SEQ ID counter to be used in transmitted FC header */;
9273 struct xstorm_fcoe_context_flags tx_flags;
9274#elif defined(__LITTLE_ENDIAN)
9275 struct xstorm_fcoe_context_flags tx_flags;
9276 uint8_t seq_id /* SEQ ID counter to be used in transmitted FC header */;
9277 uint8_t func_id /* Function ID */;
9278 uint8_t port_id /* Port ID */;
9279#endif
9280#if defined(__BIG_ENDIAN)
9281 uint16_t mtu /* MTU */;
9282 uint8_t func_mode /* Function mode */;
9283 uint8_t vnic_id /* Vnic ID */;
9284#elif defined(__LITTLE_ENDIAN)
9285 uint8_t vnic_id /* Vnic ID */;
9286 uint8_t func_mode /* Function mode */;
9287 uint16_t mtu /* MTU */;
9288#endif
9289 struct regpair_t confq_curr_page_addr /* The current page of CONFQ to be processed */;
9290 struct fcoe_cached_wqe cached_wqe[8] /* Up to 8 SQ/XFRQ WQEs read in one shot */;
9291 struct regpair_t lcq_base_addr /* The page address which the LCQ resides in host memory */;
9292 struct xstorm_fcoe_tce tce /* TX section task context */;
9293 struct xstorm_fcoe_fcp_data fcp_data /* The parameters required for FCP_DATA Sequences transmission */;
9294#if defined(__BIG_ENDIAN)
9295 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by traget, received during PLOGI */;
9296 struct xstorm_fcoe_context_flags_cont tx_flags_cont;
9297 uint8_t dcb_val /* DCB val - let us know if dcb info changes */;
9298 uint8_t data_pb_cmd_size /* Data pb cmd size */;
9299#elif defined(__LITTLE_ENDIAN)
9300 uint8_t data_pb_cmd_size /* Data pb cmd size */;
9301 uint8_t dcb_val /* DCB val - let us know if dcb info changes */;
9302 struct xstorm_fcoe_context_flags_cont tx_flags_cont;
9303 uint8_t tx_max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by traget, received during PLOGI */;
9304#endif
9305#if defined(__BIG_ENDIAN)
9306 uint16_t fcoe_tx_stat_params_ram_addr /* stat Ram Addr */;
9307 uint16_t fcoe_tx_fc_seq_ram_addr /* Tx FC sequence Ram Addr */;
9308#elif defined(__LITTLE_ENDIAN)
9309 uint16_t fcoe_tx_fc_seq_ram_addr /* Tx FC sequence Ram Addr */;
9310 uint16_t fcoe_tx_stat_params_ram_addr /* stat Ram Addr */;
9311#endif
9312#if defined(__BIG_ENDIAN)
9313 uint8_t fcp_cmd_line_credit;
9314 uint8_t eth_hdr_size /* Ethernet header size without eth type */;
9315 uint16_t pbf_addr /* PBF addr */;
9316#elif defined(__LITTLE_ENDIAN)
9317 uint16_t pbf_addr /* PBF addr */;
9318 uint8_t eth_hdr_size /* Ethernet header size without eth type */;
9319 uint8_t fcp_cmd_line_credit;
9320#endif
9321#if defined(__BIG_ENDIAN)
9322 union fcoe_vlan_vif_field_union multi_func_val /* Outer vlan vif union */;
9323 uint8_t page_log_size /* Page log size */;
9324 struct xstorm_fcoe_vlan_conf orig_vlan_conf /* original vlan configuration, used when we switch from dcb enable to dcb disabled */;
9325#elif defined(__LITTLE_ENDIAN)
9326 struct xstorm_fcoe_vlan_conf orig_vlan_conf /* original vlan configuration, used when we switch from dcb enable to dcb disabled */;
9327 uint8_t page_log_size /* Page log size */;
9328 union fcoe_vlan_vif_field_union multi_func_val /* Outer vlan vif union */;
9329#endif
9330#if defined(__BIG_ENDIAN)
9331 uint16_t fcp_cmd_frame_size /* FCP_CMD frame size */;
9332 uint16_t pbf_addr_ff /* PBF addr with ff */;
9333#elif defined(__LITTLE_ENDIAN)
9334 uint16_t pbf_addr_ff /* PBF addr with ff */;
9335 uint16_t fcp_cmd_frame_size /* FCP_CMD frame size */;
9336#endif
9337#if defined(__BIG_ENDIAN)
9338 uint8_t vlan_num /* Vlan number */;
9339 uint8_t cos /* Cos */;
9340 uint8_t cache_xfrq_cons /* Cache xferq consumer */;
9341 uint8_t cache_sq_cons /* Cache sq consumer */;
9342#elif defined(__LITTLE_ENDIAN)
9343 uint8_t cache_sq_cons /* Cache sq consumer */;
9344 uint8_t cache_xfrq_cons /* Cache xferq consumer */;
9345 uint8_t cos /* Cos */;
9346 uint8_t vlan_num /* Vlan number */;
9347#endif
9348 uint32_t verify_tx_seq /* Sequence number of last transmitted sequence in order to verify target did not send FCP_RSP before the actual transmission of PBF from the SGL */;
9349};
9350
9351/*
9352 * Xstorm FCoE Storm Context
9353 */
9354struct xstorm_fcoe_st_context
9355{
9356 struct xstorm_fcoe_eth_context_section eth;
9357 struct xstorm_fcoe_context_section fcoe;
9358};
9359
9360/*
9361 * Fcoe connection context
9362 */
9363struct fcoe_context
9364{
9365 struct ustorm_fcoe_st_context ustorm_st_context /* Ustorm storm context */;
9366 struct tstorm_fcoe_st_context tstorm_st_context /* Tstorm storm context */;
9367 struct xstorm_fcoe_ag_context xstorm_ag_context /* Xstorm aggregative context */;
9368 struct tstorm_fcoe_ag_context tstorm_ag_context /* Tstorm aggregative context */;
9369 struct ustorm_fcoe_ag_context ustorm_ag_context /* Ustorm aggregative context */;
9370 struct timers_block_context timers_context /* Timers block context */;
9371 struct xstorm_fcoe_st_context xstorm_st_context /* Xstorm storm context */;
9372};
9373
9374
9375/*
9376 * FCoE init params passed by driver to FW in FCoE init ramrod $$KEEP_ENDIANNESS$$
9377 */
9378struct fcoe_init_ramrod_params
9379{
9380 struct fcoe_kwqe_init1 init_kwqe1;
9381 struct fcoe_kwqe_init2 init_kwqe2;
9382 struct fcoe_kwqe_init3 init_kwqe3;
9383 struct regpair_t eq_pbl_base /* Physical address of PBL */;
9384 uint32_t eq_pbl_size /* PBL size */;
9385 uint32_t reserved2;
9386 uint16_t eq_prod /* EQ prdocuer */;
9387 uint16_t sb_num /* Status block number */;
9388 uint8_t sb_id /* Status block id (EQ consumer) */;
9389 uint8_t reserved0;
9390 uint16_t reserved1;
9391};
9392
9393
9394/*
9395 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod $$KEEP_ENDIANNESS$$
9396 */
9397struct fcoe_stat_ramrod_params
9398{
9399 struct fcoe_kwqe_stat stat_kwqe;
9400};
9401
9402
9403/*
9404 * CQ DB CQ producer and pending completion counter
9405 */
9406struct iscsi_cq_db_prod_pnd_cmpltn_cnt
9407{
9408#if defined(__BIG_ENDIAN)
9409 uint16_t cntr /* CQ pending completion counter */;
9410 uint16_t prod /* Ustorm CQ producer , updated by Ustorm */;
9411#elif defined(__LITTLE_ENDIAN)
9412 uint16_t prod /* Ustorm CQ producer , updated by Ustorm */;
9413 uint16_t cntr /* CQ pending completion counter */;
9414#endif
9415};
9416
9417/*
9418 * CQ DB pending completion ITT array
9419 */
9420struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr
9421{
9422 struct iscsi_cq_db_prod_pnd_cmpltn_cnt prod_pend_comp[8] /* CQ pending completion ITT array */;
9423};
9424
9425/*
9426 * CQ DB pending completion ITT array
9427 */
9428struct iscsi_cq_db_pnd_comp_itt_arr
9429{
9430 uint16_t itt[8] /* CQ pending completion ITT array */;
9431};
9432
9433/*
9434 * Cstorm CQ sequence to notify array, updated by driver
9435 */
9436struct iscsi_cq_db_sqn_2_notify_arr
9437{
9438 uint16_t sqn[8] /* Cstorm CQ sequence to notify array, updated by driver */;
9439};
9440
9441/*
9442 * CQ DB
9443 */
9444struct iscsi_cq_db
9445{
9446 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_u_prod_pend_comp_ctr_arr /* Ustorm CQ producer and pending completion counter array, updated by Ustorm */;
9447 struct iscsi_cq_db_pnd_comp_itt_arr cq_c_pend_comp_itt_arr /* Cstorm CQ pending completion ITT array, updated by Cstorm */;
9448 struct iscsi_cq_db_sqn_2_notify_arr cq_drv_sqn_2_notify_arr /* Cstorm CQ sequence to notify array, updated by driver */;
9449 uint32_t reserved[4] /* 16 byte allignment */;
9450};
9451
9452
9453/*
9454 * iSCSI KCQ CQE parameters
9455 */
9456union iscsi_kcqe_params
9457{
9458 uint32_t reserved0[4];
9459};
9460
9461/*
9462 * iSCSI KCQ CQE
9463 */
9464struct iscsi_kcqe
9465{
9466 uint32_t iscsi_conn_id /* Drivers connection ID (only 16 bits are used) */;
9467 uint32_t completion_status /* 0=command completed successfully, 1=command failed */;
9468 uint32_t iscsi_conn_context_id /* Context ID of the iSCSI connection */;
9469 union iscsi_kcqe_params params /* command-specific parameters */;
9470#if defined(__BIG_ENDIAN)
9471 uint8_t flags;
9472 #define ISCSI_KCQE_RESERVED0 (0x7<<0) /* BitField flags */
9473 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9474 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */
9475 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
9476 #define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */
9477 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4
9478 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */
9479 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
9480 uint8_t op_code /* iSCSI KCQ opcode */;
9481 uint16_t qe_self_seq /* Self identifying sequence number */;
9482#elif defined(__LITTLE_ENDIAN)
9483 uint16_t qe_self_seq /* Self identifying sequence number */;
9484 uint8_t op_code /* iSCSI KCQ opcode */;
9485 uint8_t flags;
9486 #define ISCSI_KCQE_RESERVED0 (0x7<<0) /* BitField flags */
9487 #define ISCSI_KCQE_RESERVED0_SHIFT 0
9488 #define ISCSI_KCQE_RAMROD_COMPLETION (0x1<<3) /* BitField flags Everest only - indicates whether this KCQE is a ramrod completion */
9489 #define ISCSI_KCQE_RAMROD_COMPLETION_SHIFT 3
9490 #define ISCSI_KCQE_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */
9491 #define ISCSI_KCQE_LAYER_CODE_SHIFT 4
9492 #define ISCSI_KCQE_LINKED_WITH_NEXT (0x1<<7) /* BitField flags Indicates whether this KCQE is linked with the next KCQE */
9493 #define ISCSI_KCQE_LINKED_WITH_NEXT_SHIFT 7
9494#endif
9495};
9496
9497
9498/*
9499 * iSCSI KWQE header
9500 */
9501struct iscsi_kwqe_header
9502{
9503#if defined(__BIG_ENDIAN)
9504 uint8_t flags;
9505 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */
9506 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9507 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */
9508 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
9509 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */
9510 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
9511 uint8_t op_code /* iSCSI KWQE opcode */;
9512#elif defined(__LITTLE_ENDIAN)
9513 uint8_t op_code /* iSCSI KWQE opcode */;
9514 uint8_t flags;
9515 #define ISCSI_KWQE_HEADER_RESERVED0 (0xF<<0) /* BitField flags */
9516 #define ISCSI_KWQE_HEADER_RESERVED0_SHIFT 0
9517 #define ISCSI_KWQE_HEADER_LAYER_CODE (0x7<<4) /* BitField flags protocol layer (L2,L3,L4,L5,iSCSI) */
9518 #define ISCSI_KWQE_HEADER_LAYER_CODE_SHIFT 4
9519 #define ISCSI_KWQE_HEADER_RESERVED1 (0x1<<7) /* BitField flags */
9520 #define ISCSI_KWQE_HEADER_RESERVED1_SHIFT 7
9521#endif
9522};
9523
9524/*
9525 * iSCSI firmware init request 1
9526 */
9527struct iscsi_kwqe_init1
9528{
9529#if defined(__BIG_ENDIAN)
9530 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9531 uint8_t hsi_version /* HSI version number */;
9532 uint8_t num_cqs /* Number of completion queues */;
9533#elif defined(__LITTLE_ENDIAN)
9534 uint8_t num_cqs /* Number of completion queues */;
9535 uint8_t hsi_version /* HSI version number */;
9536 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9537#endif
9538 uint32_t dummy_buffer_addr_lo /* Lower 32-bit of dummy buffer - Teton only */;
9539 uint32_t dummy_buffer_addr_hi /* Higher 32-bit of dummy buffer - Teton only */;
9540#if defined(__BIG_ENDIAN)
9541 uint16_t num_ccells_per_conn /* Number of ccells per connection */;
9542 uint16_t num_tasks_per_conn /* Number of tasks per connection */;
9543#elif defined(__LITTLE_ENDIAN)
9544 uint16_t num_tasks_per_conn /* Number of tasks per connection */;
9545 uint16_t num_ccells_per_conn /* Number of ccells per connection */;
9546#endif
9547#if defined(__BIG_ENDIAN)
9548 uint16_t sq_wqes_per_page /* Number of work entries in a single page of SQ */;
9549 uint16_t sq_num_wqes /* Number of entries in the Send Queue */;
9550#elif defined(__LITTLE_ENDIAN)
9551 uint16_t sq_num_wqes /* Number of entries in the Send Queue */;
9552 uint16_t sq_wqes_per_page /* Number of work entries in a single page of SQ */;
9553#endif
9554#if defined(__BIG_ENDIAN)
9555 uint8_t cq_log_wqes_per_page /* Log of number of work entries in a single page of CQ */;
9556 uint8_t flags;
9557 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* BitField flags page size code */
9558 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9559 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* BitField flags if set, delayed ack is enabled */
9560 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
9561 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* BitField flags if set, keep alive is enabled */
9562 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
9563 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* BitField flags */
9564 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
9565 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */;
9566#elif defined(__LITTLE_ENDIAN)
9567 uint16_t cq_num_wqes /* Number of entries in the Completion Queue */;
9568 uint8_t flags;
9569 #define ISCSI_KWQE_INIT1_PAGE_SIZE (0xF<<0) /* BitField flags page size code */
9570 #define ISCSI_KWQE_INIT1_PAGE_SIZE_SHIFT 0
9571 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE (0x1<<4) /* BitField flags if set, delayed ack is enabled */
9572 #define ISCSI_KWQE_INIT1_DELAYED_ACK_ENABLE_SHIFT 4
9573 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE (0x1<<5) /* BitField flags if set, keep alive is enabled */
9574 #define ISCSI_KWQE_INIT1_KEEP_ALIVE_ENABLE_SHIFT 5
9575 #define ISCSI_KWQE_INIT1_RESERVED1 (0x3<<6) /* BitField flags */
9576 #define ISCSI_KWQE_INIT1_RESERVED1_SHIFT 6
9577 uint8_t cq_log_wqes_per_page /* Log of number of work entries in a single page of CQ */;
9578#endif
9579#if defined(__BIG_ENDIAN)
9580 uint16_t cq_num_pages /* Number of pages in CQ page table */;
9581 uint16_t sq_num_pages /* Number of pages in SQ page table */;
9582#elif defined(__LITTLE_ENDIAN)
9583 uint16_t sq_num_pages /* Number of pages in SQ page table */;
9584 uint16_t cq_num_pages /* Number of pages in CQ page table */;
9585#endif
9586#if defined(__BIG_ENDIAN)
9587 uint16_t rq_buffer_size /* Size of a single buffer (entry) in the RQ */;
9588 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */;
9589#elif defined(__LITTLE_ENDIAN)
9590 uint16_t rq_num_wqes /* Number of entries in the Receive Queue */;
9591 uint16_t rq_buffer_size /* Size of a single buffer (entry) in the RQ */;
9592#endif
9593};
9594
9595/*
9596 * iSCSI firmware init request 2
9597 */
9598struct iscsi_kwqe_init2
9599{
9600#if defined(__BIG_ENDIAN)
9601 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9602 uint16_t max_cq_sqn /* CQ wraparound value */;
9603#elif defined(__LITTLE_ENDIAN)
9604 uint16_t max_cq_sqn /* CQ wraparound value */;
9605 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9606#endif
9607 uint32_t error_bit_map[2] /* bit per error type, 0=error, 1=warning */;
9608 uint32_t tcp_keepalive /* TCP keepalive time in seconds */;
9609 uint32_t reserved1[4];
9610};
9611
9612/*
9613 * Initial iSCSI connection offload request 1
9614 */
9615struct iscsi_kwqe_conn_offload1
9616{
9617#if defined(__BIG_ENDIAN)
9618 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9619 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */;
9620#elif defined(__LITTLE_ENDIAN)
9621 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */;
9622 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9623#endif
9624 uint32_t sq_page_table_addr_lo /* Lower 32-bit of the SQs page table address */;
9625 uint32_t sq_page_table_addr_hi /* Higher 32-bit of the SQs page table address */;
9626 uint32_t cq_page_table_addr_lo /* Lower 32-bit of the CQs page table address */;
9627 uint32_t cq_page_table_addr_hi /* Higher 32-bit of the CQs page table address */;
9628 uint32_t reserved0[3];
9629};
9630
9631/*
9632 * iSCSI Page Table Entry (PTE)
9633 */
9634struct iscsi_pte
9635{
9636 uint32_t hi /* Higher 32 bits of address */;
9637 uint32_t lo /* Lower 32 bits of address */;
9638};
9639
9640/*
9641 * Initial iSCSI connection offload request 2
9642 */
9643struct iscsi_kwqe_conn_offload2
9644{
9645#if defined(__BIG_ENDIAN)
9646 struct iscsi_kwqe_header hdr /* KWQE header */;
9647 uint16_t reserved0;
9648#elif defined(__LITTLE_ENDIAN)
9649 uint16_t reserved0;
9650 struct iscsi_kwqe_header hdr /* KWQE header */;
9651#endif
9652 uint32_t rq_page_table_addr_lo /* Lower 32-bits of the RQs page table address */;
9653 uint32_t rq_page_table_addr_hi /* Higher 32-bits of the RQs page table address */;
9654 struct iscsi_pte sq_first_pte /* first SQ page table entry (for FW caching) */;
9655 struct iscsi_pte cq_first_pte /* first CQ page table entry (for FW caching) */;
9656 uint32_t num_additional_wqes /* Everest specific - number of offload3 KWQEs that will follow this KWQE */;
9657};
9658
9659/*
9660 * Everest specific - Initial iSCSI connection offload request 3
9661 */
9662struct iscsi_kwqe_conn_offload3
9663{
9664#if defined(__BIG_ENDIAN)
9665 struct iscsi_kwqe_header hdr /* KWQE header */;
9666 uint16_t reserved0;
9667#elif defined(__LITTLE_ENDIAN)
9668 uint16_t reserved0;
9669 struct iscsi_kwqe_header hdr /* KWQE header */;
9670#endif
9671 uint32_t reserved1;
9672 struct iscsi_pte qp_first_pte[3] /* first page table entry of some iSCSI ring (for FW caching) */;
9673};
9674
9675/*
9676 * iSCSI connection update request
9677 */
9678struct iscsi_kwqe_conn_update
9679{
9680#if defined(__BIG_ENDIAN)
9681 struct iscsi_kwqe_header hdr /* KWQE header */;
9682 uint16_t reserved0;
9683#elif defined(__LITTLE_ENDIAN)
9684 uint16_t reserved0;
9685 struct iscsi_kwqe_header hdr /* KWQE header */;
9686#endif
9687#if defined(__BIG_ENDIAN)
9688 uint8_t session_error_recovery_level /* iSCSI Error Recovery Level negotiated on this connection */;
9689 uint8_t max_outstanding_r2ts /* Maximum number of outstanding R2ts that a target can send for a command */;
9690 uint8_t reserved2;
9691 uint8_t conn_flags;
9692 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, 1=on */
9693 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9694 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, 1=on */
9695 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
9696 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1=yes */
9697 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
9698 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1=yes */
9699 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
9700 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* BitField conn_flags (use enum tcp_tstorm_ooo) */
9701 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
9702 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* BitField conn_flags */
9703 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
9704#elif defined(__LITTLE_ENDIAN)
9705 uint8_t conn_flags;
9706 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST (0x1<<0) /* BitField conn_flags 0=off, 1=on */
9707 #define ISCSI_KWQE_CONN_UPDATE_HEADER_DIGEST_SHIFT 0
9708 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST (0x1<<1) /* BitField conn_flags 0=off, 1=on */
9709 #define ISCSI_KWQE_CONN_UPDATE_DATA_DIGEST_SHIFT 1
9710 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T (0x1<<2) /* BitField conn_flags 0=no, 1=yes */
9711 #define ISCSI_KWQE_CONN_UPDATE_INITIAL_R2T_SHIFT 2
9712 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA (0x1<<3) /* BitField conn_flags 0=no, 1=yes */
9713 #define ISCSI_KWQE_CONN_UPDATE_IMMEDIATE_DATA_SHIFT 3
9714 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE (0x3<<4) /* BitField conn_flags (use enum tcp_tstorm_ooo) */
9715 #define ISCSI_KWQE_CONN_UPDATE_OOO_SUPPORT_MODE_SHIFT 4
9716 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1 (0x3<<6) /* BitField conn_flags */
9717 #define ISCSI_KWQE_CONN_UPDATE_RESERVED1_SHIFT 6
9718 uint8_t reserved2;
9719 uint8_t max_outstanding_r2ts /* Maximum number of outstanding R2ts that a target can send for a command */;
9720 uint8_t session_error_recovery_level /* iSCSI Error Recovery Level negotiated on this connection */;
9721#endif
9722 uint32_t context_id /* Context ID of the iSCSI connection */;
9723 uint32_t max_send_pdu_length /* Maximum length of a PDU that the target can receive */;
9724 uint32_t max_recv_pdu_length /* Maximum length of a PDU that the Initiator can receive */;
9725 uint32_t first_burst_length /* Maximum length of the immediate and unsolicited data that Initiator can send */;
9726 uint32_t max_burst_length /* Maximum length of the data that Initiator and target can send in one burst */;
9727 uint32_t exp_stat_sn /* Expected Status Serial Number */;
9728};
9729
9730/*
9731 * iSCSI destroy connection request
9732 */
9733struct iscsi_kwqe_conn_destroy
9734{
9735#if defined(__BIG_ENDIAN)
9736 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9737 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */;
9738#elif defined(__LITTLE_ENDIAN)
9739 uint16_t iscsi_conn_id /* Drivers connection ID. Should be sent in KCQEs to speed-up drivers access to connection data. */;
9740 struct iscsi_kwqe_header hdr /* KWQ WQE header */;
9741#endif
9742 uint32_t context_id /* Context ID of the iSCSI connection */;
9743 uint32_t reserved1[6];
9744};
9745
9746/*
9747 * iSCSI KWQ WQE
9748 */
9749union iscsi_kwqe
9750{
9751 struct iscsi_kwqe_init1 init1;
9752 struct iscsi_kwqe_init2 init2;
9753 struct iscsi_kwqe_conn_offload1 conn_offload1;
9754 struct iscsi_kwqe_conn_offload2 conn_offload2;
9755 struct iscsi_kwqe_conn_offload3 conn_offload3;
9756 struct iscsi_kwqe_conn_update conn_update;
9757 struct iscsi_kwqe_conn_destroy conn_destroy;
9758};
9759
9760
9761struct iscsi_rq_db
9762{
9763#if defined(__BIG_ENDIAN)
9764 uint16_t reserved1;
9765 uint16_t rq_prod;
9766#elif defined(__LITTLE_ENDIAN)
9767 uint16_t rq_prod;
9768 uint16_t reserved1;
9769#endif
9770 uint32_t __fw_hdr[15] /* Used by FW for partial header placement */;
9771};
9772
9773
9774struct iscsi_sq_db
9775{
9776#if defined(__BIG_ENDIAN)
9777 uint16_t reserved0 /* Pad structure size to 16 bytes */;
9778 uint16_t sq_prod;
9779#elif defined(__LITTLE_ENDIAN)
9780 uint16_t sq_prod;
9781 uint16_t reserved0 /* Pad structure size to 16 bytes */;
9782#endif
9783 uint32_t reserved1[3] /* Pad structure size to 16 bytes */;
9784};
9785
9786
9787/*
9788 * Tstorm Tcp flags
9789 */
9790struct tstorm_l5cm_tcp_flags
9791{
9792 uint16_t flags;
9793 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID (0xFFF<<0) /* BitField flags */
9794 #define TSTORM_L5CM_TCP_FLAGS_VLAN_ID_SHIFT 0
9795 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN (0x1<<12) /* BitField flags */
9796 #define TSTORM_L5CM_TCP_FLAGS_DELAYED_ACK_EN_SHIFT 12
9797 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED (0x1<<13) /* BitField flags */
9798 #define TSTORM_L5CM_TCP_FLAGS_TS_ENABLED_SHIFT 13
9799 #define TSTORM_L5CM_TCP_FLAGS_RSRV1 (0x3<<14) /* BitField flags */
9800 #define TSTORM_L5CM_TCP_FLAGS_RSRV1_SHIFT 14
9801};
9802
9803
9804/*
9805 * Cstorm iSCSI Storm Context
9806 */
9807struct cstorm_iscsi_st_context
9808{
9809 struct iscsi_cq_db_prod_pnd_cmpltn_cnt_arr cq_c_prod_pend_comp_ctr_arr /* Cstorm CQ producer and CQ pending completion array, updated by Cstorm */;
9810 struct iscsi_cq_db_sqn_2_notify_arr cq_c_prod_sqn_arr /* Cstorm CQ producer sequence, updated by Cstorm */;
9811 struct iscsi_cq_db_sqn_2_notify_arr cq_c_sqn_2_notify_arr /* Event Coalescing CQ sequence to notify driver, copied by Cstorm from CQ DB that is updated by Driver */;
9812 struct regpair_t hq_pbl_base /* HQ PBL base */;
9813 struct regpair_t hq_curr_pbe /* HQ current PBE */;
9814 struct regpair_t task_pbl_base /* Task Context Entry PBL base */;
9815 struct regpair_t cq_db_base /* pointer to CQ DB array. each CQ DB entry consists of CQ PBL, arm bit and idx to notify */;
9816#if defined(__BIG_ENDIAN)
9817 uint16_t hq_bd_itt /* copied from HQ BD */;
9818 uint16_t iscsi_conn_id;
9819#elif defined(__LITTLE_ENDIAN)
9820 uint16_t iscsi_conn_id;
9821 uint16_t hq_bd_itt /* copied from HQ BD */;
9822#endif
9823 uint32_t hq_bd_data_segment_len /* copied from HQ BD */;
9824 uint32_t hq_bd_buffer_offset /* copied from HQ BD */;
9825#if defined(__BIG_ENDIAN)
9826 uint8_t rsrv;
9827 uint8_t cq_proc_en_bit_map /* CQ processing enable bit map, 1 bit per CQ */;
9828 uint8_t cq_pend_comp_itt_valid_bit_map /* CQ pending completion ITT valid bit map, 1 bit per CQ */;
9829 uint8_t hq_bd_opcode /* copied from HQ BD */;
9830#elif defined(__LITTLE_ENDIAN)
9831 uint8_t hq_bd_opcode /* copied from HQ BD */;
9832 uint8_t cq_pend_comp_itt_valid_bit_map /* CQ pending completion ITT valid bit map, 1 bit per CQ */;
9833 uint8_t cq_proc_en_bit_map /* CQ processing enable bit map, 1 bit per CQ */;
9834 uint8_t rsrv;
9835#endif
9836 uint32_t hq_tcp_seq /* TCP sequence of next BD to release */;
9837#if defined(__BIG_ENDIAN)
9838 uint16_t flags;
9839 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* BitField flags */
9840 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9841 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* BitField flags */
9842 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
9843 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* BitField flags copied from HQ BD */
9844 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
9845 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* BitField flags copied from HQ BD */
9846 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
9847 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* BitField flags calculated using HQ BD opcode and write flag */
9848 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
9849 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /* BitField flags */
9850 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
9851 uint16_t hq_cons /* HQ consumer */;
9852#elif defined(__LITTLE_ENDIAN)
9853 uint16_t hq_cons /* HQ consumer */;
9854 uint16_t flags;
9855 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN (0x1<<0) /* BitField flags */
9856 #define CSTORM_ISCSI_ST_CONTEXT_DATA_DIGEST_EN_SHIFT 0
9857 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN (0x1<<1) /* BitField flags */
9858 #define CSTORM_ISCSI_ST_CONTEXT_HDR_DIGEST_EN_SHIFT 1
9859 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID (0x1<<2) /* BitField flags copied from HQ BD */
9860 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_CTXT_VALID_SHIFT 2
9861 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG (0x1<<3) /* BitField flags copied from HQ BD */
9862 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_LCL_CMPLN_FLG_SHIFT 3
9863 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK (0x1<<4) /* BitField flags calculated using HQ BD opcode and write flag */
9864 #define CSTORM_ISCSI_ST_CONTEXT_HQ_BD_WRITE_TASK_SHIFT 4
9865 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV (0x7FF<<5) /* BitField flags */
9866 #define CSTORM_ISCSI_ST_CONTEXT_CTRL_FLAGS_RSRV_SHIFT 5
9867#endif
9868 struct regpair_t rsrv1;
9869};
9870
9871
9872/*
9873 * SCSI read/write SQ WQE
9874 */
9875struct iscsi_cmd_pdu_hdr_little_endian
9876{
9877#if defined(__BIG_ENDIAN)
9878 uint8_t opcode;
9879 uint8_t op_attr;
9880 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* BitField op_attr Attributes of the SCSI command. To be sent with the outgoing command PDU. */
9881 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9882 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* BitField op_attr */
9883 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
9884 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* BitField op_attr Write bit. Initiator is expected to send the data to the target */
9885 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
9886 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* BitField op_attr Read bit. Data from target is expected */
9887 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
9888 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr Final bit. Firmware can change this bit based on the command before putting it into the outgoing PDU. */
9889 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
9890 uint16_t rsrv0;
9891#elif defined(__LITTLE_ENDIAN)
9892 uint16_t rsrv0;
9893 uint8_t op_attr;
9894 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES (0x7<<0) /* BitField op_attr Attributes of the SCSI command. To be sent with the outgoing command PDU. */
9895 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_ATTRIBUTES_SHIFT 0
9896 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x3<<3) /* BitField op_attr */
9897 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 3
9898 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG (0x1<<5) /* BitField op_attr Write bit. Initiator is expected to send the data to the target */
9899 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_WRITE_FLAG_SHIFT 5
9900 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG (0x1<<6) /* BitField op_attr Read bit. Data from target is expected */
9901 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_READ_FLAG_SHIFT 6
9902 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr Final bit. Firmware can change this bit based on the command before putting it into the outgoing PDU. */
9903 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
9904 uint8_t opcode;
9905#endif
9906 uint32_t data_fields;
9907 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
9908 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
9909 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
9910 #define ISCSI_CMD_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
9911 struct regpair_t lun;
9912 uint32_t itt;
9913 uint32_t expected_data_transfer_length;
9914 uint32_t cmd_sn;
9915 uint32_t exp_stat_sn;
9916 uint32_t scsi_command_block[4];
9917};
9918
9919
9920/*
9921 * Buffer per connection, used in Tstorm
9922 */
9923struct iscsi_conn_buf
9924{
9925 struct regpair_t reserved[8];
9926};
9927
9928
9929/*
9930 * iSCSI context region, used only in iSCSI
9931 */
9932struct ustorm_iscsi_rq_db
9933{
9934 struct regpair_t pbl_base /* Pointer to the rq page base list. */;
9935 struct regpair_t curr_pbe /* Pointer to the current rq page base. */;
9936};
9937
9938/*
9939 * iSCSI context region, used only in iSCSI
9940 */
9941struct ustorm_iscsi_r2tq_db
9942{
9943 struct regpair_t pbl_base /* Pointer to the r2tq page base list. */;
9944 struct regpair_t curr_pbe /* Pointer to the current r2tq page base. */;
9945};
9946
9947/*
9948 * iSCSI context region, used only in iSCSI
9949 */
9950struct ustorm_iscsi_cq_db
9951{
9952#if defined(__BIG_ENDIAN)
9953 uint16_t cq_sn /* CQ serial number */;
9954 uint16_t prod /* CQ producer */;
9955#elif defined(__LITTLE_ENDIAN)
9956 uint16_t prod /* CQ producer */;
9957 uint16_t cq_sn /* CQ serial number */;
9958#endif
9959 struct regpair_t curr_pbe /* Pointer to the current cq page base. */;
9960};
9961
9962/*
9963 * iSCSI context region, used only in iSCSI
9964 */
9965struct rings_db
9966{
9967 struct ustorm_iscsi_rq_db rq /* RQ db. */;
9968 struct ustorm_iscsi_r2tq_db r2tq /* R2TQ db. */;
9969 struct ustorm_iscsi_cq_db cq[8] /* CQ db. */;
9970#if defined(__BIG_ENDIAN)
9971 uint16_t rq_prod /* RQ prod */;
9972 uint16_t r2tq_prod /* R2TQ producer. */;
9973#elif defined(__LITTLE_ENDIAN)
9974 uint16_t r2tq_prod /* R2TQ producer. */;
9975 uint16_t rq_prod /* RQ prod */;
9976#endif
9977 struct regpair_t cq_pbl_base /* Pointer to the cq page base list. */;
9978};
9979
9980/*
9981 * iSCSI context region, used only in iSCSI
9982 */
9983struct ustorm_iscsi_placement_db
9984{
9985 uint32_t sgl_base_lo /* SGL base address lo */;
9986 uint32_t sgl_base_hi /* SGL base address hi */;
9987 uint32_t local_sge_0_address_hi /* SGE address hi */;
9988 uint32_t local_sge_0_address_lo /* SGE address lo */;
9989#if defined(__BIG_ENDIAN)
9990 uint16_t curr_sge_offset /* Current offset in the SGE */;
9991 uint16_t local_sge_0_size /* SGE size */;
9992#elif defined(__LITTLE_ENDIAN)
9993 uint16_t local_sge_0_size /* SGE size */;
9994 uint16_t curr_sge_offset /* Current offset in the SGE */;
9995#endif
9996 uint32_t local_sge_1_address_hi /* SGE address hi */;
9997 uint32_t local_sge_1_address_lo /* SGE address lo */;
9998#if defined(__BIG_ENDIAN)
9999 uint8_t exp_padding_2b /* Number of padding bytes not yet processed */;
10000 uint8_t nal_len_3b /* Non 4 byte aligned bytes in the previous iteration */;
10001 uint16_t local_sge_1_size /* SGE size */;
10002#elif defined(__LITTLE_ENDIAN)
10003 uint16_t local_sge_1_size /* SGE size */;
10004 uint8_t nal_len_3b /* Non 4 byte aligned bytes in the previous iteration */;
10005 uint8_t exp_padding_2b /* Number of padding bytes not yet processed */;
10006#endif
10007#if defined(__BIG_ENDIAN)
10008 uint8_t sgl_size /* Number of SGEs remaining till end of SGL */;
10009 uint8_t local_sge_index_2b /* Index to the local SGE currently used */;
10010 uint16_t reserved7;
10011#elif defined(__LITTLE_ENDIAN)
10012 uint16_t reserved7;
10013 uint8_t local_sge_index_2b /* Index to the local SGE currently used */;
10014 uint8_t sgl_size /* Number of SGEs remaining till end of SGL */;
10015#endif
10016 uint32_t rem_pdu /* Number of bytes remaining in PDU */;
10017 uint32_t place_db_bitfield_1;
10018 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD (0xFFFFFF<<0) /* BitField place_db_bitfield_1place_db_bitfield_1 Number of bytes remaining in PDU payload */
10019 #define USTORM_ISCSI_PLACEMENT_DB_REM_PDU_PAYLOAD_SHIFT 0
10020 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID (0xFF<<24) /* BitField place_db_bitfield_1place_db_bitfield_1 Temp task context - determines the CQ index for CQE placement */
10021 #define USTORM_ISCSI_PLACEMENT_DB_CQ_ID_SHIFT 24
10022 uint32_t place_db_bitfield_2;
10023 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE (0xFFFFFF<<0) /* BitField place_db_bitfield_2place_db_bitfield_2 Bytes to truncate from the payload. */
10024 #define USTORM_ISCSI_PLACEMENT_DB_BYTES_2_TRUNCATE_SHIFT 0
10025 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX (0xFF<<24) /* BitField place_db_bitfield_2place_db_bitfield_2 Sge index on host */
10026 #define USTORM_ISCSI_PLACEMENT_DB_HOST_SGE_INDEX_SHIFT 24
10027 uint32_t nal;
10028 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE (0xFFFFFF<<0) /* BitField nalNon aligned db Number of bytes remaining in local SGEs */
10029 #define USTORM_ISCSI_PLACEMENT_DB_REM_SGE_SIZE_SHIFT 0
10030 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B (0xFF<<24) /* BitField nalNon aligned db Number of digest bytes not yet processed */
10031 #define USTORM_ISCSI_PLACEMENT_DB_EXP_DIGEST_3B_SHIFT 24
10032};
10033
10034/*
10035 * Ustorm iSCSI Storm Context
10036 */
10037struct ustorm_iscsi_st_context
10038{
10039 uint32_t exp_stat_sn /* Expected status sequence number, incremented with each response/middle path/unsolicited received. */;
10040 uint32_t exp_data_sn /* Expected Data sequence number, incremented with each data in */;
10041 struct rings_db ring /* rq, r2tq ,cq */;
10042 struct regpair_t task_pbl_base /* Task PBL base will be read from RAM to context */;
10043 struct regpair_t tce_phy_addr /* Pointer to the task context physical address */;
10044 struct ustorm_iscsi_placement_db place_db;
10045 uint32_t reserved8 /* reserved */;
10046 uint32_t rem_rcv_len /* Temp task context - Remaining bytes to end of task */;
10047#if defined(__BIG_ENDIAN)
10048 uint16_t hdr_itt /* field copied from PDU header */;
10049 uint16_t iscsi_conn_id;
10050#elif defined(__LITTLE_ENDIAN)
10051 uint16_t iscsi_conn_id;
10052 uint16_t hdr_itt /* field copied from PDU header */;
10053#endif
10054 uint32_t nal_bytes /* nal bytes read from BRB */;
10055#if defined(__BIG_ENDIAN)
10056 uint8_t hdr_second_byte_union /* field copied from PDU header */;
10057 uint8_t bitfield_0;
10058 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* BitField bitfield_0bitfield_0 marks that processing of payload has started */
10059 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10060 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* BitField bitfield_0bitfield_0 marks that fence is need on the next CQE */
10061 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
10062 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* BitField bitfield_0bitfield_0 marks that a RESET should be sent to CRC machine. Used in NAL condition in the beginning of a PDU. */
10063 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
10064 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* BitField bitfield_0bitfield_0 reserved */
10065 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
10066 uint8_t task_pdu_cache_index;
10067 uint8_t task_pbe_cache_index;
10068#elif defined(__LITTLE_ENDIAN)
10069 uint8_t task_pbe_cache_index;
10070 uint8_t task_pdu_cache_index;
10071 uint8_t bitfield_0;
10072 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU (0x1<<0) /* BitField bitfield_0bitfield_0 marks that processing of payload has started */
10073 #define USTORM_ISCSI_ST_CONTEXT_BMIDDLEOFPDU_SHIFT 0
10074 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE (0x1<<1) /* BitField bitfield_0bitfield_0 marks that fence is need on the next CQE */
10075 #define USTORM_ISCSI_ST_CONTEXT_BFENCECQE_SHIFT 1
10076 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC (0x1<<2) /* BitField bitfield_0bitfield_0 marks that a RESET should be sent to CRC machine. Used in NAL condition in the beginning of a PDU. */
10077 #define USTORM_ISCSI_ST_CONTEXT_BRESETCRC_SHIFT 2
10078 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1 (0x1F<<3) /* BitField bitfield_0bitfield_0 reserved */
10079 #define USTORM_ISCSI_ST_CONTEXT_RESERVED1_SHIFT 3
10080 uint8_t hdr_second_byte_union /* field copied from PDU header */;
10081#endif
10082#if defined(__BIG_ENDIAN)
10083 uint16_t reserved3 /* reserved */;
10084 uint8_t reserved2 /* reserved */;
10085 uint8_t acDecrement /* Manage the AC decrement that should be done by USDM */;
10086#elif defined(__LITTLE_ENDIAN)
10087 uint8_t acDecrement /* Manage the AC decrement that should be done by USDM */;
10088 uint8_t reserved2 /* reserved */;
10089 uint16_t reserved3 /* reserved */;
10090#endif
10091 uint32_t task_stat /* counts dataIn for read and holds data outs, r2t for write */;
10092#if defined(__BIG_ENDIAN)
10093 uint8_t hdr_opcode /* field copied from PDU header */;
10094 uint8_t num_cqs /* Number of CQs supported by this connection */;
10095 uint16_t reserved5 /* reserved */;
10096#elif defined(__LITTLE_ENDIAN)
10097 uint16_t reserved5 /* reserved */;
10098 uint8_t num_cqs /* Number of CQs supported by this connection */;
10099 uint8_t hdr_opcode /* field copied from PDU header */;
10100#endif
10101 uint32_t negotiated_rx;
10102 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx */
10103 #define USTORM_ISCSI_ST_CONTEXT_MAX_RECV_PDU_LENGTH_SHIFT 0
10104 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS (0xFF<<24) /* BitField negotiated_rx */
10105 #define USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT 24
10106 uint32_t negotiated_rx_and_flags;
10107 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH (0xFFFFFF<<0) /* BitField negotiated_rx_and_flags Negotiated maximum length of sequence */
10108 #define USTORM_ISCSI_ST_CONTEXT_MAX_BURST_LENGTH_SHIFT 0
10109 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED (0x1<<24) /* BitField negotiated_rx_and_flags Marks that unvalid CQE was already posted or PDU header was cachaed in RAM */
10110 #define USTORM_ISCSI_ST_CONTEXT_B_CQE_POSTED_OR_HEADER_CACHED_SHIFT 24
10111 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN (0x1<<25) /* BitField negotiated_rx_and_flags Header digest support enable */
10112 #define USTORM_ISCSI_ST_CONTEXT_B_HDR_DIGEST_EN_SHIFT 25
10113 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN (0x1<<26) /* BitField negotiated_rx_and_flags Data digest support enable */
10114 #define USTORM_ISCSI_ST_CONTEXT_B_DATA_DIGEST_EN_SHIFT 26
10115 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR (0x1<<27) /* BitField negotiated_rx_and_flags */
10116 #define USTORM_ISCSI_ST_CONTEXT_B_PROTOCOL_ERROR_SHIFT 27
10117 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID (0x1<<28) /* BitField negotiated_rx_and_flags temp task context */
10118 #define USTORM_ISCSI_ST_CONTEXT_B_TASK_VALID_SHIFT 28
10119 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE (0x3<<29) /* BitField negotiated_rx_and_flags Task type: 0 = slow-path (non-RW) 1 = read 2 = write */
10120 #define USTORM_ISCSI_ST_CONTEXT_TASK_TYPE_SHIFT 29
10121 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED (0x1<<31) /* BitField negotiated_rx_and_flags Set if all data is acked */
10122 #define USTORM_ISCSI_ST_CONTEXT_B_ALL_DATA_ACKED_SHIFT 31
10123};
10124
10125/*
10126 * TCP context region, shared in TOE, RDMA and ISCSI
10127 */
10128struct tstorm_tcp_st_context_section
10129{
10130 uint32_t flags1;
10131 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT (0xFFFFFF<<0) /* BitField flags1various state flags 20b only, Smoothed Rount Trip Time */
10132 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_SRTT_SHIFT 0
10133 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID (0x1<<24) /* BitField flags1various state flags PAWS asserted as invalid in KA flow */
10134 #define TSTORM_TCP_ST_CONTEXT_SECTION_PAWS_INVALID_SHIFT 24
10135 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS (0x1<<25) /* BitField flags1various state flags Timestamps supported on this connection */
10136 #define TSTORM_TCP_ST_CONTEXT_SECTION_TIMESTAMP_EXISTS_SHIFT 25
10137 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0 (0x1<<26) /* BitField flags1various state flags */
10138 #define TSTORM_TCP_ST_CONTEXT_SECTION_RESERVED0_SHIFT 26
10139 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD (0x1<<27) /* BitField flags1various state flags stop receiving rx payload */
10140 #define TSTORM_TCP_ST_CONTEXT_SECTION_STOP_RX_PAYLOAD_SHIFT 27
10141 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED (0x1<<28) /* BitField flags1various state flags Keep Alive enabled */
10142 #define TSTORM_TCP_ST_CONTEXT_SECTION_KA_ENABLED_SHIFT 28
10143 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE (0x1<<29) /* BitField flags1various state flags First Retransmition Timout Estimation */
10144 #define TSTORM_TCP_ST_CONTEXT_SECTION_FIRST_RTO_ESTIMATE_SHIFT 29
10145 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN (0x1<<30) /* BitField flags1various state flags per connection flag, signals whether to check if rt count exceeds max_seg_retransmit */
10146 #define TSTORM_TCP_ST_CONTEXT_SECTION_MAX_SEG_RETRANSMIT_EN_SHIFT 30
10147 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN (0x1<<31) /* BitField flags1various state flags last isle ends with FIN. FIN is counted as 1 byte for isle end sequence */
10148 #define TSTORM_TCP_ST_CONTEXT_SECTION_LAST_ISLE_HAS_FIN_SHIFT 31
10149 uint32_t flags2;
10150 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION (0xFFFFFF<<0) /* BitField flags2various state flags 20b only, Round Trip Time variation */
10151 #define TSTORM_TCP_ST_CONTEXT_SECTION_RTT_VARIATION_SHIFT 0
10152 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN (0x1<<24) /* BitField flags2various state flags */
10153 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN_SHIFT 24
10154 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN (0x1<<25) /* BitField flags2various state flags per GOS flags, but duplicated for each context */
10155 #define TSTORM_TCP_ST_CONTEXT_SECTION_DA_COUNTER_EN_SHIFT 25
10156 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT (0x1<<26) /* BitField flags2various state flags keep alive packet was sent */
10157 #define __TSTORM_TCP_ST_CONTEXT_SECTION_KA_PROBE_SENT_SHIFT 26
10158 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT (0x1<<27) /* BitField flags2various state flags persist packet was sent */
10159 #define __TSTORM_TCP_ST_CONTEXT_SECTION_PERSIST_PROBE_SENT_SHIFT 27
10160 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<28) /* BitField flags2various state flags determines wheather or not to update l2 statistics */
10161 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 28
10162 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<29) /* BitField flags2various state flags determines wheather or not to update l4 statistics */
10163 #define TSTORM_TCP_ST_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 29
10164 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK (0x1<<30) /* BitField flags2various state flags possible blind-in-window RST attack detected */
10165 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_RST_ATTACK_SHIFT 30
10166 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK (0x1<<31) /* BitField flags2various state flags possible blind-in-window SYN attack detected */
10167 #define __TSTORM_TCP_ST_CONTEXT_SECTION_IN_WINDOW_SYN_ATTACK_SHIFT 31
10168#if defined(__BIG_ENDIAN)
10169 uint16_t mss;
10170 uint8_t tcp_sm_state /* 3b only, Tcp state machine state */;
10171 uint8_t rto_exp /* 3b only, Exponential Backoff index */;
10172#elif defined(__LITTLE_ENDIAN)
10173 uint8_t rto_exp /* 3b only, Exponential Backoff index */;
10174 uint8_t tcp_sm_state /* 3b only, Tcp state machine state */;
10175 uint16_t mss;
10176#endif
10177 uint32_t rcv_nxt /* Receive sequence: next expected */;
10178 uint32_t timestamp_recent /* last timestamp from segTS */;
10179 uint32_t timestamp_recent_time /* time at which timestamp_recent has been set */;
10180 uint32_t cwnd /* Congestion window */;
10181 uint32_t ss_thresh /* Slow Start Threshold */;
10182 uint32_t cwnd_accum /* Congestion window accumilation */;
10183 uint32_t prev_seg_seq /* Sequence number used for last sndWnd update (was: snd_wnd_l1) */;
10184 uint32_t expected_rel_seq /* the last update of rel_seq */;
10185 uint32_t recover /* Recording of sndMax when we enter retransmit */;
10186#if defined(__BIG_ENDIAN)
10187 uint8_t retransmit_count /* Number of times a packet was retransmitted */;
10188 uint8_t ka_max_probe_count /* Keep Alive maximum probe counter */;
10189 uint8_t persist_probe_count /* Persist probe counter */;
10190 uint8_t ka_probe_count /* Keep Alive probe counter */;
10191#elif defined(__LITTLE_ENDIAN)
10192 uint8_t ka_probe_count /* Keep Alive probe counter */;
10193 uint8_t persist_probe_count /* Persist probe counter */;
10194 uint8_t ka_max_probe_count /* Keep Alive maximum probe counter */;
10195 uint8_t retransmit_count /* Number of times a packet was retransmitted */;
10196#endif
10197#if defined(__BIG_ENDIAN)
10198 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */;
10199 uint8_t ooo_support_mode;
10200 uint8_t snd_wnd_scale /* 4b only, Far-end window (Snd.Wind.Scale) scale */;
10201 uint8_t dup_ack_count /* Duplicate Ack Counter */;
10202#elif defined(__LITTLE_ENDIAN)
10203 uint8_t dup_ack_count /* Duplicate Ack Counter */;
10204 uint8_t snd_wnd_scale /* 4b only, Far-end window (Snd.Wind.Scale) scale */;
10205 uint8_t ooo_support_mode;
10206 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */;
10207#endif
10208 uint32_t retransmit_start_time /* Used by retransmit as a recording of start time */;
10209 uint32_t ka_timeout /* Keep Alive timeout */;
10210 uint32_t ka_interval /* Keep Alive interval */;
10211 uint32_t isle_start_seq /* First Out-of-order isle start sequence */;
10212 uint32_t isle_end_seq /* First Out-of-order isle end sequence */;
10213#if defined(__BIG_ENDIAN)
10214 uint16_t second_isle_address /* address of the second isle (if exists) in internal RAM */;
10215 uint16_t recent_seg_wnd /* Last far end window received (not scaled!) */;
10216#elif defined(__LITTLE_ENDIAN)
10217 uint16_t recent_seg_wnd /* Last far end window received (not scaled!) */;
10218 uint16_t second_isle_address /* address of the second isle (if exists) in internal RAM */;
10219#endif
10220#if defined(__BIG_ENDIAN)
10221 uint8_t max_isles_ever_happened /* for statistics only - max number of isles ever happened on this connection */;
10222 uint8_t isles_number /* number of isles */;
10223 uint16_t last_isle_address /* address of the last isle (if exists) in internal RAM */;
10224#elif defined(__LITTLE_ENDIAN)
10225 uint16_t last_isle_address /* address of the last isle (if exists) in internal RAM */;
10226 uint8_t isles_number /* number of isles */;
10227 uint8_t max_isles_ever_happened /* for statistics only - max number of isles ever happened on this connection */;
10228#endif
10229 uint32_t max_rt_time;
10230#if defined(__BIG_ENDIAN)
10231 uint16_t lsb_mac_address /* TX source MAC LSB-16 */;
10232 uint16_t vlan_id /* Connection-configured VLAN ID */;
10233#elif defined(__LITTLE_ENDIAN)
10234 uint16_t vlan_id /* Connection-configured VLAN ID */;
10235 uint16_t lsb_mac_address /* TX source MAC LSB-16 */;
10236#endif
10237#if defined(__BIG_ENDIAN)
10238 uint16_t msb_mac_address /* TX source MAC MSB-16 */;
10239 uint16_t mid_mac_address /* TX source MAC MID-16 */;
10240#elif defined(__LITTLE_ENDIAN)
10241 uint16_t mid_mac_address /* TX source MAC MID-16 */;
10242 uint16_t msb_mac_address /* TX source MAC MSB-16 */;
10243#endif
10244 uint32_t rightmost_received_seq /* The maximum sequence ever received - used for The New Patent */;
10245};
10246
10247/*
10248 * Termination variables
10249 */
10250struct iscsi_term_vars
10251{
10252 uint8_t BitMap;
10253 #define ISCSI_TERM_VARS_TCP_STATE (0xF<<0) /* BitField BitMap tcp state for the termination process */
10254 #define ISCSI_TERM_VARS_TCP_STATE_SHIFT 0
10255 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT (0x1<<4) /* BitField BitMap fin received sticky bit */
10256 #define ISCSI_TERM_VARS_FIN_RECEIVED_SBIT_SHIFT 4
10257 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT (0x1<<5) /* BitField BitMap ack on fin received stick bit */
10258 #define ISCSI_TERM_VARS_ACK_ON_FIN_RECEIVED_SBIT_SHIFT 5
10259 #define ISCSI_TERM_VARS_TERM_ON_CHIP (0x1<<6) /* BitField BitMap termination on chip ( option2 ) */
10260 #define ISCSI_TERM_VARS_TERM_ON_CHIP_SHIFT 6
10261 #define ISCSI_TERM_VARS_RSRV (0x1<<7) /* BitField BitMap */
10262 #define ISCSI_TERM_VARS_RSRV_SHIFT 7
10263};
10264
10265/*
10266 * iSCSI context region, used only in iSCSI
10267 */
10268struct tstorm_iscsi_st_context_section
10269{
10270 uint32_t nalPayload /* Non-aligned payload */;
10271 uint32_t b2nh /* Number of bytes to next iSCSI header */;
10272#if defined(__BIG_ENDIAN)
10273 uint16_t rq_cons /* RQ consumer */;
10274 uint8_t flags;
10275 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* BitField flags header digest enable, set at login stage */
10276 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10277 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* BitField flags data digest enable, set at login stage */
10278 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
10279 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* BitField flags partial header flow indication */
10280 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
10281 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* BitField flags */
10282 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
10283 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* BitField flags */
10284 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
10285 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* BitField flags Non-aligned length */
10286 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
10287 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* BitField flags */
10288 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
10289 uint8_t hdr_bytes_2_fetch /* Number of bytes left to fetch to complete iSCSI header */;
10290#elif defined(__LITTLE_ENDIAN)
10291 uint8_t hdr_bytes_2_fetch /* Number of bytes left to fetch to complete iSCSI header */;
10292 uint8_t flags;
10293 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN (0x1<<0) /* BitField flags header digest enable, set at login stage */
10294 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_HDR_DIGEST_EN_SHIFT 0
10295 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN (0x1<<1) /* BitField flags data digest enable, set at login stage */
10296 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DATA_DIGEST_EN_SHIFT 1
10297 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER (0x1<<2) /* BitField flags partial header flow indication */
10298 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_PARTIAL_HEADER_SHIFT 2
10299 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE (0x1<<3) /* BitField flags */
10300 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_FULL_FEATURE_SHIFT 3
10301 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS (0x1<<4) /* BitField flags */
10302 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_B_DROP_ALL_PDUS_SHIFT 4
10303 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN (0x3<<5) /* BitField flags Non-aligned length */
10304 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_NALLEN_SHIFT 5
10305 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0 (0x1<<7) /* BitField flags */
10306 #define TSTORM_ISCSI_ST_CONTEXT_SECTION_RSRV0_SHIFT 7
10307 uint16_t rq_cons /* RQ consumer */;
10308#endif
10309 struct regpair_t rq_db_phy_addr;
10310#if defined(__BIG_ENDIAN)
10311 struct iscsi_term_vars term_vars /* Termination variables */;
10312 uint8_t rsrv1;
10313 uint16_t iscsi_conn_id;
10314#elif defined(__LITTLE_ENDIAN)
10315 uint16_t iscsi_conn_id;
10316 uint8_t rsrv1;
10317 struct iscsi_term_vars term_vars /* Termination variables */;
10318#endif
10319 uint32_t process_nxt /* next TCP sequence to be processed by the iSCSI layer. */;
10320};
10321
10322/*
10323 * The iSCSI non-aggregative context of Tstorm
10324 */
10325struct tstorm_iscsi_st_context
10326{
10327 struct tstorm_tcp_st_context_section tcp /* TCP context region, shared in TOE, RDMA and iSCSI */;
10328 struct tstorm_iscsi_st_context_section iscsi /* iSCSI context region, used only in iSCSI */;
10329};
10330
10331/*
10332 * Ethernet context section, shared in TOE, RDMA and ISCSI
10333 */
10334struct xstorm_eth_context_section
10335{
10336#if defined(__BIG_ENDIAN)
10337 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
10338 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
10339 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
10340 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
10341#elif defined(__LITTLE_ENDIAN)
10342 uint8_t local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */;
10343 uint8_t local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */;
10344 uint8_t remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */;
10345 uint8_t remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */;
10346#endif
10347#if defined(__BIG_ENDIAN)
10348 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
10349 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
10350 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
10351 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
10352#elif defined(__LITTLE_ENDIAN)
10353 uint8_t remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */;
10354 uint8_t remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */;
10355 uint8_t remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */;
10356 uint8_t remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */;
10357#endif
10358#if defined(__BIG_ENDIAN)
10359 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */;
10360 uint16_t vlan_params;
10361 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField vlan_params part of PBF Header Builder Command */
10362 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10363 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField vlan_params Canonical format indicator, part of PBF Header Builder Command */
10364 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
10365 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField vlan_params part of PBF Header Builder Command */
10366 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
10367#elif defined(__LITTLE_ENDIAN)
10368 uint16_t vlan_params;
10369 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID (0xFFF<<0) /* BitField vlan_params part of PBF Header Builder Command */
10370 #define XSTORM_ETH_CONTEXT_SECTION_VLAN_ID_SHIFT 0
10371 #define XSTORM_ETH_CONTEXT_SECTION_CFI (0x1<<12) /* BitField vlan_params Canonical format indicator, part of PBF Header Builder Command */
10372 #define XSTORM_ETH_CONTEXT_SECTION_CFI_SHIFT 12
10373 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY (0x7<<13) /* BitField vlan_params part of PBF Header Builder Command */
10374 #define XSTORM_ETH_CONTEXT_SECTION_PRIORITY_SHIFT 13
10375 uint16_t reserved_vlan_type /* this field is not an absolute must, but the reseved was here */;
10376#endif
10377#if defined(__BIG_ENDIAN)
10378 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
10379 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
10380 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
10381 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
10382#elif defined(__LITTLE_ENDIAN)
10383 uint8_t local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */;
10384 uint8_t local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */;
10385 uint8_t local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */;
10386 uint8_t local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */;
10387#endif
10388};
10389
10390/*
10391 * IpV4 context section, shared in TOE, RDMA and ISCSI
10392 */
10393struct xstorm_ip_v4_context_section
10394{
10395#if defined(__BIG_ENDIAN)
10396 uint16_t __pbf_hdr_cmd_rsvd_id;
10397 uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
10398#elif defined(__LITTLE_ENDIAN)
10399 uint16_t __pbf_hdr_cmd_rsvd_flags_offset;
10400 uint16_t __pbf_hdr_cmd_rsvd_id;
10401#endif
10402#if defined(__BIG_ENDIAN)
10403 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
10404 uint8_t tos /* Type Of Service, used in PBF Header Builder Command */;
10405 uint16_t __pbf_hdr_cmd_rsvd_length;
10406#elif defined(__LITTLE_ENDIAN)
10407 uint16_t __pbf_hdr_cmd_rsvd_length;
10408 uint8_t tos /* Type Of Service, used in PBF Header Builder Command */;
10409 uint8_t __pbf_hdr_cmd_rsvd_ver_ihl;
10410#endif
10411 uint32_t ip_local_addr /* used in PBF Header Builder Command */;
10412#if defined(__BIG_ENDIAN)
10413 uint8_t ttl /* Time to live, used in PBF Header Builder Command */;
10414 uint8_t __pbf_hdr_cmd_rsvd_protocol;
10415 uint16_t __pbf_hdr_cmd_rsvd_csum;
10416#elif defined(__LITTLE_ENDIAN)
10417 uint16_t __pbf_hdr_cmd_rsvd_csum;
10418 uint8_t __pbf_hdr_cmd_rsvd_protocol;
10419 uint8_t ttl /* Time to live, used in PBF Header Builder Command */;
10420#endif
10421 uint32_t __pbf_hdr_cmd_rsvd_1 /* places the ip_remote_addr field in the proper place in the regpair */;
10422 uint32_t ip_remote_addr /* used in PBF Header Builder Command */;
10423};
10424
10425/*
10426 * context section, shared in TOE, RDMA and ISCSI
10427 */
10428struct xstorm_padded_ip_v4_context_section
10429{
10430 struct xstorm_ip_v4_context_section ip_v4;
10431 uint32_t reserved1[4];
10432};
10433
10434/*
10435 * IpV6 context section, shared in TOE, RDMA and ISCSI
10436 */
10437struct xstorm_ip_v6_context_section
10438{
10439#if defined(__BIG_ENDIAN)
10440 uint16_t pbf_hdr_cmd_rsvd_payload_len;
10441 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
10442 uint8_t hop_limit /* used in PBF Header Builder Command */;
10443#elif defined(__LITTLE_ENDIAN)
10444 uint8_t hop_limit /* used in PBF Header Builder Command */;
10445 uint8_t pbf_hdr_cmd_rsvd_nxt_hdr;
10446 uint16_t pbf_hdr_cmd_rsvd_payload_len;
10447#endif
10448 uint32_t priority_flow_label;
10449 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL (0xFFFFF<<0) /* BitField priority_flow_label used in PBF Header Builder Command */
10450 #define XSTORM_IP_V6_CONTEXT_SECTION_FLOW_LABEL_SHIFT 0
10451 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS (0xFF<<20) /* BitField priority_flow_label used in PBF Header Builder Command */
10452 #define XSTORM_IP_V6_CONTEXT_SECTION_TRAFFIC_CLASS_SHIFT 20
10453 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER (0xF<<28) /* BitField priority_flow_label */
10454 #define XSTORM_IP_V6_CONTEXT_SECTION_PBF_HDR_CMD_RSVD_VER_SHIFT 28
10455 uint32_t ip_local_addr_lo_hi /* second 32 bits of Ip local Address, used in PBF Header Builder Command */;
10456 uint32_t ip_local_addr_lo_lo /* first 32 bits of Ip local Address, used in PBF Header Builder Command */;
10457 uint32_t ip_local_addr_hi_hi /* fourth 32 bits of Ip local Address, used in PBF Header Builder Command */;
10458 uint32_t ip_local_addr_hi_lo /* third 32 bits of Ip local Address, used in PBF Header Builder Command */;
10459 uint32_t ip_remote_addr_lo_hi /* second 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */;
10460 uint32_t ip_remote_addr_lo_lo /* first 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */;
10461 uint32_t ip_remote_addr_hi_hi /* fourth 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */;
10462 uint32_t ip_remote_addr_hi_lo /* third 32 bits of Ip remoteinsation Address, used in PBF Header Builder Command */;
10463};
10464
10465union xstorm_ip_context_section_types
10466{
10467 struct xstorm_padded_ip_v4_context_section padded_ip_v4;
10468 struct xstorm_ip_v6_context_section ip_v6;
10469};
10470
10471/*
10472 * TCP context section, shared in TOE, RDMA and ISCSI
10473 */
10474struct xstorm_tcp_context_section
10475{
10476 uint32_t snd_max;
10477#if defined(__BIG_ENDIAN)
10478 uint16_t remote_port /* used in PBF Header Builder Command */;
10479 uint16_t local_port /* used in PBF Header Builder Command */;
10480#elif defined(__LITTLE_ENDIAN)
10481 uint16_t local_port /* used in PBF Header Builder Command */;
10482 uint16_t remote_port /* used in PBF Header Builder Command */;
10483#endif
10484#if defined(__BIG_ENDIAN)
10485 uint8_t original_nagle_1b;
10486 uint8_t ts_enabled /* Only 1 bit is used */;
10487 uint16_t tcp_params;
10488 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* BitField tcp_paramsTcp parameters for ease of pbf command construction */
10489 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10490 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* BitField tcp_paramsTcp parameters */
10491 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
10492 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* BitField tcp_paramsTcp parameters */
10493 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
10494 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* BitField tcp_paramsTcp parameters Selective Ack Enabled */
10495 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
10496 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* BitField tcp_paramsTcp parameters window smaller than initial window was advertised to far end */
10497 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
10498 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* BitField tcp_paramsTcp parameters */
10499 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
10500 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* BitField tcp_paramsTcp parameters */
10501 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
10502 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* BitField tcp_paramsTcp parameters */
10503 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
10504#elif defined(__LITTLE_ENDIAN)
10505 uint16_t tcp_params;
10506 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE (0xFF<<0) /* BitField tcp_paramsTcp parameters for ease of pbf command construction */
10507 #define XSTORM_TCP_CONTEXT_SECTION_TOTAL_HEADER_SIZE_SHIFT 0
10508 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT (0x1<<8) /* BitField tcp_paramsTcp parameters */
10509 #define __XSTORM_TCP_CONTEXT_SECTION_ECT_BIT_SHIFT 8
10510 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED (0x1<<9) /* BitField tcp_paramsTcp parameters */
10511 #define __XSTORM_TCP_CONTEXT_SECTION_ECN_ENABLED_SHIFT 9
10512 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED (0x1<<10) /* BitField tcp_paramsTcp parameters Selective Ack Enabled */
10513 #define XSTORM_TCP_CONTEXT_SECTION_SACK_ENABLED_SHIFT 10
10514 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV (0x1<<11) /* BitField tcp_paramsTcp parameters window smaller than initial window was advertised to far end */
10515 #define XSTORM_TCP_CONTEXT_SECTION_SMALL_WIN_ADV_SHIFT 11
10516 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG (0x1<<12) /* BitField tcp_paramsTcp parameters */
10517 #define XSTORM_TCP_CONTEXT_SECTION_FIN_SENT_FLAG_SHIFT 12
10518 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED (0x1<<13) /* BitField tcp_paramsTcp parameters */
10519 #define XSTORM_TCP_CONTEXT_SECTION_WINDOW_SATURATED_SHIFT 13
10520 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER (0x3<<14) /* BitField tcp_paramsTcp parameters */
10521 #define XSTORM_TCP_CONTEXT_SECTION_SLOWPATH_QUEUES_FLUSH_COUNTER_SHIFT 14
10522 uint8_t ts_enabled /* Only 1 bit is used */;
10523 uint8_t original_nagle_1b;
10524#endif
10525#if defined(__BIG_ENDIAN)
10526 uint16_t pseudo_csum /* the precaluclated pseudo checksum header for pbf command construction */;
10527 uint16_t window_scaling_factor /* local_adv_wnd by this variable to reach the advertised window to far end */;
10528#elif defined(__LITTLE_ENDIAN)
10529 uint16_t window_scaling_factor /* local_adv_wnd by this variable to reach the advertised window to far end */;
10530 uint16_t pseudo_csum /* the precaluclated pseudo checksum header for pbf command construction */;
10531#endif
10532#if defined(__BIG_ENDIAN)
10533 uint16_t reserved2 /* The ID of the statistics client for counting common/L2 statistics */;
10534 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */;
10535 uint8_t statistics_params;
10536 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l2 statistics */
10537 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10538 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l4 statistics */
10539 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
10540 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* BitField statistics_paramsTcp parameters */
10541 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
10542#elif defined(__LITTLE_ENDIAN)
10543 uint8_t statistics_params;
10544 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS (0x1<<0) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l2 statistics */
10545 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L2_STATSTICS_SHIFT 0
10546 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS (0x1<<1) /* BitField statistics_paramsTcp parameters set by the driver, determines wheather or not to update l4 statistics */
10547 #define XSTORM_TCP_CONTEXT_SECTION_UPDATE_L4_STATSTICS_SHIFT 1
10548 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED (0x3F<<2) /* BitField statistics_paramsTcp parameters */
10549 #define XSTORM_TCP_CONTEXT_SECTION_RESERVED_SHIFT 2
10550 uint8_t statistics_counter_id /* The ID of the statistics client for counting common/L2 statistics */;
10551 uint16_t reserved2 /* The ID of the statistics client for counting common/L2 statistics */;
10552#endif
10553 uint32_t ts_time_diff /* Time Stamp Offload, used in PBF Header Builder Command */;
10554 uint32_t __next_timer_expir /* Last Packet Real Time Clock Stamp */;
10555};
10556
10557/*
10558 * Common context section, shared in TOE, RDMA and ISCSI
10559 */
10560struct xstorm_common_context_section
10561{
10562 struct xstorm_eth_context_section ethernet;
10563 union xstorm_ip_context_section_types ip_union;
10564 struct xstorm_tcp_context_section tcp;
10565#if defined(__BIG_ENDIAN)
10566 uint8_t __dcb_val;
10567 uint8_t flags;
10568 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* BitField flagsTcp parameters part of the tx switching state machine */
10569 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10570 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* BitField flagsTcp parameters determines to which voq credit will be returned */
10571 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
10572 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* BitField flagsTcp parameters Flag that states wether inner valn was provided by the OS */
10573 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
10574 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* BitField flagsTcp parameters original priority given from the OS */
10575 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
10576 uint8_t outer_tag_flags;
10577 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB enabled */
10578 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10579 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB disabled */
10580 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
10581 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* BitField outer_tag_flagsTcp parameters */
10582 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
10583 uint8_t ip_version_1b;
10584#elif defined(__LITTLE_ENDIAN)
10585 uint8_t ip_version_1b;
10586 uint8_t outer_tag_flags;
10587 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI (0x7<<0) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB enabled */
10588 #define XSTORM_COMMON_CONTEXT_SECTION_DCB_OUTER_PRI_SHIFT 0
10589 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI (0x7<<3) /* BitField outer_tag_flagsTcp parameters Priority of outer tag in case of DCB disabled */
10590 #define XSTORM_COMMON_CONTEXT_SECTION_OUTER_PRI_SHIFT 3
10591 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED (0x3<<6) /* BitField outer_tag_flagsTcp parameters */
10592 #define XSTORM_COMMON_CONTEXT_SECTION_RESERVED_SHIFT 6
10593 uint8_t flags;
10594 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED (0x1<<0) /* BitField flagsTcp parameters part of the tx switching state machine */
10595 #define XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT 0
10596 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT (0x7<<1) /* BitField flagsTcp parameters determines to which voq credit will be returned */
10597 #define XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT 1
10598 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE (0x1<<4) /* BitField flagsTcp parameters Flag that states wether inner valn was provided by the OS */
10599 #define XSTORM_COMMON_CONTEXT_SECTION_VLAN_MODE_SHIFT 4
10600 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY (0x7<<5) /* BitField flagsTcp parameters original priority given from the OS */
10601 #define XSTORM_COMMON_CONTEXT_SECTION_ORIGINAL_PRIORITY_SHIFT 5
10602 uint8_t __dcb_val;
10603#endif
10604};
10605
10606/*
10607 * Flags used in ISCSI context section
10608 */
10609struct xstorm_iscsi_context_flags
10610{
10611 uint8_t flags;
10612 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA (0x1<<0) /* BitField flags */
10613 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA_SHIFT 0
10614 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T (0x1<<1) /* BitField flags */
10615 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T_SHIFT 1
10616 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST (0x1<<2) /* BitField flags */
10617 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_HEADER_DIGEST_SHIFT 2
10618 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST (0x1<<3) /* BitField flags */
10619 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_EN_DATA_DIGEST_SHIFT 3
10620 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN (0x1<<4) /* BitField flags */
10621 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_HQ_BD_WRITTEN_SHIFT 4
10622 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ (0x1<<5) /* BitField flags */
10623 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_LAST_OP_SQ_SHIFT 5
10624 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT (0x1<<6) /* BitField flags */
10625 #define XSTORM_ISCSI_CONTEXT_FLAGS_B_UPDATE_SND_NXT_SHIFT 6
10626 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4 (0x1<<7) /* BitField flags */
10627 #define XSTORM_ISCSI_CONTEXT_FLAGS_RESERVED4_SHIFT 7
10628};
10629
10630struct iscsi_task_context_entry_x
10631{
10632 uint32_t data_out_buffer_offset;
10633 uint32_t itt;
10634 uint32_t data_sn;
10635};
10636
10637struct iscsi_task_context_entry_xuc_x_write_only
10638{
10639 uint32_t tx_r2t_sn /* Xstorm increments for every data-out seq sent. */;
10640};
10641
10642struct iscsi_task_context_entry_xuc_xu_write_both
10643{
10644 uint32_t sgl_base_lo;
10645 uint32_t sgl_base_hi;
10646#if defined(__BIG_ENDIAN)
10647 uint8_t sgl_size;
10648 uint8_t sge_index;
10649 uint16_t sge_offset;
10650#elif defined(__LITTLE_ENDIAN)
10651 uint16_t sge_offset;
10652 uint8_t sge_index;
10653 uint8_t sgl_size;
10654#endif
10655};
10656
10657/*
10658 * iSCSI context section
10659 */
10660struct xstorm_iscsi_context_section
10661{
10662 uint32_t first_burst_length;
10663 uint32_t max_send_pdu_length;
10664 struct regpair_t sq_pbl_base;
10665 struct regpair_t sq_curr_pbe;
10666 struct regpair_t hq_pbl_base;
10667 struct regpair_t hq_curr_pbe_base;
10668 struct regpair_t r2tq_pbl_base;
10669 struct regpair_t r2tq_curr_pbe_base;
10670 struct regpair_t task_pbl_base;
10671#if defined(__BIG_ENDIAN)
10672 uint16_t data_out_count;
10673 struct xstorm_iscsi_context_flags flags;
10674 uint8_t task_pbl_cache_idx /* All-ones value stands for PBL not cached */;
10675#elif defined(__LITTLE_ENDIAN)
10676 uint8_t task_pbl_cache_idx /* All-ones value stands for PBL not cached */;
10677 struct xstorm_iscsi_context_flags flags;
10678 uint16_t data_out_count;
10679#endif
10680 uint32_t seq_more_2_send;
10681 uint32_t pdu_more_2_send;
10682 struct iscsi_task_context_entry_x temp_tce_x;
10683 struct iscsi_task_context_entry_xuc_x_write_only temp_tce_x_wr;
10684 struct iscsi_task_context_entry_xuc_xu_write_both temp_tce_xu_wr;
10685 struct regpair_t lun;
10686 uint32_t exp_data_transfer_len_ttt /* Overloaded with ttt in multi-pdu sequences flow. */;
10687 uint32_t pdu_data_2_rxmit;
10688 uint32_t rxmit_bytes_2_dr;
10689#if defined(__BIG_ENDIAN)
10690 uint16_t rxmit_sge_offset;
10691 uint16_t hq_rxmit_cons;
10692#elif defined(__LITTLE_ENDIAN)
10693 uint16_t hq_rxmit_cons;
10694 uint16_t rxmit_sge_offset;
10695#endif
10696#if defined(__BIG_ENDIAN)
10697 uint16_t r2tq_cons;
10698 uint8_t rxmit_flags;
10699 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* BitField rxmit_flags */
10700 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10701 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* BitField rxmit_flags */
10702 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
10703 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* BitField rxmit_flags */
10704 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
10705 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* BitField rxmit_flags */
10706 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
10707 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* BitField rxmit_flags */
10708 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
10709 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* BitField rxmit_flags */
10710 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
10711 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* BitField rxmit_flags */
10712 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
10713 uint8_t rxmit_sge_idx;
10714#elif defined(__LITTLE_ENDIAN)
10715 uint8_t rxmit_sge_idx;
10716 uint8_t rxmit_flags;
10717 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD (0x1<<0) /* BitField rxmit_flags */
10718 #define XSTORM_ISCSI_CONTEXT_SECTION_B_NEW_HQ_BD_SHIFT 0
10719 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR (0x1<<1) /* BitField rxmit_flags */
10720 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PDU_HDR_SHIFT 1
10721 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU (0x1<<2) /* BitField rxmit_flags */
10722 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_END_PDU_SHIFT 2
10723 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR (0x1<<3) /* BitField rxmit_flags */
10724 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_DR_SHIFT 3
10725 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR (0x1<<4) /* BitField rxmit_flags */
10726 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_START_DR_SHIFT 4
10727 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING (0x3<<5) /* BitField rxmit_flags */
10728 #define XSTORM_ISCSI_CONTEXT_SECTION_B_RXMIT_PADDING_SHIFT 5
10729 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT (0x1<<7) /* BitField rxmit_flags */
10730 #define XSTORM_ISCSI_CONTEXT_SECTION_B_ISCSI_CONT_FAST_RXMIT_SHIFT 7
10731 uint16_t r2tq_cons;
10732#endif
10733 uint32_t hq_rxmit_tcp_seq;
10734};
10735
10736/*
10737 * Xstorm iSCSI Storm Context
10738 */
10739struct xstorm_iscsi_st_context
10740{
10741 struct xstorm_common_context_section common;
10742 struct xstorm_iscsi_context_section iscsi;
10743};
10744
10745/*
10746 * Iscsi connection context
10747 */
10748struct iscsi_context
10749{
10750 struct ustorm_iscsi_st_context ustorm_st_context /* Ustorm storm context */;
10751 struct tstorm_iscsi_st_context tstorm_st_context /* Tstorm storm context */;
10752 struct xstorm_iscsi_ag_context xstorm_ag_context /* Xstorm aggregative context */;
10753 struct tstorm_iscsi_ag_context tstorm_ag_context /* Tstorm aggregative context */;
10754 struct cstorm_iscsi_ag_context cstorm_ag_context /* Cstorm aggregative context */;
10755 struct ustorm_iscsi_ag_context ustorm_ag_context /* Ustorm aggregative context */;
10756 struct timers_block_context timers_context /* Timers block context */;
10757 struct regpair_t upb_context /* UPb context */;
10758 struct xstorm_iscsi_st_context xstorm_st_context /* Xstorm storm context */;
10759 struct regpair_t xpb_context /* XPb context (inside the PBF) */;
10760 struct cstorm_iscsi_st_context cstorm_st_context /* Cstorm storm context */;
10761};
10762
10763
10764/*
10765 * PDU header of an iSCSI DATA-OUT
10766 */
10767struct iscsi_data_pdu_hdr_little_endian
10768{
10769#if defined(__BIG_ENDIAN)
10770 uint8_t opcode;
10771 uint8_t op_attr;
10772 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */
10773 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10774 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr */
10775 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
10776 uint16_t rsrv0;
10777#elif defined(__LITTLE_ENDIAN)
10778 uint16_t rsrv0;
10779 uint8_t op_attr;
10780 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */
10781 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10782 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG (0x1<<7) /* BitField op_attr */
10783 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_FINAL_FLAG_SHIFT 7
10784 uint8_t opcode;
10785#endif
10786 uint32_t data_fields;
10787 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
10788 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10789 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
10790 #define ISCSI_DATA_PDU_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10791 struct regpair_t lun;
10792 uint32_t itt;
10793 uint32_t ttt;
10794 uint32_t rsrv2;
10795 uint32_t exp_stat_sn;
10796 uint32_t rsrv3;
10797 uint32_t data_sn;
10798 uint32_t buffer_offset;
10799 uint32_t rsrv4;
10800};
10801
10802
10803/*
10804 * PDU header of an iSCSI login request
10805 */
10806struct iscsi_login_req_hdr_little_endian
10807{
10808#if defined(__BIG_ENDIAN)
10809 uint8_t opcode;
10810 uint8_t op_attr;
10811 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* BitField op_attr */
10812 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10813 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* BitField op_attr */
10814 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
10815 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* BitField op_attr */
10816 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
10817 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */
10818 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10819 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* BitField op_attr */
10820 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
10821 uint8_t version_max;
10822 uint8_t version_min;
10823#elif defined(__LITTLE_ENDIAN)
10824 uint8_t version_min;
10825 uint8_t version_max;
10826 uint8_t op_attr;
10827 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG (0x3<<0) /* BitField op_attr */
10828 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_NSG_SHIFT 0
10829 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG (0x3<<2) /* BitField op_attr */
10830 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CSG_SHIFT 2
10831 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0 (0x3<<4) /* BitField op_attr */
10832 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_RSRV0_SHIFT 4
10833 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */
10834 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10835 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT (0x1<<7) /* BitField op_attr */
10836 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TRANSIT_SHIFT 7
10837 uint8_t opcode;
10838#endif
10839 uint32_t data_fields;
10840 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
10841 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10842 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
10843 #define ISCSI_LOGIN_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10844 uint32_t isid_lo;
10845#if defined(__BIG_ENDIAN)
10846 uint16_t isid_hi;
10847 uint16_t tsih;
10848#elif defined(__LITTLE_ENDIAN)
10849 uint16_t tsih;
10850 uint16_t isid_hi;
10851#endif
10852 uint32_t itt;
10853#if defined(__BIG_ENDIAN)
10854 uint16_t cid;
10855 uint16_t rsrv1;
10856#elif defined(__LITTLE_ENDIAN)
10857 uint16_t rsrv1;
10858 uint16_t cid;
10859#endif
10860 uint32_t cmd_sn;
10861 uint32_t exp_stat_sn;
10862 uint32_t rsrv2[4];
10863};
10864
10865/*
10866 * PDU header of an iSCSI logout request
10867 */
10868struct iscsi_logout_req_hdr_little_endian
10869{
10870#if defined(__BIG_ENDIAN)
10871 uint8_t opcode;
10872 uint8_t op_attr;
10873 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* BitField op_attr */
10874 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10875 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */
10876 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10877 uint16_t rsrv0;
10878#elif defined(__LITTLE_ENDIAN)
10879 uint16_t rsrv0;
10880 uint8_t op_attr;
10881 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE (0x7F<<0) /* BitField op_attr */
10882 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_REASON_CODE_SHIFT 0
10883 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */
10884 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10885 uint8_t opcode;
10886#endif
10887 uint32_t data_fields;
10888 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
10889 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10890 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
10891 #define ISCSI_LOGOUT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10892 uint32_t rsrv2[2];
10893 uint32_t itt;
10894#if defined(__BIG_ENDIAN)
10895 uint16_t cid;
10896 uint16_t rsrv1;
10897#elif defined(__LITTLE_ENDIAN)
10898 uint16_t rsrv1;
10899 uint16_t cid;
10900#endif
10901 uint32_t cmd_sn;
10902 uint32_t exp_stat_sn;
10903 uint32_t rsrv3[4];
10904};
10905
10906/*
10907 * PDU header of an iSCSI TMF request
10908 */
10909struct iscsi_tmf_req_hdr_little_endian
10910{
10911#if defined(__BIG_ENDIAN)
10912 uint8_t opcode;
10913 uint8_t op_attr;
10914 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* BitField op_attr */
10915 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10916 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */
10917 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10918 uint16_t rsrv0;
10919#elif defined(__LITTLE_ENDIAN)
10920 uint16_t rsrv0;
10921 uint8_t op_attr;
10922 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION (0x7F<<0) /* BitField op_attr */
10923 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_FUNCTION_SHIFT 0
10924 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1 (0x1<<7) /* BitField op_attr this value must be 1 */
10925 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_RSRV1_1_SHIFT 7
10926 uint8_t opcode;
10927#endif
10928 uint32_t data_fields;
10929 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
10930 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10931 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
10932 #define ISCSI_TMF_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10933 struct regpair_t lun;
10934 uint32_t itt;
10935 uint32_t referenced_task_tag;
10936 uint32_t cmd_sn;
10937 uint32_t exp_stat_sn;
10938 uint32_t ref_cmd_sn;
10939 uint32_t exp_data_sn;
10940 uint32_t rsrv2[2];
10941};
10942
10943/*
10944 * PDU header of an iSCSI Text request
10945 */
10946struct iscsi_text_req_hdr_little_endian
10947{
10948#if defined(__BIG_ENDIAN)
10949 uint8_t opcode;
10950 uint8_t op_attr;
10951 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* BitField op_attr */
10952 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10953 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */
10954 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10955 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* BitField op_attr */
10956 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
10957 uint16_t rsrv0;
10958#elif defined(__LITTLE_ENDIAN)
10959 uint16_t rsrv0;
10960 uint8_t op_attr;
10961 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1 (0x3F<<0) /* BitField op_attr */
10962 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10963 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG (0x1<<6) /* BitField op_attr */
10964 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_CONTINUE_FLG_SHIFT 6
10965 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL (0x1<<7) /* BitField op_attr */
10966 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_FINAL_SHIFT 7
10967 uint8_t opcode;
10968#endif
10969 uint32_t data_fields;
10970 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
10971 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
10972 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
10973 #define ISCSI_TEXT_REQ_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
10974 struct regpair_t lun;
10975 uint32_t itt;
10976 uint32_t ttt;
10977 uint32_t cmd_sn;
10978 uint32_t exp_stat_sn;
10979 uint32_t rsrv3[4];
10980};
10981
10982/*
10983 * PDU header of an iSCSI Nop-Out
10984 */
10985struct iscsi_nop_out_hdr_little_endian
10986{
10987#if defined(__BIG_ENDIAN)
10988 uint8_t opcode;
10989 uint8_t op_attr;
10990 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */
10991 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
10992 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* BitField op_attr this reserved bit must be set to 1 */
10993 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
10994 uint16_t rsrv0;
10995#elif defined(__LITTLE_ENDIAN)
10996 uint16_t rsrv0;
10997 uint8_t op_attr;
10998 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1 (0x7F<<0) /* BitField op_attr */
10999 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV1_SHIFT 0
11000 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1 (0x1<<7) /* BitField op_attr this reserved bit must be set to 1 */
11001 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_RSRV2_1_SHIFT 7
11002 uint8_t opcode;
11003#endif
11004 uint32_t data_fields;
11005 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH (0xFFFFFF<<0) /* BitField data_fields */
11006 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_DATA_SEGMENT_LENGTH_SHIFT 0
11007 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH (0xFF<<24) /* BitField data_fields */
11008 #define ISCSI_NOP_OUT_HDR_LITTLE_ENDIAN_TOTAL_AHS_LENGTH_SHIFT 24
11009 struct regpair_t lun;
11010 uint32_t itt;
11011 uint32_t ttt;
11012 uint32_t cmd_sn;
11013 uint32_t exp_stat_sn;
11014 uint32_t rsrv3[4];
11015};
11016
11017/*
11018 * iscsi pdu headers in little endian form.
11019 */
11020union iscsi_pdu_headers_little_endian
11021{
11022 uint32_t fullHeaderSize[12] /* The full size of the header. protects the union size */;
11023 struct iscsi_cmd_pdu_hdr_little_endian command_pdu_hdr /* PDU header of an iSCSI command - read,write */;
11024 struct iscsi_data_pdu_hdr_little_endian data_out_pdu_hdr /* PDU header of an iSCSI DATA-IN and DATA-OUT PDU */;
11025 struct iscsi_login_req_hdr_little_endian login_req_pdu_hdr /* PDU header of an iSCSI Login request */;
11026 struct iscsi_logout_req_hdr_little_endian logout_req_pdu_hdr /* PDU header of an iSCSI Logout request */;
11027 struct iscsi_tmf_req_hdr_little_endian tmf_req_pdu_hdr /* PDU header of an iSCSI TMF request */;
11028 struct iscsi_text_req_hdr_little_endian text_req_pdu_hdr /* PDU header of an iSCSI Text request */;
11029 struct iscsi_nop_out_hdr_little_endian nop_out_pdu_hdr /* PDU header of an iSCSI Nop-Out */;
11030};
11031
11032struct iscsi_hq_bd
11033{
11034 union iscsi_pdu_headers_little_endian pdu_header;
11035#if defined(__BIG_ENDIAN)
11036 uint16_t reserved1;
11037 uint16_t lcl_cmp_flg;
11038#elif defined(__LITTLE_ENDIAN)
11039 uint16_t lcl_cmp_flg;
11040 uint16_t reserved1;
11041#endif
11042 uint32_t sgl_base_lo;
11043 uint32_t sgl_base_hi;
11044#if defined(__BIG_ENDIAN)
11045 uint8_t sgl_size;
11046 uint8_t sge_index;
11047 uint16_t sge_offset;
11048#elif defined(__LITTLE_ENDIAN)
11049 uint16_t sge_offset;
11050 uint8_t sge_index;
11051 uint8_t sgl_size;
11052#endif
11053};
11054
11055
11056/*
11057 * CQE data for L2 OOO connection $$KEEP_ENDIANNESS$$
11058 */
11059struct iscsi_l2_ooo_data
11060{
11061 uint32_t iscsi_cid /* iSCSI context ID */;
11062 uint8_t drop_isle /* isle number of the first isle to drop */;
11063 uint8_t drop_size /* number of isles to drop */;
11064 uint8_t ooo_opcode /* Out Of Order opcode (use enum tcp_ooo_event */;
11065 uint8_t ooo_isle /* OOO isle number to add the packet to */;
11066 uint8_t reserved[8];
11067};
11068
11069
11070struct iscsi_task_context_entry_xuc_c_write_only
11071{
11072 uint32_t total_data_acked /* Xstorm inits to zero. C increments. U validates */;
11073};
11074
11075struct iscsi_task_context_r2t_table_entry
11076{
11077 uint32_t ttt;
11078 uint32_t desired_data_len;
11079};
11080
11081struct iscsi_task_context_entry_xuc_u_write_only
11082{
11083 uint32_t exp_r2t_sn /* Xstorm inits to zero. U increments. */;
11084 struct iscsi_task_context_r2t_table_entry r2t_table[4] /* U updates. X reads */;
11085#if defined(__BIG_ENDIAN)
11086 uint16_t data_in_count /* X inits to zero. U increments. */;
11087 uint8_t cq_id /* X inits to zero. U uses. */;
11088 uint8_t valid_1b /* X sets. U resets. */;
11089#elif defined(__LITTLE_ENDIAN)
11090 uint8_t valid_1b /* X sets. U resets. */;
11091 uint8_t cq_id /* X inits to zero. U uses. */;
11092 uint16_t data_in_count /* X inits to zero. U increments. */;
11093#endif
11094};
11095
11096struct iscsi_task_context_entry_xuc
11097{
11098 struct iscsi_task_context_entry_xuc_c_write_only write_c /* Cstorm only inits data here, without further change by any storm. */;
11099 uint32_t exp_data_transfer_len /* Xstorm only inits data here. */;
11100 struct iscsi_task_context_entry_xuc_x_write_only write_x /* only Xstorm writes data here. */;
11101 uint32_t lun_lo /* Xstorm only inits data here. */;
11102 struct iscsi_task_context_entry_xuc_xu_write_both write_xu /* Both X and U update this struct, but in different flow. */;
11103 uint32_t lun_hi /* Xstorm only inits data here. */;
11104 struct iscsi_task_context_entry_xuc_u_write_only write_u /* Ustorm only inits data here, without further change by any storm. */;
11105};
11106
11107struct iscsi_task_context_entry_u
11108{
11109 uint32_t exp_r2t_buff_offset;
11110 uint32_t rem_rcv_len;
11111 uint32_t exp_data_sn;
11112};
11113
11114struct iscsi_task_context_entry
11115{
11116 struct iscsi_task_context_entry_x tce_x;
11117#if defined(__BIG_ENDIAN)
11118 uint16_t data_out_count;
11119 uint16_t rsrv0;
11120#elif defined(__LITTLE_ENDIAN)
11121 uint16_t rsrv0;
11122 uint16_t data_out_count;
11123#endif
11124 struct iscsi_task_context_entry_xuc tce_xuc;
11125 struct iscsi_task_context_entry_u tce_u;
11126 uint32_t rsrv1[7] /* increase the size to 128 bytes */;
11127};
11128
11129
11130struct iscsi_task_context_entry_xuc_x_init_only
11131{
11132 struct regpair_t lun /* X inits. U validates */;
11133 uint32_t exp_data_transfer_len /* Xstorm inits to SQ WQE data. U validates */;
11134};
11135
11136
11137/*
11138 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$
11139 */
11140struct afex_vif_list_ramrod_data
11141{
11142 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */;
11143 uint8_t func_bit_map /* the function bit map to set */;
11144 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */;
11145 uint8_t func_to_clear /* the func id to clear in case of clear func mode */;
11146 uint8_t echo;
11147 uint16_t reserved1;
11148};
11149
11150
11151/*
11152 * $$KEEP_ENDIANNESS$$
11153 */
11154struct c2s_pri_trans_table_entry
11155{
11156 uint8_t val[MAX_VLAN_PRIORITIES] /* Inner to outer vlan priority translation table entry for current PF */;
11157};
11158
11159
11160/*
11161 * cfc delete event data $$KEEP_ENDIANNESS$$
11162 */
11163struct cfc_del_event_data
11164{
11165 uint32_t cid /* cid of deleted connection */;
11166 uint32_t reserved0;
11167 uint32_t reserved1;
11168};
11169
11170
11171/*
11172 * per-port SAFC demo variables
11173 */
11174struct cmng_flags_per_port
11175{
11176 uint32_t cmng_enables;
11177 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */
11178 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0
11179 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */
11180 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1
11181 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */
11182 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2
11183 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */
11184 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3
11185 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */
11186 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4
11187 uint32_t __reserved1;
11188};
11189
11190
11191/*
11192 * per-port rate shaping variables
11193 */
11194struct rate_shaping_vars_per_port
11195{
11196 uint32_t rs_periodic_timeout /* timeout of periodic timer */;
11197 uint32_t rs_threshold /* threshold, below which we start to stop queues */;
11198};
11199
11200/*
11201 * per-port fairness variables
11202 */
11203struct fairness_vars_per_port
11204{
11205 uint32_t upper_bound /* Quota for a protocol/vnic */;
11206 uint32_t fair_threshold /* almost-empty threshold */;
11207 uint32_t fairness_timeout /* timeout of fairness timer */;
11208 uint32_t reserved0;
11209};
11210
11211/*
11212 * per-port SAFC variables
11213 */
11214struct safc_struct_per_port
11215{
11216#if defined(__BIG_ENDIAN)
11217 uint16_t __reserved1;
11218 uint8_t __reserved0;
11219 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
11220#elif defined(__LITTLE_ENDIAN)
11221 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */;
11222 uint8_t __reserved0;
11223 uint16_t __reserved1;
11224#endif
11225 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */;
11226 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */;
11227};
11228
11229/*
11230 * Per-port congestion management variables
11231 */
11232struct cmng_struct_per_port
11233{
11234 struct rate_shaping_vars_per_port rs_vars;
11235 struct fairness_vars_per_port fair_vars;
11236 struct safc_struct_per_port safc_vars;
11237 struct cmng_flags_per_port flags;
11238};
11239
11240/*
11241 * a single rate shaping counter. can be used as protocol or vnic counter
11242 */
11243struct rate_shaping_counter
11244{
11245 uint32_t quota /* Quota for a protocol/vnic */;
11246#if defined(__BIG_ENDIAN)
11247 uint16_t __reserved0;
11248 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
11249#elif defined(__LITTLE_ENDIAN)
11250 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */;
11251 uint16_t __reserved0;
11252#endif
11253};
11254
11255/*
11256 * per-vnic rate shaping variables
11257 */
11258struct rate_shaping_vars_per_vn
11259{
11260 struct rate_shaping_counter vn_counter /* per-vnic counter */;
11261};
11262
11263/*
11264 * per-vnic fairness variables
11265 */
11266struct fairness_vars_per_vn
11267{
11268 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */;
11269 uint32_t vn_credit_delta /* used for incrementing the credit */;
11270 uint32_t __reserved0;
11271};
11272
11273/*
11274 * cmng port init state
11275 */
11276struct cmng_vnic
11277{
11278 struct rate_shaping_vars_per_vn vnic_max_rate[4];
11279 struct fairness_vars_per_vn vnic_min_rate[4];
11280};
11281
11282/*
11283 * cmng port init state
11284 */
11285struct cmng_init
11286{
11287 struct cmng_struct_per_port port;
11288 struct cmng_vnic vnic;
11289};
11290
11291
11292/*
11293 * driver parameters for congestion management init, all rates are in Mbps
11294 */
11295struct cmng_init_input
11296{
11297 uint32_t port_rate;
11298 uint16_t vnic_min_rate[4] /* rates are in Mbps */;
11299 uint16_t vnic_max_rate[4] /* rates are in Mbps */;
11300 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */;
11301 uint16_t cos_to_pause_mask[MAX_COS_NUMBER];
11302 struct cmng_flags_per_port flags;
11303};
11304
11305
11306/*
11307 * Protocol-common command ID for slow path elements
11308 */
11309enum common_spqe_cmd_id
11310{
11311 RAMROD_CMD_ID_COMMON_UNUSED,
11312 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */,
11313 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */,
11314 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */,
11315 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */,
11316 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
11317 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */,
11318 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
11319 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
11320 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */,
11321 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
11322 MAX_COMMON_SPQE_CMD_ID};
11323
11324
11325/*
11326 * Per-protocol connection types
11327 */
11328enum connection_type
11329{
11330 ETH_CONNECTION_TYPE /* Ethernet */,
11331 TOE_CONNECTION_TYPE /* TOE */,
11332 RDMA_CONNECTION_TYPE /* RDMA */,
11333 ISCSI_CONNECTION_TYPE /* iSCSI */,
11334 FCOE_CONNECTION_TYPE /* FCoE */,
11335 RESERVED_CONNECTION_TYPE_0,
11336 RESERVED_CONNECTION_TYPE_1,
11337 RESERVED_CONNECTION_TYPE_2,
11338 NONE_CONNECTION_TYPE /* General- used for common slow path */,
11339 MAX_CONNECTION_TYPE};
11340
11341
11342/*
11343 * Cos modes
11344 */
11345enum cos_mode
11346{
11347 OVERRIDE_COS /* Firmware deduce cos according to DCB */,
11348 STATIC_COS /* Firmware has constant queues per CoS */,
11349 FW_WRR /* Firmware keep fairness between different CoSes */,
11350 MAX_COS_MODE};
11351
11352
11353/*
11354 * Dynamic HC counters set by the driver
11355 */
11356struct hc_dynamic_drv_counter
11357{
11358 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */;
11359};
11360
11361/*
11362 * zone A per-queue data
11363 */
11364struct cstorm_queue_zone_data
11365{
11366 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */;
11367 struct regpair_t reserved[2];
11368};
11369
11370
11371/*
11372 * Vf-PF channel data in cstorm ram (non-triggered zone)
11373 */
11374struct vf_pf_channel_zone_data
11375{
11376 uint32_t msg_addr_lo /* the message address on VF memory */;
11377 uint32_t msg_addr_hi /* the message address on VF memory */;
11378};
11379
11380/*
11381 * zone for VF non-triggered data
11382 */
11383struct non_trigger_vf_zone
11384{
11385 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */;
11386};
11387
11388/*
11389 * Vf-PF channel trigger zone in cstorm ram
11390 */
11391struct vf_pf_channel_zone_trigger
11392{
11393 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */;
11394};
11395
11396/*
11397 * zone that triggers the in-bound interrupt
11398 */
11399struct trigger_vf_zone
11400{
11401#if defined(__BIG_ENDIAN)
11402 uint16_t reserved1;
11403 uint8_t reserved0;
11404 struct vf_pf_channel_zone_trigger vf_pf_channel;
11405#elif defined(__LITTLE_ENDIAN)
11406 struct vf_pf_channel_zone_trigger vf_pf_channel;
11407 uint8_t reserved0;
11408 uint16_t reserved1;
11409#endif
11410 uint32_t reserved2;
11411};
11412
11413/*
11414 * zone B per-VF data
11415 */
11416struct cstorm_vf_zone_data
11417{
11418 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */;
11419 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */;
11420};
11421
11422
11423/*
11424 * Dynamic host coalescing init parameters, per state machine
11425 */
11426struct dynamic_hc_sm_config
11427{
11428 uint32_t threshold[3] /* thresholds of number of outstanding bytes */;
11429 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */;
11430 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */;
11431 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */;
11432 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */;
11433 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */;
11434};
11435
11436/*
11437 * Dynamic host coalescing init parameters
11438 */
11439struct dynamic_hc_config
11440{
11441 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */;
11442};
11443
11444
11445struct e2_integ_data
11446{
11447#if defined(__BIG_ENDIAN)
11448 uint8_t flags;
11449 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
11450 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11451 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
11452 #define E2_INTEG_DATA_LB_TX_SHIFT 1
11453 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
11454 #define E2_INTEG_DATA_COS_TX_SHIFT 2
11455 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
11456 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
11457 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
11458 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
11459 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
11460 #define E2_INTEG_DATA_RESERVED_SHIFT 5
11461 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
11462 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
11463 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
11464#elif defined(__LITTLE_ENDIAN)
11465 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
11466 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */;
11467 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */;
11468 uint8_t flags;
11469 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */
11470 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0
11471 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */
11472 #define E2_INTEG_DATA_LB_TX_SHIFT 1
11473 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */
11474 #define E2_INTEG_DATA_COS_TX_SHIFT 2
11475 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */
11476 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3
11477 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */
11478 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4
11479 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */
11480 #define E2_INTEG_DATA_RESERVED_SHIFT 5
11481#endif
11482#if defined(__BIG_ENDIAN)
11483 uint16_t reserved3;
11484 uint8_t reserved2;
11485 uint8_t ramEn /* context area reserved for reading enable bit from ram */;
11486#elif defined(__LITTLE_ENDIAN)
11487 uint8_t ramEn /* context area reserved for reading enable bit from ram */;
11488 uint8_t reserved2;
11489 uint16_t reserved3;
11490#endif
11491};
11492
11493
11494/*
11495 * set mac event data $$KEEP_ENDIANNESS$$
11496 */
11497struct eth_event_data
11498{
11499 uint32_t echo /* set mac echo data to return to driver */;
11500 uint32_t reserved0;
11501 uint32_t reserved1;
11502};
11503
11504
11505/*
11506 * pf-vf event data $$KEEP_ENDIANNESS$$
11507 */
11508struct vf_pf_event_data
11509{
11510 uint8_t vf_id /* VF ID (0-63) */;
11511 uint8_t reserved0;
11512 uint16_t reserved1;
11513 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */;
11514 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */;
11515};
11516
11517/*
11518 * VF FLR event data $$KEEP_ENDIANNESS$$
11519 */
11520struct vf_flr_event_data
11521{
11522 uint8_t vf_id /* VF ID (0-63) */;
11523 uint8_t reserved0;
11524 uint16_t reserved1;
11525 uint32_t reserved2;
11526 uint32_t reserved3;
11527};
11528
11529/*
11530 * malicious VF event data $$KEEP_ENDIANNESS$$
11531 */
11532struct malicious_vf_event_data
11533{
11534 uint8_t vf_id /* VF ID (0-63) */;
11535 uint8_t err_id /* reason for malicious notification */;
11536 uint16_t reserved1;
11537 uint32_t reserved2;
11538 uint32_t reserved3;
11539};
11540
11541/*
11542 * vif list event data $$KEEP_ENDIANNESS$$
11543 */
11544struct vif_list_event_data
11545{
11546 uint8_t func_bit_map /* bit map of pf indice */;
11547 uint8_t echo;
11548 uint16_t reserved0;
11549 uint32_t reserved1;
11550 uint32_t reserved2;
11551};
11552
11553/*
11554 * function update event data $$KEEP_ENDIANNESS$$
11555 */
11556struct function_update_event_data
11557{
11558 uint8_t echo;
11559 uint8_t reserved;
11560 uint16_t reserved0;
11561 uint32_t reserved1;
11562 uint32_t reserved2;
11563};
11564
11565/*
11566 * union for all event ring message types
11567 */
11568union event_data
11569{
11570 struct vf_pf_event_data vf_pf_event /* vf-pf event data */;
11571 struct eth_event_data eth_event /* set mac event data */;
11572 struct cfc_del_event_data cfc_del_event /* cfc delete event data */;
11573 struct vf_flr_event_data vf_flr_event /* vf flr event data */;
11574 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */;
11575 struct vif_list_event_data vif_list_event /* vif list event data */;
11576 struct function_update_event_data function_update_event /* function update event data */;
11577};
11578
11579
11580/*
11581 * per PF event ring data
11582 */
11583struct event_ring_data
11584{
11585 struct regpair_native_t base_addr /* ring base address */;
11586#if defined(__BIG_ENDIAN)
11587 uint8_t index_id /* index ID within the status block */;
11588 uint8_t sb_id /* status block ID */;
11589 uint16_t producer /* event ring producer */;
11590#elif defined(__LITTLE_ENDIAN)
11591 uint16_t producer /* event ring producer */;
11592 uint8_t sb_id /* status block ID */;
11593 uint8_t index_id /* index ID within the status block */;
11594#endif
11595 uint32_t reserved0;
11596};
11597
11598
11599/*
11600 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$
11601 */
11602struct event_ring_msg
11603{
11604 uint8_t opcode;
11605 uint8_t error /* error on the mesasage */;
11606 uint16_t reserved1;
11607 union event_data data /* message data (96 bits data) */;
11608};
11609
11610/*
11611 * event ring next page element (128 bits)
11612 */
11613struct event_ring_next
11614{
11615 struct regpair_t addr /* Address of the next page of the ring */;
11616 uint32_t reserved[2];
11617};
11618
11619/*
11620 * union for event ring element types (each element is 128 bits)
11621 */
11622union event_ring_elem
11623{
11624 struct event_ring_msg message /* event ring message */;
11625 struct event_ring_next next_page /* event ring next page */;
11626};
11627
11628
11629/*
11630 * Common event ring opcodes
11631 */
11632enum event_ring_opcode
11633{
11634 EVENT_RING_OPCODE_VF_PF_CHANNEL,
11635 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */,
11636 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */,
11637 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */,
11638 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */,
11639 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */,
11640 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */,
11641 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */,
11642 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */,
11643 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */,
11644 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */,
11645 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */,
11646 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */,
11647 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */,
11648 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */,
11649 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */,
11650 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */,
11651 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */,
11652 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */,
11653 MAX_EVENT_RING_OPCODE};
11654
11655
11656/*
11657 * Modes for fairness algorithm
11658 */
11659enum fairness_mode
11660{
11661 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */,
11662 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */,
11663 MAX_FAIRNESS_MODE};
11664
11665
11666/*
11667 * Priority and cos $$KEEP_ENDIANNESS$$
11668 */
11669struct priority_cos
11670{
11671 uint8_t priority /* Priority */;
11672 uint8_t cos /* Cos */;
11673 uint16_t reserved1;
11674};
11675
11676/*
11677 * The data for flow control configuration $$KEEP_ENDIANNESS$$
11678 */
11679struct flow_control_configuration
11680{
11681 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */;
11682 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */;
11683 uint8_t dcb_version /* DCB version Increase by one on each DCB update */;
11684 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */;
11685 uint8_t reserved1;
11686 uint32_t reserved2;
11687 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES] /* Indicates the updated DCB outer tag priority per protocol */;
11688};
11689
11690
11691/*
11692 * $$KEEP_ENDIANNESS$$
11693 */
11694struct function_start_data
11695{
11696 uint8_t function_mode /* the function mode */;
11697 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode. (E2/E3 Only) */;
11698 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */;
11699 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
11700 uint8_t path_id;
11701 uint8_t network_cos_mode /* The cos mode for network traffic. */;
11702 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */;
11703 uint8_t no_added_tags /* If set, the mfTag length is always zero (used in UFP) */;
11704 uint16_t reserved0;
11705 uint32_t reserved1;
11706 uint8_t inner_clss_vxlan /* Classification type for VXLAN */;
11707 uint8_t inner_clss_l2gre /* If set, classification on the inner MAC/VLAN of L2GRE tunneled packets is enabled */;
11708 uint8_t inner_clss_l2geneve /* If set, classification on the inner MAC/(VLAN or VNI) of L2GENEVE tunneled packets is enabled */;
11709 uint8_t inner_rss /* If set, RSS on the inner headers of tunneled packets is enabled */;
11710 uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is disabled) */;
11711 uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is disabled) */;
11712 uint8_t sd_accept_mf_clss_fail /* If set, accept packets that fail Multi-Function Switch-Dependent classification. Only one VNIC on the port can have this set to 1 */;
11713 uint8_t sd_accept_mf_clss_fail_match_ethtype /* If set, accepted packets must match the ethertype of sd_clss_fail_ethtype */;
11714 uint16_t sd_accept_mf_clss_fail_ethtype /* Ethertype to match in the case of sd_accept_mf_clss_fail_match_ethtype */;
11715 uint16_t sd_vlan_eth_type /* Value of ether-type to use in the case of switch dependent multi-function mode. Setting this to 0 uses the default value of 0x8100 */;
11716 uint8_t sd_vlan_force_pri_flg /* If set, the SD Vlan Priority is forced to the value of the sd_vlan_pri_force_val field regardless of the DCB or inband VLAN priority. */;
11717 uint8_t sd_vlan_force_pri_val /* value to force SD Vlan Priority if sd_vlan_pri_force_flg is set */;
11718 uint8_t c2s_pri_tt_valid /* When set, c2s_pri_trans_table is valid */;
11719 uint8_t c2s_pri_default /* This value will be the sVlan pri value in case no Cvlan is present */;
11720 uint8_t reserved2[6];
11721 struct c2s_pri_trans_table_entry c2s_pri_trans_table /* Inner to outer vlan priority translation table entry for current PF */;
11722};
11723
11724
11725/*
11726 * $$KEEP_ENDIANNESS$$
11727 */
11728struct function_update_data
11729{
11730 uint8_t vif_id_change_flg /* If set, vif_id will be checked */;
11731 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */;
11732 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */;
11733 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */;
11734 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */;
11735 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */;
11736 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */;
11737 uint8_t network_cos_mode /* The cos mode for network traffic. */;
11738 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */;
11739 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */;
11740 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */;
11741 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */;
11742 uint8_t echo;
11743 uint8_t update_tunn_cfg_flg /* If set, tunneling config for the function will be updated according to the following fields */;
11744 uint8_t inner_clss_vxlan /* Classification type for VXLAN */;
11745 uint8_t inner_clss_l2gre /* If set, classification on the inner MAC/VLAN of L2GRE tunneled packets is enabled */;
11746 uint8_t inner_clss_l2geneve /* If set, classification on the inner MAC/(VLAN or VNI) of L2GENEVE tunneled packets is enabled */;
11747 uint8_t inner_rss /* If set, RSS on the inner headers of tunneled packets is enabled */;
11748 uint16_t vxlan_dst_port /* UDP Destination Port to be recognised as VXLAN tunneled packets (0 is disabled) */;
11749 uint16_t geneve_dst_port /* UDP Destination Port to be recognised as GENEVE tunneled packets (0 is disabled) */;
11750 uint8_t sd_vlan_force_pri_change_flg /* If set, the SD VLAN Priority Fixed configuration is updated from fields sd_vlan_pri_force_flg and sd_vlan_pri_force_val */;
11751 uint8_t sd_vlan_force_pri_flg /* If set, the SD Vlan Priority is forced to the value of the sd_vlan_pri_force_val field regardless of the DCB or inband VLAN priority. */;
11752 uint8_t sd_vlan_force_pri_val /* value to force SD Vlan Priority if sd_vlan_pri_force_flg is set */;
11753 uint8_t sd_vlan_tag_change_flg /* If set, the SD VLAN Tag is changed according to the field sd_vlan_tag */;
11754 uint8_t sd_vlan_eth_type_change_flg /* If set, the SD VLAN Ethertype is changed according to the field sd_vlan_eth_type */;
11755 uint8_t reserved1;
11756 uint16_t sd_vlan_tag /* New value of Outer Vlan in case of switch depended multi-function mode */;
11757 uint16_t sd_vlan_eth_type /* New value of ether-type in the case of switch dependent multi-function mode. Setting this to 0 restores the default value of 0x8100 */;
11758 uint16_t reserved0;
11759 uint32_t reserved2;
11760};
11761
11762
11763/*
11764 * FW version stored in the Xstorm RAM
11765 */
11766struct fw_version
11767{
11768#if defined(__BIG_ENDIAN)
11769 uint8_t engineering /* firmware current engineering version */;
11770 uint8_t revision /* firmware current revision version */;
11771 uint8_t minor /* firmware current minor version */;
11772 uint8_t major /* firmware current major version */;
11773#elif defined(__LITTLE_ENDIAN)
11774 uint8_t major /* firmware current major version */;
11775 uint8_t minor /* firmware current minor version */;
11776 uint8_t revision /* firmware current revision version */;
11777 uint8_t engineering /* firmware current engineering version */;
11778#endif
11779 uint32_t flags;
11780 #define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
11781 #define FW_VERSION_OPTIMIZED_SHIFT 0
11782 #define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */
11783 #define FW_VERSION_BIG_ENDIEN_SHIFT 1
11784 #define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */
11785 #define FW_VERSION_CHIP_VERSION_SHIFT 2
11786 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */
11787 #define __FW_VERSION_RESERVED_SHIFT 4
11788};
11789
11790
11791/*
11792 * Dynamic Host-Coalescing - Driver(host) counters
11793 */
11794struct hc_dynamic_sb_drv_counters
11795{
11796 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */;
11797};
11798
11799
11800/*
11801 * 2 bytes. configuration/state parameters for a single protocol index
11802 */
11803struct hc_index_data
11804{
11805#if defined(__BIG_ENDIAN)
11806 uint8_t flags;
11807 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
11808 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11809 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
11810 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
11811 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
11812 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
11813 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
11814 #define HC_INDEX_DATA_RESERVE_SHIFT 3
11815 uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
11816#elif defined(__LITTLE_ENDIAN)
11817 uint8_t timeout /* the timeout values for this index. Units are 4 usec */;
11818 uint8_t flags;
11819 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */
11820 #define HC_INDEX_DATA_SM_ID_SHIFT 0
11821 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */
11822 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1
11823 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */
11824 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2
11825 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */
11826 #define HC_INDEX_DATA_RESERVE_SHIFT 3
11827#endif
11828};
11829
11830
11831/*
11832 * HC state-machine
11833 */
11834struct hc_status_block_sm
11835{
11836#if defined(__BIG_ENDIAN)
11837 uint8_t igu_seg_id;
11838 uint8_t igu_sb_id /* sb_id within the IGU */;
11839 uint8_t timer_value /* Determines the time_to_expire */;
11840 uint8_t __flags;
11841#elif defined(__LITTLE_ENDIAN)
11842 uint8_t __flags;
11843 uint8_t timer_value /* Determines the time_to_expire */;
11844 uint8_t igu_sb_id /* sb_id within the IGU */;
11845 uint8_t igu_seg_id;
11846#endif
11847 uint32_t time_to_expire /* The time in which it expects to wake up */;
11848};
11849
11850/*
11851 * hold PCI identification variables- used in various places in firmware
11852 */
11853struct pci_entity
11854{
11855#if defined(__BIG_ENDIAN)
11856 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
11857 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
11858 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
11859 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
11860#elif defined(__LITTLE_ENDIAN)
11861 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */;
11862 uint8_t vnic_id /* Virtual NIC ID (0-3) */;
11863 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */;
11864 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */;
11865#endif
11866};
11867
11868/*
11869 * The fast-path status block meta-data, common to all chips
11870 */
11871struct hc_sb_data
11872{
11873 struct regpair_native_t host_sb_addr /* Host status block address */;
11874 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */;
11875 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
11876#if defined(__BIG_ENDIAN)
11877 uint8_t rsrv0;
11878 uint8_t state;
11879 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
11880 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
11881#elif defined(__LITTLE_ENDIAN)
11882 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */;
11883 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */;
11884 uint8_t state;
11885 uint8_t rsrv0;
11886#endif
11887 struct regpair_native_t rsrv1[2];
11888};
11889
11890
11891/*
11892 * Segment types for host coaslescing
11893 */
11894enum hc_segment
11895{
11896 HC_REGULAR_SEGMENT,
11897 HC_DEFAULT_SEGMENT,
11898 MAX_HC_SEGMENT};
11899
11900
11901/*
11902 * The fast-path status block meta-data
11903 */
11904struct hc_sp_status_block_data
11905{
11906 struct regpair_native_t host_sb_addr /* Host status block address */;
11907#if defined(__BIG_ENDIAN)
11908 uint8_t rsrv1;
11909 uint8_t state;
11910 uint8_t igu_seg_id /* segment id of the IGU */;
11911 uint8_t igu_sb_id /* sb_id within the IGU */;
11912#elif defined(__LITTLE_ENDIAN)
11913 uint8_t igu_sb_id /* sb_id within the IGU */;
11914 uint8_t igu_seg_id /* segment id of the IGU */;
11915 uint8_t state;
11916 uint8_t rsrv1;
11917#endif
11918 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */;
11919};
11920
11921
11922/*
11923 * The fast-path status block meta-data
11924 */
11925struct hc_status_block_data_e1x
11926{
11927 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */;
11928 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
11929};
11930
11931
11932/*
11933 * The fast-path status block meta-data
11934 */
11935struct hc_status_block_data_e2
11936{
11937 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */;
11938 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */;
11939};
11940
11941
11942/*
11943 * IGU block operartion modes (in Everest2)
11944 */
11945enum igu_mode
11946{
11947 HC_IGU_BC_MODE /* Backward compatible mode */,
11948 HC_IGU_NBC_MODE /* Non-backward compatible mode */,
11949 MAX_IGU_MODE};
11950
11951
11952/*
11953 * Inner Headers Classification Type
11954 */
11955enum inner_clss_type
11956{
11957 INNER_CLSS_DISABLED /* Inner Classification Disabled */,
11958 INNER_CLSS_USE_VLAN /* Inner Classification using MAC/Inner VLAN */,
11959 INNER_CLSS_USE_VNI /* Inner Classification using MAC/VNI (Only for VXLAN and GENEVE) */,
11960 MAX_INNER_CLSS_TYPE};
11961
11962
11963/*
11964 * IP versions
11965 */
11966enum ip_ver
11967{
11968 IP_V4,
11969 IP_V6,
11970 MAX_IP_VER};
11971
11972
11973/*
11974 * Malicious VF error ID
11975 */
11976enum malicious_vf_error_id
11977{
11978 MALICIOUS_VF_NO_ERROR /* Zero placeholder value */,
11979 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */,
11980 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */,
11981 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */,
11982 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */,
11983 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */,
11984 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */,
11985 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */,
11986 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */,
11987 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */,
11988 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */,
11989 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */,
11990 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */,
11991 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */,
11992 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */,
11993 MAX_MALICIOUS_VF_ERROR_ID};
11994
11995
11996/*
11997 * Multi-function modes
11998 */
11999enum mf_mode
12000{
12001 SINGLE_FUNCTION,
12002 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */,
12003 MULTI_FUNCTION_SI /* Switch independent (mac based) */,
12004 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */,
12005 MAX_MF_MODE};
12006
12007
12008/*
12009 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$
12010 */
12011struct tstorm_per_pf_stats
12012{
12013 struct regpair_t rcv_error_bytes /* number of bytes received with errors */;
12014};
12015
12016/*
12017 * $$KEEP_ENDIANNESS$$
12018 */
12019struct per_pf_stats
12020{
12021 struct tstorm_per_pf_stats tstorm_pf_statistics;
12022};
12023
12024
12025/*
12026 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$
12027 */
12028struct tstorm_per_port_stats
12029{
12030 uint32_t mac_discard /* number of packets with mac errors */;
12031 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */;
12032 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */;
12033 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */;
12034 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */;
12035 uint32_t reserved;
12036};
12037
12038/*
12039 * $$KEEP_ENDIANNESS$$
12040 */
12041struct per_port_stats
12042{
12043 struct tstorm_per_port_stats tstorm_port_statistics;
12044};
12045
12046
12047/*
12048 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$
12049 */
12050struct tstorm_per_queue_stats
12051{
12052 struct regpair_t rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */;
12053 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */;
12054 uint32_t checksum_discard /* number of total packets received with checksum error */;
12055 struct regpair_t rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */;
12056 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */;
12057 uint32_t pkts_too_big_discard /* number of too long packets received */;
12058 struct regpair_t rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */;
12059 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */;
12060 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */;
12061 uint16_t no_buff_discard;
12062 uint16_t reserved0;
12063 uint32_t reserved1;
12064};
12065
12066/*
12067 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$
12068 */
12069struct ustorm_per_queue_stats
12070{
12071 struct regpair_t ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */;
12072 struct regpair_t mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */;
12073 struct regpair_t bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */;
12074 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
12075 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
12076 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */;
12077 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */;
12078 struct regpair_t coalesced_bytes /* the number of bytes coalesced in all aggregations */;
12079 uint32_t coalesced_events /* the number of aggregations */;
12080 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */;
12081};
12082
12083/*
12084 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$
12085 */
12086struct xstorm_per_queue_stats
12087{
12088 struct regpair_t ucast_bytes_sent /* number of total bytes sent without errors */;
12089 struct regpair_t mcast_bytes_sent /* number of total bytes sent without errors */;
12090 struct regpair_t bcast_bytes_sent /* number of total bytes sent without errors */;
12091 uint32_t ucast_pkts_sent /* number of total packets sent without errors */;
12092 uint32_t mcast_pkts_sent /* number of total packets sent without errors */;
12093 uint32_t bcast_pkts_sent /* number of total packets sent without errors */;
12094 uint32_t error_drop_pkts /* number of total packets drooped due to errors */;
12095};
12096
12097/*
12098 * $$KEEP_ENDIANNESS$$
12099 */
12100struct per_queue_stats
12101{
12102 struct tstorm_per_queue_stats tstorm_queue_statistics;
12103 struct ustorm_per_queue_stats ustorm_queue_statistics;
12104 struct xstorm_per_queue_stats xstorm_queue_statistics;
12105};
12106
12107
12108/*
12109 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$
12110 */
12111struct pram_fw_version
12112{
12113 uint8_t major /* firmware current major version */;
12114 uint8_t minor /* firmware current minor version */;
12115 uint8_t revision /* firmware current revision version */;
12116 uint8_t engineering /* firmware current engineering version */;
12117 uint8_t flags;
12118 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */
12119 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0
12120 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */
12121 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1
12122 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */
12123 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3
12124 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */
12125 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4
12126 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */
12127 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6
12128};
12129
12130
12131/*
12132 * Ethernet slow path element
12133 */
12134union protocol_common_specific_data
12135{
12136 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
12137 struct regpair_t phy_address /* SPE physical address */;
12138 struct regpair_t mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */;
12139 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */;
12140};
12141
12142/*
12143 * The send queue element
12144 */
12145struct protocol_common_spe
12146{
12147 struct spe_hdr_t hdr /* SPE header */;
12148 union protocol_common_specific_data data /* data specific to common protocol */;
12149};
12150
12151
12152/*
12153 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$
12154 */
12155struct set_timesync_ramrod_data
12156{
12157 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */;
12158 uint8_t offset_cmd /* Timesync Offset Command */;
12159 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */;
12160 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */;
12161 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */;
12162 struct regpair_t offset_delta /* Timesync Offset Delta (in ns) */;
12163};
12164
12165
12166/*
12167 * The send queue element
12168 */
12169struct slow_path_element
12170{
12171 struct spe_hdr_t hdr /* common data for all protocols */;
12172 struct regpair_t protocol_data /* additional data specific to the protocol */;
12173};
12174
12175
12176/*
12177 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$
12178 */
12179struct stats_counter
12180{
12181 uint16_t xstats_counter /* xstorm statistics counter */;
12182 uint16_t reserved0;
12183 uint32_t reserved1;
12184 uint16_t tstats_counter /* tstorm statistics counter */;
12185 uint16_t reserved2;
12186 uint32_t reserved3;
12187 uint16_t ustats_counter /* ustorm statistics counter */;
12188 uint16_t reserved4;
12189 uint32_t reserved5;
12190 uint16_t cstats_counter /* ustorm statistics counter */;
12191 uint16_t reserved6;
12192 uint32_t reserved7;
12193};
12194
12195
12196/*
12197 * $$KEEP_ENDIANNESS$$
12198 */
12199struct stats_query_entry
12200{
12201 uint8_t kind;
12202 uint8_t index /* queue index */;
12203 uint16_t funcID /* the func the statistic will send to */;
12204 uint32_t reserved;
12205 struct regpair_t address /* pxp address */;
12206};
12207
12208/*
12209 * statistic command $$KEEP_ENDIANNESS$$
12210 */
12211struct stats_query_cmd_group
12212{
12213 struct stats_query_entry query[STATS_QUERY_CMD_COUNT];
12214};
12215
12216
12217/*
12218 * statistic command header $$KEEP_ENDIANNESS$$
12219 */
12220struct stats_query_header
12221{
12222 uint8_t cmd_num /* command number */;
12223 uint8_t reserved0;
12224 uint16_t drv_stats_counter;
12225 uint32_t reserved1;
12226 struct regpair_t stats_counters_addrs /* stats counter */;
12227};
12228
12229
12230/*
12231 * Types of statistcis query entry
12232 */
12233enum stats_query_type
12234{
12235 STATS_TYPE_QUEUE,
12236 STATS_TYPE_PORT,
12237 STATS_TYPE_PF,
12238 STATS_TYPE_TOE,
12239 STATS_TYPE_FCOE,
12240 MAX_STATS_QUERY_TYPE};
12241
12242
12243/*
12244 * Indicate of the function status block state
12245 */
12246enum status_block_state
12247{
12248 SB_DISABLED,
12249 SB_ENABLED,
12250 SB_CLEANED,
12251 MAX_STATUS_BLOCK_STATE};
12252
12253
12254/*
12255 * Storm IDs (including attentions for IGU related enums)
12256 */
12257enum storm_id
12258{
12259 USTORM_ID,
12260 CSTORM_ID,
12261 XSTORM_ID,
12262 TSTORM_ID,
12263 ATTENTION_ID,
12264 MAX_STORM_ID};
12265
12266
12267/*
12268 * Taffic types used in ETS and flow control algorithms
12269 */
12270enum traffic_type
12271{
12272 LLFC_TRAFFIC_TYPE_NW /* Networking */,
12273 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */,
12274 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */,
12275 MAX_TRAFFIC_TYPE};
12276
12277
12278/*
12279 * zone A per-queue data
12280 */
12281struct tstorm_queue_zone_data
12282{
12283 struct regpair_t reserved[4];
12284};
12285
12286
12287/*
12288 * zone B per-VF data
12289 */
12290struct tstorm_vf_zone_data
12291{
12292 struct regpair_t reserved;
12293};
12294
12295
12296/*
12297 * Add or Subtract Value for Set Timesync Ramrod
12298 */
12299enum ts_add_sub_value
12300{
12301 TS_SUB_VALUE /* Subtract Value */,
12302 TS_ADD_VALUE /* Add Value */,
12303 MAX_TS_ADD_SUB_VALUE};
12304
12305
12306/*
12307 * Drift-Adjust Commands for Set Timesync Ramrod
12308 */
12309enum ts_drift_adjust_cmd
12310{
12311 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */,
12312 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */,
12313 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */,
12314 MAX_TS_DRIFT_ADJUST_CMD};
12315
12316
12317/*
12318 * Offset Commands for Set Timesync Ramrod
12319 */
12320enum ts_offset_cmd
12321{
12322 TS_OFFSET_KEEP /* Keep Offset at current values */,
12323 TS_OFFSET_INC /* Increase Offset by Offset Delta */,
12324 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */,
12325 MAX_TS_OFFSET_CMD};
12326
12327
12328/*
12329 * Input for measuring Pci Latency
12330 */
12331struct t_measure_pci_latency_ctrl
12332{
12333 struct regpair_t read_addr /* Address to read from */;
12334#if defined(__BIG_ENDIAN)
12335 uint8_t sleep /* Measure including a thread sleep */;
12336 uint8_t enable /* Enable PCI Latency measurements */;
12337 uint8_t func_id /* Function ID */;
12338 uint8_t read_size /* Amount of bytes to read */;
12339#elif defined(__LITTLE_ENDIAN)
12340 uint8_t read_size /* Amount of bytes to read */;
12341 uint8_t func_id /* Function ID */;
12342 uint8_t enable /* Enable PCI Latency measurements */;
12343 uint8_t sleep /* Measure including a thread sleep */;
12344#endif
12345#if defined(__BIG_ENDIAN)
12346 uint16_t num_meas /* Number of measurements to make */;
12347 uint8_t reserved;
12348 uint8_t period_10us /* Number of 10s of microseconds to wait between measurements */;
12349#elif defined(__LITTLE_ENDIAN)
12350 uint8_t period_10us /* Number of 10s of microseconds to wait between measurements */;
12351 uint8_t reserved;
12352 uint16_t num_meas /* Number of measurements to make */;
12353#endif
12354};
12355
12356
12357/*
12358 * Input for measuring Pci Latency
12359 */
12360struct t_measure_pci_latency_data
12361{
12362#if defined(__BIG_ENDIAN)
12363 uint16_t max_time_ns /* Maximum Time for a read (in ns) */;
12364 uint16_t min_time_ns /* Minimum Time for a read (in ns) */;
12365#elif defined(__LITTLE_ENDIAN)
12366 uint16_t min_time_ns /* Minimum Time for a read (in ns) */;
12367 uint16_t max_time_ns /* Maximum Time for a read (in ns) */;
12368#endif
12369#if defined(__BIG_ENDIAN)
12370 uint16_t reserved;
12371 uint16_t num_reads /* Number of reads - Used for Average */;
12372#elif defined(__LITTLE_ENDIAN)
12373 uint16_t num_reads /* Number of reads - Used for Average */;
12374 uint16_t reserved;
12375#endif
12376 struct regpair_t sum_time_ns /* Sum of all the reads (in ns) - Used for Average */;
12377};
12378
12379
12380/*
12381 * zone A per-queue data
12382 */
12383struct ustorm_queue_zone_data
12384{
12385 struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */;
12386 struct regpair_t reserved[3];
12387};
12388
12389
12390/*
12391 * zone B per-VF data
12392 */
12393struct ustorm_vf_zone_data
12394{
12395 struct regpair_t reserved;
12396};
12397
12398
12399/*
12400 * data per VF-PF channel
12401 */
12402struct vf_pf_channel_data
12403{
12404#if defined(__BIG_ENDIAN)
12405 uint16_t reserved0;
12406 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
12407 uint8_t state /* channel state (ready / waiting for ack) */;
12408#elif defined(__LITTLE_ENDIAN)
12409 uint8_t state /* channel state (ready / waiting for ack) */;
12410 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */;
12411 uint16_t reserved0;
12412#endif
12413 uint32_t reserved1;
12414};
12415
12416
12417/*
12418 * State of VF-PF channel
12419 */
12420enum vf_pf_channel_state
12421{
12422 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */,
12423 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */,
12424 MAX_VF_PF_CHANNEL_STATE};
12425
12426
12427/*
12428 * vif_list_rule_kind
12429 */
12430enum vif_list_rule_kind
12431{
12432 VIF_LIST_RULE_SET,
12433 VIF_LIST_RULE_GET,
12434 VIF_LIST_RULE_CLEAR_ALL,
12435 VIF_LIST_RULE_CLEAR_FUNC,
12436 MAX_VIF_LIST_RULE_KIND};
12437
12438
12439/*
12440 * zone A per-queue data
12441 */
12442struct xstorm_queue_zone_data
12443{
12444 struct regpair_t reserved[4];
12445};
12446
12447
12448/*
12449 * zone B per-VF data
12450 */
12451struct xstorm_vf_zone_data
12452{
12453 struct regpair_t reserved;
12454};
12455
12456
12457/*
12458 * Out-of-order states
12459 */
12460enum tcp_ooo_event
12461{
12462 TCP_EVENT_ADD_PEN=0,
12463 TCP_EVENT_ADD_NEW_ISLE=1,
12464 TCP_EVENT_ADD_ISLE_RIGHT=2,
12465 TCP_EVENT_ADD_ISLE_LEFT=3,
12466 TCP_EVENT_JOIN=4,
12467 TCP_EVENT_NOP=5,
12468 MAX_TCP_OOO_EVENT};
12469
12470
12471/*
12472 * OOO support modes
12473 */
12474enum tcp_tstorm_ooo
12475{
12476 TCP_TSTORM_OOO_DROP_AND_PROC_ACK,
12477 TCP_TSTORM_OOO_SEND_PURE_ACK,
12478 TCP_TSTORM_OOO_SUPPORTED,
12479 MAX_TCP_TSTORM_OOO};
12480
12481
12482/*
12483 * toe statistics collected by the Cstorm (per port)
12484 */
12485struct cstorm_toe_stats
12486{
12487 uint32_t no_tx_cqes /* count the number of time storm find that there are no more CQEs */;
12488 uint32_t reserved;
12489};
12490
12491
12492/*
12493 * The toe storm context of Cstorm
12494 */
12495struct cstorm_toe_st_context
12496{
12497 uint32_t bds_ring_page_base_addr_lo /* Base address of next page in host bds ring */;
12498 uint32_t bds_ring_page_base_addr_hi /* Base address of next page in host bds ring */;
12499 uint32_t free_seq /* Sequnce number of the last byte that was free including */;
12500 uint32_t __last_rel_to_notify /* Accumulated release size for the next Chimney completion msg */;
12501#if defined(__BIG_ENDIAN)
12502 uint16_t __rss_params_ram_line /* The ram line containing the rss params */;
12503 uint16_t bd_cons /* The bd s ring consumer */;
12504#elif defined(__LITTLE_ENDIAN)
12505 uint16_t bd_cons /* The bd s ring consumer */;
12506 uint16_t __rss_params_ram_line /* The ram line containing the rss params */;
12507#endif
12508 uint32_t cpu_id /* CPU id for sending completion for TSS (only 8 bits are used) */;
12509 uint32_t prev_snd_max /* last snd_max that was used for dynamic HC producer update */;
12510 uint32_t __reserved4 /* reserved */;
12511};
12512
12513/*
12514 * Cstorm Toe Storm Aligned Context
12515 */
12516struct cstorm_toe_st_aligned_context
12517{
12518 struct cstorm_toe_st_context context /* context */;
12519};
12520
12521
12522/*
12523 * prefetched isle bd
12524 */
12525struct ustorm_toe_prefetched_isle_bd
12526{
12527 uint32_t __addr_lo /* receive payload base address - Single continuous buffer (page) pointer */;
12528 uint32_t __addr_hi /* receive payload base address - Single continuous buffer (page) pointer */;
12529#if defined(__BIG_ENDIAN)
12530 uint8_t __reserved1 /* reserved */;
12531 uint8_t __isle_num /* isle_number of the pre-fetched BD */;
12532 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */;
12533#elif defined(__LITTLE_ENDIAN)
12534 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */;
12535 uint8_t __isle_num /* isle_number of the pre-fetched BD */;
12536 uint8_t __reserved1 /* reserved */;
12537#endif
12538};
12539
12540/*
12541 * ring params
12542 */
12543struct ustorm_toe_ring_params
12544{
12545 uint32_t rq_cons_addr_lo /* A pointer to the next to consume application bd */;
12546 uint32_t rq_cons_addr_hi /* A pointer to the next to consume application bd */;
12547#if defined(__BIG_ENDIAN)
12548 uint8_t __rq_local_cons /* consumer of the local rq ring */;
12549 uint8_t __rq_local_prod /* producer of the local rq ring */;
12550 uint16_t rq_cons /* RQ consumer is the index of the next to consume application bd */;
12551#elif defined(__LITTLE_ENDIAN)
12552 uint16_t rq_cons /* RQ consumer is the index of the next to consume application bd */;
12553 uint8_t __rq_local_prod /* producer of the local rq ring */;
12554 uint8_t __rq_local_cons /* consumer of the local rq ring */;
12555#endif
12556};
12557
12558/*
12559 * prefetched bd
12560 */
12561struct ustorm_toe_prefetched_bd
12562{
12563 uint32_t __addr_lo /* receive payload base address - Single continuous buffer (page) pointer */;
12564 uint32_t __addr_hi /* receive payload base address - Single continuous buffer (page) pointer */;
12565#if defined(__BIG_ENDIAN)
12566 uint16_t flags;
12567 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */
12568 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12569 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */
12570 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
12571 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */
12572 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
12573 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */
12574 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
12575 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
12576 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
12577 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */;
12578#elif defined(__LITTLE_ENDIAN)
12579 uint16_t __buf_un_used /* Number of bytes left for placement in the pre fetched application/grq bd 0 size for buffer is not valid */;
12580 uint16_t flags;
12581 #define __USTORM_TOE_PREFETCHED_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */
12582 #define __USTORM_TOE_PREFETCHED_BD_START_SHIFT 0
12583 #define __USTORM_TOE_PREFETCHED_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */
12584 #define __USTORM_TOE_PREFETCHED_BD_END_SHIFT 1
12585 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */
12586 #define __USTORM_TOE_PREFETCHED_BD_NO_PUSH_SHIFT 2
12587 #define USTORM_TOE_PREFETCHED_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */
12588 #define USTORM_TOE_PREFETCHED_BD_SPLIT_SHIFT 3
12589 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
12590 #define __USTORM_TOE_PREFETCHED_BD_RESERVED1_SHIFT 4
12591#endif
12592};
12593
12594/*
12595 * Ustorm Toe Storm Context
12596 */
12597struct ustorm_toe_st_context
12598{
12599 uint32_t __pen_rq_placed /* Number of bytes that were placed in the RQ and not completed yet. */;
12600 uint32_t pen_grq_placed_bytes /* The number of in-order bytes (peninsula) that were placed in the GRQ (excluding bytes that were already copied to RQ BDs or RQ dummy BDs) */;
12601#if defined(__BIG_ENDIAN)
12602 uint8_t flags2;
12603 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* BitField flags2various state flags we will ignore grq push unless it is ping pong test */
12604 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12605 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* BitField flags2various state flags indicates if push timer is set */
12606 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
12607 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* BitField flags2various state flags indicates if RSS update is supported */
12608 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
12609 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* BitField flags2various state flags */
12610 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
12611 uint8_t __indirection_shift /* Offset in bits of the cupid of this connection on the 64Bits fetched from internal memoy */;
12612 uint16_t indirection_ram_offset /* address offset in internal memory from the beginning of the table consisting the cpu id of this connection (Only 12 bits are used) */;
12613#elif defined(__LITTLE_ENDIAN)
12614 uint16_t indirection_ram_offset /* address offset in internal memory from the beginning of the table consisting the cpu id of this connection (Only 12 bits are used) */;
12615 uint8_t __indirection_shift /* Offset in bits of the cupid of this connection on the 64Bits fetched from internal memoy */;
12616 uint8_t flags2;
12617 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH (0x1<<0) /* BitField flags2various state flags we will ignore grq push unless it is ping pong test */
12618 #define USTORM_TOE_ST_CONTEXT_IGNORE_GRQ_PUSH_SHIFT 0
12619 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG (0x1<<1) /* BitField flags2various state flags indicates if push timer is set */
12620 #define USTORM_TOE_ST_CONTEXT_PUSH_FLAG_SHIFT 1
12621 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED (0x1<<2) /* BitField flags2various state flags indicates if RSS update is supported */
12622 #define USTORM_TOE_ST_CONTEXT_RSS_UPDATE_ENABLED_SHIFT 2
12623 #define USTORM_TOE_ST_CONTEXT_RESERVED0 (0x1F<<3) /* BitField flags2various state flags */
12624 #define USTORM_TOE_ST_CONTEXT_RESERVED0_SHIFT 3
12625#endif
12626 uint32_t __rq_available_bytes;
12627#if defined(__BIG_ENDIAN)
12628 uint8_t isles_counter /* signals that dca is enabled */;
12629 uint8_t __push_timer_state /* indicates if push timer is set */;
12630 uint16_t rcv_indication_size /* The chip will release the current GRQ buffer to the driver when it knows that the driver has no knowledge of other GRQ payload that it can indicate and the current GRQ buffer has at least RcvIndicationSize bytes. */;
12631#elif defined(__LITTLE_ENDIAN)
12632 uint16_t rcv_indication_size /* The chip will release the current GRQ buffer to the driver when it knows that the driver has no knowledge of other GRQ payload that it can indicate and the current GRQ buffer has at least RcvIndicationSize bytes. */;
12633 uint8_t __push_timer_state /* indicates if push timer is set */;
12634 uint8_t isles_counter /* signals that dca is enabled */;
12635#endif
12636 uint32_t __min_expiration_time /* if the timer will expire before this time it will be considered as a race */;
12637 uint32_t initial_rcv_wnd /* the maximal advertized window */;
12638 uint32_t __bytes_cons /* the last rq_available_bytes producer that was read from host - used to know how many bytes were added */;
12639 uint32_t __prev_consumed_grq_bytes /* the last rq_available_bytes producer that was read from host - used to know how many bytes were added */;
12640 uint32_t prev_rcv_win_right_edge /* siquence of the last bytes that can be received - used to know how many bytes were added */;
12641 uint32_t rcv_nxt /* Receive sequence: next expected - of the right most received packet */;
12642 struct ustorm_toe_prefetched_isle_bd __isle_bd /* prefetched bd for the isle */;
12643 struct ustorm_toe_ring_params pen_ring_params /* peninsula ring params */;
12644 struct ustorm_toe_prefetched_bd __pen_bd_0 /* peninsula prefetched bd for the peninsula */;
12645 struct ustorm_toe_prefetched_bd __pen_bd_1 /* peninsula prefetched bd for the peninsula */;
12646 struct ustorm_toe_prefetched_bd __pen_bd_2 /* peninsula prefetched bd for the peninsula */;
12647 struct ustorm_toe_prefetched_bd __pen_bd_3 /* peninsula prefetched bd for the peninsula */;
12648 struct ustorm_toe_prefetched_bd __pen_bd_4 /* peninsula prefetched bd for the peninsula */;
12649 struct ustorm_toe_prefetched_bd __pen_bd_5 /* peninsula prefetched bd for the peninsula */;
12650 struct ustorm_toe_prefetched_bd __pen_bd_6 /* peninsula prefetched bd for the peninsula */;
12651 struct ustorm_toe_prefetched_bd __pen_bd_7 /* peninsula prefetched bd for the peninsula */;
12652 struct ustorm_toe_prefetched_bd __pen_bd_8 /* peninsula prefetched bd for the peninsula */;
12653 struct ustorm_toe_prefetched_bd __pen_bd_9 /* peninsula prefetched bd for the peninsula */;
12654 uint32_t __reserved3 /* reserved */;
12655};
12656
12657/*
12658 * Ustorm Toe Storm Aligned Context
12659 */
12660struct ustorm_toe_st_aligned_context
12661{
12662 struct ustorm_toe_st_context context /* context */;
12663};
12664
12665/*
12666 * TOE context region, used only in TOE
12667 */
12668struct tstorm_toe_st_context_section
12669{
12670 uint32_t reserved0[3];
12671};
12672
12673/*
12674 * The TOE non-aggregative context of Tstorm
12675 */
12676struct tstorm_toe_st_context
12677{
12678 struct tstorm_tcp_st_context_section tcp /* TCP context region, shared in TOE, RDMA and ISCSI */;
12679 struct tstorm_toe_st_context_section toe /* TOE context region, used only in TOE */;
12680};
12681
12682/*
12683 * The TOE non-aggregative aligned context of Tstorm
12684 */
12685struct tstorm_toe_st_aligned_context
12686{
12687 struct tstorm_toe_st_context context /* context */;
12688 uint8_t padding[16] /* padding to 64 byte aligned */;
12689};
12690
12691/*
12692 * TOE context section
12693 */
12694struct xstorm_toe_context_section
12695{
12696 uint32_t tx_bd_page_base_lo /* BD page base address at the host for TxBdCons */;
12697 uint32_t tx_bd_page_base_hi /* BD page base address at the host for TxBdCons */;
12698#if defined(__BIG_ENDIAN)
12699 uint16_t tx_bd_offset /* The offset within the BD */;
12700 uint16_t tx_bd_cons /* The transmit BD cons pointer to the host ring */;
12701#elif defined(__LITTLE_ENDIAN)
12702 uint16_t tx_bd_cons /* The transmit BD cons pointer to the host ring */;
12703 uint16_t tx_bd_offset /* The offset within the BD */;
12704#endif
12705#if defined(__BIG_ENDIAN)
12706 uint16_t bd_prod;
12707 uint16_t seqMismatchCnt;
12708#elif defined(__LITTLE_ENDIAN)
12709 uint16_t seqMismatchCnt;
12710 uint16_t bd_prod;
12711#endif
12712 uint32_t driver_doorbell_info_ptr_lo;
12713 uint32_t driver_doorbell_info_ptr_hi;
12714};
12715
12716/*
12717 * Xstorm Toe Storm Context
12718 */
12719struct xstorm_toe_st_context
12720{
12721 struct xstorm_common_context_section common;
12722 struct xstorm_toe_context_section toe;
12723};
12724
12725/*
12726 * Xstorm Toe Storm Aligned Context
12727 */
12728struct xstorm_toe_st_aligned_context
12729{
12730 struct xstorm_toe_st_context context /* context */;
12731};
12732
12733/*
12734 * Ethernet connection context
12735 */
12736struct toe_context
12737{
12738 struct ustorm_toe_st_aligned_context ustorm_st_context /* Ustorm storm context */;
12739 struct tstorm_toe_st_aligned_context tstorm_st_context /* Tstorm storm context */;
12740 struct xstorm_toe_ag_context xstorm_ag_context /* Xstorm aggregative context */;
12741 struct tstorm_toe_ag_context tstorm_ag_context /* Tstorm aggregative context */;
12742 struct cstorm_toe_ag_context cstorm_ag_context /* Cstorm aggregative context */;
12743 struct ustorm_toe_ag_context ustorm_ag_context /* Ustorm aggregative context */;
12744 struct timers_block_context timers_context /* Timers block context */;
12745 struct xstorm_toe_st_aligned_context xstorm_st_context /* Xstorm storm context */;
12746 struct cstorm_toe_st_aligned_context cstorm_st_context /* Cstorm storm context */;
12747};
12748
12749
12750/*
12751 * ramrod data for toe protocol initiate offload ramrod (CQE)
12752 */
12753struct toe_initiate_offload_ramrod_data
12754{
12755 uint32_t flags;
12756 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED (0x1<<0) /* BitField flags error in searcher configuration */
12757 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_SEARCH_CONFIG_FAILED_SHIFT 0
12758 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE (0x1<<1) /* BitField flags license errors */
12759 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_LICENSE_FAILURE_SHIFT 1
12760 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0 (0x3FFFFFFF<<2) /* BitField flags */
12761 #define TOE_INITIATE_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 2
12762 uint32_t reserved1;
12763};
12764
12765
12766/*
12767 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits)
12768 */
12769struct toe_init_ramrod_data
12770{
12771#if defined(__BIG_ENDIAN)
12772 uint16_t reserved1;
12773 uint8_t reserved0;
12774 uint8_t rss_num /* the rss num in its rqr to complete this ramrod */;
12775#elif defined(__LITTLE_ENDIAN)
12776 uint8_t rss_num /* the rss num in its rqr to complete this ramrod */;
12777 uint8_t reserved0;
12778 uint16_t reserved1;
12779#endif
12780 uint32_t reserved2;
12781};
12782
12783
12784/*
12785 * next page pointer bd used in toe CQs and tx/rx bd chains
12786 */
12787struct toe_page_addr_bd
12788{
12789 uint32_t addr_lo /* page pointer */;
12790 uint32_t addr_hi /* page pointer */;
12791 uint8_t reserved[8] /* resereved for driver use */;
12792};
12793
12794
12795/*
12796 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits)
12797 */
12798union toe_ramrod_data
12799{
12800 struct ramrod_data general;
12801 struct toe_initiate_offload_ramrod_data initiate_offload;
12802};
12803
12804
12805/*
12806 * TOE_RX_CQES_OPCODE_RSS_UPD results
12807 */
12808enum toe_rss_update_opcode
12809{
12810 TOE_RSS_UPD_QUIET,
12811 TOE_RSS_UPD_SLEEPING,
12812 TOE_RSS_UPD_DELAYED,
12813 MAX_TOE_RSS_UPDATE_OPCODE};
12814
12815
12816/*
12817 * union for ramrod data for TOE protocol (CQE) (force size of 16 bits)
12818 */
12819struct toe_rss_update_ramrod_data
12820{
12821 uint8_t indirection_table[128] /* RSS indirection table */;
12822#if defined(__BIG_ENDIAN)
12823 uint16_t reserved0;
12824 uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 bitmap is not valid option). The port is gleaned from the CID */;
12825#elif defined(__LITTLE_ENDIAN)
12826 uint16_t toe_rss_bitmap /* The bitmap specifies which toe rss chains to complete the ramrod on (0 bitmap is not valid option). The port is gleaned from the CID */;
12827 uint16_t reserved0;
12828#endif
12829 uint32_t reserved1;
12830};
12831
12832
12833/*
12834 * The toe Rx Buffer Descriptor
12835 */
12836struct toe_rx_bd
12837{
12838 uint32_t addr_lo /* receive payload base address - Single continuous buffer (page) pointer */;
12839 uint32_t addr_hi /* receive payload base address - Single continuous buffer (page) pointer */;
12840#if defined(__BIG_ENDIAN)
12841 uint16_t flags;
12842 #define TOE_RX_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */
12843 #define TOE_RX_BD_START_SHIFT 0
12844 #define TOE_RX_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */
12845 #define TOE_RX_BD_END_SHIFT 1
12846 #define TOE_RX_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */
12847 #define TOE_RX_BD_NO_PUSH_SHIFT 2
12848 #define TOE_RX_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */
12849 #define TOE_RX_BD_SPLIT_SHIFT 3
12850 #define TOE_RX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
12851 #define TOE_RX_BD_RESERVED1_SHIFT 4
12852 uint16_t size /* Size of the buffer pointed by the BD */;
12853#elif defined(__LITTLE_ENDIAN)
12854 uint16_t size /* Size of the buffer pointed by the BD */;
12855 uint16_t flags;
12856 #define TOE_RX_BD_START (0x1<<0) /* BitField flagsbd command flags this bd is the beginning of an application buffer */
12857 #define TOE_RX_BD_START_SHIFT 0
12858 #define TOE_RX_BD_END (0x1<<1) /* BitField flagsbd command flags this bd is the end of an application buffer */
12859 #define TOE_RX_BD_END_SHIFT 1
12860 #define TOE_RX_BD_NO_PUSH (0x1<<2) /* BitField flagsbd command flags this application buffer must not be partially completed */
12861 #define TOE_RX_BD_NO_PUSH_SHIFT 2
12862 #define TOE_RX_BD_SPLIT (0x1<<3) /* BitField flagsbd command flags this application buffer is part of a bigger buffer and this buffer is not the last */
12863 #define TOE_RX_BD_SPLIT_SHIFT 3
12864 #define TOE_RX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
12865 #define TOE_RX_BD_RESERVED1_SHIFT 4
12866#endif
12867 uint32_t dbg_bytes_prod /* a cyclic parameter that caounts how many byte were available for placement till no not including this bd */;
12868};
12869
12870
12871/*
12872 * ramrod data for toe protocol General rx completion
12873 */
12874struct toe_rx_completion_ramrod_data
12875{
12876#if defined(__BIG_ENDIAN)
12877 uint16_t reserved0;
12878 uint16_t hash_value /* information for ustorm to use in completion */;
12879#elif defined(__LITTLE_ENDIAN)
12880 uint16_t hash_value /* information for ustorm to use in completion */;
12881 uint16_t reserved0;
12882#endif
12883 uint32_t reserved1;
12884};
12885
12886
12887/*
12888 * OOO params in union for TOE rx cqe data
12889 */
12890struct toe_rx_cqe_ooo_params
12891{
12892 uint32_t ooo_params;
12893 #define TOE_RX_CQE_OOO_PARAMS_NBYTES (0xFFFFFF<<0) /* BitField ooo_paramsdata params for OOO cqe connection nbytes */
12894 #define TOE_RX_CQE_OOO_PARAMS_NBYTES_SHIFT 0
12895 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM (0xFF<<24) /* BitField ooo_paramsdata params for OOO cqe isle number for OOO completions */
12896 #define TOE_RX_CQE_OOO_PARAMS_ISLE_NUM_SHIFT 24
12897};
12898
12899/*
12900 * in order params in union for TOE rx cqe data
12901 */
12902struct toe_rx_cqe_in_order_params
12903{
12904 uint32_t in_order_params;
12905 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES (0xFFFFFFFF<<0) /* BitField in_order_paramsdata params for in order cqe connection nbytes */
12906 #define TOE_RX_CQE_IN_ORDER_PARAMS_NBYTES_SHIFT 0
12907};
12908
12909/*
12910 * union for TOE rx cqe data
12911 */
12912union toe_rx_cqe_data_union
12913{
12914 struct toe_rx_cqe_ooo_params ooo_params /* data params for OOO cqe - nbytes and isle number */;
12915 struct toe_rx_cqe_in_order_params in_order_params /* data params for in order cqe - nbytes */;
12916 uint32_t raw_data /* global data param */;
12917};
12918
12919/*
12920 * The toe Rx cq element
12921 */
12922struct toe_rx_cqe
12923{
12924 uint32_t params1;
12925 #define TOE_RX_CQE_CID (0xFFFFFF<<0) /* BitField params1completion cid and opcode connection id */
12926 #define TOE_RX_CQE_CID_SHIFT 0
12927 #define TOE_RX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField params1completion cid and opcode completion opcode - use enum toe_rx_cqe_type or toe_rss_update_opcode */
12928 #define TOE_RX_CQE_COMPLETION_OPCODE_SHIFT 24
12929 union toe_rx_cqe_data_union data /* completion cid and opcode */;
12930};
12931
12932
12933/*
12934 * toe rx doorbell data in host memory
12935 */
12936struct toe_rx_db_data
12937{
12938 uint32_t rcv_win_right_edge /* siquence of the last bytes that can be received */;
12939 uint32_t bytes_prod /* cyclic counter of posted bytes */;
12940#if defined(__BIG_ENDIAN)
12941 uint8_t reserved1 /* reserved */;
12942 uint8_t flags;
12943 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* BitField flags ustorm ignores window updates when this flag is set */
12944 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12945 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* BitField flags indicates if to set push timer due to partially filled receive request after offload */
12946 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
12947 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* BitField flags */
12948 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
12949 uint16_t bds_prod /* cyclic counter of bds to post */;
12950#elif defined(__LITTLE_ENDIAN)
12951 uint16_t bds_prod /* cyclic counter of bds to post */;
12952 uint8_t flags;
12953 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES (0x1<<0) /* BitField flags ustorm ignores window updates when this flag is set */
12954 #define TOE_RX_DB_DATA_IGNORE_WND_UPDATES_SHIFT 0
12955 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF (0x1<<1) /* BitField flags indicates if to set push timer due to partially filled receive request after offload */
12956 #define TOE_RX_DB_DATA_PARTIAL_FILLED_BUF_SHIFT 1
12957 #define TOE_RX_DB_DATA_RESERVED0 (0x3F<<2) /* BitField flags */
12958 #define TOE_RX_DB_DATA_RESERVED0_SHIFT 2
12959 uint8_t reserved1 /* reserved */;
12960#endif
12961 uint32_t consumed_grq_bytes /* cyclic counter of consumed grq bytes */;
12962};
12963
12964
12965/*
12966 * The toe Rx Generic Buffer Descriptor
12967 */
12968struct toe_rx_grq_bd
12969{
12970 uint32_t addr_lo /* receive payload base address - Single continuous buffer (page) pointer */;
12971 uint32_t addr_hi /* receive payload base address - Single continuous buffer (page) pointer */;
12972};
12973
12974
12975/*
12976 * toe slow path element
12977 */
12978union toe_spe_data
12979{
12980 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */;
12981 struct regpair_t phys_addr /* used in initiate offload ramrod */;
12982 struct toe_rx_completion_ramrod_data rx_completion /* used in all ramrods that have a general rx completion */;
12983 struct toe_init_ramrod_data toe_init /* used in toe init ramrod */;
12984};
12985
12986/*
12987 * toe slow path element
12988 */
12989struct toe_spe
12990{
12991 struct spe_hdr_t hdr /* common data for all protocols */;
12992 union toe_spe_data toe_data /* data specific to toe protocol */;
12993};
12994
12995
12996/*
12997 * TOE slow path opcodes (opcode 0 is illegal) - includes commands and completions
12998 */
12999enum toe_sq_opcode_type
13000{
13001 CMP_OPCODE_TOE_GA=1,
13002 CMP_OPCODE_TOE_GR=2,
13003 CMP_OPCODE_TOE_GNI=3,
13004 CMP_OPCODE_TOE_GAIR=4,
13005 CMP_OPCODE_TOE_GAIL=5,
13006 CMP_OPCODE_TOE_GRI=6,
13007 CMP_OPCODE_TOE_GJ=7,
13008 CMP_OPCODE_TOE_DGI=8,
13009 CMP_OPCODE_TOE_CMP=9,
13010 CMP_OPCODE_TOE_REL=10,
13011 CMP_OPCODE_TOE_SKP=11,
13012 CMP_OPCODE_TOE_URG=12,
13013 CMP_OPCODE_TOE_RT_TO=13,
13014 CMP_OPCODE_TOE_KA_TO=14,
13015 CMP_OPCODE_TOE_MAX_RT=15,
13016 CMP_OPCODE_TOE_DBT_RE=16,
13017 CMP_OPCODE_TOE_SYN=17,
13018 CMP_OPCODE_TOE_OPT_ERR=18,
13019 CMP_OPCODE_TOE_FW2_TO=19,
13020 CMP_OPCODE_TOE_2WY_CLS=20,
13021 CMP_OPCODE_TOE_TX_CMP=21,
13022 RAMROD_OPCODE_TOE_INIT=32,
13023 RAMROD_OPCODE_TOE_RSS_UPDATE=33,
13024 RAMROD_OPCODE_TOE_TERMINATE_RING=34,
13025 CMP_OPCODE_TOE_RST_RCV=48,
13026 CMP_OPCODE_TOE_FIN_RCV=49,
13027 CMP_OPCODE_TOE_FIN_UPL=50,
13028 CMP_OPCODE_TOE_SRC_ERR=51,
13029 CMP_OPCODE_TOE_LCN_ERR=52,
13030 RAMROD_OPCODE_TOE_INITIATE_OFFLOAD=80,
13031 RAMROD_OPCODE_TOE_SEARCHER_DELETE=81,
13032 RAMROD_OPCODE_TOE_TERMINATE=82,
13033 RAMROD_OPCODE_TOE_QUERY=83,
13034 RAMROD_OPCODE_TOE_RESET_SEND=84,
13035 RAMROD_OPCODE_TOE_INVALIDATE=85,
13036 RAMROD_OPCODE_TOE_EMPTY_RAMROD=86,
13037 RAMROD_OPCODE_TOE_UPDATE=87,
13038 MAX_TOE_SQ_OPCODE_TYPE};
13039
13040
13041/*
13042 * Toe statistics collected by the Xstorm (per port)
13043 */
13044struct xstorm_toe_stats_section
13045{
13046 uint32_t tcp_out_segments;
13047 uint32_t tcp_retransmitted_segments;
13048 struct regpair_t ip_out_octets;
13049 uint32_t ip_out_requests;
13050 uint32_t reserved;
13051};
13052
13053/*
13054 * Toe statistics collected by the Xstorm (per port)
13055 */
13056struct xstorm_toe_stats
13057{
13058 struct xstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */;
13059 uint32_t reserved[2];
13060};
13061
13062/*
13063 * Toe statistics collected by the Tstorm (per port)
13064 */
13065struct tstorm_toe_stats_section
13066{
13067 uint32_t ip_in_receives;
13068 uint32_t ip_in_delivers;
13069 struct regpair_t ip_in_octets;
13070 uint32_t tcp_in_errors /* all discards except discards already counted by Ipv4 stats */;
13071 uint32_t ip_in_header_errors /* IP checksum */;
13072 uint32_t ip_in_discards /* no resources */;
13073 uint32_t ip_in_truncated_packets;
13074};
13075
13076/*
13077 * Toe statistics collected by the Tstorm (per port)
13078 */
13079struct tstorm_toe_stats
13080{
13081 struct tstorm_toe_stats_section statistics[2] /* 0 - ipv4 , 1 - ipv6 */;
13082 uint32_t reserved[2];
13083};
13084
13085/*
13086 * Eth statistics query structure for the eth_stats_query ramrod
13087 */
13088struct toe_stats_query
13089{
13090 struct xstorm_toe_stats xstorm_toe /* Xstorm Toe statistics structure */;
13091 struct tstorm_toe_stats tstorm_toe /* Tstorm Toe statistics structure */;
13092 struct cstorm_toe_stats cstorm_toe /* Cstorm Toe statistics structure */;
13093};
13094
13095
13096/*
13097 * The toe Tx Buffer Descriptor
13098 */
13099struct toe_tx_bd
13100{
13101 uint32_t addr_lo /* tranasmit payload base address - Single continuous buffer (page) pointer */;
13102 uint32_t addr_hi /* tranasmit payload base address - Single continuous buffer (page) pointer */;
13103#if defined(__BIG_ENDIAN)
13104 uint16_t flags;
13105 #define TOE_TX_BD_PUSH (0x1<<0) /* BitField flagsbd command flags End of data flag */
13106 #define TOE_TX_BD_PUSH_SHIFT 0
13107 #define TOE_TX_BD_NOTIFY (0x1<<1) /* BitField flagsbd command flags notify driver with released data bytes including this bd */
13108 #define TOE_TX_BD_NOTIFY_SHIFT 1
13109 #define TOE_TX_BD_FIN (0x1<<2) /* BitField flagsbd command flags send fin request */
13110 #define TOE_TX_BD_FIN_SHIFT 2
13111 #define TOE_TX_BD_LARGE_IO (0x1<<3) /* BitField flagsbd command flags this bd is part of an application buffer larger than mss */
13112 #define TOE_TX_BD_LARGE_IO_SHIFT 3
13113 #define TOE_TX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
13114 #define TOE_TX_BD_RESERVED1_SHIFT 4
13115 uint16_t size /* Size of the data represented by the BD */;
13116#elif defined(__LITTLE_ENDIAN)
13117 uint16_t size /* Size of the data represented by the BD */;
13118 uint16_t flags;
13119 #define TOE_TX_BD_PUSH (0x1<<0) /* BitField flagsbd command flags End of data flag */
13120 #define TOE_TX_BD_PUSH_SHIFT 0
13121 #define TOE_TX_BD_NOTIFY (0x1<<1) /* BitField flagsbd command flags notify driver with released data bytes including this bd */
13122 #define TOE_TX_BD_NOTIFY_SHIFT 1
13123 #define TOE_TX_BD_FIN (0x1<<2) /* BitField flagsbd command flags send fin request */
13124 #define TOE_TX_BD_FIN_SHIFT 2
13125 #define TOE_TX_BD_LARGE_IO (0x1<<3) /* BitField flagsbd command flags this bd is part of an application buffer larger than mss */
13126 #define TOE_TX_BD_LARGE_IO_SHIFT 3
13127 #define TOE_TX_BD_RESERVED1 (0xFFF<<4) /* BitField flagsbd command flags reserved */
13128 #define TOE_TX_BD_RESERVED1_SHIFT 4
13129#endif
13130 uint32_t nextBdStartSeq;
13131};
13132
13133
13134/*
13135 * The toe Tx cqe
13136 */
13137struct toe_tx_cqe
13138{
13139 uint32_t params;
13140 #define TOE_TX_CQE_CID (0xFFFFFF<<0) /* BitField paramscompletion cid and opcode connection id */
13141 #define TOE_TX_CQE_CID_SHIFT 0
13142 #define TOE_TX_CQE_COMPLETION_OPCODE (0xFF<<24) /* BitField paramscompletion cid and opcode completion opcode (use enum toe_tx_cqe_type) */
13143 #define TOE_TX_CQE_COMPLETION_OPCODE_SHIFT 24
13144 uint32_t len /* the more2release in Bytes */;
13145};
13146
13147
13148/*
13149 * toe tx doorbell data in host memory
13150 */
13151struct toe_tx_db_data
13152{
13153 uint32_t bytes_prod_seq /* greatest sequence the chip can transmit */;
13154#if defined(__BIG_ENDIAN)
13155 uint16_t flags;
13156 #define TOE_TX_DB_DATA_FIN (0x1<<0) /* BitField flags flag for post FIN request */
13157 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13158 #define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* BitField flags flag for last doorbell - flushing doorbell queue */
13159 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1
13160 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /* BitField flags */
13161 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2
13162 uint16_t bds_prod /* cyclic counter of posted bds */;
13163#elif defined(__LITTLE_ENDIAN)
13164 uint16_t bds_prod /* cyclic counter of posted bds */;
13165 uint16_t flags;
13166 #define TOE_TX_DB_DATA_FIN (0x1<<0) /* BitField flags flag for post FIN request */
13167 #define TOE_TX_DB_DATA_FIN_SHIFT 0
13168 #define TOE_TX_DB_DATA_FLUSH (0x1<<1) /* BitField flags flag for last doorbell - flushing doorbell queue */
13169 #define TOE_TX_DB_DATA_FLUSH_SHIFT 1
13170 #define TOE_TX_DB_DATA_RESERVE (0x3FFF<<2) /* BitField flags */
13171 #define TOE_TX_DB_DATA_RESERVE_SHIFT 2
13172#endif
13173};
13174
13175
13176/*
13177 * sturct used in update ramrod. Driver notifies chip which fields have changed via the bitmap $$KEEP_ENDIANNESS$$
13178 */
13179struct toe_update_ramrod_cached_params
13180{
13181 uint16_t changed_fields;
13182 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED (0x1<<0) /* BitField changed_fieldsbitmap for indicating changed fields */
13183 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_DEST_ADDR_CHANGED_SHIFT 0
13184 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED (0x1<<1) /* BitField changed_fieldsbitmap for indicating changed fields */
13185 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MSS_CHANGED_SHIFT 1
13186 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED (0x1<<2) /* BitField changed_fieldsbitmap for indicating changed fields */
13187 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 2
13188 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED (0x1<<3) /* BitField changed_fieldsbitmap for indicating changed fields */
13189 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_INTERVAL_CHANGED_SHIFT 3
13190 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED (0x1<<4) /* BitField changed_fieldsbitmap for indicating changed fields */
13191 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_MAX_RT_CHANGED_SHIFT 4
13192 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED (0x1<<5) /* BitField changed_fieldsbitmap for indicating changed fields */
13193 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_RCV_INDICATION_SIZE_CHANGED_SHIFT 5
13194 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED (0x1<<6) /* BitField changed_fieldsbitmap for indicating changed fields */
13195 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_FLOW_LABEL_CHANGED_SHIFT 6
13196 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED (0x1<<7) /* BitField changed_fieldsbitmap for indicating changed fields */
13197 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_KEEPALIVE_CHANGED_SHIFT 7
13198 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED (0x1<<8) /* BitField changed_fieldsbitmap for indicating changed fields */
13199 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_ENABLE_NAGLE_CHANGED_SHIFT 8
13200 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED (0x1<<9) /* BitField changed_fieldsbitmap for indicating changed fields */
13201 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TTL_CHANGED_SHIFT 9
13202 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED (0x1<<10) /* BitField changed_fieldsbitmap for indicating changed fields */
13203 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_HOP_LIMIT_CHANGED_SHIFT 10
13204 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED (0x1<<11) /* BitField changed_fieldsbitmap for indicating changed fields */
13205 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TOS_CHANGED_SHIFT 11
13206 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED (0x1<<12) /* BitField changed_fieldsbitmap for indicating changed fields */
13207 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_TRAFFIC_CLASS_CHANGED_SHIFT 12
13208 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED (0x1<<13) /* BitField changed_fieldsbitmap for indicating changed fields */
13209 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_KA_MAX_PROBE_COUNT_CHANGED_SHIFT 13
13210 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED (0x1<<14) /* BitField changed_fieldsbitmap for indicating changed fields */
13211 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_USER_PRIORITY_CHANGED_SHIFT 14
13212 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED (0x1<<15) /* BitField changed_fieldsbitmap for indicating changed fields */
13213 #define TOE_UPDATE_RAMROD_CACHED_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 15
13214 uint8_t ka_restart /* Only 1 bit is used */;
13215 uint8_t retransmit_restart /* Only 1 bit is used */;
13216 uint8_t dest_addr[6];
13217 uint16_t mss;
13218 uint32_t ka_timeout;
13219 uint32_t ka_interval;
13220 uint32_t max_rt;
13221 uint32_t flow_label /* Only 20 bits are used */;
13222 uint16_t rcv_indication_size;
13223 uint8_t enable_keepalive /* Only 1 bit is used */;
13224 uint8_t enable_nagle /* Only 1 bit is used */;
13225 uint8_t ttl;
13226 uint8_t hop_limit;
13227 uint8_t tos;
13228 uint8_t traffic_class;
13229 uint8_t ka_max_probe_count;
13230 uint8_t user_priority /* Only 4 bits are used */;
13231 uint16_t reserved2;
13232 uint32_t initial_rcv_wnd;
13233 uint32_t reserved1;
13234};
13235
13236
13237/*
13238 * rx rings pause data for E1h only
13239 */
13240struct ustorm_toe_rx_pause_data_e1h
13241{
13242#if defined(__BIG_ENDIAN)
13243 uint16_t grq_thr_low /* number of remaining grqes under which, we send pause message */;
13244 uint16_t cq_thr_low /* number of remaining cqes under which, we send pause message */;
13245#elif defined(__LITTLE_ENDIAN)
13246 uint16_t cq_thr_low /* number of remaining cqes under which, we send pause message */;
13247 uint16_t grq_thr_low /* number of remaining grqes under which, we send pause message */;
13248#endif
13249#if defined(__BIG_ENDIAN)
13250 uint16_t grq_thr_high /* number of remaining grqes above which, we send un-pause message */;
13251 uint16_t cq_thr_high /* number of remaining cqes above which, we send un-pause message */;
13252#elif defined(__LITTLE_ENDIAN)
13253 uint16_t cq_thr_high /* number of remaining cqes above which, we send un-pause message */;
13254 uint16_t grq_thr_high /* number of remaining grqes above which, we send un-pause message */;
13255#endif
13256};
13257
13258
13259#endif /* ECORE_HSI_H */
13260