1/* 2 * Generic register and struct definitions for the BusLogic 3 * MultiMaster SCSI host adapters. Product specific probe and 4 * attach routines can be found in: 5 * i386/isa/bt_isa.c BT-54X, BT-445 cards 6 * i386/eisa/bt_eisa.c BT-74x, BT-75x cards 7 * pci/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards 8 * 9 * Copyright (c) 1998 Justin T. Gibbs. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification, immediately at the beginning of the file. 18 * 2. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 *
| 1/* 2 * Generic register and struct definitions for the BusLogic 3 * MultiMaster SCSI host adapters. Product specific probe and 4 * attach routines can be found in: 5 * i386/isa/bt_isa.c BT-54X, BT-445 cards 6 * i386/eisa/bt_eisa.c BT-74x, BT-75x cards 7 * pci/bt_pci.c BT-946, BT-948, BT-956, BT-958 cards 8 * 9 * Copyright (c) 1998 Justin T. Gibbs. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions, and the following disclaimer, 17 * without modification, immediately at the beginning of the file. 18 * 2. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 *
|
33 * $Id: btreg.h,v 1.1 1998/09/15 07:32:49 gibbs Exp $
| 33 * $Id: btreg.h,v 1.2 1998/10/30 02:06:44 gibbs Exp $
|
34 */ 35 36#ifndef _BTREG_H_ 37#define _BTREG_H_ 38 39#include "bt.h" 40 41#include <sys/queue.h> 42 43#define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */ 44#define BT_NSEG 32 /* The number of dma segments supported. 45 * BT_NSEG can be maxed out at 8192 entries, 46 * but the kernel will never need to transfer 47 * such a large request. To reduce the 48 * driver's memory consumption, we reduce the 49 * max to 32. 16 would work if all transfers 50 * are paged alined since the kernel will only 51 * generate at most a 64k transfer, but to 52 * handle non-page aligned transfers, you need 53 * 17, so we round to the next power of two 54 * to make allocating SG space easy and 55 * efficient. 56 */ 57 58#define ALL_TARGETS (~0) 59 60/* 61 * Control Register pp. 1-8, 1-9 (Write Only) 62 */ 63#define CONTROL_REG 0x00 64#define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 65#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 66#define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 67#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 68 69/* 70 * Status Register pp. 1-9, 1-10 (Read Only) 71 */ 72#define STATUS_REG 0x00 73#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 74#define DIAG_FAIL 0x40 /* Internal Diags failed */ 75#define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 76#define HA_READY 0x10 /* HA ready for new commands */ 77#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 78#define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 79#define STATUS_REG_RSVD 0x02 80#define CMD_INVALID 0x01 /* Invalid Command detected */ 81 82/* 83 * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 84 */ 85#define COMMAND_REG 0x01 86 87/* 88 * Data in Register p. 1-11 (Read Only) 89 */ 90#define DATAIN_REG 0x01 91 92/* 93 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 94 */ 95#define INTSTAT_REG 0x02 96#define INTR_PENDING 0x80 /* There is a pending INTR */ 97#define INTSTAT_REG_RSVD 0x70 98#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 99#define CMD_COMPLETE 0x04 100#define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 101#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 102 103/* 104 * Definitions for the "undocumented" geometry register 105 */ 106typedef enum { 107 GEOM_NODISK, 108 GEOM_64x32, 109 GEOM_128x32, 110 GEOM_255x32 111} disk_geom_t; 112 113#define GEOMETRY_REG 0x03 114#define DISK0_GEOMETRY 0x03 115#define DISK1_GEOMETRY 0x0c 116#define EXTENDED_TRANSLATION 0x10 117#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 118#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 119 120#define BT_NREGS (4) 121/* 122 * Opcodes for Adapter commands. 123 * pp 1-18 -> 1-20 124 */ 125typedef enum { 126 BOP_TEST_CMDC_INTR = 0x00, 127 BOP_INITIALIZE_24BMBOX = 0x01, 128 BOP_START_MBOX = 0x02, 129 BOP_EXECUTE_BIOS_CMD = 0x03, 130 BOP_INQUIRE_BOARD_ID = 0x04, 131 BOP_ENABLE_OMBR_INT = 0x05, 132 BOP_SET_SEL_TIMOUT = 0x06, 133 BOP_SET_TIME_ON_BUS = 0x07, 134 BOP_SET_TIME_OFF_BUS = 0x08, 135 BOP_SET_BUS_TRANS_RATE = 0x09, 136 BOP_INQUIRE_INST_LDEVS = 0x0A, 137 BOP_INQUIRE_CONFIG = 0x0B, 138 BOP_ENABLE_TARGET_MODE = 0x0C, 139 BOP_INQUIRE_SETUP_INFO = 0x0D, 140 BOP_WRITE_LRAM = 0x1A, 141 BOP_READ_LRAM = 0x1B, 142 BOP_WRITE_CHIP_FIFO = 0x1C, 143 BOP_READ_CHIP_FIFO = 0x1C, 144 BOP_ECHO_DATA_BYTE = 0x1F, 145 BOP_ADAPTER_DIAGNOSTICS = 0x20, 146 BOP_SET_ADAPTER_OPTIONS = 0x21, 147 BOP_INQUIRE_INST_HDEVS = 0x23, 148 BOP_INQUIRE_TARG_DEVS = 0x24, 149 BOP_DISABLE_HAC_INTR = 0x25, 150 BOP_INITIALIZE_32BMBOX = 0x81, 151 BOP_EXECUTE_SCSI_CMD = 0x83, 152 BOP_INQUIRE_FW_VER_3DIG = 0x84, 153 BOP_INQUIRE_FW_VER_4DIG = 0x85, 154 BOP_INQUIRE_PCI_INFO = 0x86, 155 BOP_INQUIRE_MODEL = 0x8B, 156 BOP_TARG_SYNC_INFO = 0x8C, 157 BOP_INQUIRE_ESETUP_INFO = 0x8D, 158 BOP_ENABLE_STRICT_RR = 0x8F, 159 BOP_STORE_LRAM = 0x90, 160 BOP_FETCH_LRAM = 0x91, 161 BOP_SAVE_TO_EEPROM = 0x92, 162 BOP_UPLOAD_AUTO_SCSI = 0x94, 163 BOP_MODIFY_IO_ADDR = 0x95, 164 BOP_SET_CCB_FORMAT = 0x96, 165 BOP_FLASH_ROM_DOWNLOAD = 0x97, 166 BOP_FLASH_WRITE_ENABLE = 0x98, 167 BOP_WRITE_INQ_BUFFER = 0x9A, 168 BOP_READ_INQ_BUFFER = 0x9B, 169 BOP_FLASH_UP_DOWNLOAD = 0xA7, 170 BOP_READ_SCAM_DATA = 0xA8, 171 BOP_WRITE_SCAM_DATA = 0xA9 172} bt_op_t; 173 174/************** Definitions of Multi-byte commands and responses ************/ 175 176typedef struct { 177 u_int8_t num_mboxes; 178 u_int8_t base_addr[3]; 179} init_24b_mbox_params_t; 180 181typedef struct { 182 u_int8_t board_type; 183#define BOARD_TYPE_NON_MCA 0x41 184#define BOARD_TYPE_MCA 0x42 185 u_int8_t cust_features; 186#define FEATURES_STANDARD 0x41 187 u_int8_t firmware_rev_major; 188 u_int8_t firmware_rev_minor; 189} board_id_data_t; 190 191typedef struct { 192 u_int8_t enable; 193} enable_ombr_intr_params_t; 194 195typedef struct { 196 u_int8_t enable; 197 u_int8_t reserved; 198 u_int8_t timeout[2]; /* timeout in milliseconds */ 199} set_selto_parmas_t; 200 201typedef struct { 202 u_int8_t time; /* time in milliseconds (2-15) */ 203} set_timeon_bus_params_t; 204 205typedef struct { 206 u_int8_t time; /* time in milliseconds (2-15) */ 207} set_timeoff_bus_params_t; 208 209typedef struct { 210 u_int8_t rate; 211} set_bus_trasfer_rate_params_t; 212 213typedef struct { 214 u_int8_t targets[8]; 215} installed_ldevs_data_t; 216 217typedef struct { 218 u_int8_t dma_chan; 219#define DMA_CHAN_5 0x20 220#define DMA_CHAN_6 0x40 221#define DMA_CHAN_7 0x80 222 u_int8_t irq; 223#define IRQ_9 0x01 224#define IRQ_10 0x02 225#define IRQ_11 0x04 226#define IRQ_12 0x08 227#define IRQ_14 0x20 228#define IRQ_15 0x40 229 u_int8_t scsi_id; 230} config_data_t; 231 232typedef struct { 233 u_int8_t enable; 234} target_mode_params_t; 235 236typedef struct { 237 u_int8_t offset : 4, 238 period : 3, 239 sync : 1; 240} targ_syncinfo_t; 241 242typedef enum { 243 HAB_ISA = 'A', 244 HAB_MCA = 'B', 245 HAB_EISA = 'C', 246 HAB_NUBUS = 'D', 247 HAB_VESA = 'E', 248 HAB_PCI = 'F' 249} ha_type_t; 250 251typedef struct { 252 u_int8_t initiate_sync : 1, 253 parity_enable : 1, 254 : 6; 255 256 u_int8_t bus_transfer_rate; 257 u_int8_t time_on_bus; 258 u_int8_t time_off_bus; 259 u_int8_t num_mboxes; 260 u_int8_t mbox_base_addr[3]; 261 targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */ 262 u_int8_t low_discinfo; 263 u_int8_t customer_sig; 264 u_int8_t letter_d; 265 u_int8_t ha_type; 266 u_int8_t low_wide_allowed; 267 u_int8_t low_wide_active; 268 targ_syncinfo_t high_syncinfo[8]; 269 u_int8_t high_discinfo; 270 u_int8_t high_wide_allowed; 271 u_int8_t high_wide_active; 272} setup_data_t; 273 274typedef struct { 275 u_int8_t phys_addr[3]; 276} write_adapter_lram_params_t; 277 278typedef struct { 279 u_int8_t phys_addr[3]; 280} read_adapter_lram_params_t; 281 282typedef struct { 283 u_int8_t phys_addr[3]; 284} write_chip_fifo_params_t; 285 286typedef struct { 287 u_int8_t phys_addr[3]; 288} read_chip_fifo_params_t; 289 290typedef struct { 291 u_int8_t length; /* Excludes this member */ 292 u_int8_t low_disc_disable; 293 u_int8_t low_busy_retry_disable; 294 u_int8_t high_disc_disable; 295 u_int8_t high_busy_retry_disable; 296} set_adapter_options_params_t; 297 298typedef struct { 299 u_int8_t targets[8]; 300} installed_hdevs_data_t; 301 302typedef struct { 303 u_int8_t low_devs; 304 u_int8_t high_devs; 305} target_devs_data_t; 306 307typedef struct { 308 u_int8_t enable; 309} enable_hac_interrupt_params_t; 310 311typedef struct { 312 u_int8_t num_boxes; 313 u_int8_t base_addr[4]; 314} init_32b_mbox_params_t; 315 316typedef u_int8_t fw_ver_3dig_data_t; 317 318typedef u_int8_t fw_ver_4dig_data_t; 319 320typedef struct { 321 u_int8_t offset; 322 u_int8_t response_len; 323} fetch_lram_params_t; 324 325#define AUTO_SCSI_BYTE_OFFSET 64 326typedef struct { 327 u_int8_t factory_sig[2]; 328 u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */ 329 u_int8_t model_num[6]; 330 u_int8_t adapter_ioport; 331 u_int8_t floppy_enabled :1, 332 floppy_secondary :1, 333 level_trigger :1, 334 :2, 335 system_ram_area :3; 336 u_int8_t dma_channel :7, 337 dma_autoconf :1; 338 u_int8_t irq_channel :7, 339 irq_autoconf :1; 340 u_int8_t dma_trans_rate; 341 u_int8_t scsi_id; 342 u_int8_t low_termination :1, 343 scsi_parity :1, 344 high_termination :1, 345 req_ack_filter :1, 346 fast_sync :1, 347 bus_reset :1, 348 :1, 349 active_negation :1; 350 u_int8_t bus_on_delay; 351 u_int8_t bus_off_delay; 352 u_int8_t bios_enabled :1, 353 int19h_redirect :1, 354 extended_trans :1, 355 removable_drives :1, 356 :1, 357 morethan2disks :1, 358 interrupt_mode :1, 359 floptical_support:1; 360 u_int8_t low_device_enabled; 361 u_int8_t high_device_enabled; 362 u_int8_t low_wide_permitted; 363 u_int8_t high_wide_permitted; 364 u_int8_t low_fast_permitted; 365 u_int8_t high_fast_permitted; 366 u_int8_t low_sync_permitted; 367 u_int8_t high_sync_permitted; 368 u_int8_t low_disc_permitted; 369 u_int8_t high_disc_permitted; 370 u_int8_t low_send_start_unit; 371 u_int8_t high_send_start_unit; 372 u_int8_t low_ignore_in_bios_scan; 373 u_int8_t high_ignore_in_bios_scan; 374 u_int8_t pci_int_pin :2, 375 host_ioport :2, 376 round_robin :1, 377 vesa_bus_over_33 :1, 378 vesa_burst_write :1, 379 vesa_burst_read :1; 380 u_int8_t low_ultra_permitted; 381 u_int8_t high_ultra_permitted; 382 u_int8_t reserved[5]; 383 u_int8_t auto_scsi_max_lun; 384 u_int8_t :1, 385 scam_dominant :1, 386 scam_enabled :1, 387 scam_level2 :1, 388 :4; 389 u_int8_t int13_extensions :1, 390 :1, 391 cdrom_boot :1, 392 :2, 393 multi_boot :1, 394 :2; 395 u_int8_t boot_target_id :4, 396 boot_channel :4; 397 u_int8_t force_dev_scan :1, 398 :7; 399 u_int8_t low_tagged_lun_independance; 400 u_int8_t high_tagged_lun_independance; 401 u_int8_t low_renegotiate_after_cc; 402 u_int8_t high_renegotiate_after_cc; 403 u_int8_t reserverd2[10]; 404 u_int8_t manufacturing_diagnotic[2]; 405 u_int8_t checksum[2]; 406} auto_scsi_data_t; 407 408struct bt_isa_port { 409 u_int16_t addr; 410 u_int8_t probed;
| 34 */ 35 36#ifndef _BTREG_H_ 37#define _BTREG_H_ 38 39#include "bt.h" 40 41#include <sys/queue.h> 42 43#define BT_MAXTRANSFER_SIZE 0xffffffff /* limited by 32bit counter */ 44#define BT_NSEG 32 /* The number of dma segments supported. 45 * BT_NSEG can be maxed out at 8192 entries, 46 * but the kernel will never need to transfer 47 * such a large request. To reduce the 48 * driver's memory consumption, we reduce the 49 * max to 32. 16 would work if all transfers 50 * are paged alined since the kernel will only 51 * generate at most a 64k transfer, but to 52 * handle non-page aligned transfers, you need 53 * 17, so we round to the next power of two 54 * to make allocating SG space easy and 55 * efficient. 56 */ 57 58#define ALL_TARGETS (~0) 59 60/* 61 * Control Register pp. 1-8, 1-9 (Write Only) 62 */ 63#define CONTROL_REG 0x00 64#define HARD_RESET 0x80 /* Hard Reset - return to POST state */ 65#define SOFT_RESET 0x40 /* Soft Reset - Clears Adapter state */ 66#define RESET_INTR 0x20 /* Reset/Ack Interrupt */ 67#define RESET_SBUS 0x10 /* Drive SCSI bus reset signal */ 68 69/* 70 * Status Register pp. 1-9, 1-10 (Read Only) 71 */ 72#define STATUS_REG 0x00 73#define DIAG_ACTIVE 0x80 /* Performing Internal Diags */ 74#define DIAG_FAIL 0x40 /* Internal Diags failed */ 75#define INIT_REQUIRED 0x20 /* MBOXes need initialization */ 76#define HA_READY 0x10 /* HA ready for new commands */ 77#define CMD_REG_BUSY 0x08 /* HA busy with last cmd byte */ 78#define DATAIN_REG_READY 0x04 /* Data-in Byte available */ 79#define STATUS_REG_RSVD 0x02 80#define CMD_INVALID 0x01 /* Invalid Command detected */ 81 82/* 83 * Command/Parameter Register pp. 1-10, 1-11 (Write Only) 84 */ 85#define COMMAND_REG 0x01 86 87/* 88 * Data in Register p. 1-11 (Read Only) 89 */ 90#define DATAIN_REG 0x01 91 92/* 93 * Interrupt Status Register pp. 1-12 -> 1-14 (Read Only) 94 */ 95#define INTSTAT_REG 0x02 96#define INTR_PENDING 0x80 /* There is a pending INTR */ 97#define INTSTAT_REG_RSVD 0x70 98#define SCSI_BUS_RESET 0x08 /* Bus Reset detected */ 99#define CMD_COMPLETE 0x04 100#define OMB_READY 0x02 /* Outgoin Mailbox Ready */ 101#define IMB_LOADED 0x01 /* Incoming Mailbox loaded */ 102 103/* 104 * Definitions for the "undocumented" geometry register 105 */ 106typedef enum { 107 GEOM_NODISK, 108 GEOM_64x32, 109 GEOM_128x32, 110 GEOM_255x32 111} disk_geom_t; 112 113#define GEOMETRY_REG 0x03 114#define DISK0_GEOMETRY 0x03 115#define DISK1_GEOMETRY 0x0c 116#define EXTENDED_TRANSLATION 0x10 117#define GEOMETRY_DISK0(g_reg) (greg & DISK0_GEOMETRY) 118#define GEOMETRY_DISK1(g_reg) ((greg & DISK1_GEOMETRY) >> 2) 119 120#define BT_NREGS (4) 121/* 122 * Opcodes for Adapter commands. 123 * pp 1-18 -> 1-20 124 */ 125typedef enum { 126 BOP_TEST_CMDC_INTR = 0x00, 127 BOP_INITIALIZE_24BMBOX = 0x01, 128 BOP_START_MBOX = 0x02, 129 BOP_EXECUTE_BIOS_CMD = 0x03, 130 BOP_INQUIRE_BOARD_ID = 0x04, 131 BOP_ENABLE_OMBR_INT = 0x05, 132 BOP_SET_SEL_TIMOUT = 0x06, 133 BOP_SET_TIME_ON_BUS = 0x07, 134 BOP_SET_TIME_OFF_BUS = 0x08, 135 BOP_SET_BUS_TRANS_RATE = 0x09, 136 BOP_INQUIRE_INST_LDEVS = 0x0A, 137 BOP_INQUIRE_CONFIG = 0x0B, 138 BOP_ENABLE_TARGET_MODE = 0x0C, 139 BOP_INQUIRE_SETUP_INFO = 0x0D, 140 BOP_WRITE_LRAM = 0x1A, 141 BOP_READ_LRAM = 0x1B, 142 BOP_WRITE_CHIP_FIFO = 0x1C, 143 BOP_READ_CHIP_FIFO = 0x1C, 144 BOP_ECHO_DATA_BYTE = 0x1F, 145 BOP_ADAPTER_DIAGNOSTICS = 0x20, 146 BOP_SET_ADAPTER_OPTIONS = 0x21, 147 BOP_INQUIRE_INST_HDEVS = 0x23, 148 BOP_INQUIRE_TARG_DEVS = 0x24, 149 BOP_DISABLE_HAC_INTR = 0x25, 150 BOP_INITIALIZE_32BMBOX = 0x81, 151 BOP_EXECUTE_SCSI_CMD = 0x83, 152 BOP_INQUIRE_FW_VER_3DIG = 0x84, 153 BOP_INQUIRE_FW_VER_4DIG = 0x85, 154 BOP_INQUIRE_PCI_INFO = 0x86, 155 BOP_INQUIRE_MODEL = 0x8B, 156 BOP_TARG_SYNC_INFO = 0x8C, 157 BOP_INQUIRE_ESETUP_INFO = 0x8D, 158 BOP_ENABLE_STRICT_RR = 0x8F, 159 BOP_STORE_LRAM = 0x90, 160 BOP_FETCH_LRAM = 0x91, 161 BOP_SAVE_TO_EEPROM = 0x92, 162 BOP_UPLOAD_AUTO_SCSI = 0x94, 163 BOP_MODIFY_IO_ADDR = 0x95, 164 BOP_SET_CCB_FORMAT = 0x96, 165 BOP_FLASH_ROM_DOWNLOAD = 0x97, 166 BOP_FLASH_WRITE_ENABLE = 0x98, 167 BOP_WRITE_INQ_BUFFER = 0x9A, 168 BOP_READ_INQ_BUFFER = 0x9B, 169 BOP_FLASH_UP_DOWNLOAD = 0xA7, 170 BOP_READ_SCAM_DATA = 0xA8, 171 BOP_WRITE_SCAM_DATA = 0xA9 172} bt_op_t; 173 174/************** Definitions of Multi-byte commands and responses ************/ 175 176typedef struct { 177 u_int8_t num_mboxes; 178 u_int8_t base_addr[3]; 179} init_24b_mbox_params_t; 180 181typedef struct { 182 u_int8_t board_type; 183#define BOARD_TYPE_NON_MCA 0x41 184#define BOARD_TYPE_MCA 0x42 185 u_int8_t cust_features; 186#define FEATURES_STANDARD 0x41 187 u_int8_t firmware_rev_major; 188 u_int8_t firmware_rev_minor; 189} board_id_data_t; 190 191typedef struct { 192 u_int8_t enable; 193} enable_ombr_intr_params_t; 194 195typedef struct { 196 u_int8_t enable; 197 u_int8_t reserved; 198 u_int8_t timeout[2]; /* timeout in milliseconds */ 199} set_selto_parmas_t; 200 201typedef struct { 202 u_int8_t time; /* time in milliseconds (2-15) */ 203} set_timeon_bus_params_t; 204 205typedef struct { 206 u_int8_t time; /* time in milliseconds (2-15) */ 207} set_timeoff_bus_params_t; 208 209typedef struct { 210 u_int8_t rate; 211} set_bus_trasfer_rate_params_t; 212 213typedef struct { 214 u_int8_t targets[8]; 215} installed_ldevs_data_t; 216 217typedef struct { 218 u_int8_t dma_chan; 219#define DMA_CHAN_5 0x20 220#define DMA_CHAN_6 0x40 221#define DMA_CHAN_7 0x80 222 u_int8_t irq; 223#define IRQ_9 0x01 224#define IRQ_10 0x02 225#define IRQ_11 0x04 226#define IRQ_12 0x08 227#define IRQ_14 0x20 228#define IRQ_15 0x40 229 u_int8_t scsi_id; 230} config_data_t; 231 232typedef struct { 233 u_int8_t enable; 234} target_mode_params_t; 235 236typedef struct { 237 u_int8_t offset : 4, 238 period : 3, 239 sync : 1; 240} targ_syncinfo_t; 241 242typedef enum { 243 HAB_ISA = 'A', 244 HAB_MCA = 'B', 245 HAB_EISA = 'C', 246 HAB_NUBUS = 'D', 247 HAB_VESA = 'E', 248 HAB_PCI = 'F' 249} ha_type_t; 250 251typedef struct { 252 u_int8_t initiate_sync : 1, 253 parity_enable : 1, 254 : 6; 255 256 u_int8_t bus_transfer_rate; 257 u_int8_t time_on_bus; 258 u_int8_t time_off_bus; 259 u_int8_t num_mboxes; 260 u_int8_t mbox_base_addr[3]; 261 targ_syncinfo_t low_syncinfo[8]; /* For fast and ultra, use 8C */ 262 u_int8_t low_discinfo; 263 u_int8_t customer_sig; 264 u_int8_t letter_d; 265 u_int8_t ha_type; 266 u_int8_t low_wide_allowed; 267 u_int8_t low_wide_active; 268 targ_syncinfo_t high_syncinfo[8]; 269 u_int8_t high_discinfo; 270 u_int8_t high_wide_allowed; 271 u_int8_t high_wide_active; 272} setup_data_t; 273 274typedef struct { 275 u_int8_t phys_addr[3]; 276} write_adapter_lram_params_t; 277 278typedef struct { 279 u_int8_t phys_addr[3]; 280} read_adapter_lram_params_t; 281 282typedef struct { 283 u_int8_t phys_addr[3]; 284} write_chip_fifo_params_t; 285 286typedef struct { 287 u_int8_t phys_addr[3]; 288} read_chip_fifo_params_t; 289 290typedef struct { 291 u_int8_t length; /* Excludes this member */ 292 u_int8_t low_disc_disable; 293 u_int8_t low_busy_retry_disable; 294 u_int8_t high_disc_disable; 295 u_int8_t high_busy_retry_disable; 296} set_adapter_options_params_t; 297 298typedef struct { 299 u_int8_t targets[8]; 300} installed_hdevs_data_t; 301 302typedef struct { 303 u_int8_t low_devs; 304 u_int8_t high_devs; 305} target_devs_data_t; 306 307typedef struct { 308 u_int8_t enable; 309} enable_hac_interrupt_params_t; 310 311typedef struct { 312 u_int8_t num_boxes; 313 u_int8_t base_addr[4]; 314} init_32b_mbox_params_t; 315 316typedef u_int8_t fw_ver_3dig_data_t; 317 318typedef u_int8_t fw_ver_4dig_data_t; 319 320typedef struct { 321 u_int8_t offset; 322 u_int8_t response_len; 323} fetch_lram_params_t; 324 325#define AUTO_SCSI_BYTE_OFFSET 64 326typedef struct { 327 u_int8_t factory_sig[2]; 328 u_int8_t auto_scsi_data_size; /* 2 -> 64 bytes */ 329 u_int8_t model_num[6]; 330 u_int8_t adapter_ioport; 331 u_int8_t floppy_enabled :1, 332 floppy_secondary :1, 333 level_trigger :1, 334 :2, 335 system_ram_area :3; 336 u_int8_t dma_channel :7, 337 dma_autoconf :1; 338 u_int8_t irq_channel :7, 339 irq_autoconf :1; 340 u_int8_t dma_trans_rate; 341 u_int8_t scsi_id; 342 u_int8_t low_termination :1, 343 scsi_parity :1, 344 high_termination :1, 345 req_ack_filter :1, 346 fast_sync :1, 347 bus_reset :1, 348 :1, 349 active_negation :1; 350 u_int8_t bus_on_delay; 351 u_int8_t bus_off_delay; 352 u_int8_t bios_enabled :1, 353 int19h_redirect :1, 354 extended_trans :1, 355 removable_drives :1, 356 :1, 357 morethan2disks :1, 358 interrupt_mode :1, 359 floptical_support:1; 360 u_int8_t low_device_enabled; 361 u_int8_t high_device_enabled; 362 u_int8_t low_wide_permitted; 363 u_int8_t high_wide_permitted; 364 u_int8_t low_fast_permitted; 365 u_int8_t high_fast_permitted; 366 u_int8_t low_sync_permitted; 367 u_int8_t high_sync_permitted; 368 u_int8_t low_disc_permitted; 369 u_int8_t high_disc_permitted; 370 u_int8_t low_send_start_unit; 371 u_int8_t high_send_start_unit; 372 u_int8_t low_ignore_in_bios_scan; 373 u_int8_t high_ignore_in_bios_scan; 374 u_int8_t pci_int_pin :2, 375 host_ioport :2, 376 round_robin :1, 377 vesa_bus_over_33 :1, 378 vesa_burst_write :1, 379 vesa_burst_read :1; 380 u_int8_t low_ultra_permitted; 381 u_int8_t high_ultra_permitted; 382 u_int8_t reserved[5]; 383 u_int8_t auto_scsi_max_lun; 384 u_int8_t :1, 385 scam_dominant :1, 386 scam_enabled :1, 387 scam_level2 :1, 388 :4; 389 u_int8_t int13_extensions :1, 390 :1, 391 cdrom_boot :1, 392 :2, 393 multi_boot :1, 394 :2; 395 u_int8_t boot_target_id :4, 396 boot_channel :4; 397 u_int8_t force_dev_scan :1, 398 :7; 399 u_int8_t low_tagged_lun_independance; 400 u_int8_t high_tagged_lun_independance; 401 u_int8_t low_renegotiate_after_cc; 402 u_int8_t high_renegotiate_after_cc; 403 u_int8_t reserverd2[10]; 404 u_int8_t manufacturing_diagnotic[2]; 405 u_int8_t checksum[2]; 406} auto_scsi_data_t; 407 408struct bt_isa_port { 409 u_int16_t addr; 410 u_int8_t probed;
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| 411 u_int8_t bio;
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411}; 412 413extern struct bt_isa_port bt_isa_ports[]; 414 415#define BT_NUM_ISAPORTS 6 416 417typedef enum { 418 BIO_330 = 0, 419 BIO_334 = 1, 420 BIO_230 = 2, 421 BIO_234 = 3, 422 BIO_130 = 4, 423 BIO_134 = 5, 424 BIO_DISABLED = 6, 425 BIO_DISABLED2 = 7 426} isa_compat_io_t; 427 428typedef struct { 429 u_int8_t io_port; 430 u_int8_t irq_num; 431 u_int8_t low_byte_term :1, 432 high_byte_term :1, 433 :2, 434 jp1_status :1, 435 jp2_status :1, 436 jp3_status :1, 437 :1; 438 u_int8_t reserved; 439} pci_info_data_t; 440 441typedef struct { 442 u_int8_t ascii_model[5]; /* Fifth byte is always 0 */ 443} ha_model_data_t; 444 445typedef struct { 446 u_int8_t sync_rate[16]; /* Sync in 10ns units */ 447} target_sync_info_data_t; 448 449typedef struct { 450 u_int8_t bus_type; 451 u_int8_t bios_addr; 452 u_int16_t max_sg; 453 u_int8_t num_mboxes; 454 u_int8_t mbox_base[4]; 455 u_int8_t :2, 456 sync_neg10MB :1, 457 floppy_disable :1, 458 floppy_secondary_port :1, 459 burst_mode_enabled :1, 460 level_trigger_ints :1, 461 :1; 462 u_int8_t fw_ver_bytes_2_to_4[3]; 463 u_int8_t wide_bus :1, 464 diff_bus :1, 465 scam_capable :1, 466 ultra_scsi :1, 467 auto_term :1, 468 :3; 469} esetup_info_data_t; 470 471typedef struct { 472 u_int32_t len; 473 u_int32_t addr; 474} bt_sg_t; 475 476/********************** Mail Box definitions *******************************/ 477 478typedef enum { 479 BMBO_FREE = 0x0, /* MBO intry is free */ 480 BMBO_START = 0x1, /* MBO activate entry */ 481 BMBO_ABORT = 0x2 /* MBO abort entry */ 482} bt_mbo_action_code_t; 483 484typedef struct bt_mbox_out { 485 u_int32_t ccb_addr; 486 u_int8_t reserved[3]; 487 u_int8_t action_code; 488} bt_mbox_out_t; 489 490typedef enum { 491 BMBI_FREE = 0x0, /* MBI entry is free */ 492 BMBI_OK = 0x1, /* completed without error */ 493 BMBI_ABORT = 0x2, /* aborted ccb */ 494 BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 495 BMBI_ERROR = 0x4 /* Completed with error */ 496} bt_mbi_comp_code_t; 497 498typedef struct bt_mbox_in { 499 u_int32_t ccb_addr; 500 u_int8_t btstat; 501 u_int8_t sdstat; 502 u_int8_t reserved; 503 u_int8_t comp_code; 504} bt_mbox_in_t; 505 506/****************** Hardware CCB definition *********************************/ 507typedef enum { 508 INITIATOR_CCB = 0x00, 509 INITIATOR_SG_CCB = 0x02, 510 INITIATOR_CCB_WRESID = 0x03, 511 INITIATOR_SG_CCB_WRESID = 0x04, 512 INITIATOR_BUS_DEV_RESET = 0x81 513} bt_ccb_opcode_t; 514 515typedef enum { 516 BTSTAT_NOERROR = 0x00, 517 BTSTAT_LINKED_CMD_COMPLETE = 0x0A, 518 BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B, 519 BTSTAT_DATAUNDERUN_ERROR = 0x0C, 520 BTSTAT_SELTIMEOUT = 0x11, 521 BTSTAT_DATARUN_ERROR = 0x12, 522 BTSTAT_UNEXPECTED_BUSFREE = 0x13, 523 BTSTAT_INVALID_PHASE = 0x14, 524 BTSTAT_INVALID_ACTION_CODE = 0x15, 525 BTSTAT_INVALID_OPCODE = 0x16, 526 BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 527 BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 528 BTSTAT_AUTOSENSE_FAILED = 0x1B, 529 BTSTAT_TAGGED_MSG_REJECTED = 0x1C, 530 BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D, 531 BTSTAT_HARDWARE_FAILURE = 0x20, 532 BTSTAT_TARGET_IGNORED_ATN = 0x21, 533 BTSTAT_HA_SCSI_BUS_RESET = 0x22, 534 BTSTAT_OTHER_SCSI_BUS_RESET = 0x23, 535 BTSTAT_INVALID_RECONNECT = 0x24, 536 BTSTAT_HA_BDR = 0x25, 537 BTSTAT_ABORT_QUEUE_GENERATED = 0x26, 538 BTSTAT_HA_SOFTWARE_ERROR = 0x27, 539 BTSTAT_HA_WATCHDOG_ERROR = 0x28, 540 BTSTAT_SCSI_PERROR_DETECTED = 0x30 541} btstat_t; 542 543struct bt_hccb { 544 u_int8_t opcode; 545 u_int8_t :3, 546 datain :1, 547 dataout :1, 548 wide_tag_enable :1, /* Wide Lun CCB format */ 549 wide_tag_type :2; /* Wide Lun CCB format */ 550 u_int8_t cmd_len; 551 u_int8_t sense_len;
| 412}; 413 414extern struct bt_isa_port bt_isa_ports[]; 415 416#define BT_NUM_ISAPORTS 6 417 418typedef enum { 419 BIO_330 = 0, 420 BIO_334 = 1, 421 BIO_230 = 2, 422 BIO_234 = 3, 423 BIO_130 = 4, 424 BIO_134 = 5, 425 BIO_DISABLED = 6, 426 BIO_DISABLED2 = 7 427} isa_compat_io_t; 428 429typedef struct { 430 u_int8_t io_port; 431 u_int8_t irq_num; 432 u_int8_t low_byte_term :1, 433 high_byte_term :1, 434 :2, 435 jp1_status :1, 436 jp2_status :1, 437 jp3_status :1, 438 :1; 439 u_int8_t reserved; 440} pci_info_data_t; 441 442typedef struct { 443 u_int8_t ascii_model[5]; /* Fifth byte is always 0 */ 444} ha_model_data_t; 445 446typedef struct { 447 u_int8_t sync_rate[16]; /* Sync in 10ns units */ 448} target_sync_info_data_t; 449 450typedef struct { 451 u_int8_t bus_type; 452 u_int8_t bios_addr; 453 u_int16_t max_sg; 454 u_int8_t num_mboxes; 455 u_int8_t mbox_base[4]; 456 u_int8_t :2, 457 sync_neg10MB :1, 458 floppy_disable :1, 459 floppy_secondary_port :1, 460 burst_mode_enabled :1, 461 level_trigger_ints :1, 462 :1; 463 u_int8_t fw_ver_bytes_2_to_4[3]; 464 u_int8_t wide_bus :1, 465 diff_bus :1, 466 scam_capable :1, 467 ultra_scsi :1, 468 auto_term :1, 469 :3; 470} esetup_info_data_t; 471 472typedef struct { 473 u_int32_t len; 474 u_int32_t addr; 475} bt_sg_t; 476 477/********************** Mail Box definitions *******************************/ 478 479typedef enum { 480 BMBO_FREE = 0x0, /* MBO intry is free */ 481 BMBO_START = 0x1, /* MBO activate entry */ 482 BMBO_ABORT = 0x2 /* MBO abort entry */ 483} bt_mbo_action_code_t; 484 485typedef struct bt_mbox_out { 486 u_int32_t ccb_addr; 487 u_int8_t reserved[3]; 488 u_int8_t action_code; 489} bt_mbox_out_t; 490 491typedef enum { 492 BMBI_FREE = 0x0, /* MBI entry is free */ 493 BMBI_OK = 0x1, /* completed without error */ 494 BMBI_ABORT = 0x2, /* aborted ccb */ 495 BMBI_NOT_FOUND = 0x3, /* Tried to abort invalid CCB */ 496 BMBI_ERROR = 0x4 /* Completed with error */ 497} bt_mbi_comp_code_t; 498 499typedef struct bt_mbox_in { 500 u_int32_t ccb_addr; 501 u_int8_t btstat; 502 u_int8_t sdstat; 503 u_int8_t reserved; 504 u_int8_t comp_code; 505} bt_mbox_in_t; 506 507/****************** Hardware CCB definition *********************************/ 508typedef enum { 509 INITIATOR_CCB = 0x00, 510 INITIATOR_SG_CCB = 0x02, 511 INITIATOR_CCB_WRESID = 0x03, 512 INITIATOR_SG_CCB_WRESID = 0x04, 513 INITIATOR_BUS_DEV_RESET = 0x81 514} bt_ccb_opcode_t; 515 516typedef enum { 517 BTSTAT_NOERROR = 0x00, 518 BTSTAT_LINKED_CMD_COMPLETE = 0x0A, 519 BTSTAT_LINKED_CMD_FLAG_COMPLETE = 0x0B, 520 BTSTAT_DATAUNDERUN_ERROR = 0x0C, 521 BTSTAT_SELTIMEOUT = 0x11, 522 BTSTAT_DATARUN_ERROR = 0x12, 523 BTSTAT_UNEXPECTED_BUSFREE = 0x13, 524 BTSTAT_INVALID_PHASE = 0x14, 525 BTSTAT_INVALID_ACTION_CODE = 0x15, 526 BTSTAT_INVALID_OPCODE = 0x16, 527 BTSTAT_LINKED_CCB_LUN_MISMATCH = 0x17, 528 BTSTAT_INVALID_CCB_OR_SG_PARAM = 0x1A, 529 BTSTAT_AUTOSENSE_FAILED = 0x1B, 530 BTSTAT_TAGGED_MSG_REJECTED = 0x1C, 531 BTSTAT_UNSUPPORTED_MSG_RECEIVED = 0x1D, 532 BTSTAT_HARDWARE_FAILURE = 0x20, 533 BTSTAT_TARGET_IGNORED_ATN = 0x21, 534 BTSTAT_HA_SCSI_BUS_RESET = 0x22, 535 BTSTAT_OTHER_SCSI_BUS_RESET = 0x23, 536 BTSTAT_INVALID_RECONNECT = 0x24, 537 BTSTAT_HA_BDR = 0x25, 538 BTSTAT_ABORT_QUEUE_GENERATED = 0x26, 539 BTSTAT_HA_SOFTWARE_ERROR = 0x27, 540 BTSTAT_HA_WATCHDOG_ERROR = 0x28, 541 BTSTAT_SCSI_PERROR_DETECTED = 0x30 542} btstat_t; 543 544struct bt_hccb { 545 u_int8_t opcode; 546 u_int8_t :3, 547 datain :1, 548 dataout :1, 549 wide_tag_enable :1, /* Wide Lun CCB format */ 550 wide_tag_type :2; /* Wide Lun CCB format */ 551 u_int8_t cmd_len; 552 u_int8_t sense_len;
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552 u_int32_t data_len;
| 553 int32_t data_len; /* residuals can be negative */
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553 u_int32_t data_addr; 554 u_int8_t reserved[2]; 555 u_int8_t btstat; 556 u_int8_t sdstat; 557 u_int8_t target_id; 558 u_int8_t target_lun :5, 559 tag_enable :1, 560 tag_type :2; 561 u_int8_t scsi_cdb[12]; 562 u_int8_t reserved2[6]; 563 u_int32_t sense_addr; 564}; 565 566typedef enum { 567 BCCB_FREE = 0x0, 568 BCCB_ACTIVE = 0x1, 569 BCCB_DEVICE_RESET = 0x2, 570 BCCB_RELEASE_SIMQ = 0x4 571} bccb_flags_t; 572 573struct bt_ccb { 574 struct bt_hccb hccb; 575 SLIST_ENTRY(bt_ccb) links; 576 u_int32_t flags; 577 union ccb *ccb; 578 bus_dmamap_t dmamap; 579 bt_sg_t *sg_list; 580 u_int32_t sg_list_phys; 581}; 582 583struct sg_map_node { 584 bus_dmamap_t sg_dmamap; 585 bus_addr_t sg_physaddr; 586 bt_sg_t* sg_vaddr; 587 SLIST_ENTRY(sg_map_node) links; 588}; 589 590struct bt_softc { 591 bus_space_tag_t tag; 592 bus_space_handle_t bsh; 593 struct cam_sim *sim; 594 struct cam_path *path; 595 bt_mbox_out_t *cur_outbox; 596 bt_mbox_in_t *cur_inbox; 597 bt_mbox_out_t *last_outbox; 598 bt_mbox_in_t *last_inbox; 599 struct bt_ccb *bt_ccb_array; 600 SLIST_HEAD(,bt_ccb) free_bt_ccbs; 601 LIST_HEAD(,ccb_hdr) pending_ccbs;
| 554 u_int32_t data_addr; 555 u_int8_t reserved[2]; 556 u_int8_t btstat; 557 u_int8_t sdstat; 558 u_int8_t target_id; 559 u_int8_t target_lun :5, 560 tag_enable :1, 561 tag_type :2; 562 u_int8_t scsi_cdb[12]; 563 u_int8_t reserved2[6]; 564 u_int32_t sense_addr; 565}; 566 567typedef enum { 568 BCCB_FREE = 0x0, 569 BCCB_ACTIVE = 0x1, 570 BCCB_DEVICE_RESET = 0x2, 571 BCCB_RELEASE_SIMQ = 0x4 572} bccb_flags_t; 573 574struct bt_ccb { 575 struct bt_hccb hccb; 576 SLIST_ENTRY(bt_ccb) links; 577 u_int32_t flags; 578 union ccb *ccb; 579 bus_dmamap_t dmamap; 580 bt_sg_t *sg_list; 581 u_int32_t sg_list_phys; 582}; 583 584struct sg_map_node { 585 bus_dmamap_t sg_dmamap; 586 bus_addr_t sg_physaddr; 587 bt_sg_t* sg_vaddr; 588 SLIST_ENTRY(sg_map_node) links; 589}; 590 591struct bt_softc { 592 bus_space_tag_t tag; 593 bus_space_handle_t bsh; 594 struct cam_sim *sim; 595 struct cam_path *path; 596 bt_mbox_out_t *cur_outbox; 597 bt_mbox_in_t *cur_inbox; 598 bt_mbox_out_t *last_outbox; 599 bt_mbox_in_t *last_inbox; 600 struct bt_ccb *bt_ccb_array; 601 SLIST_HEAD(,bt_ccb) free_bt_ccbs; 602 LIST_HEAD(,ccb_hdr) pending_ccbs;
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| 603 u_int active_ccbs;
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602 u_int32_t bt_ccb_physbase; 603 bt_mbox_in_t *in_boxes; 604 bt_mbox_out_t *out_boxes; 605 struct scsi_sense_data *sense_buffers; 606 u_int32_t sense_buffers_physbase; 607 struct bt_ccb *recovery_bccb; 608 u_int num_boxes; 609 bus_dma_tag_t parent_dmat; /* 610 * All dmat's derive from 611 * the dmat defined by our 612 * bus. 613 */ 614 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 615 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 616 bus_dmamap_t mailbox_dmamap; 617 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 618 bus_dmamap_t ccb_dmamap; 619 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 620 bus_dma_tag_t sense_dmat; /* dmat for our sg maps */ 621 bus_dmamap_t sense_dmamap; 622 SLIST_HEAD(, sg_map_node) sg_maps; 623 bus_addr_t mailbox_physbase; 624 u_int num_ccbs; /* Number of CCBs malloc'd */ 625 u_int max_ccbs; /* Maximum allocatable CCBs */ 626 u_int max_sg; 627 u_int unit; 628 u_int scsi_id; 629 u_int32_t extended_trans :1, 630 wide_bus :1, 631 diff_bus :1, 632 ultra_scsi :1, 633 extended_lun :1, 634 strict_rr :1, 635 tag_capable :1, 636 wide_lun_ccb :1, 637 resource_shortage:1, 638 :23; 639 u_int16_t tags_permitted; 640 u_int16_t disc_permitted; 641 u_int16_t sync_permitted; 642 u_int16_t fast_permitted; 643 u_int16_t ultra_permitted; 644 u_int16_t wide_permitted; 645 u_int8_t init_level; 646 volatile u_int8_t command_cmp; 647 volatile u_int8_t latched_status; 648 u_int32_t bios_addr; 649 char firmware_ver[6]; 650 char model[5]; 651}; 652 653extern struct bt_softc *bt_softcs[]; /* XXX Config should handle this */ 654extern u_long bt_unit; 655 656#define BT_TEMP_UNIT 0xFF /* Unit for probes */ 657struct bt_softc* bt_alloc(int unit, bus_space_tag_t tag, 658 bus_space_handle_t bsh); 659void bt_free(struct bt_softc *bt); 660int bt_probe(struct bt_softc *bt); 661int bt_fetch_adapter_info(struct bt_softc *bt); 662int bt_init(struct bt_softc *bt); 663int bt_attach(struct bt_softc *bt); 664void bt_intr(void *arg); 665char * bt_name(struct bt_softc *bt); 666int bt_check_probed_iop(u_int ioport);
| 604 u_int32_t bt_ccb_physbase; 605 bt_mbox_in_t *in_boxes; 606 bt_mbox_out_t *out_boxes; 607 struct scsi_sense_data *sense_buffers; 608 u_int32_t sense_buffers_physbase; 609 struct bt_ccb *recovery_bccb; 610 u_int num_boxes; 611 bus_dma_tag_t parent_dmat; /* 612 * All dmat's derive from 613 * the dmat defined by our 614 * bus. 615 */ 616 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 617 bus_dma_tag_t mailbox_dmat; /* dmat for our mailboxes */ 618 bus_dmamap_t mailbox_dmamap; 619 bus_dma_tag_t ccb_dmat; /* dmat for our ccb array */ 620 bus_dmamap_t ccb_dmamap; 621 bus_dma_tag_t sg_dmat; /* dmat for our sg maps */ 622 bus_dma_tag_t sense_dmat; /* dmat for our sg maps */ 623 bus_dmamap_t sense_dmamap; 624 SLIST_HEAD(, sg_map_node) sg_maps; 625 bus_addr_t mailbox_physbase; 626 u_int num_ccbs; /* Number of CCBs malloc'd */ 627 u_int max_ccbs; /* Maximum allocatable CCBs */ 628 u_int max_sg; 629 u_int unit; 630 u_int scsi_id; 631 u_int32_t extended_trans :1, 632 wide_bus :1, 633 diff_bus :1, 634 ultra_scsi :1, 635 extended_lun :1, 636 strict_rr :1, 637 tag_capable :1, 638 wide_lun_ccb :1, 639 resource_shortage:1, 640 :23; 641 u_int16_t tags_permitted; 642 u_int16_t disc_permitted; 643 u_int16_t sync_permitted; 644 u_int16_t fast_permitted; 645 u_int16_t ultra_permitted; 646 u_int16_t wide_permitted; 647 u_int8_t init_level; 648 volatile u_int8_t command_cmp; 649 volatile u_int8_t latched_status; 650 u_int32_t bios_addr; 651 char firmware_ver[6]; 652 char model[5]; 653}; 654 655extern struct bt_softc *bt_softcs[]; /* XXX Config should handle this */ 656extern u_long bt_unit; 657 658#define BT_TEMP_UNIT 0xFF /* Unit for probes */ 659struct bt_softc* bt_alloc(int unit, bus_space_tag_t tag, 660 bus_space_handle_t bsh); 661void bt_free(struct bt_softc *bt); 662int bt_probe(struct bt_softc *bt); 663int bt_fetch_adapter_info(struct bt_softc *bt); 664int bt_init(struct bt_softc *bt); 665int bt_attach(struct bt_softc *bt); 666void bt_intr(void *arg); 667char * bt_name(struct bt_softc *bt); 668int bt_check_probed_iop(u_int ioport);
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667u_int bt_fetch_isa_iop(isa_compat_io_t port);
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668void bt_mark_probed_bio(isa_compat_io_t port); 669void bt_mark_probed_iop(u_int ioport);
| 669void bt_mark_probed_bio(isa_compat_io_t port); 670void bt_mark_probed_iop(u_int ioport);
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| 671void bt_find_probe_range(int ioport, 672 int *port_index, 673 int *max_port_index);
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670
| 674
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| 675int bt_iop_from_bio(isa_compat_io_t bio_index); 676
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671#define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */ 672int bt_cmd(struct bt_softc *bt, bt_op_t opcode, 673 u_int8_t *params, u_int param_len, 674 u_int8_t *reply_data, u_int reply_len, 675 u_int cmd_timeout); 676 677#define bt_inb(bt, port) \ 678 bus_space_read_1((bt)->tag, (bt)->bsh, port) 679 680#define bt_outb(bt, port, value) \ 681 bus_space_write_1((bt)->tag, (bt)->bsh, port, value) 682 683#endif /* _BT_H_ */
| 677#define DEFAULT_CMD_TIMEOUT 10000 /* 1 sec */ 678int bt_cmd(struct bt_softc *bt, bt_op_t opcode, 679 u_int8_t *params, u_int param_len, 680 u_int8_t *reply_data, u_int reply_len, 681 u_int cmd_timeout); 682 683#define bt_inb(bt, port) \ 684 bus_space_read_1((bt)->tag, (bt)->bsh, port) 685 686#define bt_outb(bt, port, value) \ 687 bus_space_write_1((bt)->tag, (bt)->bsh, port, value) 688 689#endif /* _BT_H_ */
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