| if_bgereg.h (226867) | if_bgereg.h (226871) |
|---|---|
| 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * | 1/*- 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: --- 16 unchanged lines hidden (view full) --- 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * |
| 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226867 2011-10-27 22:10:52Z yongari $ | 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226871 2011-10-28 01:04:40Z yongari $ |
| 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 211 unchanged lines hidden (view full) --- 253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259 260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) | 34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and --- 211 unchanged lines hidden (view full) --- 253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259 260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) |
| 261#if BYTE_ORDER == LITTLE_ENDIAN 262#define BGE_DMA_SWAP_OPTIONS \ 263 BGE_MODECTL_WORDSWAP_NONFRAME| \ 264 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 265#else 266#define BGE_DMA_SWAP_OPTIONS \ 267 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \ 268 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA 269#endif | |
| 270 271#define BGE_INIT \ 272 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 273 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 274 275#define BGE_CHIPID_TIGON_I 0x4000 276#define BGE_CHIPID_TIGON_II 0x6000 277#define BGE_CHIPID_BCM5700_A0 0x7000 --- 56 unchanged lines hidden (view full) --- 334#define BGE_CHIPID_BCM5906_A0 0xc000 335#define BGE_CHIPID_BCM5906_A1 0xc001 336#define BGE_CHIPID_BCM5906_A2 0xc002 337#define BGE_CHIPID_BCM57780_A0 0x57780000 338#define BGE_CHIPID_BCM57780_A1 0x57780001 339#define BGE_CHIPID_BCM5717_A0 0x05717000 340#define BGE_CHIPID_BCM5717_B0 0x05717100 341#define BGE_CHIPID_BCM5719_A0 0x05719000 | 261 262#define BGE_INIT \ 263 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \ 264 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS) 265 266#define BGE_CHIPID_TIGON_I 0x4000 267#define BGE_CHIPID_TIGON_II 0x6000 268#define BGE_CHIPID_BCM5700_A0 0x7000 --- 56 unchanged lines hidden (view full) --- 325#define BGE_CHIPID_BCM5906_A0 0xc000 326#define BGE_CHIPID_BCM5906_A1 0xc001 327#define BGE_CHIPID_BCM5906_A2 0xc002 328#define BGE_CHIPID_BCM57780_A0 0x57780000 329#define BGE_CHIPID_BCM57780_A1 0x57780001 330#define BGE_CHIPID_BCM5717_A0 0x05717000 331#define BGE_CHIPID_BCM5717_B0 0x05717100 332#define BGE_CHIPID_BCM5719_A0 0x05719000 |
| 333#define BGE_CHIPID_BCM5720_A0 0x05720000 |
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| 342#define BGE_CHIPID_BCM57765_A0 0x57785000 343#define BGE_CHIPID_BCM57765_B0 0x57785100 344 345/* shorthand one */ 346#define BGE_ASICREV(x) ((x) >> 12) 347#define BGE_ASICREV_BCM5701 0x00 348#define BGE_ASICREV_BCM5703 0x01 349#define BGE_ASICREV_BCM5704 0x02 --- 8 unchanged lines hidden (view full) --- 358#define BGE_ASICREV_BCM5754 0x0b 359#define BGE_ASICREV_BCM5787 0x0b 360#define BGE_ASICREV_BCM5906 0x0c 361/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 362#define BGE_ASICREV_USE_PRODID_REG 0x0f 363/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 364#define BGE_ASICREV_BCM5717 0x5717 365#define BGE_ASICREV_BCM5719 0x5719 | 334#define BGE_CHIPID_BCM57765_A0 0x57785000 335#define BGE_CHIPID_BCM57765_B0 0x57785100 336 337/* shorthand one */ 338#define BGE_ASICREV(x) ((x) >> 12) 339#define BGE_ASICREV_BCM5701 0x00 340#define BGE_ASICREV_BCM5703 0x01 341#define BGE_ASICREV_BCM5704 0x02 --- 8 unchanged lines hidden (view full) --- 350#define BGE_ASICREV_BCM5754 0x0b 351#define BGE_ASICREV_BCM5787 0x0b 352#define BGE_ASICREV_BCM5906 0x0c 353/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */ 354#define BGE_ASICREV_USE_PRODID_REG 0x0f 355/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */ 356#define BGE_ASICREV_BCM5717 0x5717 357#define BGE_ASICREV_BCM5719 0x5719 |
| 358#define BGE_ASICREV_BCM5720 0x5720 |
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| 366#define BGE_ASICREV_BCM5761 0x5761 367#define BGE_ASICREV_BCM5784 0x5784 368#define BGE_ASICREV_BCM5785 0x5785 369#define BGE_ASICREV_BCM57765 0x57785 370#define BGE_ASICREV_BCM57780 0x57780 371 372/* chip revisions */ 373#define BGE_CHIPREV(x) ((x) >> 8) --- 428 unchanged lines hidden (view full) --- 802 803/* Transmit MAC mode register */ 804#define BGE_TXMODE_RESET 0x00000001 805#define BGE_TXMODE_ENABLE 0x00000002 806#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 807#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 808#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 809#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 | 359#define BGE_ASICREV_BCM5761 0x5761 360#define BGE_ASICREV_BCM5784 0x5784 361#define BGE_ASICREV_BCM5785 0x5785 362#define BGE_ASICREV_BCM57765 0x57785 363#define BGE_ASICREV_BCM57780 0x57780 364 365/* chip revisions */ 366#define BGE_CHIPREV(x) ((x) >> 8) --- 428 unchanged lines hidden (view full) --- 795 796/* Transmit MAC mode register */ 797#define BGE_TXMODE_RESET 0x00000001 798#define BGE_TXMODE_ENABLE 0x00000002 799#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 800#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 801#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 802#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 |
| 803#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 804#define BGE_TXMODE_CNT_DN_MODE 0x00800000 |
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| 810 811/* Transmit MAC status register */ 812#define BGE_TXSTAT_RX_XOFFED 0x00000001 813#define BGE_TXSTAT_SENT_XOFF 0x00000002 814#define BGE_TXSTAT_SENT_XON 0x00000004 815#define BGE_TXSTAT_LINK_UP 0x00000008 816#define BGE_TXSTAT_ODI_UFLOW 0x00000010 817#define BGE_TXSTAT_ODI_OFLOW 0x00000020 818 819/* Transmit MAC lengths register */ 820#define BGE_TXLEN_SLOTTIME 0x000000FF 821#define BGE_TXLEN_IPG 0x00000F00 822#define BGE_TXLEN_CRS 0x00003000 | 805 806/* Transmit MAC status register */ 807#define BGE_TXSTAT_RX_XOFFED 0x00000001 808#define BGE_TXSTAT_SENT_XOFF 0x00000002 809#define BGE_TXSTAT_SENT_XON 0x00000004 810#define BGE_TXSTAT_LINK_UP 0x00000008 811#define BGE_TXSTAT_ODI_UFLOW 0x00000010 812#define BGE_TXSTAT_ODI_OFLOW 0x00000020 813 814/* Transmit MAC lengths register */ 815#define BGE_TXLEN_SLOTTIME 0x000000FF 816#define BGE_TXLEN_IPG 0x00000F00 817#define BGE_TXLEN_CRS 0x00003000 |
| 818#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 819#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 |
|
| 823 824/* Receive MAC mode register */ 825#define BGE_RXMODE_RESET 0x00000001 826#define BGE_RXMODE_ENABLE 0x00000002 827#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 828#define BGE_RXMODE_RX_GIANTS 0x00000020 829#define BGE_RXMODE_RX_RUNTS 0x00000040 830#define BGE_RXMODE_8022_LENCHECK 0x00000080 --- 441 unchanged lines hidden (view full) --- 1272/* Receive List Selector Status register */ 1273#define BGE_RXLSSTAT_ERROR 0x00000004 1274 1275#define BGE_CPMU_CTRL 0x3600 1276#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1277#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1278#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1279#define BGE_CPMU_HST_ACC 0x361C | 820 821/* Receive MAC mode register */ 822#define BGE_RXMODE_RESET 0x00000001 823#define BGE_RXMODE_ENABLE 0x00000002 824#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 825#define BGE_RXMODE_RX_GIANTS 0x00000020 826#define BGE_RXMODE_RX_RUNTS 0x00000040 827#define BGE_RXMODE_8022_LENCHECK 0x00000080 --- 441 unchanged lines hidden (view full) --- 1269/* Receive List Selector Status register */ 1270#define BGE_RXLSSTAT_ERROR 0x00000004 1271 1272#define BGE_CPMU_CTRL 0x3600 1273#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1274#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1275#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1276#define BGE_CPMU_HST_ACC 0x361C |
| 1277#define BGE_CPMU_CLCK_ORIDE 0x3624 |
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| 1280#define BGE_CPMU_CLCK_STAT 0x3630 1281#define BGE_CPMU_MUTEX_REQ 0x365C 1282#define BGE_CPMU_MUTEX_GNT 0x3660 1283#define BGE_CPMU_PHY_STRAP 0x3664 1284 1285/* Central Power Management Unit (CPMU) register */ 1286#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1287#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 --- 11 unchanged lines hidden (view full) --- 1299 1300/* Link Aware Power Mode Clock Policy register */ 1301#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1302#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1303 1304#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1305#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1306 | 1278#define BGE_CPMU_CLCK_STAT 0x3630 1279#define BGE_CPMU_MUTEX_REQ 0x365C 1280#define BGE_CPMU_MUTEX_GNT 0x3660 1281#define BGE_CPMU_PHY_STRAP 0x3664 1282 1283/* Central Power Management Unit (CPMU) register */ 1284#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1285#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 --- 11 unchanged lines hidden (view full) --- 1297 1298/* Link Aware Power Mode Clock Policy register */ 1299#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1300#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1301 1302#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1303#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1304 |
| 1305/* Clock Speed Override Policy register */ 1306#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1307 |
|
| 1307/* CPMU Clock Status register */ 1308#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1309#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1310#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1311#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1312 1313/* CPMU Mutex Request register */ 1314#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 --- 231 unchanged lines hidden (view full) --- 1546#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1547#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1548#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1549#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1550#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1551#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1552#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1553#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 | 1308/* CPMU Clock Status register */ 1309#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1310#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1311#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1312#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1313 1314/* CPMU Mutex Request register */ 1315#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 --- 231 unchanged lines hidden (view full) --- 1547#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1548#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1549#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1550#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1551#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1552#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1553#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1554#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 |
| 1555#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 |
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| 1554 1555/* Read DMA status register */ 1556#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1557#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1558#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1559#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1560#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1561#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 --- 394 unchanged lines hidden (view full) --- 1956#define BGE_NVRAMACC_WRENABLE 0x00000002 1957 1958/* Mode control register */ 1959#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1960#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1961#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1962#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1963#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 | 1556 1557/* Read DMA status register */ 1558#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1559#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1560#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1561#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1562#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1563#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 --- 394 unchanged lines hidden (view full) --- 1958#define BGE_NVRAMACC_WRENABLE 0x00000002 1959 1960/* Mode control register */ 1961#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1962#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1963#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1964#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1965#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 |
| 1966#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1967#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 |
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| 1964#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1965#define BGE_MODECTL_NO_RX_CRC 0x00000400 1966#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1967#define BGE_MODECTL_NO_TX_INTR 0x00002000 1968#define BGE_MODECTL_NO_RX_INTR 0x00004000 1969#define BGE_MODECTL_FORCE_PCI32 0x00008000 | 1968#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1969#define BGE_MODECTL_NO_RX_CRC 0x00000400 1970#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1971#define BGE_MODECTL_NO_TX_INTR 0x00002000 1972#define BGE_MODECTL_NO_RX_INTR 0x00004000 1973#define BGE_MODECTL_FORCE_PCI32 0x00008000 |
| 1974#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 |
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| 1970#define BGE_MODECTL_STACKUP 0x00010000 1971#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 | 1975#define BGE_MODECTL_STACKUP 0x00010000 1976#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 |
| 1977#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 |
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| 1972#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1973#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1974#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1975#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1976#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1977#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1978#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1979#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 --- 313 unchanged lines hidden (view full) --- 2293#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2294#define BCOM_DEVICEID_BCM5714C 0x1668 2295#define BCOM_DEVICEID_BCM5714S 0x1669 2296#define BCOM_DEVICEID_BCM5715 0x1678 2297#define BCOM_DEVICEID_BCM5715S 0x1679 2298#define BCOM_DEVICEID_BCM5717 0x1655 2299#define BCOM_DEVICEID_BCM5718 0x1656 2300#define BCOM_DEVICEID_BCM5719 0x1657 | 1978#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1979#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1980#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1981#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1982#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1983#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1984#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1985#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 --- 313 unchanged lines hidden (view full) --- 2299#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2300#define BCOM_DEVICEID_BCM5714C 0x1668 2301#define BCOM_DEVICEID_BCM5714S 0x1669 2302#define BCOM_DEVICEID_BCM5715 0x1678 2303#define BCOM_DEVICEID_BCM5715S 0x1679 2304#define BCOM_DEVICEID_BCM5717 0x1655 2305#define BCOM_DEVICEID_BCM5718 0x1656 2306#define BCOM_DEVICEID_BCM5719 0x1657 |
| 2301#define BCOM_DEVICEID_BCM5720 0x1658 | 2307#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */ 2308#define BCOM_DEVICEID_BCM5720 0x165F |
| 2302#define BCOM_DEVICEID_BCM5721 0x1659 2303#define BCOM_DEVICEID_BCM5722 0x165A 2304#define BCOM_DEVICEID_BCM5723 0x165B 2305#define BCOM_DEVICEID_BCM5750 0x1676 2306#define BCOM_DEVICEID_BCM5750M 0x167C 2307#define BCOM_DEVICEID_BCM5751 0x1677 2308#define BCOM_DEVICEID_BCM5751F 0x167E 2309#define BCOM_DEVICEID_BCM5751M 0x167D --- 568 unchanged lines hidden --- | 2309#define BCOM_DEVICEID_BCM5721 0x1659 2310#define BCOM_DEVICEID_BCM5722 0x165A 2311#define BCOM_DEVICEID_BCM5723 0x165B 2312#define BCOM_DEVICEID_BCM5750 0x1676 2313#define BCOM_DEVICEID_BCM5750M 0x167C 2314#define BCOM_DEVICEID_BCM5751 0x1677 2315#define BCOM_DEVICEID_BCM5751F 0x167E 2316#define BCOM_DEVICEID_BCM5751M 0x167D --- 568 unchanged lines hidden --- |