1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
|
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 110367 2003-02-05 08:54:36Z ps $
|
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 114547 2003-05-02 19:53:40Z ps $ |
34 */ 35 36/* 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 */ 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 78#define BGE_UNMAPPED 0x00001000 79#define BGE_UNMAPPED_END 0x00001FFF 80#define BGE_DMA_DESCRIPTORS 0x00002000 81#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 82#define BGE_SEND_RING_1_TO_4 0x00004000 83#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 84 85/* Mappings for internal memory configuration */ 86#define BGE_STD_RX_RINGS 0x00006000 87#define BGE_STD_RX_RINGS_END 0x00006FFF 88#define BGE_JUMBO_RX_RINGS 0x00007000 89#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 90#define BGE_BUFFPOOL_1 0x00008000 91#define BGE_BUFFPOOL_1_END 0x0000FFFF 92#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */ 93#define BGE_BUFFPOOL_2_END 0x00017FFF 94#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */ 95#define BGE_BUFFPOOL_3_END 0x0001FFFF 96 97/* Mappings for external SSRAM configurations */ 98#define BGE_SEND_RING_5_TO_6 0x00006000 99#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 100#define BGE_SEND_RING_7_TO_8 0x00007000 101#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 102#define BGE_SEND_RING_9_TO_16 0x00008000 103#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 104#define BGE_EXT_STD_RX_RINGS 0x0000C000 105#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 106#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 107#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 108#define BGE_MINI_RX_RINGS 0x0000E000 109#define BGE_MINI_RX_RINGS_END 0x0000FFFF 110#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */ 111#define BGE_AVAIL_REGION1_END 0x00017FFF 112#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */ 113#define BGE_AVAIL_REGION2_END 0x0001FFFF 114#define BGE_EXT_SSRAM 0x00020000 115#define BGE_EXT_SSRAM_END 0x000FFFFF 116 117 118/* 119 * BCM570x register offsets. These are memory mapped registers 120 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 121 * Each register must be accessed using 32 bit operations. 122 * 123 * All registers are accessed through a 32K shared memory block. 124 * The first group of registers are actually copies of the PCI 125 * configuration space registers. 126 */ 127 128/* 129 * PCI registers defined in the PCI 2.2 spec. 130 */ 131#define BGE_PCI_VID 0x00 132#define BGE_PCI_DID 0x02 133#define BGE_PCI_CMD 0x04 134#define BGE_PCI_STS 0x06 135#define BGE_PCI_REV 0x08 136#define BGE_PCI_CLASS 0x09 137#define BGE_PCI_CACHESZ 0x0C 138#define BGE_PCI_LATTIMER 0x0D 139#define BGE_PCI_HDRTYPE 0x0E 140#define BGE_PCI_BIST 0x0F 141#define BGE_PCI_BAR0 0x10 142#define BGE_PCI_BAR1 0x14 143#define BGE_PCI_SUBSYS 0x2C 144#define BGE_PCI_SUBVID 0x2E 145#define BGE_PCI_ROMBASE 0x30 146#define BGE_PCI_CAPPTR 0x34 147#define BGE_PCI_INTLINE 0x3C 148#define BGE_PCI_INTPIN 0x3D 149#define BGE_PCI_MINGNT 0x3E 150#define BGE_PCI_MAXLAT 0x3F 151#define BGE_PCI_PCIXCAP 0x40 152#define BGE_PCI_NEXTPTR_PM 0x41 153#define BGE_PCI_PCIX_CMD 0x42 154#define BGE_PCI_PCIX_STS 0x44 155#define BGE_PCI_PWRMGMT_CAPID 0x48 156#define BGE_PCI_NEXTPTR_VPD 0x49 157#define BGE_PCI_PWRMGMT_CAPS 0x4A 158#define BGE_PCI_PWRMGMT_CMD 0x4C 159#define BGE_PCI_PWRMGMT_STS 0x4D 160#define BGE_PCI_PWRMGMT_DATA 0x4F 161#define BGE_PCI_VPD_CAPID 0x50 162#define BGE_PCI_NEXTPTR_MSI 0x51 163#define BGE_PCI_VPD_ADDR 0x52 164#define BGE_PCI_VPD_DATA 0x54 165#define BGE_PCI_MSI_CAPID 0x58 166#define BGE_PCI_NEXTPTR_NONE 0x59 167#define BGE_PCI_MSI_CTL 0x5A 168#define BGE_PCI_MSI_ADDR_HI 0x5C 169#define BGE_PCI_MSI_ADDR_LO 0x60 170#define BGE_PCI_MSI_DATA 0x64 171 172/* 173 * PCI registers specific to the BCM570x family. 174 */ 175#define BGE_PCI_MISC_CTL 0x68 176#define BGE_PCI_DMA_RW_CTL 0x6C 177#define BGE_PCI_PCISTATE 0x70 178#define BGE_PCI_CLKCTL 0x74 179#define BGE_PCI_REG_BASEADDR 0x78 180#define BGE_PCI_MEMWIN_BASEADDR 0x7C 181#define BGE_PCI_REG_DATA 0x80 182#define BGE_PCI_MEMWIN_DATA 0x84 183#define BGE_PCI_MODECTL 0x88 184#define BGE_PCI_MISC_CFG 0x8C 185#define BGE_PCI_MISC_LOCALCTL 0x90 186#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 187#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 188#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 189#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 190#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 191#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 192#define BGE_PCI_ISR_MBX_HI 0xB0 193#define BGE_PCI_ISR_MBX_LO 0xB4 194 195/* PCI Misc. Host control register */ 196#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 197#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 198#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 199#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 200#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 201#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 202#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 203#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 204#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 205 206#define BGE_BIGENDIAN_INIT \ 207 (BGE_PCIMISCCTL_ENDIAN_BYTESWAP| \ 208 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_CLEAR_INTA| \ 209 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR) 210 211#define BGE_LITTLEENDIAN_INIT \ 212 (BGE_PCIMISCCTL_CLEAR_INTA|BGE_PCIMISCCTL_MASK_PCI_INTR| \ 213 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_INDIRECT_ACCESS) 214 215#define BGE_ASICREV_TIGON_I 0x40000000 216#define BGE_ASICREV_TIGON_II 0x60000000 217#define BGE_ASICREV_BCM5700_B0 0x71000000 218#define BGE_ASICREV_BCM5700_B1 0x71020000 219#define BGE_ASICREV_BCM5700_B2 0x71030000 220#define BGE_ASICREV_BCM5700_ALTIMA 0x71040000 221#define BGE_ASICREV_BCM5700_C0 0x72000000 222#define BGE_ASICREV_BCM5701_A0 0x00000000 /* grrrr */ 223#define BGE_ASICREV_BCM5701_B0 0x01000000 224#define BGE_ASICREV_BCM5701_B2 0x01020000 225#define BGE_ASICREV_BCM5701_B5 0x01050000 226#define BGE_ASICREV_BCM5703_A0 0x10000000 227#define BGE_ASICREV_BCM5703_A1 0x10010000 228#define BGE_ASICREV_BCM5703_A2 0x10020000
|
229#define BGE_ASICREV_BCM5704_A0 0x20000000 230#define BGE_ASICREV_BCM5704_A1 0x20010000 231#define BGE_ASICREV_BCM5704_A2 0x20020000 |
232 233/* shorthand one */ 234#define BGE_ASICREV_BCM5700 0x71000000 235 236/* PCI DMA Read/Write Control register */ 237#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 238#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 239#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 240#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 241#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 242#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 243#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 244#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 245#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 246#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 247 248#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 249#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 250#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 251#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 252#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 253#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 254#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 255#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 256 257#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 258#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 259#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 260#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 261#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 262#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 263#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 264#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 265 266/* 267 * PCI state register -- note, this register is read only 268 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 269 * register is set. 270 */ 271#define BGE_PCISTATE_FORCE_RESET 0x00000001 272#define BGE_PCISTATE_INTR_STATE 0x00000002 273#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */ 274#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 33/66, 0 = 66/133 */ 275#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */ 276#define BGE_PCISTATE_WANT_EXPROM 0x00000020 277#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 278#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 279#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 280 281/* 282 * PCI Clock Control register -- note, this register is read only 283 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 284 * register is set. 285 */ 286#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 287#define BGE_PCICLOCKCTL_M66EN 0x00000080 288#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 289#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 290#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 291#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 292#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 293#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 294#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 295#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 296 297 298#ifndef PCIM_CMD_MWIEN 299#define PCIM_CMD_MWIEN 0x0010 300#endif 301 302/* 303 * High priority mailbox registers 304 * Each mailbox is 64-bits wide, though we only use the 305 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 306 * first. The NIC will load the mailbox after the lower 32 bit word 307 * has been updated. 308 */ 309#define BGE_MBX_IRQ0_HI 0x0200 310#define BGE_MBX_IRQ0_LO 0x0204 311#define BGE_MBX_IRQ1_HI 0x0208 312#define BGE_MBX_IRQ1_LO 0x020C 313#define BGE_MBX_IRQ2_HI 0x0210 314#define BGE_MBX_IRQ2_LO 0x0214 315#define BGE_MBX_IRQ3_HI 0x0218 316#define BGE_MBX_IRQ3_LO 0x021C 317#define BGE_MBX_GEN0_HI 0x0220 318#define BGE_MBX_GEN0_LO 0x0224 319#define BGE_MBX_GEN1_HI 0x0228 320#define BGE_MBX_GEN1_LO 0x022C 321#define BGE_MBX_GEN2_HI 0x0230 322#define BGE_MBX_GEN2_LO 0x0234 323#define BGE_MBX_GEN3_HI 0x0228 324#define BGE_MBX_GEN3_LO 0x022C 325#define BGE_MBX_GEN4_HI 0x0240 326#define BGE_MBX_GEN4_LO 0x0244 327#define BGE_MBX_GEN5_HI 0x0248 328#define BGE_MBX_GEN5_LO 0x024C 329#define BGE_MBX_GEN6_HI 0x0250 330#define BGE_MBX_GEN6_LO 0x0254 331#define BGE_MBX_GEN7_HI 0x0258 332#define BGE_MBX_GEN7_LO 0x025C 333#define BGE_MBX_RELOAD_STATS_HI 0x0260 334#define BGE_MBX_RELOAD_STATS_LO 0x0264 335#define BGE_MBX_RX_STD_PROD_HI 0x0268 336#define BGE_MBX_RX_STD_PROD_LO 0x026C 337#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 338#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 339#define BGE_MBX_RX_MINI_PROD_HI 0x0278 340#define BGE_MBX_RX_MINI_PROD_LO 0x027C 341#define BGE_MBX_RX_CONS0_HI 0x0280 342#define BGE_MBX_RX_CONS0_LO 0x0284 343#define BGE_MBX_RX_CONS1_HI 0x0288 344#define BGE_MBX_RX_CONS1_LO 0x028C 345#define BGE_MBX_RX_CONS2_HI 0x0290 346#define BGE_MBX_RX_CONS2_LO 0x0294 347#define BGE_MBX_RX_CONS3_HI 0x0298 348#define BGE_MBX_RX_CONS3_LO 0x029C 349#define BGE_MBX_RX_CONS4_HI 0x02A0 350#define BGE_MBX_RX_CONS4_LO 0x02A4 351#define BGE_MBX_RX_CONS5_HI 0x02A8 352#define BGE_MBX_RX_CONS5_LO 0x02AC 353#define BGE_MBX_RX_CONS6_HI 0x02B0 354#define BGE_MBX_RX_CONS6_LO 0x02B4 355#define BGE_MBX_RX_CONS7_HI 0x02B8 356#define BGE_MBX_RX_CONS7_LO 0x02BC 357#define BGE_MBX_RX_CONS8_HI 0x02C0 358#define BGE_MBX_RX_CONS8_LO 0x02C4 359#define BGE_MBX_RX_CONS9_HI 0x02C8 360#define BGE_MBX_RX_CONS9_LO 0x02CC 361#define BGE_MBX_RX_CONS10_HI 0x02D0 362#define BGE_MBX_RX_CONS10_LO 0x02D4 363#define BGE_MBX_RX_CONS11_HI 0x02D8 364#define BGE_MBX_RX_CONS11_LO 0x02DC 365#define BGE_MBX_RX_CONS12_HI 0x02E0 366#define BGE_MBX_RX_CONS12_LO 0x02E4 367#define BGE_MBX_RX_CONS13_HI 0x02E8 368#define BGE_MBX_RX_CONS13_LO 0x02EC 369#define BGE_MBX_RX_CONS14_HI 0x02F0 370#define BGE_MBX_RX_CONS14_LO 0x02F4 371#define BGE_MBX_RX_CONS15_HI 0x02F8 372#define BGE_MBX_RX_CONS15_LO 0x02FC 373#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 374#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 375#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 376#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 377#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 378#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 379#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 380#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 381#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 382#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 383#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 384#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 385#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 386#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 387#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 388#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 389#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 390#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 391#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 392#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 393#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 394#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 395#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 396#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 397#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 398#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 399#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 400#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 401#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 402#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 403#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 404#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 405#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 406#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 407#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 408#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 409#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 410#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 411#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 412#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 413#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 414#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 415#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 416#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 417#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 418#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 419#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 420#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 421#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 422#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 423#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 424#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 425#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 426#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 427#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 428#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 429#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 430#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 431#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 432#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 433#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 434#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 435#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 436#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 437 438#define BGE_TX_RINGS_MAX 4 439#define BGE_TX_RINGS_EXTSSRAM_MAX 16 440#define BGE_RX_RINGS_MAX 16 441 442/* Ethernet MAC control registers */ 443#define BGE_MAC_MODE 0x0400 444#define BGE_MAC_STS 0x0404 445#define BGE_MAC_EVT_ENB 0x0408 446#define BGE_MAC_LED_CTL 0x040C 447#define BGE_MAC_ADDR1_LO 0x0410 448#define BGE_MAC_ADDR1_HI 0x0414 449#define BGE_MAC_ADDR2_LO 0x0418 450#define BGE_MAC_ADDR2_HI 0x041C 451#define BGE_MAC_ADDR3_LO 0x0420 452#define BGE_MAC_ADDR3_HI 0x0424 453#define BGE_MAC_ADDR4_LO 0x0428 454#define BGE_MAC_ADDR4_HI 0x042C 455#define BGE_WOL_PATPTR 0x0430 456#define BGE_WOL_PATCFG 0x0434 457#define BGE_TX_RANDOM_BACKOFF 0x0438 458#define BGE_RX_MTU 0x043C 459#define BGE_GBIT_PCS_TEST 0x0440 460#define BGE_TX_TBI_AUTONEG 0x0444 461#define BGE_RX_TBI_AUTONEG 0x0448 462#define BGE_MI_COMM 0x044C 463#define BGE_MI_STS 0x0450 464#define BGE_MI_MODE 0x0454 465#define BGE_AUTOPOLL_STS 0x0458 466#define BGE_TX_MODE 0x045C 467#define BGE_TX_STS 0x0460 468#define BGE_TX_LENGTHS 0x0464 469#define BGE_RX_MODE 0x0468 470#define BGE_RX_STS 0x046C 471#define BGE_MAR0 0x0470 472#define BGE_MAR1 0x0474 473#define BGE_MAR2 0x0478 474#define BGE_MAR3 0x047C 475#define BGE_RX_BD_RULES_CTL0 0x0480 476#define BGE_RX_BD_RULES_MASKVAL0 0x0484 477#define BGE_RX_BD_RULES_CTL1 0x0488 478#define BGE_RX_BD_RULES_MASKVAL1 0x048C 479#define BGE_RX_BD_RULES_CTL2 0x0490 480#define BGE_RX_BD_RULES_MASKVAL2 0x0494 481#define BGE_RX_BD_RULES_CTL3 0x0498 482#define BGE_RX_BD_RULES_MASKVAL3 0x049C 483#define BGE_RX_BD_RULES_CTL4 0x04A0 484#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 485#define BGE_RX_BD_RULES_CTL5 0x04A8 486#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 487#define BGE_RX_BD_RULES_CTL6 0x04B0 488#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 489#define BGE_RX_BD_RULES_CTL7 0x04B8 490#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 491#define BGE_RX_BD_RULES_CTL8 0x04C0 492#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 493#define BGE_RX_BD_RULES_CTL9 0x04C8 494#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 495#define BGE_RX_BD_RULES_CTL10 0x04D0 496#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 497#define BGE_RX_BD_RULES_CTL11 0x04D8 498#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 499#define BGE_RX_BD_RULES_CTL12 0x04E0 500#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 501#define BGE_RX_BD_RULES_CTL13 0x04E8 502#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 503#define BGE_RX_BD_RULES_CTL14 0x04F0 504#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 505#define BGE_RX_BD_RULES_CTL15 0x04F8 506#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 507#define BGE_RX_RULES_CFG 0x0500 508#define BGE_RX_STATS 0x0800 509#define BGE_TX_STATS 0x0880 510 511/* Ethernet MAC Mode register */ 512#define BGE_MACMODE_RESET 0x00000001 513#define BGE_MACMODE_HALF_DUPLEX 0x00000002 514#define BGE_MACMODE_PORTMODE 0x0000000C 515#define BGE_MACMODE_LOOPBACK 0x00000010 516#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 517#define BGE_MACMODE_TX_BURST_ENB 0x00000100 518#define BGE_MACMODE_MAX_DEFER 0x00000200 519#define BGE_MACMODE_LINK_POLARITY 0x00000400 520#define BGE_MACMODE_RX_STATS_ENB 0x00000800 521#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 522#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 523#define BGE_MACMODE_TX_STATS_ENB 0x00004000 524#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 525#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 526#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 527#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 528#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 529#define BGE_MACMODE_MIP_ENB 0x00100000 530#define BGE_MACMODE_TXDMA_ENB 0x00200000 531#define BGE_MACMODE_RXDMA_ENB 0x00400000 532#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 533 534#define BGE_PORTMODE_NONE 0x00000000 535#define BGE_PORTMODE_MII 0x00000004 536#define BGE_PORTMODE_GMII 0x00000008 537#define BGE_PORTMODE_TBI 0x0000000C 538 539/* MAC Status register */ 540#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 541#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 542#define BGE_MACSTAT_RX_CFG 0x00000004 543#define BGE_MACSTAT_CFG_CHANGED 0x00000008 544#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 545#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 546#define BGE_MACSTAT_LINK_CHANGED 0x00001000 547#define BGE_MACSTAT_MI_COMPLETE 0x00400000 548#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 549#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 550#define BGE_MACSTAT_ODI_ERROR 0x02000000 551#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 552#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 553 554/* MAC Event Enable Register */ 555#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 556#define BGE_EVTENB_LINK_CHANGED 0x00001000 557#define BGE_EVTENB_MI_COMPLETE 0x00400000 558#define BGE_EVTENB_MI_INTERRUPT 0x00800000 559#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 560#define BGE_EVTENB_ODI_ERROR 0x02000000 561#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 562#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 563 564/* LED Control Register */ 565#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 566#define BGE_LEDCTL_1000MBPS_LED 0x00000002 567#define BGE_LEDCTL_100MBPS_LED 0x00000004 568#define BGE_LEDCTL_10MBPS_LED 0x00000008 569#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 570#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 571#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 572#define BGE_LEDCTL_1000MBPS_STS 0x00000080 573#define BGE_LEDCTL_100MBPS_STS 0x00000100 574#define BGE_LEDCTL_10MBPS_STS 0x00000200 575#define BGE_LEDCTL_TRADLED_STS 0x00000400 576#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 577#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 578 579/* TX backoff seed register */ 580#define BGE_TX_BACKOFF_SEED_MASK 0x3F 581 582/* Autopoll status register */ 583#define BGE_AUTOPOLLSTS_ERROR 0x00000001 584 585/* Transmit MAC mode register */ 586#define BGE_TXMODE_RESET 0x00000001 587#define BGE_TXMODE_ENABLE 0x00000002 588#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 589#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 590#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 591 592/* Transmit MAC status register */ 593#define BGE_TXSTAT_RX_XOFFED 0x00000001 594#define BGE_TXSTAT_SENT_XOFF 0x00000002 595#define BGE_TXSTAT_SENT_XON 0x00000004 596#define BGE_TXSTAT_LINK_UP 0x00000008 597#define BGE_TXSTAT_ODI_UFLOW 0x00000010 598#define BGE_TXSTAT_ODI_OFLOW 0x00000020 599 600/* Transmit MAC lengths register */ 601#define BGE_TXLEN_SLOTTIME 0x000000FF 602#define BGE_TXLEN_IPG 0x00000F00 603#define BGE_TXLEN_CRS 0x00003000 604 605/* Receive MAC mode register */ 606#define BGE_RXMODE_RESET 0x00000001 607#define BGE_RXMODE_ENABLE 0x00000002 608#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 609#define BGE_RXMODE_RX_GIANTS 0x00000020 610#define BGE_RXMODE_RX_RUNTS 0x00000040 611#define BGE_RXMODE_8022_LENCHECK 0x00000080 612#define BGE_RXMODE_RX_PROMISC 0x00000100 613#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 614#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 615 616/* Receive MAC status register */ 617#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 618#define BGE_RXSTAT_RCVD_XOFF 0x00000002 619#define BGE_RXSTAT_RCVD_XON 0x00000004 620 621/* Receive Rules Control register */ 622#define BGE_RXRULECTL_OFFSET 0x000000FF 623#define BGE_RXRULECTL_CLASS 0x00001F00 624#define BGE_RXRULECTL_HDRTYPE 0x0000E000 625#define BGE_RXRULECTL_COMPARE_OP 0x00030000 626#define BGE_RXRULECTL_MAP 0x01000000 627#define BGE_RXRULECTL_DISCARD 0x02000000 628#define BGE_RXRULECTL_MASK 0x04000000 629#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 630#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 631#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 632#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 633 634/* Receive Rules Mask register */ 635#define BGE_RXRULEMASK_VALUE 0x0000FFFF 636#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 637 638/* MI communication register */ 639#define BGE_MICOMM_DATA 0x0000FFFF 640#define BGE_MICOMM_REG 0x001F0000 641#define BGE_MICOMM_PHY 0x03E00000 642#define BGE_MICOMM_CMD 0x0C000000 643#define BGE_MICOMM_READFAIL 0x10000000 644#define BGE_MICOMM_BUSY 0x20000000 645 646#define BGE_MIREG(x) ((x & 0x1F) << 16) 647#define BGE_MIPHY(x) ((x & 0x1F) << 21) 648#define BGE_MICMD_WRITE 0x04000000 649#define BGE_MICMD_READ 0x08000000 650 651/* MI status register */ 652#define BGE_MISTS_LINK 0x00000001 653#define BGE_MISTS_10MBPS 0x00000002 654 655#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 656#define BGE_MIMODE_AUTOPOLL 0x00000010 657#define BGE_MIMODE_CLKCNT 0x001F0000 658 659 660/* 661 * Send data initiator control registers. 662 */ 663#define BGE_SDI_MODE 0x0C00 664#define BGE_SDI_STATUS 0x0C04 665#define BGE_SDI_STATS_CTL 0x0C08 666#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 667#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 668#define BGE_LOCSTATS_COS0 0x0C80 669#define BGE_LOCSTATS_COS1 0x0C84 670#define BGE_LOCSTATS_COS2 0x0C88 671#define BGE_LOCSTATS_COS3 0x0C8C 672#define BGE_LOCSTATS_COS4 0x0C90 673#define BGE_LOCSTATS_COS5 0x0C84 674#define BGE_LOCSTATS_COS6 0x0C98 675#define BGE_LOCSTATS_COS7 0x0C9C 676#define BGE_LOCSTATS_COS8 0x0CA0 677#define BGE_LOCSTATS_COS9 0x0CA4 678#define BGE_LOCSTATS_COS10 0x0CA8 679#define BGE_LOCSTATS_COS11 0x0CAC 680#define BGE_LOCSTATS_COS12 0x0CB0 681#define BGE_LOCSTATS_COS13 0x0CB4 682#define BGE_LOCSTATS_COS14 0x0CB8 683#define BGE_LOCSTATS_COS15 0x0CBC 684#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 685#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 686#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 687#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 688#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 689#define BGE_LOCSTATS_IRQS 0x0CD4 690#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 691#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 692 693/* Send Data Initiator mode register */ 694#define BGE_SDIMODE_RESET 0x00000001 695#define BGE_SDIMODE_ENABLE 0x00000002 696#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 697 698/* Send Data Initiator stats register */ 699#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 700 701/* Send Data Initiator stats control register */ 702#define BGE_SDISTATSCTL_ENABLE 0x00000001 703#define BGE_SDISTATSCTL_FASTER 0x00000002 704#define BGE_SDISTATSCTL_CLEAR 0x00000004 705#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 706#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 707 708/* 709 * Send Data Completion Control registers 710 */ 711#define BGE_SDC_MODE 0x1000 712#define BGE_SDC_STATUS 0x1004 713 714/* Send Data completion mode register */ 715#define BGE_SDCMODE_RESET 0x00000001 716#define BGE_SDCMODE_ENABLE 0x00000002 717#define BGE_SDCMODE_ATTN 0x00000004 718 719/* Send Data completion status register */ 720#define BGE_SDCSTAT_ATTN 0x00000004 721 722/* 723 * Send BD Ring Selector Control registers 724 */ 725#define BGE_SRS_MODE 0x1400 726#define BGE_SRS_STATUS 0x1404 727#define BGE_SRS_HWDIAG 0x1408 728#define BGE_SRS_LOC_NIC_CONS0 0x1440 729#define BGE_SRS_LOC_NIC_CONS1 0x1444 730#define BGE_SRS_LOC_NIC_CONS2 0x1448 731#define BGE_SRS_LOC_NIC_CONS3 0x144C 732#define BGE_SRS_LOC_NIC_CONS4 0x1450 733#define BGE_SRS_LOC_NIC_CONS5 0x1454 734#define BGE_SRS_LOC_NIC_CONS6 0x1458 735#define BGE_SRS_LOC_NIC_CONS7 0x145C 736#define BGE_SRS_LOC_NIC_CONS8 0x1460 737#define BGE_SRS_LOC_NIC_CONS9 0x1464 738#define BGE_SRS_LOC_NIC_CONS10 0x1468 739#define BGE_SRS_LOC_NIC_CONS11 0x146C 740#define BGE_SRS_LOC_NIC_CONS12 0x1470 741#define BGE_SRS_LOC_NIC_CONS13 0x1474 742#define BGE_SRS_LOC_NIC_CONS14 0x1478 743#define BGE_SRS_LOC_NIC_CONS15 0x147C 744 745/* Send BD Ring Selector Mode register */ 746#define BGE_SRSMODE_RESET 0x00000001 747#define BGE_SRSMODE_ENABLE 0x00000002 748#define BGE_SRSMODE_ATTN 0x00000004 749 750/* Send BD Ring Selector Status register */ 751#define BGE_SRSSTAT_ERROR 0x00000004 752 753/* Send BD Ring Selector HW Diagnostics register */ 754#define BGE_SRSHWDIAG_STATE 0x0000000F 755#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 756#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 757#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 758 759/* 760 * Send BD Initiator Selector Control registers 761 */ 762#define BGE_SBDI_MODE 0x1800 763#define BGE_SBDI_STATUS 0x1804 764#define BGE_SBDI_LOC_NIC_PROD0 0x1808 765#define BGE_SBDI_LOC_NIC_PROD1 0x180C 766#define BGE_SBDI_LOC_NIC_PROD2 0x1810 767#define BGE_SBDI_LOC_NIC_PROD3 0x1814 768#define BGE_SBDI_LOC_NIC_PROD4 0x1818 769#define BGE_SBDI_LOC_NIC_PROD5 0x181C 770#define BGE_SBDI_LOC_NIC_PROD6 0x1820 771#define BGE_SBDI_LOC_NIC_PROD7 0x1824 772#define BGE_SBDI_LOC_NIC_PROD8 0x1828 773#define BGE_SBDI_LOC_NIC_PROD9 0x182C 774#define BGE_SBDI_LOC_NIC_PROD10 0x1830 775#define BGE_SBDI_LOC_NIC_PROD11 0x1834 776#define BGE_SBDI_LOC_NIC_PROD12 0x1838 777#define BGE_SBDI_LOC_NIC_PROD13 0x183C 778#define BGE_SBDI_LOC_NIC_PROD14 0x1840 779#define BGE_SBDI_LOC_NIC_PROD15 0x1844 780 781/* Send BD Initiator Mode register */ 782#define BGE_SBDIMODE_RESET 0x00000001 783#define BGE_SBDIMODE_ENABLE 0x00000002 784#define BGE_SBDIMODE_ATTN 0x00000004 785 786/* Send BD Initiator Status register */ 787#define BGE_SBDISTAT_ERROR 0x00000004 788 789/* 790 * Send BD Completion Control registers 791 */ 792#define BGE_SBDC_MODE 0x1C00 793#define BGE_SBDC_STATUS 0x1C04 794 795/* Send BD Completion Control Mode register */ 796#define BGE_SBDCMODE_RESET 0x00000001 797#define BGE_SBDCMODE_ENABLE 0x00000002 798#define BGE_SBDCMODE_ATTN 0x00000004 799 800/* Send BD Completion Control Status register */ 801#define BGE_SBDCSTAT_ATTN 0x00000004 802 803/* 804 * Receive List Placement Control registers 805 */ 806#define BGE_RXLP_MODE 0x2000 807#define BGE_RXLP_STATUS 0x2004 808#define BGE_RXLP_SEL_LIST_LOCK 0x2008 809#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 810#define BGE_RXLP_CFG 0x2010 811#define BGE_RXLP_STATS_CTL 0x2014 812#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 813#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 814#define BGE_RXLP_HEAD0 0x2100 815#define BGE_RXLP_TAIL0 0x2104 816#define BGE_RXLP_COUNT0 0x2108 817#define BGE_RXLP_HEAD1 0x2110 818#define BGE_RXLP_TAIL1 0x2114 819#define BGE_RXLP_COUNT1 0x2118 820#define BGE_RXLP_HEAD2 0x2120 821#define BGE_RXLP_TAIL2 0x2124 822#define BGE_RXLP_COUNT2 0x2128 823#define BGE_RXLP_HEAD3 0x2130 824#define BGE_RXLP_TAIL3 0x2134 825#define BGE_RXLP_COUNT3 0x2138 826#define BGE_RXLP_HEAD4 0x2140 827#define BGE_RXLP_TAIL4 0x2144 828#define BGE_RXLP_COUNT4 0x2148 829#define BGE_RXLP_HEAD5 0x2150 830#define BGE_RXLP_TAIL5 0x2154 831#define BGE_RXLP_COUNT5 0x2158 832#define BGE_RXLP_HEAD6 0x2160 833#define BGE_RXLP_TAIL6 0x2164 834#define BGE_RXLP_COUNT6 0x2168 835#define BGE_RXLP_HEAD7 0x2170 836#define BGE_RXLP_TAIL7 0x2174 837#define BGE_RXLP_COUNT7 0x2178 838#define BGE_RXLP_HEAD8 0x2180 839#define BGE_RXLP_TAIL8 0x2184 840#define BGE_RXLP_COUNT8 0x2188 841#define BGE_RXLP_HEAD9 0x2190 842#define BGE_RXLP_TAIL9 0x2194 843#define BGE_RXLP_COUNT9 0x2198 844#define BGE_RXLP_HEAD10 0x21A0 845#define BGE_RXLP_TAIL10 0x21A4 846#define BGE_RXLP_COUNT10 0x21A8 847#define BGE_RXLP_HEAD11 0x21B0 848#define BGE_RXLP_TAIL11 0x21B4 849#define BGE_RXLP_COUNT11 0x21B8 850#define BGE_RXLP_HEAD12 0x21C0 851#define BGE_RXLP_TAIL12 0x21C4 852#define BGE_RXLP_COUNT12 0x21C8 853#define BGE_RXLP_HEAD13 0x21D0 854#define BGE_RXLP_TAIL13 0x21D4 855#define BGE_RXLP_COUNT13 0x21D8 856#define BGE_RXLP_HEAD14 0x21E0 857#define BGE_RXLP_TAIL14 0x21E4 858#define BGE_RXLP_COUNT14 0x21E8 859#define BGE_RXLP_HEAD15 0x21F0 860#define BGE_RXLP_TAIL15 0x21F4 861#define BGE_RXLP_COUNT15 0x21F8 862#define BGE_RXLP_LOCSTAT_COS0 0x2200 863#define BGE_RXLP_LOCSTAT_COS1 0x2204 864#define BGE_RXLP_LOCSTAT_COS2 0x2208 865#define BGE_RXLP_LOCSTAT_COS3 0x220C 866#define BGE_RXLP_LOCSTAT_COS4 0x2210 867#define BGE_RXLP_LOCSTAT_COS5 0x2214 868#define BGE_RXLP_LOCSTAT_COS6 0x2218 869#define BGE_RXLP_LOCSTAT_COS7 0x221C 870#define BGE_RXLP_LOCSTAT_COS8 0x2220 871#define BGE_RXLP_LOCSTAT_COS9 0x2224 872#define BGE_RXLP_LOCSTAT_COS10 0x2228 873#define BGE_RXLP_LOCSTAT_COS11 0x222C 874#define BGE_RXLP_LOCSTAT_COS12 0x2230 875#define BGE_RXLP_LOCSTAT_COS13 0x2234 876#define BGE_RXLP_LOCSTAT_COS14 0x2238 877#define BGE_RXLP_LOCSTAT_COS15 0x223C 878#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 879#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 880#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 881#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 882#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 883#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 884#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 885 886 887/* Receive List Placement mode register */ 888#define BGE_RXLPMODE_RESET 0x00000001 889#define BGE_RXLPMODE_ENABLE 0x00000002 890#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 891#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 892#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 893 894/* Receive List Placement Status register */ 895#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 896#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 897#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 898 899/* 900 * Receive Data and Receive BD Initiator Control Registers 901 */ 902#define BGE_RDBDI_MODE 0x2400 903#define BGE_RDBDI_STATUS 0x2404 904#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 905#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 906#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 907#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 908#define BGE_RX_STD_RCB_HADDR_HI 0x2450 909#define BGE_RX_STD_RCB_HADDR_LO 0x2454 910#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 911#define BGE_RX_STD_RCB_NICADDR 0x245C 912#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 913#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 914#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 915#define BGE_RX_MINI_RCB_NICADDR 0x246C 916#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 917#define BGE_RDBDI_STD_RX_CONS 0x2474 918#define BGE_RDBDI_MINI_RX_CONS 0x2478 919#define BGE_RDBDI_RETURN_PROD0 0x2480 920#define BGE_RDBDI_RETURN_PROD1 0x2484 921#define BGE_RDBDI_RETURN_PROD2 0x2488 922#define BGE_RDBDI_RETURN_PROD3 0x248C 923#define BGE_RDBDI_RETURN_PROD4 0x2490 924#define BGE_RDBDI_RETURN_PROD5 0x2494 925#define BGE_RDBDI_RETURN_PROD6 0x2498 926#define BGE_RDBDI_RETURN_PROD7 0x249C 927#define BGE_RDBDI_RETURN_PROD8 0x24A0 928#define BGE_RDBDI_RETURN_PROD9 0x24A4 929#define BGE_RDBDI_RETURN_PROD10 0x24A8 930#define BGE_RDBDI_RETURN_PROD11 0x24AC 931#define BGE_RDBDI_RETURN_PROD12 0x24B0 932#define BGE_RDBDI_RETURN_PROD13 0x24B4 933#define BGE_RDBDI_RETURN_PROD14 0x24B8 934#define BGE_RDBDI_RETURN_PROD15 0x24BC 935#define BGE_RDBDI_HWDIAG 0x24C0 936 937 938/* Receive Data and Receive BD Initiator Mode register */ 939#define BGE_RDBDIMODE_RESET 0x00000001 940#define BGE_RDBDIMODE_ENABLE 0x00000002 941#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 942#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 943#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 944 945/* Receive Data and Receive BD Initiator Status register */ 946#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 947#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 948#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 949 950 951/* 952 * Receive Data Completion Control registers 953 */ 954#define BGE_RDC_MODE 0x2800 955 956/* Receive Data Completion Mode register */ 957#define BGE_RDCMODE_RESET 0x00000001 958#define BGE_RDCMODE_ENABLE 0x00000002 959#define BGE_RDCMODE_ATTN 0x00000004 960 961/* 962 * Receive BD Initiator Control registers 963 */ 964#define BGE_RBDI_MODE 0x2C00 965#define BGE_RBDI_STATUS 0x2C04 966#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 967#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 968#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 969#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 970#define BGE_RBDI_STD_REPL_THRESH 0x2C18 971#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 972 973/* Receive BD Initiator Mode register */ 974#define BGE_RBDIMODE_RESET 0x00000001 975#define BGE_RBDIMODE_ENABLE 0x00000002 976#define BGE_RBDIMODE_ATTN 0x00000004 977 978/* Receive BD Initiator Status register */ 979#define BGE_RBDISTAT_ATTN 0x00000004 980 981/* 982 * Receive BD Completion Control registers 983 */ 984#define BGE_RBDC_MODE 0x3000 985#define BGE_RBDC_STATUS 0x3004 986#define BGE_RBDC_JUMBO_BD_PROD 0x3008 987#define BGE_RBDC_STD_BD_PROD 0x300C 988#define BGE_RBDC_MINI_BD_PROD 0x3010 989 990/* Receive BD completion mode register */ 991#define BGE_RBDCMODE_RESET 0x00000001 992#define BGE_RBDCMODE_ENABLE 0x00000002 993#define BGE_RBDCMODE_ATTN 0x00000004 994 995/* Receive BD completion status register */ 996#define BGE_RBDCSTAT_ERROR 0x00000004 997 998/* 999 * Receive List Selector Control registers 1000 */ 1001#define BGE_RXLS_MODE 0x3400 1002#define BGE_RXLS_STATUS 0x3404 1003 1004/* Receive List Selector Mode register */ 1005#define BGE_RXLSMODE_RESET 0x00000001 1006#define BGE_RXLSMODE_ENABLE 0x00000002 1007#define BGE_RXLSMODE_ATTN 0x00000004 1008 1009/* Receive List Selector Status register */ 1010#define BGE_RXLSSTAT_ERROR 0x00000004 1011 1012/* 1013 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1014 */ 1015#define BGE_MBCF_MODE 0x3800 1016#define BGE_MBCF_STATUS 0x3804 1017 1018/* Mbuf Cluster Free mode register */ 1019#define BGE_MBCFMODE_RESET 0x00000001 1020#define BGE_MBCFMODE_ENABLE 0x00000002 1021#define BGE_MBCFMODE_ATTN 0x00000004 1022 1023/* Mbuf Cluster Free status register */ 1024#define BGE_MBCFSTAT_ERROR 0x00000004 1025 1026/* 1027 * Host Coalescing Control registers 1028 */ 1029#define BGE_HCC_MODE 0x3C00 1030#define BGE_HCC_STATUS 0x3C04 1031#define BGE_HCC_RX_COAL_TICKS 0x3C08 1032#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1033#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1034#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1035#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */ 1036#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */ 1037#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */ 1038#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C34 /* BDs during interrupt */ 1039#define BGE_HCC_STATS_TICKS 0x3C28 1040#define BGE_HCC_STATS_ADDR_HI 0x3C30 1041#define BGE_HCC_STATS_ADDR_LO 0x3C34 1042#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1043#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1044#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */ 1045#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */ 1046#define BGE_FLOW_ATTN 0x3C48 1047#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1048#define BGE_HCC_STD_BD_CONS 0x3C54 1049#define BGE_HCC_MINI_BD_CONS 0x3C58 1050#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1051#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1052#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1053#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1054#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1055#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1056#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1057#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1058#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1059#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1060#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1061#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1062#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1063#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1064#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1065#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1066#define BGE_HCC_TX_BD_CONS0 0x3CC0 1067#define BGE_HCC_TX_BD_CONS1 0x3CC4 1068#define BGE_HCC_TX_BD_CONS2 0x3CC8 1069#define BGE_HCC_TX_BD_CONS3 0x3CCC 1070#define BGE_HCC_TX_BD_CONS4 0x3CD0 1071#define BGE_HCC_TX_BD_CONS5 0x3CD4 1072#define BGE_HCC_TX_BD_CONS6 0x3CD8 1073#define BGE_HCC_TX_BD_CONS7 0x3CDC 1074#define BGE_HCC_TX_BD_CONS8 0x3CE0 1075#define BGE_HCC_TX_BD_CONS9 0x3CE4 1076#define BGE_HCC_TX_BD_CONS10 0x3CE8 1077#define BGE_HCC_TX_BD_CONS11 0x3CEC 1078#define BGE_HCC_TX_BD_CONS12 0x3CF0 1079#define BGE_HCC_TX_BD_CONS13 0x3CF4 1080#define BGE_HCC_TX_BD_CONS14 0x3CF8 1081#define BGE_HCC_TX_BD_CONS15 0x3CFC 1082 1083 1084/* Host coalescing mode register */ 1085#define BGE_HCCMODE_RESET 0x00000001 1086#define BGE_HCCMODE_ENABLE 0x00000002 1087#define BGE_HCCMODE_ATTN 0x00000004 1088#define BGE_HCCMODE_COAL_NOW 0x00000008 1089#define BGE_HCCMODE_MSI_BITS 0x0x000070 1090#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1091 1092#define BGE_STATBLKSZ_FULL 0x00000000 1093#define BGE_STATBLKSZ_64BYTE 0x00000080 1094#define BGE_STATBLKSZ_32BYTE 0x00000100 1095 1096/* Host coalescing status register */ 1097#define BGE_HCCSTAT_ERROR 0x00000004 1098 1099/* Flow attention register */ 1100#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1101#define BGE_FLOWATTN_MEMARB 0x00000080 1102#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1103#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1104#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1105#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1106#define BGE_FLOWATTN_RDBDI 0x00080000 1107#define BGE_FLOWATTN_RXLS 0x00100000 1108#define BGE_FLOWATTN_RXLP 0x00200000 1109#define BGE_FLOWATTN_RBDC 0x00400000 1110#define BGE_FLOWATTN_RBDI 0x00800000 1111#define BGE_FLOWATTN_SDC 0x08000000 1112#define BGE_FLOWATTN_SDI 0x10000000 1113#define BGE_FLOWATTN_SRS 0x20000000 1114#define BGE_FLOWATTN_SBDC 0x40000000 1115#define BGE_FLOWATTN_SBDI 0x80000000 1116 1117/* 1118 * Memory arbiter registers 1119 */ 1120#define BGE_MARB_MODE 0x4000 1121#define BGE_MARB_STATUS 0x4004 1122#define BGE_MARB_TRAPADDR_HI 0x4008 1123#define BGE_MARB_TRAPADDR_LO 0x400C 1124 1125/* Memory arbiter mode register */ 1126#define BGE_MARBMODE_RESET 0x00000001 1127#define BGE_MARBMODE_ENABLE 0x00000002 1128#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1129#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1130#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1131#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1132#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1133#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1134#define BGE_MARBMODE_PCI_TRAP 0x00000100 1135#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1136#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1137#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1138#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1139#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1140#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1141#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1142#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1143#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1144#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1145#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1146#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1147#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1148#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1149#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1150#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1151#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1152 1153/* Memory arbiter status register */ 1154#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1155#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1156#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1157#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1158#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1159#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1160#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1161#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1162#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1163#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1164#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1165#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1166#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1167#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1168#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1169#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1170#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1171#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1172#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1173#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1174#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1175#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1176#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1177#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1178 1179/* 1180 * Buffer manager control registers 1181 */ 1182#define BGE_BMAN_MODE 0x4400 1183#define BGE_BMAN_STATUS 0x4404 1184#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1185#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1186#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1187#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1188#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1189#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1190#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1191#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1192#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1193#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1194#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1195#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1196#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1197#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1198#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1199#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1200#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1201#define BGE_BMAN_HWDIAG_1 0x444C 1202#define BGE_BMAN_HWDIAG_2 0x4450 1203#define BGE_BMAN_HWDIAG_3 0x4454 1204 1205/* Buffer manager mode register */ 1206#define BGE_BMANMODE_RESET 0x00000001 1207#define BGE_BMANMODE_ENABLE 0x00000002 1208#define BGE_BMANMODE_ATTN 0x00000004 1209#define BGE_BMANMODE_TESTMODE 0x00000008 1210#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1211 1212/* Buffer manager status register */ 1213#define BGE_BMANSTAT_ERRO 0x00000004 1214#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1215 1216 1217/* 1218 * Read DMA Control registers 1219 */ 1220#define BGE_RDMA_MODE 0x4800 1221#define BGE_RDMA_STATUS 0x4804 1222 1223/* Read DMA mode register */ 1224#define BGE_RDMAMODE_RESET 0x00000001 1225#define BGE_RDMAMODE_ENABLE 0x00000002 1226#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1227#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1228#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1229#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1230#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1231#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1232#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1233#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1234#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1235 1236/* Read DMA status register */ 1237#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1238#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1239#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1240#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1241#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1242#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1243#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1244#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1245 1246/* 1247 * Write DMA control registers 1248 */ 1249#define BGE_WDMA_MODE 0x4C00 1250#define BGE_WDMA_STATUS 0x4C04 1251 1252/* Write DMA mode register */ 1253#define BGE_WDMAMODE_RESET 0x00000001 1254#define BGE_WDMAMODE_ENABLE 0x00000002 1255#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1256#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1257#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1258#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1259#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1260#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1261#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1262#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1263#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1264 1265/* Write DMA status register */ 1266#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1267#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1268#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1269#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1270#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1271#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1272#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1273#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1274 1275 1276/* 1277 * RX CPU registers 1278 */ 1279#define BGE_RXCPU_MODE 0x5000 1280#define BGE_RXCPU_STATUS 0x5004 1281#define BGE_RXCPU_PC 0x501C 1282 1283/* RX CPU mode register */ 1284#define BGE_RXCPUMODE_RESET 0x00000001 1285#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1286#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1287#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1288#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1289#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1290#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1291#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1292#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1293#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1294#define BGE_RXCPUMODE_HALTCPU 0x00000400 1295#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1296#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1297#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1298 1299/* RX CPU status register */ 1300#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1301#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1302#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1303#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1304#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1305#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1306#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1307#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1308#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1309#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1310#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1311#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1312#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1313#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1314#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1315#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1316#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1317 1318 1319/* 1320 * TX CPU registers 1321 */ 1322#define BGE_TXCPU_MODE 0x5400 1323#define BGE_TXCPU_STATUS 0x5404 1324#define BGE_TXCPU_PC 0x541C 1325 1326/* TX CPU mode register */ 1327#define BGE_TXCPUMODE_RESET 0x00000001 1328#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1329#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1330#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1331#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1332#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1333#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1334#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1335#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1336#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1337#define BGE_TXCPUMODE_HALTCPU 0x00000400 1338#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1339#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1340 1341/* TX CPU status register */ 1342#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1343#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1344#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1345#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1346#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1347#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1348#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1349#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1350#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1351#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1352#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1353#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1354#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1355#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1356#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1357#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1358#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1359 1360 1361/* 1362 * Low priority mailbox registers 1363 */ 1364#define BGE_LPMBX_IRQ0_HI 0x5800 1365#define BGE_LPMBX_IRQ0_LO 0x5804 1366#define BGE_LPMBX_IRQ1_HI 0x5808 1367#define BGE_LPMBX_IRQ1_LO 0x580C 1368#define BGE_LPMBX_IRQ2_HI 0x5810 1369#define BGE_LPMBX_IRQ2_LO 0x5814 1370#define BGE_LPMBX_IRQ3_HI 0x5818 1371#define BGE_LPMBX_IRQ3_LO 0x581C 1372#define BGE_LPMBX_GEN0_HI 0x5820 1373#define BGE_LPMBX_GEN0_LO 0x5824 1374#define BGE_LPMBX_GEN1_HI 0x5828 1375#define BGE_LPMBX_GEN1_LO 0x582C 1376#define BGE_LPMBX_GEN2_HI 0x5830 1377#define BGE_LPMBX_GEN2_LO 0x5834 1378#define BGE_LPMBX_GEN3_HI 0x5828 1379#define BGE_LPMBX_GEN3_LO 0x582C 1380#define BGE_LPMBX_GEN4_HI 0x5840 1381#define BGE_LPMBX_GEN4_LO 0x5844 1382#define BGE_LPMBX_GEN5_HI 0x5848 1383#define BGE_LPMBX_GEN5_LO 0x584C 1384#define BGE_LPMBX_GEN6_HI 0x5850 1385#define BGE_LPMBX_GEN6_LO 0x5854 1386#define BGE_LPMBX_GEN7_HI 0x5858 1387#define BGE_LPMBX_GEN7_LO 0x585C 1388#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1389#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1390#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1391#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1392#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1393#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1394#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1395#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1396#define BGE_LPMBX_RX_CONS0_HI 0x5880 1397#define BGE_LPMBX_RX_CONS0_LO 0x5884 1398#define BGE_LPMBX_RX_CONS1_HI 0x5888 1399#define BGE_LPMBX_RX_CONS1_LO 0x588C 1400#define BGE_LPMBX_RX_CONS2_HI 0x5890 1401#define BGE_LPMBX_RX_CONS2_LO 0x5894 1402#define BGE_LPMBX_RX_CONS3_HI 0x5898 1403#define BGE_LPMBX_RX_CONS3_LO 0x589C 1404#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1405#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1406#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1407#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1408#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1409#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1410#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1411#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1412#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1413#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1414#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1415#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1416#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1417#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1418#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1419#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1420#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1421#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1422#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1423#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1424#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1425#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1426#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1427#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1428#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1429#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1430#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1431#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1432#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1433#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1434#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1435#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1436#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1437#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1438#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1439#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1440#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1441#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1442#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1443#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1444#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1445#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1446#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1447#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1448#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1449#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1450#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1451#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1452#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1453#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1454#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1455#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1456#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1457#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1458#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1459#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1460#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1461#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1462#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1463#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1464#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1465#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1466#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1467#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1468#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1469#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1470#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1471#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1472#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1473#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1474#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1475#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1476#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1477#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1478#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1479#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1480#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1481#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1482#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1483#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1484#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1485#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1486#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1487#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1488#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1489#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1490#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1491#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1492 1493/* 1494 * Flow throw Queue reset register 1495 */ 1496#define BGE_FTQ_RESET 0x5C00 1497 1498#define BGE_FTQRESET_DMAREAD 0x00000002 1499#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1500#define BGE_FTQRESET_DMADONE 0x00000010 1501#define BGE_FTQRESET_SBDC 0x00000020 1502#define BGE_FTQRESET_SDI 0x00000040 1503#define BGE_FTQRESET_WDMA 0x00000080 1504#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1505#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1506#define BGE_FTQRESET_SDC 0x00000400 1507#define BGE_FTQRESET_HCC 0x00000800 1508#define BGE_FTQRESET_TXFIFO 0x00001000 1509#define BGE_FTQRESET_MBC 0x00002000 1510#define BGE_FTQRESET_RBDC 0x00004000 1511#define BGE_FTQRESET_RXLP 0x00008000 1512#define BGE_FTQRESET_RDBDI 0x00010000 1513#define BGE_FTQRESET_RDC 0x00020000 1514#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1515 1516/* 1517 * Message Signaled Interrupt registers 1518 */ 1519#define BGE_MSI_MODE 0x6000 1520#define BGE_MSI_STATUS 0x6004 1521#define BGE_MSI_FIFOACCESS 0x6008 1522 1523/* MSI mode register */ 1524#define BGE_MSIMODE_RESET 0x00000001 1525#define BGE_MSIMODE_ENABLE 0x00000002 1526#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1527#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1528#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1529#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1530#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1531 1532/* MSI status register */ 1533#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1534#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1535#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1536#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1537#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1538 1539 1540/* 1541 * DMA Completion registers 1542 */ 1543#define BGE_DMAC_MODE 0x6400 1544 1545/* DMA Completion mode register */ 1546#define BGE_DMACMODE_RESET 0x00000001 1547#define BGE_DMACMODE_ENABLE 0x00000002 1548 1549 1550/* 1551 * General control registers. 1552 */ 1553#define BGE_MODE_CTL 0x6800 1554#define BGE_MISC_CFG 0x6804 1555#define BGE_MISC_LOCAL_CTL 0x6808 1556#define BGE_EE_ADDR 0x6838 1557#define BGE_EE_DATA 0x683C 1558#define BGE_EE_CTL 0x6840 1559#define BGE_MDI_CTL 0x6844 1560#define BGE_EE_DELAY 0x6848 1561 1562/* Mode control register */ 1563#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1564#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1565#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1566#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1567#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1568#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1569#define BGE_MODECTL_NO_RX_CRC 0x00000400 1570#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1571#define BGE_MODECTL_NO_TX_INTR 0x00002000 1572#define BGE_MODECTL_NO_RX_INTR 0x00004000 1573#define BGE_MODECTL_FORCE_PCI32 0x00008000 1574#define BGE_MODECTL_STACKUP 0x00010000 1575#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1576#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1577#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1578#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1579#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1580#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1581#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1582#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1583#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1584#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1585 1586/* Misc. config register */ 1587#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1588#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1589 1590#define BGE_32BITTIME_66MHZ (0x41 << 1) 1591 1592/* Misc. Local Control */ 1593#define BGE_MLC_INTR_STATE 0x00000001 1594#define BGE_MLC_INTR_CLR 0x00000002 1595#define BGE_MLC_INTR_SET 0x00000004 1596#define BGE_MLC_INTR_ONATTN 0x00000008 1597#define BGE_MLC_MISCIO_IN0 0x00000100 1598#define BGE_MLC_MISCIO_IN1 0x00000200 1599#define BGE_MLC_MISCIO_IN2 0x00000400 1600#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1601#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1602#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1603#define BGE_MLC_MISCIO_OUT0 0x00004000 1604#define BGE_MLC_MISCIO_OUT1 0x00008000 1605#define BGE_MLC_MISCIO_OUT2 0x00010000 1606#define BGE_MLC_EXTRAM_ENB 0x00020000 1607#define BGE_MLC_SRAM_SIZE 0x001C0000 1608#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */ 1609#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */ 1610#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1611#define BGE_MLC_AUTO_EEPROM 0x01000000 1612 1613#define BGE_SSRAMSIZE_256KB 0x00000000 1614#define BGE_SSRAMSIZE_512KB 0x00040000 1615#define BGE_SSRAMSIZE_1MB 0x00080000 1616#define BGE_SSRAMSIZE_2MB 0x000C0000 1617#define BGE_SSRAMSIZE_4MB 0x00100000 1618#define BGE_SSRAMSIZE_8MB 0x00140000 1619#define BGE_SSRAMSIZE_16M 0x00180000 1620 1621/* EEPROM address register */ 1622#define BGE_EEADDR_ADDRESS 0x0000FFFC 1623#define BGE_EEADDR_HALFCLK 0x01FF0000 1624#define BGE_EEADDR_START 0x02000000 1625#define BGE_EEADDR_DEVID 0x1C000000 1626#define BGE_EEADDR_RESET 0x20000000 1627#define BGE_EEADDR_DONE 0x40000000 1628#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */ 1629 1630#define BGE_EEDEVID(x) ((x & 7) << 26) 1631#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1632#define BGE_HALFCLK_384SCL 0x60 1633#define BGE_EE_READCMD \ 1634 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1635 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE) 1636#define BGE_EE_WRCMD \ 1637 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \ 1638 BGE_EEADDR_START|BGE_EEADDR_DONE) 1639 1640/* EEPROM Control register */ 1641#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1642#define BGE_EECTL_CLKOUT 0x00000002 1643#define BGE_EECTL_CLKIN 0x00000004 1644#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1645#define BGE_EECTL_DATAOUT 0x00000010 1646#define BGE_EECTL_DATAIN 0x00000020 1647 1648/* MDI (MII/GMII) access register */ 1649#define BGE_MDI_DATA 0x00000001 1650#define BGE_MDI_DIR 0x00000002 1651#define BGE_MDI_SEL 0x00000004 1652#define BGE_MDI_CLK 0x00000008 1653 1654#define BGE_MEMWIN_START 0x00008000 1655#define BGE_MEMWIN_END 0x0000FFFF 1656 1657 1658#define BGE_MEMWIN_READ(sc, x, val) \ 1659 do { \ 1660 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1661 (0xFFFF0000 & x), 4); \ 1662 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1663 } while(0) 1664 1665#define BGE_MEMWIN_WRITE(sc, x, val) \ 1666 do { \ 1667 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1668 (0xFFFF0000 & x), 4); \ 1669 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1670 } while(0) 1671 1672/* 1673 * This magic number is used to prevent PXE restart when we 1674 * issue a software reset. We write this magic number to the 1675 * firmware mailbox at 0xB50 in order to prevent the PXE boot 1676 * code from running. 1677 */ 1678#define BGE_MAGIC_NUMBER 0x4B657654 1679 1680typedef struct { 1681 u_int32_t bge_addr_hi; 1682 u_int32_t bge_addr_lo; 1683} bge_hostaddr; 1684#define BGE_HOSTADDR(x) ((x).bge_addr_lo) 1685 1686/* Ring control block structure */ 1687struct bge_rcb { 1688 bge_hostaddr bge_hostaddr; 1689 u_int32_t bge_maxlen_flags; 1690 u_int32_t bge_nicaddr; 1691}; 1692#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags)) 1693 1694#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1695#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1696 1697struct bge_tx_bd { 1698 bge_hostaddr bge_addr; 1699 u_int16_t bge_flags; 1700 u_int16_t bge_len; 1701 u_int16_t bge_vlan_tag; 1702 u_int16_t bge_rsvd; 1703}; 1704 1705#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1706#define BGE_TXBDFLAG_IP_CSUM 0x0002 1707#define BGE_TXBDFLAG_END 0x0004 1708#define BGE_TXBDFLAG_IP_FRAG 0x0008 1709#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1710#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1711#define BGE_TXBDFLAG_COAL_NOW 0x0080 1712#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1713#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1714#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1715#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1716#define BGE_TXBDFLAG_NO_CRC 0x8000 1717 1718#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1719 BGE_SEND_RING_1_TO_4 + \ 1720 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1721 1722struct bge_rx_bd { 1723 bge_hostaddr bge_addr; 1724 u_int16_t bge_len; 1725 u_int16_t bge_idx; 1726 u_int16_t bge_flags; 1727 u_int16_t bge_type; 1728 u_int16_t bge_tcp_udp_csum; 1729 u_int16_t bge_ip_csum; 1730 u_int16_t bge_vlan_tag; 1731 u_int16_t bge_error_flag; 1732 u_int32_t bge_rsvd; 1733 u_int32_t bge_opaque; 1734}; 1735 1736#define BGE_RXBDFLAG_END 0x0004 1737#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1738#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1739#define BGE_RXBDFLAG_ERROR 0x0400 1740#define BGE_RXBDFLAG_MINI_RING 0x0800 1741#define BGE_RXBDFLAG_IP_CSUM 0x1000 1742#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1743#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1744 1745#define BGE_RXERRFLAG_BAD_CRC 0x0001 1746#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1747#define BGE_RXERRFLAG_LINK_LOST 0x0004 1748#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1749#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1750#define BGE_RXERRFLAG_RUNT 0x0020 1751#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1752#define BGE_RXERRFLAG_GIANT 0x0080 1753 1754struct bge_sts_idx { 1755 u_int16_t bge_rx_prod_idx; 1756 u_int16_t bge_tx_cons_idx; 1757}; 1758 1759struct bge_status_block { 1760 u_int32_t bge_status; 1761 u_int32_t bge_rsvd0; 1762 u_int16_t bge_rx_jumbo_cons_idx; 1763 u_int16_t bge_rx_std_cons_idx; 1764 u_int16_t bge_rx_mini_cons_idx; 1765 u_int16_t bge_rsvd1; 1766 struct bge_sts_idx bge_idx[16]; 1767}; 1768 1769#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1770#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1771 1772#define BGE_STATFLAG_UPDATED 0x00000001 1773#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1774#define BGE_STATFLAG_ERROR 0x00000004 1775 1776 1777/* 1778 * Broadcom Vendor ID 1779 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1780 * even though they're now manufactured by Broadcom) 1781 */ 1782#define BCOM_VENDORID 0x14E4 1783#define BCOM_DEVICEID_BCM5700 0x1644 1784#define BCOM_DEVICEID_BCM5701 0x1645 1785#define BCOM_DEVICEID_BCM5702X 0x16A6 1786#define BCOM_DEVICEID_BCM5703X 0x16A7
|
1787#define BCOM_DEVICEID_BCM5704C 0x1648 1788#define BCOM_DEVICEID_BCM5704S 0x16A8 |
1789 1790/* 1791 * Alteon AceNIC PCI vendor/device ID. 1792 */ 1793#define ALT_VENDORID 0x12AE 1794#define ALT_DEVICEID_ACENIC 0x0001 1795#define ALT_DEVICEID_ACENIC_COPPER 0x0002 1796#define ALT_DEVICEID_BCM5700 0x0003 1797#define ALT_DEVICEID_BCM5701 0x0004 1798 1799/* 1800 * 3Com 3c985 PCI vendor/device ID. 1801 */ 1802#define TC_VENDORID 0x10B7 1803#define TC_DEVICEID_3C985 0x0001 1804#define TC_DEVICEID_3C996 0x0003 1805 1806/* 1807 * SysKonnect PCI vendor ID 1808 */ 1809#define SK_VENDORID 0x1148 1810#define SK_DEVICEID_ALTIMA 0x4400 1811#define SK_SUBSYSID_9D21 0x4421 1812#define SK_SUBSYSID_9D41 0x4441 1813 1814/* 1815 * Altima PCI vendor/device ID. 1816 */ 1817#define ALTIMA_VENDORID 0x173b 1818#define ALTIMA_DEVICE_AC1000 0x03e8 1819#define ALTIMA_DEVICE_AC9100 0x03ea 1820 1821/* 1822 * Offset of MAC address inside EEPROM. 1823 */ 1824#define BGE_EE_MAC_OFFSET 0x7C 1825#define BGE_EE_HWCFG_OFFSET 0xC8 1826 1827#define BGE_HWCFG_VOLTAGE 0x00000003 1828#define BGE_HWCFG_PHYLED_MODE 0x0000000C 1829#define BGE_HWCFG_MEDIA 0x00000030 1830 1831#define BGE_VOLTAGE_1POINT3 0x00000000 1832#define BGE_VOLTAGE_1POINT8 0x00000001 1833 1834#define BGE_PHYLEDMODE_UNSPEC 0x00000000 1835#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 1836#define BGE_PHYLEDMODE_SINGLELED 0x00000008 1837 1838#define BGE_MEDIA_UNSPEC 0x00000000 1839#define BGE_MEDIA_COPPER 0x00000010 1840#define BGE_MEDIA_FIBER 0x00000020 1841 1842#define BGE_PCI_READ_CMD 0x06000000 1843#define BGE_PCI_WRITE_CMD 0x70000000 1844 1845#define BGE_TICKS_PER_SEC 1000000 1846 1847/* 1848 * Ring size constants. 1849 */ 1850#define BGE_EVENT_RING_CNT 256 1851#define BGE_CMD_RING_CNT 64 1852#define BGE_STD_RX_RING_CNT 512 1853#define BGE_JUMBO_RX_RING_CNT 256 1854#define BGE_MINI_RX_RING_CNT 1024 1855#define BGE_RETURN_RING_CNT 1024 1856 1857/* 1858 * Possible TX ring sizes. 1859 */ 1860#define BGE_TX_RING_CNT_128 128 1861#define BGE_TX_RING_BASE_128 0x3800 1862 1863#define BGE_TX_RING_CNT_256 256 1864#define BGE_TX_RING_BASE_256 0x3000 1865 1866#define BGE_TX_RING_CNT_512 512 1867#define BGE_TX_RING_BASE_512 0x2000 1868 1869#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 1870#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 1871 1872/* 1873 * Tigon III statistics counters. 1874 */ 1875struct bge_stats { 1876 u_int8_t Reserved0[256]; 1877 1878 /* Statistics maintained by Receive MAC. */ 1879 bge_hostaddr ifHCInOctets; 1880 bge_hostaddr Reserved1; 1881 bge_hostaddr etherStatsFragments; 1882 bge_hostaddr ifHCInUcastPkts; 1883 bge_hostaddr ifHCInMulticastPkts; 1884 bge_hostaddr ifHCInBroadcastPkts; 1885 bge_hostaddr dot3StatsFCSErrors; 1886 bge_hostaddr dot3StatsAlignmentErrors; 1887 bge_hostaddr xonPauseFramesReceived; 1888 bge_hostaddr xoffPauseFramesReceived; 1889 bge_hostaddr macControlFramesReceived; 1890 bge_hostaddr xoffStateEntered; 1891 bge_hostaddr dot3StatsFramesTooLong; 1892 bge_hostaddr etherStatsJabbers; 1893 bge_hostaddr etherStatsUndersizePkts; 1894 bge_hostaddr inRangeLengthError; 1895 bge_hostaddr outRangeLengthError; 1896 bge_hostaddr etherStatsPkts64Octets; 1897 bge_hostaddr etherStatsPkts65Octetsto127Octets; 1898 bge_hostaddr etherStatsPkts128Octetsto255Octets; 1899 bge_hostaddr etherStatsPkts256Octetsto511Octets; 1900 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 1901 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 1902 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 1903 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 1904 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 1905 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 1906 1907 bge_hostaddr Unused1[37]; 1908 1909 /* Statistics maintained by Transmit MAC. */ 1910 bge_hostaddr ifHCOutOctets; 1911 bge_hostaddr Reserved2; 1912 bge_hostaddr etherStatsCollisions; 1913 bge_hostaddr outXonSent; 1914 bge_hostaddr outXoffSent; 1915 bge_hostaddr flowControlDone; 1916 bge_hostaddr dot3StatsInternalMacTransmitErrors; 1917 bge_hostaddr dot3StatsSingleCollisionFrames; 1918 bge_hostaddr dot3StatsMultipleCollisionFrames; 1919 bge_hostaddr dot3StatsDeferredTransmissions; 1920 bge_hostaddr Reserved3; 1921 bge_hostaddr dot3StatsExcessiveCollisions; 1922 bge_hostaddr dot3StatsLateCollisions; 1923 bge_hostaddr dot3Collided2Times; 1924 bge_hostaddr dot3Collided3Times; 1925 bge_hostaddr dot3Collided4Times; 1926 bge_hostaddr dot3Collided5Times; 1927 bge_hostaddr dot3Collided6Times; 1928 bge_hostaddr dot3Collided7Times; 1929 bge_hostaddr dot3Collided8Times; 1930 bge_hostaddr dot3Collided9Times; 1931 bge_hostaddr dot3Collided10Times; 1932 bge_hostaddr dot3Collided11Times; 1933 bge_hostaddr dot3Collided12Times; 1934 bge_hostaddr dot3Collided13Times; 1935 bge_hostaddr dot3Collided14Times; 1936 bge_hostaddr dot3Collided15Times; 1937 bge_hostaddr ifHCOutUcastPkts; 1938 bge_hostaddr ifHCOutMulticastPkts; 1939 bge_hostaddr ifHCOutBroadcastPkts; 1940 bge_hostaddr dot3StatsCarrierSenseErrors; 1941 bge_hostaddr ifOutDiscards; 1942 bge_hostaddr ifOutErrors; 1943 1944 bge_hostaddr Unused2[31]; 1945 1946 /* Statistics maintained by Receive List Placement. */ 1947 bge_hostaddr COSIfHCInPkts[16]; 1948 bge_hostaddr COSFramesDroppedDueToFilters; 1949 bge_hostaddr nicDmaWriteQueueFull; 1950 bge_hostaddr nicDmaWriteHighPriQueueFull; 1951 bge_hostaddr nicNoMoreRxBDs; 1952 bge_hostaddr ifInDiscards; 1953 bge_hostaddr ifInErrors; 1954 bge_hostaddr nicRecvThresholdHit; 1955 1956 bge_hostaddr Unused3[9]; 1957 1958 /* Statistics maintained by Send Data Initiator. */ 1959 bge_hostaddr COSIfHCOutPkts[16]; 1960 bge_hostaddr nicDmaReadQueueFull; 1961 bge_hostaddr nicDmaReadHighPriQueueFull; 1962 bge_hostaddr nicSendDataCompQueueFull; 1963 1964 /* Statistics maintained by Host Coalescing. */ 1965 bge_hostaddr nicRingSetSendProdIndex; 1966 bge_hostaddr nicRingStatusUpdate; 1967 bge_hostaddr nicInterrupts; 1968 bge_hostaddr nicAvoidedInterrupts; 1969 bge_hostaddr nicSendThresholdHit; 1970 1971 u_int8_t Reserved4[320]; 1972}; 1973 1974/* 1975 * Tigon general information block. This resides in host memory 1976 * and contains the status counters, ring control blocks and 1977 * producer pointers. 1978 */ 1979 1980struct bge_gib { 1981 struct bge_stats bge_stats; 1982 struct bge_rcb bge_tx_rcb[16]; 1983 struct bge_rcb bge_std_rx_rcb; 1984 struct bge_rcb bge_jumbo_rx_rcb; 1985 struct bge_rcb bge_mini_rx_rcb; 1986 struct bge_rcb bge_return_rcb; 1987}; 1988 1989#define BGE_FRAMELEN 1518 1990#define BGE_MAX_FRAMELEN 1536 1991#define BGE_JUMBO_FRAMELEN 9018 1992#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 1993#define BGE_PAGE_SIZE PAGE_SIZE 1994#define BGE_MIN_FRAMELEN 60 1995 1996/* 1997 * Other utility macros. 1998 */ 1999#define BGE_INC(x, y) (x) = (x + 1) % y 2000 2001/* 2002 * Vital product data and structures. 2003 */ 2004#define BGE_VPD_FLAG 0x8000 2005 2006/* VPD structures */ 2007struct vpd_res { 2008 u_int8_t vr_id; 2009 u_int8_t vr_len; 2010 u_int8_t vr_pad; 2011}; 2012 2013struct vpd_key { 2014 char vk_key[2]; 2015 u_int8_t vk_len; 2016}; 2017 2018#define VPD_RES_ID 0x82 /* ID string */ 2019#define VPD_RES_READ 0x90 /* start of read only area */ 2020#define VPD_RES_WRITE 0x81 /* start of read/write area */ 2021#define VPD_RES_END 0x78 /* end tag */ 2022 2023 2024/* 2025 * Register access macros. The Tigon always uses memory mapped register 2026 * accesses and all registers must be accessed with 32 bit operations. 2027 */ 2028 2029#define CSR_WRITE_4(sc, reg, val) \ 2030 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2031 2032#define CSR_READ_4(sc, reg) \ 2033 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2034 2035#define BGE_SETBIT(sc, reg, x) \ 2036 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x))) 2037#define BGE_CLRBIT(sc, reg, x) \ 2038 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2039 2040#define PCI_SETBIT(dev, reg, x, s) \ 2041 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s) 2042#define PCI_CLRBIT(dev, reg, x, s) \ 2043 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2044 2045/* 2046 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2047 * values are tuneable. They control the actual amount of buffers 2048 * allocated for the standard, mini and jumbo receive rings. 2049 */ 2050 2051#define BGE_SSLOTS 256 2052#define BGE_MSLOTS 256 2053#define BGE_JSLOTS 384 2054 2055#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2056#define BGE_JLEN (BGE_JRAWLEN + (sizeof(u_int64_t) - \ 2057 (BGE_JRAWLEN % sizeof(u_int64_t)))) 2058#define BGE_JPAGESZ PAGE_SIZE 2059#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2060#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2061 2062/* 2063 * Ring structures. Most of these reside in host memory and we tell 2064 * the NIC where they are via the ring control blocks. The exceptions 2065 * are the tx and command rings, which live in NIC memory and which 2066 * we access via the shared memory window. 2067 */ 2068struct bge_ring_data { 2069 struct bge_rx_bd bge_rx_std_ring[BGE_STD_RX_RING_CNT]; 2070 struct bge_rx_bd bge_rx_jumbo_ring[BGE_JUMBO_RX_RING_CNT]; 2071 struct bge_rx_bd bge_rx_return_ring[BGE_RETURN_RING_CNT]; 2072 struct bge_tx_bd bge_tx_ring[BGE_TX_RING_CNT]; 2073 struct bge_status_block bge_status_block; 2074 struct bge_tx_desc *bge_tx_ring_nic;/* pointer to shared mem */ 2075 struct bge_cmd_desc *bge_cmd_ring; /* pointer to shared mem */ 2076 struct bge_gib bge_info; 2077}; 2078 2079/* 2080 * Mbuf pointers. We need these to keep track of the virtual addresses 2081 * of our mbuf chains since we can only convert from physical to virtual, 2082 * not the other way around. 2083 */ 2084struct bge_chain_data { 2085 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT]; 2086 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2087 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2088 struct mbuf *bge_rx_mini_chain[BGE_MINI_RX_RING_CNT]; 2089 /* Stick the jumbo mem management stuff here too. */ 2090 caddr_t bge_jslots[BGE_JSLOTS]; 2091 void *bge_jumbo_buf; 2092}; 2093 2094struct bge_type { 2095 u_int16_t bge_vid; 2096 u_int16_t bge_did; 2097 char *bge_name; 2098}; 2099 2100#define BGE_HWREV_TIGON 0x01 2101#define BGE_HWREV_TIGON_II 0x02 2102#define BGE_TIMEOUT 1000 2103#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */ 2104 2105struct bge_jpool_entry { 2106 int slot; 2107 SLIST_ENTRY(bge_jpool_entry) jpool_entries; 2108}; 2109 2110struct bge_bcom_hack { 2111 int reg; 2112 int val; 2113}; 2114 2115struct bge_softc { 2116 struct arpcom arpcom; /* interface info */ 2117 device_t bge_dev; 2118 device_t bge_miibus; 2119 bus_space_handle_t bge_bhandle; 2120 vm_offset_t bge_vhandle; 2121 bus_space_tag_t bge_btag; 2122 void *bge_intrhand; 2123 struct resource *bge_irq; 2124 struct resource *bge_res; 2125 struct ifmedia bge_ifmedia; /* TBI media info */ 2126 u_int8_t bge_unit; /* interface number */ 2127 u_int8_t bge_extram; /* has external SSRAM */ 2128 u_int8_t bge_tbi; 2129 u_int8_t bge_rx_alignment_bug; 2130 u_int32_t bge_asicrev; 2131 struct bge_ring_data *bge_rdata; /* rings */ 2132 struct bge_chain_data bge_cdata; /* mbufs */ 2133 u_int16_t bge_tx_saved_considx; 2134 u_int16_t bge_rx_saved_considx; 2135 u_int16_t bge_ev_saved_considx; 2136 u_int16_t bge_std; /* current std ring head */ 2137 u_int16_t bge_jumbo; /* current jumo ring head */ 2138 SLIST_HEAD(__bge_jfreehead, bge_jpool_entry) bge_jfree_listhead; 2139 SLIST_HEAD(__bge_jinusehead, bge_jpool_entry) bge_jinuse_listhead; 2140 u_int32_t bge_stat_ticks; 2141 u_int32_t bge_rx_coal_ticks; 2142 u_int32_t bge_tx_coal_ticks; 2143 u_int32_t bge_rx_max_coal_bds; 2144 u_int32_t bge_tx_max_coal_bds; 2145 u_int32_t bge_tx_buf_ratio; 2146 int bge_if_flags; 2147 int bge_txcnt; 2148 int bge_link; 2149 struct callout_handle bge_stat_ch; 2150 char *bge_vpd_prodname; 2151 char *bge_vpd_readonly; 2152}; 2153 2154#ifdef __alpha__ 2155#undef vtophys 2156#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 2157#endif
|