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1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *	1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 253408 2013-07-17 04:53:53Z yongari $	33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 253480 2013-07-20 07:09:50Z yongari $
34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SRAM_FW_MB 0x00000B50 75#define BGE_SRAM_DATA_SIG 0x00000B54 76#define BGE_SRAM_DATA_CFG 0x00000B58 77#define BGE_SRAM_FW_CMD_MB 0x00000B78 78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84#define BGE_UNMAPPED 0x00001000 85#define BGE_UNMAPPED_END 0x00001FFF 86#define BGE_DMA_DESCRIPTORS 0x00002000 87#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88#define BGE_SEND_RING_5717 0x00004000 89#define BGE_SEND_RING_1_TO_4 0x00004000 90#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 91 92/ Firmware interface / 93#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 / 'KevT' / 94 95#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96#define BGE_FW_CMD_PAUSE 0x00000002 97#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102* 103#define BGE_FW_HB_TIMEOUT_SEC 3 104 105#define BGE_FW_DRV_STATE_START 0x00000001 106#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109#define BGE_FW_DRV_STATE_WOL 0x00000003 110#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111 112/* Mappings for internal memory configuration / 113#define BGE_STD_RX_RINGS 0x00006000 114#define BGE_STD_RX_RINGS_END 0x00006FFF 115#define BGE_JUMBO_RX_RINGS 0x00007000 116#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117#define BGE_BUFFPOOL_1 0x00008000 118#define BGE_BUFFPOOL_1_END 0x0000FFFF 119#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 120#define BGE_BUFFPOOL_2_END 0x00017FFF 121#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 122#define BGE_BUFFPOOL_3_END 0x0001FFFF 123#define BGE_STD_RX_RINGS_5717 0x00040000 124#define BGE_JUMBO_RX_RINGS_5717 0x00044400 125* 126/* Mappings for external SSRAM configurations / 127#define BGE_SEND_RING_5_TO_6 0x00006000 128#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129#define BGE_SEND_RING_7_TO_8 0x00007000 130#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131#define BGE_SEND_RING_9_TO_16 0x00008000 132#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133#define BGE_EXT_STD_RX_RINGS 0x0000C000 134#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137#define BGE_MINI_RX_RINGS 0x0000E000 138#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 140#define BGE_AVAIL_REGION1_END 0x00017FFF 141#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 142#define BGE_AVAIL_REGION2_END 0x0001FFFF 143#define BGE_EXT_SSRAM 0x00020000 144#define BGE_EXT_SSRAM_END 0x000FFFFF 145* 146 147/* 148 * BCM570x register offsets. These are memory mapped registers 149 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 150 * Each register must be accessed using 32 bit operations. 151 * 152 * All registers are accessed through a 32K shared memory block. 153 * The first group of registers are actually copies of the PCI 154 * configuration space registers. 155 / 156* 157/* 158 * PCI registers defined in the PCI 2.2 spec. 159 / 160#define BGE_PCI_VID 0x00 161#define BGE_PCI_DID 0x02 162#define BGE_PCI_CMD 0x04 163#define BGE_PCI_STS 0x06 164#define BGE_PCI_REV 0x08 165#define BGE_PCI_CLASS 0x09 166#define BGE_PCI_CACHESZ 0x0C 167#define BGE_PCI_LATTIMER 0x0D 168#define BGE_PCI_HDRTYPE 0x0E 169#define BGE_PCI_BIST 0x0F 170#define BGE_PCI_BAR0 0x10 171#define BGE_PCI_BAR1 0x14 172#define BGE_PCI_SUBSYS 0x2C 173#define BGE_PCI_SUBVID 0x2E 174#define BGE_PCI_ROMBASE 0x30 175#define BGE_PCI_CAPPTR 0x34 176#define BGE_PCI_INTLINE 0x3C 177#define BGE_PCI_INTPIN 0x3D 178#define BGE_PCI_MINGNT 0x3E 179#define BGE_PCI_MAXLAT 0x3F 180#define BGE_PCI_PCIXCAP 0x40 181#define BGE_PCI_NEXTPTR_PM 0x41 182#define BGE_PCI_PCIX_CMD 0x42 183#define BGE_PCI_PCIX_STS 0x44 184#define BGE_PCI_PWRMGMT_CAPID 0x48 185#define BGE_PCI_NEXTPTR_VPD 0x49 186#define BGE_PCI_PWRMGMT_CAPS 0x4A 187#define BGE_PCI_PWRMGMT_CMD 0x4C 188#define BGE_PCI_PWRMGMT_STS 0x4D 189#define BGE_PCI_PWRMGMT_DATA 0x4F 190#define BGE_PCI_VPD_CAPID 0x50 191#define BGE_PCI_NEXTPTR_MSI 0x51 192#define BGE_PCI_VPD_ADDR 0x52 193#define BGE_PCI_VPD_DATA 0x54 194#define BGE_PCI_MSI_CAPID 0x58 195#define BGE_PCI_NEXTPTR_NONE 0x59 196#define BGE_PCI_MSI_CTL 0x5A 197#define BGE_PCI_MSI_ADDR_HI 0x5C 198#define BGE_PCI_MSI_ADDR_LO 0x60 199#define BGE_PCI_MSI_DATA 0x64 200* 201/* 202 * PCI Express definitions 203 * According to 204 * PCI Express base specification, REV. 1.0a 205 / 206* 207/* PCI Express device control, 16bits / 208#define BGE_PCIE_DEVCTL 0x08 209#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216* 217/* PCI MSI. ??? / 218#define BGE_PCIE_CAPID_REG 0xD0 219#define BGE_PCIE_CAPID 0x10 220* 221/* 222 * PCI registers specific to the BCM570x family. 223 / 224#define BGE_PCI_MISC_CTL 0x68 225#define BGE_PCI_DMA_RW_CTL 0x6C 226#define BGE_PCI_PCISTATE 0x70 227#define BGE_PCI_CLKCTL 0x74 228#define BGE_PCI_REG_BASEADDR 0x78 229#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230#define BGE_PCI_REG_DATA 0x80 231#define BGE_PCI_MEMWIN_DATA 0x84 232#define BGE_PCI_MODECTL 0x88 233#define BGE_PCI_MISC_CFG 0x8C 234#define BGE_PCI_MISC_LOCALCTL 0x90 235#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241#define BGE_PCI_ISR_MBX_HI 0xB0 242#define BGE_PCI_ISR_MBX_LO 0xB4 243#define BGE_PCI_PRODID_ASICREV 0xBC 244#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 246* 247/* PCI Misc. Host control register / 248#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259* 260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 261 262#define BGE_INIT \ 263 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 264 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 265 266#define BGE_CHIPID_TIGON_I 0x4000 267#define BGE_CHIPID_TIGON_II 0x6000 268#define BGE_CHIPID_BCM5700_A0 0x7000 269#define BGE_CHIPID_BCM5700_A1 0x7001 270#define BGE_CHIPID_BCM5700_B0 0x7100 271#define BGE_CHIPID_BCM5700_B1 0x7101 272#define BGE_CHIPID_BCM5700_B2 0x7102 273#define BGE_CHIPID_BCM5700_B3 0x7103 274#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275#define BGE_CHIPID_BCM5700_C0 0x7200 276#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 277#define BGE_CHIPID_BCM5701_B0 0x0100 278#define BGE_CHIPID_BCM5701_B2 0x0102 279#define BGE_CHIPID_BCM5701_B5 0x0105 280#define BGE_CHIPID_BCM5703_A0 0x1000 281#define BGE_CHIPID_BCM5703_A1 0x1001 282#define BGE_CHIPID_BCM5703_A2 0x1002 283#define BGE_CHIPID_BCM5703_A3 0x1003 284#define BGE_CHIPID_BCM5703_B0 0x1100 285#define BGE_CHIPID_BCM5704_A0 0x2000 286#define BGE_CHIPID_BCM5704_A1 0x2001 287#define BGE_CHIPID_BCM5704_A2 0x2002 288#define BGE_CHIPID_BCM5704_A3 0x2003 289#define BGE_CHIPID_BCM5704_B0 0x2100 290#define BGE_CHIPID_BCM5705_A0 0x3000 291#define BGE_CHIPID_BCM5705_A1 0x3001 292#define BGE_CHIPID_BCM5705_A2 0x3002 293#define BGE_CHIPID_BCM5705_A3 0x3003 294#define BGE_CHIPID_BCM5750_A0 0x4000 295#define BGE_CHIPID_BCM5750_A1 0x4001 296#define BGE_CHIPID_BCM5750_A3 0x4000 297#define BGE_CHIPID_BCM5750_B0 0x4100 298#define BGE_CHIPID_BCM5750_B1 0x4101 299#define BGE_CHIPID_BCM5750_C0 0x4200 300#define BGE_CHIPID_BCM5750_C1 0x4201 301#define BGE_CHIPID_BCM5750_C2 0x4202 302#define BGE_CHIPID_BCM5714_A0 0x5000 303#define BGE_CHIPID_BCM5752_A0 0x6000 304#define BGE_CHIPID_BCM5752_A1 0x6001 305#define BGE_CHIPID_BCM5752_A2 0x6002 306#define BGE_CHIPID_BCM5714_B0 0x8000 307#define BGE_CHIPID_BCM5714_B3 0x8003 308#define BGE_CHIPID_BCM5715_A0 0x9000 309#define BGE_CHIPID_BCM5715_A1 0x9001 310#define BGE_CHIPID_BCM5715_A3 0x9003 311#define BGE_CHIPID_BCM5755_A0 0xa000 312#define BGE_CHIPID_BCM5755_A1 0xa001 313#define BGE_CHIPID_BCM5755_A2 0xa002 314#define BGE_CHIPID_BCM5722_A0 0xa200 315#define BGE_CHIPID_BCM5754_A0 0xb000 316#define BGE_CHIPID_BCM5754_A1 0xb001 317#define BGE_CHIPID_BCM5754_A2 0xb002 318#define BGE_CHIPID_BCM5761_A0 0x5761000 319#define BGE_CHIPID_BCM5761_A1 0x5761100 320#define BGE_CHIPID_BCM5784_A0 0x5784000 321#define BGE_CHIPID_BCM5784_A1 0x5784100 322#define BGE_CHIPID_BCM5787_A0 0xb000 323#define BGE_CHIPID_BCM5787_A1 0xb001 324#define BGE_CHIPID_BCM5787_A2 0xb002 325#define BGE_CHIPID_BCM5906_A0 0xc000 326#define BGE_CHIPID_BCM5906_A1 0xc001 327#define BGE_CHIPID_BCM5906_A2 0xc002 328#define BGE_CHIPID_BCM57780_A0 0x57780000 329#define BGE_CHIPID_BCM57780_A1 0x57780001 330#define BGE_CHIPID_BCM5717_A0 0x05717000 331#define BGE_CHIPID_BCM5717_B0 0x05717100 332#define BGE_CHIPID_BCM5719_A0 0x05719000 333#define BGE_CHIPID_BCM5720_A0 0x05720000 334#define BGE_CHIPID_BCM57765_A0 0x57785000 335#define BGE_CHIPID_BCM57765_B0 0x57785100 336* 337/* shorthand one / 338#define BGE_ASICREV(x) ((x) >> 12) 339#define BGE_ASICREV_BCM5701 0x00 340#define BGE_ASICREV_BCM5703 0x01 341#define BGE_ASICREV_BCM5704 0x02 342#define BGE_ASICREV_BCM5705 0x03 343#define BGE_ASICREV_BCM5750 0x04 344#define BGE_ASICREV_BCM5714_A0 0x05 345#define BGE_ASICREV_BCM5752 0x06 346#define BGE_ASICREV_BCM5700 0x07 347#define BGE_ASICREV_BCM5780 0x08 348#define BGE_ASICREV_BCM5714 0x09 349#define BGE_ASICREV_BCM5755 0x0a 350#define BGE_ASICREV_BCM5754 0x0b 351#define BGE_ASICREV_BCM5787 0x0b 352#define BGE_ASICREV_BCM5906 0x0c 353/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 354#define BGE_ASICREV_USE_PRODID_REG 0x0f 355/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 356#define BGE_ASICREV_BCM5717 0x5717 357#define BGE_ASICREV_BCM5719 0x5719 358#define BGE_ASICREV_BCM5720 0x5720 359#define BGE_ASICREV_BCM5761 0x5761 360#define BGE_ASICREV_BCM5784 0x5784 361#define BGE_ASICREV_BCM5785 0x5785 362#define BGE_ASICREV_BCM57765 0x57785 363#define BGE_ASICREV_BCM57766 0x57766 364#define BGE_ASICREV_BCM57780 0x57780 365* 366/* chip revisions / 367#define BGE_CHIPREV(x) ((x) >> 8) 368#define BGE_CHIPREV_5700_AX 0x70 369#define BGE_CHIPREV_5700_BX 0x71 370#define BGE_CHIPREV_5700_CX 0x72 371#define BGE_CHIPREV_5701_AX 0x00 372#define BGE_CHIPREV_5703_AX 0x10 373#define BGE_CHIPREV_5704_AX 0x20 374#define BGE_CHIPREV_5704_BX 0x21 375#define BGE_CHIPREV_5750_AX 0x40 376#define BGE_CHIPREV_5750_BX 0x41 377/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 378#define BGE_CHIPREV_5717_AX 0x57170 379#define BGE_CHIPREV_5717_BX 0x57171 380*#define BGE_CHIPREV_5761_AX 0x57611	34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SRAM_FW_MB 0x00000B50 75#define BGE_SRAM_DATA_SIG 0x00000B54 76#define BGE_SRAM_DATA_CFG 0x00000B58 77#define BGE_SRAM_FW_CMD_MB 0x00000B78 78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C 79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80 80#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04 81#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14 82#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18 83#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 84#define BGE_UNMAPPED 0x00001000 85#define BGE_UNMAPPED_END 0x00001FFF 86#define BGE_DMA_DESCRIPTORS 0x00002000 87#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 88#define BGE_SEND_RING_5717 0x00004000 89#define BGE_SEND_RING_1_TO_4 0x00004000 90#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 91 92/ Firmware interface / 93#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 / 'KevT' / 94 95#define BGE_FW_CMD_DRV_ALIVE 0x00000001 96#define BGE_FW_CMD_PAUSE 0x00000002 97#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003 98#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004 99#define BGE_FW_CMD_LINK_UPDATE 0x0000000C 100#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D 101#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E 102* 103#define BGE_FW_HB_TIMEOUT_SEC 3 104 105#define BGE_FW_DRV_STATE_START 0x00000001 106#define BGE_FW_DRV_STATE_START_DONE 0x80000001 107#define BGE_FW_DRV_STATE_UNLOAD 0x00000002 108#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002 109#define BGE_FW_DRV_STATE_WOL 0x00000003 110#define BGE_FW_DRV_STATE_SUSPEND 0x00000004 111 112/* Mappings for internal memory configuration / 113#define BGE_STD_RX_RINGS 0x00006000 114#define BGE_STD_RX_RINGS_END 0x00006FFF 115#define BGE_JUMBO_RX_RINGS 0x00007000 116#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 117#define BGE_BUFFPOOL_1 0x00008000 118#define BGE_BUFFPOOL_1_END 0x0000FFFF 119#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 120#define BGE_BUFFPOOL_2_END 0x00017FFF 121#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 122#define BGE_BUFFPOOL_3_END 0x0001FFFF 123#define BGE_STD_RX_RINGS_5717 0x00040000 124#define BGE_JUMBO_RX_RINGS_5717 0x00044400 125* 126/* Mappings for external SSRAM configurations / 127#define BGE_SEND_RING_5_TO_6 0x00006000 128#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 129#define BGE_SEND_RING_7_TO_8 0x00007000 130#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 131#define BGE_SEND_RING_9_TO_16 0x00008000 132#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 133#define BGE_EXT_STD_RX_RINGS 0x0000C000 134#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 135#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 136#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 137#define BGE_MINI_RX_RINGS 0x0000E000 138#define BGE_MINI_RX_RINGS_END 0x0000FFFF 139#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 140#define BGE_AVAIL_REGION1_END 0x00017FFF 141#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 142#define BGE_AVAIL_REGION2_END 0x0001FFFF 143#define BGE_EXT_SSRAM 0x00020000 144#define BGE_EXT_SSRAM_END 0x000FFFFF 145* 146 147/* 148 * BCM570x register offsets. These are memory mapped registers 149 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 150 * Each register must be accessed using 32 bit operations. 151 * 152 * All registers are accessed through a 32K shared memory block. 153 * The first group of registers are actually copies of the PCI 154 * configuration space registers. 155 / 156* 157/* 158 * PCI registers defined in the PCI 2.2 spec. 159 / 160#define BGE_PCI_VID 0x00 161#define BGE_PCI_DID 0x02 162#define BGE_PCI_CMD 0x04 163#define BGE_PCI_STS 0x06 164#define BGE_PCI_REV 0x08 165#define BGE_PCI_CLASS 0x09 166#define BGE_PCI_CACHESZ 0x0C 167#define BGE_PCI_LATTIMER 0x0D 168#define BGE_PCI_HDRTYPE 0x0E 169#define BGE_PCI_BIST 0x0F 170#define BGE_PCI_BAR0 0x10 171#define BGE_PCI_BAR1 0x14 172#define BGE_PCI_SUBSYS 0x2C 173#define BGE_PCI_SUBVID 0x2E 174#define BGE_PCI_ROMBASE 0x30 175#define BGE_PCI_CAPPTR 0x34 176#define BGE_PCI_INTLINE 0x3C 177#define BGE_PCI_INTPIN 0x3D 178#define BGE_PCI_MINGNT 0x3E 179#define BGE_PCI_MAXLAT 0x3F 180#define BGE_PCI_PCIXCAP 0x40 181#define BGE_PCI_NEXTPTR_PM 0x41 182#define BGE_PCI_PCIX_CMD 0x42 183#define BGE_PCI_PCIX_STS 0x44 184#define BGE_PCI_PWRMGMT_CAPID 0x48 185#define BGE_PCI_NEXTPTR_VPD 0x49 186#define BGE_PCI_PWRMGMT_CAPS 0x4A 187#define BGE_PCI_PWRMGMT_CMD 0x4C 188#define BGE_PCI_PWRMGMT_STS 0x4D 189#define BGE_PCI_PWRMGMT_DATA 0x4F 190#define BGE_PCI_VPD_CAPID 0x50 191#define BGE_PCI_NEXTPTR_MSI 0x51 192#define BGE_PCI_VPD_ADDR 0x52 193#define BGE_PCI_VPD_DATA 0x54 194#define BGE_PCI_MSI_CAPID 0x58 195#define BGE_PCI_NEXTPTR_NONE 0x59 196#define BGE_PCI_MSI_CTL 0x5A 197#define BGE_PCI_MSI_ADDR_HI 0x5C 198#define BGE_PCI_MSI_ADDR_LO 0x60 199#define BGE_PCI_MSI_DATA 0x64 200* 201/* 202 * PCI Express definitions 203 * According to 204 * PCI Express base specification, REV. 1.0a 205 / 206* 207/* PCI Express device control, 16bits / 208#define BGE_PCIE_DEVCTL 0x08 209#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 210#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 211#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 212#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 213#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 214#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 215#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 216* 217/* PCI MSI. ??? / 218#define BGE_PCIE_CAPID_REG 0xD0 219#define BGE_PCIE_CAPID 0x10 220* 221/* 222 * PCI registers specific to the BCM570x family. 223 / 224#define BGE_PCI_MISC_CTL 0x68 225#define BGE_PCI_DMA_RW_CTL 0x6C 226#define BGE_PCI_PCISTATE 0x70 227#define BGE_PCI_CLKCTL 0x74 228#define BGE_PCI_REG_BASEADDR 0x78 229#define BGE_PCI_MEMWIN_BASEADDR 0x7C 230#define BGE_PCI_REG_DATA 0x80 231#define BGE_PCI_MEMWIN_DATA 0x84 232#define BGE_PCI_MODECTL 0x88 233#define BGE_PCI_MISC_CFG 0x8C 234#define BGE_PCI_MISC_LOCALCTL 0x90 235#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 236#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 237#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 238#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 239#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 240#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 241#define BGE_PCI_ISR_MBX_HI 0xB0 242#define BGE_PCI_ISR_MBX_LO 0xB4 243#define BGE_PCI_PRODID_ASICREV 0xBC 244#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4 245#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC 246* 247/* PCI Misc. Host control register / 248#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 249#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 250#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 251#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 252#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200 257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 259* 260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 261 262#define BGE_INIT \ 263 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 264 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 265 266#define BGE_CHIPID_TIGON_I 0x4000 267#define BGE_CHIPID_TIGON_II 0x6000 268#define BGE_CHIPID_BCM5700_A0 0x7000 269#define BGE_CHIPID_BCM5700_A1 0x7001 270#define BGE_CHIPID_BCM5700_B0 0x7100 271#define BGE_CHIPID_BCM5700_B1 0x7101 272#define BGE_CHIPID_BCM5700_B2 0x7102 273#define BGE_CHIPID_BCM5700_B3 0x7103 274#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 275#define BGE_CHIPID_BCM5700_C0 0x7200 276#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 277#define BGE_CHIPID_BCM5701_B0 0x0100 278#define BGE_CHIPID_BCM5701_B2 0x0102 279#define BGE_CHIPID_BCM5701_B5 0x0105 280#define BGE_CHIPID_BCM5703_A0 0x1000 281#define BGE_CHIPID_BCM5703_A1 0x1001 282#define BGE_CHIPID_BCM5703_A2 0x1002 283#define BGE_CHIPID_BCM5703_A3 0x1003 284#define BGE_CHIPID_BCM5703_B0 0x1100 285#define BGE_CHIPID_BCM5704_A0 0x2000 286#define BGE_CHIPID_BCM5704_A1 0x2001 287#define BGE_CHIPID_BCM5704_A2 0x2002 288#define BGE_CHIPID_BCM5704_A3 0x2003 289#define BGE_CHIPID_BCM5704_B0 0x2100 290#define BGE_CHIPID_BCM5705_A0 0x3000 291#define BGE_CHIPID_BCM5705_A1 0x3001 292#define BGE_CHIPID_BCM5705_A2 0x3002 293#define BGE_CHIPID_BCM5705_A3 0x3003 294#define BGE_CHIPID_BCM5750_A0 0x4000 295#define BGE_CHIPID_BCM5750_A1 0x4001 296#define BGE_CHIPID_BCM5750_A3 0x4000 297#define BGE_CHIPID_BCM5750_B0 0x4100 298#define BGE_CHIPID_BCM5750_B1 0x4101 299#define BGE_CHIPID_BCM5750_C0 0x4200 300#define BGE_CHIPID_BCM5750_C1 0x4201 301#define BGE_CHIPID_BCM5750_C2 0x4202 302#define BGE_CHIPID_BCM5714_A0 0x5000 303#define BGE_CHIPID_BCM5752_A0 0x6000 304#define BGE_CHIPID_BCM5752_A1 0x6001 305#define BGE_CHIPID_BCM5752_A2 0x6002 306#define BGE_CHIPID_BCM5714_B0 0x8000 307#define BGE_CHIPID_BCM5714_B3 0x8003 308#define BGE_CHIPID_BCM5715_A0 0x9000 309#define BGE_CHIPID_BCM5715_A1 0x9001 310#define BGE_CHIPID_BCM5715_A3 0x9003 311#define BGE_CHIPID_BCM5755_A0 0xa000 312#define BGE_CHIPID_BCM5755_A1 0xa001 313#define BGE_CHIPID_BCM5755_A2 0xa002 314#define BGE_CHIPID_BCM5722_A0 0xa200 315#define BGE_CHIPID_BCM5754_A0 0xb000 316#define BGE_CHIPID_BCM5754_A1 0xb001 317#define BGE_CHIPID_BCM5754_A2 0xb002 318#define BGE_CHIPID_BCM5761_A0 0x5761000 319#define BGE_CHIPID_BCM5761_A1 0x5761100 320#define BGE_CHIPID_BCM5784_A0 0x5784000 321#define BGE_CHIPID_BCM5784_A1 0x5784100 322#define BGE_CHIPID_BCM5787_A0 0xb000 323#define BGE_CHIPID_BCM5787_A1 0xb001 324#define BGE_CHIPID_BCM5787_A2 0xb002 325#define BGE_CHIPID_BCM5906_A0 0xc000 326#define BGE_CHIPID_BCM5906_A1 0xc001 327#define BGE_CHIPID_BCM5906_A2 0xc002 328#define BGE_CHIPID_BCM57780_A0 0x57780000 329#define BGE_CHIPID_BCM57780_A1 0x57780001 330#define BGE_CHIPID_BCM5717_A0 0x05717000 331#define BGE_CHIPID_BCM5717_B0 0x05717100 332#define BGE_CHIPID_BCM5719_A0 0x05719000 333#define BGE_CHIPID_BCM5720_A0 0x05720000 334#define BGE_CHIPID_BCM57765_A0 0x57785000 335#define BGE_CHIPID_BCM57765_B0 0x57785100 336* 337/* shorthand one / 338#define BGE_ASICREV(x) ((x) >> 12) 339#define BGE_ASICREV_BCM5701 0x00 340#define BGE_ASICREV_BCM5703 0x01 341#define BGE_ASICREV_BCM5704 0x02 342#define BGE_ASICREV_BCM5705 0x03 343#define BGE_ASICREV_BCM5750 0x04 344#define BGE_ASICREV_BCM5714_A0 0x05 345#define BGE_ASICREV_BCM5752 0x06 346#define BGE_ASICREV_BCM5700 0x07 347#define BGE_ASICREV_BCM5780 0x08 348#define BGE_ASICREV_BCM5714 0x09 349#define BGE_ASICREV_BCM5755 0x0a 350#define BGE_ASICREV_BCM5754 0x0b 351#define BGE_ASICREV_BCM5787 0x0b 352#define BGE_ASICREV_BCM5906 0x0c 353/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 354#define BGE_ASICREV_USE_PRODID_REG 0x0f 355/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 356#define BGE_ASICREV_BCM5717 0x5717 357#define BGE_ASICREV_BCM5719 0x5719 358#define BGE_ASICREV_BCM5720 0x5720 359#define BGE_ASICREV_BCM5761 0x5761 360#define BGE_ASICREV_BCM5784 0x5784 361#define BGE_ASICREV_BCM5785 0x5785 362#define BGE_ASICREV_BCM57765 0x57785 363#define BGE_ASICREV_BCM57766 0x57766 364#define BGE_ASICREV_BCM57780 0x57780 365* 366/* chip revisions / 367#define BGE_CHIPREV(x) ((x) >> 8) 368#define BGE_CHIPREV_5700_AX 0x70 369#define BGE_CHIPREV_5700_BX 0x71 370#define BGE_CHIPREV_5700_CX 0x72 371#define BGE_CHIPREV_5701_AX 0x00 372#define BGE_CHIPREV_5703_AX 0x10 373#define BGE_CHIPREV_5704_AX 0x20 374#define BGE_CHIPREV_5704_BX 0x21 375#define BGE_CHIPREV_5750_AX 0x40 376#define BGE_CHIPREV_5750_BX 0x41 377/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 378#define BGE_CHIPREV_5717_AX 0x57170 379#define BGE_CHIPREV_5717_BX 0x57171 380*#define BGE_CHIPREV_5761_AX 0x57611
	381#define BGE_CHIPREV_57765_AX 0x577850
381#define BGE_CHIPREV_5784_AX 0x57841 382 383/* PCI DMA Read/Write Control register / 384#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 385#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 386#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 387#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 388#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 389#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 390#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 391#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 392#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 393#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 394#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 395#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 396#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 397* 398#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 399#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 400#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 401#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 402 403#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 404#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 405 406#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 407#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 408#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 409#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 410#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 411#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 412#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 413#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 414 415#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 416#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 417#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 418#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 419#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 420#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 421#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 422#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 423 424/* 425 * PCI state register -- note, this register is read only 426 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 427 * register is set. 428 / 429#define BGE_PCISTATE_FORCE_RESET 0x00000001 430#define BGE_PCISTATE_INTR_STATE 0x00000002 431#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 432#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 433#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 434#define BGE_PCISTATE_ROM_ENABLE 0x00000020 435#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 436#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 437#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 438#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 439#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 440#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 441#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 442* 443/* 444 * PCI Clock Control register -- note, this register is read only 445 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 446 * register is set. 447 / 448#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 449#define BGE_PCICLOCKCTL_M66EN 0x00000080 450#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 451#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 452#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 453#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 454#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 455#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 456#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 457#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 458* 459 460#ifndef PCIM_CMD_MWIEN 461#define PCIM_CMD_MWIEN 0x0010 462#endif 463#ifndef PCIM_CMD_INTxDIS 464#define PCIM_CMD_INTxDIS 0x0400 465#endif 466 467/* BAR0 (MAC) Register Definitions / 468* 469/* 470 * High priority mailbox registers 471 * Each mailbox is 64-bits wide, though we only use the 472 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 473 * first. The NIC will load the mailbox after the lower 32 bit word 474 * has been updated. 475 / 476#define BGE_MBX_IRQ0_HI 0x0200 477#define BGE_MBX_IRQ0_LO 0x0204 478#define BGE_MBX_IRQ1_HI 0x0208 479#define BGE_MBX_IRQ1_LO 0x020C 480#define BGE_MBX_IRQ2_HI 0x0210 481#define BGE_MBX_IRQ2_LO 0x0214 482#define BGE_MBX_IRQ3_HI 0x0218 483#define BGE_MBX_IRQ3_LO 0x021C 484#define BGE_MBX_GEN0_HI 0x0220 485#define BGE_MBX_GEN0_LO 0x0224 486#define BGE_MBX_GEN1_HI 0x0228 487#define BGE_MBX_GEN1_LO 0x022C 488#define BGE_MBX_GEN2_HI 0x0230 489#define BGE_MBX_GEN2_LO 0x0234 490#define BGE_MBX_GEN3_HI 0x0228 491#define BGE_MBX_GEN3_LO 0x022C 492#define BGE_MBX_GEN4_HI 0x0240 493#define BGE_MBX_GEN4_LO 0x0244 494#define BGE_MBX_GEN5_HI 0x0248 495#define BGE_MBX_GEN5_LO 0x024C 496#define BGE_MBX_GEN6_HI 0x0250 497#define BGE_MBX_GEN6_LO 0x0254 498#define BGE_MBX_GEN7_HI 0x0258 499#define BGE_MBX_GEN7_LO 0x025C 500#define BGE_MBX_RELOAD_STATS_HI 0x0260 501#define BGE_MBX_RELOAD_STATS_LO 0x0264 502#define BGE_MBX_RX_STD_PROD_HI 0x0268 503#define BGE_MBX_RX_STD_PROD_LO 0x026C 504#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 505#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 506#define BGE_MBX_RX_MINI_PROD_HI 0x0278 507#define BGE_MBX_RX_MINI_PROD_LO 0x027C 508#define BGE_MBX_RX_CONS0_HI 0x0280 509#define BGE_MBX_RX_CONS0_LO 0x0284 510#define BGE_MBX_RX_CONS1_HI 0x0288 511#define BGE_MBX_RX_CONS1_LO 0x028C 512#define BGE_MBX_RX_CONS2_HI 0x0290 513#define BGE_MBX_RX_CONS2_LO 0x0294 514#define BGE_MBX_RX_CONS3_HI 0x0298 515#define BGE_MBX_RX_CONS3_LO 0x029C 516#define BGE_MBX_RX_CONS4_HI 0x02A0 517#define BGE_MBX_RX_CONS4_LO 0x02A4 518#define BGE_MBX_RX_CONS5_HI 0x02A8 519#define BGE_MBX_RX_CONS5_LO 0x02AC 520#define BGE_MBX_RX_CONS6_HI 0x02B0 521#define BGE_MBX_RX_CONS6_LO 0x02B4 522#define BGE_MBX_RX_CONS7_HI 0x02B8 523#define BGE_MBX_RX_CONS7_LO 0x02BC 524#define BGE_MBX_RX_CONS8_HI 0x02C0 525#define BGE_MBX_RX_CONS8_LO 0x02C4 526#define BGE_MBX_RX_CONS9_HI 0x02C8 527#define BGE_MBX_RX_CONS9_LO 0x02CC 528#define BGE_MBX_RX_CONS10_HI 0x02D0 529#define BGE_MBX_RX_CONS10_LO 0x02D4 530#define BGE_MBX_RX_CONS11_HI 0x02D8 531#define BGE_MBX_RX_CONS11_LO 0x02DC 532#define BGE_MBX_RX_CONS12_HI 0x02E0 533#define BGE_MBX_RX_CONS12_LO 0x02E4 534#define BGE_MBX_RX_CONS13_HI 0x02E8 535#define BGE_MBX_RX_CONS13_LO 0x02EC 536#define BGE_MBX_RX_CONS14_HI 0x02F0 537#define BGE_MBX_RX_CONS14_LO 0x02F4 538#define BGE_MBX_RX_CONS15_HI 0x02F8 539#define BGE_MBX_RX_CONS15_LO 0x02FC 540#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 541#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 542#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 543#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 544#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 545#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 546#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 547#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 548#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 549#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 550#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 551#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 552#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 553#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 554#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 555#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 556#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 557#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 558#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 559#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 560#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 561#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 562#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 563#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 564#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 565#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 566#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 567#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 568#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 569#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 570#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 571#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 572#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 573#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 574#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 575#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 576#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 577#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 578#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 579#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 580#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 581#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 582#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 583#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 584#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 585#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 586#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 587#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 588#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 589#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 590#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 591#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 592#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 593#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 594#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 595#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 596#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 597#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 598#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 599#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 600#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 601#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 602#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 603#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 604* 605#define BGE_TX_RINGS_MAX 4 606#define BGE_TX_RINGS_EXTSSRAM_MAX 16 607#define BGE_RX_RINGS_MAX 16 608#define BGE_RX_RINGS_MAX_5717 17 609 610/* Ethernet MAC control registers / 611#define BGE_MAC_MODE 0x0400 612#define BGE_MAC_STS 0x0404 613#define BGE_MAC_EVT_ENB 0x0408 614#define BGE_MAC_LED_CTL 0x040C 615#define BGE_MAC_ADDR1_LO 0x0410 616#define BGE_MAC_ADDR1_HI 0x0414 617#define BGE_MAC_ADDR2_LO 0x0418 618#define BGE_MAC_ADDR2_HI 0x041C 619#define BGE_MAC_ADDR3_LO 0x0420 620#define BGE_MAC_ADDR3_HI 0x0424 621#define BGE_MAC_ADDR4_LO 0x0428 622#define BGE_MAC_ADDR4_HI 0x042C 623#define BGE_WOL_PATPTR 0x0430 624#define BGE_WOL_PATCFG 0x0434 625#define BGE_TX_RANDOM_BACKOFF 0x0438 626#define BGE_RX_MTU 0x043C 627#define BGE_GBIT_PCS_TEST 0x0440 628#define BGE_TX_TBI_AUTONEG 0x0444 629#define BGE_RX_TBI_AUTONEG 0x0448 630#define BGE_MI_COMM 0x044C 631#define BGE_MI_STS 0x0450 632#define BGE_MI_MODE 0x0454 633#define BGE_AUTOPOLL_STS 0x0458 634#define BGE_TX_MODE 0x045C 635#define BGE_TX_STS 0x0460 636#define BGE_TX_LENGTHS 0x0464 637#define BGE_RX_MODE 0x0468 638#define BGE_RX_STS 0x046C 639#define BGE_MAR0 0x0470 640#define BGE_MAR1 0x0474 641#define BGE_MAR2 0x0478 642#define BGE_MAR3 0x047C 643#define BGE_RX_BD_RULES_CTL0 0x0480 644#define BGE_RX_BD_RULES_MASKVAL0 0x0484 645#define BGE_RX_BD_RULES_CTL1 0x0488 646#define BGE_RX_BD_RULES_MASKVAL1 0x048C 647#define BGE_RX_BD_RULES_CTL2 0x0490 648#define BGE_RX_BD_RULES_MASKVAL2 0x0494 649#define BGE_RX_BD_RULES_CTL3 0x0498 650#define BGE_RX_BD_RULES_MASKVAL3 0x049C 651#define BGE_RX_BD_RULES_CTL4 0x04A0 652#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 653#define BGE_RX_BD_RULES_CTL5 0x04A8 654#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 655#define BGE_RX_BD_RULES_CTL6 0x04B0 656#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 657#define BGE_RX_BD_RULES_CTL7 0x04B8 658#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 659#define BGE_RX_BD_RULES_CTL8 0x04C0 660#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 661#define BGE_RX_BD_RULES_CTL9 0x04C8 662#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 663#define BGE_RX_BD_RULES_CTL10 0x04D0 664#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 665#define BGE_RX_BD_RULES_CTL11 0x04D8 666#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 667#define BGE_RX_BD_RULES_CTL12 0x04E0 668#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 669#define BGE_RX_BD_RULES_CTL13 0x04E8 670#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 671#define BGE_RX_BD_RULES_CTL14 0x04F0 672#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 673#define BGE_RX_BD_RULES_CTL15 0x04F8 674#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 675#define BGE_RX_RULES_CFG 0x0500 676#define BGE_MAX_RX_FRAME_LOWAT 0x0504 677#define BGE_SERDES_CFG 0x0590 678#define BGE_SERDES_STS 0x0594 679#define BGE_SGDIG_CFG 0x05B0 680#define BGE_SGDIG_STS 0x05B4 681#define BGE_TX_MAC_STATS_OCTETS 0x0800 682#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 683#define BGE_TX_MAC_STATS_COLLS 0x0808 684#define BGE_TX_MAC_STATS_XON_SENT 0x080C 685#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 686#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 687#define BGE_TX_MAC_STATS_ERRORS 0x0818 688#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 689#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 690#define BGE_TX_MAC_STATS_DEFERRED 0x0824 691#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 692#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 693#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 694#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 695#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 696#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 697#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 698#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 699#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 700#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 701#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 702#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 703#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 704#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 705#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 706#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 707#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 708#define BGE_TX_MAC_STATS_UCAST 0x086C 709#define BGE_TX_MAC_STATS_MCAST 0x0870 710#define BGE_TX_MAC_STATS_BCAST 0x0874 711#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 712#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 713#define BGE_RX_MAC_STATS_OCTESTS 0x0880 714#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 715#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 716#define BGE_RX_MAC_STATS_UCAST 0x088C 717#define BGE_RX_MAC_STATS_MCAST 0x0890 718#define BGE_RX_MAC_STATS_BCAST 0x0894 719#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 720#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 721#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 722#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 723#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 724#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 725#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 726#define BGE_RX_MAC_STATS_JABBERS 0x08B4 727#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 728* 729/* Ethernet MAC Mode register / 730#define BGE_MACMODE_RESET 0x00000001 731#define BGE_MACMODE_HALF_DUPLEX 0x00000002 732#define BGE_MACMODE_PORTMODE 0x0000000C 733#define BGE_MACMODE_LOOPBACK 0x00000010 734#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 735#define BGE_MACMODE_TX_BURST_ENB 0x00000100 736#define BGE_MACMODE_MAX_DEFER 0x00000200 737#define BGE_MACMODE_LINK_POLARITY 0x00000400 738#define BGE_MACMODE_RX_STATS_ENB 0x00000800 739#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 740#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 741#define BGE_MACMODE_TX_STATS_ENB 0x00004000 742#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 743#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 744#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 745#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 746#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 747#define BGE_MACMODE_MIP_ENB 0x00100000 748#define BGE_MACMODE_TXDMA_ENB 0x00200000 749#define BGE_MACMODE_RXDMA_ENB 0x00400000 750#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 751#define BGE_MACMODE_APE_RX_EN 0x08000000 752#define BGE_MACMODE_APE_TX_EN 0x10000000 753* 754#define BGE_PORTMODE_NONE 0x00000000 755#define BGE_PORTMODE_MII 0x00000004 756#define BGE_PORTMODE_GMII 0x00000008 757#define BGE_PORTMODE_TBI 0x0000000C 758 759/* MAC Status register / 760#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 761#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 762#define BGE_MACSTAT_RX_CFG 0x00000004 763#define BGE_MACSTAT_CFG_CHANGED 0x00000008 764#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 765#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 766#define BGE_MACSTAT_LINK_CHANGED 0x00001000 767#define BGE_MACSTAT_MI_COMPLETE 0x00400000 768#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 769#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 770#define BGE_MACSTAT_ODI_ERROR 0x02000000 771#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 772#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 773* 774/* MAC Event Enable Register / 775#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 776#define BGE_EVTENB_LINK_CHANGED 0x00001000 777#define BGE_EVTENB_MI_COMPLETE 0x00400000 778#define BGE_EVTENB_MI_INTERRUPT 0x00800000 779#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 780#define BGE_EVTENB_ODI_ERROR 0x02000000 781#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 782#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 783* 784/* LED Control Register / 785#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 786#define BGE_LEDCTL_1000MBPS_LED 0x00000002 787#define BGE_LEDCTL_100MBPS_LED 0x00000004 788#define BGE_LEDCTL_10MBPS_LED 0x00000008 789#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 790#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 791#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 792#define BGE_LEDCTL_1000MBPS_STS 0x00000080 793#define BGE_LEDCTL_100MBPS_STS 0x00000100 794#define BGE_LEDCTL_10MBPS_STS 0x00000200 795#define BGE_LEDCTL_TRAFLED_STS 0x00000400 796#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 797#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 798* 799/* TX backoff seed register / 800#define BGE_TX_BACKOFF_SEED_MASK 0x3FF 801* 802/* Autopoll status register / 803#define BGE_AUTOPOLLSTS_ERROR 0x00000001 804* 805/* Transmit MAC mode register / 806#define BGE_TXMODE_RESET 0x00000001 807#define BGE_TXMODE_ENABLE 0x00000002 808#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 809#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 810#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 811#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 812#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 813#define BGE_TXMODE_CNT_DN_MODE 0x00800000 814* 815/* Transmit MAC status register / 816#define BGE_TXSTAT_RX_XOFFED 0x00000001 817#define BGE_TXSTAT_SENT_XOFF 0x00000002 818#define BGE_TXSTAT_SENT_XON 0x00000004 819#define BGE_TXSTAT_LINK_UP 0x00000008 820#define BGE_TXSTAT_ODI_UFLOW 0x00000010 821#define BGE_TXSTAT_ODI_OFLOW 0x00000020 822* 823/* Transmit MAC lengths register / 824#define BGE_TXLEN_SLOTTIME 0x000000FF 825#define BGE_TXLEN_IPG 0x00000F00 826#define BGE_TXLEN_CRS 0x00003000 827#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 828#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 829* 830/* Receive MAC mode register / 831#define BGE_RXMODE_RESET 0x00000001 832#define BGE_RXMODE_ENABLE 0x00000002 833#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 834#define BGE_RXMODE_RX_GIANTS 0x00000020 835#define BGE_RXMODE_RX_RUNTS 0x00000040 836#define BGE_RXMODE_8022_LENCHECK 0x00000080 837#define BGE_RXMODE_RX_PROMISC 0x00000100 838#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 839#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 840#define BGE_RXMODE_IPV6_ENABLE 0x01000000 841* 842/* Receive MAC status register / 843#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 844#define BGE_RXSTAT_RCVD_XOFF 0x00000002 845#define BGE_RXSTAT_RCVD_XON 0x00000004 846* 847/* Receive Rules Control register / 848#define BGE_RXRULECTL_OFFSET 0x000000FF 849#define BGE_RXRULECTL_CLASS 0x00001F00 850#define BGE_RXRULECTL_HDRTYPE 0x0000E000 851#define BGE_RXRULECTL_COMPARE_OP 0x00030000 852#define BGE_RXRULECTL_MAP 0x01000000 853#define BGE_RXRULECTL_DISCARD 0x02000000 854#define BGE_RXRULECTL_MASK 0x04000000 855#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 856#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 857#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 858#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 859* 860/* Receive Rules Mask register / 861#define BGE_RXRULEMASK_VALUE 0x0000FFFF 862#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 863* 864/* SERDES configuration register / 865#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 866#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 867#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 868#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 869#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 870#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 871#define BGE_SERDESCFG_TXMODE 0x00001000 872#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 873#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 874#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 875#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 876#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 877#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 878#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 879#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 880#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 881* 882/* SERDES status register / 883#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 884#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 885* 886/* SGDIG config (not documented) / 887#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 888#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 889#define BGE_SGDIGCFG_SEND 0x40000000 890#define BGE_SGDIGCFG_AUTO 0x80000000 891* 892/* SGDIG status (not documented) / 893#define BGE_SGDIGSTS_DONE 0x00000002 894#define BGE_SGDIGSTS_IS_SERDES 0x00000100 895#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 896#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 897* 898 899/* MI communication register / 900#define BGE_MICOMM_DATA 0x0000FFFF 901#define BGE_MICOMM_REG 0x001F0000 902#define BGE_MICOMM_PHY 0x03E00000 903#define BGE_MICOMM_CMD 0x0C000000 904#define BGE_MICOMM_READFAIL 0x10000000 905#define BGE_MICOMM_BUSY 0x20000000 906* 907#define BGE_MIREG(x) ((x & 0x1F) << 16) 908#define BGE_MIPHY(x) ((x & 0x1F) << 21) 909#define BGE_MICMD_WRITE 0x04000000 910#define BGE_MICMD_READ 0x08000000 911 912/* MI status register / 913#define BGE_MISTS_LINK 0x00000001 914#define BGE_MISTS_10MBPS 0x00000002 915* 916#define BGE_MIMODE_CLK_10MHZ 0x00000001 917#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 918#define BGE_MIMODE_AUTOPOLL 0x00000010 919#define BGE_MIMODE_CLKCNT 0x001F0000 920#define BGE_MIMODE_500KHZ_CONST 0x00008000 921#define BGE_MIMODE_BASE 0x000C0000 922 923 924/* 925 * Send data initiator control registers. 926 / 927#define BGE_SDI_MODE 0x0C00 928#define BGE_SDI_STATUS 0x0C04 929#define BGE_SDI_STATS_CTL 0x0C08 930#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 931#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 932#define BGE_ISO_PKT_TX 0x0C20 933#define BGE_LOCSTATS_COS0 0x0C80 934#define BGE_LOCSTATS_COS1 0x0C84 935#define BGE_LOCSTATS_COS2 0x0C88 936#define BGE_LOCSTATS_COS3 0x0C8C 937#define BGE_LOCSTATS_COS4 0x0C90 938#define BGE_LOCSTATS_COS5 0x0C84 939#define BGE_LOCSTATS_COS6 0x0C98 940#define BGE_LOCSTATS_COS7 0x0C9C 941#define BGE_LOCSTATS_COS8 0x0CA0 942#define BGE_LOCSTATS_COS9 0x0CA4 943#define BGE_LOCSTATS_COS10 0x0CA8 944#define BGE_LOCSTATS_COS11 0x0CAC 945#define BGE_LOCSTATS_COS12 0x0CB0 946#define BGE_LOCSTATS_COS13 0x0CB4 947#define BGE_LOCSTATS_COS14 0x0CB8 948#define BGE_LOCSTATS_COS15 0x0CBC 949#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 950#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 951#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 952#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 953#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 954#define BGE_LOCSTATS_IRQS 0x0CD4 955#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 956#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 957* 958/* Send Data Initiator mode register / 959#define BGE_SDIMODE_RESET 0x00000001 960#define BGE_SDIMODE_ENABLE 0x00000002 961#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 962#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 963* 964/* Send Data Initiator stats register / 965#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 966* 967/* Send Data Initiator stats control register / 968#define BGE_SDISTATSCTL_ENABLE 0x00000001 969#define BGE_SDISTATSCTL_FASTER 0x00000002 970#define BGE_SDISTATSCTL_CLEAR 0x00000004 971#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 972#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 973* 974/* 975 * Send Data Completion Control registers 976 / 977#define BGE_SDC_MODE 0x1000 978#define BGE_SDC_STATUS 0x1004 979* 980/* Send Data completion mode register / 981#define BGE_SDCMODE_RESET 0x00000001 982#define BGE_SDCMODE_ENABLE 0x00000002 983#define BGE_SDCMODE_ATTN 0x00000004 984#define BGE_SDCMODE_CDELAY 0x00000010 985* 986/* Send Data completion status register / 987#define BGE_SDCSTAT_ATTN 0x00000004 988* 989/* 990 * Send BD Ring Selector Control registers 991 / 992#define BGE_SRS_MODE 0x1400 993#define BGE_SRS_STATUS 0x1404 994#define BGE_SRS_HWDIAG 0x1408 995#define BGE_SRS_LOC_NIC_CONS0 0x1440 996#define BGE_SRS_LOC_NIC_CONS1 0x1444 997#define BGE_SRS_LOC_NIC_CONS2 0x1448 998#define BGE_SRS_LOC_NIC_CONS3 0x144C 999#define BGE_SRS_LOC_NIC_CONS4 0x1450 1000#define BGE_SRS_LOC_NIC_CONS5 0x1454 1001#define BGE_SRS_LOC_NIC_CONS6 0x1458 1002#define BGE_SRS_LOC_NIC_CONS7 0x145C 1003#define BGE_SRS_LOC_NIC_CONS8 0x1460 1004#define BGE_SRS_LOC_NIC_CONS9 0x1464 1005#define BGE_SRS_LOC_NIC_CONS10 0x1468 1006#define BGE_SRS_LOC_NIC_CONS11 0x146C 1007#define BGE_SRS_LOC_NIC_CONS12 0x1470 1008#define BGE_SRS_LOC_NIC_CONS13 0x1474 1009#define BGE_SRS_LOC_NIC_CONS14 0x1478 1010#define BGE_SRS_LOC_NIC_CONS15 0x147C 1011* 1012/* Send BD Ring Selector Mode register / 1013#define BGE_SRSMODE_RESET 0x00000001 1014#define BGE_SRSMODE_ENABLE 0x00000002 1015#define BGE_SRSMODE_ATTN 0x00000004 1016* 1017/* Send BD Ring Selector Status register / 1018#define BGE_SRSSTAT_ERROR 0x00000004 1019* 1020/* Send BD Ring Selector HW Diagnostics register / 1021#define BGE_SRSHWDIAG_STATE 0x0000000F 1022#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1023#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1024#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1025* 1026/* 1027 * Send BD Initiator Selector Control registers 1028 / 1029#define BGE_SBDI_MODE 0x1800 1030#define BGE_SBDI_STATUS 0x1804 1031#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1032#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1033#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1034#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1035#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1036#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1037#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1038#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1039#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1040#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1041#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1042#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1043#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1044#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1045#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1046#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1047* 1048/* Send BD Initiator Mode register / 1049#define BGE_SBDIMODE_RESET 0x00000001 1050#define BGE_SBDIMODE_ENABLE 0x00000002 1051#define BGE_SBDIMODE_ATTN 0x00000004 1052* 1053/* Send BD Initiator Status register / 1054#define BGE_SBDISTAT_ERROR 0x00000004 1055* 1056/* 1057 * Send BD Completion Control registers 1058 / 1059#define BGE_SBDC_MODE 0x1C00 1060#define BGE_SBDC_STATUS 0x1C04 1061* 1062/* Send BD Completion Control Mode register / 1063#define BGE_SBDCMODE_RESET 0x00000001 1064#define BGE_SBDCMODE_ENABLE 0x00000002 1065#define BGE_SBDCMODE_ATTN 0x00000004 1066* 1067/* Send BD Completion Control Status register / 1068#define BGE_SBDCSTAT_ATTN 0x00000004 1069* 1070/* 1071 * Receive List Placement Control registers 1072 / 1073#define BGE_RXLP_MODE 0x2000 1074#define BGE_RXLP_STATUS 0x2004 1075#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1076#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1077#define BGE_RXLP_CFG 0x2010 1078#define BGE_RXLP_STATS_CTL 0x2014 1079#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1080#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1081#define BGE_RXLP_HEAD0 0x2100 1082#define BGE_RXLP_TAIL0 0x2104 1083#define BGE_RXLP_COUNT0 0x2108 1084#define BGE_RXLP_HEAD1 0x2110 1085#define BGE_RXLP_TAIL1 0x2114 1086#define BGE_RXLP_COUNT1 0x2118 1087#define BGE_RXLP_HEAD2 0x2120 1088#define BGE_RXLP_TAIL2 0x2124 1089#define BGE_RXLP_COUNT2 0x2128 1090#define BGE_RXLP_HEAD3 0x2130 1091#define BGE_RXLP_TAIL3 0x2134 1092#define BGE_RXLP_COUNT3 0x2138 1093#define BGE_RXLP_HEAD4 0x2140 1094#define BGE_RXLP_TAIL4 0x2144 1095#define BGE_RXLP_COUNT4 0x2148 1096#define BGE_RXLP_HEAD5 0x2150 1097#define BGE_RXLP_TAIL5 0x2154 1098#define BGE_RXLP_COUNT5 0x2158 1099#define BGE_RXLP_HEAD6 0x2160 1100#define BGE_RXLP_TAIL6 0x2164 1101#define BGE_RXLP_COUNT6 0x2168 1102#define BGE_RXLP_HEAD7 0x2170 1103#define BGE_RXLP_TAIL7 0x2174 1104#define BGE_RXLP_COUNT7 0x2178 1105#define BGE_RXLP_HEAD8 0x2180 1106#define BGE_RXLP_TAIL8 0x2184 1107#define BGE_RXLP_COUNT8 0x2188 1108#define BGE_RXLP_HEAD9 0x2190 1109#define BGE_RXLP_TAIL9 0x2194 1110#define BGE_RXLP_COUNT9 0x2198 1111#define BGE_RXLP_HEAD10 0x21A0 1112#define BGE_RXLP_TAIL10 0x21A4 1113#define BGE_RXLP_COUNT10 0x21A8 1114#define BGE_RXLP_HEAD11 0x21B0 1115#define BGE_RXLP_TAIL11 0x21B4 1116#define BGE_RXLP_COUNT11 0x21B8 1117#define BGE_RXLP_HEAD12 0x21C0 1118#define BGE_RXLP_TAIL12 0x21C4 1119#define BGE_RXLP_COUNT12 0x21C8 1120#define BGE_RXLP_HEAD13 0x21D0 1121#define BGE_RXLP_TAIL13 0x21D4 1122#define BGE_RXLP_COUNT13 0x21D8 1123#define BGE_RXLP_HEAD14 0x21E0 1124#define BGE_RXLP_TAIL14 0x21E4 1125#define BGE_RXLP_COUNT14 0x21E8 1126#define BGE_RXLP_HEAD15 0x21F0 1127#define BGE_RXLP_TAIL15 0x21F4 1128#define BGE_RXLP_COUNT15 0x21F8 1129#define BGE_RXLP_LOCSTAT_COS0 0x2200 1130#define BGE_RXLP_LOCSTAT_COS1 0x2204 1131#define BGE_RXLP_LOCSTAT_COS2 0x2208 1132#define BGE_RXLP_LOCSTAT_COS3 0x220C 1133#define BGE_RXLP_LOCSTAT_COS4 0x2210 1134#define BGE_RXLP_LOCSTAT_COS5 0x2214 1135#define BGE_RXLP_LOCSTAT_COS6 0x2218 1136#define BGE_RXLP_LOCSTAT_COS7 0x221C 1137#define BGE_RXLP_LOCSTAT_COS8 0x2220 1138#define BGE_RXLP_LOCSTAT_COS9 0x2224 1139#define BGE_RXLP_LOCSTAT_COS10 0x2228 1140#define BGE_RXLP_LOCSTAT_COS11 0x222C 1141#define BGE_RXLP_LOCSTAT_COS12 0x2230 1142#define BGE_RXLP_LOCSTAT_COS13 0x2234 1143#define BGE_RXLP_LOCSTAT_COS14 0x2238 1144#define BGE_RXLP_LOCSTAT_COS15 0x223C 1145#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1146#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1147#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1148#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1149#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1150#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1151#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1152* 1153 1154/* Receive List Placement mode register / 1155#define BGE_RXLPMODE_RESET 0x00000001 1156#define BGE_RXLPMODE_ENABLE 0x00000002 1157#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1158#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1159#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1160* 1161/* Receive List Placement Status register / 1162#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1163#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1164#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1165* 1166/* 1167 * Receive Data and Receive BD Initiator Control Registers 1168 / 1169#define BGE_RDBDI_MODE 0x2400 1170#define BGE_RDBDI_STATUS 0x2404 1171#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1172#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1173#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1174#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1175#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1176#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1177#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1178#define BGE_RX_STD_RCB_NICADDR 0x245C 1179#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1180#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1181#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1182#define BGE_RX_MINI_RCB_NICADDR 0x246C 1183#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1184#define BGE_RDBDI_STD_RX_CONS 0x2474 1185#define BGE_RDBDI_MINI_RX_CONS 0x2478 1186#define BGE_RDBDI_RETURN_PROD0 0x2480 1187#define BGE_RDBDI_RETURN_PROD1 0x2484 1188#define BGE_RDBDI_RETURN_PROD2 0x2488 1189#define BGE_RDBDI_RETURN_PROD3 0x248C 1190#define BGE_RDBDI_RETURN_PROD4 0x2490 1191#define BGE_RDBDI_RETURN_PROD5 0x2494 1192#define BGE_RDBDI_RETURN_PROD6 0x2498 1193#define BGE_RDBDI_RETURN_PROD7 0x249C 1194#define BGE_RDBDI_RETURN_PROD8 0x24A0 1195#define BGE_RDBDI_RETURN_PROD9 0x24A4 1196#define BGE_RDBDI_RETURN_PROD10 0x24A8 1197#define BGE_RDBDI_RETURN_PROD11 0x24AC 1198#define BGE_RDBDI_RETURN_PROD12 0x24B0 1199#define BGE_RDBDI_RETURN_PROD13 0x24B4 1200#define BGE_RDBDI_RETURN_PROD14 0x24B8 1201#define BGE_RDBDI_RETURN_PROD15 0x24BC 1202#define BGE_RDBDI_HWDIAG 0x24C0 1203* 1204 1205/* Receive Data and Receive BD Initiator Mode register / 1206#define BGE_RDBDIMODE_RESET 0x00000001 1207#define BGE_RDBDIMODE_ENABLE 0x00000002 1208#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1209#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1210#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1211* 1212/* Receive Data and Receive BD Initiator Status register / 1213#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1214#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1215#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1216* 1217 1218/* 1219 * Receive Data Completion Control registers 1220 / 1221#define BGE_RDC_MODE 0x2800 1222* 1223/* Receive Data Completion Mode register / 1224#define BGE_RDCMODE_RESET 0x00000001 1225#define BGE_RDCMODE_ENABLE 0x00000002 1226#define BGE_RDCMODE_ATTN 0x00000004 1227* 1228/* 1229 * Receive BD Initiator Control registers 1230 / 1231#define BGE_RBDI_MODE 0x2C00 1232#define BGE_RBDI_STATUS 0x2C04 1233#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1234#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1235#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1236#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1237#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1238#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1239* 1240#define BGE_STD_REPLENISH_LWM 0x2D00 1241#define BGE_JMB_REPLENISH_LWM 0x2D04 1242 1243/* Receive BD Initiator Mode register / 1244#define BGE_RBDIMODE_RESET 0x00000001 1245#define BGE_RBDIMODE_ENABLE 0x00000002 1246#define BGE_RBDIMODE_ATTN 0x00000004 1247* 1248/* Receive BD Initiator Status register / 1249#define BGE_RBDISTAT_ATTN 0x00000004 1250* 1251/* 1252 * Receive BD Completion Control registers 1253 / 1254#define BGE_RBDC_MODE 0x3000 1255#define BGE_RBDC_STATUS 0x3004 1256#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1257#define BGE_RBDC_STD_BD_PROD 0x300C 1258#define BGE_RBDC_MINI_BD_PROD 0x3010 1259* 1260/* Receive BD completion mode register / 1261#define BGE_RBDCMODE_RESET 0x00000001 1262#define BGE_RBDCMODE_ENABLE 0x00000002 1263#define BGE_RBDCMODE_ATTN 0x00000004 1264* 1265/* Receive BD completion status register / 1266#define BGE_RBDCSTAT_ERROR 0x00000004 1267* 1268/* 1269 * Receive List Selector Control registers 1270 / 1271#define BGE_RXLS_MODE 0x3400 1272#define BGE_RXLS_STATUS 0x3404 1273* 1274/* Receive List Selector Mode register / 1275#define BGE_RXLSMODE_RESET 0x00000001 1276#define BGE_RXLSMODE_ENABLE 0x00000002 1277#define BGE_RXLSMODE_ATTN 0x00000004 1278* 1279/* Receive List Selector Status register / 1280#define BGE_RXLSSTAT_ERROR 0x00000004 1281* 1282#define BGE_CPMU_CTRL 0x3600 1283#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1284#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1285#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1286#define BGE_CPMU_HST_ACC 0x361C 1287#define BGE_CPMU_CLCK_ORIDE 0x3624 1288#define BGE_CPMU_CLCK_STAT 0x3630 1289#define BGE_CPMU_MUTEX_REQ 0x365C 1290#define BGE_CPMU_MUTEX_GNT 0x3660 1291#define BGE_CPMU_PHY_STRAP 0x3664	382#define BGE_CHIPREV_5784_AX 0x57841 383 384/* PCI DMA Read/Write Control register / 385#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 386#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001 387#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 388#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 389#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 390#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 391#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 392#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 393#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 394#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 395#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 396#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 397#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 398* 399#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 400#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 401#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 402#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 403 404#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080 405#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380 406 407#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 408#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 409#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 410#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 411#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 412#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 413#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 414#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 415 416#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 417#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 418#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 419#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 420#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 421#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 422#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 423#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 424 425/* 426 * PCI state register -- note, this register is read only 427 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 428 * register is set. 429 / 430#define BGE_PCISTATE_FORCE_RESET 0x00000001 431#define BGE_PCISTATE_INTR_STATE 0x00000002 432#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 433#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 434#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 435#define BGE_PCISTATE_ROM_ENABLE 0x00000020 436#define BGE_PCISTATE_ROM_RETRY_ENABLE 0x00000040 437#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 438#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 439#define BGE_PCISTATE_RETRY_SAME_DMA 0x00002000 440#define BGE_PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000 441#define BGE_PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000 442#define BGE_PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000 443* 444/* 445 * PCI Clock Control register -- note, this register is read only 446 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 447 * register is set. 448 / 449#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 450#define BGE_PCICLOCKCTL_M66EN 0x00000080 451#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 452#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 453#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 454#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 455#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 456#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 457#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 458#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 459* 460 461#ifndef PCIM_CMD_MWIEN 462#define PCIM_CMD_MWIEN 0x0010 463#endif 464#ifndef PCIM_CMD_INTxDIS 465#define PCIM_CMD_INTxDIS 0x0400 466#endif 467 468/* BAR0 (MAC) Register Definitions / 469* 470/* 471 * High priority mailbox registers 472 * Each mailbox is 64-bits wide, though we only use the 473 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 474 * first. The NIC will load the mailbox after the lower 32 bit word 475 * has been updated. 476 / 477#define BGE_MBX_IRQ0_HI 0x0200 478#define BGE_MBX_IRQ0_LO 0x0204 479#define BGE_MBX_IRQ1_HI 0x0208 480#define BGE_MBX_IRQ1_LO 0x020C 481#define BGE_MBX_IRQ2_HI 0x0210 482#define BGE_MBX_IRQ2_LO 0x0214 483#define BGE_MBX_IRQ3_HI 0x0218 484#define BGE_MBX_IRQ3_LO 0x021C 485#define BGE_MBX_GEN0_HI 0x0220 486#define BGE_MBX_GEN0_LO 0x0224 487#define BGE_MBX_GEN1_HI 0x0228 488#define BGE_MBX_GEN1_LO 0x022C 489#define BGE_MBX_GEN2_HI 0x0230 490#define BGE_MBX_GEN2_LO 0x0234 491#define BGE_MBX_GEN3_HI 0x0228 492#define BGE_MBX_GEN3_LO 0x022C 493#define BGE_MBX_GEN4_HI 0x0240 494#define BGE_MBX_GEN4_LO 0x0244 495#define BGE_MBX_GEN5_HI 0x0248 496#define BGE_MBX_GEN5_LO 0x024C 497#define BGE_MBX_GEN6_HI 0x0250 498#define BGE_MBX_GEN6_LO 0x0254 499#define BGE_MBX_GEN7_HI 0x0258 500#define BGE_MBX_GEN7_LO 0x025C 501#define BGE_MBX_RELOAD_STATS_HI 0x0260 502#define BGE_MBX_RELOAD_STATS_LO 0x0264 503#define BGE_MBX_RX_STD_PROD_HI 0x0268 504#define BGE_MBX_RX_STD_PROD_LO 0x026C 505#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 506#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 507#define BGE_MBX_RX_MINI_PROD_HI 0x0278 508#define BGE_MBX_RX_MINI_PROD_LO 0x027C 509#define BGE_MBX_RX_CONS0_HI 0x0280 510#define BGE_MBX_RX_CONS0_LO 0x0284 511#define BGE_MBX_RX_CONS1_HI 0x0288 512#define BGE_MBX_RX_CONS1_LO 0x028C 513#define BGE_MBX_RX_CONS2_HI 0x0290 514#define BGE_MBX_RX_CONS2_LO 0x0294 515#define BGE_MBX_RX_CONS3_HI 0x0298 516#define BGE_MBX_RX_CONS3_LO 0x029C 517#define BGE_MBX_RX_CONS4_HI 0x02A0 518#define BGE_MBX_RX_CONS4_LO 0x02A4 519#define BGE_MBX_RX_CONS5_HI 0x02A8 520#define BGE_MBX_RX_CONS5_LO 0x02AC 521#define BGE_MBX_RX_CONS6_HI 0x02B0 522#define BGE_MBX_RX_CONS6_LO 0x02B4 523#define BGE_MBX_RX_CONS7_HI 0x02B8 524#define BGE_MBX_RX_CONS7_LO 0x02BC 525#define BGE_MBX_RX_CONS8_HI 0x02C0 526#define BGE_MBX_RX_CONS8_LO 0x02C4 527#define BGE_MBX_RX_CONS9_HI 0x02C8 528#define BGE_MBX_RX_CONS9_LO 0x02CC 529#define BGE_MBX_RX_CONS10_HI 0x02D0 530#define BGE_MBX_RX_CONS10_LO 0x02D4 531#define BGE_MBX_RX_CONS11_HI 0x02D8 532#define BGE_MBX_RX_CONS11_LO 0x02DC 533#define BGE_MBX_RX_CONS12_HI 0x02E0 534#define BGE_MBX_RX_CONS12_LO 0x02E4 535#define BGE_MBX_RX_CONS13_HI 0x02E8 536#define BGE_MBX_RX_CONS13_LO 0x02EC 537#define BGE_MBX_RX_CONS14_HI 0x02F0 538#define BGE_MBX_RX_CONS14_LO 0x02F4 539#define BGE_MBX_RX_CONS15_HI 0x02F8 540#define BGE_MBX_RX_CONS15_LO 0x02FC 541#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 542#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 543#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 544#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 545#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 546#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 547#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 548#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 549#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 550#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 551#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 552#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 553#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 554#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 555#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 556#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 557#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 558#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 559#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 560#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 561#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 562#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 563#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 564#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 565#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 566#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 567#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 568#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 569#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 570#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 571#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 572#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 573#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 574#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 575#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 576#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 577#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 578#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 579#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 580#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 581#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 582#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 583#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 584#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 585#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 586#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 587#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 588#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 589#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 590#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 591#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 592#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 593#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 594#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 595#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 596#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 597#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 598#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 599#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 600#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 601#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 602#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 603#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 604#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 605* 606#define BGE_TX_RINGS_MAX 4 607#define BGE_TX_RINGS_EXTSSRAM_MAX 16 608#define BGE_RX_RINGS_MAX 16 609#define BGE_RX_RINGS_MAX_5717 17 610 611/* Ethernet MAC control registers / 612#define BGE_MAC_MODE 0x0400 613#define BGE_MAC_STS 0x0404 614#define BGE_MAC_EVT_ENB 0x0408 615#define BGE_MAC_LED_CTL 0x040C 616#define BGE_MAC_ADDR1_LO 0x0410 617#define BGE_MAC_ADDR1_HI 0x0414 618#define BGE_MAC_ADDR2_LO 0x0418 619#define BGE_MAC_ADDR2_HI 0x041C 620#define BGE_MAC_ADDR3_LO 0x0420 621#define BGE_MAC_ADDR3_HI 0x0424 622#define BGE_MAC_ADDR4_LO 0x0428 623#define BGE_MAC_ADDR4_HI 0x042C 624#define BGE_WOL_PATPTR 0x0430 625#define BGE_WOL_PATCFG 0x0434 626#define BGE_TX_RANDOM_BACKOFF 0x0438 627#define BGE_RX_MTU 0x043C 628#define BGE_GBIT_PCS_TEST 0x0440 629#define BGE_TX_TBI_AUTONEG 0x0444 630#define BGE_RX_TBI_AUTONEG 0x0448 631#define BGE_MI_COMM 0x044C 632#define BGE_MI_STS 0x0450 633#define BGE_MI_MODE 0x0454 634#define BGE_AUTOPOLL_STS 0x0458 635#define BGE_TX_MODE 0x045C 636#define BGE_TX_STS 0x0460 637#define BGE_TX_LENGTHS 0x0464 638#define BGE_RX_MODE 0x0468 639#define BGE_RX_STS 0x046C 640#define BGE_MAR0 0x0470 641#define BGE_MAR1 0x0474 642#define BGE_MAR2 0x0478 643#define BGE_MAR3 0x047C 644#define BGE_RX_BD_RULES_CTL0 0x0480 645#define BGE_RX_BD_RULES_MASKVAL0 0x0484 646#define BGE_RX_BD_RULES_CTL1 0x0488 647#define BGE_RX_BD_RULES_MASKVAL1 0x048C 648#define BGE_RX_BD_RULES_CTL2 0x0490 649#define BGE_RX_BD_RULES_MASKVAL2 0x0494 650#define BGE_RX_BD_RULES_CTL3 0x0498 651#define BGE_RX_BD_RULES_MASKVAL3 0x049C 652#define BGE_RX_BD_RULES_CTL4 0x04A0 653#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 654#define BGE_RX_BD_RULES_CTL5 0x04A8 655#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 656#define BGE_RX_BD_RULES_CTL6 0x04B0 657#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 658#define BGE_RX_BD_RULES_CTL7 0x04B8 659#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 660#define BGE_RX_BD_RULES_CTL8 0x04C0 661#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 662#define BGE_RX_BD_RULES_CTL9 0x04C8 663#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 664#define BGE_RX_BD_RULES_CTL10 0x04D0 665#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 666#define BGE_RX_BD_RULES_CTL11 0x04D8 667#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 668#define BGE_RX_BD_RULES_CTL12 0x04E0 669#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 670#define BGE_RX_BD_RULES_CTL13 0x04E8 671#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 672#define BGE_RX_BD_RULES_CTL14 0x04F0 673#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 674#define BGE_RX_BD_RULES_CTL15 0x04F8 675#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 676#define BGE_RX_RULES_CFG 0x0500 677#define BGE_MAX_RX_FRAME_LOWAT 0x0504 678#define BGE_SERDES_CFG 0x0590 679#define BGE_SERDES_STS 0x0594 680#define BGE_SGDIG_CFG 0x05B0 681#define BGE_SGDIG_STS 0x05B4 682#define BGE_TX_MAC_STATS_OCTETS 0x0800 683#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 684#define BGE_TX_MAC_STATS_COLLS 0x0808 685#define BGE_TX_MAC_STATS_XON_SENT 0x080C 686#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 687#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 688#define BGE_TX_MAC_STATS_ERRORS 0x0818 689#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 690#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 691#define BGE_TX_MAC_STATS_DEFERRED 0x0824 692#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 693#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 694#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 695#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 696#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 697#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 698#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 699#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 700#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 701#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 702#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 703#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 704#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 705#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 706#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 707#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 708#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 709#define BGE_TX_MAC_STATS_UCAST 0x086C 710#define BGE_TX_MAC_STATS_MCAST 0x0870 711#define BGE_TX_MAC_STATS_BCAST 0x0874 712#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 713#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 714#define BGE_RX_MAC_STATS_OCTESTS 0x0880 715#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 716#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 717#define BGE_RX_MAC_STATS_UCAST 0x088C 718#define BGE_RX_MAC_STATS_MCAST 0x0890 719#define BGE_RX_MAC_STATS_BCAST 0x0894 720#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 721#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 722#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 723#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 724#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 725#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 726#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 727#define BGE_RX_MAC_STATS_JABBERS 0x08B4 728#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 729* 730/* Ethernet MAC Mode register / 731#define BGE_MACMODE_RESET 0x00000001 732#define BGE_MACMODE_HALF_DUPLEX 0x00000002 733#define BGE_MACMODE_PORTMODE 0x0000000C 734#define BGE_MACMODE_LOOPBACK 0x00000010 735#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 736#define BGE_MACMODE_TX_BURST_ENB 0x00000100 737#define BGE_MACMODE_MAX_DEFER 0x00000200 738#define BGE_MACMODE_LINK_POLARITY 0x00000400 739#define BGE_MACMODE_RX_STATS_ENB 0x00000800 740#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 741#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 742#define BGE_MACMODE_TX_STATS_ENB 0x00004000 743#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 744#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 745#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 746#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 747#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 748#define BGE_MACMODE_MIP_ENB 0x00100000 749#define BGE_MACMODE_TXDMA_ENB 0x00200000 750#define BGE_MACMODE_RXDMA_ENB 0x00400000 751#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 752#define BGE_MACMODE_APE_RX_EN 0x08000000 753#define BGE_MACMODE_APE_TX_EN 0x10000000 754* 755#define BGE_PORTMODE_NONE 0x00000000 756#define BGE_PORTMODE_MII 0x00000004 757#define BGE_PORTMODE_GMII 0x00000008 758#define BGE_PORTMODE_TBI 0x0000000C 759 760/* MAC Status register / 761#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 762#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 763#define BGE_MACSTAT_RX_CFG 0x00000004 764#define BGE_MACSTAT_CFG_CHANGED 0x00000008 765#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 766#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 767#define BGE_MACSTAT_LINK_CHANGED 0x00001000 768#define BGE_MACSTAT_MI_COMPLETE 0x00400000 769#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 770#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 771#define BGE_MACSTAT_ODI_ERROR 0x02000000 772#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 773#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 774* 775/* MAC Event Enable Register / 776#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 777#define BGE_EVTENB_LINK_CHANGED 0x00001000 778#define BGE_EVTENB_MI_COMPLETE 0x00400000 779#define BGE_EVTENB_MI_INTERRUPT 0x00800000 780#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 781#define BGE_EVTENB_ODI_ERROR 0x02000000 782#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 783#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 784* 785/* LED Control Register / 786#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 787#define BGE_LEDCTL_1000MBPS_LED 0x00000002 788#define BGE_LEDCTL_100MBPS_LED 0x00000004 789#define BGE_LEDCTL_10MBPS_LED 0x00000008 790#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 791#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 792#define BGE_LEDCTL_TRAFLED_BLINK_2 0x00000040 793#define BGE_LEDCTL_1000MBPS_STS 0x00000080 794#define BGE_LEDCTL_100MBPS_STS 0x00000100 795#define BGE_LEDCTL_10MBPS_STS 0x00000200 796#define BGE_LEDCTL_TRAFLED_STS 0x00000400 797#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 798#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 799* 800/* TX backoff seed register / 801#define BGE_TX_BACKOFF_SEED_MASK 0x3FF 802* 803/* Autopoll status register / 804#define BGE_AUTOPOLLSTS_ERROR 0x00000001 805* 806/* Transmit MAC mode register / 807#define BGE_TXMODE_RESET 0x00000001 808#define BGE_TXMODE_ENABLE 0x00000002 809#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 810#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 811#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 812#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100 813#define BGE_TXMODE_JMB_FRM_LEN 0x00400000 814#define BGE_TXMODE_CNT_DN_MODE 0x00800000 815* 816/* Transmit MAC status register / 817#define BGE_TXSTAT_RX_XOFFED 0x00000001 818#define BGE_TXSTAT_SENT_XOFF 0x00000002 819#define BGE_TXSTAT_SENT_XON 0x00000004 820#define BGE_TXSTAT_LINK_UP 0x00000008 821#define BGE_TXSTAT_ODI_UFLOW 0x00000010 822#define BGE_TXSTAT_ODI_OFLOW 0x00000020 823* 824/* Transmit MAC lengths register / 825#define BGE_TXLEN_SLOTTIME 0x000000FF 826#define BGE_TXLEN_IPG 0x00000F00 827#define BGE_TXLEN_CRS 0x00003000 828#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000 829#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000 830* 831/* Receive MAC mode register / 832#define BGE_RXMODE_RESET 0x00000001 833#define BGE_RXMODE_ENABLE 0x00000002 834#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 835#define BGE_RXMODE_RX_GIANTS 0x00000020 836#define BGE_RXMODE_RX_RUNTS 0x00000040 837#define BGE_RXMODE_8022_LENCHECK 0x00000080 838#define BGE_RXMODE_RX_PROMISC 0x00000100 839#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 840#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 841#define BGE_RXMODE_IPV6_ENABLE 0x01000000 842* 843/* Receive MAC status register / 844#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 845#define BGE_RXSTAT_RCVD_XOFF 0x00000002 846#define BGE_RXSTAT_RCVD_XON 0x00000004 847* 848/* Receive Rules Control register / 849#define BGE_RXRULECTL_OFFSET 0x000000FF 850#define BGE_RXRULECTL_CLASS 0x00001F00 851#define BGE_RXRULECTL_HDRTYPE 0x0000E000 852#define BGE_RXRULECTL_COMPARE_OP 0x00030000 853#define BGE_RXRULECTL_MAP 0x01000000 854#define BGE_RXRULECTL_DISCARD 0x02000000 855#define BGE_RXRULECTL_MASK 0x04000000 856#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 857#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 858#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 859#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 860* 861/* Receive Rules Mask register / 862#define BGE_RXRULEMASK_VALUE 0x0000FFFF 863#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 864* 865/* SERDES configuration register / 866#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 867#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 868#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 869#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 870#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 871#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 872#define BGE_SERDESCFG_TXMODE 0x00001000 873#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 874#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 875#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 876#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 877#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 878#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 879#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 880#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 881#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 882* 883/* SERDES status register / 884#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 885#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 886* 887/* SGDIG config (not documented) / 888#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 889#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 890#define BGE_SGDIGCFG_SEND 0x40000000 891#define BGE_SGDIGCFG_AUTO 0x80000000 892* 893/* SGDIG status (not documented) / 894#define BGE_SGDIGSTS_DONE 0x00000002 895#define BGE_SGDIGSTS_IS_SERDES 0x00000100 896#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 897#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 898* 899 900/* MI communication register / 901#define BGE_MICOMM_DATA 0x0000FFFF 902#define BGE_MICOMM_REG 0x001F0000 903#define BGE_MICOMM_PHY 0x03E00000 904#define BGE_MICOMM_CMD 0x0C000000 905#define BGE_MICOMM_READFAIL 0x10000000 906#define BGE_MICOMM_BUSY 0x20000000 907* 908#define BGE_MIREG(x) ((x & 0x1F) << 16) 909#define BGE_MIPHY(x) ((x & 0x1F) << 21) 910#define BGE_MICMD_WRITE 0x04000000 911#define BGE_MICMD_READ 0x08000000 912 913/* MI status register / 914#define BGE_MISTS_LINK 0x00000001 915#define BGE_MISTS_10MBPS 0x00000002 916* 917#define BGE_MIMODE_CLK_10MHZ 0x00000001 918#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 919#define BGE_MIMODE_AUTOPOLL 0x00000010 920#define BGE_MIMODE_CLKCNT 0x001F0000 921#define BGE_MIMODE_500KHZ_CONST 0x00008000 922#define BGE_MIMODE_BASE 0x000C0000 923 924 925/* 926 * Send data initiator control registers. 927 / 928#define BGE_SDI_MODE 0x0C00 929#define BGE_SDI_STATUS 0x0C04 930#define BGE_SDI_STATS_CTL 0x0C08 931#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 932#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 933#define BGE_ISO_PKT_TX 0x0C20 934#define BGE_LOCSTATS_COS0 0x0C80 935#define BGE_LOCSTATS_COS1 0x0C84 936#define BGE_LOCSTATS_COS2 0x0C88 937#define BGE_LOCSTATS_COS3 0x0C8C 938#define BGE_LOCSTATS_COS4 0x0C90 939#define BGE_LOCSTATS_COS5 0x0C84 940#define BGE_LOCSTATS_COS6 0x0C98 941#define BGE_LOCSTATS_COS7 0x0C9C 942#define BGE_LOCSTATS_COS8 0x0CA0 943#define BGE_LOCSTATS_COS9 0x0CA4 944#define BGE_LOCSTATS_COS10 0x0CA8 945#define BGE_LOCSTATS_COS11 0x0CAC 946#define BGE_LOCSTATS_COS12 0x0CB0 947#define BGE_LOCSTATS_COS13 0x0CB4 948#define BGE_LOCSTATS_COS14 0x0CB8 949#define BGE_LOCSTATS_COS15 0x0CBC 950#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 951#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 952#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 953#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 954#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 955#define BGE_LOCSTATS_IRQS 0x0CD4 956#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 957#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 958* 959/* Send Data Initiator mode register / 960#define BGE_SDIMODE_RESET 0x00000001 961#define BGE_SDIMODE_ENABLE 0x00000002 962#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 963#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008 964* 965/* Send Data Initiator stats register / 966#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 967* 968/* Send Data Initiator stats control register / 969#define BGE_SDISTATSCTL_ENABLE 0x00000001 970#define BGE_SDISTATSCTL_FASTER 0x00000002 971#define BGE_SDISTATSCTL_CLEAR 0x00000004 972#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 973#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 974* 975/* 976 * Send Data Completion Control registers 977 / 978#define BGE_SDC_MODE 0x1000 979#define BGE_SDC_STATUS 0x1004 980* 981/* Send Data completion mode register / 982#define BGE_SDCMODE_RESET 0x00000001 983#define BGE_SDCMODE_ENABLE 0x00000002 984#define BGE_SDCMODE_ATTN 0x00000004 985#define BGE_SDCMODE_CDELAY 0x00000010 986* 987/* Send Data completion status register / 988#define BGE_SDCSTAT_ATTN 0x00000004 989* 990/* 991 * Send BD Ring Selector Control registers 992 / 993#define BGE_SRS_MODE 0x1400 994#define BGE_SRS_STATUS 0x1404 995#define BGE_SRS_HWDIAG 0x1408 996#define BGE_SRS_LOC_NIC_CONS0 0x1440 997#define BGE_SRS_LOC_NIC_CONS1 0x1444 998#define BGE_SRS_LOC_NIC_CONS2 0x1448 999#define BGE_SRS_LOC_NIC_CONS3 0x144C 1000#define BGE_SRS_LOC_NIC_CONS4 0x1450 1001#define BGE_SRS_LOC_NIC_CONS5 0x1454 1002#define BGE_SRS_LOC_NIC_CONS6 0x1458 1003#define BGE_SRS_LOC_NIC_CONS7 0x145C 1004#define BGE_SRS_LOC_NIC_CONS8 0x1460 1005#define BGE_SRS_LOC_NIC_CONS9 0x1464 1006#define BGE_SRS_LOC_NIC_CONS10 0x1468 1007#define BGE_SRS_LOC_NIC_CONS11 0x146C 1008#define BGE_SRS_LOC_NIC_CONS12 0x1470 1009#define BGE_SRS_LOC_NIC_CONS13 0x1474 1010#define BGE_SRS_LOC_NIC_CONS14 0x1478 1011#define BGE_SRS_LOC_NIC_CONS15 0x147C 1012* 1013/* Send BD Ring Selector Mode register / 1014#define BGE_SRSMODE_RESET 0x00000001 1015#define BGE_SRSMODE_ENABLE 0x00000002 1016#define BGE_SRSMODE_ATTN 0x00000004 1017* 1018/* Send BD Ring Selector Status register / 1019#define BGE_SRSSTAT_ERROR 0x00000004 1020* 1021/* Send BD Ring Selector HW Diagnostics register / 1022#define BGE_SRSHWDIAG_STATE 0x0000000F 1023#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 1024#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 1025#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 1026* 1027/* 1028 * Send BD Initiator Selector Control registers 1029 / 1030#define BGE_SBDI_MODE 0x1800 1031#define BGE_SBDI_STATUS 0x1804 1032#define BGE_SBDI_LOC_NIC_PROD0 0x1808 1033#define BGE_SBDI_LOC_NIC_PROD1 0x180C 1034#define BGE_SBDI_LOC_NIC_PROD2 0x1810 1035#define BGE_SBDI_LOC_NIC_PROD3 0x1814 1036#define BGE_SBDI_LOC_NIC_PROD4 0x1818 1037#define BGE_SBDI_LOC_NIC_PROD5 0x181C 1038#define BGE_SBDI_LOC_NIC_PROD6 0x1820 1039#define BGE_SBDI_LOC_NIC_PROD7 0x1824 1040#define BGE_SBDI_LOC_NIC_PROD8 0x1828 1041#define BGE_SBDI_LOC_NIC_PROD9 0x182C 1042#define BGE_SBDI_LOC_NIC_PROD10 0x1830 1043#define BGE_SBDI_LOC_NIC_PROD11 0x1834 1044#define BGE_SBDI_LOC_NIC_PROD12 0x1838 1045#define BGE_SBDI_LOC_NIC_PROD13 0x183C 1046#define BGE_SBDI_LOC_NIC_PROD14 0x1840 1047#define BGE_SBDI_LOC_NIC_PROD15 0x1844 1048* 1049/* Send BD Initiator Mode register / 1050#define BGE_SBDIMODE_RESET 0x00000001 1051#define BGE_SBDIMODE_ENABLE 0x00000002 1052#define BGE_SBDIMODE_ATTN 0x00000004 1053* 1054/* Send BD Initiator Status register / 1055#define BGE_SBDISTAT_ERROR 0x00000004 1056* 1057/* 1058 * Send BD Completion Control registers 1059 / 1060#define BGE_SBDC_MODE 0x1C00 1061#define BGE_SBDC_STATUS 0x1C04 1062* 1063/* Send BD Completion Control Mode register / 1064#define BGE_SBDCMODE_RESET 0x00000001 1065#define BGE_SBDCMODE_ENABLE 0x00000002 1066#define BGE_SBDCMODE_ATTN 0x00000004 1067* 1068/* Send BD Completion Control Status register / 1069#define BGE_SBDCSTAT_ATTN 0x00000004 1070* 1071/* 1072 * Receive List Placement Control registers 1073 / 1074#define BGE_RXLP_MODE 0x2000 1075#define BGE_RXLP_STATUS 0x2004 1076#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1077#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1078#define BGE_RXLP_CFG 0x2010 1079#define BGE_RXLP_STATS_CTL 0x2014 1080#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1081#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1082#define BGE_RXLP_HEAD0 0x2100 1083#define BGE_RXLP_TAIL0 0x2104 1084#define BGE_RXLP_COUNT0 0x2108 1085#define BGE_RXLP_HEAD1 0x2110 1086#define BGE_RXLP_TAIL1 0x2114 1087#define BGE_RXLP_COUNT1 0x2118 1088#define BGE_RXLP_HEAD2 0x2120 1089#define BGE_RXLP_TAIL2 0x2124 1090#define BGE_RXLP_COUNT2 0x2128 1091#define BGE_RXLP_HEAD3 0x2130 1092#define BGE_RXLP_TAIL3 0x2134 1093#define BGE_RXLP_COUNT3 0x2138 1094#define BGE_RXLP_HEAD4 0x2140 1095#define BGE_RXLP_TAIL4 0x2144 1096#define BGE_RXLP_COUNT4 0x2148 1097#define BGE_RXLP_HEAD5 0x2150 1098#define BGE_RXLP_TAIL5 0x2154 1099#define BGE_RXLP_COUNT5 0x2158 1100#define BGE_RXLP_HEAD6 0x2160 1101#define BGE_RXLP_TAIL6 0x2164 1102#define BGE_RXLP_COUNT6 0x2168 1103#define BGE_RXLP_HEAD7 0x2170 1104#define BGE_RXLP_TAIL7 0x2174 1105#define BGE_RXLP_COUNT7 0x2178 1106#define BGE_RXLP_HEAD8 0x2180 1107#define BGE_RXLP_TAIL8 0x2184 1108#define BGE_RXLP_COUNT8 0x2188 1109#define BGE_RXLP_HEAD9 0x2190 1110#define BGE_RXLP_TAIL9 0x2194 1111#define BGE_RXLP_COUNT9 0x2198 1112#define BGE_RXLP_HEAD10 0x21A0 1113#define BGE_RXLP_TAIL10 0x21A4 1114#define BGE_RXLP_COUNT10 0x21A8 1115#define BGE_RXLP_HEAD11 0x21B0 1116#define BGE_RXLP_TAIL11 0x21B4 1117#define BGE_RXLP_COUNT11 0x21B8 1118#define BGE_RXLP_HEAD12 0x21C0 1119#define BGE_RXLP_TAIL12 0x21C4 1120#define BGE_RXLP_COUNT12 0x21C8 1121#define BGE_RXLP_HEAD13 0x21D0 1122#define BGE_RXLP_TAIL13 0x21D4 1123#define BGE_RXLP_COUNT13 0x21D8 1124#define BGE_RXLP_HEAD14 0x21E0 1125#define BGE_RXLP_TAIL14 0x21E4 1126#define BGE_RXLP_COUNT14 0x21E8 1127#define BGE_RXLP_HEAD15 0x21F0 1128#define BGE_RXLP_TAIL15 0x21F4 1129#define BGE_RXLP_COUNT15 0x21F8 1130#define BGE_RXLP_LOCSTAT_COS0 0x2200 1131#define BGE_RXLP_LOCSTAT_COS1 0x2204 1132#define BGE_RXLP_LOCSTAT_COS2 0x2208 1133#define BGE_RXLP_LOCSTAT_COS3 0x220C 1134#define BGE_RXLP_LOCSTAT_COS4 0x2210 1135#define BGE_RXLP_LOCSTAT_COS5 0x2214 1136#define BGE_RXLP_LOCSTAT_COS6 0x2218 1137#define BGE_RXLP_LOCSTAT_COS7 0x221C 1138#define BGE_RXLP_LOCSTAT_COS8 0x2220 1139#define BGE_RXLP_LOCSTAT_COS9 0x2224 1140#define BGE_RXLP_LOCSTAT_COS10 0x2228 1141#define BGE_RXLP_LOCSTAT_COS11 0x222C 1142#define BGE_RXLP_LOCSTAT_COS12 0x2230 1143#define BGE_RXLP_LOCSTAT_COS13 0x2234 1144#define BGE_RXLP_LOCSTAT_COS14 0x2238 1145#define BGE_RXLP_LOCSTAT_COS15 0x223C 1146#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1147#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1148#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1149#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1150#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1151#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1152#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1153* 1154 1155/* Receive List Placement mode register / 1156#define BGE_RXLPMODE_RESET 0x00000001 1157#define BGE_RXLPMODE_ENABLE 0x00000002 1158#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1159#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1160#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1161* 1162/* Receive List Placement Status register / 1163#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1164#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1165#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1166* 1167/* 1168 * Receive Data and Receive BD Initiator Control Registers 1169 / 1170#define BGE_RDBDI_MODE 0x2400 1171#define BGE_RDBDI_STATUS 0x2404 1172#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1173#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1174#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1175#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1176#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1177#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1178#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1179#define BGE_RX_STD_RCB_NICADDR 0x245C 1180#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1181#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1182#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1183#define BGE_RX_MINI_RCB_NICADDR 0x246C 1184#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1185#define BGE_RDBDI_STD_RX_CONS 0x2474 1186#define BGE_RDBDI_MINI_RX_CONS 0x2478 1187#define BGE_RDBDI_RETURN_PROD0 0x2480 1188#define BGE_RDBDI_RETURN_PROD1 0x2484 1189#define BGE_RDBDI_RETURN_PROD2 0x2488 1190#define BGE_RDBDI_RETURN_PROD3 0x248C 1191#define BGE_RDBDI_RETURN_PROD4 0x2490 1192#define BGE_RDBDI_RETURN_PROD5 0x2494 1193#define BGE_RDBDI_RETURN_PROD6 0x2498 1194#define BGE_RDBDI_RETURN_PROD7 0x249C 1195#define BGE_RDBDI_RETURN_PROD8 0x24A0 1196#define BGE_RDBDI_RETURN_PROD9 0x24A4 1197#define BGE_RDBDI_RETURN_PROD10 0x24A8 1198#define BGE_RDBDI_RETURN_PROD11 0x24AC 1199#define BGE_RDBDI_RETURN_PROD12 0x24B0 1200#define BGE_RDBDI_RETURN_PROD13 0x24B4 1201#define BGE_RDBDI_RETURN_PROD14 0x24B8 1202#define BGE_RDBDI_RETURN_PROD15 0x24BC 1203#define BGE_RDBDI_HWDIAG 0x24C0 1204* 1205 1206/* Receive Data and Receive BD Initiator Mode register / 1207#define BGE_RDBDIMODE_RESET 0x00000001 1208#define BGE_RDBDIMODE_ENABLE 0x00000002 1209#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1210#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1211#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1212* 1213/* Receive Data and Receive BD Initiator Status register / 1214#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1215#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1216#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1217* 1218 1219/* 1220 * Receive Data Completion Control registers 1221 / 1222#define BGE_RDC_MODE 0x2800 1223* 1224/* Receive Data Completion Mode register / 1225#define BGE_RDCMODE_RESET 0x00000001 1226#define BGE_RDCMODE_ENABLE 0x00000002 1227#define BGE_RDCMODE_ATTN 0x00000004 1228* 1229/* 1230 * Receive BD Initiator Control registers 1231 / 1232#define BGE_RBDI_MODE 0x2C00 1233#define BGE_RBDI_STATUS 0x2C04 1234#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1235#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1236#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1237#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1238#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1239#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1240* 1241#define BGE_STD_REPLENISH_LWM 0x2D00 1242#define BGE_JMB_REPLENISH_LWM 0x2D04 1243 1244/* Receive BD Initiator Mode register / 1245#define BGE_RBDIMODE_RESET 0x00000001 1246#define BGE_RBDIMODE_ENABLE 0x00000002 1247#define BGE_RBDIMODE_ATTN 0x00000004 1248* 1249/* Receive BD Initiator Status register / 1250#define BGE_RBDISTAT_ATTN 0x00000004 1251* 1252/* 1253 * Receive BD Completion Control registers 1254 / 1255#define BGE_RBDC_MODE 0x3000 1256#define BGE_RBDC_STATUS 0x3004 1257#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1258#define BGE_RBDC_STD_BD_PROD 0x300C 1259#define BGE_RBDC_MINI_BD_PROD 0x3010 1260* 1261/* Receive BD completion mode register / 1262#define BGE_RBDCMODE_RESET 0x00000001 1263#define BGE_RBDCMODE_ENABLE 0x00000002 1264#define BGE_RBDCMODE_ATTN 0x00000004 1265* 1266/* Receive BD completion status register / 1267#define BGE_RBDCSTAT_ERROR 0x00000004 1268* 1269/* 1270 * Receive List Selector Control registers 1271 / 1272#define BGE_RXLS_MODE 0x3400 1273#define BGE_RXLS_STATUS 0x3404 1274* 1275/* Receive List Selector Mode register / 1276#define BGE_RXLSMODE_RESET 0x00000001 1277#define BGE_RXLSMODE_ENABLE 0x00000002 1278#define BGE_RXLSMODE_ATTN 0x00000004 1279* 1280/* Receive List Selector Status register / 1281#define BGE_RXLSSTAT_ERROR 0x00000004 1282* 1283#define BGE_CPMU_CTRL 0x3600 1284#define BGE_CPMU_LSPD_10MB_CLK 0x3604 1285#define BGE_CPMU_LSPD_1000MB_CLK 0x360C 1286#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610 1287#define BGE_CPMU_HST_ACC 0x361C 1288#define BGE_CPMU_CLCK_ORIDE 0x3624 1289#define BGE_CPMU_CLCK_STAT 0x3630 1290#define BGE_CPMU_MUTEX_REQ 0x365C 1291#define BGE_CPMU_MUTEX_GNT 0x3660 1292#define BGE_CPMU_PHY_STRAP 0x3664
	1293#define BGE_CPMU_PADRNG_CTL 0x3668
1292 1293/* Central Power Management Unit (CPMU) register / 1294#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1295#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1296#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1297#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1298* 1299/* Link Speed 10MB/No Link Power Mode Clock Policy register / 1300#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1301#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1302* 1303/* Link Speed 1000MB Power Mode Clock Policy register / 1304#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1305#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1306#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1307* 1308/* Link Aware Power Mode Clock Policy register / 1309#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1310#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1311* 1312#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1313#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1314 1315/* Clock Speed Override Policy register / 1316#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1317* 1318/* CPMU Clock Status register / 1319#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1320#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1321#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1322#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1323* 1324/* CPMU Mutex Request register / 1325#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1326#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1327* 1328/* CPMU GPHY Strap register / 1329#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1330*	1294 1295/* Central Power Management Unit (CPMU) register / 1296#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200 1297#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400 1298#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000 1299#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000 1300* 1301/* Link Speed 10MB/No Link Power Mode Clock Policy register / 1302#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000 1303#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000 1304* 1305/* Link Speed 1000MB Power Mode Clock Policy register / 1306#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000 1307#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000 1308#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000 1309* 1310/* Link Aware Power Mode Clock Policy register / 1311#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000 1312#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000 1313* 1314#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000 1315#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000 1316 1317/* Clock Speed Override Policy register / 1318#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000 1319* 1320/* CPMU Clock Status register / 1321#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000 1322#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000 1323#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000 1324#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000 1325* 1326/* CPMU Mutex Request register / 1327#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000 1328#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000 1329* 1330/* CPMU GPHY Strap register / 1331#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020 1332*
	1333/* CPMU Padring Control register / 1334#define BGE_CPMU_PADRNG_CTL_RDIV2 0x00040000 1335*
1331/* 1332 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1333 / 1334#define BGE_MBCF_MODE 0x3800 1335#define BGE_MBCF_STATUS 0x3804 1336* 1337/* Mbuf Cluster Free mode register / 1338#define BGE_MBCFMODE_RESET 0x00000001 1339#define BGE_MBCFMODE_ENABLE 0x00000002 1340#define BGE_MBCFMODE_ATTN 0x00000004 1341* 1342/* Mbuf Cluster Free status register / 1343#define BGE_MBCFSTAT_ERROR 0x00000004 1344* 1345/* 1346 * Host Coalescing Control registers 1347 / 1348#define BGE_HCC_MODE 0x3C00 1349#define BGE_HCC_STATUS 0x3C04 1350#define BGE_HCC_RX_COAL_TICKS 0x3C08 1351#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1352#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1353#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1354#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1355#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1356#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1357#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1358#define BGE_HCC_STATS_TICKS 0x3C28 1359#define BGE_HCC_STATS_ADDR_HI 0x3C30 1360#define BGE_HCC_STATS_ADDR_LO 0x3C34 1361#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1362#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1363#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1364#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1365#define BGE_FLOW_ATTN 0x3C48 1366#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1367#define BGE_HCC_STD_BD_CONS 0x3C54 1368#define BGE_HCC_MINI_BD_CONS 0x3C58 1369#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1370#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1371#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1372#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1373#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1374#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1375#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1376#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1377#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1378#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1379#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1380#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1381#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1382#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1383#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1384#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1385#define BGE_HCC_TX_BD_CONS0 0x3CC0 1386#define BGE_HCC_TX_BD_CONS1 0x3CC4 1387#define BGE_HCC_TX_BD_CONS2 0x3CC8 1388#define BGE_HCC_TX_BD_CONS3 0x3CCC 1389#define BGE_HCC_TX_BD_CONS4 0x3CD0 1390#define BGE_HCC_TX_BD_CONS5 0x3CD4 1391#define BGE_HCC_TX_BD_CONS6 0x3CD8 1392#define BGE_HCC_TX_BD_CONS7 0x3CDC 1393#define BGE_HCC_TX_BD_CONS8 0x3CE0 1394#define BGE_HCC_TX_BD_CONS9 0x3CE4 1395#define BGE_HCC_TX_BD_CONS10 0x3CE8 1396#define BGE_HCC_TX_BD_CONS11 0x3CEC 1397#define BGE_HCC_TX_BD_CONS12 0x3CF0 1398#define BGE_HCC_TX_BD_CONS13 0x3CF4 1399#define BGE_HCC_TX_BD_CONS14 0x3CF8 1400#define BGE_HCC_TX_BD_CONS15 0x3CFC 1401* 1402 1403/* Host coalescing mode register / 1404#define BGE_HCCMODE_RESET 0x00000001 1405#define BGE_HCCMODE_ENABLE 0x00000002 1406#define BGE_HCCMODE_ATTN 0x00000004 1407#define BGE_HCCMODE_COAL_NOW 0x00000008 1408#define BGE_HCCMODE_MSI_BITS 0x00000070 1409#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1410* 1411#define BGE_STATBLKSZ_FULL 0x00000000 1412#define BGE_STATBLKSZ_64BYTE 0x00000080 1413#define BGE_STATBLKSZ_32BYTE 0x00000100 1414 1415/* Host coalescing status register / 1416#define BGE_HCCSTAT_ERROR 0x00000004 1417* 1418/* Flow attention register / 1419#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1420#define BGE_FLOWATTN_MEMARB 0x00000080 1421#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1422#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1423#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1424#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1425#define BGE_FLOWATTN_RDBDI 0x00080000 1426#define BGE_FLOWATTN_RXLS 0x00100000 1427#define BGE_FLOWATTN_RXLP 0x00200000 1428#define BGE_FLOWATTN_RBDC 0x00400000 1429#define BGE_FLOWATTN_RBDI 0x00800000 1430#define BGE_FLOWATTN_SDC 0x08000000 1431#define BGE_FLOWATTN_SDI 0x10000000 1432#define BGE_FLOWATTN_SRS 0x20000000 1433#define BGE_FLOWATTN_SBDC 0x40000000 1434#define BGE_FLOWATTN_SBDI 0x80000000 1435* 1436/* 1437 * Memory arbiter registers 1438 / 1439#define BGE_MARB_MODE 0x4000 1440#define BGE_MARB_STATUS 0x4004 1441#define BGE_MARB_TRAPADDR_HI 0x4008 1442#define BGE_MARB_TRAPADDR_LO 0x400C 1443* 1444/* Memory arbiter mode register / 1445#define BGE_MARBMODE_RESET 0x00000001 1446#define BGE_MARBMODE_ENABLE 0x00000002 1447#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1448#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1449#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1450#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1451#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1452#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1453#define BGE_MARBMODE_PCI_TRAP 0x00000100 1454#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1455#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1456#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1457#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1458#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1459#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1460#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1461#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1462#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1463#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1464#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1465#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1466#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1467#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1468#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1469#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1470#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1471* 1472/* Memory arbiter status register / 1473#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1474#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1475#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1476#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1477#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1478#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1479#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1480#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1481#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1482#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1483#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1484#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1485#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1486#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1487#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1488#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1489#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1490#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1491#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1492#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1493#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1494#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1495#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1496#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1497* 1498/* 1499 * Buffer manager control registers 1500 / 1501#define BGE_BMAN_MODE 0x4400 1502#define BGE_BMAN_STATUS 0x4404 1503#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1504#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1505#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1506#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1507#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1508#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1509#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1510#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1511#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1512#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1513#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1514#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1515#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1516#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1517#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1518#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1519#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1520#define BGE_BMAN_HWDIAG_1 0x444C 1521#define BGE_BMAN_HWDIAG_2 0x4450 1522#define BGE_BMAN_HWDIAG_3 0x4454 1523* 1524/* Buffer manager mode register / 1525#define BGE_BMANMODE_RESET 0x00000001 1526#define BGE_BMANMODE_ENABLE 0x00000002 1527#define BGE_BMANMODE_ATTN 0x00000004 1528#define BGE_BMANMODE_TESTMODE 0x00000008 1529#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1530#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1531* 1532/* Buffer manager status register / 1533#define BGE_BMANSTAT_ERRO 0x00000004 1534#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1535* 1536 1537/* 1538 * Read DMA Control registers 1539 / 1540#define BGE_RDMA_MODE 0x4800 1541#define BGE_RDMA_STATUS 0x4804 1542#define BGE_RDMA_RSRVCTRL 0x4900 1543#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1544* 1545/* Read DMA mode register / 1546#define BGE_RDMAMODE_RESET 0x00000001 1547#define BGE_RDMAMODE_ENABLE 0x00000002 1548#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1549#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1550#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1551#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1552#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1553#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1554#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1555#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1556#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1557#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1558#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1559#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1560#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1561#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1562#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1563#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1564#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1565#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1566* 1567/* Read DMA status register / 1568#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1569#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1570#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1571#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1572#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1573#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1574#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1575#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1576* 1577/* Read DMA Reserved Control register / 1578#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1579#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1580#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1581#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1582#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1583#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1584#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1585* 1586#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1587#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1588#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1589#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1590#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1591 1592/* BD Read DMA Mode register / 1593#define BGE_RDMA_BD_MODE 0x4A00 1594/ BD Read DMA Mode status register / 1595#define BGE_RDMA_BD_STATUS 0x4A04 1596* 1597#define BGE_RDMA_BD_MODE_RESET 0x00000001 1598#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1599 1600/* Non-LSO Read DMA Mode register / 1601#define BGE_RDMA_NON_LSO_MODE 0x4B00 1602/ Non-LSO Read DMA Mode status register / 1603#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1604* 1605#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1606#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1607 1608#define BGE_RDMA_LENGTH 0x4BE0 1609#define BGE_NUM_RDMA_CHANNELS 4 1610 1611/* 1612 * Write DMA control registers 1613 / 1614#define BGE_WDMA_MODE 0x4C00 1615#define BGE_WDMA_STATUS 0x4C04 1616* 1617/* Write DMA mode register / 1618#define BGE_WDMAMODE_RESET 0x00000001 1619#define BGE_WDMAMODE_ENABLE 0x00000002 1620#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1621#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1622#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1623#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1624#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1625#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1626#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1627#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1628#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1629#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1630#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1631* 1632/* Write DMA status register / 1633#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1634#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1635#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1636#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1637#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1638#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1639#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1640#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1641* 1642 1643/* 1644 * RX CPU registers 1645 / 1646#define BGE_RXCPU_MODE 0x5000 1647#define BGE_RXCPU_STATUS 0x5004 1648#define BGE_RXCPU_PC 0x501C 1649* 1650/* RX CPU mode register / 1651#define BGE_RXCPUMODE_RESET 0x00000001 1652#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1653#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1654#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1655#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1656#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1657#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1658#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1659#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1660#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1661#define BGE_RXCPUMODE_HALTCPU 0x00000400 1662#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1663#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1664#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1665* 1666/* RX CPU status register / 1667#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1668#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1669#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1670#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1671#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1672#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1673#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1674#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1675#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1676#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1677#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1678#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1679#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1680#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1681#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1682#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1683#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1684* 1685/* 1686 * V? CPU registers 1687 / 1688#define BGE_VCPU_STATUS 0x5100 1689#define BGE_VCPU_EXT_CTRL 0x6890 1690* 1691#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1692#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1693 1694#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1695#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1696 1697/* 1698 * TX CPU registers 1699 / 1700#define BGE_TXCPU_MODE 0x5400 1701#define BGE_TXCPU_STATUS 0x5404 1702#define BGE_TXCPU_PC 0x541C 1703* 1704/* TX CPU mode register / 1705#define BGE_TXCPUMODE_RESET 0x00000001 1706#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1707#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1708#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1709#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1710#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1711#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1712#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1713#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1714#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1715#define BGE_TXCPUMODE_HALTCPU 0x00000400 1716#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1717#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1718* 1719/* TX CPU status register / 1720#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1721#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1722#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1723#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1724#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1725#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1726#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1727#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1728#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1729#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1730#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1731#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1732#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1733#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1734#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1735#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1736#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1737* 1738 1739/* 1740 * Low priority mailbox registers 1741 / 1742#define BGE_LPMBX_IRQ0_HI 0x5800 1743#define BGE_LPMBX_IRQ0_LO 0x5804 1744#define BGE_LPMBX_IRQ1_HI 0x5808 1745#define BGE_LPMBX_IRQ1_LO 0x580C 1746#define BGE_LPMBX_IRQ2_HI 0x5810 1747#define BGE_LPMBX_IRQ2_LO 0x5814 1748#define BGE_LPMBX_IRQ3_HI 0x5818 1749#define BGE_LPMBX_IRQ3_LO 0x581C 1750#define BGE_LPMBX_GEN0_HI 0x5820 1751#define BGE_LPMBX_GEN0_LO 0x5824 1752#define BGE_LPMBX_GEN1_HI 0x5828 1753#define BGE_LPMBX_GEN1_LO 0x582C 1754#define BGE_LPMBX_GEN2_HI 0x5830 1755#define BGE_LPMBX_GEN2_LO 0x5834 1756#define BGE_LPMBX_GEN3_HI 0x5828 1757#define BGE_LPMBX_GEN3_LO 0x582C 1758#define BGE_LPMBX_GEN4_HI 0x5840 1759#define BGE_LPMBX_GEN4_LO 0x5844 1760#define BGE_LPMBX_GEN5_HI 0x5848 1761#define BGE_LPMBX_GEN5_LO 0x584C 1762#define BGE_LPMBX_GEN6_HI 0x5850 1763#define BGE_LPMBX_GEN6_LO 0x5854 1764#define BGE_LPMBX_GEN7_HI 0x5858 1765#define BGE_LPMBX_GEN7_LO 0x585C 1766#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1767#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1768#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1769#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1770#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1771#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1772#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1773#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1774#define BGE_LPMBX_RX_CONS0_HI 0x5880 1775#define BGE_LPMBX_RX_CONS0_LO 0x5884 1776#define BGE_LPMBX_RX_CONS1_HI 0x5888 1777#define BGE_LPMBX_RX_CONS1_LO 0x588C 1778#define BGE_LPMBX_RX_CONS2_HI 0x5890 1779#define BGE_LPMBX_RX_CONS2_LO 0x5894 1780#define BGE_LPMBX_RX_CONS3_HI 0x5898 1781#define BGE_LPMBX_RX_CONS3_LO 0x589C 1782#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1783#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1784#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1785#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1786#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1787#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1788#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1789#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1790#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1791#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1792#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1793#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1794#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1795#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1796#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1797#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1798#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1799#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1800#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1801#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1802#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1803#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1804#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1805#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1806#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1807#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1808#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1809#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1810#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1811#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1812#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1813#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1814#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1815#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1816#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1817#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1818#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1819#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1820#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1821#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1822#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1823#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1824#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1825#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1826#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1827#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1828#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1829#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1830#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1831#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1832#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1833#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1834#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1835#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1836#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1837#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1838#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1839#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1840#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1841#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1842#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1843#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1844#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1845#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1846#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1847#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1848#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1849#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1850#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1851#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1852#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1853#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1854#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1855#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1856#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1857#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1858#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1859#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1860#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1861#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1862#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1863#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1864#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1865#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1866#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1867#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1868#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1869#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1870* 1871/* 1872 * Flow throw Queue reset register 1873 / 1874#define BGE_FTQ_RESET 0x5C00 1875* 1876#define BGE_FTQRESET_DMAREAD 0x00000002 1877#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1878#define BGE_FTQRESET_DMADONE 0x00000010 1879#define BGE_FTQRESET_SBDC 0x00000020 1880#define BGE_FTQRESET_SDI 0x00000040 1881#define BGE_FTQRESET_WDMA 0x00000080 1882#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1883#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1884#define BGE_FTQRESET_SDC 0x00000400 1885#define BGE_FTQRESET_HCC 0x00000800 1886#define BGE_FTQRESET_TXFIFO 0x00001000 1887#define BGE_FTQRESET_MBC 0x00002000 1888#define BGE_FTQRESET_RBDC 0x00004000 1889#define BGE_FTQRESET_RXLP 0x00008000 1890#define BGE_FTQRESET_RDBDI 0x00010000 1891#define BGE_FTQRESET_RDC 0x00020000 1892#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1893 1894/* 1895 * Message Signaled Interrupt registers 1896 / 1897#define BGE_MSI_MODE 0x6000 1898#define BGE_MSI_STATUS 0x6004 1899#define BGE_MSI_FIFOACCESS 0x6008 1900* 1901/* MSI mode register / 1902#define BGE_MSIMODE_RESET 0x00000001 1903#define BGE_MSIMODE_ENABLE 0x00000002 1904#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1905#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1906* 1907/* MSI status register / 1908#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1909#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1910#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1911#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1912#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1913* 1914 1915/* 1916 * DMA Completion registers 1917 / 1918#define BGE_DMAC_MODE 0x6400 1919* 1920/* DMA Completion mode register / 1921#define BGE_DMACMODE_RESET 0x00000001 1922#define BGE_DMACMODE_ENABLE 0x00000002 1923* 1924 1925/* 1926 * General control registers. 1927 / 1928#define BGE_MODE_CTL 0x6800 1929#define BGE_MISC_CFG 0x6804 1930#define BGE_MISC_LOCAL_CTL 0x6808 1931#define BGE_RX_CPU_EVENT 0x6810 1932#define BGE_TX_CPU_EVENT 0x6820 1933#define BGE_EE_ADDR 0x6838 1934#define BGE_EE_DATA 0x683C 1935#define BGE_EE_CTL 0x6840 1936#define BGE_MDI_CTL 0x6844 1937#define BGE_EE_DELAY 0x6848 1938#define BGE_FASTBOOT_PC 0x6894 1939* 1940#define BGE_RX_CPU_DRV_EVENT 0x00004000 1941 1942/* 1943 * NVRAM Control registers 1944 / 1945#define BGE_NVRAM_CMD 0x7000 1946#define BGE_NVRAM_STAT 0x7004 1947#define BGE_NVRAM_WRDATA 0x7008 1948#define BGE_NVRAM_ADDR 0x700c 1949#define BGE_NVRAM_RDDATA 0x7010 1950#define BGE_NVRAM_CFG1 0x7014 1951#define BGE_NVRAM_CFG2 0x7018 1952#define BGE_NVRAM_CFG3 0x701c 1953#define BGE_NVRAM_SWARB 0x7020 1954#define BGE_NVRAM_ACCESS 0x7024 1955#define BGE_NVRAM_WRITE1 0x7028 1956* 1957#define BGE_NVRAMCMD_RESET 0x00000001 1958#define BGE_NVRAMCMD_DONE 0x00000008 1959#define BGE_NVRAMCMD_START 0x00000010 1960#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1961#define BGE_NVRAMCMD_ERASE 0x00000040 1962#define BGE_NVRAMCMD_FIRST 0x00000080 1963#define BGE_NVRAMCMD_LAST 0x00000100 1964* 1965#define BGE_NVRAM_READCMD \ 1966 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1967 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1968#define BGE_NVRAM_WRITECMD \ 1969 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1970 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1971 1972#define BGE_NVRAMSWARB_SET0 0x00000001 1973#define BGE_NVRAMSWARB_SET1 0x00000002 1974#define BGE_NVRAMSWARB_SET2 0x00000003 1975#define BGE_NVRAMSWARB_SET3 0x00000004 1976#define BGE_NVRAMSWARB_CLR0 0x00000010 1977#define BGE_NVRAMSWARB_CLR1 0x00000020 1978#define BGE_NVRAMSWARB_CLR2 0x00000040 1979#define BGE_NVRAMSWARB_CLR3 0x00000080 1980#define BGE_NVRAMSWARB_GNT0 0x00000100 1981#define BGE_NVRAMSWARB_GNT1 0x00000200 1982#define BGE_NVRAMSWARB_GNT2 0x00000400 1983#define BGE_NVRAMSWARB_GNT3 0x00000800 1984#define BGE_NVRAMSWARB_REQ0 0x00001000 1985#define BGE_NVRAMSWARB_REQ1 0x00002000 1986#define BGE_NVRAMSWARB_REQ2 0x00004000 1987#define BGE_NVRAMSWARB_REQ3 0x00008000 1988 1989#define BGE_NVRAMACC_ENABLE 0x00000001 1990#define BGE_NVRAMACC_WRENABLE 0x00000002 1991 1992/* Mode control register / 1993#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1994#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1995#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1996#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1997#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1998#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 1999#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2000#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2001#define BGE_MODECTL_NO_RX_CRC 0x00000400 2002#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2003#define BGE_MODECTL_NO_TX_INTR 0x00002000 2004#define BGE_MODECTL_NO_RX_INTR 0x00004000 2005#define BGE_MODECTL_FORCE_PCI32 0x00008000 2006#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2007#define BGE_MODECTL_STACKUP 0x00010000 2008#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2009#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2010#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2011#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2012#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2013#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2014#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2015#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2016#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2017#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2018#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2019* 2020/* Misc. config register / 2021#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2022#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2023#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2024#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2025#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2026#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2027#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2028#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2029#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2030* 2031#define BGE_32BITTIME_66MHZ (0x41 << 1) 2032 2033/* Misc. Local Control / 2034#define BGE_MLC_INTR_STATE 0x00000001 2035#define BGE_MLC_INTR_CLR 0x00000002 2036#define BGE_MLC_INTR_SET 0x00000004 2037#define BGE_MLC_INTR_ONATTN 0x00000008 2038#define BGE_MLC_MISCIO_IN0 0x00000100 2039#define BGE_MLC_MISCIO_IN1 0x00000200 2040#define BGE_MLC_MISCIO_IN2 0x00000400 2041#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2042#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2043#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2044#define BGE_MLC_MISCIO_OUT0 0x00004000 2045#define BGE_MLC_MISCIO_OUT1 0x00008000 2046#define BGE_MLC_MISCIO_OUT2 0x00010000 2047#define BGE_MLC_EXTRAM_ENB 0x00020000 2048#define BGE_MLC_SRAM_SIZE 0x001C0000 2049#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 2050#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 2051#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2052#define BGE_MLC_AUTO_EEPROM 0x01000000 2053* 2054#define BGE_SSRAMSIZE_256KB 0x00000000 2055#define BGE_SSRAMSIZE_512KB 0x00040000 2056#define BGE_SSRAMSIZE_1MB 0x00080000 2057#define BGE_SSRAMSIZE_2MB 0x000C0000 2058#define BGE_SSRAMSIZE_4MB 0x00100000 2059#define BGE_SSRAMSIZE_8MB 0x00140000 2060#define BGE_SSRAMSIZE_16M 0x00180000 2061 2062/* EEPROM address register / 2063#define BGE_EEADDR_ADDRESS 0x0000FFFC 2064#define BGE_EEADDR_HALFCLK 0x01FF0000 2065#define BGE_EEADDR_START 0x02000000 2066#define BGE_EEADDR_DEVID 0x1C000000 2067#define BGE_EEADDR_RESET 0x20000000 2068#define BGE_EEADDR_DONE 0x40000000 2069#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 2070* 2071#define BGE_EEDEVID(x) ((x & 7) << 26) 2072#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2073#define BGE_HALFCLK_384SCL 0x60 2074#define BGE_EE_READCMD \ 2075 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 2076 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 2077#define BGE_EE_WRCMD \ 2078 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 2079 BGE_EEADDR_START\|BGE_EEADDR_DONE) 2080 2081/* EEPROM Control register / 2082#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2083#define BGE_EECTL_CLKOUT 0x00000002 2084#define BGE_EECTL_CLKIN 0x00000004 2085#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2086#define BGE_EECTL_DATAOUT 0x00000010 2087#define BGE_EECTL_DATAIN 0x00000020 2088* 2089/* MDI (MII/GMII) access register / 2090#define BGE_MDI_DATA 0x00000001 2091#define BGE_MDI_DIR 0x00000002 2092#define BGE_MDI_SEL 0x00000004 2093#define BGE_MDI_CLK 0x00000008 2094* 2095#define BGE_MEMWIN_START 0x00008000 2096#define BGE_MEMWIN_END 0x0000FFFF 2097 2098/* BAR1 (APE) Register Definitions / 2099* 2100#define BGE_APE_GPIO_MSG 0x0008 2101#define BGE_APE_EVENT 0x000C 2102#define BGE_APE_LOCK_REQ 0x002C 2103#define BGE_APE_LOCK_GRANT 0x004C 2104 2105#define BGE_APE_GPIO_MSG_SHIFT 4 2106 2107#define BGE_APE_EVENT_1 0x00000001 2108 2109#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2110 2111#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2112 2113/* APE Shared Memory block (writable by APE only) / 2114#define BGE_APE_SEG_SIG 0x4000 2115#define BGE_APE_FW_STATUS 0x400C 2116#define BGE_APE_FW_FEATURES 0x4010 2117#define BGE_APE_FW_BEHAVIOR 0x4014 2118#define BGE_APE_FW_VERSION 0x4018 2119#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2120#define BGE_APE_FW_HEARTBEAT 0x4028 2121#define BGE_APE_FW_ERROR_FLAGS 0x4074 2122* 2123#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2124 2125#define BGE_APE_FW_STATUS_READY 0x00000100 2126 2127#define BGE_APE_FW_FEATURE_DASH 0x00000001 2128#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2129 2130#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2131#define BGE_APE_FW_VERSION_MAJSFT 24 2132#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2133#define BGE_APE_FW_VERSION_MINSFT 16 2134#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2135#define BGE_APE_FW_VERSION_REVSFT 8 2136#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2137 2138/* Host Shared Memory block (writable by host only) / 2139#define BGE_APE_HOST_SEG_SIG 0x4200 2140#define BGE_APE_HOST_SEG_LEN 0x4204 2141#define BGE_APE_HOST_INIT_COUNT 0x4208 2142#define BGE_APE_HOST_DRIVER_ID 0x420C 2143#define BGE_APE_HOST_BEHAVIOR 0x4210 2144#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2145#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2146#define BGE_APE_HOST_DRVR_STATE 0x421C 2147#define BGE_APE_HOST_WOL_SPEED 0x4224 2148* 2149#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2150 2151#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2152 2153#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2154#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2155 (BGE_APE_HOST_DRIVER_ID_FBSD \| \ 2156 ((maj) & 0xffd) << 16 \| ((min) & 0xff) << 8) 2157 2158#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2159 2160#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2161#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2162 2163#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2164#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2165#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2166#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2167 2168#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2169 2170#define BGE_APE_EVENT_STATUS 0x4300 2171 2172#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2173#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2174#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2175#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2176#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2177#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2178#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2179 2180#define BGE_APE_DEBUG_LOG 0x4E00 2181#define BGE_APE_DEBUG_LOG_LEN 0x0100 2182 2183#define BGE_APE_PER_LOCK_REQ 0x8400 2184#define BGE_APE_PER_LOCK_GRANT 0x8420 2185 2186#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2187#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2188#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2189#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2190 2191#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2192#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2193#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2194#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2195 2196/* APE Mutex Resources / 2197#define BGE_APE_LOCK_PHY0 0 2198#define BGE_APE_LOCK_GRC 1 2199#define BGE_APE_LOCK_PHY1 2 2200#define BGE_APE_LOCK_PHY2 3 2201#define BGE_APE_LOCK_MEM 4 2202#define BGE_APE_LOCK_PHY3 5 2203#define BGE_APE_LOCK_GPIO 7 2204* 2205#define BGE_MEMWIN_READ(sc, x, val) \ 2206 do { \ 2207 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2208 (0xFFFF0000 & x), 4); \ 2209 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2210 } while(0) 2211 2212#define BGE_MEMWIN_WRITE(sc, x, val) \ 2213 do { \ 2214 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2215 (0xFFFF0000 & x), 4); \ 2216 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2217 } while(0) 2218 2219/* 2220 * This magic number is written to the firmware mailbox at 0xb50 2221 * before a software reset is issued. After the internal firmware 2222 * has completed its initialization it will write the opposite of 2223 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2224 * allowing the driver to synchronize with the firmware. 2225 / 2226#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2227* 2228typedef struct { 2229 uint32_t bge_addr_hi; 2230 uint32_t bge_addr_lo; 2231} bge_hostaddr; 2232 2233#define BGE_HOSTADDR(x, y) \ 2234 do { \ 2235 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2236 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2237 } while(0) 2238 2239#define BGE_ADDR_LO(y) \ 2240 ((uint64_t) (y) & 0xFFFFFFFF) 2241#define BGE_ADDR_HI(y) \ 2242 ((uint64_t) (y) >> 32) 2243 2244/* Ring control block structure / 2245struct bge_rcb { 2246* bge_hostaddr bge_hostaddr; 2247 uint32_t bge_maxlen_flags; 2248 uint32_t bge_nicaddr; 2249}; 2250 2251#define RCB_WRITE_4(sc, rcb, offset, val) \ 2252 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2253#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 2254 2255#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2256#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2257 2258struct bge_tx_bd { 2259 bge_hostaddr bge_addr; 2260#if BYTE_ORDER == LITTLE_ENDIAN 2261 uint16_t bge_flags; 2262 uint16_t bge_len; 2263 uint16_t bge_vlan_tag; 2264 uint16_t bge_mss; 2265#else 2266 uint16_t bge_len; 2267 uint16_t bge_flags; 2268 uint16_t bge_mss; 2269 uint16_t bge_vlan_tag; 2270#endif 2271}; 2272 2273#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2274#define BGE_TXBDFLAG_IP_CSUM 0x0002 2275#define BGE_TXBDFLAG_END 0x0004 2276#define BGE_TXBDFLAG_IP_FRAG 0x0008 2277#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 / 2278#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2279#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 / 5717 / 2280#define BGE_TXBDFLAG_SNAP 0x0020 / 5717 / 2281#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2282#define BGE_TXBDFLAG_COAL_NOW 0x0080 2283#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2284#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2285#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 / 5717 / 2286#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 / 5717 / 2287#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2288#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 / 5717 / 2289#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 / 5717 / 2290#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 / 5717 / 2291#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2292#define BGE_TXBDFLAG_NO_CRC 0x8000 2293* 2294#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 / 2295/ Bits [1:0] of the MSS header length. / 2296#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 / 5717 / 2297* 2298#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2299 BGE_SEND_RING_1_TO_4 + \ 2300 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2301 2302struct bge_rx_bd { 2303 bge_hostaddr bge_addr; 2304#if BYTE_ORDER == LITTLE_ENDIAN 2305 uint16_t bge_len; 2306 uint16_t bge_idx; 2307 uint16_t bge_flags; 2308 uint16_t bge_type; 2309 uint16_t bge_tcp_udp_csum; 2310 uint16_t bge_ip_csum; 2311 uint16_t bge_vlan_tag; 2312 uint16_t bge_error_flag; 2313#else 2314 uint16_t bge_idx; 2315 uint16_t bge_len; 2316 uint16_t bge_type; 2317 uint16_t bge_flags; 2318 uint16_t bge_ip_csum; 2319 uint16_t bge_tcp_udp_csum; 2320 uint16_t bge_error_flag; 2321 uint16_t bge_vlan_tag; 2322#endif 2323 uint32_t bge_rsvd; 2324 uint32_t bge_opaque; 2325}; 2326 2327struct bge_extrx_bd { 2328 bge_hostaddr bge_addr1; 2329 bge_hostaddr bge_addr2; 2330 bge_hostaddr bge_addr3; 2331#if BYTE_ORDER == LITTLE_ENDIAN 2332 uint16_t bge_len2; 2333 uint16_t bge_len1; 2334 uint16_t bge_rsvd1; 2335 uint16_t bge_len3; 2336#else 2337 uint16_t bge_len1; 2338 uint16_t bge_len2; 2339 uint16_t bge_len3; 2340 uint16_t bge_rsvd1; 2341#endif 2342 bge_hostaddr bge_addr0; 2343#if BYTE_ORDER == LITTLE_ENDIAN 2344 uint16_t bge_len0; 2345 uint16_t bge_idx; 2346 uint16_t bge_flags; 2347 uint16_t bge_type; 2348 uint16_t bge_tcp_udp_csum; 2349 uint16_t bge_ip_csum; 2350 uint16_t bge_vlan_tag; 2351 uint16_t bge_error_flag; 2352#else 2353 uint16_t bge_idx; 2354 uint16_t bge_len0; 2355 uint16_t bge_type; 2356 uint16_t bge_flags; 2357 uint16_t bge_ip_csum; 2358 uint16_t bge_tcp_udp_csum; 2359 uint16_t bge_error_flag; 2360 uint16_t bge_vlan_tag; 2361#endif 2362 uint32_t bge_rsvd0; 2363 uint32_t bge_opaque; 2364}; 2365 2366#define BGE_RXBDFLAG_END 0x0004 2367#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2368#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2369#define BGE_RXBDFLAG_ERROR 0x0400 2370#define BGE_RXBDFLAG_MINI_RING 0x0800 2371#define BGE_RXBDFLAG_IP_CSUM 0x1000 2372#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2373#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2374#define BGE_RXBDFLAG_IPV6 0x8000 2375 2376#define BGE_RXERRFLAG_BAD_CRC 0x0001 2377#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2378#define BGE_RXERRFLAG_LINK_LOST 0x0004 2379#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2380#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2381#define BGE_RXERRFLAG_RUNT 0x0020 2382#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2383#define BGE_RXERRFLAG_GIANT 0x0080 2384#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 / 2385* 2386struct bge_sts_idx { 2387#if BYTE_ORDER == LITTLE_ENDIAN 2388 uint16_t bge_rx_prod_idx; 2389 uint16_t bge_tx_cons_idx; 2390#else 2391 uint16_t bge_tx_cons_idx; 2392 uint16_t bge_rx_prod_idx; 2393#endif 2394}; 2395 2396struct bge_status_block { 2397 uint32_t bge_status; 2398 uint32_t bge_status_tag; 2399#if BYTE_ORDER == LITTLE_ENDIAN 2400 uint16_t bge_rx_jumbo_cons_idx; 2401 uint16_t bge_rx_std_cons_idx; 2402 uint16_t bge_rx_mini_cons_idx; 2403 uint16_t bge_rsvd1; 2404#else 2405 uint16_t bge_rx_std_cons_idx; 2406 uint16_t bge_rx_jumbo_cons_idx; 2407 uint16_t bge_rsvd1; 2408 uint16_t bge_rx_mini_cons_idx; 2409#endif 2410 struct bge_sts_idx bge_idx[16]; 2411}; 2412 2413#define BGE_STATFLAG_UPDATED 0x00000001 2414#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2415#define BGE_STATFLAG_ERROR 0x00000004 2416 2417 2418/* 2419 * Broadcom Vendor ID 2420 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2421 * even though they're now manufactured by Broadcom) 2422 / 2423#define BCOM_VENDORID 0x14E4 2424#define BCOM_DEVICEID_BCM5700 0x1644 2425#define BCOM_DEVICEID_BCM5701 0x1645 2426#define BCOM_DEVICEID_BCM5702 0x1646 2427#define BCOM_DEVICEID_BCM5702X 0x16A6 2428#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2429#define BCOM_DEVICEID_BCM5703 0x1647 2430#define BCOM_DEVICEID_BCM5703X 0x16A7 2431#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2432#define BCOM_DEVICEID_BCM5704C 0x1648 2433#define BCOM_DEVICEID_BCM5704S 0x16A8 2434#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2435#define BCOM_DEVICEID_BCM5705 0x1653 2436#define BCOM_DEVICEID_BCM5705K 0x1654 2437#define BCOM_DEVICEID_BCM5705F 0x166E 2438#define BCOM_DEVICEID_BCM5705M 0x165D 2439#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2440#define BCOM_DEVICEID_BCM5714C 0x1668 2441#define BCOM_DEVICEID_BCM5714S 0x1669 2442#define BCOM_DEVICEID_BCM5715 0x1678 2443#define BCOM_DEVICEID_BCM5715S 0x1679 2444#define BCOM_DEVICEID_BCM5717 0x1655 2445#define BCOM_DEVICEID_BCM5718 0x1656 2446#define BCOM_DEVICEID_BCM5719 0x1657 2447#define BCOM_DEVICEID_BCM5720_PP 0x1658 / Not released to public. / 2448#define BCOM_DEVICEID_BCM5720 0x165F 2449#define BCOM_DEVICEID_BCM5721 0x1659 2450#define BCOM_DEVICEID_BCM5722 0x165A 2451#define BCOM_DEVICEID_BCM5723 0x165B 2452#define BCOM_DEVICEID_BCM5750 0x1676 2453#define BCOM_DEVICEID_BCM5750M 0x167C 2454#define BCOM_DEVICEID_BCM5751 0x1677 2455#define BCOM_DEVICEID_BCM5751F 0x167E 2456#define BCOM_DEVICEID_BCM5751M 0x167D 2457#define BCOM_DEVICEID_BCM5752 0x1600 2458#define BCOM_DEVICEID_BCM5752M 0x1601 2459#define BCOM_DEVICEID_BCM5753 0x16F7 2460#define BCOM_DEVICEID_BCM5753F 0x16FE 2461#define BCOM_DEVICEID_BCM5753M 0x16FD 2462#define BCOM_DEVICEID_BCM5754 0x167A 2463#define BCOM_DEVICEID_BCM5754M 0x1672 2464#define BCOM_DEVICEID_BCM5755 0x167B 2465#define BCOM_DEVICEID_BCM5755M 0x1673 2466#define BCOM_DEVICEID_BCM5756 0x1674 2467#define BCOM_DEVICEID_BCM5761 0x1681 2468#define BCOM_DEVICEID_BCM5761E 0x1680 2469#define BCOM_DEVICEID_BCM5761S 0x1688 2470#define BCOM_DEVICEID_BCM5761SE 0x1689 2471#define BCOM_DEVICEID_BCM5764 0x1684 2472#define BCOM_DEVICEID_BCM5780 0x166A 2473#define BCOM_DEVICEID_BCM5780S 0x166B 2474#define BCOM_DEVICEID_BCM5781 0x16DD 2475#define BCOM_DEVICEID_BCM5782 0x1696 2476#define BCOM_DEVICEID_BCM5784 0x1698 2477#define BCOM_DEVICEID_BCM5785F 0x16a0 2478#define BCOM_DEVICEID_BCM5785G 0x1699 2479#define BCOM_DEVICEID_BCM5786 0x169A 2480#define BCOM_DEVICEID_BCM5787 0x169B 2481#define BCOM_DEVICEID_BCM5787M 0x1693 2482#define BCOM_DEVICEID_BCM5787F 0x167f 2483#define BCOM_DEVICEID_BCM5788 0x169C 2484#define BCOM_DEVICEID_BCM5789 0x169D 2485#define BCOM_DEVICEID_BCM5901 0x170D 2486#define BCOM_DEVICEID_BCM5901A2 0x170E 2487#define BCOM_DEVICEID_BCM5903M 0x16FF 2488#define BCOM_DEVICEID_BCM5906 0x1712 2489#define BCOM_DEVICEID_BCM5906M 0x1713 2490#define BCOM_DEVICEID_BCM57760 0x1690 2491#define BCOM_DEVICEID_BCM57761 0x16B0 2492#define BCOM_DEVICEID_BCM57762 0x1682 2493#define BCOM_DEVICEID_BCM57765 0x16B4 2494#define BCOM_DEVICEID_BCM57766 0x1686 2495#define BCOM_DEVICEID_BCM57780 0x1692 2496#define BCOM_DEVICEID_BCM57781 0x16B1 2497#define BCOM_DEVICEID_BCM57785 0x16B5 2498#define BCOM_DEVICEID_BCM57788 0x1691 2499#define BCOM_DEVICEID_BCM57790 0x1694 2500#define BCOM_DEVICEID_BCM57791 0x16B2 2501#define BCOM_DEVICEID_BCM57795 0x16B6 2502* 2503/* 2504 * Alteon AceNIC PCI vendor/device ID. 2505 / 2506#define ALTEON_VENDORID 0x12AE 2507#define ALTEON_DEVICEID_ACENIC 0x0001 2508#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2509#define ALTEON_DEVICEID_BCM5700 0x0003 2510#define ALTEON_DEVICEID_BCM5701 0x0004 2511* 2512/* 2513 * 3Com 3c996 PCI vendor/device ID. 2514 / 2515#define TC_VENDORID 0x10B7 2516#define TC_DEVICEID_3C996 0x0003 2517* 2518/* 2519 * SysKonnect PCI vendor ID 2520 / 2521#define SK_VENDORID 0x1148 2522#define SK_DEVICEID_ALTIMA 0x4400 2523#define SK_SUBSYSID_9D21 0x4421 2524#define SK_SUBSYSID_9D41 0x4441 2525* 2526/* 2527 * Altima PCI vendor/device ID. 2528 / 2529#define ALTIMA_VENDORID 0x173b 2530#define ALTIMA_DEVICE_AC1000 0x03e8 2531#define ALTIMA_DEVICE_AC1002 0x03e9 2532#define ALTIMA_DEVICE_AC9100 0x03ea 2533* 2534/* 2535 * Dell PCI vendor ID 2536 / 2537* 2538#define DELL_VENDORID 0x1028 2539 2540/* 2541 * Apple PCI vendor ID. 2542 / 2543#define APPLE_VENDORID 0x106b 2544#define APPLE_DEVICE_BCM5701 0x1645 2545* 2546/* 2547 * Sun PCI vendor ID 2548 / 2549#define SUN_VENDORID 0x108e 2550* 2551/* 2552 * Fujitsu vendor/device IDs 2553 / 2554#define FJTSU_VENDORID 0x10cf 2555#define FJTSU_DEVICEID_PW008GE5 0x11a1 2556#define FJTSU_DEVICEID_PW008GE4 0x11a2 2557#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2558* 2559/* 2560 * Offset of MAC address inside EEPROM. 2561 / 2562#define BGE_EE_MAC_OFFSET 0x7C 2563#define BGE_EE_MAC_OFFSET_5906 0x10 2564#define BGE_EE_HWCFG_OFFSET 0xC8 2565* 2566#define BGE_HWCFG_VOLTAGE 0x00000003 2567#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2568#define BGE_HWCFG_MEDIA 0x00000030 2569#define BGE_HWCFG_ASF 0x00000080 2570 2571#define BGE_VOLTAGE_1POINT3 0x00000000 2572#define BGE_VOLTAGE_1POINT8 0x00000001 2573 2574#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2575#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2576#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2577 2578#define BGE_MEDIA_UNSPEC 0x00000000 2579#define BGE_MEDIA_COPPER 0x00000010 2580#define BGE_MEDIA_FIBER 0x00000020 2581 2582#define BGE_TICKS_PER_SEC 1000000 2583 2584/* 2585 * Ring size constants. 2586 / 2587#define BGE_EVENT_RING_CNT 256 2588#define BGE_CMD_RING_CNT 64 2589#define BGE_STD_RX_RING_CNT 512 2590#define BGE_JUMBO_RX_RING_CNT 256 2591#define BGE_MINI_RX_RING_CNT 1024 2592#define BGE_RETURN_RING_CNT 1024 2593* 2594/* 5705 has smaller return ring size / 2595* 2596#define BGE_RETURN_RING_CNT_5705 512 2597 2598/* 2599 * Possible TX ring sizes. 2600 / 2601#define BGE_TX_RING_CNT_128 128 2602#define BGE_TX_RING_BASE_128 0x3800 2603* 2604#define BGE_TX_RING_CNT_256 256 2605#define BGE_TX_RING_BASE_256 0x3000 2606 2607#define BGE_TX_RING_CNT_512 512 2608#define BGE_TX_RING_BASE_512 0x2000 2609 2610#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2611#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2612 2613/* 2614 * Tigon III statistics counters. 2615 / 2616/ Statistics maintained MAC Receive block. / 2617struct bge_rx_mac_stats { 2618* bge_hostaddr ifHCInOctets; 2619 bge_hostaddr Reserved1; 2620 bge_hostaddr etherStatsFragments; 2621 bge_hostaddr ifHCInUcastPkts; 2622 bge_hostaddr ifHCInMulticastPkts; 2623 bge_hostaddr ifHCInBroadcastPkts; 2624 bge_hostaddr dot3StatsFCSErrors; 2625 bge_hostaddr dot3StatsAlignmentErrors; 2626 bge_hostaddr xonPauseFramesReceived; 2627 bge_hostaddr xoffPauseFramesReceived; 2628 bge_hostaddr macControlFramesReceived; 2629 bge_hostaddr xoffStateEntered; 2630 bge_hostaddr dot3StatsFramesTooLong; 2631 bge_hostaddr etherStatsJabbers; 2632 bge_hostaddr etherStatsUndersizePkts; 2633 bge_hostaddr inRangeLengthError; 2634 bge_hostaddr outRangeLengthError; 2635 bge_hostaddr etherStatsPkts64Octets; 2636 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2637 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2638 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2639 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2640 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2641 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2642 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2643 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2644 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2645}; 2646 2647 2648/* Statistics maintained MAC Transmit block. / 2649struct bge_tx_mac_stats { 2650* bge_hostaddr ifHCOutOctets; 2651 bge_hostaddr Reserved2; 2652 bge_hostaddr etherStatsCollisions; 2653 bge_hostaddr outXonSent; 2654 bge_hostaddr outXoffSent; 2655 bge_hostaddr flowControlDone; 2656 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2657 bge_hostaddr dot3StatsSingleCollisionFrames; 2658 bge_hostaddr dot3StatsMultipleCollisionFrames; 2659 bge_hostaddr dot3StatsDeferredTransmissions; 2660 bge_hostaddr Reserved3; 2661 bge_hostaddr dot3StatsExcessiveCollisions; 2662 bge_hostaddr dot3StatsLateCollisions; 2663 bge_hostaddr dot3Collided2Times; 2664 bge_hostaddr dot3Collided3Times; 2665 bge_hostaddr dot3Collided4Times; 2666 bge_hostaddr dot3Collided5Times; 2667 bge_hostaddr dot3Collided6Times; 2668 bge_hostaddr dot3Collided7Times; 2669 bge_hostaddr dot3Collided8Times; 2670 bge_hostaddr dot3Collided9Times; 2671 bge_hostaddr dot3Collided10Times; 2672 bge_hostaddr dot3Collided11Times; 2673 bge_hostaddr dot3Collided12Times; 2674 bge_hostaddr dot3Collided13Times; 2675 bge_hostaddr dot3Collided14Times; 2676 bge_hostaddr dot3Collided15Times; 2677 bge_hostaddr ifHCOutUcastPkts; 2678 bge_hostaddr ifHCOutMulticastPkts; 2679 bge_hostaddr ifHCOutBroadcastPkts; 2680 bge_hostaddr dot3StatsCarrierSenseErrors; 2681 bge_hostaddr ifOutDiscards; 2682 bge_hostaddr ifOutErrors; 2683}; 2684 2685/* Stats counters access through registers / 2686struct bge_mac_stats { 2687* /* TX MAC statistics / 2688* uint64_t ifHCOutOctets; 2689 uint64_t Reserved0; 2690 uint64_t etherStatsCollisions; 2691 uint64_t outXonSent; 2692 uint64_t outXoffSent; 2693 uint64_t Reserved1; 2694 uint64_t dot3StatsInternalMacTransmitErrors; 2695 uint64_t dot3StatsSingleCollisionFrames; 2696 uint64_t dot3StatsMultipleCollisionFrames; 2697 uint64_t dot3StatsDeferredTransmissions; 2698 uint64_t Reserved2; 2699 uint64_t dot3StatsExcessiveCollisions; 2700 uint64_t dot3StatsLateCollisions; 2701 uint64_t Reserved3[14]; 2702 uint64_t ifHCOutUcastPkts; 2703 uint64_t ifHCOutMulticastPkts; 2704 uint64_t ifHCOutBroadcastPkts; 2705 uint64_t Reserved4[2]; 2706 /* RX MAC statistics / 2707* uint64_t ifHCInOctets; 2708 uint64_t Reserved5; 2709 uint64_t etherStatsFragments; 2710 uint64_t ifHCInUcastPkts; 2711 uint64_t ifHCInMulticastPkts; 2712 uint64_t ifHCInBroadcastPkts; 2713 uint64_t dot3StatsFCSErrors; 2714 uint64_t dot3StatsAlignmentErrors; 2715 uint64_t xonPauseFramesReceived; 2716 uint64_t xoffPauseFramesReceived; 2717 uint64_t macControlFramesReceived; 2718 uint64_t xoffStateEntered; 2719 uint64_t dot3StatsFramesTooLong; 2720 uint64_t etherStatsJabbers; 2721 uint64_t etherStatsUndersizePkts; 2722 /* Receive List Placement control / 2723* uint64_t FramesDroppedDueToFilters; 2724 uint64_t DmaWriteQueueFull; 2725 uint64_t DmaWriteHighPriQueueFull; 2726 uint64_t NoMoreRxBDs; 2727 uint64_t InputDiscards; 2728 uint64_t InputErrors; 2729 uint64_t RecvThresholdHit; 2730}; 2731 2732struct bge_stats { 2733 uint8_t Reserved0[256]; 2734 2735 /* Statistics maintained by Receive MAC. / 2736* struct bge_rx_mac_stats rxstats; 2737 2738 bge_hostaddr Unused1[37]; 2739 2740 /* Statistics maintained by Transmit MAC. / 2741* struct bge_tx_mac_stats txstats; 2742 2743 bge_hostaddr Unused2[31]; 2744 2745 /* Statistics maintained by Receive List Placement. / 2746* bge_hostaddr COSIfHCInPkts[16]; 2747 bge_hostaddr COSFramesDroppedDueToFilters; 2748 bge_hostaddr nicDmaWriteQueueFull; 2749 bge_hostaddr nicDmaWriteHighPriQueueFull; 2750 bge_hostaddr nicNoMoreRxBDs; 2751 bge_hostaddr ifInDiscards; 2752 bge_hostaddr ifInErrors; 2753 bge_hostaddr nicRecvThresholdHit; 2754 2755 bge_hostaddr Unused3[9]; 2756 2757 /* Statistics maintained by Send Data Initiator. / 2758* bge_hostaddr COSIfHCOutPkts[16]; 2759 bge_hostaddr nicDmaReadQueueFull; 2760 bge_hostaddr nicDmaReadHighPriQueueFull; 2761 bge_hostaddr nicSendDataCompQueueFull; 2762 2763 /* Statistics maintained by Host Coalescing. / 2764* bge_hostaddr nicRingSetSendProdIndex; 2765 bge_hostaddr nicRingStatusUpdate; 2766 bge_hostaddr nicInterrupts; 2767 bge_hostaddr nicAvoidedInterrupts; 2768 bge_hostaddr nicSendThresholdHit; 2769 2770 uint8_t Reserved4[320]; 2771}; 2772 2773/* 2774 * Tigon general information block. This resides in host memory 2775 * and contains the status counters, ring control blocks and 2776 * producer pointers. 2777 / 2778* 2779struct bge_gib { 2780 struct bge_stats bge_stats; 2781 struct bge_rcb bge_tx_rcb[16]; 2782 struct bge_rcb bge_std_rx_rcb; 2783 struct bge_rcb bge_jumbo_rx_rcb; 2784 struct bge_rcb bge_mini_rx_rcb; 2785 struct bge_rcb bge_return_rcb; 2786}; 2787 2788#define BGE_FRAMELEN 1518 2789#define BGE_MAX_FRAMELEN 1536 2790#define BGE_JUMBO_FRAMELEN 9018 2791#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2792#define BGE_MIN_FRAMELEN 60 2793 2794/* 2795 * Other utility macros. 2796 / 2797#define BGE_INC(x, y) (x) = (x + 1) % y 2798* 2799/* 2800 * BAR0 MAC register access macros. The Tigon always uses memory mapped register 2801 * accesses and all registers must be accessed with 32 bit operations. 2802 / 2803* 2804#define CSR_WRITE_4(sc, reg, val) \ 2805 bus_write_4(sc->bge_res, reg, val) 2806 2807#define CSR_READ_4(sc, reg) \ 2808 bus_read_4(sc->bge_res, reg) 2809 2810#define BGE_SETBIT(sc, reg, x) \ 2811 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2812#define BGE_CLRBIT(sc, reg, x) \ 2813 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2814 2815/* BAR2 APE register access macros. / 2816#define APE_WRITE_4(sc, reg, val) \ 2817* bus_write_4(sc->bge_res2, reg, val) 2818 2819#define APE_READ_4(sc, reg) \ 2820 bus_read_4(sc->bge_res2, reg) 2821 2822#define APE_SETBIT(sc, reg, x) \ 2823 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) \| (x))) 2824#define APE_CLRBIT(sc, reg, x) \ 2825 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2826 2827#define PCI_SETBIT(dev, reg, x, s) \ 2828 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2829#define PCI_CLRBIT(dev, reg, x, s) \ 2830 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2831 2832/* 2833 * Memory management stuff. 2834 / 2835* 2836#define BGE_NSEG_JUMBO 4 2837#define BGE_NSEG_NEW 32 2838#define BGE_TSOSEG_SZ 4096 2839 2840/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2841#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2842#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2843#else 2844#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2845#endif 2846* 2847/* 2848 * Ring structures. Most of these reside in host memory and we tell 2849 * the NIC where they are via the ring control blocks. The exceptions 2850 * are the tx and command rings, which live in NIC memory and which 2851 * we access via the shared memory window. 2852 / 2853* 2854struct bge_ring_data { 2855 struct bge_rx_bd bge_rx_std_ring; 2856* bus_addr_t bge_rx_std_ring_paddr; 2857 struct bge_extrx_bd bge_rx_jumbo_ring; 2858* bus_addr_t bge_rx_jumbo_ring_paddr; 2859 struct bge_rx_bd bge_rx_return_ring; 2860* bus_addr_t bge_rx_return_ring_paddr; 2861 struct bge_tx_bd bge_tx_ring; 2862* bus_addr_t bge_tx_ring_paddr; 2863 struct bge_status_block bge_status_block; 2864* bus_addr_t bge_status_block_paddr; 2865 struct bge_stats bge_stats; 2866* bus_addr_t bge_stats_paddr; 2867 struct bge_gib bge_info; 2868}; 2869 2870#define BGE_STD_RX_RING_SZ \ 2871 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2872#define BGE_JUMBO_RX_RING_SZ \ 2873 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2874#define BGE_TX_RING_SZ \ 2875 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2876#define BGE_RX_RTN_RING_SZ(x) \ 2877 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2878 2879#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2880 2881#define BGE_STATS_SZ sizeof (struct bge_stats) 2882 2883/* 2884 * Mbuf pointers. We need these to keep track of the virtual addresses 2885 * of our mbuf chains since we can only convert from physical to virtual, 2886 * not the other way around. 2887 / 2888struct bge_chain_data { 2889* bus_dma_tag_t bge_parent_tag; 2890 bus_dma_tag_t bge_buffer_tag; 2891 bus_dma_tag_t bge_rx_std_ring_tag; 2892 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2893 bus_dma_tag_t bge_rx_return_ring_tag; 2894 bus_dma_tag_t bge_tx_ring_tag; 2895 bus_dma_tag_t bge_status_tag; 2896 bus_dma_tag_t bge_stats_tag; 2897 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2898* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2899* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2900* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2901 bus_dmamap_t bge_rx_std_sparemap; 2902 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2903 bus_dmamap_t bge_rx_jumbo_sparemap; 2904 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2905 bus_dmamap_t bge_rx_std_ring_map; 2906 bus_dmamap_t bge_rx_jumbo_ring_map; 2907 bus_dmamap_t bge_tx_ring_map; 2908 bus_dmamap_t bge_rx_return_ring_map; 2909 bus_dmamap_t bge_status_map; 2910 bus_dmamap_t bge_stats_map; 2911 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2912* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2913* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2914* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2915 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2916}; 2917 2918struct bge_dmamap_arg { 2919 bus_addr_t bge_busaddr; 2920}; 2921 2922#define BGE_HWREV_TIGON 0x01 2923#define BGE_HWREV_TIGON_II 0x02 2924#define BGE_TIMEOUT 100000 2925#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2926#define BGE_TX_TIMEOUT 5 2927* 2928struct bge_bcom_hack { 2929 int reg; 2930 int val; 2931}; 2932 2933#define ASF_ENABLE 1 2934#define ASF_NEW_HANDSHAKE 2 2935#define ASF_STACKUP 4 2936 2937struct bge_softc { 2938 struct ifnet bge_ifp; / interface info / 2939* device_t bge_dev; 2940 struct mtx bge_mtx; 2941 device_t bge_miibus; 2942 void bge_intrhand; 2943* struct resource bge_irq; 2944* struct resource bge_res; / MAC mapped I/O / 2945* struct resource bge_res2; / APE mapped I/O / 2946* struct ifmedia bge_ifmedia; /* TBI media info / 2947* int bge_expcap; 2948 int bge_expmrq; 2949 int bge_msicap; 2950 int bge_pcixcap; 2951 uint32_t bge_flags; 2952#define BGE_FLAG_TBI 0x00000001 2953#define BGE_FLAG_JUMBO 0x00000002 2954#define BGE_FLAG_JUMBO_STD 0x00000004 2955#define BGE_FLAG_EADDR 0x00000008 2956#define BGE_FLAG_MII_SERDES 0x00000010 2957#define BGE_FLAG_CPMU_PRESENT 0x00000020 2958#define BGE_FLAG_TAGGED_STATUS 0x00000040 2959#define BGE_FLAG_APE 0x00000080 2960#define BGE_FLAG_MSI 0x00000100 2961#define BGE_FLAG_PCIX 0x00000200 2962#define BGE_FLAG_PCIE 0x00000400 2963#define BGE_FLAG_TSO 0x00000800 2964#define BGE_FLAG_TSO3 0x00001000 2965#define BGE_FLAG_JUMBO_FRAME 0x00002000 2966#define BGE_FLAG_5700_FAMILY 0x00010000 2967#define BGE_FLAG_5705_PLUS 0x00020000 2968#define BGE_FLAG_5714_FAMILY 0x00040000 2969#define BGE_FLAG_575X_PLUS 0x00080000 2970#define BGE_FLAG_5755_PLUS 0x00100000 2971#define BGE_FLAG_5788 0x00200000 2972#define BGE_FLAG_5717_PLUS 0x00400000 2973#define BGE_FLAG_57765_PLUS 0x00800000 2974#define BGE_FLAG_40BIT_BUG 0x01000000 2975#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2976#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2977#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2978#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2979#define BGE_FLAG_MBOX_REORDER 0x20000000 2980#define BGE_FLAG_RDMA_BUG 0x40000000 2981 uint32_t bge_mfw_flags; /* Management F/W flags / 2982#define BGE_MFW_ON_RXCPU 0x00000001 2983#define BGE_MFW_ON_APE 0x00000002 2984#define BGE_MFW_TYPE_NCSI 0x00000004 2985#define BGE_MFW_TYPE_DASH 0x00000008 2986* int bge_phy_ape_lock; 2987 int bge_func_addr; 2988 int bge_phy_addr; 2989 uint32_t bge_phy_flags; 2990#define BGE_PHY_NO_WIRESPEED 0x00000001 2991#define BGE_PHY_ADC_BUG 0x00000002 2992#define BGE_PHY_5704_A0_BUG 0x00000004 2993#define BGE_PHY_JITTER_BUG 0x00000008 2994#define BGE_PHY_BER_BUG 0x00000010 2995#define BGE_PHY_ADJUST_TRIM 0x00000020 2996#define BGE_PHY_CRC_BUG 0x00000040 2997#define BGE_PHY_NO_3LED 0x00000080 2998 uint32_t bge_chipid; 2999 uint32_t bge_asicrev; 3000 uint32_t bge_chiprev; 3001 uint8_t bge_asf_mode; 3002 uint8_t bge_asf_count; 3003 uint16_t bge_mps; 3004 struct bge_ring_data bge_ldata; /* rings / 3005* struct bge_chain_data bge_cdata; /* mbufs / 3006* uint16_t bge_tx_saved_considx; 3007 uint16_t bge_rx_saved_considx; 3008 uint16_t bge_ev_saved_considx; 3009 uint16_t bge_return_ring_cnt; 3010 uint16_t bge_std; /* current std ring head / 3011* uint16_t bge_jumbo; /* current jumo ring head / 3012* uint32_t bge_stat_ticks; 3013 uint32_t bge_rx_coal_ticks; 3014 uint32_t bge_tx_coal_ticks; 3015 uint32_t bge_tx_prodidx; 3016 uint32_t bge_rx_max_coal_bds; 3017 uint32_t bge_tx_max_coal_bds; 3018 uint32_t bge_mi_mode; 3019 int bge_if_flags; 3020 int bge_txcnt; 3021 int bge_link; /* link state / 3022* int bge_link_evt; /* pending link event / 3023* int bge_timer; 3024 int bge_forced_collapse; 3025 int bge_forced_udpcsum; 3026 int bge_msi; 3027 int bge_csum_features; 3028 struct callout bge_stat_ch; 3029 uint32_t bge_rx_discards; 3030 uint32_t bge_rx_inerrs; 3031 uint32_t bge_rx_nobds; 3032 uint32_t bge_tx_discards; 3033 uint32_t bge_tx_collisions; 3034#ifdef DEVICE_POLLING 3035 int rxcycles; 3036#endif /* DEVICE_POLLING / 3037* struct bge_mac_stats bge_mac_stats; 3038 struct task bge_intr_task; 3039 struct taskqueue bge_tq; 3040}; 3041* 3042#define BGE_LOCK_INIT(_sc, _name) \ 3043 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 3044#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 3045#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 3046#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 3047#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)	1336/* 1337 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1338 / 1339#define BGE_MBCF_MODE 0x3800 1340#define BGE_MBCF_STATUS 0x3804 1341* 1342/* Mbuf Cluster Free mode register / 1343#define BGE_MBCFMODE_RESET 0x00000001 1344#define BGE_MBCFMODE_ENABLE 0x00000002 1345#define BGE_MBCFMODE_ATTN 0x00000004 1346* 1347/* Mbuf Cluster Free status register / 1348#define BGE_MBCFSTAT_ERROR 0x00000004 1349* 1350/* 1351 * Host Coalescing Control registers 1352 / 1353#define BGE_HCC_MODE 0x3C00 1354#define BGE_HCC_STATUS 0x3C04 1355#define BGE_HCC_RX_COAL_TICKS 0x3C08 1356#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1357#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1358#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1359#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1360#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1361#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1362#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1363#define BGE_HCC_STATS_TICKS 0x3C28 1364#define BGE_HCC_STATS_ADDR_HI 0x3C30 1365#define BGE_HCC_STATS_ADDR_LO 0x3C34 1366#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1367#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1368#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1369#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1370#define BGE_FLOW_ATTN 0x3C48 1371#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1372#define BGE_HCC_STD_BD_CONS 0x3C54 1373#define BGE_HCC_MINI_BD_CONS 0x3C58 1374#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1375#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1376#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1377#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1378#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1379#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1380#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1381#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1382#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1383#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1384#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1385#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1386#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1387#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1388#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1389#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1390#define BGE_HCC_TX_BD_CONS0 0x3CC0 1391#define BGE_HCC_TX_BD_CONS1 0x3CC4 1392#define BGE_HCC_TX_BD_CONS2 0x3CC8 1393#define BGE_HCC_TX_BD_CONS3 0x3CCC 1394#define BGE_HCC_TX_BD_CONS4 0x3CD0 1395#define BGE_HCC_TX_BD_CONS5 0x3CD4 1396#define BGE_HCC_TX_BD_CONS6 0x3CD8 1397#define BGE_HCC_TX_BD_CONS7 0x3CDC 1398#define BGE_HCC_TX_BD_CONS8 0x3CE0 1399#define BGE_HCC_TX_BD_CONS9 0x3CE4 1400#define BGE_HCC_TX_BD_CONS10 0x3CE8 1401#define BGE_HCC_TX_BD_CONS11 0x3CEC 1402#define BGE_HCC_TX_BD_CONS12 0x3CF0 1403#define BGE_HCC_TX_BD_CONS13 0x3CF4 1404#define BGE_HCC_TX_BD_CONS14 0x3CF8 1405#define BGE_HCC_TX_BD_CONS15 0x3CFC 1406* 1407 1408/* Host coalescing mode register / 1409#define BGE_HCCMODE_RESET 0x00000001 1410#define BGE_HCCMODE_ENABLE 0x00000002 1411#define BGE_HCCMODE_ATTN 0x00000004 1412#define BGE_HCCMODE_COAL_NOW 0x00000008 1413#define BGE_HCCMODE_MSI_BITS 0x00000070 1414#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1415* 1416#define BGE_STATBLKSZ_FULL 0x00000000 1417#define BGE_STATBLKSZ_64BYTE 0x00000080 1418#define BGE_STATBLKSZ_32BYTE 0x00000100 1419 1420/* Host coalescing status register / 1421#define BGE_HCCSTAT_ERROR 0x00000004 1422* 1423/* Flow attention register / 1424#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1425#define BGE_FLOWATTN_MEMARB 0x00000080 1426#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1427#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1428#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1429#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1430#define BGE_FLOWATTN_RDBDI 0x00080000 1431#define BGE_FLOWATTN_RXLS 0x00100000 1432#define BGE_FLOWATTN_RXLP 0x00200000 1433#define BGE_FLOWATTN_RBDC 0x00400000 1434#define BGE_FLOWATTN_RBDI 0x00800000 1435#define BGE_FLOWATTN_SDC 0x08000000 1436#define BGE_FLOWATTN_SDI 0x10000000 1437#define BGE_FLOWATTN_SRS 0x20000000 1438#define BGE_FLOWATTN_SBDC 0x40000000 1439#define BGE_FLOWATTN_SBDI 0x80000000 1440* 1441/* 1442 * Memory arbiter registers 1443 / 1444#define BGE_MARB_MODE 0x4000 1445#define BGE_MARB_STATUS 0x4004 1446#define BGE_MARB_TRAPADDR_HI 0x4008 1447#define BGE_MARB_TRAPADDR_LO 0x400C 1448* 1449/* Memory arbiter mode register / 1450#define BGE_MARBMODE_RESET 0x00000001 1451#define BGE_MARBMODE_ENABLE 0x00000002 1452#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1453#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1454#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1455#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1456#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1457#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1458#define BGE_MARBMODE_PCI_TRAP 0x00000100 1459#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1460#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1461#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1462#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1463#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1464#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1465#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1466#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1467#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1468#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1469#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1470#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1471#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1472#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1473#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1474#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1475#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1476* 1477/* Memory arbiter status register / 1478#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1479#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1480#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1481#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1482#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1483#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1484#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1485#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1486#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1487#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1488#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1489#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1490#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1491#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1492#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1493#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1494#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1495#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1496#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1497#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1498#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1499#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1500#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1501#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1502* 1503/* 1504 * Buffer manager control registers 1505 / 1506#define BGE_BMAN_MODE 0x4400 1507#define BGE_BMAN_STATUS 0x4404 1508#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1509#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1510#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1511#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1512#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1513#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1514#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1515#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1516#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1517#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1518#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1519#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1520#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1521#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1522#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1523#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1524#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1525#define BGE_BMAN_HWDIAG_1 0x444C 1526#define BGE_BMAN_HWDIAG_2 0x4450 1527#define BGE_BMAN_HWDIAG_3 0x4454 1528* 1529/* Buffer manager mode register / 1530#define BGE_BMANMODE_RESET 0x00000001 1531#define BGE_BMANMODE_ENABLE 0x00000002 1532#define BGE_BMANMODE_ATTN 0x00000004 1533#define BGE_BMANMODE_TESTMODE 0x00000008 1534#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1535#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000 1536* 1537/* Buffer manager status register / 1538#define BGE_BMANSTAT_ERRO 0x00000004 1539#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1540* 1541 1542/* 1543 * Read DMA Control registers 1544 / 1545#define BGE_RDMA_MODE 0x4800 1546#define BGE_RDMA_STATUS 0x4804 1547#define BGE_RDMA_RSRVCTRL 0x4900 1548#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910 1549* 1550/* Read DMA mode register / 1551#define BGE_RDMAMODE_RESET 0x00000001 1552#define BGE_RDMAMODE_ENABLE 0x00000002 1553#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1554#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1555#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1556#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1557#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1558#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1559#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1560#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1561#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1562#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1563#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1564#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1565#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1566#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1567#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000 1568#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1569#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1570#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000 1571* 1572/* Read DMA status register / 1573#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1574#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1575#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1576#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1577#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1578#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1579#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1580#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1581* 1582/* Read DMA Reserved Control register / 1583#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1584#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00 1585#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000 1586#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000 1587#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0 1588#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000 1589#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000 1590* 1591#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_512 0x00020000 1592#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000 1593#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000 1594#define BGE_RDMA_TX_LENGTH_WA_5719 0x02000000 1595#define BGE_RDMA_TX_LENGTH_WA_5720 0x00200000 1596 1597/* BD Read DMA Mode register / 1598#define BGE_RDMA_BD_MODE 0x4A00 1599/ BD Read DMA Mode status register / 1600#define BGE_RDMA_BD_STATUS 0x4A04 1601* 1602#define BGE_RDMA_BD_MODE_RESET 0x00000001 1603#define BGE_RDMA_BD_MODE_ENABLE 0x00000002 1604 1605/* Non-LSO Read DMA Mode register / 1606#define BGE_RDMA_NON_LSO_MODE 0x4B00 1607/ Non-LSO Read DMA Mode status register / 1608#define BGE_RDMA_NON_LSO_STATUS 0x4B04 1609* 1610#define BGE_RDMA_NON_LSO_MODE_RESET 0x00000001 1611#define BGE_RDMA_NON_LSO_MODE_ENABLE 0x00000002 1612 1613#define BGE_RDMA_LENGTH 0x4BE0 1614#define BGE_NUM_RDMA_CHANNELS 4 1615 1616/* 1617 * Write DMA control registers 1618 / 1619#define BGE_WDMA_MODE 0x4C00 1620#define BGE_WDMA_STATUS 0x4C04 1621* 1622/* Write DMA mode register / 1623#define BGE_WDMAMODE_RESET 0x00000001 1624#define BGE_WDMAMODE_ENABLE 0x00000002 1625#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1626#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1627#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1628#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1629#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1630#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1631#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1632#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1633#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1634#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1635#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1636* 1637/* Write DMA status register / 1638#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1639#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1640#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1641#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1642#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1643#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1644#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1645#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1646* 1647 1648/* 1649 * RX CPU registers 1650 / 1651#define BGE_RXCPU_MODE 0x5000 1652#define BGE_RXCPU_STATUS 0x5004 1653#define BGE_RXCPU_PC 0x501C 1654* 1655/* RX CPU mode register / 1656#define BGE_RXCPUMODE_RESET 0x00000001 1657#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1658#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1659#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1660#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1661#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1662#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1663#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1664#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1665#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1666#define BGE_RXCPUMODE_HALTCPU 0x00000400 1667#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1668#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1669#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1670* 1671/* RX CPU status register / 1672#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1673#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1674#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1675#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1676#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1677#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1678#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1679#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1680#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1681#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1682#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1683#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1684#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1685#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1686#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1687#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1688#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1689* 1690/* 1691 * V? CPU registers 1692 / 1693#define BGE_VCPU_STATUS 0x5100 1694#define BGE_VCPU_EXT_CTRL 0x6890 1695* 1696#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1697#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1698 1699#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1700#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1701 1702/* 1703 * TX CPU registers 1704 / 1705#define BGE_TXCPU_MODE 0x5400 1706#define BGE_TXCPU_STATUS 0x5404 1707#define BGE_TXCPU_PC 0x541C 1708* 1709/* TX CPU mode register / 1710#define BGE_TXCPUMODE_RESET 0x00000001 1711#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1712#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1713#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1714#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1715#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1716#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1717#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1718#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1719#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1720#define BGE_TXCPUMODE_HALTCPU 0x00000400 1721#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1722#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1723* 1724/* TX CPU status register / 1725#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1726#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1727#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1728#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1729#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1730#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1731#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1732#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1733#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1734#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1735#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1736#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1737#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1738#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1739#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1740#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1741#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1742* 1743 1744/* 1745 * Low priority mailbox registers 1746 / 1747#define BGE_LPMBX_IRQ0_HI 0x5800 1748#define BGE_LPMBX_IRQ0_LO 0x5804 1749#define BGE_LPMBX_IRQ1_HI 0x5808 1750#define BGE_LPMBX_IRQ1_LO 0x580C 1751#define BGE_LPMBX_IRQ2_HI 0x5810 1752#define BGE_LPMBX_IRQ2_LO 0x5814 1753#define BGE_LPMBX_IRQ3_HI 0x5818 1754#define BGE_LPMBX_IRQ3_LO 0x581C 1755#define BGE_LPMBX_GEN0_HI 0x5820 1756#define BGE_LPMBX_GEN0_LO 0x5824 1757#define BGE_LPMBX_GEN1_HI 0x5828 1758#define BGE_LPMBX_GEN1_LO 0x582C 1759#define BGE_LPMBX_GEN2_HI 0x5830 1760#define BGE_LPMBX_GEN2_LO 0x5834 1761#define BGE_LPMBX_GEN3_HI 0x5828 1762#define BGE_LPMBX_GEN3_LO 0x582C 1763#define BGE_LPMBX_GEN4_HI 0x5840 1764#define BGE_LPMBX_GEN4_LO 0x5844 1765#define BGE_LPMBX_GEN5_HI 0x5848 1766#define BGE_LPMBX_GEN5_LO 0x584C 1767#define BGE_LPMBX_GEN6_HI 0x5850 1768#define BGE_LPMBX_GEN6_LO 0x5854 1769#define BGE_LPMBX_GEN7_HI 0x5858 1770#define BGE_LPMBX_GEN7_LO 0x585C 1771#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1772#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1773#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1774#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1775#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1776#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1777#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1778#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1779#define BGE_LPMBX_RX_CONS0_HI 0x5880 1780#define BGE_LPMBX_RX_CONS0_LO 0x5884 1781#define BGE_LPMBX_RX_CONS1_HI 0x5888 1782#define BGE_LPMBX_RX_CONS1_LO 0x588C 1783#define BGE_LPMBX_RX_CONS2_HI 0x5890 1784#define BGE_LPMBX_RX_CONS2_LO 0x5894 1785#define BGE_LPMBX_RX_CONS3_HI 0x5898 1786#define BGE_LPMBX_RX_CONS3_LO 0x589C 1787#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1788#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1789#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1790#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1791#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1792#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1793#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1794#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1795#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1796#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1797#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1798#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1799#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1800#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1801#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1802#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1803#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1804#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1805#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1806#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1807#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1808#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1809#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1810#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1811#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1812#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1813#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1814#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1815#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1816#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1817#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1818#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1819#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1820#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1821#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1822#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1823#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1824#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1825#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1826#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1827#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1828#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1829#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1830#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1831#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1832#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1833#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1834#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1835#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1836#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1837#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1838#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1839#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1840#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1841#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1842#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1843#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1844#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1845#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1846#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1847#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1848#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1849#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1850#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1851#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1852#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1853#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1854#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1855#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1856#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1857#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1858#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1859#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1860#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1861#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1862#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1863#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1864#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1865#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1866#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1867#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1868#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1869#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1870#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1871#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1872#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1873#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1874#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1875* 1876/* 1877 * Flow throw Queue reset register 1878 / 1879#define BGE_FTQ_RESET 0x5C00 1880* 1881#define BGE_FTQRESET_DMAREAD 0x00000002 1882#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1883#define BGE_FTQRESET_DMADONE 0x00000010 1884#define BGE_FTQRESET_SBDC 0x00000020 1885#define BGE_FTQRESET_SDI 0x00000040 1886#define BGE_FTQRESET_WDMA 0x00000080 1887#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1888#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1889#define BGE_FTQRESET_SDC 0x00000400 1890#define BGE_FTQRESET_HCC 0x00000800 1891#define BGE_FTQRESET_TXFIFO 0x00001000 1892#define BGE_FTQRESET_MBC 0x00002000 1893#define BGE_FTQRESET_RBDC 0x00004000 1894#define BGE_FTQRESET_RXLP 0x00008000 1895#define BGE_FTQRESET_RDBDI 0x00010000 1896#define BGE_FTQRESET_RDC 0x00020000 1897#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1898 1899/* 1900 * Message Signaled Interrupt registers 1901 / 1902#define BGE_MSI_MODE 0x6000 1903#define BGE_MSI_STATUS 0x6004 1904#define BGE_MSI_FIFOACCESS 0x6008 1905* 1906/* MSI mode register / 1907#define BGE_MSIMODE_RESET 0x00000001 1908#define BGE_MSIMODE_ENABLE 0x00000002 1909#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1910#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1911* 1912/* MSI status register / 1913#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1914#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1915#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1916#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1917#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1918* 1919 1920/* 1921 * DMA Completion registers 1922 / 1923#define BGE_DMAC_MODE 0x6400 1924* 1925/* DMA Completion mode register / 1926#define BGE_DMACMODE_RESET 0x00000001 1927#define BGE_DMACMODE_ENABLE 0x00000002 1928* 1929 1930/* 1931 * General control registers. 1932 / 1933#define BGE_MODE_CTL 0x6800 1934#define BGE_MISC_CFG 0x6804 1935#define BGE_MISC_LOCAL_CTL 0x6808 1936#define BGE_RX_CPU_EVENT 0x6810 1937#define BGE_TX_CPU_EVENT 0x6820 1938#define BGE_EE_ADDR 0x6838 1939#define BGE_EE_DATA 0x683C 1940#define BGE_EE_CTL 0x6840 1941#define BGE_MDI_CTL 0x6844 1942#define BGE_EE_DELAY 0x6848 1943#define BGE_FASTBOOT_PC 0x6894 1944* 1945#define BGE_RX_CPU_DRV_EVENT 0x00004000 1946 1947/* 1948 * NVRAM Control registers 1949 / 1950#define BGE_NVRAM_CMD 0x7000 1951#define BGE_NVRAM_STAT 0x7004 1952#define BGE_NVRAM_WRDATA 0x7008 1953#define BGE_NVRAM_ADDR 0x700c 1954#define BGE_NVRAM_RDDATA 0x7010 1955#define BGE_NVRAM_CFG1 0x7014 1956#define BGE_NVRAM_CFG2 0x7018 1957#define BGE_NVRAM_CFG3 0x701c 1958#define BGE_NVRAM_SWARB 0x7020 1959#define BGE_NVRAM_ACCESS 0x7024 1960#define BGE_NVRAM_WRITE1 0x7028 1961* 1962#define BGE_NVRAMCMD_RESET 0x00000001 1963#define BGE_NVRAMCMD_DONE 0x00000008 1964#define BGE_NVRAMCMD_START 0x00000010 1965#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1966#define BGE_NVRAMCMD_ERASE 0x00000040 1967#define BGE_NVRAMCMD_FIRST 0x00000080 1968#define BGE_NVRAMCMD_LAST 0x00000100 1969* 1970#define BGE_NVRAM_READCMD \ 1971 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1972 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1973#define BGE_NVRAM_WRITECMD \ 1974 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1975 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1976 1977#define BGE_NVRAMSWARB_SET0 0x00000001 1978#define BGE_NVRAMSWARB_SET1 0x00000002 1979#define BGE_NVRAMSWARB_SET2 0x00000003 1980#define BGE_NVRAMSWARB_SET3 0x00000004 1981#define BGE_NVRAMSWARB_CLR0 0x00000010 1982#define BGE_NVRAMSWARB_CLR1 0x00000020 1983#define BGE_NVRAMSWARB_CLR2 0x00000040 1984#define BGE_NVRAMSWARB_CLR3 0x00000080 1985#define BGE_NVRAMSWARB_GNT0 0x00000100 1986#define BGE_NVRAMSWARB_GNT1 0x00000200 1987#define BGE_NVRAMSWARB_GNT2 0x00000400 1988#define BGE_NVRAMSWARB_GNT3 0x00000800 1989#define BGE_NVRAMSWARB_REQ0 0x00001000 1990#define BGE_NVRAMSWARB_REQ1 0x00002000 1991#define BGE_NVRAMSWARB_REQ2 0x00004000 1992#define BGE_NVRAMSWARB_REQ3 0x00008000 1993 1994#define BGE_NVRAMACC_ENABLE 0x00000001 1995#define BGE_NVRAMACC_WRENABLE 0x00000002 1996 1997/* Mode control register / 1998#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1999#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 2000#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 2001#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 2002#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 2003#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040 2004#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080 2005#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 2006#define BGE_MODECTL_NO_RX_CRC 0x00000400 2007#define BGE_MODECTL_RX_BADFRAMES 0x00000800 2008#define BGE_MODECTL_NO_TX_INTR 0x00002000 2009#define BGE_MODECTL_NO_RX_INTR 0x00004000 2010#define BGE_MODECTL_FORCE_PCI32 0x00008000 2011#define BGE_MODECTL_B2HRX_ENABLE 0x00008000 2012#define BGE_MODECTL_STACKUP 0x00010000 2013#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 2014#define BGE_MODECTL_HTX2B_ENABLE 0x00040000 2015#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 2016#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 2017#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 2018#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 2019#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 2020#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 2021#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 2022#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 2023#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 2024* 2025/* Misc. config register / 2026#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 2027#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 2028#define BGE_MISCCFG_BOARD_ID_MASK 0x0001E000 2029#define BGE_MISCCFG_BOARD_ID_5704 0x00000000 2030#define BGE_MISCCFG_BOARD_ID_5704CIOBE 0x00004000 2031#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 2032#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 2033#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 2034#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 2035* 2036#define BGE_32BITTIME_66MHZ (0x41 << 1) 2037 2038/* Misc. Local Control / 2039#define BGE_MLC_INTR_STATE 0x00000001 2040#define BGE_MLC_INTR_CLR 0x00000002 2041#define BGE_MLC_INTR_SET 0x00000004 2042#define BGE_MLC_INTR_ONATTN 0x00000008 2043#define BGE_MLC_MISCIO_IN0 0x00000100 2044#define BGE_MLC_MISCIO_IN1 0x00000200 2045#define BGE_MLC_MISCIO_IN2 0x00000400 2046#define BGE_MLC_MISCIO_OUTEN0 0x00000800 2047#define BGE_MLC_MISCIO_OUTEN1 0x00001000 2048#define BGE_MLC_MISCIO_OUTEN2 0x00002000 2049#define BGE_MLC_MISCIO_OUT0 0x00004000 2050#define BGE_MLC_MISCIO_OUT1 0x00008000 2051#define BGE_MLC_MISCIO_OUT2 0x00010000 2052#define BGE_MLC_EXTRAM_ENB 0x00020000 2053#define BGE_MLC_SRAM_SIZE 0x001C0000 2054#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 2055#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 2056#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 2057#define BGE_MLC_AUTO_EEPROM 0x01000000 2058* 2059#define BGE_SSRAMSIZE_256KB 0x00000000 2060#define BGE_SSRAMSIZE_512KB 0x00040000 2061#define BGE_SSRAMSIZE_1MB 0x00080000 2062#define BGE_SSRAMSIZE_2MB 0x000C0000 2063#define BGE_SSRAMSIZE_4MB 0x00100000 2064#define BGE_SSRAMSIZE_8MB 0x00140000 2065#define BGE_SSRAMSIZE_16M 0x00180000 2066 2067/* EEPROM address register / 2068#define BGE_EEADDR_ADDRESS 0x0000FFFC 2069#define BGE_EEADDR_HALFCLK 0x01FF0000 2070#define BGE_EEADDR_START 0x02000000 2071#define BGE_EEADDR_DEVID 0x1C000000 2072#define BGE_EEADDR_RESET 0x20000000 2073#define BGE_EEADDR_DONE 0x40000000 2074#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 2075* 2076#define BGE_EEDEVID(x) ((x & 7) << 26) 2077#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 2078#define BGE_HALFCLK_384SCL 0x60 2079#define BGE_EE_READCMD \ 2080 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 2081 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 2082#define BGE_EE_WRCMD \ 2083 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 2084 BGE_EEADDR_START\|BGE_EEADDR_DONE) 2085 2086/* EEPROM Control register / 2087#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 2088#define BGE_EECTL_CLKOUT 0x00000002 2089#define BGE_EECTL_CLKIN 0x00000004 2090#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 2091#define BGE_EECTL_DATAOUT 0x00000010 2092#define BGE_EECTL_DATAIN 0x00000020 2093* 2094/* MDI (MII/GMII) access register / 2095#define BGE_MDI_DATA 0x00000001 2096#define BGE_MDI_DIR 0x00000002 2097#define BGE_MDI_SEL 0x00000004 2098#define BGE_MDI_CLK 0x00000008 2099* 2100#define BGE_MEMWIN_START 0x00008000 2101#define BGE_MEMWIN_END 0x0000FFFF 2102 2103/* BAR1 (APE) Register Definitions / 2104* 2105#define BGE_APE_GPIO_MSG 0x0008 2106#define BGE_APE_EVENT 0x000C 2107#define BGE_APE_LOCK_REQ 0x002C 2108#define BGE_APE_LOCK_GRANT 0x004C 2109 2110#define BGE_APE_GPIO_MSG_SHIFT 4 2111 2112#define BGE_APE_EVENT_1 0x00000001 2113 2114#define BGE_APE_LOCK_REQ_DRIVER0 0x00001000 2115 2116#define BGE_APE_LOCK_GRANT_DRIVER0 0x00001000 2117 2118/* APE Shared Memory block (writable by APE only) / 2119#define BGE_APE_SEG_SIG 0x4000 2120#define BGE_APE_FW_STATUS 0x400C 2121#define BGE_APE_FW_FEATURES 0x4010 2122#define BGE_APE_FW_BEHAVIOR 0x4014 2123#define BGE_APE_FW_VERSION 0x4018 2124#define BGE_APE_FW_HEARTBEAT_INTERVAL 0x4024 2125#define BGE_APE_FW_HEARTBEAT 0x4028 2126#define BGE_APE_FW_ERROR_FLAGS 0x4074 2127* 2128#define BGE_APE_SEG_SIG_MAGIC 0x41504521 2129 2130#define BGE_APE_FW_STATUS_READY 0x00000100 2131 2132#define BGE_APE_FW_FEATURE_DASH 0x00000001 2133#define BGE_APE_FW_FEATURE_NCSI 0x00000002 2134 2135#define BGE_APE_FW_VERSION_MAJMSK 0xFF000000 2136#define BGE_APE_FW_VERSION_MAJSFT 24 2137#define BGE_APE_FW_VERSION_MINMSK 0x00FF0000 2138#define BGE_APE_FW_VERSION_MINSFT 16 2139#define BGE_APE_FW_VERSION_REVMSK 0x0000FF00 2140#define BGE_APE_FW_VERSION_REVSFT 8 2141#define BGE_APE_FW_VERSION_BLDMSK 0x000000FF 2142 2143/* Host Shared Memory block (writable by host only) / 2144#define BGE_APE_HOST_SEG_SIG 0x4200 2145#define BGE_APE_HOST_SEG_LEN 0x4204 2146#define BGE_APE_HOST_INIT_COUNT 0x4208 2147#define BGE_APE_HOST_DRIVER_ID 0x420C 2148#define BGE_APE_HOST_BEHAVIOR 0x4210 2149#define BGE_APE_HOST_HEARTBEAT_INT_MS 0x4214 2150#define BGE_APE_HOST_HEARTBEAT_COUNT 0x4218 2151#define BGE_APE_HOST_DRVR_STATE 0x421C 2152#define BGE_APE_HOST_WOL_SPEED 0x4224 2153* 2154#define BGE_APE_HOST_SEG_SIG_MAGIC 0x484F5354 2155 2156#define BGE_APE_HOST_SEG_LEN_MAGIC 0x00000020 2157 2158#define BGE_APE_HOST_DRIVER_ID_FBSD 0xF6000000 2159#define BGE_APE_HOST_DRIVER_ID_MAGIC(maj, min) \ 2160 (BGE_APE_HOST_DRIVER_ID_FBSD \| \ 2161 ((maj) & 0xffd) << 16 \| ((min) & 0xff) << 8) 2162 2163#define BGE_APE_HOST_BEHAV_NO_PHYLOCK 0x00000001 2164 2165#define BGE_APE_HOST_HEARTBEAT_INT_DISABLE 0 2166#define BGE_APE_HOST_HEARTBEAT_INT_5SEC 5000 2167 2168#define BGE_APE_HOST_DRVR_STATE_START 0x00000001 2169#define BGE_APE_HOST_DRVR_STATE_UNLOAD 0x00000002 2170#define BGE_APE_HOST_DRVR_STATE_WOL 0x00000003 2171#define BGE_APE_HOST_DRVR_STATE_SUSPEND 0x00000004 2172 2173#define BGE_APE_HOST_WOL_SPEED_AUTO 0x00008000 2174 2175#define BGE_APE_EVENT_STATUS 0x4300 2176 2177#define BGE_APE_EVENT_STATUS_DRIVER_EVNT 0x00000010 2178#define BGE_APE_EVENT_STATUS_STATE_CHNGE 0x00000500 2179#define BGE_APE_EVENT_STATUS_STATE_START 0x00010000 2180#define BGE_APE_EVENT_STATUS_STATE_UNLOAD 0x00020000 2181#define BGE_APE_EVENT_STATUS_STATE_WOL 0x00030000 2182#define BGE_APE_EVENT_STATUS_STATE_SUSPEND 0x00040000 2183#define BGE_APE_EVENT_STATUS_EVENT_PENDING 0x80000000 2184 2185#define BGE_APE_DEBUG_LOG 0x4E00 2186#define BGE_APE_DEBUG_LOG_LEN 0x0100 2187 2188#define BGE_APE_PER_LOCK_REQ 0x8400 2189#define BGE_APE_PER_LOCK_GRANT 0x8420 2190 2191#define BGE_APE_LOCK_PER_REQ_DRIVER0 0x00001000 2192#define BGE_APE_LOCK_PER_REQ_DRIVER1 0x00000002 2193#define BGE_APE_LOCK_PER_REQ_DRIVER2 0x00000004 2194#define BGE_APE_LOCK_PER_REQ_DRIVER3 0x00000008 2195 2196#define BGE_APE_PER_LOCK_GRANT_DRIVER0 0x00001000 2197#define BGE_APE_PER_LOCK_GRANT_DRIVER1 0x00000002 2198#define BGE_APE_PER_LOCK_GRANT_DRIVER2 0x00000004 2199#define BGE_APE_PER_LOCK_GRANT_DRIVER3 0x00000008 2200 2201/* APE Mutex Resources / 2202#define BGE_APE_LOCK_PHY0 0 2203#define BGE_APE_LOCK_GRC 1 2204#define BGE_APE_LOCK_PHY1 2 2205#define BGE_APE_LOCK_PHY2 3 2206#define BGE_APE_LOCK_MEM 4 2207#define BGE_APE_LOCK_PHY3 5 2208#define BGE_APE_LOCK_GPIO 7 2209* 2210#define BGE_MEMWIN_READ(sc, x, val) \ 2211 do { \ 2212 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2213 (0xFFFF0000 & x), 4); \ 2214 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 2215 } while(0) 2216 2217#define BGE_MEMWIN_WRITE(sc, x, val) \ 2218 do { \ 2219 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 2220 (0xFFFF0000 & x), 4); \ 2221 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 2222 } while(0) 2223 2224/* 2225 * This magic number is written to the firmware mailbox at 0xb50 2226 * before a software reset is issued. After the internal firmware 2227 * has completed its initialization it will write the opposite of 2228 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location, 2229 * allowing the driver to synchronize with the firmware. 2230 / 2231#define BGE_SRAM_FW_MB_MAGIC 0x4B657654 2232* 2233typedef struct { 2234 uint32_t bge_addr_hi; 2235 uint32_t bge_addr_lo; 2236} bge_hostaddr; 2237 2238#define BGE_HOSTADDR(x, y) \ 2239 do { \ 2240 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 2241 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 2242 } while(0) 2243 2244#define BGE_ADDR_LO(y) \ 2245 ((uint64_t) (y) & 0xFFFFFFFF) 2246#define BGE_ADDR_HI(y) \ 2247 ((uint64_t) (y) >> 32) 2248 2249/* Ring control block structure / 2250struct bge_rcb { 2251* bge_hostaddr bge_hostaddr; 2252 uint32_t bge_maxlen_flags; 2253 uint32_t bge_nicaddr; 2254}; 2255 2256#define RCB_WRITE_4(sc, rcb, offset, val) \ 2257 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 2258#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 2259 2260#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 2261#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2262 2263struct bge_tx_bd { 2264 bge_hostaddr bge_addr; 2265#if BYTE_ORDER == LITTLE_ENDIAN 2266 uint16_t bge_flags; 2267 uint16_t bge_len; 2268 uint16_t bge_vlan_tag; 2269 uint16_t bge_mss; 2270#else 2271 uint16_t bge_len; 2272 uint16_t bge_flags; 2273 uint16_t bge_mss; 2274 uint16_t bge_vlan_tag; 2275#endif 2276}; 2277 2278#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2279#define BGE_TXBDFLAG_IP_CSUM 0x0002 2280#define BGE_TXBDFLAG_END 0x0004 2281#define BGE_TXBDFLAG_IP_FRAG 0x0008 2282#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 / 2283#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2284#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 / 5717 / 2285#define BGE_TXBDFLAG_SNAP 0x0020 / 5717 / 2286#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2287#define BGE_TXBDFLAG_COAL_NOW 0x0080 2288#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2289#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2290#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 / 5717 / 2291#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 / 5717 / 2292#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2293#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 / 5717 / 2294#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 / 5717 / 2295#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 / 5717 / 2296#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2297#define BGE_TXBDFLAG_NO_CRC 0x8000 2298* 2299#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 / 2300/ Bits [1:0] of the MSS header length. / 2301#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 / 5717 / 2302* 2303#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2304 BGE_SEND_RING_1_TO_4 + \ 2305 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2306 2307struct bge_rx_bd { 2308 bge_hostaddr bge_addr; 2309#if BYTE_ORDER == LITTLE_ENDIAN 2310 uint16_t bge_len; 2311 uint16_t bge_idx; 2312 uint16_t bge_flags; 2313 uint16_t bge_type; 2314 uint16_t bge_tcp_udp_csum; 2315 uint16_t bge_ip_csum; 2316 uint16_t bge_vlan_tag; 2317 uint16_t bge_error_flag; 2318#else 2319 uint16_t bge_idx; 2320 uint16_t bge_len; 2321 uint16_t bge_type; 2322 uint16_t bge_flags; 2323 uint16_t bge_ip_csum; 2324 uint16_t bge_tcp_udp_csum; 2325 uint16_t bge_error_flag; 2326 uint16_t bge_vlan_tag; 2327#endif 2328 uint32_t bge_rsvd; 2329 uint32_t bge_opaque; 2330}; 2331 2332struct bge_extrx_bd { 2333 bge_hostaddr bge_addr1; 2334 bge_hostaddr bge_addr2; 2335 bge_hostaddr bge_addr3; 2336#if BYTE_ORDER == LITTLE_ENDIAN 2337 uint16_t bge_len2; 2338 uint16_t bge_len1; 2339 uint16_t bge_rsvd1; 2340 uint16_t bge_len3; 2341#else 2342 uint16_t bge_len1; 2343 uint16_t bge_len2; 2344 uint16_t bge_len3; 2345 uint16_t bge_rsvd1; 2346#endif 2347 bge_hostaddr bge_addr0; 2348#if BYTE_ORDER == LITTLE_ENDIAN 2349 uint16_t bge_len0; 2350 uint16_t bge_idx; 2351 uint16_t bge_flags; 2352 uint16_t bge_type; 2353 uint16_t bge_tcp_udp_csum; 2354 uint16_t bge_ip_csum; 2355 uint16_t bge_vlan_tag; 2356 uint16_t bge_error_flag; 2357#else 2358 uint16_t bge_idx; 2359 uint16_t bge_len0; 2360 uint16_t bge_type; 2361 uint16_t bge_flags; 2362 uint16_t bge_ip_csum; 2363 uint16_t bge_tcp_udp_csum; 2364 uint16_t bge_error_flag; 2365 uint16_t bge_vlan_tag; 2366#endif 2367 uint32_t bge_rsvd0; 2368 uint32_t bge_opaque; 2369}; 2370 2371#define BGE_RXBDFLAG_END 0x0004 2372#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2373#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2374#define BGE_RXBDFLAG_ERROR 0x0400 2375#define BGE_RXBDFLAG_MINI_RING 0x0800 2376#define BGE_RXBDFLAG_IP_CSUM 0x1000 2377#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2378#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2379#define BGE_RXBDFLAG_IPV6 0x8000 2380 2381#define BGE_RXERRFLAG_BAD_CRC 0x0001 2382#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2383#define BGE_RXERRFLAG_LINK_LOST 0x0004 2384#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2385#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2386#define BGE_RXERRFLAG_RUNT 0x0020 2387#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2388#define BGE_RXERRFLAG_GIANT 0x0080 2389#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 / 2390* 2391struct bge_sts_idx { 2392#if BYTE_ORDER == LITTLE_ENDIAN 2393 uint16_t bge_rx_prod_idx; 2394 uint16_t bge_tx_cons_idx; 2395#else 2396 uint16_t bge_tx_cons_idx; 2397 uint16_t bge_rx_prod_idx; 2398#endif 2399}; 2400 2401struct bge_status_block { 2402 uint32_t bge_status; 2403 uint32_t bge_status_tag; 2404#if BYTE_ORDER == LITTLE_ENDIAN 2405 uint16_t bge_rx_jumbo_cons_idx; 2406 uint16_t bge_rx_std_cons_idx; 2407 uint16_t bge_rx_mini_cons_idx; 2408 uint16_t bge_rsvd1; 2409#else 2410 uint16_t bge_rx_std_cons_idx; 2411 uint16_t bge_rx_jumbo_cons_idx; 2412 uint16_t bge_rsvd1; 2413 uint16_t bge_rx_mini_cons_idx; 2414#endif 2415 struct bge_sts_idx bge_idx[16]; 2416}; 2417 2418#define BGE_STATFLAG_UPDATED 0x00000001 2419#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2420#define BGE_STATFLAG_ERROR 0x00000004 2421 2422 2423/* 2424 * Broadcom Vendor ID 2425 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2426 * even though they're now manufactured by Broadcom) 2427 / 2428#define BCOM_VENDORID 0x14E4 2429#define BCOM_DEVICEID_BCM5700 0x1644 2430#define BCOM_DEVICEID_BCM5701 0x1645 2431#define BCOM_DEVICEID_BCM5702 0x1646 2432#define BCOM_DEVICEID_BCM5702X 0x16A6 2433#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2434#define BCOM_DEVICEID_BCM5703 0x1647 2435#define BCOM_DEVICEID_BCM5703X 0x16A7 2436#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2437#define BCOM_DEVICEID_BCM5704C 0x1648 2438#define BCOM_DEVICEID_BCM5704S 0x16A8 2439#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2440#define BCOM_DEVICEID_BCM5705 0x1653 2441#define BCOM_DEVICEID_BCM5705K 0x1654 2442#define BCOM_DEVICEID_BCM5705F 0x166E 2443#define BCOM_DEVICEID_BCM5705M 0x165D 2444#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2445#define BCOM_DEVICEID_BCM5714C 0x1668 2446#define BCOM_DEVICEID_BCM5714S 0x1669 2447#define BCOM_DEVICEID_BCM5715 0x1678 2448#define BCOM_DEVICEID_BCM5715S 0x1679 2449#define BCOM_DEVICEID_BCM5717 0x1655 2450#define BCOM_DEVICEID_BCM5718 0x1656 2451#define BCOM_DEVICEID_BCM5719 0x1657 2452#define BCOM_DEVICEID_BCM5720_PP 0x1658 / Not released to public. / 2453#define BCOM_DEVICEID_BCM5720 0x165F 2454#define BCOM_DEVICEID_BCM5721 0x1659 2455#define BCOM_DEVICEID_BCM5722 0x165A 2456#define BCOM_DEVICEID_BCM5723 0x165B 2457#define BCOM_DEVICEID_BCM5750 0x1676 2458#define BCOM_DEVICEID_BCM5750M 0x167C 2459#define BCOM_DEVICEID_BCM5751 0x1677 2460#define BCOM_DEVICEID_BCM5751F 0x167E 2461#define BCOM_DEVICEID_BCM5751M 0x167D 2462#define BCOM_DEVICEID_BCM5752 0x1600 2463#define BCOM_DEVICEID_BCM5752M 0x1601 2464#define BCOM_DEVICEID_BCM5753 0x16F7 2465#define BCOM_DEVICEID_BCM5753F 0x16FE 2466#define BCOM_DEVICEID_BCM5753M 0x16FD 2467#define BCOM_DEVICEID_BCM5754 0x167A 2468#define BCOM_DEVICEID_BCM5754M 0x1672 2469#define BCOM_DEVICEID_BCM5755 0x167B 2470#define BCOM_DEVICEID_BCM5755M 0x1673 2471#define BCOM_DEVICEID_BCM5756 0x1674 2472#define BCOM_DEVICEID_BCM5761 0x1681 2473#define BCOM_DEVICEID_BCM5761E 0x1680 2474#define BCOM_DEVICEID_BCM5761S 0x1688 2475#define BCOM_DEVICEID_BCM5761SE 0x1689 2476#define BCOM_DEVICEID_BCM5764 0x1684 2477#define BCOM_DEVICEID_BCM5780 0x166A 2478#define BCOM_DEVICEID_BCM5780S 0x166B 2479#define BCOM_DEVICEID_BCM5781 0x16DD 2480#define BCOM_DEVICEID_BCM5782 0x1696 2481#define BCOM_DEVICEID_BCM5784 0x1698 2482#define BCOM_DEVICEID_BCM5785F 0x16a0 2483#define BCOM_DEVICEID_BCM5785G 0x1699 2484#define BCOM_DEVICEID_BCM5786 0x169A 2485#define BCOM_DEVICEID_BCM5787 0x169B 2486#define BCOM_DEVICEID_BCM5787M 0x1693 2487#define BCOM_DEVICEID_BCM5787F 0x167f 2488#define BCOM_DEVICEID_BCM5788 0x169C 2489#define BCOM_DEVICEID_BCM5789 0x169D 2490#define BCOM_DEVICEID_BCM5901 0x170D 2491#define BCOM_DEVICEID_BCM5901A2 0x170E 2492#define BCOM_DEVICEID_BCM5903M 0x16FF 2493#define BCOM_DEVICEID_BCM5906 0x1712 2494#define BCOM_DEVICEID_BCM5906M 0x1713 2495#define BCOM_DEVICEID_BCM57760 0x1690 2496#define BCOM_DEVICEID_BCM57761 0x16B0 2497#define BCOM_DEVICEID_BCM57762 0x1682 2498#define BCOM_DEVICEID_BCM57765 0x16B4 2499#define BCOM_DEVICEID_BCM57766 0x1686 2500#define BCOM_DEVICEID_BCM57780 0x1692 2501#define BCOM_DEVICEID_BCM57781 0x16B1 2502#define BCOM_DEVICEID_BCM57785 0x16B5 2503#define BCOM_DEVICEID_BCM57788 0x1691 2504#define BCOM_DEVICEID_BCM57790 0x1694 2505#define BCOM_DEVICEID_BCM57791 0x16B2 2506#define BCOM_DEVICEID_BCM57795 0x16B6 2507* 2508/* 2509 * Alteon AceNIC PCI vendor/device ID. 2510 / 2511#define ALTEON_VENDORID 0x12AE 2512#define ALTEON_DEVICEID_ACENIC 0x0001 2513#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2514#define ALTEON_DEVICEID_BCM5700 0x0003 2515#define ALTEON_DEVICEID_BCM5701 0x0004 2516* 2517/* 2518 * 3Com 3c996 PCI vendor/device ID. 2519 / 2520#define TC_VENDORID 0x10B7 2521#define TC_DEVICEID_3C996 0x0003 2522* 2523/* 2524 * SysKonnect PCI vendor ID 2525 / 2526#define SK_VENDORID 0x1148 2527#define SK_DEVICEID_ALTIMA 0x4400 2528#define SK_SUBSYSID_9D21 0x4421 2529#define SK_SUBSYSID_9D41 0x4441 2530* 2531/* 2532 * Altima PCI vendor/device ID. 2533 / 2534#define ALTIMA_VENDORID 0x173b 2535#define ALTIMA_DEVICE_AC1000 0x03e8 2536#define ALTIMA_DEVICE_AC1002 0x03e9 2537#define ALTIMA_DEVICE_AC9100 0x03ea 2538* 2539/* 2540 * Dell PCI vendor ID 2541 / 2542* 2543#define DELL_VENDORID 0x1028 2544 2545/* 2546 * Apple PCI vendor ID. 2547 / 2548#define APPLE_VENDORID 0x106b 2549#define APPLE_DEVICE_BCM5701 0x1645 2550* 2551/* 2552 * Sun PCI vendor ID 2553 / 2554#define SUN_VENDORID 0x108e 2555* 2556/* 2557 * Fujitsu vendor/device IDs 2558 / 2559#define FJTSU_VENDORID 0x10cf 2560#define FJTSU_DEVICEID_PW008GE5 0x11a1 2561#define FJTSU_DEVICEID_PW008GE4 0x11a2 2562#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2563* 2564/* 2565 * Offset of MAC address inside EEPROM. 2566 / 2567#define BGE_EE_MAC_OFFSET 0x7C 2568#define BGE_EE_MAC_OFFSET_5906 0x10 2569#define BGE_EE_HWCFG_OFFSET 0xC8 2570* 2571#define BGE_HWCFG_VOLTAGE 0x00000003 2572#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2573#define BGE_HWCFG_MEDIA 0x00000030 2574#define BGE_HWCFG_ASF 0x00000080 2575 2576#define BGE_VOLTAGE_1POINT3 0x00000000 2577#define BGE_VOLTAGE_1POINT8 0x00000001 2578 2579#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2580#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2581#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2582 2583#define BGE_MEDIA_UNSPEC 0x00000000 2584#define BGE_MEDIA_COPPER 0x00000010 2585#define BGE_MEDIA_FIBER 0x00000020 2586 2587#define BGE_TICKS_PER_SEC 1000000 2588 2589/* 2590 * Ring size constants. 2591 / 2592#define BGE_EVENT_RING_CNT 256 2593#define BGE_CMD_RING_CNT 64 2594#define BGE_STD_RX_RING_CNT 512 2595#define BGE_JUMBO_RX_RING_CNT 256 2596#define BGE_MINI_RX_RING_CNT 1024 2597#define BGE_RETURN_RING_CNT 1024 2598* 2599/* 5705 has smaller return ring size / 2600* 2601#define BGE_RETURN_RING_CNT_5705 512 2602 2603/* 2604 * Possible TX ring sizes. 2605 / 2606#define BGE_TX_RING_CNT_128 128 2607#define BGE_TX_RING_BASE_128 0x3800 2608* 2609#define BGE_TX_RING_CNT_256 256 2610#define BGE_TX_RING_BASE_256 0x3000 2611 2612#define BGE_TX_RING_CNT_512 512 2613#define BGE_TX_RING_BASE_512 0x2000 2614 2615#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2616#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2617 2618/* 2619 * Tigon III statistics counters. 2620 / 2621/ Statistics maintained MAC Receive block. / 2622struct bge_rx_mac_stats { 2623* bge_hostaddr ifHCInOctets; 2624 bge_hostaddr Reserved1; 2625 bge_hostaddr etherStatsFragments; 2626 bge_hostaddr ifHCInUcastPkts; 2627 bge_hostaddr ifHCInMulticastPkts; 2628 bge_hostaddr ifHCInBroadcastPkts; 2629 bge_hostaddr dot3StatsFCSErrors; 2630 bge_hostaddr dot3StatsAlignmentErrors; 2631 bge_hostaddr xonPauseFramesReceived; 2632 bge_hostaddr xoffPauseFramesReceived; 2633 bge_hostaddr macControlFramesReceived; 2634 bge_hostaddr xoffStateEntered; 2635 bge_hostaddr dot3StatsFramesTooLong; 2636 bge_hostaddr etherStatsJabbers; 2637 bge_hostaddr etherStatsUndersizePkts; 2638 bge_hostaddr inRangeLengthError; 2639 bge_hostaddr outRangeLengthError; 2640 bge_hostaddr etherStatsPkts64Octets; 2641 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2642 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2643 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2644 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2645 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2646 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2647 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2648 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2649 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2650}; 2651 2652 2653/* Statistics maintained MAC Transmit block. / 2654struct bge_tx_mac_stats { 2655* bge_hostaddr ifHCOutOctets; 2656 bge_hostaddr Reserved2; 2657 bge_hostaddr etherStatsCollisions; 2658 bge_hostaddr outXonSent; 2659 bge_hostaddr outXoffSent; 2660 bge_hostaddr flowControlDone; 2661 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2662 bge_hostaddr dot3StatsSingleCollisionFrames; 2663 bge_hostaddr dot3StatsMultipleCollisionFrames; 2664 bge_hostaddr dot3StatsDeferredTransmissions; 2665 bge_hostaddr Reserved3; 2666 bge_hostaddr dot3StatsExcessiveCollisions; 2667 bge_hostaddr dot3StatsLateCollisions; 2668 bge_hostaddr dot3Collided2Times; 2669 bge_hostaddr dot3Collided3Times; 2670 bge_hostaddr dot3Collided4Times; 2671 bge_hostaddr dot3Collided5Times; 2672 bge_hostaddr dot3Collided6Times; 2673 bge_hostaddr dot3Collided7Times; 2674 bge_hostaddr dot3Collided8Times; 2675 bge_hostaddr dot3Collided9Times; 2676 bge_hostaddr dot3Collided10Times; 2677 bge_hostaddr dot3Collided11Times; 2678 bge_hostaddr dot3Collided12Times; 2679 bge_hostaddr dot3Collided13Times; 2680 bge_hostaddr dot3Collided14Times; 2681 bge_hostaddr dot3Collided15Times; 2682 bge_hostaddr ifHCOutUcastPkts; 2683 bge_hostaddr ifHCOutMulticastPkts; 2684 bge_hostaddr ifHCOutBroadcastPkts; 2685 bge_hostaddr dot3StatsCarrierSenseErrors; 2686 bge_hostaddr ifOutDiscards; 2687 bge_hostaddr ifOutErrors; 2688}; 2689 2690/* Stats counters access through registers / 2691struct bge_mac_stats { 2692* /* TX MAC statistics / 2693* uint64_t ifHCOutOctets; 2694 uint64_t Reserved0; 2695 uint64_t etherStatsCollisions; 2696 uint64_t outXonSent; 2697 uint64_t outXoffSent; 2698 uint64_t Reserved1; 2699 uint64_t dot3StatsInternalMacTransmitErrors; 2700 uint64_t dot3StatsSingleCollisionFrames; 2701 uint64_t dot3StatsMultipleCollisionFrames; 2702 uint64_t dot3StatsDeferredTransmissions; 2703 uint64_t Reserved2; 2704 uint64_t dot3StatsExcessiveCollisions; 2705 uint64_t dot3StatsLateCollisions; 2706 uint64_t Reserved3[14]; 2707 uint64_t ifHCOutUcastPkts; 2708 uint64_t ifHCOutMulticastPkts; 2709 uint64_t ifHCOutBroadcastPkts; 2710 uint64_t Reserved4[2]; 2711 /* RX MAC statistics / 2712* uint64_t ifHCInOctets; 2713 uint64_t Reserved5; 2714 uint64_t etherStatsFragments; 2715 uint64_t ifHCInUcastPkts; 2716 uint64_t ifHCInMulticastPkts; 2717 uint64_t ifHCInBroadcastPkts; 2718 uint64_t dot3StatsFCSErrors; 2719 uint64_t dot3StatsAlignmentErrors; 2720 uint64_t xonPauseFramesReceived; 2721 uint64_t xoffPauseFramesReceived; 2722 uint64_t macControlFramesReceived; 2723 uint64_t xoffStateEntered; 2724 uint64_t dot3StatsFramesTooLong; 2725 uint64_t etherStatsJabbers; 2726 uint64_t etherStatsUndersizePkts; 2727 /* Receive List Placement control / 2728* uint64_t FramesDroppedDueToFilters; 2729 uint64_t DmaWriteQueueFull; 2730 uint64_t DmaWriteHighPriQueueFull; 2731 uint64_t NoMoreRxBDs; 2732 uint64_t InputDiscards; 2733 uint64_t InputErrors; 2734 uint64_t RecvThresholdHit; 2735}; 2736 2737struct bge_stats { 2738 uint8_t Reserved0[256]; 2739 2740 /* Statistics maintained by Receive MAC. / 2741* struct bge_rx_mac_stats rxstats; 2742 2743 bge_hostaddr Unused1[37]; 2744 2745 /* Statistics maintained by Transmit MAC. / 2746* struct bge_tx_mac_stats txstats; 2747 2748 bge_hostaddr Unused2[31]; 2749 2750 /* Statistics maintained by Receive List Placement. / 2751* bge_hostaddr COSIfHCInPkts[16]; 2752 bge_hostaddr COSFramesDroppedDueToFilters; 2753 bge_hostaddr nicDmaWriteQueueFull; 2754 bge_hostaddr nicDmaWriteHighPriQueueFull; 2755 bge_hostaddr nicNoMoreRxBDs; 2756 bge_hostaddr ifInDiscards; 2757 bge_hostaddr ifInErrors; 2758 bge_hostaddr nicRecvThresholdHit; 2759 2760 bge_hostaddr Unused3[9]; 2761 2762 /* Statistics maintained by Send Data Initiator. / 2763* bge_hostaddr COSIfHCOutPkts[16]; 2764 bge_hostaddr nicDmaReadQueueFull; 2765 bge_hostaddr nicDmaReadHighPriQueueFull; 2766 bge_hostaddr nicSendDataCompQueueFull; 2767 2768 /* Statistics maintained by Host Coalescing. / 2769* bge_hostaddr nicRingSetSendProdIndex; 2770 bge_hostaddr nicRingStatusUpdate; 2771 bge_hostaddr nicInterrupts; 2772 bge_hostaddr nicAvoidedInterrupts; 2773 bge_hostaddr nicSendThresholdHit; 2774 2775 uint8_t Reserved4[320]; 2776}; 2777 2778/* 2779 * Tigon general information block. This resides in host memory 2780 * and contains the status counters, ring control blocks and 2781 * producer pointers. 2782 / 2783* 2784struct bge_gib { 2785 struct bge_stats bge_stats; 2786 struct bge_rcb bge_tx_rcb[16]; 2787 struct bge_rcb bge_std_rx_rcb; 2788 struct bge_rcb bge_jumbo_rx_rcb; 2789 struct bge_rcb bge_mini_rx_rcb; 2790 struct bge_rcb bge_return_rcb; 2791}; 2792 2793#define BGE_FRAMELEN 1518 2794#define BGE_MAX_FRAMELEN 1536 2795#define BGE_JUMBO_FRAMELEN 9018 2796#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2797#define BGE_MIN_FRAMELEN 60 2798 2799/* 2800 * Other utility macros. 2801 / 2802#define BGE_INC(x, y) (x) = (x + 1) % y 2803* 2804/* 2805 * BAR0 MAC register access macros. The Tigon always uses memory mapped register 2806 * accesses and all registers must be accessed with 32 bit operations. 2807 / 2808* 2809#define CSR_WRITE_4(sc, reg, val) \ 2810 bus_write_4(sc->bge_res, reg, val) 2811 2812#define CSR_READ_4(sc, reg) \ 2813 bus_read_4(sc->bge_res, reg) 2814 2815#define BGE_SETBIT(sc, reg, x) \ 2816 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2817#define BGE_CLRBIT(sc, reg, x) \ 2818 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2819 2820/* BAR2 APE register access macros. / 2821#define APE_WRITE_4(sc, reg, val) \ 2822* bus_write_4(sc->bge_res2, reg, val) 2823 2824#define APE_READ_4(sc, reg) \ 2825 bus_read_4(sc->bge_res2, reg) 2826 2827#define APE_SETBIT(sc, reg, x) \ 2828 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) \| (x))) 2829#define APE_CLRBIT(sc, reg, x) \ 2830 APE_WRITE_4(sc, reg, (APE_READ_4(sc, reg) & ~(x))) 2831 2832#define PCI_SETBIT(dev, reg, x, s) \ 2833 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2834#define PCI_CLRBIT(dev, reg, x, s) \ 2835 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2836 2837/* 2838 * Memory management stuff. 2839 / 2840* 2841#define BGE_NSEG_JUMBO 4 2842#define BGE_NSEG_NEW 32 2843#define BGE_TSOSEG_SZ 4096 2844 2845/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2846#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2847#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2848#else 2849#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2850#endif 2851* 2852/* 2853 * Ring structures. Most of these reside in host memory and we tell 2854 * the NIC where they are via the ring control blocks. The exceptions 2855 * are the tx and command rings, which live in NIC memory and which 2856 * we access via the shared memory window. 2857 / 2858* 2859struct bge_ring_data { 2860 struct bge_rx_bd bge_rx_std_ring; 2861* bus_addr_t bge_rx_std_ring_paddr; 2862 struct bge_extrx_bd bge_rx_jumbo_ring; 2863* bus_addr_t bge_rx_jumbo_ring_paddr; 2864 struct bge_rx_bd bge_rx_return_ring; 2865* bus_addr_t bge_rx_return_ring_paddr; 2866 struct bge_tx_bd bge_tx_ring; 2867* bus_addr_t bge_tx_ring_paddr; 2868 struct bge_status_block bge_status_block; 2869* bus_addr_t bge_status_block_paddr; 2870 struct bge_stats bge_stats; 2871* bus_addr_t bge_stats_paddr; 2872 struct bge_gib bge_info; 2873}; 2874 2875#define BGE_STD_RX_RING_SZ \ 2876 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2877#define BGE_JUMBO_RX_RING_SZ \ 2878 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2879#define BGE_TX_RING_SZ \ 2880 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2881#define BGE_RX_RTN_RING_SZ(x) \ 2882 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2883 2884#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2885 2886#define BGE_STATS_SZ sizeof (struct bge_stats) 2887 2888/* 2889 * Mbuf pointers. We need these to keep track of the virtual addresses 2890 * of our mbuf chains since we can only convert from physical to virtual, 2891 * not the other way around. 2892 / 2893struct bge_chain_data { 2894* bus_dma_tag_t bge_parent_tag; 2895 bus_dma_tag_t bge_buffer_tag; 2896 bus_dma_tag_t bge_rx_std_ring_tag; 2897 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2898 bus_dma_tag_t bge_rx_return_ring_tag; 2899 bus_dma_tag_t bge_tx_ring_tag; 2900 bus_dma_tag_t bge_status_tag; 2901 bus_dma_tag_t bge_stats_tag; 2902 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2903* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2904* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2905* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2906 bus_dmamap_t bge_rx_std_sparemap; 2907 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2908 bus_dmamap_t bge_rx_jumbo_sparemap; 2909 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2910 bus_dmamap_t bge_rx_std_ring_map; 2911 bus_dmamap_t bge_rx_jumbo_ring_map; 2912 bus_dmamap_t bge_tx_ring_map; 2913 bus_dmamap_t bge_rx_return_ring_map; 2914 bus_dmamap_t bge_status_map; 2915 bus_dmamap_t bge_stats_map; 2916 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2917* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2918* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2919* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2920 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2921}; 2922 2923struct bge_dmamap_arg { 2924 bus_addr_t bge_busaddr; 2925}; 2926 2927#define BGE_HWREV_TIGON 0x01 2928#define BGE_HWREV_TIGON_II 0x02 2929#define BGE_TIMEOUT 100000 2930#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2931#define BGE_TX_TIMEOUT 5 2932* 2933struct bge_bcom_hack { 2934 int reg; 2935 int val; 2936}; 2937 2938#define ASF_ENABLE 1 2939#define ASF_NEW_HANDSHAKE 2 2940#define ASF_STACKUP 4 2941 2942struct bge_softc { 2943 struct ifnet bge_ifp; / interface info / 2944* device_t bge_dev; 2945 struct mtx bge_mtx; 2946 device_t bge_miibus; 2947 void bge_intrhand; 2948* struct resource bge_irq; 2949* struct resource bge_res; / MAC mapped I/O / 2950* struct resource bge_res2; / APE mapped I/O / 2951* struct ifmedia bge_ifmedia; /* TBI media info / 2952* int bge_expcap; 2953 int bge_expmrq; 2954 int bge_msicap; 2955 int bge_pcixcap; 2956 uint32_t bge_flags; 2957#define BGE_FLAG_TBI 0x00000001 2958#define BGE_FLAG_JUMBO 0x00000002 2959#define BGE_FLAG_JUMBO_STD 0x00000004 2960#define BGE_FLAG_EADDR 0x00000008 2961#define BGE_FLAG_MII_SERDES 0x00000010 2962#define BGE_FLAG_CPMU_PRESENT 0x00000020 2963#define BGE_FLAG_TAGGED_STATUS 0x00000040 2964#define BGE_FLAG_APE 0x00000080 2965#define BGE_FLAG_MSI 0x00000100 2966#define BGE_FLAG_PCIX 0x00000200 2967#define BGE_FLAG_PCIE 0x00000400 2968#define BGE_FLAG_TSO 0x00000800 2969#define BGE_FLAG_TSO3 0x00001000 2970#define BGE_FLAG_JUMBO_FRAME 0x00002000 2971#define BGE_FLAG_5700_FAMILY 0x00010000 2972#define BGE_FLAG_5705_PLUS 0x00020000 2973#define BGE_FLAG_5714_FAMILY 0x00040000 2974#define BGE_FLAG_575X_PLUS 0x00080000 2975#define BGE_FLAG_5755_PLUS 0x00100000 2976#define BGE_FLAG_5788 0x00200000 2977#define BGE_FLAG_5717_PLUS 0x00400000 2978#define BGE_FLAG_57765_PLUS 0x00800000 2979#define BGE_FLAG_40BIT_BUG 0x01000000 2980#define BGE_FLAG_4G_BNDRY_BUG 0x02000000 2981#define BGE_FLAG_RX_ALIGNBUG 0x04000000 2982#define BGE_FLAG_SHORT_DMA_BUG 0x08000000 2983#define BGE_FLAG_4K_RDMA_BUG 0x10000000 2984#define BGE_FLAG_MBOX_REORDER 0x20000000 2985#define BGE_FLAG_RDMA_BUG 0x40000000 2986 uint32_t bge_mfw_flags; /* Management F/W flags / 2987#define BGE_MFW_ON_RXCPU 0x00000001 2988#define BGE_MFW_ON_APE 0x00000002 2989#define BGE_MFW_TYPE_NCSI 0x00000004 2990#define BGE_MFW_TYPE_DASH 0x00000008 2991* int bge_phy_ape_lock; 2992 int bge_func_addr; 2993 int bge_phy_addr; 2994 uint32_t bge_phy_flags; 2995#define BGE_PHY_NO_WIRESPEED 0x00000001 2996#define BGE_PHY_ADC_BUG 0x00000002 2997#define BGE_PHY_5704_A0_BUG 0x00000004 2998#define BGE_PHY_JITTER_BUG 0x00000008 2999#define BGE_PHY_BER_BUG 0x00000010 3000#define BGE_PHY_ADJUST_TRIM 0x00000020 3001#define BGE_PHY_CRC_BUG 0x00000040 3002#define BGE_PHY_NO_3LED 0x00000080 3003 uint32_t bge_chipid; 3004 uint32_t bge_asicrev; 3005 uint32_t bge_chiprev; 3006 uint8_t bge_asf_mode; 3007 uint8_t bge_asf_count; 3008 uint16_t bge_mps; 3009 struct bge_ring_data bge_ldata; /* rings / 3010* struct bge_chain_data bge_cdata; /* mbufs / 3011* uint16_t bge_tx_saved_considx; 3012 uint16_t bge_rx_saved_considx; 3013 uint16_t bge_ev_saved_considx; 3014 uint16_t bge_return_ring_cnt; 3015 uint16_t bge_std; /* current std ring head / 3016* uint16_t bge_jumbo; /* current jumo ring head / 3017* uint32_t bge_stat_ticks; 3018 uint32_t bge_rx_coal_ticks; 3019 uint32_t bge_tx_coal_ticks; 3020 uint32_t bge_tx_prodidx; 3021 uint32_t bge_rx_max_coal_bds; 3022 uint32_t bge_tx_max_coal_bds; 3023 uint32_t bge_mi_mode; 3024 int bge_if_flags; 3025 int bge_txcnt; 3026 int bge_link; /* link state / 3027* int bge_link_evt; /* pending link event / 3028* int bge_timer; 3029 int bge_forced_collapse; 3030 int bge_forced_udpcsum; 3031 int bge_msi; 3032 int bge_csum_features; 3033 struct callout bge_stat_ch; 3034 uint32_t bge_rx_discards; 3035 uint32_t bge_rx_inerrs; 3036 uint32_t bge_rx_nobds; 3037 uint32_t bge_tx_discards; 3038 uint32_t bge_tx_collisions; 3039#ifdef DEVICE_POLLING 3040 int rxcycles; 3041#endif /* DEVICE_POLLING / 3042* struct bge_mac_stats bge_mac_stats; 3043 struct task bge_intr_task; 3044 struct taskqueue bge_tq; 3045}; 3046* 3047#define BGE_LOCK_INIT(_sc, _name) \ 3048 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 3049#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 3050#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 3051#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 3052#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)