1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
| 1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 *
|
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226867 2011-10-27 22:10:52Z yongari $
| 33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 226871 2011-10-28 01:04:40Z yongari $
|
34 */
35
36/*
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
45 *
46 * The NIC's memory can be accessed by the host in one of 3 ways:
47 *
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
51 *
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
55 * of NIC memory.
56 *
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
62 * recommended.
63 */
64#define BGE_PAGE_ZERO 0x00000000
65#define BGE_PAGE_ZERO_END 0x000000FF
66#define BGE_SEND_RING_RCB 0x00000100
67#define BGE_SEND_RING_RCB_END 0x000001FF
68#define BGE_RX_RETURN_RING_RCB 0x00000200
69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70#define BGE_STATS_BLOCK 0x00000300
71#define BGE_STATS_BLOCK_END 0x00000AFF
72#define BGE_STATUS_BLOCK 0x00000B00
73#define BGE_STATUS_BLOCK_END 0x00000B4F
74#define BGE_SRAM_FW_MB 0x00000B50
75#define BGE_SRAM_DATA_SIG 0x00000B54
76#define BGE_SRAM_DATA_CFG 0x00000B58
77#define BGE_SRAM_FW_CMD_MB 0x00000B78
78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C
79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80
80#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04
81#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14
82#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18
83#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
84#define BGE_UNMAPPED 0x00001000
85#define BGE_UNMAPPED_END 0x00001FFF
86#define BGE_DMA_DESCRIPTORS 0x00002000
87#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
88#define BGE_SEND_RING_5717 0x00004000
89#define BGE_SEND_RING_1_TO_4 0x00004000
90#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
91
92/* Firmware interface */
93#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */
94
95#define BGE_FW_CMD_DRV_ALIVE 0x00000001
96#define BGE_FW_CMD_PAUSE 0x00000002
97#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003
98#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004
99#define BGE_FW_CMD_LINK_UPDATE 0x0000000C
100#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D
101#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E
102
103#define BGE_FW_HB_TIMEOUT_SEC 3
104
105#define BGE_FW_DRV_STATE_START 0x00000001
106#define BGE_FW_DRV_STATE_START_DONE 0x80000001
107#define BGE_FW_DRV_STATE_UNLOAD 0x00000002
108#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002
109#define BGE_FW_DRV_STATE_WOL 0x00000003
110#define BGE_FW_DRV_STATE_SUSPEND 0x00000004
111
112/* Mappings for internal memory configuration */
113#define BGE_STD_RX_RINGS 0x00006000
114#define BGE_STD_RX_RINGS_END 0x00006FFF
115#define BGE_JUMBO_RX_RINGS 0x00007000
116#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
117#define BGE_BUFFPOOL_1 0x00008000
118#define BGE_BUFFPOOL_1_END 0x0000FFFF
119#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
120#define BGE_BUFFPOOL_2_END 0x00017FFF
121#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
122#define BGE_BUFFPOOL_3_END 0x0001FFFF
123#define BGE_STD_RX_RINGS_5717 0x00040000
124#define BGE_JUMBO_RX_RINGS_5717 0x00044400
125
126/* Mappings for external SSRAM configurations */
127#define BGE_SEND_RING_5_TO_6 0x00006000
128#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
129#define BGE_SEND_RING_7_TO_8 0x00007000
130#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
131#define BGE_SEND_RING_9_TO_16 0x00008000
132#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
133#define BGE_EXT_STD_RX_RINGS 0x0000C000
134#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
135#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
136#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
137#define BGE_MINI_RX_RINGS 0x0000E000
138#define BGE_MINI_RX_RINGS_END 0x0000FFFF
139#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
140#define BGE_AVAIL_REGION1_END 0x00017FFF
141#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
142#define BGE_AVAIL_REGION2_END 0x0001FFFF
143#define BGE_EXT_SSRAM 0x00020000
144#define BGE_EXT_SSRAM_END 0x000FFFFF
145
146
147/*
148 * BCM570x register offsets. These are memory mapped registers
149 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
150 * Each register must be accessed using 32 bit operations.
151 *
152 * All registers are accessed through a 32K shared memory block.
153 * The first group of registers are actually copies of the PCI
154 * configuration space registers.
155 */
156
157/*
158 * PCI registers defined in the PCI 2.2 spec.
159 */
160#define BGE_PCI_VID 0x00
161#define BGE_PCI_DID 0x02
162#define BGE_PCI_CMD 0x04
163#define BGE_PCI_STS 0x06
164#define BGE_PCI_REV 0x08
165#define BGE_PCI_CLASS 0x09
166#define BGE_PCI_CACHESZ 0x0C
167#define BGE_PCI_LATTIMER 0x0D
168#define BGE_PCI_HDRTYPE 0x0E
169#define BGE_PCI_BIST 0x0F
170#define BGE_PCI_BAR0 0x10
171#define BGE_PCI_BAR1 0x14
172#define BGE_PCI_SUBSYS 0x2C
173#define BGE_PCI_SUBVID 0x2E
174#define BGE_PCI_ROMBASE 0x30
175#define BGE_PCI_CAPPTR 0x34
176#define BGE_PCI_INTLINE 0x3C
177#define BGE_PCI_INTPIN 0x3D
178#define BGE_PCI_MINGNT 0x3E
179#define BGE_PCI_MAXLAT 0x3F
180#define BGE_PCI_PCIXCAP 0x40
181#define BGE_PCI_NEXTPTR_PM 0x41
182#define BGE_PCI_PCIX_CMD 0x42
183#define BGE_PCI_PCIX_STS 0x44
184#define BGE_PCI_PWRMGMT_CAPID 0x48
185#define BGE_PCI_NEXTPTR_VPD 0x49
186#define BGE_PCI_PWRMGMT_CAPS 0x4A
187#define BGE_PCI_PWRMGMT_CMD 0x4C
188#define BGE_PCI_PWRMGMT_STS 0x4D
189#define BGE_PCI_PWRMGMT_DATA 0x4F
190#define BGE_PCI_VPD_CAPID 0x50
191#define BGE_PCI_NEXTPTR_MSI 0x51
192#define BGE_PCI_VPD_ADDR 0x52
193#define BGE_PCI_VPD_DATA 0x54
194#define BGE_PCI_MSI_CAPID 0x58
195#define BGE_PCI_NEXTPTR_NONE 0x59
196#define BGE_PCI_MSI_CTL 0x5A
197#define BGE_PCI_MSI_ADDR_HI 0x5C
198#define BGE_PCI_MSI_ADDR_LO 0x60
199#define BGE_PCI_MSI_DATA 0x64
200
201/*
202 * PCI Express definitions
203 * According to
204 * PCI Express base specification, REV. 1.0a
205 */
206
207/* PCI Express device control, 16bits */
208#define BGE_PCIE_DEVCTL 0x08
209#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
210#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
211#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
212#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
213#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
214#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
215#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
216
217/* PCI MSI. ??? */
218#define BGE_PCIE_CAPID_REG 0xD0
219#define BGE_PCIE_CAPID 0x10
220
221/*
222 * PCI registers specific to the BCM570x family.
223 */
224#define BGE_PCI_MISC_CTL 0x68
225#define BGE_PCI_DMA_RW_CTL 0x6C
226#define BGE_PCI_PCISTATE 0x70
227#define BGE_PCI_CLKCTL 0x74
228#define BGE_PCI_REG_BASEADDR 0x78
229#define BGE_PCI_MEMWIN_BASEADDR 0x7C
230#define BGE_PCI_REG_DATA 0x80
231#define BGE_PCI_MEMWIN_DATA 0x84
232#define BGE_PCI_MODECTL 0x88
233#define BGE_PCI_MISC_CFG 0x8C
234#define BGE_PCI_MISC_LOCALCTL 0x90
235#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
236#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
237#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
238#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
239#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
240#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
241#define BGE_PCI_ISR_MBX_HI 0xB0
242#define BGE_PCI_ISR_MBX_LO 0xB4
243#define BGE_PCI_PRODID_ASICREV 0xBC
244#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4
245#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC
246
247/* PCI Misc. Host control register */
248#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
249#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
250#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
251#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
252#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200
257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16
259
260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
| 34 */
35
36/*
37 * BCM570x memory map. The internal memory layout varies somewhat
38 * depending on whether or not we have external SSRAM attached.
39 * The BCM5700 can have up to 16MB of external memory. The BCM5701
40 * is apparently not designed to use external SSRAM. The mappings
41 * up to the first 4 send rings are the same for both internal and
42 * external memory configurations. Note that mini RX ring space is
43 * only available with external SSRAM configurations, which means
44 * the mini RX ring is not supported on the BCM5701.
45 *
46 * The NIC's memory can be accessed by the host in one of 3 ways:
47 *
48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA
49 * registers in PCI config space can be used to read any 32-bit
50 * address within the NIC's memory.
51 *
52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config
53 * space can be used in conjunction with the memory window in the
54 * device register space at offset 0x8000 to read any 32K chunk
55 * of NIC memory.
56 *
57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is
58 * set, the device I/O mapping consumes 32MB of host address space,
59 * allowing all of the registers and internal NIC memory to be
60 * accessed directly. NIC memory addresses are offset by 0x01000000.
61 * Flat mode consumes so much host address space that it is not
62 * recommended.
63 */
64#define BGE_PAGE_ZERO 0x00000000
65#define BGE_PAGE_ZERO_END 0x000000FF
66#define BGE_SEND_RING_RCB 0x00000100
67#define BGE_SEND_RING_RCB_END 0x000001FF
68#define BGE_RX_RETURN_RING_RCB 0x00000200
69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF
70#define BGE_STATS_BLOCK 0x00000300
71#define BGE_STATS_BLOCK_END 0x00000AFF
72#define BGE_STATUS_BLOCK 0x00000B00
73#define BGE_STATUS_BLOCK_END 0x00000B4F
74#define BGE_SRAM_FW_MB 0x00000B50
75#define BGE_SRAM_DATA_SIG 0x00000B54
76#define BGE_SRAM_DATA_CFG 0x00000B58
77#define BGE_SRAM_FW_CMD_MB 0x00000B78
78#define BGE_SRAM_FW_CMD_LEN_MB 0x00000B7C
79#define BGE_SRAM_FW_CMD_DATA_MB 0x00000B80
80#define BGE_SRAM_FW_DRV_STATE_MB 0x00000C04
81#define BGE_SRAM_MAC_ADDR_HIGH_MB 0x00000C14
82#define BGE_SRAM_MAC_ADDR_LOW_MB 0x00000C18
83#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF
84#define BGE_UNMAPPED 0x00001000
85#define BGE_UNMAPPED_END 0x00001FFF
86#define BGE_DMA_DESCRIPTORS 0x00002000
87#define BGE_DMA_DESCRIPTORS_END 0x00003FFF
88#define BGE_SEND_RING_5717 0x00004000
89#define BGE_SEND_RING_1_TO_4 0x00004000
90#define BGE_SEND_RING_1_TO_4_END 0x00005FFF
91
92/* Firmware interface */
93#define BGE_SRAM_DATA_SIG_MAGIC 0x4B657654 /* 'KevT' */
94
95#define BGE_FW_CMD_DRV_ALIVE 0x00000001
96#define BGE_FW_CMD_PAUSE 0x00000002
97#define BGE_FW_CMD_IPV4_ADDR_CHANGE 0x00000003
98#define BGE_FW_CMD_IPV6_ADDR_CHANGE 0x00000004
99#define BGE_FW_CMD_LINK_UPDATE 0x0000000C
100#define BGE_FW_CMD_DRV_ALIVE2 0x0000000D
101#define BGE_FW_CMD_DRV_ALIVE3 0x0000000E
102
103#define BGE_FW_HB_TIMEOUT_SEC 3
104
105#define BGE_FW_DRV_STATE_START 0x00000001
106#define BGE_FW_DRV_STATE_START_DONE 0x80000001
107#define BGE_FW_DRV_STATE_UNLOAD 0x00000002
108#define BGE_FW_DRV_STATE_UNLOAD_DONE 0x80000002
109#define BGE_FW_DRV_STATE_WOL 0x00000003
110#define BGE_FW_DRV_STATE_SUSPEND 0x00000004
111
112/* Mappings for internal memory configuration */
113#define BGE_STD_RX_RINGS 0x00006000
114#define BGE_STD_RX_RINGS_END 0x00006FFF
115#define BGE_JUMBO_RX_RINGS 0x00007000
116#define BGE_JUMBO_RX_RINGS_END 0x00007FFF
117#define BGE_BUFFPOOL_1 0x00008000
118#define BGE_BUFFPOOL_1_END 0x0000FFFF
119#define BGE_BUFFPOOL_2 0x00010000 /* or expansion ROM */
120#define BGE_BUFFPOOL_2_END 0x00017FFF
121#define BGE_BUFFPOOL_3 0x00018000 /* or expansion ROM */
122#define BGE_BUFFPOOL_3_END 0x0001FFFF
123#define BGE_STD_RX_RINGS_5717 0x00040000
124#define BGE_JUMBO_RX_RINGS_5717 0x00044400
125
126/* Mappings for external SSRAM configurations */
127#define BGE_SEND_RING_5_TO_6 0x00006000
128#define BGE_SEND_RING_5_TO_6_END 0x00006FFF
129#define BGE_SEND_RING_7_TO_8 0x00007000
130#define BGE_SEND_RING_7_TO_8_END 0x00007FFF
131#define BGE_SEND_RING_9_TO_16 0x00008000
132#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF
133#define BGE_EXT_STD_RX_RINGS 0x0000C000
134#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF
135#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000
136#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF
137#define BGE_MINI_RX_RINGS 0x0000E000
138#define BGE_MINI_RX_RINGS_END 0x0000FFFF
139#define BGE_AVAIL_REGION1 0x00010000 /* or expansion ROM */
140#define BGE_AVAIL_REGION1_END 0x00017FFF
141#define BGE_AVAIL_REGION2 0x00018000 /* or expansion ROM */
142#define BGE_AVAIL_REGION2_END 0x0001FFFF
143#define BGE_EXT_SSRAM 0x00020000
144#define BGE_EXT_SSRAM_END 0x000FFFFF
145
146
147/*
148 * BCM570x register offsets. These are memory mapped registers
149 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros.
150 * Each register must be accessed using 32 bit operations.
151 *
152 * All registers are accessed through a 32K shared memory block.
153 * The first group of registers are actually copies of the PCI
154 * configuration space registers.
155 */
156
157/*
158 * PCI registers defined in the PCI 2.2 spec.
159 */
160#define BGE_PCI_VID 0x00
161#define BGE_PCI_DID 0x02
162#define BGE_PCI_CMD 0x04
163#define BGE_PCI_STS 0x06
164#define BGE_PCI_REV 0x08
165#define BGE_PCI_CLASS 0x09
166#define BGE_PCI_CACHESZ 0x0C
167#define BGE_PCI_LATTIMER 0x0D
168#define BGE_PCI_HDRTYPE 0x0E
169#define BGE_PCI_BIST 0x0F
170#define BGE_PCI_BAR0 0x10
171#define BGE_PCI_BAR1 0x14
172#define BGE_PCI_SUBSYS 0x2C
173#define BGE_PCI_SUBVID 0x2E
174#define BGE_PCI_ROMBASE 0x30
175#define BGE_PCI_CAPPTR 0x34
176#define BGE_PCI_INTLINE 0x3C
177#define BGE_PCI_INTPIN 0x3D
178#define BGE_PCI_MINGNT 0x3E
179#define BGE_PCI_MAXLAT 0x3F
180#define BGE_PCI_PCIXCAP 0x40
181#define BGE_PCI_NEXTPTR_PM 0x41
182#define BGE_PCI_PCIX_CMD 0x42
183#define BGE_PCI_PCIX_STS 0x44
184#define BGE_PCI_PWRMGMT_CAPID 0x48
185#define BGE_PCI_NEXTPTR_VPD 0x49
186#define BGE_PCI_PWRMGMT_CAPS 0x4A
187#define BGE_PCI_PWRMGMT_CMD 0x4C
188#define BGE_PCI_PWRMGMT_STS 0x4D
189#define BGE_PCI_PWRMGMT_DATA 0x4F
190#define BGE_PCI_VPD_CAPID 0x50
191#define BGE_PCI_NEXTPTR_MSI 0x51
192#define BGE_PCI_VPD_ADDR 0x52
193#define BGE_PCI_VPD_DATA 0x54
194#define BGE_PCI_MSI_CAPID 0x58
195#define BGE_PCI_NEXTPTR_NONE 0x59
196#define BGE_PCI_MSI_CTL 0x5A
197#define BGE_PCI_MSI_ADDR_HI 0x5C
198#define BGE_PCI_MSI_ADDR_LO 0x60
199#define BGE_PCI_MSI_DATA 0x64
200
201/*
202 * PCI Express definitions
203 * According to
204 * PCI Express base specification, REV. 1.0a
205 */
206
207/* PCI Express device control, 16bits */
208#define BGE_PCIE_DEVCTL 0x08
209#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000
210#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000
211#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000
212#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000
213#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000
214#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000
215#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000
216
217/* PCI MSI. ??? */
218#define BGE_PCIE_CAPID_REG 0xD0
219#define BGE_PCIE_CAPID 0x10
220
221/*
222 * PCI registers specific to the BCM570x family.
223 */
224#define BGE_PCI_MISC_CTL 0x68
225#define BGE_PCI_DMA_RW_CTL 0x6C
226#define BGE_PCI_PCISTATE 0x70
227#define BGE_PCI_CLKCTL 0x74
228#define BGE_PCI_REG_BASEADDR 0x78
229#define BGE_PCI_MEMWIN_BASEADDR 0x7C
230#define BGE_PCI_REG_DATA 0x80
231#define BGE_PCI_MEMWIN_DATA 0x84
232#define BGE_PCI_MODECTL 0x88
233#define BGE_PCI_MISC_CFG 0x8C
234#define BGE_PCI_MISC_LOCALCTL 0x90
235#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98
236#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C
237#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0
238#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4
239#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8
240#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC
241#define BGE_PCI_ISR_MBX_HI 0xB0
242#define BGE_PCI_ISR_MBX_LO 0xB4
243#define BGE_PCI_PRODID_ASICREV 0xBC
244#define BGE_PCI_GEN2_PRODID_ASICREV 0xF4
245#define BGE_PCI_GEN15_PRODID_ASICREV 0xFC
246
247/* PCI Misc. Host control register */
248#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001
249#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002
250#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004
251#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008
252#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010
253#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020
254#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040
255#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080
256#define BGE_PCIMISCCTL_TAGGED_STATUS 0x00000200
257#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000
258#define BGE_PCIMISCCTL_ASICREV_SHIFT 16
259
260#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP)
|
261#if BYTE_ORDER == LITTLE_ENDIAN
262#define BGE_DMA_SWAP_OPTIONS \
263 BGE_MODECTL_WORDSWAP_NONFRAME| \
264 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
265#else
266#define BGE_DMA_SWAP_OPTIONS \
267 BGE_MODECTL_WORDSWAP_NONFRAME|BGE_MODECTL_BYTESWAP_NONFRAME| \
268 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA
269#endif
| |
270
271#define BGE_INIT \
272 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
273 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
274
275#define BGE_CHIPID_TIGON_I 0x4000
276#define BGE_CHIPID_TIGON_II 0x6000
277#define BGE_CHIPID_BCM5700_A0 0x7000
278#define BGE_CHIPID_BCM5700_A1 0x7001
279#define BGE_CHIPID_BCM5700_B0 0x7100
280#define BGE_CHIPID_BCM5700_B1 0x7101
281#define BGE_CHIPID_BCM5700_B2 0x7102
282#define BGE_CHIPID_BCM5700_B3 0x7103
283#define BGE_CHIPID_BCM5700_ALTIMA 0x7104
284#define BGE_CHIPID_BCM5700_C0 0x7200
285#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
286#define BGE_CHIPID_BCM5701_B0 0x0100
287#define BGE_CHIPID_BCM5701_B2 0x0102
288#define BGE_CHIPID_BCM5701_B5 0x0105
289#define BGE_CHIPID_BCM5703_A0 0x1000
290#define BGE_CHIPID_BCM5703_A1 0x1001
291#define BGE_CHIPID_BCM5703_A2 0x1002
292#define BGE_CHIPID_BCM5703_A3 0x1003
293#define BGE_CHIPID_BCM5703_B0 0x1100
294#define BGE_CHIPID_BCM5704_A0 0x2000
295#define BGE_CHIPID_BCM5704_A1 0x2001
296#define BGE_CHIPID_BCM5704_A2 0x2002
297#define BGE_CHIPID_BCM5704_A3 0x2003
298#define BGE_CHIPID_BCM5704_B0 0x2100
299#define BGE_CHIPID_BCM5705_A0 0x3000
300#define BGE_CHIPID_BCM5705_A1 0x3001
301#define BGE_CHIPID_BCM5705_A2 0x3002
302#define BGE_CHIPID_BCM5705_A3 0x3003
303#define BGE_CHIPID_BCM5750_A0 0x4000
304#define BGE_CHIPID_BCM5750_A1 0x4001
305#define BGE_CHIPID_BCM5750_A3 0x4000
306#define BGE_CHIPID_BCM5750_B0 0x4100
307#define BGE_CHIPID_BCM5750_B1 0x4101
308#define BGE_CHIPID_BCM5750_C0 0x4200
309#define BGE_CHIPID_BCM5750_C1 0x4201
310#define BGE_CHIPID_BCM5750_C2 0x4202
311#define BGE_CHIPID_BCM5714_A0 0x5000
312#define BGE_CHIPID_BCM5752_A0 0x6000
313#define BGE_CHIPID_BCM5752_A1 0x6001
314#define BGE_CHIPID_BCM5752_A2 0x6002
315#define BGE_CHIPID_BCM5714_B0 0x8000
316#define BGE_CHIPID_BCM5714_B3 0x8003
317#define BGE_CHIPID_BCM5715_A0 0x9000
318#define BGE_CHIPID_BCM5715_A1 0x9001
319#define BGE_CHIPID_BCM5715_A3 0x9003
320#define BGE_CHIPID_BCM5755_A0 0xa000
321#define BGE_CHIPID_BCM5755_A1 0xa001
322#define BGE_CHIPID_BCM5755_A2 0xa002
323#define BGE_CHIPID_BCM5722_A0 0xa200
324#define BGE_CHIPID_BCM5754_A0 0xb000
325#define BGE_CHIPID_BCM5754_A1 0xb001
326#define BGE_CHIPID_BCM5754_A2 0xb002
327#define BGE_CHIPID_BCM5761_A0 0x5761000
328#define BGE_CHIPID_BCM5761_A1 0x5761100
329#define BGE_CHIPID_BCM5784_A0 0x5784000
330#define BGE_CHIPID_BCM5784_A1 0x5784100
331#define BGE_CHIPID_BCM5787_A0 0xb000
332#define BGE_CHIPID_BCM5787_A1 0xb001
333#define BGE_CHIPID_BCM5787_A2 0xb002
334#define BGE_CHIPID_BCM5906_A0 0xc000
335#define BGE_CHIPID_BCM5906_A1 0xc001
336#define BGE_CHIPID_BCM5906_A2 0xc002
337#define BGE_CHIPID_BCM57780_A0 0x57780000
338#define BGE_CHIPID_BCM57780_A1 0x57780001
339#define BGE_CHIPID_BCM5717_A0 0x05717000
340#define BGE_CHIPID_BCM5717_B0 0x05717100
341#define BGE_CHIPID_BCM5719_A0 0x05719000
| 261
262#define BGE_INIT \
263 (BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_CLEAR_INTA| \
264 BGE_PCIMISCCTL_MASK_PCI_INTR|BGE_PCIMISCCTL_INDIRECT_ACCESS)
265
266#define BGE_CHIPID_TIGON_I 0x4000
267#define BGE_CHIPID_TIGON_II 0x6000
268#define BGE_CHIPID_BCM5700_A0 0x7000
269#define BGE_CHIPID_BCM5700_A1 0x7001
270#define BGE_CHIPID_BCM5700_B0 0x7100
271#define BGE_CHIPID_BCM5700_B1 0x7101
272#define BGE_CHIPID_BCM5700_B2 0x7102
273#define BGE_CHIPID_BCM5700_B3 0x7103
274#define BGE_CHIPID_BCM5700_ALTIMA 0x7104
275#define BGE_CHIPID_BCM5700_C0 0x7200
276#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr */
277#define BGE_CHIPID_BCM5701_B0 0x0100
278#define BGE_CHIPID_BCM5701_B2 0x0102
279#define BGE_CHIPID_BCM5701_B5 0x0105
280#define BGE_CHIPID_BCM5703_A0 0x1000
281#define BGE_CHIPID_BCM5703_A1 0x1001
282#define BGE_CHIPID_BCM5703_A2 0x1002
283#define BGE_CHIPID_BCM5703_A3 0x1003
284#define BGE_CHIPID_BCM5703_B0 0x1100
285#define BGE_CHIPID_BCM5704_A0 0x2000
286#define BGE_CHIPID_BCM5704_A1 0x2001
287#define BGE_CHIPID_BCM5704_A2 0x2002
288#define BGE_CHIPID_BCM5704_A3 0x2003
289#define BGE_CHIPID_BCM5704_B0 0x2100
290#define BGE_CHIPID_BCM5705_A0 0x3000
291#define BGE_CHIPID_BCM5705_A1 0x3001
292#define BGE_CHIPID_BCM5705_A2 0x3002
293#define BGE_CHIPID_BCM5705_A3 0x3003
294#define BGE_CHIPID_BCM5750_A0 0x4000
295#define BGE_CHIPID_BCM5750_A1 0x4001
296#define BGE_CHIPID_BCM5750_A3 0x4000
297#define BGE_CHIPID_BCM5750_B0 0x4100
298#define BGE_CHIPID_BCM5750_B1 0x4101
299#define BGE_CHIPID_BCM5750_C0 0x4200
300#define BGE_CHIPID_BCM5750_C1 0x4201
301#define BGE_CHIPID_BCM5750_C2 0x4202
302#define BGE_CHIPID_BCM5714_A0 0x5000
303#define BGE_CHIPID_BCM5752_A0 0x6000
304#define BGE_CHIPID_BCM5752_A1 0x6001
305#define BGE_CHIPID_BCM5752_A2 0x6002
306#define BGE_CHIPID_BCM5714_B0 0x8000
307#define BGE_CHIPID_BCM5714_B3 0x8003
308#define BGE_CHIPID_BCM5715_A0 0x9000
309#define BGE_CHIPID_BCM5715_A1 0x9001
310#define BGE_CHIPID_BCM5715_A3 0x9003
311#define BGE_CHIPID_BCM5755_A0 0xa000
312#define BGE_CHIPID_BCM5755_A1 0xa001
313#define BGE_CHIPID_BCM5755_A2 0xa002
314#define BGE_CHIPID_BCM5722_A0 0xa200
315#define BGE_CHIPID_BCM5754_A0 0xb000
316#define BGE_CHIPID_BCM5754_A1 0xb001
317#define BGE_CHIPID_BCM5754_A2 0xb002
318#define BGE_CHIPID_BCM5761_A0 0x5761000
319#define BGE_CHIPID_BCM5761_A1 0x5761100
320#define BGE_CHIPID_BCM5784_A0 0x5784000
321#define BGE_CHIPID_BCM5784_A1 0x5784100
322#define BGE_CHIPID_BCM5787_A0 0xb000
323#define BGE_CHIPID_BCM5787_A1 0xb001
324#define BGE_CHIPID_BCM5787_A2 0xb002
325#define BGE_CHIPID_BCM5906_A0 0xc000
326#define BGE_CHIPID_BCM5906_A1 0xc001
327#define BGE_CHIPID_BCM5906_A2 0xc002
328#define BGE_CHIPID_BCM57780_A0 0x57780000
329#define BGE_CHIPID_BCM57780_A1 0x57780001
330#define BGE_CHIPID_BCM5717_A0 0x05717000
331#define BGE_CHIPID_BCM5717_B0 0x05717100
332#define BGE_CHIPID_BCM5719_A0 0x05719000
|
| 333#define BGE_CHIPID_BCM5720_A0 0x05720000
|
342#define BGE_CHIPID_BCM57765_A0 0x57785000
343#define BGE_CHIPID_BCM57765_B0 0x57785100
344
345/* shorthand one */
346#define BGE_ASICREV(x) ((x) >> 12)
347#define BGE_ASICREV_BCM5701 0x00
348#define BGE_ASICREV_BCM5703 0x01
349#define BGE_ASICREV_BCM5704 0x02
350#define BGE_ASICREV_BCM5705 0x03
351#define BGE_ASICREV_BCM5750 0x04
352#define BGE_ASICREV_BCM5714_A0 0x05
353#define BGE_ASICREV_BCM5752 0x06
354#define BGE_ASICREV_BCM5700 0x07
355#define BGE_ASICREV_BCM5780 0x08
356#define BGE_ASICREV_BCM5714 0x09
357#define BGE_ASICREV_BCM5755 0x0a
358#define BGE_ASICREV_BCM5754 0x0b
359#define BGE_ASICREV_BCM5787 0x0b
360#define BGE_ASICREV_BCM5906 0x0c
361/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
362#define BGE_ASICREV_USE_PRODID_REG 0x0f
363/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
364#define BGE_ASICREV_BCM5717 0x5717
365#define BGE_ASICREV_BCM5719 0x5719
| 334#define BGE_CHIPID_BCM57765_A0 0x57785000
335#define BGE_CHIPID_BCM57765_B0 0x57785100
336
337/* shorthand one */
338#define BGE_ASICREV(x) ((x) >> 12)
339#define BGE_ASICREV_BCM5701 0x00
340#define BGE_ASICREV_BCM5703 0x01
341#define BGE_ASICREV_BCM5704 0x02
342#define BGE_ASICREV_BCM5705 0x03
343#define BGE_ASICREV_BCM5750 0x04
344#define BGE_ASICREV_BCM5714_A0 0x05
345#define BGE_ASICREV_BCM5752 0x06
346#define BGE_ASICREV_BCM5700 0x07
347#define BGE_ASICREV_BCM5780 0x08
348#define BGE_ASICREV_BCM5714 0x09
349#define BGE_ASICREV_BCM5755 0x0a
350#define BGE_ASICREV_BCM5754 0x0b
351#define BGE_ASICREV_BCM5787 0x0b
352#define BGE_ASICREV_BCM5906 0x0c
353/* Should consult BGE_PCI_PRODID_ASICREV for ChipID */
354#define BGE_ASICREV_USE_PRODID_REG 0x0f
355/* BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. */
356#define BGE_ASICREV_BCM5717 0x5717
357#define BGE_ASICREV_BCM5719 0x5719
|
| 358#define BGE_ASICREV_BCM5720 0x5720
|
366#define BGE_ASICREV_BCM5761 0x5761
367#define BGE_ASICREV_BCM5784 0x5784
368#define BGE_ASICREV_BCM5785 0x5785
369#define BGE_ASICREV_BCM57765 0x57785
370#define BGE_ASICREV_BCM57780 0x57780
371
372/* chip revisions */
373#define BGE_CHIPREV(x) ((x) >> 8)
374#define BGE_CHIPREV_5700_AX 0x70
375#define BGE_CHIPREV_5700_BX 0x71
376#define BGE_CHIPREV_5700_CX 0x72
377#define BGE_CHIPREV_5701_AX 0x00
378#define BGE_CHIPREV_5703_AX 0x10
379#define BGE_CHIPREV_5704_AX 0x20
380#define BGE_CHIPREV_5704_BX 0x21
381#define BGE_CHIPREV_5750_AX 0x40
382#define BGE_CHIPREV_5750_BX 0x41
383/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
384#define BGE_CHIPREV_5717_AX 0x57170
385#define BGE_CHIPREV_5717_BX 0x57171
386#define BGE_CHIPREV_5761_AX 0x57611
387#define BGE_CHIPREV_5784_AX 0x57841
388
389/* PCI DMA Read/Write Control register */
390#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
391#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001
392#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
393#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
394#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
395#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
396#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
397#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
398#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
399#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
400#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
401#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
402#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
403
404#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
405#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
406#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
407#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
408
409#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080
410#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
411
412#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
413#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
414#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
415#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
416#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
417#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
418#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
419#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
420
421#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
422#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
423#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
424#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
425#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
426#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
427#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
428#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
429
430/*
431 * PCI state register -- note, this register is read only
432 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
433 * register is set.
434 */
435#define BGE_PCISTATE_FORCE_RESET 0x00000001
436#define BGE_PCISTATE_INTR_STATE 0x00000002
437#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
438#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
439#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
440#define BGE_PCISTATE_WANT_EXPROM 0x00000020
441#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
442#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
443#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
444
445/*
446 * PCI Clock Control register -- note, this register is read only
447 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
448 * register is set.
449 */
450#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
451#define BGE_PCICLOCKCTL_M66EN 0x00000080
452#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
453#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
454#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
455#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
456#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
457#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
458#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
459#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
460
461
462#ifndef PCIM_CMD_MWIEN
463#define PCIM_CMD_MWIEN 0x0010
464#endif
465#ifndef PCIM_CMD_INTxDIS
466#define PCIM_CMD_INTxDIS 0x0400
467#endif
468
469/*
470 * High priority mailbox registers
471 * Each mailbox is 64-bits wide, though we only use the
472 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
473 * first. The NIC will load the mailbox after the lower 32 bit word
474 * has been updated.
475 */
476#define BGE_MBX_IRQ0_HI 0x0200
477#define BGE_MBX_IRQ0_LO 0x0204
478#define BGE_MBX_IRQ1_HI 0x0208
479#define BGE_MBX_IRQ1_LO 0x020C
480#define BGE_MBX_IRQ2_HI 0x0210
481#define BGE_MBX_IRQ2_LO 0x0214
482#define BGE_MBX_IRQ3_HI 0x0218
483#define BGE_MBX_IRQ3_LO 0x021C
484#define BGE_MBX_GEN0_HI 0x0220
485#define BGE_MBX_GEN0_LO 0x0224
486#define BGE_MBX_GEN1_HI 0x0228
487#define BGE_MBX_GEN1_LO 0x022C
488#define BGE_MBX_GEN2_HI 0x0230
489#define BGE_MBX_GEN2_LO 0x0234
490#define BGE_MBX_GEN3_HI 0x0228
491#define BGE_MBX_GEN3_LO 0x022C
492#define BGE_MBX_GEN4_HI 0x0240
493#define BGE_MBX_GEN4_LO 0x0244
494#define BGE_MBX_GEN5_HI 0x0248
495#define BGE_MBX_GEN5_LO 0x024C
496#define BGE_MBX_GEN6_HI 0x0250
497#define BGE_MBX_GEN6_LO 0x0254
498#define BGE_MBX_GEN7_HI 0x0258
499#define BGE_MBX_GEN7_LO 0x025C
500#define BGE_MBX_RELOAD_STATS_HI 0x0260
501#define BGE_MBX_RELOAD_STATS_LO 0x0264
502#define BGE_MBX_RX_STD_PROD_HI 0x0268
503#define BGE_MBX_RX_STD_PROD_LO 0x026C
504#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
505#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
506#define BGE_MBX_RX_MINI_PROD_HI 0x0278
507#define BGE_MBX_RX_MINI_PROD_LO 0x027C
508#define BGE_MBX_RX_CONS0_HI 0x0280
509#define BGE_MBX_RX_CONS0_LO 0x0284
510#define BGE_MBX_RX_CONS1_HI 0x0288
511#define BGE_MBX_RX_CONS1_LO 0x028C
512#define BGE_MBX_RX_CONS2_HI 0x0290
513#define BGE_MBX_RX_CONS2_LO 0x0294
514#define BGE_MBX_RX_CONS3_HI 0x0298
515#define BGE_MBX_RX_CONS3_LO 0x029C
516#define BGE_MBX_RX_CONS4_HI 0x02A0
517#define BGE_MBX_RX_CONS4_LO 0x02A4
518#define BGE_MBX_RX_CONS5_HI 0x02A8
519#define BGE_MBX_RX_CONS5_LO 0x02AC
520#define BGE_MBX_RX_CONS6_HI 0x02B0
521#define BGE_MBX_RX_CONS6_LO 0x02B4
522#define BGE_MBX_RX_CONS7_HI 0x02B8
523#define BGE_MBX_RX_CONS7_LO 0x02BC
524#define BGE_MBX_RX_CONS8_HI 0x02C0
525#define BGE_MBX_RX_CONS8_LO 0x02C4
526#define BGE_MBX_RX_CONS9_HI 0x02C8
527#define BGE_MBX_RX_CONS9_LO 0x02CC
528#define BGE_MBX_RX_CONS10_HI 0x02D0
529#define BGE_MBX_RX_CONS10_LO 0x02D4
530#define BGE_MBX_RX_CONS11_HI 0x02D8
531#define BGE_MBX_RX_CONS11_LO 0x02DC
532#define BGE_MBX_RX_CONS12_HI 0x02E0
533#define BGE_MBX_RX_CONS12_LO 0x02E4
534#define BGE_MBX_RX_CONS13_HI 0x02E8
535#define BGE_MBX_RX_CONS13_LO 0x02EC
536#define BGE_MBX_RX_CONS14_HI 0x02F0
537#define BGE_MBX_RX_CONS14_LO 0x02F4
538#define BGE_MBX_RX_CONS15_HI 0x02F8
539#define BGE_MBX_RX_CONS15_LO 0x02FC
540#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
541#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
542#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
543#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
544#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
545#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
546#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
547#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
548#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
549#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
550#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
551#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
552#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
553#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
554#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
555#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
556#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
557#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
558#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
559#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
560#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
561#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
562#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
563#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
564#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
565#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
566#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
567#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
568#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
569#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
570#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
571#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
572#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
573#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
574#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
575#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
576#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
577#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
578#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
579#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
580#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
581#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
582#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
583#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
584#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
585#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
586#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
587#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
588#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
589#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
590#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
591#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
592#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
593#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
594#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
595#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
596#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
597#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
598#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
599#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
600#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
601#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
602#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
603#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
604
605#define BGE_TX_RINGS_MAX 4
606#define BGE_TX_RINGS_EXTSSRAM_MAX 16
607#define BGE_RX_RINGS_MAX 16
608#define BGE_RX_RINGS_MAX_5717 17
609
610/* Ethernet MAC control registers */
611#define BGE_MAC_MODE 0x0400
612#define BGE_MAC_STS 0x0404
613#define BGE_MAC_EVT_ENB 0x0408
614#define BGE_MAC_LED_CTL 0x040C
615#define BGE_MAC_ADDR1_LO 0x0410
616#define BGE_MAC_ADDR1_HI 0x0414
617#define BGE_MAC_ADDR2_LO 0x0418
618#define BGE_MAC_ADDR2_HI 0x041C
619#define BGE_MAC_ADDR3_LO 0x0420
620#define BGE_MAC_ADDR3_HI 0x0424
621#define BGE_MAC_ADDR4_LO 0x0428
622#define BGE_MAC_ADDR4_HI 0x042C
623#define BGE_WOL_PATPTR 0x0430
624#define BGE_WOL_PATCFG 0x0434
625#define BGE_TX_RANDOM_BACKOFF 0x0438
626#define BGE_RX_MTU 0x043C
627#define BGE_GBIT_PCS_TEST 0x0440
628#define BGE_TX_TBI_AUTONEG 0x0444
629#define BGE_RX_TBI_AUTONEG 0x0448
630#define BGE_MI_COMM 0x044C
631#define BGE_MI_STS 0x0450
632#define BGE_MI_MODE 0x0454
633#define BGE_AUTOPOLL_STS 0x0458
634#define BGE_TX_MODE 0x045C
635#define BGE_TX_STS 0x0460
636#define BGE_TX_LENGTHS 0x0464
637#define BGE_RX_MODE 0x0468
638#define BGE_RX_STS 0x046C
639#define BGE_MAR0 0x0470
640#define BGE_MAR1 0x0474
641#define BGE_MAR2 0x0478
642#define BGE_MAR3 0x047C
643#define BGE_RX_BD_RULES_CTL0 0x0480
644#define BGE_RX_BD_RULES_MASKVAL0 0x0484
645#define BGE_RX_BD_RULES_CTL1 0x0488
646#define BGE_RX_BD_RULES_MASKVAL1 0x048C
647#define BGE_RX_BD_RULES_CTL2 0x0490
648#define BGE_RX_BD_RULES_MASKVAL2 0x0494
649#define BGE_RX_BD_RULES_CTL3 0x0498
650#define BGE_RX_BD_RULES_MASKVAL3 0x049C
651#define BGE_RX_BD_RULES_CTL4 0x04A0
652#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
653#define BGE_RX_BD_RULES_CTL5 0x04A8
654#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
655#define BGE_RX_BD_RULES_CTL6 0x04B0
656#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
657#define BGE_RX_BD_RULES_CTL7 0x04B8
658#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
659#define BGE_RX_BD_RULES_CTL8 0x04C0
660#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
661#define BGE_RX_BD_RULES_CTL9 0x04C8
662#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
663#define BGE_RX_BD_RULES_CTL10 0x04D0
664#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
665#define BGE_RX_BD_RULES_CTL11 0x04D8
666#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
667#define BGE_RX_BD_RULES_CTL12 0x04E0
668#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
669#define BGE_RX_BD_RULES_CTL13 0x04E8
670#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
671#define BGE_RX_BD_RULES_CTL14 0x04F0
672#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
673#define BGE_RX_BD_RULES_CTL15 0x04F8
674#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
675#define BGE_RX_RULES_CFG 0x0500
676#define BGE_MAX_RX_FRAME_LOWAT 0x0504
677#define BGE_SERDES_CFG 0x0590
678#define BGE_SERDES_STS 0x0594
679#define BGE_SGDIG_CFG 0x05B0
680#define BGE_SGDIG_STS 0x05B4
681#define BGE_TX_MAC_STATS_OCTETS 0x0800
682#define BGE_TX_MAC_STATS_RESERVE_0 0x0804
683#define BGE_TX_MAC_STATS_COLLS 0x0808
684#define BGE_TX_MAC_STATS_XON_SENT 0x080C
685#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810
686#define BGE_TX_MAC_STATS_RESERVE_1 0x0814
687#define BGE_TX_MAC_STATS_ERRORS 0x0818
688#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C
689#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820
690#define BGE_TX_MAC_STATS_DEFERRED 0x0824
691#define BGE_TX_MAC_STATS_RESERVE_2 0x0828
692#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C
693#define BGE_TX_MAC_STATS_LATE_COLL 0x0830
694#define BGE_TX_MAC_STATS_RESERVE_3 0x0834
695#define BGE_TX_MAC_STATS_RESERVE_4 0x0838
696#define BGE_TX_MAC_STATS_RESERVE_5 0x083C
697#define BGE_TX_MAC_STATS_RESERVE_6 0x0840
698#define BGE_TX_MAC_STATS_RESERVE_7 0x0844
699#define BGE_TX_MAC_STATS_RESERVE_8 0x0848
700#define BGE_TX_MAC_STATS_RESERVE_9 0x084C
701#define BGE_TX_MAC_STATS_RESERVE_10 0x0850
702#define BGE_TX_MAC_STATS_RESERVE_11 0x0854
703#define BGE_TX_MAC_STATS_RESERVE_12 0x0858
704#define BGE_TX_MAC_STATS_RESERVE_13 0x085C
705#define BGE_TX_MAC_STATS_RESERVE_14 0x0860
706#define BGE_TX_MAC_STATS_RESERVE_15 0x0864
707#define BGE_TX_MAC_STATS_RESERVE_16 0x0868
708#define BGE_TX_MAC_STATS_UCAST 0x086C
709#define BGE_TX_MAC_STATS_MCAST 0x0870
710#define BGE_TX_MAC_STATS_BCAST 0x0874
711#define BGE_TX_MAC_STATS_RESERVE_17 0x0878
712#define BGE_TX_MAC_STATS_RESERVE_18 0x087C
713#define BGE_RX_MAC_STATS_OCTESTS 0x0880
714#define BGE_RX_MAC_STATS_RESERVE_0 0x0884
715#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888
716#define BGE_RX_MAC_STATS_UCAST 0x088C
717#define BGE_RX_MAC_STATS_MCAST 0x0890
718#define BGE_RX_MAC_STATS_BCAST 0x0894
719#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898
720#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C
721#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0
722#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4
723#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8
724#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC
725#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0
726#define BGE_RX_MAC_STATS_JABBERS 0x08B4
727#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8
728
729/* Ethernet MAC Mode register */
730#define BGE_MACMODE_RESET 0x00000001
731#define BGE_MACMODE_HALF_DUPLEX 0x00000002
732#define BGE_MACMODE_PORTMODE 0x0000000C
733#define BGE_MACMODE_LOOPBACK 0x00000010
734#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
735#define BGE_MACMODE_TX_BURST_ENB 0x00000100
736#define BGE_MACMODE_MAX_DEFER 0x00000200
737#define BGE_MACMODE_LINK_POLARITY 0x00000400
738#define BGE_MACMODE_RX_STATS_ENB 0x00000800
739#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
740#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
741#define BGE_MACMODE_TX_STATS_ENB 0x00004000
742#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
743#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
744#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
745#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
746#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
747#define BGE_MACMODE_MIP_ENB 0x00100000
748#define BGE_MACMODE_TXDMA_ENB 0x00200000
749#define BGE_MACMODE_RXDMA_ENB 0x00400000
750#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
751
752#define BGE_PORTMODE_NONE 0x00000000
753#define BGE_PORTMODE_MII 0x00000004
754#define BGE_PORTMODE_GMII 0x00000008
755#define BGE_PORTMODE_TBI 0x0000000C
756
757/* MAC Status register */
758#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
759#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
760#define BGE_MACSTAT_RX_CFG 0x00000004
761#define BGE_MACSTAT_CFG_CHANGED 0x00000008
762#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
763#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
764#define BGE_MACSTAT_LINK_CHANGED 0x00001000
765#define BGE_MACSTAT_MI_COMPLETE 0x00400000
766#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
767#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
768#define BGE_MACSTAT_ODI_ERROR 0x02000000
769#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
770#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
771
772/* MAC Event Enable Register */
773#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
774#define BGE_EVTENB_LINK_CHANGED 0x00001000
775#define BGE_EVTENB_MI_COMPLETE 0x00400000
776#define BGE_EVTENB_MI_INTERRUPT 0x00800000
777#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
778#define BGE_EVTENB_ODI_ERROR 0x02000000
779#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
780#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
781
782/* LED Control Register */
783#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
784#define BGE_LEDCTL_1000MBPS_LED 0x00000002
785#define BGE_LEDCTL_100MBPS_LED 0x00000004
786#define BGE_LEDCTL_10MBPS_LED 0x00000008
787#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
788#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
789#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
790#define BGE_LEDCTL_1000MBPS_STS 0x00000080
791#define BGE_LEDCTL_100MBPS_STS 0x00000100
792#define BGE_LEDCTL_10MBPS_STS 0x00000200
793#define BGE_LEDCTL_TRADLED_STS 0x00000400
794#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
795#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
796
797/* TX backoff seed register */
798#define BGE_TX_BACKOFF_SEED_MASK 0x3F
799
800/* Autopoll status register */
801#define BGE_AUTOPOLLSTS_ERROR 0x00000001
802
803/* Transmit MAC mode register */
804#define BGE_TXMODE_RESET 0x00000001
805#define BGE_TXMODE_ENABLE 0x00000002
806#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
807#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
808#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
809#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100
| 359#define BGE_ASICREV_BCM5761 0x5761
360#define BGE_ASICREV_BCM5784 0x5784
361#define BGE_ASICREV_BCM5785 0x5785
362#define BGE_ASICREV_BCM57765 0x57785
363#define BGE_ASICREV_BCM57780 0x57780
364
365/* chip revisions */
366#define BGE_CHIPREV(x) ((x) >> 8)
367#define BGE_CHIPREV_5700_AX 0x70
368#define BGE_CHIPREV_5700_BX 0x71
369#define BGE_CHIPREV_5700_CX 0x72
370#define BGE_CHIPREV_5701_AX 0x00
371#define BGE_CHIPREV_5703_AX 0x10
372#define BGE_CHIPREV_5704_AX 0x20
373#define BGE_CHIPREV_5704_BX 0x21
374#define BGE_CHIPREV_5750_AX 0x40
375#define BGE_CHIPREV_5750_BX 0x41
376/* BGE_PCI_PRODID_ASICREV chip rev. identifiers. */
377#define BGE_CHIPREV_5717_AX 0x57170
378#define BGE_CHIPREV_5717_BX 0x57171
379#define BGE_CHIPREV_5761_AX 0x57611
380#define BGE_CHIPREV_5784_AX 0x57841
381
382/* PCI DMA Read/Write Control register */
383#define BGE_PCIDMARWCTL_MINDMA 0x000000FF
384#define BGE_PCIDMARWCTL_DIS_CACHE_ALIGNMENT 0x00000001
385#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700
386#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800
387#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000
388#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000
389#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000
390#define BGE_PCIDMARWCTL_RD_WAT 0x00070000
391#define BGE_PCIDMARWCTL_WR_WAT 0x00380000
392#define BGE_PCIDMARWCTL_USE_MRM 0x00400000
393#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000
394#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000
395#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000
396
397#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16)
398#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19)
399#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24)
400#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28)
401
402#define BGE_PCIDMARWCTL_TAGGED_STATUS_WA 0x00000080
403#define BGE_PCIDMARWCTL_CRDRDR_RDMA_MRRS_MSK 0x00000380
404
405#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000
406#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100
407#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200
408#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300
409#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400
410#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500
411#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600
412#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700
413
414#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000
415#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800
416#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000
417#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800
418#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000
419#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800
420#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000
421#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800
422
423/*
424 * PCI state register -- note, this register is read only
425 * unless the PCISTATE_WR bit of the PCI Misc. Host Control
426 * register is set.
427 */
428#define BGE_PCISTATE_FORCE_RESET 0x00000001
429#define BGE_PCISTATE_INTR_STATE 0x00000002
430#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 /* 1 = PCI, 0 = PCI-X */
431#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 /* 1 = 66/133, 0 = 33/66 */
432#define BGE_PCISTATE_32BIT_BUS 0x00000010 /* 1 = 32bit, 0 = 64bit */
433#define BGE_PCISTATE_WANT_EXPROM 0x00000020
434#define BGE_PCISTATE_EXPROM_RETRY 0x00000040
435#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100
436#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00
437
438/*
439 * PCI Clock Control register -- note, this register is read only
440 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control
441 * register is set.
442 */
443#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F
444#define BGE_PCICLOCKCTL_M66EN 0x00000080
445#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200
446#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400
447#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800
448#define BGE_PCICLOCKCTL_ALTCLK 0x00001000
449#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000
450#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000
451#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000
452#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000
453
454
455#ifndef PCIM_CMD_MWIEN
456#define PCIM_CMD_MWIEN 0x0010
457#endif
458#ifndef PCIM_CMD_INTxDIS
459#define PCIM_CMD_INTxDIS 0x0400
460#endif
461
462/*
463 * High priority mailbox registers
464 * Each mailbox is 64-bits wide, though we only use the
465 * lower 32 bits. To write a 64-bit value, write the upper 32 bits
466 * first. The NIC will load the mailbox after the lower 32 bit word
467 * has been updated.
468 */
469#define BGE_MBX_IRQ0_HI 0x0200
470#define BGE_MBX_IRQ0_LO 0x0204
471#define BGE_MBX_IRQ1_HI 0x0208
472#define BGE_MBX_IRQ1_LO 0x020C
473#define BGE_MBX_IRQ2_HI 0x0210
474#define BGE_MBX_IRQ2_LO 0x0214
475#define BGE_MBX_IRQ3_HI 0x0218
476#define BGE_MBX_IRQ3_LO 0x021C
477#define BGE_MBX_GEN0_HI 0x0220
478#define BGE_MBX_GEN0_LO 0x0224
479#define BGE_MBX_GEN1_HI 0x0228
480#define BGE_MBX_GEN1_LO 0x022C
481#define BGE_MBX_GEN2_HI 0x0230
482#define BGE_MBX_GEN2_LO 0x0234
483#define BGE_MBX_GEN3_HI 0x0228
484#define BGE_MBX_GEN3_LO 0x022C
485#define BGE_MBX_GEN4_HI 0x0240
486#define BGE_MBX_GEN4_LO 0x0244
487#define BGE_MBX_GEN5_HI 0x0248
488#define BGE_MBX_GEN5_LO 0x024C
489#define BGE_MBX_GEN6_HI 0x0250
490#define BGE_MBX_GEN6_LO 0x0254
491#define BGE_MBX_GEN7_HI 0x0258
492#define BGE_MBX_GEN7_LO 0x025C
493#define BGE_MBX_RELOAD_STATS_HI 0x0260
494#define BGE_MBX_RELOAD_STATS_LO 0x0264
495#define BGE_MBX_RX_STD_PROD_HI 0x0268
496#define BGE_MBX_RX_STD_PROD_LO 0x026C
497#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270
498#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274
499#define BGE_MBX_RX_MINI_PROD_HI 0x0278
500#define BGE_MBX_RX_MINI_PROD_LO 0x027C
501#define BGE_MBX_RX_CONS0_HI 0x0280
502#define BGE_MBX_RX_CONS0_LO 0x0284
503#define BGE_MBX_RX_CONS1_HI 0x0288
504#define BGE_MBX_RX_CONS1_LO 0x028C
505#define BGE_MBX_RX_CONS2_HI 0x0290
506#define BGE_MBX_RX_CONS2_LO 0x0294
507#define BGE_MBX_RX_CONS3_HI 0x0298
508#define BGE_MBX_RX_CONS3_LO 0x029C
509#define BGE_MBX_RX_CONS4_HI 0x02A0
510#define BGE_MBX_RX_CONS4_LO 0x02A4
511#define BGE_MBX_RX_CONS5_HI 0x02A8
512#define BGE_MBX_RX_CONS5_LO 0x02AC
513#define BGE_MBX_RX_CONS6_HI 0x02B0
514#define BGE_MBX_RX_CONS6_LO 0x02B4
515#define BGE_MBX_RX_CONS7_HI 0x02B8
516#define BGE_MBX_RX_CONS7_LO 0x02BC
517#define BGE_MBX_RX_CONS8_HI 0x02C0
518#define BGE_MBX_RX_CONS8_LO 0x02C4
519#define BGE_MBX_RX_CONS9_HI 0x02C8
520#define BGE_MBX_RX_CONS9_LO 0x02CC
521#define BGE_MBX_RX_CONS10_HI 0x02D0
522#define BGE_MBX_RX_CONS10_LO 0x02D4
523#define BGE_MBX_RX_CONS11_HI 0x02D8
524#define BGE_MBX_RX_CONS11_LO 0x02DC
525#define BGE_MBX_RX_CONS12_HI 0x02E0
526#define BGE_MBX_RX_CONS12_LO 0x02E4
527#define BGE_MBX_RX_CONS13_HI 0x02E8
528#define BGE_MBX_RX_CONS13_LO 0x02EC
529#define BGE_MBX_RX_CONS14_HI 0x02F0
530#define BGE_MBX_RX_CONS14_LO 0x02F4
531#define BGE_MBX_RX_CONS15_HI 0x02F8
532#define BGE_MBX_RX_CONS15_LO 0x02FC
533#define BGE_MBX_TX_HOST_PROD0_HI 0x0300
534#define BGE_MBX_TX_HOST_PROD0_LO 0x0304
535#define BGE_MBX_TX_HOST_PROD1_HI 0x0308
536#define BGE_MBX_TX_HOST_PROD1_LO 0x030C
537#define BGE_MBX_TX_HOST_PROD2_HI 0x0310
538#define BGE_MBX_TX_HOST_PROD2_LO 0x0314
539#define BGE_MBX_TX_HOST_PROD3_HI 0x0318
540#define BGE_MBX_TX_HOST_PROD3_LO 0x031C
541#define BGE_MBX_TX_HOST_PROD4_HI 0x0320
542#define BGE_MBX_TX_HOST_PROD4_LO 0x0324
543#define BGE_MBX_TX_HOST_PROD5_HI 0x0328
544#define BGE_MBX_TX_HOST_PROD5_LO 0x032C
545#define BGE_MBX_TX_HOST_PROD6_HI 0x0330
546#define BGE_MBX_TX_HOST_PROD6_LO 0x0334
547#define BGE_MBX_TX_HOST_PROD7_HI 0x0338
548#define BGE_MBX_TX_HOST_PROD7_LO 0x033C
549#define BGE_MBX_TX_HOST_PROD8_HI 0x0340
550#define BGE_MBX_TX_HOST_PROD8_LO 0x0344
551#define BGE_MBX_TX_HOST_PROD9_HI 0x0348
552#define BGE_MBX_TX_HOST_PROD9_LO 0x034C
553#define BGE_MBX_TX_HOST_PROD10_HI 0x0350
554#define BGE_MBX_TX_HOST_PROD10_LO 0x0354
555#define BGE_MBX_TX_HOST_PROD11_HI 0x0358
556#define BGE_MBX_TX_HOST_PROD11_LO 0x035C
557#define BGE_MBX_TX_HOST_PROD12_HI 0x0360
558#define BGE_MBX_TX_HOST_PROD12_LO 0x0364
559#define BGE_MBX_TX_HOST_PROD13_HI 0x0368
560#define BGE_MBX_TX_HOST_PROD13_LO 0x036C
561#define BGE_MBX_TX_HOST_PROD14_HI 0x0370
562#define BGE_MBX_TX_HOST_PROD14_LO 0x0374
563#define BGE_MBX_TX_HOST_PROD15_HI 0x0378
564#define BGE_MBX_TX_HOST_PROD15_LO 0x037C
565#define BGE_MBX_TX_NIC_PROD0_HI 0x0380
566#define BGE_MBX_TX_NIC_PROD0_LO 0x0384
567#define BGE_MBX_TX_NIC_PROD1_HI 0x0388
568#define BGE_MBX_TX_NIC_PROD1_LO 0x038C
569#define BGE_MBX_TX_NIC_PROD2_HI 0x0390
570#define BGE_MBX_TX_NIC_PROD2_LO 0x0394
571#define BGE_MBX_TX_NIC_PROD3_HI 0x0398
572#define BGE_MBX_TX_NIC_PROD3_LO 0x039C
573#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0
574#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4
575#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8
576#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC
577#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0
578#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4
579#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8
580#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC
581#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0
582#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4
583#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8
584#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC
585#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0
586#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4
587#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8
588#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC
589#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0
590#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4
591#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8
592#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC
593#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0
594#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4
595#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8
596#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC
597
598#define BGE_TX_RINGS_MAX 4
599#define BGE_TX_RINGS_EXTSSRAM_MAX 16
600#define BGE_RX_RINGS_MAX 16
601#define BGE_RX_RINGS_MAX_5717 17
602
603/* Ethernet MAC control registers */
604#define BGE_MAC_MODE 0x0400
605#define BGE_MAC_STS 0x0404
606#define BGE_MAC_EVT_ENB 0x0408
607#define BGE_MAC_LED_CTL 0x040C
608#define BGE_MAC_ADDR1_LO 0x0410
609#define BGE_MAC_ADDR1_HI 0x0414
610#define BGE_MAC_ADDR2_LO 0x0418
611#define BGE_MAC_ADDR2_HI 0x041C
612#define BGE_MAC_ADDR3_LO 0x0420
613#define BGE_MAC_ADDR3_HI 0x0424
614#define BGE_MAC_ADDR4_LO 0x0428
615#define BGE_MAC_ADDR4_HI 0x042C
616#define BGE_WOL_PATPTR 0x0430
617#define BGE_WOL_PATCFG 0x0434
618#define BGE_TX_RANDOM_BACKOFF 0x0438
619#define BGE_RX_MTU 0x043C
620#define BGE_GBIT_PCS_TEST 0x0440
621#define BGE_TX_TBI_AUTONEG 0x0444
622#define BGE_RX_TBI_AUTONEG 0x0448
623#define BGE_MI_COMM 0x044C
624#define BGE_MI_STS 0x0450
625#define BGE_MI_MODE 0x0454
626#define BGE_AUTOPOLL_STS 0x0458
627#define BGE_TX_MODE 0x045C
628#define BGE_TX_STS 0x0460
629#define BGE_TX_LENGTHS 0x0464
630#define BGE_RX_MODE 0x0468
631#define BGE_RX_STS 0x046C
632#define BGE_MAR0 0x0470
633#define BGE_MAR1 0x0474
634#define BGE_MAR2 0x0478
635#define BGE_MAR3 0x047C
636#define BGE_RX_BD_RULES_CTL0 0x0480
637#define BGE_RX_BD_RULES_MASKVAL0 0x0484
638#define BGE_RX_BD_RULES_CTL1 0x0488
639#define BGE_RX_BD_RULES_MASKVAL1 0x048C
640#define BGE_RX_BD_RULES_CTL2 0x0490
641#define BGE_RX_BD_RULES_MASKVAL2 0x0494
642#define BGE_RX_BD_RULES_CTL3 0x0498
643#define BGE_RX_BD_RULES_MASKVAL3 0x049C
644#define BGE_RX_BD_RULES_CTL4 0x04A0
645#define BGE_RX_BD_RULES_MASKVAL4 0x04A4
646#define BGE_RX_BD_RULES_CTL5 0x04A8
647#define BGE_RX_BD_RULES_MASKVAL5 0x04AC
648#define BGE_RX_BD_RULES_CTL6 0x04B0
649#define BGE_RX_BD_RULES_MASKVAL6 0x04B4
650#define BGE_RX_BD_RULES_CTL7 0x04B8
651#define BGE_RX_BD_RULES_MASKVAL7 0x04BC
652#define BGE_RX_BD_RULES_CTL8 0x04C0
653#define BGE_RX_BD_RULES_MASKVAL8 0x04C4
654#define BGE_RX_BD_RULES_CTL9 0x04C8
655#define BGE_RX_BD_RULES_MASKVAL9 0x04CC
656#define BGE_RX_BD_RULES_CTL10 0x04D0
657#define BGE_RX_BD_RULES_MASKVAL10 0x04D4
658#define BGE_RX_BD_RULES_CTL11 0x04D8
659#define BGE_RX_BD_RULES_MASKVAL11 0x04DC
660#define BGE_RX_BD_RULES_CTL12 0x04E0
661#define BGE_RX_BD_RULES_MASKVAL12 0x04E4
662#define BGE_RX_BD_RULES_CTL13 0x04E8
663#define BGE_RX_BD_RULES_MASKVAL13 0x04EC
664#define BGE_RX_BD_RULES_CTL14 0x04F0
665#define BGE_RX_BD_RULES_MASKVAL14 0x04F4
666#define BGE_RX_BD_RULES_CTL15 0x04F8
667#define BGE_RX_BD_RULES_MASKVAL15 0x04FC
668#define BGE_RX_RULES_CFG 0x0500
669#define BGE_MAX_RX_FRAME_LOWAT 0x0504
670#define BGE_SERDES_CFG 0x0590
671#define BGE_SERDES_STS 0x0594
672#define BGE_SGDIG_CFG 0x05B0
673#define BGE_SGDIG_STS 0x05B4
674#define BGE_TX_MAC_STATS_OCTETS 0x0800
675#define BGE_TX_MAC_STATS_RESERVE_0 0x0804
676#define BGE_TX_MAC_STATS_COLLS 0x0808
677#define BGE_TX_MAC_STATS_XON_SENT 0x080C
678#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810
679#define BGE_TX_MAC_STATS_RESERVE_1 0x0814
680#define BGE_TX_MAC_STATS_ERRORS 0x0818
681#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C
682#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820
683#define BGE_TX_MAC_STATS_DEFERRED 0x0824
684#define BGE_TX_MAC_STATS_RESERVE_2 0x0828
685#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C
686#define BGE_TX_MAC_STATS_LATE_COLL 0x0830
687#define BGE_TX_MAC_STATS_RESERVE_3 0x0834
688#define BGE_TX_MAC_STATS_RESERVE_4 0x0838
689#define BGE_TX_MAC_STATS_RESERVE_5 0x083C
690#define BGE_TX_MAC_STATS_RESERVE_6 0x0840
691#define BGE_TX_MAC_STATS_RESERVE_7 0x0844
692#define BGE_TX_MAC_STATS_RESERVE_8 0x0848
693#define BGE_TX_MAC_STATS_RESERVE_9 0x084C
694#define BGE_TX_MAC_STATS_RESERVE_10 0x0850
695#define BGE_TX_MAC_STATS_RESERVE_11 0x0854
696#define BGE_TX_MAC_STATS_RESERVE_12 0x0858
697#define BGE_TX_MAC_STATS_RESERVE_13 0x085C
698#define BGE_TX_MAC_STATS_RESERVE_14 0x0860
699#define BGE_TX_MAC_STATS_RESERVE_15 0x0864
700#define BGE_TX_MAC_STATS_RESERVE_16 0x0868
701#define BGE_TX_MAC_STATS_UCAST 0x086C
702#define BGE_TX_MAC_STATS_MCAST 0x0870
703#define BGE_TX_MAC_STATS_BCAST 0x0874
704#define BGE_TX_MAC_STATS_RESERVE_17 0x0878
705#define BGE_TX_MAC_STATS_RESERVE_18 0x087C
706#define BGE_RX_MAC_STATS_OCTESTS 0x0880
707#define BGE_RX_MAC_STATS_RESERVE_0 0x0884
708#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888
709#define BGE_RX_MAC_STATS_UCAST 0x088C
710#define BGE_RX_MAC_STATS_MCAST 0x0890
711#define BGE_RX_MAC_STATS_BCAST 0x0894
712#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898
713#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C
714#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0
715#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4
716#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8
717#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC
718#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0
719#define BGE_RX_MAC_STATS_JABBERS 0x08B4
720#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8
721
722/* Ethernet MAC Mode register */
723#define BGE_MACMODE_RESET 0x00000001
724#define BGE_MACMODE_HALF_DUPLEX 0x00000002
725#define BGE_MACMODE_PORTMODE 0x0000000C
726#define BGE_MACMODE_LOOPBACK 0x00000010
727#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080
728#define BGE_MACMODE_TX_BURST_ENB 0x00000100
729#define BGE_MACMODE_MAX_DEFER 0x00000200
730#define BGE_MACMODE_LINK_POLARITY 0x00000400
731#define BGE_MACMODE_RX_STATS_ENB 0x00000800
732#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000
733#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000
734#define BGE_MACMODE_TX_STATS_ENB 0x00004000
735#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000
736#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000
737#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000
738#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000
739#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000
740#define BGE_MACMODE_MIP_ENB 0x00100000
741#define BGE_MACMODE_TXDMA_ENB 0x00200000
742#define BGE_MACMODE_RXDMA_ENB 0x00400000
743#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000
744
745#define BGE_PORTMODE_NONE 0x00000000
746#define BGE_PORTMODE_MII 0x00000004
747#define BGE_PORTMODE_GMII 0x00000008
748#define BGE_PORTMODE_TBI 0x0000000C
749
750/* MAC Status register */
751#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001
752#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002
753#define BGE_MACSTAT_RX_CFG 0x00000004
754#define BGE_MACSTAT_CFG_CHANGED 0x00000008
755#define BGE_MACSTAT_SYNC_CHANGED 0x00000010
756#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400
757#define BGE_MACSTAT_LINK_CHANGED 0x00001000
758#define BGE_MACSTAT_MI_COMPLETE 0x00400000
759#define BGE_MACSTAT_MI_INTERRUPT 0x00800000
760#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000
761#define BGE_MACSTAT_ODI_ERROR 0x02000000
762#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000
763#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000
764
765/* MAC Event Enable Register */
766#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400
767#define BGE_EVTENB_LINK_CHANGED 0x00001000
768#define BGE_EVTENB_MI_COMPLETE 0x00400000
769#define BGE_EVTENB_MI_INTERRUPT 0x00800000
770#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000
771#define BGE_EVTENB_ODI_ERROR 0x02000000
772#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000
773#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000
774
775/* LED Control Register */
776#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001
777#define BGE_LEDCTL_1000MBPS_LED 0x00000002
778#define BGE_LEDCTL_100MBPS_LED 0x00000004
779#define BGE_LEDCTL_10MBPS_LED 0x00000008
780#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010
781#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020
782#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040
783#define BGE_LEDCTL_1000MBPS_STS 0x00000080
784#define BGE_LEDCTL_100MBPS_STS 0x00000100
785#define BGE_LEDCTL_10MBPS_STS 0x00000200
786#define BGE_LEDCTL_TRADLED_STS 0x00000400
787#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000
788#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000
789
790/* TX backoff seed register */
791#define BGE_TX_BACKOFF_SEED_MASK 0x3F
792
793/* Autopoll status register */
794#define BGE_AUTOPOLLSTS_ERROR 0x00000001
795
796/* Transmit MAC mode register */
797#define BGE_TXMODE_RESET 0x00000001
798#define BGE_TXMODE_ENABLE 0x00000002
799#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010
800#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020
801#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040
802#define BGE_TXMODE_MBUF_LOCKUP_FIX 0x00000100
|
| 803#define BGE_TXMODE_JMB_FRM_LEN 0x00400000
804#define BGE_TXMODE_CNT_DN_MODE 0x00800000
|
810
811/* Transmit MAC status register */
812#define BGE_TXSTAT_RX_XOFFED 0x00000001
813#define BGE_TXSTAT_SENT_XOFF 0x00000002
814#define BGE_TXSTAT_SENT_XON 0x00000004
815#define BGE_TXSTAT_LINK_UP 0x00000008
816#define BGE_TXSTAT_ODI_UFLOW 0x00000010
817#define BGE_TXSTAT_ODI_OFLOW 0x00000020
818
819/* Transmit MAC lengths register */
820#define BGE_TXLEN_SLOTTIME 0x000000FF
821#define BGE_TXLEN_IPG 0x00000F00
822#define BGE_TXLEN_CRS 0x00003000
| 805
806/* Transmit MAC status register */
807#define BGE_TXSTAT_RX_XOFFED 0x00000001
808#define BGE_TXSTAT_SENT_XOFF 0x00000002
809#define BGE_TXSTAT_SENT_XON 0x00000004
810#define BGE_TXSTAT_LINK_UP 0x00000008
811#define BGE_TXSTAT_ODI_UFLOW 0x00000010
812#define BGE_TXSTAT_ODI_OFLOW 0x00000020
813
814/* Transmit MAC lengths register */
815#define BGE_TXLEN_SLOTTIME 0x000000FF
816#define BGE_TXLEN_IPG 0x00000F00
817#define BGE_TXLEN_CRS 0x00003000
|
| 818#define BGE_TXLEN_JMB_FRM_LEN_MSK 0x00FF0000
819#define BGE_TXLEN_CNT_DN_VAL_MSK 0xFF000000
|
823
824/* Receive MAC mode register */
825#define BGE_RXMODE_RESET 0x00000001
826#define BGE_RXMODE_ENABLE 0x00000002
827#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
828#define BGE_RXMODE_RX_GIANTS 0x00000020
829#define BGE_RXMODE_RX_RUNTS 0x00000040
830#define BGE_RXMODE_8022_LENCHECK 0x00000080
831#define BGE_RXMODE_RX_PROMISC 0x00000100
832#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
833#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
834
835/* Receive MAC status register */
836#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
837#define BGE_RXSTAT_RCVD_XOFF 0x00000002
838#define BGE_RXSTAT_RCVD_XON 0x00000004
839
840/* Receive Rules Control register */
841#define BGE_RXRULECTL_OFFSET 0x000000FF
842#define BGE_RXRULECTL_CLASS 0x00001F00
843#define BGE_RXRULECTL_HDRTYPE 0x0000E000
844#define BGE_RXRULECTL_COMPARE_OP 0x00030000
845#define BGE_RXRULECTL_MAP 0x01000000
846#define BGE_RXRULECTL_DISCARD 0x02000000
847#define BGE_RXRULECTL_MASK 0x04000000
848#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
849#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
850#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
851#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
852
853/* Receive Rules Mask register */
854#define BGE_RXRULEMASK_VALUE 0x0000FFFF
855#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
856
857/* SERDES configuration register */
858#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
859#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
860#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
861#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
862#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
863#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
864#define BGE_SERDESCFG_TXMODE 0x00001000
865#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
866#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
867#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
868#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
869#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
870#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
871#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
872#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
873#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
874
875/* SERDES status register */
876#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
877#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
878
879/* SGDIG config (not documented) */
880#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
881#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
882#define BGE_SGDIGCFG_SEND 0x40000000
883#define BGE_SGDIGCFG_AUTO 0x80000000
884
885/* SGDIG status (not documented) */
886#define BGE_SGDIGSTS_DONE 0x00000002
887#define BGE_SGDIGSTS_IS_SERDES 0x00000100
888#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
889#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
890
891
892/* MI communication register */
893#define BGE_MICOMM_DATA 0x0000FFFF
894#define BGE_MICOMM_REG 0x001F0000
895#define BGE_MICOMM_PHY 0x03E00000
896#define BGE_MICOMM_CMD 0x0C000000
897#define BGE_MICOMM_READFAIL 0x10000000
898#define BGE_MICOMM_BUSY 0x20000000
899
900#define BGE_MIREG(x) ((x & 0x1F) << 16)
901#define BGE_MIPHY(x) ((x & 0x1F) << 21)
902#define BGE_MICMD_WRITE 0x04000000
903#define BGE_MICMD_READ 0x08000000
904
905/* MI status register */
906#define BGE_MISTS_LINK 0x00000001
907#define BGE_MISTS_10MBPS 0x00000002
908
909#define BGE_MIMODE_CLK_10MHZ 0x00000001
910#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
911#define BGE_MIMODE_AUTOPOLL 0x00000010
912#define BGE_MIMODE_CLKCNT 0x001F0000
913#define BGE_MIMODE_500KHZ_CONST 0x00008000
914#define BGE_MIMODE_BASE 0x000C0000
915
916
917/*
918 * Send data initiator control registers.
919 */
920#define BGE_SDI_MODE 0x0C00
921#define BGE_SDI_STATUS 0x0C04
922#define BGE_SDI_STATS_CTL 0x0C08
923#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
924#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
925#define BGE_ISO_PKT_TX 0x0C20
926#define BGE_LOCSTATS_COS0 0x0C80
927#define BGE_LOCSTATS_COS1 0x0C84
928#define BGE_LOCSTATS_COS2 0x0C88
929#define BGE_LOCSTATS_COS3 0x0C8C
930#define BGE_LOCSTATS_COS4 0x0C90
931#define BGE_LOCSTATS_COS5 0x0C84
932#define BGE_LOCSTATS_COS6 0x0C98
933#define BGE_LOCSTATS_COS7 0x0C9C
934#define BGE_LOCSTATS_COS8 0x0CA0
935#define BGE_LOCSTATS_COS9 0x0CA4
936#define BGE_LOCSTATS_COS10 0x0CA8
937#define BGE_LOCSTATS_COS11 0x0CAC
938#define BGE_LOCSTATS_COS12 0x0CB0
939#define BGE_LOCSTATS_COS13 0x0CB4
940#define BGE_LOCSTATS_COS14 0x0CB8
941#define BGE_LOCSTATS_COS15 0x0CBC
942#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
943#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
944#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
945#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
946#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
947#define BGE_LOCSTATS_IRQS 0x0CD4
948#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
949#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
950
951/* Send Data Initiator mode register */
952#define BGE_SDIMODE_RESET 0x00000001
953#define BGE_SDIMODE_ENABLE 0x00000002
954#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
955#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008
956
957/* Send Data Initiator stats register */
958#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
959
960/* Send Data Initiator stats control register */
961#define BGE_SDISTATSCTL_ENABLE 0x00000001
962#define BGE_SDISTATSCTL_FASTER 0x00000002
963#define BGE_SDISTATSCTL_CLEAR 0x00000004
964#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
965#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
966
967/*
968 * Send Data Completion Control registers
969 */
970#define BGE_SDC_MODE 0x1000
971#define BGE_SDC_STATUS 0x1004
972
973/* Send Data completion mode register */
974#define BGE_SDCMODE_RESET 0x00000001
975#define BGE_SDCMODE_ENABLE 0x00000002
976#define BGE_SDCMODE_ATTN 0x00000004
977#define BGE_SDCMODE_CDELAY 0x00000010
978
979/* Send Data completion status register */
980#define BGE_SDCSTAT_ATTN 0x00000004
981
982/*
983 * Send BD Ring Selector Control registers
984 */
985#define BGE_SRS_MODE 0x1400
986#define BGE_SRS_STATUS 0x1404
987#define BGE_SRS_HWDIAG 0x1408
988#define BGE_SRS_LOC_NIC_CONS0 0x1440
989#define BGE_SRS_LOC_NIC_CONS1 0x1444
990#define BGE_SRS_LOC_NIC_CONS2 0x1448
991#define BGE_SRS_LOC_NIC_CONS3 0x144C
992#define BGE_SRS_LOC_NIC_CONS4 0x1450
993#define BGE_SRS_LOC_NIC_CONS5 0x1454
994#define BGE_SRS_LOC_NIC_CONS6 0x1458
995#define BGE_SRS_LOC_NIC_CONS7 0x145C
996#define BGE_SRS_LOC_NIC_CONS8 0x1460
997#define BGE_SRS_LOC_NIC_CONS9 0x1464
998#define BGE_SRS_LOC_NIC_CONS10 0x1468
999#define BGE_SRS_LOC_NIC_CONS11 0x146C
1000#define BGE_SRS_LOC_NIC_CONS12 0x1470
1001#define BGE_SRS_LOC_NIC_CONS13 0x1474
1002#define BGE_SRS_LOC_NIC_CONS14 0x1478
1003#define BGE_SRS_LOC_NIC_CONS15 0x147C
1004
1005/* Send BD Ring Selector Mode register */
1006#define BGE_SRSMODE_RESET 0x00000001
1007#define BGE_SRSMODE_ENABLE 0x00000002
1008#define BGE_SRSMODE_ATTN 0x00000004
1009
1010/* Send BD Ring Selector Status register */
1011#define BGE_SRSSTAT_ERROR 0x00000004
1012
1013/* Send BD Ring Selector HW Diagnostics register */
1014#define BGE_SRSHWDIAG_STATE 0x0000000F
1015#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
1016#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
1017#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
1018
1019/*
1020 * Send BD Initiator Selector Control registers
1021 */
1022#define BGE_SBDI_MODE 0x1800
1023#define BGE_SBDI_STATUS 0x1804
1024#define BGE_SBDI_LOC_NIC_PROD0 0x1808
1025#define BGE_SBDI_LOC_NIC_PROD1 0x180C
1026#define BGE_SBDI_LOC_NIC_PROD2 0x1810
1027#define BGE_SBDI_LOC_NIC_PROD3 0x1814
1028#define BGE_SBDI_LOC_NIC_PROD4 0x1818
1029#define BGE_SBDI_LOC_NIC_PROD5 0x181C
1030#define BGE_SBDI_LOC_NIC_PROD6 0x1820
1031#define BGE_SBDI_LOC_NIC_PROD7 0x1824
1032#define BGE_SBDI_LOC_NIC_PROD8 0x1828
1033#define BGE_SBDI_LOC_NIC_PROD9 0x182C
1034#define BGE_SBDI_LOC_NIC_PROD10 0x1830
1035#define BGE_SBDI_LOC_NIC_PROD11 0x1834
1036#define BGE_SBDI_LOC_NIC_PROD12 0x1838
1037#define BGE_SBDI_LOC_NIC_PROD13 0x183C
1038#define BGE_SBDI_LOC_NIC_PROD14 0x1840
1039#define BGE_SBDI_LOC_NIC_PROD15 0x1844
1040
1041/* Send BD Initiator Mode register */
1042#define BGE_SBDIMODE_RESET 0x00000001
1043#define BGE_SBDIMODE_ENABLE 0x00000002
1044#define BGE_SBDIMODE_ATTN 0x00000004
1045
1046/* Send BD Initiator Status register */
1047#define BGE_SBDISTAT_ERROR 0x00000004
1048
1049/*
1050 * Send BD Completion Control registers
1051 */
1052#define BGE_SBDC_MODE 0x1C00
1053#define BGE_SBDC_STATUS 0x1C04
1054
1055/* Send BD Completion Control Mode register */
1056#define BGE_SBDCMODE_RESET 0x00000001
1057#define BGE_SBDCMODE_ENABLE 0x00000002
1058#define BGE_SBDCMODE_ATTN 0x00000004
1059
1060/* Send BD Completion Control Status register */
1061#define BGE_SBDCSTAT_ATTN 0x00000004
1062
1063/*
1064 * Receive List Placement Control registers
1065 */
1066#define BGE_RXLP_MODE 0x2000
1067#define BGE_RXLP_STATUS 0x2004
1068#define BGE_RXLP_SEL_LIST_LOCK 0x2008
1069#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
1070#define BGE_RXLP_CFG 0x2010
1071#define BGE_RXLP_STATS_CTL 0x2014
1072#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
1073#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
1074#define BGE_RXLP_HEAD0 0x2100
1075#define BGE_RXLP_TAIL0 0x2104
1076#define BGE_RXLP_COUNT0 0x2108
1077#define BGE_RXLP_HEAD1 0x2110
1078#define BGE_RXLP_TAIL1 0x2114
1079#define BGE_RXLP_COUNT1 0x2118
1080#define BGE_RXLP_HEAD2 0x2120
1081#define BGE_RXLP_TAIL2 0x2124
1082#define BGE_RXLP_COUNT2 0x2128
1083#define BGE_RXLP_HEAD3 0x2130
1084#define BGE_RXLP_TAIL3 0x2134
1085#define BGE_RXLP_COUNT3 0x2138
1086#define BGE_RXLP_HEAD4 0x2140
1087#define BGE_RXLP_TAIL4 0x2144
1088#define BGE_RXLP_COUNT4 0x2148
1089#define BGE_RXLP_HEAD5 0x2150
1090#define BGE_RXLP_TAIL5 0x2154
1091#define BGE_RXLP_COUNT5 0x2158
1092#define BGE_RXLP_HEAD6 0x2160
1093#define BGE_RXLP_TAIL6 0x2164
1094#define BGE_RXLP_COUNT6 0x2168
1095#define BGE_RXLP_HEAD7 0x2170
1096#define BGE_RXLP_TAIL7 0x2174
1097#define BGE_RXLP_COUNT7 0x2178
1098#define BGE_RXLP_HEAD8 0x2180
1099#define BGE_RXLP_TAIL8 0x2184
1100#define BGE_RXLP_COUNT8 0x2188
1101#define BGE_RXLP_HEAD9 0x2190
1102#define BGE_RXLP_TAIL9 0x2194
1103#define BGE_RXLP_COUNT9 0x2198
1104#define BGE_RXLP_HEAD10 0x21A0
1105#define BGE_RXLP_TAIL10 0x21A4
1106#define BGE_RXLP_COUNT10 0x21A8
1107#define BGE_RXLP_HEAD11 0x21B0
1108#define BGE_RXLP_TAIL11 0x21B4
1109#define BGE_RXLP_COUNT11 0x21B8
1110#define BGE_RXLP_HEAD12 0x21C0
1111#define BGE_RXLP_TAIL12 0x21C4
1112#define BGE_RXLP_COUNT12 0x21C8
1113#define BGE_RXLP_HEAD13 0x21D0
1114#define BGE_RXLP_TAIL13 0x21D4
1115#define BGE_RXLP_COUNT13 0x21D8
1116#define BGE_RXLP_HEAD14 0x21E0
1117#define BGE_RXLP_TAIL14 0x21E4
1118#define BGE_RXLP_COUNT14 0x21E8
1119#define BGE_RXLP_HEAD15 0x21F0
1120#define BGE_RXLP_TAIL15 0x21F4
1121#define BGE_RXLP_COUNT15 0x21F8
1122#define BGE_RXLP_LOCSTAT_COS0 0x2200
1123#define BGE_RXLP_LOCSTAT_COS1 0x2204
1124#define BGE_RXLP_LOCSTAT_COS2 0x2208
1125#define BGE_RXLP_LOCSTAT_COS3 0x220C
1126#define BGE_RXLP_LOCSTAT_COS4 0x2210
1127#define BGE_RXLP_LOCSTAT_COS5 0x2214
1128#define BGE_RXLP_LOCSTAT_COS6 0x2218
1129#define BGE_RXLP_LOCSTAT_COS7 0x221C
1130#define BGE_RXLP_LOCSTAT_COS8 0x2220
1131#define BGE_RXLP_LOCSTAT_COS9 0x2224
1132#define BGE_RXLP_LOCSTAT_COS10 0x2228
1133#define BGE_RXLP_LOCSTAT_COS11 0x222C
1134#define BGE_RXLP_LOCSTAT_COS12 0x2230
1135#define BGE_RXLP_LOCSTAT_COS13 0x2234
1136#define BGE_RXLP_LOCSTAT_COS14 0x2238
1137#define BGE_RXLP_LOCSTAT_COS15 0x223C
1138#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1139#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1140#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1141#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1142#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1143#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1144#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1145
1146
1147/* Receive List Placement mode register */
1148#define BGE_RXLPMODE_RESET 0x00000001
1149#define BGE_RXLPMODE_ENABLE 0x00000002
1150#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1151#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1152#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1153
1154/* Receive List Placement Status register */
1155#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1156#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1157#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1158
1159/*
1160 * Receive Data and Receive BD Initiator Control Registers
1161 */
1162#define BGE_RDBDI_MODE 0x2400
1163#define BGE_RDBDI_STATUS 0x2404
1164#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1165#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1166#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1167#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1168#define BGE_RX_STD_RCB_HADDR_HI 0x2450
1169#define BGE_RX_STD_RCB_HADDR_LO 0x2454
1170#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1171#define BGE_RX_STD_RCB_NICADDR 0x245C
1172#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1173#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1174#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1175#define BGE_RX_MINI_RCB_NICADDR 0x246C
1176#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1177#define BGE_RDBDI_STD_RX_CONS 0x2474
1178#define BGE_RDBDI_MINI_RX_CONS 0x2478
1179#define BGE_RDBDI_RETURN_PROD0 0x2480
1180#define BGE_RDBDI_RETURN_PROD1 0x2484
1181#define BGE_RDBDI_RETURN_PROD2 0x2488
1182#define BGE_RDBDI_RETURN_PROD3 0x248C
1183#define BGE_RDBDI_RETURN_PROD4 0x2490
1184#define BGE_RDBDI_RETURN_PROD5 0x2494
1185#define BGE_RDBDI_RETURN_PROD6 0x2498
1186#define BGE_RDBDI_RETURN_PROD7 0x249C
1187#define BGE_RDBDI_RETURN_PROD8 0x24A0
1188#define BGE_RDBDI_RETURN_PROD9 0x24A4
1189#define BGE_RDBDI_RETURN_PROD10 0x24A8
1190#define BGE_RDBDI_RETURN_PROD11 0x24AC
1191#define BGE_RDBDI_RETURN_PROD12 0x24B0
1192#define BGE_RDBDI_RETURN_PROD13 0x24B4
1193#define BGE_RDBDI_RETURN_PROD14 0x24B8
1194#define BGE_RDBDI_RETURN_PROD15 0x24BC
1195#define BGE_RDBDI_HWDIAG 0x24C0
1196
1197
1198/* Receive Data and Receive BD Initiator Mode register */
1199#define BGE_RDBDIMODE_RESET 0x00000001
1200#define BGE_RDBDIMODE_ENABLE 0x00000002
1201#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1202#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1203#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1204
1205/* Receive Data and Receive BD Initiator Status register */
1206#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1207#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1208#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1209
1210
1211/*
1212 * Receive Data Completion Control registers
1213 */
1214#define BGE_RDC_MODE 0x2800
1215
1216/* Receive Data Completion Mode register */
1217#define BGE_RDCMODE_RESET 0x00000001
1218#define BGE_RDCMODE_ENABLE 0x00000002
1219#define BGE_RDCMODE_ATTN 0x00000004
1220
1221/*
1222 * Receive BD Initiator Control registers
1223 */
1224#define BGE_RBDI_MODE 0x2C00
1225#define BGE_RBDI_STATUS 0x2C04
1226#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1227#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1228#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1229#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1230#define BGE_RBDI_STD_REPL_THRESH 0x2C18
1231#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1232
1233#define BGE_STD_REPLENISH_LWM 0x2D00
1234#define BGE_JMB_REPLENISH_LWM 0x2D04
1235
1236/* Receive BD Initiator Mode register */
1237#define BGE_RBDIMODE_RESET 0x00000001
1238#define BGE_RBDIMODE_ENABLE 0x00000002
1239#define BGE_RBDIMODE_ATTN 0x00000004
1240
1241/* Receive BD Initiator Status register */
1242#define BGE_RBDISTAT_ATTN 0x00000004
1243
1244/*
1245 * Receive BD Completion Control registers
1246 */
1247#define BGE_RBDC_MODE 0x3000
1248#define BGE_RBDC_STATUS 0x3004
1249#define BGE_RBDC_JUMBO_BD_PROD 0x3008
1250#define BGE_RBDC_STD_BD_PROD 0x300C
1251#define BGE_RBDC_MINI_BD_PROD 0x3010
1252
1253/* Receive BD completion mode register */
1254#define BGE_RBDCMODE_RESET 0x00000001
1255#define BGE_RBDCMODE_ENABLE 0x00000002
1256#define BGE_RBDCMODE_ATTN 0x00000004
1257
1258/* Receive BD completion status register */
1259#define BGE_RBDCSTAT_ERROR 0x00000004
1260
1261/*
1262 * Receive List Selector Control registers
1263 */
1264#define BGE_RXLS_MODE 0x3400
1265#define BGE_RXLS_STATUS 0x3404
1266
1267/* Receive List Selector Mode register */
1268#define BGE_RXLSMODE_RESET 0x00000001
1269#define BGE_RXLSMODE_ENABLE 0x00000002
1270#define BGE_RXLSMODE_ATTN 0x00000004
1271
1272/* Receive List Selector Status register */
1273#define BGE_RXLSSTAT_ERROR 0x00000004
1274
1275#define BGE_CPMU_CTRL 0x3600
1276#define BGE_CPMU_LSPD_10MB_CLK 0x3604
1277#define BGE_CPMU_LSPD_1000MB_CLK 0x360C
1278#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
1279#define BGE_CPMU_HST_ACC 0x361C
| 820
821/* Receive MAC mode register */
822#define BGE_RXMODE_RESET 0x00000001
823#define BGE_RXMODE_ENABLE 0x00000002
824#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004
825#define BGE_RXMODE_RX_GIANTS 0x00000020
826#define BGE_RXMODE_RX_RUNTS 0x00000040
827#define BGE_RXMODE_8022_LENCHECK 0x00000080
828#define BGE_RXMODE_RX_PROMISC 0x00000100
829#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200
830#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400
831
832/* Receive MAC status register */
833#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001
834#define BGE_RXSTAT_RCVD_XOFF 0x00000002
835#define BGE_RXSTAT_RCVD_XON 0x00000004
836
837/* Receive Rules Control register */
838#define BGE_RXRULECTL_OFFSET 0x000000FF
839#define BGE_RXRULECTL_CLASS 0x00001F00
840#define BGE_RXRULECTL_HDRTYPE 0x0000E000
841#define BGE_RXRULECTL_COMPARE_OP 0x00030000
842#define BGE_RXRULECTL_MAP 0x01000000
843#define BGE_RXRULECTL_DISCARD 0x02000000
844#define BGE_RXRULECTL_MASK 0x04000000
845#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000
846#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000
847#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000
848#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000
849
850/* Receive Rules Mask register */
851#define BGE_RXRULEMASK_VALUE 0x0000FFFF
852#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000
853
854/* SERDES configuration register */
855#define BGE_SERDESCFG_RXR 0x00000007 /* phase interpolator */
856#define BGE_SERDESCFG_RXG 0x00000018 /* rx gain setting */
857#define BGE_SERDESCFG_RXEDGESEL 0x00000040 /* rising/falling egde */
858#define BGE_SERDESCFG_TX_BIAS 0x00000380 /* TXDAC bias setting */
859#define BGE_SERDESCFG_IBMAX 0x00000400 /* bias current +25% */
860#define BGE_SERDESCFG_IBMIN 0x00000800 /* bias current -25% */
861#define BGE_SERDESCFG_TXMODE 0x00001000
862#define BGE_SERDESCFG_TXEDGESEL 0x00002000 /* rising/falling edge */
863#define BGE_SERDESCFG_MODE 0x00004000 /* TXCP/TXCN disabled */
864#define BGE_SERDESCFG_PLLTEST 0x00008000 /* PLL test mode */
865#define BGE_SERDESCFG_CDET 0x00010000 /* comma detect enable */
866#define BGE_SERDESCFG_TBILOOP 0x00020000 /* local loopback */
867#define BGE_SERDESCFG_REMLOOP 0x00040000 /* remote loopback */
868#define BGE_SERDESCFG_INVPHASE 0x00080000 /* Reverse 125Mhz clock */
869#define BGE_SERDESCFG_12REGCTL 0x00300000 /* 1.2v regulator ctl */
870#define BGE_SERDESCFG_REGCTL 0x00C00000 /* regulator ctl (2.5v) */
871
872/* SERDES status register */
873#define BGE_SERDESSTS_RXSTAT 0x0000000F /* receive status bits */
874#define BGE_SERDESSTS_CDET 0x00000010 /* comma code detected */
875
876/* SGDIG config (not documented) */
877#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800
878#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000
879#define BGE_SGDIGCFG_SEND 0x40000000
880#define BGE_SGDIGCFG_AUTO 0x80000000
881
882/* SGDIG status (not documented) */
883#define BGE_SGDIGSTS_DONE 0x00000002
884#define BGE_SGDIGSTS_IS_SERDES 0x00000100
885#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000
886#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000
887
888
889/* MI communication register */
890#define BGE_MICOMM_DATA 0x0000FFFF
891#define BGE_MICOMM_REG 0x001F0000
892#define BGE_MICOMM_PHY 0x03E00000
893#define BGE_MICOMM_CMD 0x0C000000
894#define BGE_MICOMM_READFAIL 0x10000000
895#define BGE_MICOMM_BUSY 0x20000000
896
897#define BGE_MIREG(x) ((x & 0x1F) << 16)
898#define BGE_MIPHY(x) ((x & 0x1F) << 21)
899#define BGE_MICMD_WRITE 0x04000000
900#define BGE_MICMD_READ 0x08000000
901
902/* MI status register */
903#define BGE_MISTS_LINK 0x00000001
904#define BGE_MISTS_10MBPS 0x00000002
905
906#define BGE_MIMODE_CLK_10MHZ 0x00000001
907#define BGE_MIMODE_SHORTPREAMBLE 0x00000002
908#define BGE_MIMODE_AUTOPOLL 0x00000010
909#define BGE_MIMODE_CLKCNT 0x001F0000
910#define BGE_MIMODE_500KHZ_CONST 0x00008000
911#define BGE_MIMODE_BASE 0x000C0000
912
913
914/*
915 * Send data initiator control registers.
916 */
917#define BGE_SDI_MODE 0x0C00
918#define BGE_SDI_STATUS 0x0C04
919#define BGE_SDI_STATS_CTL 0x0C08
920#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C
921#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10
922#define BGE_ISO_PKT_TX 0x0C20
923#define BGE_LOCSTATS_COS0 0x0C80
924#define BGE_LOCSTATS_COS1 0x0C84
925#define BGE_LOCSTATS_COS2 0x0C88
926#define BGE_LOCSTATS_COS3 0x0C8C
927#define BGE_LOCSTATS_COS4 0x0C90
928#define BGE_LOCSTATS_COS5 0x0C84
929#define BGE_LOCSTATS_COS6 0x0C98
930#define BGE_LOCSTATS_COS7 0x0C9C
931#define BGE_LOCSTATS_COS8 0x0CA0
932#define BGE_LOCSTATS_COS9 0x0CA4
933#define BGE_LOCSTATS_COS10 0x0CA8
934#define BGE_LOCSTATS_COS11 0x0CAC
935#define BGE_LOCSTATS_COS12 0x0CB0
936#define BGE_LOCSTATS_COS13 0x0CB4
937#define BGE_LOCSTATS_COS14 0x0CB8
938#define BGE_LOCSTATS_COS15 0x0CBC
939#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0
940#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4
941#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8
942#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC
943#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0
944#define BGE_LOCSTATS_IRQS 0x0CD4
945#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8
946#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC
947
948/* Send Data Initiator mode register */
949#define BGE_SDIMODE_RESET 0x00000001
950#define BGE_SDIMODE_ENABLE 0x00000002
951#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004
952#define BGE_SDIMODE_HW_LSO_PRE_DMA 0x00000008
953
954/* Send Data Initiator stats register */
955#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004
956
957/* Send Data Initiator stats control register */
958#define BGE_SDISTATSCTL_ENABLE 0x00000001
959#define BGE_SDISTATSCTL_FASTER 0x00000002
960#define BGE_SDISTATSCTL_CLEAR 0x00000004
961#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008
962#define BGE_SDISTATSCTL_FORCEZERO 0x00000010
963
964/*
965 * Send Data Completion Control registers
966 */
967#define BGE_SDC_MODE 0x1000
968#define BGE_SDC_STATUS 0x1004
969
970/* Send Data completion mode register */
971#define BGE_SDCMODE_RESET 0x00000001
972#define BGE_SDCMODE_ENABLE 0x00000002
973#define BGE_SDCMODE_ATTN 0x00000004
974#define BGE_SDCMODE_CDELAY 0x00000010
975
976/* Send Data completion status register */
977#define BGE_SDCSTAT_ATTN 0x00000004
978
979/*
980 * Send BD Ring Selector Control registers
981 */
982#define BGE_SRS_MODE 0x1400
983#define BGE_SRS_STATUS 0x1404
984#define BGE_SRS_HWDIAG 0x1408
985#define BGE_SRS_LOC_NIC_CONS0 0x1440
986#define BGE_SRS_LOC_NIC_CONS1 0x1444
987#define BGE_SRS_LOC_NIC_CONS2 0x1448
988#define BGE_SRS_LOC_NIC_CONS3 0x144C
989#define BGE_SRS_LOC_NIC_CONS4 0x1450
990#define BGE_SRS_LOC_NIC_CONS5 0x1454
991#define BGE_SRS_LOC_NIC_CONS6 0x1458
992#define BGE_SRS_LOC_NIC_CONS7 0x145C
993#define BGE_SRS_LOC_NIC_CONS8 0x1460
994#define BGE_SRS_LOC_NIC_CONS9 0x1464
995#define BGE_SRS_LOC_NIC_CONS10 0x1468
996#define BGE_SRS_LOC_NIC_CONS11 0x146C
997#define BGE_SRS_LOC_NIC_CONS12 0x1470
998#define BGE_SRS_LOC_NIC_CONS13 0x1474
999#define BGE_SRS_LOC_NIC_CONS14 0x1478
1000#define BGE_SRS_LOC_NIC_CONS15 0x147C
1001
1002/* Send BD Ring Selector Mode register */
1003#define BGE_SRSMODE_RESET 0x00000001
1004#define BGE_SRSMODE_ENABLE 0x00000002
1005#define BGE_SRSMODE_ATTN 0x00000004
1006
1007/* Send BD Ring Selector Status register */
1008#define BGE_SRSSTAT_ERROR 0x00000004
1009
1010/* Send BD Ring Selector HW Diagnostics register */
1011#define BGE_SRSHWDIAG_STATE 0x0000000F
1012#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0
1013#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00
1014#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000
1015
1016/*
1017 * Send BD Initiator Selector Control registers
1018 */
1019#define BGE_SBDI_MODE 0x1800
1020#define BGE_SBDI_STATUS 0x1804
1021#define BGE_SBDI_LOC_NIC_PROD0 0x1808
1022#define BGE_SBDI_LOC_NIC_PROD1 0x180C
1023#define BGE_SBDI_LOC_NIC_PROD2 0x1810
1024#define BGE_SBDI_LOC_NIC_PROD3 0x1814
1025#define BGE_SBDI_LOC_NIC_PROD4 0x1818
1026#define BGE_SBDI_LOC_NIC_PROD5 0x181C
1027#define BGE_SBDI_LOC_NIC_PROD6 0x1820
1028#define BGE_SBDI_LOC_NIC_PROD7 0x1824
1029#define BGE_SBDI_LOC_NIC_PROD8 0x1828
1030#define BGE_SBDI_LOC_NIC_PROD9 0x182C
1031#define BGE_SBDI_LOC_NIC_PROD10 0x1830
1032#define BGE_SBDI_LOC_NIC_PROD11 0x1834
1033#define BGE_SBDI_LOC_NIC_PROD12 0x1838
1034#define BGE_SBDI_LOC_NIC_PROD13 0x183C
1035#define BGE_SBDI_LOC_NIC_PROD14 0x1840
1036#define BGE_SBDI_LOC_NIC_PROD15 0x1844
1037
1038/* Send BD Initiator Mode register */
1039#define BGE_SBDIMODE_RESET 0x00000001
1040#define BGE_SBDIMODE_ENABLE 0x00000002
1041#define BGE_SBDIMODE_ATTN 0x00000004
1042
1043/* Send BD Initiator Status register */
1044#define BGE_SBDISTAT_ERROR 0x00000004
1045
1046/*
1047 * Send BD Completion Control registers
1048 */
1049#define BGE_SBDC_MODE 0x1C00
1050#define BGE_SBDC_STATUS 0x1C04
1051
1052/* Send BD Completion Control Mode register */
1053#define BGE_SBDCMODE_RESET 0x00000001
1054#define BGE_SBDCMODE_ENABLE 0x00000002
1055#define BGE_SBDCMODE_ATTN 0x00000004
1056
1057/* Send BD Completion Control Status register */
1058#define BGE_SBDCSTAT_ATTN 0x00000004
1059
1060/*
1061 * Receive List Placement Control registers
1062 */
1063#define BGE_RXLP_MODE 0x2000
1064#define BGE_RXLP_STATUS 0x2004
1065#define BGE_RXLP_SEL_LIST_LOCK 0x2008
1066#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C
1067#define BGE_RXLP_CFG 0x2010
1068#define BGE_RXLP_STATS_CTL 0x2014
1069#define BGE_RXLP_STATS_ENABLE_MASK 0x2018
1070#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C
1071#define BGE_RXLP_HEAD0 0x2100
1072#define BGE_RXLP_TAIL0 0x2104
1073#define BGE_RXLP_COUNT0 0x2108
1074#define BGE_RXLP_HEAD1 0x2110
1075#define BGE_RXLP_TAIL1 0x2114
1076#define BGE_RXLP_COUNT1 0x2118
1077#define BGE_RXLP_HEAD2 0x2120
1078#define BGE_RXLP_TAIL2 0x2124
1079#define BGE_RXLP_COUNT2 0x2128
1080#define BGE_RXLP_HEAD3 0x2130
1081#define BGE_RXLP_TAIL3 0x2134
1082#define BGE_RXLP_COUNT3 0x2138
1083#define BGE_RXLP_HEAD4 0x2140
1084#define BGE_RXLP_TAIL4 0x2144
1085#define BGE_RXLP_COUNT4 0x2148
1086#define BGE_RXLP_HEAD5 0x2150
1087#define BGE_RXLP_TAIL5 0x2154
1088#define BGE_RXLP_COUNT5 0x2158
1089#define BGE_RXLP_HEAD6 0x2160
1090#define BGE_RXLP_TAIL6 0x2164
1091#define BGE_RXLP_COUNT6 0x2168
1092#define BGE_RXLP_HEAD7 0x2170
1093#define BGE_RXLP_TAIL7 0x2174
1094#define BGE_RXLP_COUNT7 0x2178
1095#define BGE_RXLP_HEAD8 0x2180
1096#define BGE_RXLP_TAIL8 0x2184
1097#define BGE_RXLP_COUNT8 0x2188
1098#define BGE_RXLP_HEAD9 0x2190
1099#define BGE_RXLP_TAIL9 0x2194
1100#define BGE_RXLP_COUNT9 0x2198
1101#define BGE_RXLP_HEAD10 0x21A0
1102#define BGE_RXLP_TAIL10 0x21A4
1103#define BGE_RXLP_COUNT10 0x21A8
1104#define BGE_RXLP_HEAD11 0x21B0
1105#define BGE_RXLP_TAIL11 0x21B4
1106#define BGE_RXLP_COUNT11 0x21B8
1107#define BGE_RXLP_HEAD12 0x21C0
1108#define BGE_RXLP_TAIL12 0x21C4
1109#define BGE_RXLP_COUNT12 0x21C8
1110#define BGE_RXLP_HEAD13 0x21D0
1111#define BGE_RXLP_TAIL13 0x21D4
1112#define BGE_RXLP_COUNT13 0x21D8
1113#define BGE_RXLP_HEAD14 0x21E0
1114#define BGE_RXLP_TAIL14 0x21E4
1115#define BGE_RXLP_COUNT14 0x21E8
1116#define BGE_RXLP_HEAD15 0x21F0
1117#define BGE_RXLP_TAIL15 0x21F4
1118#define BGE_RXLP_COUNT15 0x21F8
1119#define BGE_RXLP_LOCSTAT_COS0 0x2200
1120#define BGE_RXLP_LOCSTAT_COS1 0x2204
1121#define BGE_RXLP_LOCSTAT_COS2 0x2208
1122#define BGE_RXLP_LOCSTAT_COS3 0x220C
1123#define BGE_RXLP_LOCSTAT_COS4 0x2210
1124#define BGE_RXLP_LOCSTAT_COS5 0x2214
1125#define BGE_RXLP_LOCSTAT_COS6 0x2218
1126#define BGE_RXLP_LOCSTAT_COS7 0x221C
1127#define BGE_RXLP_LOCSTAT_COS8 0x2220
1128#define BGE_RXLP_LOCSTAT_COS9 0x2224
1129#define BGE_RXLP_LOCSTAT_COS10 0x2228
1130#define BGE_RXLP_LOCSTAT_COS11 0x222C
1131#define BGE_RXLP_LOCSTAT_COS12 0x2230
1132#define BGE_RXLP_LOCSTAT_COS13 0x2234
1133#define BGE_RXLP_LOCSTAT_COS14 0x2238
1134#define BGE_RXLP_LOCSTAT_COS15 0x223C
1135#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240
1136#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244
1137#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248
1138#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C
1139#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250
1140#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254
1141#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258
1142
1143
1144/* Receive List Placement mode register */
1145#define BGE_RXLPMODE_RESET 0x00000001
1146#define BGE_RXLPMODE_ENABLE 0x00000002
1147#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004
1148#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008
1149#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010
1150
1151/* Receive List Placement Status register */
1152#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004
1153#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008
1154#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010
1155
1156/*
1157 * Receive Data and Receive BD Initiator Control Registers
1158 */
1159#define BGE_RDBDI_MODE 0x2400
1160#define BGE_RDBDI_STATUS 0x2404
1161#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440
1162#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444
1163#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448
1164#define BGE_RX_JUMBO_RCB_NICADDR 0x244C
1165#define BGE_RX_STD_RCB_HADDR_HI 0x2450
1166#define BGE_RX_STD_RCB_HADDR_LO 0x2454
1167#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458
1168#define BGE_RX_STD_RCB_NICADDR 0x245C
1169#define BGE_RX_MINI_RCB_HADDR_HI 0x2460
1170#define BGE_RX_MINI_RCB_HADDR_LO 0x2464
1171#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468
1172#define BGE_RX_MINI_RCB_NICADDR 0x246C
1173#define BGE_RDBDI_JUMBO_RX_CONS 0x2470
1174#define BGE_RDBDI_STD_RX_CONS 0x2474
1175#define BGE_RDBDI_MINI_RX_CONS 0x2478
1176#define BGE_RDBDI_RETURN_PROD0 0x2480
1177#define BGE_RDBDI_RETURN_PROD1 0x2484
1178#define BGE_RDBDI_RETURN_PROD2 0x2488
1179#define BGE_RDBDI_RETURN_PROD3 0x248C
1180#define BGE_RDBDI_RETURN_PROD4 0x2490
1181#define BGE_RDBDI_RETURN_PROD5 0x2494
1182#define BGE_RDBDI_RETURN_PROD6 0x2498
1183#define BGE_RDBDI_RETURN_PROD7 0x249C
1184#define BGE_RDBDI_RETURN_PROD8 0x24A0
1185#define BGE_RDBDI_RETURN_PROD9 0x24A4
1186#define BGE_RDBDI_RETURN_PROD10 0x24A8
1187#define BGE_RDBDI_RETURN_PROD11 0x24AC
1188#define BGE_RDBDI_RETURN_PROD12 0x24B0
1189#define BGE_RDBDI_RETURN_PROD13 0x24B4
1190#define BGE_RDBDI_RETURN_PROD14 0x24B8
1191#define BGE_RDBDI_RETURN_PROD15 0x24BC
1192#define BGE_RDBDI_HWDIAG 0x24C0
1193
1194
1195/* Receive Data and Receive BD Initiator Mode register */
1196#define BGE_RDBDIMODE_RESET 0x00000001
1197#define BGE_RDBDIMODE_ENABLE 0x00000002
1198#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004
1199#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008
1200#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010
1201
1202/* Receive Data and Receive BD Initiator Status register */
1203#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004
1204#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008
1205#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010
1206
1207
1208/*
1209 * Receive Data Completion Control registers
1210 */
1211#define BGE_RDC_MODE 0x2800
1212
1213/* Receive Data Completion Mode register */
1214#define BGE_RDCMODE_RESET 0x00000001
1215#define BGE_RDCMODE_ENABLE 0x00000002
1216#define BGE_RDCMODE_ATTN 0x00000004
1217
1218/*
1219 * Receive BD Initiator Control registers
1220 */
1221#define BGE_RBDI_MODE 0x2C00
1222#define BGE_RBDI_STATUS 0x2C04
1223#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08
1224#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C
1225#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10
1226#define BGE_RBDI_MINI_REPL_THRESH 0x2C14
1227#define BGE_RBDI_STD_REPL_THRESH 0x2C18
1228#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C
1229
1230#define BGE_STD_REPLENISH_LWM 0x2D00
1231#define BGE_JMB_REPLENISH_LWM 0x2D04
1232
1233/* Receive BD Initiator Mode register */
1234#define BGE_RBDIMODE_RESET 0x00000001
1235#define BGE_RBDIMODE_ENABLE 0x00000002
1236#define BGE_RBDIMODE_ATTN 0x00000004
1237
1238/* Receive BD Initiator Status register */
1239#define BGE_RBDISTAT_ATTN 0x00000004
1240
1241/*
1242 * Receive BD Completion Control registers
1243 */
1244#define BGE_RBDC_MODE 0x3000
1245#define BGE_RBDC_STATUS 0x3004
1246#define BGE_RBDC_JUMBO_BD_PROD 0x3008
1247#define BGE_RBDC_STD_BD_PROD 0x300C
1248#define BGE_RBDC_MINI_BD_PROD 0x3010
1249
1250/* Receive BD completion mode register */
1251#define BGE_RBDCMODE_RESET 0x00000001
1252#define BGE_RBDCMODE_ENABLE 0x00000002
1253#define BGE_RBDCMODE_ATTN 0x00000004
1254
1255/* Receive BD completion status register */
1256#define BGE_RBDCSTAT_ERROR 0x00000004
1257
1258/*
1259 * Receive List Selector Control registers
1260 */
1261#define BGE_RXLS_MODE 0x3400
1262#define BGE_RXLS_STATUS 0x3404
1263
1264/* Receive List Selector Mode register */
1265#define BGE_RXLSMODE_RESET 0x00000001
1266#define BGE_RXLSMODE_ENABLE 0x00000002
1267#define BGE_RXLSMODE_ATTN 0x00000004
1268
1269/* Receive List Selector Status register */
1270#define BGE_RXLSSTAT_ERROR 0x00000004
1271
1272#define BGE_CPMU_CTRL 0x3600
1273#define BGE_CPMU_LSPD_10MB_CLK 0x3604
1274#define BGE_CPMU_LSPD_1000MB_CLK 0x360C
1275#define BGE_CPMU_LNK_AWARE_PWRMD 0x3610
1276#define BGE_CPMU_HST_ACC 0x361C
|
| 1277#define BGE_CPMU_CLCK_ORIDE 0x3624
|
1280#define BGE_CPMU_CLCK_STAT 0x3630
1281#define BGE_CPMU_MUTEX_REQ 0x365C
1282#define BGE_CPMU_MUTEX_GNT 0x3660
1283#define BGE_CPMU_PHY_STRAP 0x3664
1284
1285/* Central Power Management Unit (CPMU) register */
1286#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1287#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1288#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1289#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1290
1291/* Link Speed 10MB/No Link Power Mode Clock Policy register */
1292#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
1293#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1294
1295/* Link Speed 1000MB Power Mode Clock Policy register */
1296#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1297#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1298#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
1299
1300/* Link Aware Power Mode Clock Policy register */
1301#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
1302#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1303
1304#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
1305#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
1306
| 1278#define BGE_CPMU_CLCK_STAT 0x3630
1279#define BGE_CPMU_MUTEX_REQ 0x365C
1280#define BGE_CPMU_MUTEX_GNT 0x3660
1281#define BGE_CPMU_PHY_STRAP 0x3664
1282
1283/* Central Power Management Unit (CPMU) register */
1284#define BGE_CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1285#define BGE_CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1286#define BGE_CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1287#define BGE_CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1288
1289/* Link Speed 10MB/No Link Power Mode Clock Policy register */
1290#define BGE_CPMU_LSPD_10MB_MACCLK_MASK 0x001F0000
1291#define BGE_CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1292
1293/* Link Speed 1000MB Power Mode Clock Policy register */
1294#define BGE_CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1295#define BGE_CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1296#define BGE_CPMU_LSPD_1000MB_MACCLK_MASK 0x001F0000
1297
1298/* Link Aware Power Mode Clock Policy register */
1299#define BGE_CPMU_LNK_AWARE_MACCLK_MASK 0x001F0000
1300#define BGE_CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1301
1302#define BGE_CPMU_HST_ACC_MACCLK_MASK 0x001F0000
1303#define BGE_CPMU_HST_ACC_MACCLK_6_25 0x00130000
1304
|
| 1305/* Clock Speed Override Policy register */
1306#define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1307
|
1307/* CPMU Clock Status register */
1308#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
1309#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1310#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1311#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1312
1313/* CPMU Mutex Request register */
1314#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
1315#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
1316
1317/* CPMU GPHY Strap register */
1318#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1319
1320/*
1321 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1322 */
1323#define BGE_MBCF_MODE 0x3800
1324#define BGE_MBCF_STATUS 0x3804
1325
1326/* Mbuf Cluster Free mode register */
1327#define BGE_MBCFMODE_RESET 0x00000001
1328#define BGE_MBCFMODE_ENABLE 0x00000002
1329#define BGE_MBCFMODE_ATTN 0x00000004
1330
1331/* Mbuf Cluster Free status register */
1332#define BGE_MBCFSTAT_ERROR 0x00000004
1333
1334/*
1335 * Host Coalescing Control registers
1336 */
1337#define BGE_HCC_MODE 0x3C00
1338#define BGE_HCC_STATUS 0x3C04
1339#define BGE_HCC_RX_COAL_TICKS 0x3C08
1340#define BGE_HCC_TX_COAL_TICKS 0x3C0C
1341#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1342#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1343#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1344#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1345#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1346#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1347#define BGE_HCC_STATS_TICKS 0x3C28
1348#define BGE_HCC_STATS_ADDR_HI 0x3C30
1349#define BGE_HCC_STATS_ADDR_LO 0x3C34
1350#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1351#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1352#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1353#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1354#define BGE_FLOW_ATTN 0x3C48
1355#define BGE_HCC_JUMBO_BD_CONS 0x3C50
1356#define BGE_HCC_STD_BD_CONS 0x3C54
1357#define BGE_HCC_MINI_BD_CONS 0x3C58
1358#define BGE_HCC_RX_RETURN_PROD0 0x3C80
1359#define BGE_HCC_RX_RETURN_PROD1 0x3C84
1360#define BGE_HCC_RX_RETURN_PROD2 0x3C88
1361#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1362#define BGE_HCC_RX_RETURN_PROD4 0x3C90
1363#define BGE_HCC_RX_RETURN_PROD5 0x3C94
1364#define BGE_HCC_RX_RETURN_PROD6 0x3C98
1365#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1366#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1367#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1368#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1369#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1370#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1371#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1372#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1373#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1374#define BGE_HCC_TX_BD_CONS0 0x3CC0
1375#define BGE_HCC_TX_BD_CONS1 0x3CC4
1376#define BGE_HCC_TX_BD_CONS2 0x3CC8
1377#define BGE_HCC_TX_BD_CONS3 0x3CCC
1378#define BGE_HCC_TX_BD_CONS4 0x3CD0
1379#define BGE_HCC_TX_BD_CONS5 0x3CD4
1380#define BGE_HCC_TX_BD_CONS6 0x3CD8
1381#define BGE_HCC_TX_BD_CONS7 0x3CDC
1382#define BGE_HCC_TX_BD_CONS8 0x3CE0
1383#define BGE_HCC_TX_BD_CONS9 0x3CE4
1384#define BGE_HCC_TX_BD_CONS10 0x3CE8
1385#define BGE_HCC_TX_BD_CONS11 0x3CEC
1386#define BGE_HCC_TX_BD_CONS12 0x3CF0
1387#define BGE_HCC_TX_BD_CONS13 0x3CF4
1388#define BGE_HCC_TX_BD_CONS14 0x3CF8
1389#define BGE_HCC_TX_BD_CONS15 0x3CFC
1390
1391
1392/* Host coalescing mode register */
1393#define BGE_HCCMODE_RESET 0x00000001
1394#define BGE_HCCMODE_ENABLE 0x00000002
1395#define BGE_HCCMODE_ATTN 0x00000004
1396#define BGE_HCCMODE_COAL_NOW 0x00000008
1397#define BGE_HCCMODE_MSI_BITS 0x00000070
1398#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1399
1400#define BGE_STATBLKSZ_FULL 0x00000000
1401#define BGE_STATBLKSZ_64BYTE 0x00000080
1402#define BGE_STATBLKSZ_32BYTE 0x00000100
1403
1404/* Host coalescing status register */
1405#define BGE_HCCSTAT_ERROR 0x00000004
1406
1407/* Flow attention register */
1408#define BGE_FLOWATTN_MB_LOWAT 0x00000040
1409#define BGE_FLOWATTN_MEMARB 0x00000080
1410#define BGE_FLOWATTN_HOSTCOAL 0x00008000
1411#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1412#define BGE_FLOWATTN_RCB_INVAL 0x00020000
1413#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1414#define BGE_FLOWATTN_RDBDI 0x00080000
1415#define BGE_FLOWATTN_RXLS 0x00100000
1416#define BGE_FLOWATTN_RXLP 0x00200000
1417#define BGE_FLOWATTN_RBDC 0x00400000
1418#define BGE_FLOWATTN_RBDI 0x00800000
1419#define BGE_FLOWATTN_SDC 0x08000000
1420#define BGE_FLOWATTN_SDI 0x10000000
1421#define BGE_FLOWATTN_SRS 0x20000000
1422#define BGE_FLOWATTN_SBDC 0x40000000
1423#define BGE_FLOWATTN_SBDI 0x80000000
1424
1425/*
1426 * Memory arbiter registers
1427 */
1428#define BGE_MARB_MODE 0x4000
1429#define BGE_MARB_STATUS 0x4004
1430#define BGE_MARB_TRAPADDR_HI 0x4008
1431#define BGE_MARB_TRAPADDR_LO 0x400C
1432
1433/* Memory arbiter mode register */
1434#define BGE_MARBMODE_RESET 0x00000001
1435#define BGE_MARBMODE_ENABLE 0x00000002
1436#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1437#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1438#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1439#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1440#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1441#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1442#define BGE_MARBMODE_PCI_TRAP 0x00000100
1443#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1444#define BGE_MARBMODE_RXQ_TRAP 0x00000400
1445#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1446#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1447#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1448#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1449#define BGE_MARBMODE_MBUF_TRAP 0x00008000
1450#define BGE_MARBMODE_TXDI_TRAP 0x00010000
1451#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1452#define BGE_MARBMODE_TXBD_TRAP 0x00040000
1453#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1454#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1455#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1456#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1457#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1458#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1459#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1460
1461/* Memory arbiter status register */
1462#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1463#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1464#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1465#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1466#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1467#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1468#define BGE_MARBSTAT_PCI_TRAP 0x00000100
1469#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1470#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1471#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1472#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1473#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1474#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1475#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1476#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1477#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1478#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1479#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1480#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1481#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1482#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1483#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1484#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1485#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1486
1487/*
1488 * Buffer manager control registers
1489 */
1490#define BGE_BMAN_MODE 0x4400
1491#define BGE_BMAN_STATUS 0x4404
1492#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1493#define BGE_BMAN_MBUFPOOL_LEN 0x440C
1494#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1495#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1496#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1497#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1498#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1499#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1500#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1501#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1502#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1503#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1504#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1505#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1506#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1507#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1508#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1509#define BGE_BMAN_HWDIAG_1 0x444C
1510#define BGE_BMAN_HWDIAG_2 0x4450
1511#define BGE_BMAN_HWDIAG_3 0x4454
1512
1513/* Buffer manager mode register */
1514#define BGE_BMANMODE_RESET 0x00000001
1515#define BGE_BMANMODE_ENABLE 0x00000002
1516#define BGE_BMANMODE_ATTN 0x00000004
1517#define BGE_BMANMODE_TESTMODE 0x00000008
1518#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1519#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000
1520
1521/* Buffer manager status register */
1522#define BGE_BMANSTAT_ERRO 0x00000004
1523#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1524
1525
1526/*
1527 * Read DMA Control registers
1528 */
1529#define BGE_RDMA_MODE 0x4800
1530#define BGE_RDMA_STATUS 0x4804
1531#define BGE_RDMA_RSRVCTRL 0x4900
1532#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910
1533
1534/* Read DMA mode register */
1535#define BGE_RDMAMODE_RESET 0x00000001
1536#define BGE_RDMAMODE_ENABLE 0x00000002
1537#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1538#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1539#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1540#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1541#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1542#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1543#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1544#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1545#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1546#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1547#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1548#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1549#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1550#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1551#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000
1552#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000
1553#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000
| 1308/* CPMU Clock Status register */
1309#define BGE_CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001F0000
1310#define BGE_CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1311#define BGE_CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1312#define BGE_CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1313
1314/* CPMU Mutex Request register */
1315#define BGE_CPMU_MUTEX_REQ_DRIVER 0x00001000
1316#define BGE_CPMU_MUTEX_GNT_DRIVER 0x00001000
1317
1318/* CPMU GPHY Strap register */
1319#define BGE_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1320
1321/*
1322 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs)
1323 */
1324#define BGE_MBCF_MODE 0x3800
1325#define BGE_MBCF_STATUS 0x3804
1326
1327/* Mbuf Cluster Free mode register */
1328#define BGE_MBCFMODE_RESET 0x00000001
1329#define BGE_MBCFMODE_ENABLE 0x00000002
1330#define BGE_MBCFMODE_ATTN 0x00000004
1331
1332/* Mbuf Cluster Free status register */
1333#define BGE_MBCFSTAT_ERROR 0x00000004
1334
1335/*
1336 * Host Coalescing Control registers
1337 */
1338#define BGE_HCC_MODE 0x3C00
1339#define BGE_HCC_STATUS 0x3C04
1340#define BGE_HCC_RX_COAL_TICKS 0x3C08
1341#define BGE_HCC_TX_COAL_TICKS 0x3C0C
1342#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10
1343#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14
1344#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 /* ticks during interrupt */
1345#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C /* ticks during interrupt */
1346#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 /* BDs during interrupt */
1347#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 /* BDs during interrupt */
1348#define BGE_HCC_STATS_TICKS 0x3C28
1349#define BGE_HCC_STATS_ADDR_HI 0x3C30
1350#define BGE_HCC_STATS_ADDR_LO 0x3C34
1351#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38
1352#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C
1353#define BGE_HCC_STATS_BASEADDR 0x3C40 /* address in NIC memory */
1354#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 /* address in NIC memory */
1355#define BGE_FLOW_ATTN 0x3C48
1356#define BGE_HCC_JUMBO_BD_CONS 0x3C50
1357#define BGE_HCC_STD_BD_CONS 0x3C54
1358#define BGE_HCC_MINI_BD_CONS 0x3C58
1359#define BGE_HCC_RX_RETURN_PROD0 0x3C80
1360#define BGE_HCC_RX_RETURN_PROD1 0x3C84
1361#define BGE_HCC_RX_RETURN_PROD2 0x3C88
1362#define BGE_HCC_RX_RETURN_PROD3 0x3C8C
1363#define BGE_HCC_RX_RETURN_PROD4 0x3C90
1364#define BGE_HCC_RX_RETURN_PROD5 0x3C94
1365#define BGE_HCC_RX_RETURN_PROD6 0x3C98
1366#define BGE_HCC_RX_RETURN_PROD7 0x3C9C
1367#define BGE_HCC_RX_RETURN_PROD8 0x3CA0
1368#define BGE_HCC_RX_RETURN_PROD9 0x3CA4
1369#define BGE_HCC_RX_RETURN_PROD10 0x3CA8
1370#define BGE_HCC_RX_RETURN_PROD11 0x3CAC
1371#define BGE_HCC_RX_RETURN_PROD12 0x3CB0
1372#define BGE_HCC_RX_RETURN_PROD13 0x3CB4
1373#define BGE_HCC_RX_RETURN_PROD14 0x3CB8
1374#define BGE_HCC_RX_RETURN_PROD15 0x3CBC
1375#define BGE_HCC_TX_BD_CONS0 0x3CC0
1376#define BGE_HCC_TX_BD_CONS1 0x3CC4
1377#define BGE_HCC_TX_BD_CONS2 0x3CC8
1378#define BGE_HCC_TX_BD_CONS3 0x3CCC
1379#define BGE_HCC_TX_BD_CONS4 0x3CD0
1380#define BGE_HCC_TX_BD_CONS5 0x3CD4
1381#define BGE_HCC_TX_BD_CONS6 0x3CD8
1382#define BGE_HCC_TX_BD_CONS7 0x3CDC
1383#define BGE_HCC_TX_BD_CONS8 0x3CE0
1384#define BGE_HCC_TX_BD_CONS9 0x3CE4
1385#define BGE_HCC_TX_BD_CONS10 0x3CE8
1386#define BGE_HCC_TX_BD_CONS11 0x3CEC
1387#define BGE_HCC_TX_BD_CONS12 0x3CF0
1388#define BGE_HCC_TX_BD_CONS13 0x3CF4
1389#define BGE_HCC_TX_BD_CONS14 0x3CF8
1390#define BGE_HCC_TX_BD_CONS15 0x3CFC
1391
1392
1393/* Host coalescing mode register */
1394#define BGE_HCCMODE_RESET 0x00000001
1395#define BGE_HCCMODE_ENABLE 0x00000002
1396#define BGE_HCCMODE_ATTN 0x00000004
1397#define BGE_HCCMODE_COAL_NOW 0x00000008
1398#define BGE_HCCMODE_MSI_BITS 0x00000070
1399#define BGE_HCCMODE_STATBLK_SIZE 0x00000180
1400
1401#define BGE_STATBLKSZ_FULL 0x00000000
1402#define BGE_STATBLKSZ_64BYTE 0x00000080
1403#define BGE_STATBLKSZ_32BYTE 0x00000100
1404
1405/* Host coalescing status register */
1406#define BGE_HCCSTAT_ERROR 0x00000004
1407
1408/* Flow attention register */
1409#define BGE_FLOWATTN_MB_LOWAT 0x00000040
1410#define BGE_FLOWATTN_MEMARB 0x00000080
1411#define BGE_FLOWATTN_HOSTCOAL 0x00008000
1412#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000
1413#define BGE_FLOWATTN_RCB_INVAL 0x00020000
1414#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000
1415#define BGE_FLOWATTN_RDBDI 0x00080000
1416#define BGE_FLOWATTN_RXLS 0x00100000
1417#define BGE_FLOWATTN_RXLP 0x00200000
1418#define BGE_FLOWATTN_RBDC 0x00400000
1419#define BGE_FLOWATTN_RBDI 0x00800000
1420#define BGE_FLOWATTN_SDC 0x08000000
1421#define BGE_FLOWATTN_SDI 0x10000000
1422#define BGE_FLOWATTN_SRS 0x20000000
1423#define BGE_FLOWATTN_SBDC 0x40000000
1424#define BGE_FLOWATTN_SBDI 0x80000000
1425
1426/*
1427 * Memory arbiter registers
1428 */
1429#define BGE_MARB_MODE 0x4000
1430#define BGE_MARB_STATUS 0x4004
1431#define BGE_MARB_TRAPADDR_HI 0x4008
1432#define BGE_MARB_TRAPADDR_LO 0x400C
1433
1434/* Memory arbiter mode register */
1435#define BGE_MARBMODE_RESET 0x00000001
1436#define BGE_MARBMODE_ENABLE 0x00000002
1437#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004
1438#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008
1439#define BGE_MARBMODE_DMAW1_TRAP 0x00000010
1440#define BGE_MARBMODE_DMAR1_TRAP 0x00000020
1441#define BGE_MARBMODE_RXRISC_TRAP 0x00000040
1442#define BGE_MARBMODE_TXRISC_TRAP 0x00000080
1443#define BGE_MARBMODE_PCI_TRAP 0x00000100
1444#define BGE_MARBMODE_DMAR2_TRAP 0x00000200
1445#define BGE_MARBMODE_RXQ_TRAP 0x00000400
1446#define BGE_MARBMODE_RXDI1_TRAP 0x00000800
1447#define BGE_MARBMODE_RXDI2_TRAP 0x00001000
1448#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000
1449#define BGE_MARBMODE_HCOAL_TRAP 0x00004000
1450#define BGE_MARBMODE_MBUF_TRAP 0x00008000
1451#define BGE_MARBMODE_TXDI_TRAP 0x00010000
1452#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000
1453#define BGE_MARBMODE_TXBD_TRAP 0x00040000
1454#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000
1455#define BGE_MARBMODE_DMAW2_TRAP 0x00100000
1456#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000
1457#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000
1458#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000
1459#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000
1460#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000
1461
1462/* Memory arbiter status register */
1463#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004
1464#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008
1465#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010
1466#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020
1467#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040
1468#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080
1469#define BGE_MARBSTAT_PCI_TRAP 0x00000100
1470#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200
1471#define BGE_MARBSTAT_RXQ_TRAP 0x00000400
1472#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800
1473#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000
1474#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000
1475#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000
1476#define BGE_MARBSTAT_MBUF_TRAP 0x00008000
1477#define BGE_MARBSTAT_TXDI_TRAP 0x00010000
1478#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000
1479#define BGE_MARBSTAT_TXBD_TRAP 0x00040000
1480#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000
1481#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000
1482#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000
1483#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000
1484#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000
1485#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000
1486#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000
1487
1488/*
1489 * Buffer manager control registers
1490 */
1491#define BGE_BMAN_MODE 0x4400
1492#define BGE_BMAN_STATUS 0x4404
1493#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408
1494#define BGE_BMAN_MBUFPOOL_LEN 0x440C
1495#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410
1496#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414
1497#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418
1498#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C
1499#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420
1500#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424
1501#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428
1502#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C
1503#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430
1504#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434
1505#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438
1506#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C
1507#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440
1508#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444
1509#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448
1510#define BGE_BMAN_HWDIAG_1 0x444C
1511#define BGE_BMAN_HWDIAG_2 0x4450
1512#define BGE_BMAN_HWDIAG_3 0x4454
1513
1514/* Buffer manager mode register */
1515#define BGE_BMANMODE_RESET 0x00000001
1516#define BGE_BMANMODE_ENABLE 0x00000002
1517#define BGE_BMANMODE_ATTN 0x00000004
1518#define BGE_BMANMODE_TESTMODE 0x00000008
1519#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010
1520#define BGE_BMANMODE_NO_TX_UNDERRUN 0x80000000
1521
1522/* Buffer manager status register */
1523#define BGE_BMANSTAT_ERRO 0x00000004
1524#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010
1525
1526
1527/*
1528 * Read DMA Control registers
1529 */
1530#define BGE_RDMA_MODE 0x4800
1531#define BGE_RDMA_STATUS 0x4804
1532#define BGE_RDMA_RSRVCTRL 0x4900
1533#define BGE_RDMA_LSO_CRPTEN_CTRL 0x4910
1534
1535/* Read DMA mode register */
1536#define BGE_RDMAMODE_RESET 0x00000001
1537#define BGE_RDMAMODE_ENABLE 0x00000002
1538#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1539#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1540#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010
1541#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1542#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1543#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1544#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1545#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200
1546#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC
1547#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800
1548#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000
1549#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000
1550#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000
1551#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000
1552#define BGE_RDMAMODE_MULT_DMA_RD_DIS 0x01000000
1553#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000
1554#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000
|
| 1555#define BGE_RDMAMODE_H2BNC_VLAN_DET 0x20000000
|
1554
1555/* Read DMA status register */
1556#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1557#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1558#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1559#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1560#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1561#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1562#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1563#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1564
1565/* Read DMA Reserved Control register */
1566#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1567#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00
1568#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000
1569#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1570#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0
1571#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000
1572#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000
1573
1574#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1575#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000
1576
1577/*
1578 * Write DMA control registers
1579 */
1580#define BGE_WDMA_MODE 0x4C00
1581#define BGE_WDMA_STATUS 0x4C04
1582
1583/* Write DMA mode register */
1584#define BGE_WDMAMODE_RESET 0x00000001
1585#define BGE_WDMAMODE_ENABLE 0x00000002
1586#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1587#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1588#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1589#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1590#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1591#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1592#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1593#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1594#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1595#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1596#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000
1597
1598/* Write DMA status register */
1599#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1600#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1601#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1602#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1603#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1604#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1605#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1606#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1607
1608
1609/*
1610 * RX CPU registers
1611 */
1612#define BGE_RXCPU_MODE 0x5000
1613#define BGE_RXCPU_STATUS 0x5004
1614#define BGE_RXCPU_PC 0x501C
1615
1616/* RX CPU mode register */
1617#define BGE_RXCPUMODE_RESET 0x00000001
1618#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1619#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1620#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1621#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1622#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1623#define BGE_RXCPUMODE_ROMFAIL 0x00000040
1624#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1625#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1626#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1627#define BGE_RXCPUMODE_HALTCPU 0x00000400
1628#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1629#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1630#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1631
1632/* RX CPU status register */
1633#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1634#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1635#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1636#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1637#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1638#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1639#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1640#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1641#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1642#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1643#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1644#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1645#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1646#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1647#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1648#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1649#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1650
1651/*
1652 * V? CPU registers
1653 */
1654#define BGE_VCPU_STATUS 0x5100
1655#define BGE_VCPU_EXT_CTRL 0x6890
1656
1657#define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1658#define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1659
1660#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1661#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1662
1663/*
1664 * TX CPU registers
1665 */
1666#define BGE_TXCPU_MODE 0x5400
1667#define BGE_TXCPU_STATUS 0x5404
1668#define BGE_TXCPU_PC 0x541C
1669
1670/* TX CPU mode register */
1671#define BGE_TXCPUMODE_RESET 0x00000001
1672#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1673#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1674#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1675#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1676#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1677#define BGE_TXCPUMODE_ROMFAIL 0x00000040
1678#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1679#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1680#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1681#define BGE_TXCPUMODE_HALTCPU 0x00000400
1682#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1683#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1684
1685/* TX CPU status register */
1686#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1687#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1688#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1689#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1690#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1691#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1692#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1693#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1694#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1695#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1696#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1697#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1698#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1699#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1700#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1701#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1702#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1703
1704
1705/*
1706 * Low priority mailbox registers
1707 */
1708#define BGE_LPMBX_IRQ0_HI 0x5800
1709#define BGE_LPMBX_IRQ0_LO 0x5804
1710#define BGE_LPMBX_IRQ1_HI 0x5808
1711#define BGE_LPMBX_IRQ1_LO 0x580C
1712#define BGE_LPMBX_IRQ2_HI 0x5810
1713#define BGE_LPMBX_IRQ2_LO 0x5814
1714#define BGE_LPMBX_IRQ3_HI 0x5818
1715#define BGE_LPMBX_IRQ3_LO 0x581C
1716#define BGE_LPMBX_GEN0_HI 0x5820
1717#define BGE_LPMBX_GEN0_LO 0x5824
1718#define BGE_LPMBX_GEN1_HI 0x5828
1719#define BGE_LPMBX_GEN1_LO 0x582C
1720#define BGE_LPMBX_GEN2_HI 0x5830
1721#define BGE_LPMBX_GEN2_LO 0x5834
1722#define BGE_LPMBX_GEN3_HI 0x5828
1723#define BGE_LPMBX_GEN3_LO 0x582C
1724#define BGE_LPMBX_GEN4_HI 0x5840
1725#define BGE_LPMBX_GEN4_LO 0x5844
1726#define BGE_LPMBX_GEN5_HI 0x5848
1727#define BGE_LPMBX_GEN5_LO 0x584C
1728#define BGE_LPMBX_GEN6_HI 0x5850
1729#define BGE_LPMBX_GEN6_LO 0x5854
1730#define BGE_LPMBX_GEN7_HI 0x5858
1731#define BGE_LPMBX_GEN7_LO 0x585C
1732#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1733#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1734#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1735#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1736#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1737#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1738#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1739#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1740#define BGE_LPMBX_RX_CONS0_HI 0x5880
1741#define BGE_LPMBX_RX_CONS0_LO 0x5884
1742#define BGE_LPMBX_RX_CONS1_HI 0x5888
1743#define BGE_LPMBX_RX_CONS1_LO 0x588C
1744#define BGE_LPMBX_RX_CONS2_HI 0x5890
1745#define BGE_LPMBX_RX_CONS2_LO 0x5894
1746#define BGE_LPMBX_RX_CONS3_HI 0x5898
1747#define BGE_LPMBX_RX_CONS3_LO 0x589C
1748#define BGE_LPMBX_RX_CONS4_HI 0x58A0
1749#define BGE_LPMBX_RX_CONS4_LO 0x58A4
1750#define BGE_LPMBX_RX_CONS5_HI 0x58A8
1751#define BGE_LPMBX_RX_CONS5_LO 0x58AC
1752#define BGE_LPMBX_RX_CONS6_HI 0x58B0
1753#define BGE_LPMBX_RX_CONS6_LO 0x58B4
1754#define BGE_LPMBX_RX_CONS7_HI 0x58B8
1755#define BGE_LPMBX_RX_CONS7_LO 0x58BC
1756#define BGE_LPMBX_RX_CONS8_HI 0x58C0
1757#define BGE_LPMBX_RX_CONS8_LO 0x58C4
1758#define BGE_LPMBX_RX_CONS9_HI 0x58C8
1759#define BGE_LPMBX_RX_CONS9_LO 0x58CC
1760#define BGE_LPMBX_RX_CONS10_HI 0x58D0
1761#define BGE_LPMBX_RX_CONS10_LO 0x58D4
1762#define BGE_LPMBX_RX_CONS11_HI 0x58D8
1763#define BGE_LPMBX_RX_CONS11_LO 0x58DC
1764#define BGE_LPMBX_RX_CONS12_HI 0x58E0
1765#define BGE_LPMBX_RX_CONS12_LO 0x58E4
1766#define BGE_LPMBX_RX_CONS13_HI 0x58E8
1767#define BGE_LPMBX_RX_CONS13_LO 0x58EC
1768#define BGE_LPMBX_RX_CONS14_HI 0x58F0
1769#define BGE_LPMBX_RX_CONS14_LO 0x58F4
1770#define BGE_LPMBX_RX_CONS15_HI 0x58F8
1771#define BGE_LPMBX_RX_CONS15_LO 0x58FC
1772#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1773#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1774#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1775#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1776#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1777#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1778#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1779#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1780#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1781#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1782#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1783#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1784#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1785#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1786#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1787#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1788#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1789#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1790#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1791#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1792#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1793#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1794#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1795#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1796#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1797#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1798#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1799#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1800#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1801#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1802#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1803#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1804#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1805#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1806#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1807#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1808#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1809#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1810#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1811#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1812#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1813#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1814#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1815#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1816#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1817#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1818#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1819#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1820#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1821#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1822#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1823#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1824#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1825#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1826#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1827#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1828#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1829#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1830#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1831#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1832#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1833#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1834#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1835#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1836
1837/*
1838 * Flow throw Queue reset register
1839 */
1840#define BGE_FTQ_RESET 0x5C00
1841
1842#define BGE_FTQRESET_DMAREAD 0x00000002
1843#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1844#define BGE_FTQRESET_DMADONE 0x00000010
1845#define BGE_FTQRESET_SBDC 0x00000020
1846#define BGE_FTQRESET_SDI 0x00000040
1847#define BGE_FTQRESET_WDMA 0x00000080
1848#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1849#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1850#define BGE_FTQRESET_SDC 0x00000400
1851#define BGE_FTQRESET_HCC 0x00000800
1852#define BGE_FTQRESET_TXFIFO 0x00001000
1853#define BGE_FTQRESET_MBC 0x00002000
1854#define BGE_FTQRESET_RBDC 0x00004000
1855#define BGE_FTQRESET_RXLP 0x00008000
1856#define BGE_FTQRESET_RDBDI 0x00010000
1857#define BGE_FTQRESET_RDC 0x00020000
1858#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1859
1860/*
1861 * Message Signaled Interrupt registers
1862 */
1863#define BGE_MSI_MODE 0x6000
1864#define BGE_MSI_STATUS 0x6004
1865#define BGE_MSI_FIFOACCESS 0x6008
1866
1867/* MSI mode register */
1868#define BGE_MSIMODE_RESET 0x00000001
1869#define BGE_MSIMODE_ENABLE 0x00000002
1870#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020
1871#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080
1872
1873/* MSI status register */
1874#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1875#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1876#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1877#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1878#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1879
1880
1881/*
1882 * DMA Completion registers
1883 */
1884#define BGE_DMAC_MODE 0x6400
1885
1886/* DMA Completion mode register */
1887#define BGE_DMACMODE_RESET 0x00000001
1888#define BGE_DMACMODE_ENABLE 0x00000002
1889
1890
1891/*
1892 * General control registers.
1893 */
1894#define BGE_MODE_CTL 0x6800
1895#define BGE_MISC_CFG 0x6804
1896#define BGE_MISC_LOCAL_CTL 0x6808
1897#define BGE_RX_CPU_EVENT 0x6810
1898#define BGE_TX_CPU_EVENT 0x6820
1899#define BGE_EE_ADDR 0x6838
1900#define BGE_EE_DATA 0x683C
1901#define BGE_EE_CTL 0x6840
1902#define BGE_MDI_CTL 0x6844
1903#define BGE_EE_DELAY 0x6848
1904#define BGE_FASTBOOT_PC 0x6894
1905
1906#define BGE_RX_CPU_DRV_EVENT 0x00004000
1907
1908/*
1909 * NVRAM Control registers
1910 */
1911#define BGE_NVRAM_CMD 0x7000
1912#define BGE_NVRAM_STAT 0x7004
1913#define BGE_NVRAM_WRDATA 0x7008
1914#define BGE_NVRAM_ADDR 0x700c
1915#define BGE_NVRAM_RDDATA 0x7010
1916#define BGE_NVRAM_CFG1 0x7014
1917#define BGE_NVRAM_CFG2 0x7018
1918#define BGE_NVRAM_CFG3 0x701c
1919#define BGE_NVRAM_SWARB 0x7020
1920#define BGE_NVRAM_ACCESS 0x7024
1921#define BGE_NVRAM_WRITE1 0x7028
1922
1923#define BGE_NVRAMCMD_RESET 0x00000001
1924#define BGE_NVRAMCMD_DONE 0x00000008
1925#define BGE_NVRAMCMD_START 0x00000010
1926#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1927#define BGE_NVRAMCMD_ERASE 0x00000040
1928#define BGE_NVRAMCMD_FIRST 0x00000080
1929#define BGE_NVRAMCMD_LAST 0x00000100
1930
1931#define BGE_NVRAM_READCMD \
1932 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1933 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1934#define BGE_NVRAM_WRITECMD \
1935 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1936 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1937
1938#define BGE_NVRAMSWARB_SET0 0x00000001
1939#define BGE_NVRAMSWARB_SET1 0x00000002
1940#define BGE_NVRAMSWARB_SET2 0x00000003
1941#define BGE_NVRAMSWARB_SET3 0x00000004
1942#define BGE_NVRAMSWARB_CLR0 0x00000010
1943#define BGE_NVRAMSWARB_CLR1 0x00000020
1944#define BGE_NVRAMSWARB_CLR2 0x00000040
1945#define BGE_NVRAMSWARB_CLR3 0x00000080
1946#define BGE_NVRAMSWARB_GNT0 0x00000100
1947#define BGE_NVRAMSWARB_GNT1 0x00000200
1948#define BGE_NVRAMSWARB_GNT2 0x00000400
1949#define BGE_NVRAMSWARB_GNT3 0x00000800
1950#define BGE_NVRAMSWARB_REQ0 0x00001000
1951#define BGE_NVRAMSWARB_REQ1 0x00002000
1952#define BGE_NVRAMSWARB_REQ2 0x00004000
1953#define BGE_NVRAMSWARB_REQ3 0x00008000
1954
1955#define BGE_NVRAMACC_ENABLE 0x00000001
1956#define BGE_NVRAMACC_WRENABLE 0x00000002
1957
1958/* Mode control register */
1959#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1960#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1961#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1962#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1963#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
| 1556
1557/* Read DMA status register */
1558#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1559#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1560#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010
1561#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1562#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1563#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1564#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1565#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200
1566
1567/* Read DMA Reserved Control register */
1568#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1569#define BGE_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000C00
1570#define BGE_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000C0000
1571#define BGE_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1572#define BGE_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000FF0
1573#define BGE_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000FF000
1574#define BGE_RDMA_RSRVCTRL_TXMRGN_MASK 0xFFE00000
1575
1576#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1577#define BGE_RDMA_LSO_CRPTEN_CTRL_BLEN_LSO_4K 0x000C0000
1578
1579/*
1580 * Write DMA control registers
1581 */
1582#define BGE_WDMA_MODE 0x4C00
1583#define BGE_WDMA_STATUS 0x4C04
1584
1585/* Write DMA mode register */
1586#define BGE_WDMAMODE_RESET 0x00000001
1587#define BGE_WDMAMODE_ENABLE 0x00000002
1588#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004
1589#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008
1590#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010
1591#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020
1592#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040
1593#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080
1594#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100
1595#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200
1596#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC
1597#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000
1598#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000
1599
1600/* Write DMA status register */
1601#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004
1602#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1603#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010
1604#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020
1605#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040
1606#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080
1607#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100
1608#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200
1609
1610
1611/*
1612 * RX CPU registers
1613 */
1614#define BGE_RXCPU_MODE 0x5000
1615#define BGE_RXCPU_STATUS 0x5004
1616#define BGE_RXCPU_PC 0x501C
1617
1618/* RX CPU mode register */
1619#define BGE_RXCPUMODE_RESET 0x00000001
1620#define BGE_RXCPUMODE_SINGLESTEP 0x00000002
1621#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004
1622#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1623#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010
1624#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020
1625#define BGE_RXCPUMODE_ROMFAIL 0x00000040
1626#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080
1627#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100
1628#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1629#define BGE_RXCPUMODE_HALTCPU 0x00000400
1630#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800
1631#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1632#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000
1633
1634/* RX CPU status register */
1635#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001
1636#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1637#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004
1638#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008
1639#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010
1640#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020
1641#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1642#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080
1643#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100
1644#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200
1645#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000
1646#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000
1647#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1648#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1649#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1650#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1651#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000
1652
1653/*
1654 * V? CPU registers
1655 */
1656#define BGE_VCPU_STATUS 0x5100
1657#define BGE_VCPU_EXT_CTRL 0x6890
1658
1659#define BGE_VCPU_STATUS_INIT_DONE 0x04000000
1660#define BGE_VCPU_STATUS_DRV_RESET 0x08000000
1661
1662#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1663#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1664
1665/*
1666 * TX CPU registers
1667 */
1668#define BGE_TXCPU_MODE 0x5400
1669#define BGE_TXCPU_STATUS 0x5404
1670#define BGE_TXCPU_PC 0x541C
1671
1672/* TX CPU mode register */
1673#define BGE_TXCPUMODE_RESET 0x00000001
1674#define BGE_TXCPUMODE_SINGLESTEP 0x00000002
1675#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004
1676#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008
1677#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010
1678#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020
1679#define BGE_TXCPUMODE_ROMFAIL 0x00000040
1680#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080
1681#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100
1682#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200
1683#define BGE_TXCPUMODE_HALTCPU 0x00000400
1684#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800
1685#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000
1686
1687/* TX CPU status register */
1688#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001
1689#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002
1690#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004
1691#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008
1692#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010
1693#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020
1694#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040
1695#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080
1696#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100
1697#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200
1698#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000
1699#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000
1700#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000
1701#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000
1702#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000
1703#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000
1704#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000
1705
1706
1707/*
1708 * Low priority mailbox registers
1709 */
1710#define BGE_LPMBX_IRQ0_HI 0x5800
1711#define BGE_LPMBX_IRQ0_LO 0x5804
1712#define BGE_LPMBX_IRQ1_HI 0x5808
1713#define BGE_LPMBX_IRQ1_LO 0x580C
1714#define BGE_LPMBX_IRQ2_HI 0x5810
1715#define BGE_LPMBX_IRQ2_LO 0x5814
1716#define BGE_LPMBX_IRQ3_HI 0x5818
1717#define BGE_LPMBX_IRQ3_LO 0x581C
1718#define BGE_LPMBX_GEN0_HI 0x5820
1719#define BGE_LPMBX_GEN0_LO 0x5824
1720#define BGE_LPMBX_GEN1_HI 0x5828
1721#define BGE_LPMBX_GEN1_LO 0x582C
1722#define BGE_LPMBX_GEN2_HI 0x5830
1723#define BGE_LPMBX_GEN2_LO 0x5834
1724#define BGE_LPMBX_GEN3_HI 0x5828
1725#define BGE_LPMBX_GEN3_LO 0x582C
1726#define BGE_LPMBX_GEN4_HI 0x5840
1727#define BGE_LPMBX_GEN4_LO 0x5844
1728#define BGE_LPMBX_GEN5_HI 0x5848
1729#define BGE_LPMBX_GEN5_LO 0x584C
1730#define BGE_LPMBX_GEN6_HI 0x5850
1731#define BGE_LPMBX_GEN6_LO 0x5854
1732#define BGE_LPMBX_GEN7_HI 0x5858
1733#define BGE_LPMBX_GEN7_LO 0x585C
1734#define BGE_LPMBX_RELOAD_STATS_HI 0x5860
1735#define BGE_LPMBX_RELOAD_STATS_LO 0x5864
1736#define BGE_LPMBX_RX_STD_PROD_HI 0x5868
1737#define BGE_LPMBX_RX_STD_PROD_LO 0x586C
1738#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870
1739#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874
1740#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878
1741#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C
1742#define BGE_LPMBX_RX_CONS0_HI 0x5880
1743#define BGE_LPMBX_RX_CONS0_LO 0x5884
1744#define BGE_LPMBX_RX_CONS1_HI 0x5888
1745#define BGE_LPMBX_RX_CONS1_LO 0x588C
1746#define BGE_LPMBX_RX_CONS2_HI 0x5890
1747#define BGE_LPMBX_RX_CONS2_LO 0x5894
1748#define BGE_LPMBX_RX_CONS3_HI 0x5898
1749#define BGE_LPMBX_RX_CONS3_LO 0x589C
1750#define BGE_LPMBX_RX_CONS4_HI 0x58A0
1751#define BGE_LPMBX_RX_CONS4_LO 0x58A4
1752#define BGE_LPMBX_RX_CONS5_HI 0x58A8
1753#define BGE_LPMBX_RX_CONS5_LO 0x58AC
1754#define BGE_LPMBX_RX_CONS6_HI 0x58B0
1755#define BGE_LPMBX_RX_CONS6_LO 0x58B4
1756#define BGE_LPMBX_RX_CONS7_HI 0x58B8
1757#define BGE_LPMBX_RX_CONS7_LO 0x58BC
1758#define BGE_LPMBX_RX_CONS8_HI 0x58C0
1759#define BGE_LPMBX_RX_CONS8_LO 0x58C4
1760#define BGE_LPMBX_RX_CONS9_HI 0x58C8
1761#define BGE_LPMBX_RX_CONS9_LO 0x58CC
1762#define BGE_LPMBX_RX_CONS10_HI 0x58D0
1763#define BGE_LPMBX_RX_CONS10_LO 0x58D4
1764#define BGE_LPMBX_RX_CONS11_HI 0x58D8
1765#define BGE_LPMBX_RX_CONS11_LO 0x58DC
1766#define BGE_LPMBX_RX_CONS12_HI 0x58E0
1767#define BGE_LPMBX_RX_CONS12_LO 0x58E4
1768#define BGE_LPMBX_RX_CONS13_HI 0x58E8
1769#define BGE_LPMBX_RX_CONS13_LO 0x58EC
1770#define BGE_LPMBX_RX_CONS14_HI 0x58F0
1771#define BGE_LPMBX_RX_CONS14_LO 0x58F4
1772#define BGE_LPMBX_RX_CONS15_HI 0x58F8
1773#define BGE_LPMBX_RX_CONS15_LO 0x58FC
1774#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900
1775#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904
1776#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908
1777#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C
1778#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910
1779#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914
1780#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918
1781#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C
1782#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920
1783#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924
1784#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928
1785#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C
1786#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930
1787#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934
1788#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938
1789#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C
1790#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940
1791#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944
1792#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948
1793#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C
1794#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950
1795#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954
1796#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958
1797#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C
1798#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960
1799#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964
1800#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968
1801#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C
1802#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970
1803#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974
1804#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978
1805#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C
1806#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980
1807#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984
1808#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988
1809#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C
1810#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990
1811#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994
1812#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998
1813#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C
1814#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0
1815#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4
1816#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8
1817#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC
1818#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0
1819#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4
1820#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8
1821#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC
1822#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0
1823#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4
1824#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8
1825#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC
1826#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0
1827#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4
1828#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8
1829#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC
1830#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0
1831#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4
1832#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8
1833#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC
1834#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0
1835#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4
1836#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8
1837#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC
1838
1839/*
1840 * Flow throw Queue reset register
1841 */
1842#define BGE_FTQ_RESET 0x5C00
1843
1844#define BGE_FTQRESET_DMAREAD 0x00000002
1845#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004
1846#define BGE_FTQRESET_DMADONE 0x00000010
1847#define BGE_FTQRESET_SBDC 0x00000020
1848#define BGE_FTQRESET_SDI 0x00000040
1849#define BGE_FTQRESET_WDMA 0x00000080
1850#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100
1851#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200
1852#define BGE_FTQRESET_SDC 0x00000400
1853#define BGE_FTQRESET_HCC 0x00000800
1854#define BGE_FTQRESET_TXFIFO 0x00001000
1855#define BGE_FTQRESET_MBC 0x00002000
1856#define BGE_FTQRESET_RBDC 0x00004000
1857#define BGE_FTQRESET_RXLP 0x00008000
1858#define BGE_FTQRESET_RDBDI 0x00010000
1859#define BGE_FTQRESET_RDC 0x00020000
1860#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000
1861
1862/*
1863 * Message Signaled Interrupt registers
1864 */
1865#define BGE_MSI_MODE 0x6000
1866#define BGE_MSI_STATUS 0x6004
1867#define BGE_MSI_FIFOACCESS 0x6008
1868
1869/* MSI mode register */
1870#define BGE_MSIMODE_RESET 0x00000001
1871#define BGE_MSIMODE_ENABLE 0x00000002
1872#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020
1873#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080
1874
1875/* MSI status register */
1876#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004
1877#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008
1878#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010
1879#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020
1880#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040
1881
1882
1883/*
1884 * DMA Completion registers
1885 */
1886#define BGE_DMAC_MODE 0x6400
1887
1888/* DMA Completion mode register */
1889#define BGE_DMACMODE_RESET 0x00000001
1890#define BGE_DMACMODE_ENABLE 0x00000002
1891
1892
1893/*
1894 * General control registers.
1895 */
1896#define BGE_MODE_CTL 0x6800
1897#define BGE_MISC_CFG 0x6804
1898#define BGE_MISC_LOCAL_CTL 0x6808
1899#define BGE_RX_CPU_EVENT 0x6810
1900#define BGE_TX_CPU_EVENT 0x6820
1901#define BGE_EE_ADDR 0x6838
1902#define BGE_EE_DATA 0x683C
1903#define BGE_EE_CTL 0x6840
1904#define BGE_MDI_CTL 0x6844
1905#define BGE_EE_DELAY 0x6848
1906#define BGE_FASTBOOT_PC 0x6894
1907
1908#define BGE_RX_CPU_DRV_EVENT 0x00004000
1909
1910/*
1911 * NVRAM Control registers
1912 */
1913#define BGE_NVRAM_CMD 0x7000
1914#define BGE_NVRAM_STAT 0x7004
1915#define BGE_NVRAM_WRDATA 0x7008
1916#define BGE_NVRAM_ADDR 0x700c
1917#define BGE_NVRAM_RDDATA 0x7010
1918#define BGE_NVRAM_CFG1 0x7014
1919#define BGE_NVRAM_CFG2 0x7018
1920#define BGE_NVRAM_CFG3 0x701c
1921#define BGE_NVRAM_SWARB 0x7020
1922#define BGE_NVRAM_ACCESS 0x7024
1923#define BGE_NVRAM_WRITE1 0x7028
1924
1925#define BGE_NVRAMCMD_RESET 0x00000001
1926#define BGE_NVRAMCMD_DONE 0x00000008
1927#define BGE_NVRAMCMD_START 0x00000010
1928#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd */
1929#define BGE_NVRAMCMD_ERASE 0x00000040
1930#define BGE_NVRAMCMD_FIRST 0x00000080
1931#define BGE_NVRAMCMD_LAST 0x00000100
1932
1933#define BGE_NVRAM_READCMD \
1934 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1935 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE)
1936#define BGE_NVRAM_WRITECMD \
1937 (BGE_NVRAMCMD_FIRST|BGE_NVRAMCMD_LAST| \
1938 BGE_NVRAMCMD_START|BGE_NVRAMCMD_DONE|BGE_NVRAMCMD_WR)
1939
1940#define BGE_NVRAMSWARB_SET0 0x00000001
1941#define BGE_NVRAMSWARB_SET1 0x00000002
1942#define BGE_NVRAMSWARB_SET2 0x00000003
1943#define BGE_NVRAMSWARB_SET3 0x00000004
1944#define BGE_NVRAMSWARB_CLR0 0x00000010
1945#define BGE_NVRAMSWARB_CLR1 0x00000020
1946#define BGE_NVRAMSWARB_CLR2 0x00000040
1947#define BGE_NVRAMSWARB_CLR3 0x00000080
1948#define BGE_NVRAMSWARB_GNT0 0x00000100
1949#define BGE_NVRAMSWARB_GNT1 0x00000200
1950#define BGE_NVRAMSWARB_GNT2 0x00000400
1951#define BGE_NVRAMSWARB_GNT3 0x00000800
1952#define BGE_NVRAMSWARB_REQ0 0x00001000
1953#define BGE_NVRAMSWARB_REQ1 0x00002000
1954#define BGE_NVRAMSWARB_REQ2 0x00004000
1955#define BGE_NVRAMSWARB_REQ3 0x00008000
1956
1957#define BGE_NVRAMACC_ENABLE 0x00000001
1958#define BGE_NVRAMACC_WRENABLE 0x00000002
1959
1960/* Mode control register */
1961#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001
1962#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002
1963#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004
1964#define BGE_MODECTL_BYTESWAP_DATA 0x00000010
1965#define BGE_MODECTL_WORDSWAP_DATA 0x00000020
|
| 1966#define BGE_MODECTL_BYTESWAP_B2HRX_DATA 0x00000040
1967#define BGE_MODECTL_WORDSWAP_B2HRX_DATA 0x00000080
|
1964#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1965#define BGE_MODECTL_NO_RX_CRC 0x00000400
1966#define BGE_MODECTL_RX_BADFRAMES 0x00000800
1967#define BGE_MODECTL_NO_TX_INTR 0x00002000
1968#define BGE_MODECTL_NO_RX_INTR 0x00004000
1969#define BGE_MODECTL_FORCE_PCI32 0x00008000
| 1968#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200
1969#define BGE_MODECTL_NO_RX_CRC 0x00000400
1970#define BGE_MODECTL_RX_BADFRAMES 0x00000800
1971#define BGE_MODECTL_NO_TX_INTR 0x00002000
1972#define BGE_MODECTL_NO_RX_INTR 0x00004000
1973#define BGE_MODECTL_FORCE_PCI32 0x00008000
|
| 1974#define BGE_MODECTL_B2HRX_ENABLE 0x00008000
|
1970#define BGE_MODECTL_STACKUP 0x00010000
1971#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
| 1975#define BGE_MODECTL_STACKUP 0x00010000
1976#define BGE_MODECTL_HOST_SEND_BDS 0x00020000
|
| 1977#define BGE_MODECTL_HTX2B_ENABLE 0x00040000
|
1972#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1973#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1974#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1975#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1976#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1977#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1978#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1979#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1980#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1981
1982/* Misc. config register */
1983#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1984#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1985#define BGE_MISCCFG_BOARD_ID 0x0001E000
1986#define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1987#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1988#define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1989#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000
1990
1991#define BGE_32BITTIME_66MHZ (0x41 << 1)
1992
1993/* Misc. Local Control */
1994#define BGE_MLC_INTR_STATE 0x00000001
1995#define BGE_MLC_INTR_CLR 0x00000002
1996#define BGE_MLC_INTR_SET 0x00000004
1997#define BGE_MLC_INTR_ONATTN 0x00000008
1998#define BGE_MLC_MISCIO_IN0 0x00000100
1999#define BGE_MLC_MISCIO_IN1 0x00000200
2000#define BGE_MLC_MISCIO_IN2 0x00000400
2001#define BGE_MLC_MISCIO_OUTEN0 0x00000800
2002#define BGE_MLC_MISCIO_OUTEN1 0x00001000
2003#define BGE_MLC_MISCIO_OUTEN2 0x00002000
2004#define BGE_MLC_MISCIO_OUT0 0x00004000
2005#define BGE_MLC_MISCIO_OUT1 0x00008000
2006#define BGE_MLC_MISCIO_OUT2 0x00010000
2007#define BGE_MLC_EXTRAM_ENB 0x00020000
2008#define BGE_MLC_SRAM_SIZE 0x001C0000
2009#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
2010#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
2011#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
2012#define BGE_MLC_AUTO_EEPROM 0x01000000
2013
2014#define BGE_SSRAMSIZE_256KB 0x00000000
2015#define BGE_SSRAMSIZE_512KB 0x00040000
2016#define BGE_SSRAMSIZE_1MB 0x00080000
2017#define BGE_SSRAMSIZE_2MB 0x000C0000
2018#define BGE_SSRAMSIZE_4MB 0x00100000
2019#define BGE_SSRAMSIZE_8MB 0x00140000
2020#define BGE_SSRAMSIZE_16M 0x00180000
2021
2022/* EEPROM address register */
2023#define BGE_EEADDR_ADDRESS 0x0000FFFC
2024#define BGE_EEADDR_HALFCLK 0x01FF0000
2025#define BGE_EEADDR_START 0x02000000
2026#define BGE_EEADDR_DEVID 0x1C000000
2027#define BGE_EEADDR_RESET 0x20000000
2028#define BGE_EEADDR_DONE 0x40000000
2029#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
2030
2031#define BGE_EEDEVID(x) ((x & 7) << 26)
2032#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
2033#define BGE_HALFCLK_384SCL 0x60
2034#define BGE_EE_READCMD \
2035 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2036 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
2037#define BGE_EE_WRCMD \
2038 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2039 BGE_EEADDR_START|BGE_EEADDR_DONE)
2040
2041/* EEPROM Control register */
2042#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
2043#define BGE_EECTL_CLKOUT 0x00000002
2044#define BGE_EECTL_CLKIN 0x00000004
2045#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
2046#define BGE_EECTL_DATAOUT 0x00000010
2047#define BGE_EECTL_DATAIN 0x00000020
2048
2049/* MDI (MII/GMII) access register */
2050#define BGE_MDI_DATA 0x00000001
2051#define BGE_MDI_DIR 0x00000002
2052#define BGE_MDI_SEL 0x00000004
2053#define BGE_MDI_CLK 0x00000008
2054
2055#define BGE_MEMWIN_START 0x00008000
2056#define BGE_MEMWIN_END 0x0000FFFF
2057
2058
2059#define BGE_MEMWIN_READ(sc, x, val) \
2060 do { \
2061 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2062 (0xFFFF0000 & x), 4); \
2063 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
2064 } while(0)
2065
2066#define BGE_MEMWIN_WRITE(sc, x, val) \
2067 do { \
2068 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2069 (0xFFFF0000 & x), 4); \
2070 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
2071 } while(0)
2072
2073/*
2074 * This magic number is written to the firmware mailbox at 0xb50
2075 * before a software reset is issued. After the internal firmware
2076 * has completed its initialization it will write the opposite of
2077 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location,
2078 * allowing the driver to synchronize with the firmware.
2079 */
2080#define BGE_SRAM_FW_MB_MAGIC 0x4B657654
2081
2082typedef struct {
2083 uint32_t bge_addr_hi;
2084 uint32_t bge_addr_lo;
2085} bge_hostaddr;
2086
2087#define BGE_HOSTADDR(x, y) \
2088 do { \
2089 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
2090 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
2091 } while(0)
2092
2093#define BGE_ADDR_LO(y) \
2094 ((uint64_t) (y) & 0xFFFFFFFF)
2095#define BGE_ADDR_HI(y) \
2096 ((uint64_t) (y) >> 32)
2097
2098/* Ring control block structure */
2099struct bge_rcb {
2100 bge_hostaddr bge_hostaddr;
2101 uint32_t bge_maxlen_flags;
2102 uint32_t bge_nicaddr;
2103};
2104
2105#define RCB_WRITE_4(sc, rcb, offset, val) \
2106 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
2107#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
2108
2109#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
2110#define BGE_RCB_FLAG_RING_DISABLED 0x0002
2111
2112struct bge_tx_bd {
2113 bge_hostaddr bge_addr;
2114#if BYTE_ORDER == LITTLE_ENDIAN
2115 uint16_t bge_flags;
2116 uint16_t bge_len;
2117 uint16_t bge_vlan_tag;
2118 uint16_t bge_mss;
2119#else
2120 uint16_t bge_len;
2121 uint16_t bge_flags;
2122 uint16_t bge_mss;
2123 uint16_t bge_vlan_tag;
2124#endif
2125};
2126
2127#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
2128#define BGE_TXBDFLAG_IP_CSUM 0x0002
2129#define BGE_TXBDFLAG_END 0x0004
2130#define BGE_TXBDFLAG_IP_FRAG 0x0008
2131#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */
2132#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
2133#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */
2134#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */
2135#define BGE_TXBDFLAG_VLAN_TAG 0x0040
2136#define BGE_TXBDFLAG_COAL_NOW 0x0080
2137#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
2138#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
2139#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */
2140#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */
2141#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
2142#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */
2143#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */
2144#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */
2145#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
2146#define BGE_TXBDFLAG_NO_CRC 0x8000
2147
2148#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */
2149/* Bits [1:0] of the MSS header length. */
2150#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */
2151
2152#define BGE_NIC_TXRING_ADDR(ringno, size) \
2153 BGE_SEND_RING_1_TO_4 + \
2154 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
2155
2156struct bge_rx_bd {
2157 bge_hostaddr bge_addr;
2158#if BYTE_ORDER == LITTLE_ENDIAN
2159 uint16_t bge_len;
2160 uint16_t bge_idx;
2161 uint16_t bge_flags;
2162 uint16_t bge_type;
2163 uint16_t bge_tcp_udp_csum;
2164 uint16_t bge_ip_csum;
2165 uint16_t bge_vlan_tag;
2166 uint16_t bge_error_flag;
2167#else
2168 uint16_t bge_idx;
2169 uint16_t bge_len;
2170 uint16_t bge_type;
2171 uint16_t bge_flags;
2172 uint16_t bge_ip_csum;
2173 uint16_t bge_tcp_udp_csum;
2174 uint16_t bge_error_flag;
2175 uint16_t bge_vlan_tag;
2176#endif
2177 uint32_t bge_rsvd;
2178 uint32_t bge_opaque;
2179};
2180
2181struct bge_extrx_bd {
2182 bge_hostaddr bge_addr1;
2183 bge_hostaddr bge_addr2;
2184 bge_hostaddr bge_addr3;
2185#if BYTE_ORDER == LITTLE_ENDIAN
2186 uint16_t bge_len2;
2187 uint16_t bge_len1;
2188 uint16_t bge_rsvd1;
2189 uint16_t bge_len3;
2190#else
2191 uint16_t bge_len1;
2192 uint16_t bge_len2;
2193 uint16_t bge_len3;
2194 uint16_t bge_rsvd1;
2195#endif
2196 bge_hostaddr bge_addr0;
2197#if BYTE_ORDER == LITTLE_ENDIAN
2198 uint16_t bge_len0;
2199 uint16_t bge_idx;
2200 uint16_t bge_flags;
2201 uint16_t bge_type;
2202 uint16_t bge_tcp_udp_csum;
2203 uint16_t bge_ip_csum;
2204 uint16_t bge_vlan_tag;
2205 uint16_t bge_error_flag;
2206#else
2207 uint16_t bge_idx;
2208 uint16_t bge_len0;
2209 uint16_t bge_type;
2210 uint16_t bge_flags;
2211 uint16_t bge_ip_csum;
2212 uint16_t bge_tcp_udp_csum;
2213 uint16_t bge_error_flag;
2214 uint16_t bge_vlan_tag;
2215#endif
2216 uint32_t bge_rsvd0;
2217 uint32_t bge_opaque;
2218};
2219
2220#define BGE_RXBDFLAG_END 0x0004
2221#define BGE_RXBDFLAG_JUMBO_RING 0x0020
2222#define BGE_RXBDFLAG_VLAN_TAG 0x0040
2223#define BGE_RXBDFLAG_ERROR 0x0400
2224#define BGE_RXBDFLAG_MINI_RING 0x0800
2225#define BGE_RXBDFLAG_IP_CSUM 0x1000
2226#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2227#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2228#define BGE_RXBDFLAG_IPV6 0x8000
2229
2230#define BGE_RXERRFLAG_BAD_CRC 0x0001
2231#define BGE_RXERRFLAG_COLL_DETECT 0x0002
2232#define BGE_RXERRFLAG_LINK_LOST 0x0004
2233#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2234#define BGE_RXERRFLAG_MAC_ABORT 0x0010
2235#define BGE_RXERRFLAG_RUNT 0x0020
2236#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2237#define BGE_RXERRFLAG_GIANT 0x0080
2238#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */
2239
2240struct bge_sts_idx {
2241#if BYTE_ORDER == LITTLE_ENDIAN
2242 uint16_t bge_rx_prod_idx;
2243 uint16_t bge_tx_cons_idx;
2244#else
2245 uint16_t bge_tx_cons_idx;
2246 uint16_t bge_rx_prod_idx;
2247#endif
2248};
2249
2250struct bge_status_block {
2251 uint32_t bge_status;
2252 uint32_t bge_status_tag;
2253#if BYTE_ORDER == LITTLE_ENDIAN
2254 uint16_t bge_rx_jumbo_cons_idx;
2255 uint16_t bge_rx_std_cons_idx;
2256 uint16_t bge_rx_mini_cons_idx;
2257 uint16_t bge_rsvd1;
2258#else
2259 uint16_t bge_rx_std_cons_idx;
2260 uint16_t bge_rx_jumbo_cons_idx;
2261 uint16_t bge_rsvd1;
2262 uint16_t bge_rx_mini_cons_idx;
2263#endif
2264 struct bge_sts_idx bge_idx[16];
2265};
2266
2267#define BGE_STATFLAG_UPDATED 0x00000001
2268#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2269#define BGE_STATFLAG_ERROR 0x00000004
2270
2271
2272/*
2273 * Broadcom Vendor ID
2274 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
2275 * even though they're now manufactured by Broadcom)
2276 */
2277#define BCOM_VENDORID 0x14E4
2278#define BCOM_DEVICEID_BCM5700 0x1644
2279#define BCOM_DEVICEID_BCM5701 0x1645
2280#define BCOM_DEVICEID_BCM5702 0x1646
2281#define BCOM_DEVICEID_BCM5702X 0x16A6
2282#define BCOM_DEVICEID_BCM5702_ALT 0x16C6
2283#define BCOM_DEVICEID_BCM5703 0x1647
2284#define BCOM_DEVICEID_BCM5703X 0x16A7
2285#define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2286#define BCOM_DEVICEID_BCM5704C 0x1648
2287#define BCOM_DEVICEID_BCM5704S 0x16A8
2288#define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2289#define BCOM_DEVICEID_BCM5705 0x1653
2290#define BCOM_DEVICEID_BCM5705K 0x1654
2291#define BCOM_DEVICEID_BCM5705F 0x166E
2292#define BCOM_DEVICEID_BCM5705M 0x165D
2293#define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2294#define BCOM_DEVICEID_BCM5714C 0x1668
2295#define BCOM_DEVICEID_BCM5714S 0x1669
2296#define BCOM_DEVICEID_BCM5715 0x1678
2297#define BCOM_DEVICEID_BCM5715S 0x1679
2298#define BCOM_DEVICEID_BCM5717 0x1655
2299#define BCOM_DEVICEID_BCM5718 0x1656
2300#define BCOM_DEVICEID_BCM5719 0x1657
| 1978#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000
1979#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000
1980#define BGE_MODECTL_TX_ATTN_INTR 0x01000000
1981#define BGE_MODECTL_RX_ATTN_INTR 0x02000000
1982#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000
1983#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000
1984#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000
1985#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000
1986#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000
1987
1988/* Misc. config register */
1989#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001
1990#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE
1991#define BGE_MISCCFG_BOARD_ID 0x0001E000
1992#define BGE_MISCCFG_BOARD_ID_5788 0x00010000
1993#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000
1994#define BGE_MISCCFG_EPHY_IDDQ 0x00200000
1995#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000
1996
1997#define BGE_32BITTIME_66MHZ (0x41 << 1)
1998
1999/* Misc. Local Control */
2000#define BGE_MLC_INTR_STATE 0x00000001
2001#define BGE_MLC_INTR_CLR 0x00000002
2002#define BGE_MLC_INTR_SET 0x00000004
2003#define BGE_MLC_INTR_ONATTN 0x00000008
2004#define BGE_MLC_MISCIO_IN0 0x00000100
2005#define BGE_MLC_MISCIO_IN1 0x00000200
2006#define BGE_MLC_MISCIO_IN2 0x00000400
2007#define BGE_MLC_MISCIO_OUTEN0 0x00000800
2008#define BGE_MLC_MISCIO_OUTEN1 0x00001000
2009#define BGE_MLC_MISCIO_OUTEN2 0x00002000
2010#define BGE_MLC_MISCIO_OUT0 0x00004000
2011#define BGE_MLC_MISCIO_OUT1 0x00008000
2012#define BGE_MLC_MISCIO_OUT2 0x00010000
2013#define BGE_MLC_EXTRAM_ENB 0x00020000
2014#define BGE_MLC_SRAM_SIZE 0x001C0000
2015#define BGE_MLC_BANK_SEL 0x00200000 /* 0 = 2 banks, 1 == 1 */
2016#define BGE_MLC_SSRAM_TYPE 0x00400000 /* 1 = ZBT, 0 = standard */
2017#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000
2018#define BGE_MLC_AUTO_EEPROM 0x01000000
2019
2020#define BGE_SSRAMSIZE_256KB 0x00000000
2021#define BGE_SSRAMSIZE_512KB 0x00040000
2022#define BGE_SSRAMSIZE_1MB 0x00080000
2023#define BGE_SSRAMSIZE_2MB 0x000C0000
2024#define BGE_SSRAMSIZE_4MB 0x00100000
2025#define BGE_SSRAMSIZE_8MB 0x00140000
2026#define BGE_SSRAMSIZE_16M 0x00180000
2027
2028/* EEPROM address register */
2029#define BGE_EEADDR_ADDRESS 0x0000FFFC
2030#define BGE_EEADDR_HALFCLK 0x01FF0000
2031#define BGE_EEADDR_START 0x02000000
2032#define BGE_EEADDR_DEVID 0x1C000000
2033#define BGE_EEADDR_RESET 0x20000000
2034#define BGE_EEADDR_DONE 0x40000000
2035#define BGE_EEADDR_RW 0x80000000 /* 1 = rd, 0 = wr */
2036
2037#define BGE_EEDEVID(x) ((x & 7) << 26)
2038#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16)
2039#define BGE_HALFCLK_384SCL 0x60
2040#define BGE_EE_READCMD \
2041 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2042 BGE_EEADDR_START|BGE_EEADDR_RW|BGE_EEADDR_DONE)
2043#define BGE_EE_WRCMD \
2044 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)|BGE_EEDEVID(0)| \
2045 BGE_EEADDR_START|BGE_EEADDR_DONE)
2046
2047/* EEPROM Control register */
2048#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001
2049#define BGE_EECTL_CLKOUT 0x00000002
2050#define BGE_EECTL_CLKIN 0x00000004
2051#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008
2052#define BGE_EECTL_DATAOUT 0x00000010
2053#define BGE_EECTL_DATAIN 0x00000020
2054
2055/* MDI (MII/GMII) access register */
2056#define BGE_MDI_DATA 0x00000001
2057#define BGE_MDI_DIR 0x00000002
2058#define BGE_MDI_SEL 0x00000004
2059#define BGE_MDI_CLK 0x00000008
2060
2061#define BGE_MEMWIN_START 0x00008000
2062#define BGE_MEMWIN_END 0x0000FFFF
2063
2064
2065#define BGE_MEMWIN_READ(sc, x, val) \
2066 do { \
2067 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2068 (0xFFFF0000 & x), 4); \
2069 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \
2070 } while(0)
2071
2072#define BGE_MEMWIN_WRITE(sc, x, val) \
2073 do { \
2074 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \
2075 (0xFFFF0000 & x), 4); \
2076 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \
2077 } while(0)
2078
2079/*
2080 * This magic number is written to the firmware mailbox at 0xb50
2081 * before a software reset is issued. After the internal firmware
2082 * has completed its initialization it will write the opposite of
2083 * this value, ~BGE_SRAM_FW_MB_MAGIC, to the same location,
2084 * allowing the driver to synchronize with the firmware.
2085 */
2086#define BGE_SRAM_FW_MB_MAGIC 0x4B657654
2087
2088typedef struct {
2089 uint32_t bge_addr_hi;
2090 uint32_t bge_addr_lo;
2091} bge_hostaddr;
2092
2093#define BGE_HOSTADDR(x, y) \
2094 do { \
2095 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \
2096 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \
2097 } while(0)
2098
2099#define BGE_ADDR_LO(y) \
2100 ((uint64_t) (y) & 0xFFFFFFFF)
2101#define BGE_ADDR_HI(y) \
2102 ((uint64_t) (y) >> 32)
2103
2104/* Ring control block structure */
2105struct bge_rcb {
2106 bge_hostaddr bge_hostaddr;
2107 uint32_t bge_maxlen_flags;
2108 uint32_t bge_nicaddr;
2109};
2110
2111#define RCB_WRITE_4(sc, rcb, offset, val) \
2112 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val)
2113#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 | (flags))
2114
2115#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001
2116#define BGE_RCB_FLAG_RING_DISABLED 0x0002
2117
2118struct bge_tx_bd {
2119 bge_hostaddr bge_addr;
2120#if BYTE_ORDER == LITTLE_ENDIAN
2121 uint16_t bge_flags;
2122 uint16_t bge_len;
2123 uint16_t bge_vlan_tag;
2124 uint16_t bge_mss;
2125#else
2126 uint16_t bge_len;
2127 uint16_t bge_flags;
2128 uint16_t bge_mss;
2129 uint16_t bge_vlan_tag;
2130#endif
2131};
2132
2133#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001
2134#define BGE_TXBDFLAG_IP_CSUM 0x0002
2135#define BGE_TXBDFLAG_END 0x0004
2136#define BGE_TXBDFLAG_IP_FRAG 0x0008
2137#define BGE_TXBDFLAG_JUMBO_FRAME 0x0008 /* 5717 */
2138#define BGE_TXBDFLAG_IP_FRAG_END 0x0010
2139#define BGE_TXBDFLAG_HDRLEN_BIT2 0x0010 /* 5717 */
2140#define BGE_TXBDFLAG_SNAP 0x0020 /* 5717 */
2141#define BGE_TXBDFLAG_VLAN_TAG 0x0040
2142#define BGE_TXBDFLAG_COAL_NOW 0x0080
2143#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100
2144#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200
2145#define BGE_TXBDFLAG_HDRLEN_BIT3 0x0400 /* 5717 */
2146#define BGE_TXBDFLAG_HDRLEN_BIT4 0x0800 /* 5717 */
2147#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000
2148#define BGE_TXBDFLAG_HDRLEN_BIT5 0x1000 /* 5717 */
2149#define BGE_TXBDFLAG_HDRLEN_BIT6 0x2000 /* 5717 */
2150#define BGE_TXBDFLAG_HDRLEN_BIT7 0x4000 /* 5717 */
2151#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000
2152#define BGE_TXBDFLAG_NO_CRC 0x8000
2153
2154#define BGE_TXBDFLAG_MSS_SIZE_MASK 0x3FFF /* 5717 */
2155/* Bits [1:0] of the MSS header length. */
2156#define BGE_TXBDFLAG_MSS_HDRLEN_MASK 0xC000 /* 5717 */
2157
2158#define BGE_NIC_TXRING_ADDR(ringno, size) \
2159 BGE_SEND_RING_1_TO_4 + \
2160 ((ringno * sizeof(struct bge_tx_bd) * size) / 4)
2161
2162struct bge_rx_bd {
2163 bge_hostaddr bge_addr;
2164#if BYTE_ORDER == LITTLE_ENDIAN
2165 uint16_t bge_len;
2166 uint16_t bge_idx;
2167 uint16_t bge_flags;
2168 uint16_t bge_type;
2169 uint16_t bge_tcp_udp_csum;
2170 uint16_t bge_ip_csum;
2171 uint16_t bge_vlan_tag;
2172 uint16_t bge_error_flag;
2173#else
2174 uint16_t bge_idx;
2175 uint16_t bge_len;
2176 uint16_t bge_type;
2177 uint16_t bge_flags;
2178 uint16_t bge_ip_csum;
2179 uint16_t bge_tcp_udp_csum;
2180 uint16_t bge_error_flag;
2181 uint16_t bge_vlan_tag;
2182#endif
2183 uint32_t bge_rsvd;
2184 uint32_t bge_opaque;
2185};
2186
2187struct bge_extrx_bd {
2188 bge_hostaddr bge_addr1;
2189 bge_hostaddr bge_addr2;
2190 bge_hostaddr bge_addr3;
2191#if BYTE_ORDER == LITTLE_ENDIAN
2192 uint16_t bge_len2;
2193 uint16_t bge_len1;
2194 uint16_t bge_rsvd1;
2195 uint16_t bge_len3;
2196#else
2197 uint16_t bge_len1;
2198 uint16_t bge_len2;
2199 uint16_t bge_len3;
2200 uint16_t bge_rsvd1;
2201#endif
2202 bge_hostaddr bge_addr0;
2203#if BYTE_ORDER == LITTLE_ENDIAN
2204 uint16_t bge_len0;
2205 uint16_t bge_idx;
2206 uint16_t bge_flags;
2207 uint16_t bge_type;
2208 uint16_t bge_tcp_udp_csum;
2209 uint16_t bge_ip_csum;
2210 uint16_t bge_vlan_tag;
2211 uint16_t bge_error_flag;
2212#else
2213 uint16_t bge_idx;
2214 uint16_t bge_len0;
2215 uint16_t bge_type;
2216 uint16_t bge_flags;
2217 uint16_t bge_ip_csum;
2218 uint16_t bge_tcp_udp_csum;
2219 uint16_t bge_error_flag;
2220 uint16_t bge_vlan_tag;
2221#endif
2222 uint32_t bge_rsvd0;
2223 uint32_t bge_opaque;
2224};
2225
2226#define BGE_RXBDFLAG_END 0x0004
2227#define BGE_RXBDFLAG_JUMBO_RING 0x0020
2228#define BGE_RXBDFLAG_VLAN_TAG 0x0040
2229#define BGE_RXBDFLAG_ERROR 0x0400
2230#define BGE_RXBDFLAG_MINI_RING 0x0800
2231#define BGE_RXBDFLAG_IP_CSUM 0x1000
2232#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000
2233#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000
2234#define BGE_RXBDFLAG_IPV6 0x8000
2235
2236#define BGE_RXERRFLAG_BAD_CRC 0x0001
2237#define BGE_RXERRFLAG_COLL_DETECT 0x0002
2238#define BGE_RXERRFLAG_LINK_LOST 0x0004
2239#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008
2240#define BGE_RXERRFLAG_MAC_ABORT 0x0010
2241#define BGE_RXERRFLAG_RUNT 0x0020
2242#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040
2243#define BGE_RXERRFLAG_GIANT 0x0080
2244#define BGE_RXERRFLAG_IP_CSUM_NOK 0x1000 /* 5717 */
2245
2246struct bge_sts_idx {
2247#if BYTE_ORDER == LITTLE_ENDIAN
2248 uint16_t bge_rx_prod_idx;
2249 uint16_t bge_tx_cons_idx;
2250#else
2251 uint16_t bge_tx_cons_idx;
2252 uint16_t bge_rx_prod_idx;
2253#endif
2254};
2255
2256struct bge_status_block {
2257 uint32_t bge_status;
2258 uint32_t bge_status_tag;
2259#if BYTE_ORDER == LITTLE_ENDIAN
2260 uint16_t bge_rx_jumbo_cons_idx;
2261 uint16_t bge_rx_std_cons_idx;
2262 uint16_t bge_rx_mini_cons_idx;
2263 uint16_t bge_rsvd1;
2264#else
2265 uint16_t bge_rx_std_cons_idx;
2266 uint16_t bge_rx_jumbo_cons_idx;
2267 uint16_t bge_rsvd1;
2268 uint16_t bge_rx_mini_cons_idx;
2269#endif
2270 struct bge_sts_idx bge_idx[16];
2271};
2272
2273#define BGE_STATFLAG_UPDATED 0x00000001
2274#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002
2275#define BGE_STATFLAG_ERROR 0x00000004
2276
2277
2278/*
2279 * Broadcom Vendor ID
2280 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID
2281 * even though they're now manufactured by Broadcom)
2282 */
2283#define BCOM_VENDORID 0x14E4
2284#define BCOM_DEVICEID_BCM5700 0x1644
2285#define BCOM_DEVICEID_BCM5701 0x1645
2286#define BCOM_DEVICEID_BCM5702 0x1646
2287#define BCOM_DEVICEID_BCM5702X 0x16A6
2288#define BCOM_DEVICEID_BCM5702_ALT 0x16C6
2289#define BCOM_DEVICEID_BCM5703 0x1647
2290#define BCOM_DEVICEID_BCM5703X 0x16A7
2291#define BCOM_DEVICEID_BCM5703_ALT 0x16C7
2292#define BCOM_DEVICEID_BCM5704C 0x1648
2293#define BCOM_DEVICEID_BCM5704S 0x16A8
2294#define BCOM_DEVICEID_BCM5704S_ALT 0x1649
2295#define BCOM_DEVICEID_BCM5705 0x1653
2296#define BCOM_DEVICEID_BCM5705K 0x1654
2297#define BCOM_DEVICEID_BCM5705F 0x166E
2298#define BCOM_DEVICEID_BCM5705M 0x165D
2299#define BCOM_DEVICEID_BCM5705M_ALT 0x165E
2300#define BCOM_DEVICEID_BCM5714C 0x1668
2301#define BCOM_DEVICEID_BCM5714S 0x1669
2302#define BCOM_DEVICEID_BCM5715 0x1678
2303#define BCOM_DEVICEID_BCM5715S 0x1679
2304#define BCOM_DEVICEID_BCM5717 0x1655
2305#define BCOM_DEVICEID_BCM5718 0x1656
2306#define BCOM_DEVICEID_BCM5719 0x1657
|
2301#define BCOM_DEVICEID_BCM5720 0x1658
| 2307#define BCOM_DEVICEID_BCM5720_PP 0x1658 /* Not released to public. */
2308#define BCOM_DEVICEID_BCM5720 0x165F
|
2302#define BCOM_DEVICEID_BCM5721 0x1659
2303#define BCOM_DEVICEID_BCM5722 0x165A
2304#define BCOM_DEVICEID_BCM5723 0x165B
2305#define BCOM_DEVICEID_BCM5750 0x1676
2306#define BCOM_DEVICEID_BCM5750M 0x167C
2307#define BCOM_DEVICEID_BCM5751 0x1677
2308#define BCOM_DEVICEID_BCM5751F 0x167E
2309#define BCOM_DEVICEID_BCM5751M 0x167D
2310#define BCOM_DEVICEID_BCM5752 0x1600
2311#define BCOM_DEVICEID_BCM5752M 0x1601
2312#define BCOM_DEVICEID_BCM5753 0x16F7
2313#define BCOM_DEVICEID_BCM5753F 0x16FE
2314#define BCOM_DEVICEID_BCM5753M 0x16FD
2315#define BCOM_DEVICEID_BCM5754 0x167A
2316#define BCOM_DEVICEID_BCM5754M 0x1672
2317#define BCOM_DEVICEID_BCM5755 0x167B
2318#define BCOM_DEVICEID_BCM5755M 0x1673
2319#define BCOM_DEVICEID_BCM5756 0x1674
2320#define BCOM_DEVICEID_BCM5761 0x1681
2321#define BCOM_DEVICEID_BCM5761E 0x1680
2322#define BCOM_DEVICEID_BCM5761S 0x1688
2323#define BCOM_DEVICEID_BCM5761SE 0x1689
2324#define BCOM_DEVICEID_BCM5764 0x1684
2325#define BCOM_DEVICEID_BCM5780 0x166A
2326#define BCOM_DEVICEID_BCM5780S 0x166B
2327#define BCOM_DEVICEID_BCM5781 0x16DD
2328#define BCOM_DEVICEID_BCM5782 0x1696
2329#define BCOM_DEVICEID_BCM5784 0x1698
2330#define BCOM_DEVICEID_BCM5785F 0x16a0
2331#define BCOM_DEVICEID_BCM5785G 0x1699
2332#define BCOM_DEVICEID_BCM5786 0x169A
2333#define BCOM_DEVICEID_BCM5787 0x169B
2334#define BCOM_DEVICEID_BCM5787M 0x1693
2335#define BCOM_DEVICEID_BCM5787F 0x167f
2336#define BCOM_DEVICEID_BCM5788 0x169C
2337#define BCOM_DEVICEID_BCM5789 0x169D
2338#define BCOM_DEVICEID_BCM5901 0x170D
2339#define BCOM_DEVICEID_BCM5901A2 0x170E
2340#define BCOM_DEVICEID_BCM5903M 0x16FF
2341#define BCOM_DEVICEID_BCM5906 0x1712
2342#define BCOM_DEVICEID_BCM5906M 0x1713
2343#define BCOM_DEVICEID_BCM57760 0x1690
2344#define BCOM_DEVICEID_BCM57761 0x16B0
2345#define BCOM_DEVICEID_BCM57765 0x16B4
2346#define BCOM_DEVICEID_BCM57780 0x1692
2347#define BCOM_DEVICEID_BCM57781 0x16B1
2348#define BCOM_DEVICEID_BCM57785 0x16B5
2349#define BCOM_DEVICEID_BCM57788 0x1691
2350#define BCOM_DEVICEID_BCM57790 0x1694
2351#define BCOM_DEVICEID_BCM57791 0x16B2
2352#define BCOM_DEVICEID_BCM57795 0x16B6
2353
2354/*
2355 * Alteon AceNIC PCI vendor/device ID.
2356 */
2357#define ALTEON_VENDORID 0x12AE
2358#define ALTEON_DEVICEID_ACENIC 0x0001
2359#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2360#define ALTEON_DEVICEID_BCM5700 0x0003
2361#define ALTEON_DEVICEID_BCM5701 0x0004
2362
2363/*
2364 * 3Com 3c996 PCI vendor/device ID.
2365 */
2366#define TC_VENDORID 0x10B7
2367#define TC_DEVICEID_3C996 0x0003
2368
2369/*
2370 * SysKonnect PCI vendor ID
2371 */
2372#define SK_VENDORID 0x1148
2373#define SK_DEVICEID_ALTIMA 0x4400
2374#define SK_SUBSYSID_9D21 0x4421
2375#define SK_SUBSYSID_9D41 0x4441
2376
2377/*
2378 * Altima PCI vendor/device ID.
2379 */
2380#define ALTIMA_VENDORID 0x173b
2381#define ALTIMA_DEVICE_AC1000 0x03e8
2382#define ALTIMA_DEVICE_AC1002 0x03e9
2383#define ALTIMA_DEVICE_AC9100 0x03ea
2384
2385/*
2386 * Dell PCI vendor ID
2387 */
2388
2389#define DELL_VENDORID 0x1028
2390
2391/*
2392 * Apple PCI vendor ID.
2393 */
2394#define APPLE_VENDORID 0x106b
2395#define APPLE_DEVICE_BCM5701 0x1645
2396
2397/*
2398 * Sun PCI vendor ID
2399 */
2400#define SUN_VENDORID 0x108e
2401
2402/*
2403 * Fujitsu vendor/device IDs
2404 */
2405#define FJTSU_VENDORID 0x10cf
2406#define FJTSU_DEVICEID_PW008GE5 0x11a1
2407#define FJTSU_DEVICEID_PW008GE4 0x11a2
2408#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */
2409
2410/*
2411 * Offset of MAC address inside EEPROM.
2412 */
2413#define BGE_EE_MAC_OFFSET 0x7C
2414#define BGE_EE_MAC_OFFSET_5906 0x10
2415#define BGE_EE_HWCFG_OFFSET 0xC8
2416
2417#define BGE_HWCFG_VOLTAGE 0x00000003
2418#define BGE_HWCFG_PHYLED_MODE 0x0000000C
2419#define BGE_HWCFG_MEDIA 0x00000030
2420#define BGE_HWCFG_ASF 0x00000080
2421
2422#define BGE_VOLTAGE_1POINT3 0x00000000
2423#define BGE_VOLTAGE_1POINT8 0x00000001
2424
2425#define BGE_PHYLEDMODE_UNSPEC 0x00000000
2426#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2427#define BGE_PHYLEDMODE_SINGLELED 0x00000008
2428
2429#define BGE_MEDIA_UNSPEC 0x00000000
2430#define BGE_MEDIA_COPPER 0x00000010
2431#define BGE_MEDIA_FIBER 0x00000020
2432
2433#define BGE_TICKS_PER_SEC 1000000
2434
2435/*
2436 * Ring size constants.
2437 */
2438#define BGE_EVENT_RING_CNT 256
2439#define BGE_CMD_RING_CNT 64
2440#define BGE_STD_RX_RING_CNT 512
2441#define BGE_JUMBO_RX_RING_CNT 256
2442#define BGE_MINI_RX_RING_CNT 1024
2443#define BGE_RETURN_RING_CNT 1024
2444
2445/* 5705 has smaller return ring size */
2446
2447#define BGE_RETURN_RING_CNT_5705 512
2448
2449/*
2450 * Possible TX ring sizes.
2451 */
2452#define BGE_TX_RING_CNT_128 128
2453#define BGE_TX_RING_BASE_128 0x3800
2454
2455#define BGE_TX_RING_CNT_256 256
2456#define BGE_TX_RING_BASE_256 0x3000
2457
2458#define BGE_TX_RING_CNT_512 512
2459#define BGE_TX_RING_BASE_512 0x2000
2460
2461#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2462#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2463
2464/*
2465 * Tigon III statistics counters.
2466 */
2467/* Statistics maintained MAC Receive block. */
2468struct bge_rx_mac_stats {
2469 bge_hostaddr ifHCInOctets;
2470 bge_hostaddr Reserved1;
2471 bge_hostaddr etherStatsFragments;
2472 bge_hostaddr ifHCInUcastPkts;
2473 bge_hostaddr ifHCInMulticastPkts;
2474 bge_hostaddr ifHCInBroadcastPkts;
2475 bge_hostaddr dot3StatsFCSErrors;
2476 bge_hostaddr dot3StatsAlignmentErrors;
2477 bge_hostaddr xonPauseFramesReceived;
2478 bge_hostaddr xoffPauseFramesReceived;
2479 bge_hostaddr macControlFramesReceived;
2480 bge_hostaddr xoffStateEntered;
2481 bge_hostaddr dot3StatsFramesTooLong;
2482 bge_hostaddr etherStatsJabbers;
2483 bge_hostaddr etherStatsUndersizePkts;
2484 bge_hostaddr inRangeLengthError;
2485 bge_hostaddr outRangeLengthError;
2486 bge_hostaddr etherStatsPkts64Octets;
2487 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2488 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2489 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2490 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2491 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2492 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2493 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2494 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2495 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2496};
2497
2498
2499/* Statistics maintained MAC Transmit block. */
2500struct bge_tx_mac_stats {
2501 bge_hostaddr ifHCOutOctets;
2502 bge_hostaddr Reserved2;
2503 bge_hostaddr etherStatsCollisions;
2504 bge_hostaddr outXonSent;
2505 bge_hostaddr outXoffSent;
2506 bge_hostaddr flowControlDone;
2507 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2508 bge_hostaddr dot3StatsSingleCollisionFrames;
2509 bge_hostaddr dot3StatsMultipleCollisionFrames;
2510 bge_hostaddr dot3StatsDeferredTransmissions;
2511 bge_hostaddr Reserved3;
2512 bge_hostaddr dot3StatsExcessiveCollisions;
2513 bge_hostaddr dot3StatsLateCollisions;
2514 bge_hostaddr dot3Collided2Times;
2515 bge_hostaddr dot3Collided3Times;
2516 bge_hostaddr dot3Collided4Times;
2517 bge_hostaddr dot3Collided5Times;
2518 bge_hostaddr dot3Collided6Times;
2519 bge_hostaddr dot3Collided7Times;
2520 bge_hostaddr dot3Collided8Times;
2521 bge_hostaddr dot3Collided9Times;
2522 bge_hostaddr dot3Collided10Times;
2523 bge_hostaddr dot3Collided11Times;
2524 bge_hostaddr dot3Collided12Times;
2525 bge_hostaddr dot3Collided13Times;
2526 bge_hostaddr dot3Collided14Times;
2527 bge_hostaddr dot3Collided15Times;
2528 bge_hostaddr ifHCOutUcastPkts;
2529 bge_hostaddr ifHCOutMulticastPkts;
2530 bge_hostaddr ifHCOutBroadcastPkts;
2531 bge_hostaddr dot3StatsCarrierSenseErrors;
2532 bge_hostaddr ifOutDiscards;
2533 bge_hostaddr ifOutErrors;
2534};
2535
2536/* Stats counters access through registers */
2537struct bge_mac_stats {
2538 /* TX MAC statistics */
2539 uint64_t ifHCOutOctets;
2540 uint64_t Reserved0;
2541 uint64_t etherStatsCollisions;
2542 uint64_t outXonSent;
2543 uint64_t outXoffSent;
2544 uint64_t Reserved1;
2545 uint64_t dot3StatsInternalMacTransmitErrors;
2546 uint64_t dot3StatsSingleCollisionFrames;
2547 uint64_t dot3StatsMultipleCollisionFrames;
2548 uint64_t dot3StatsDeferredTransmissions;
2549 uint64_t Reserved2;
2550 uint64_t dot3StatsExcessiveCollisions;
2551 uint64_t dot3StatsLateCollisions;
2552 uint64_t Reserved3[14];
2553 uint64_t ifHCOutUcastPkts;
2554 uint64_t ifHCOutMulticastPkts;
2555 uint64_t ifHCOutBroadcastPkts;
2556 uint64_t Reserved4[2];
2557 /* RX MAC statistics */
2558 uint64_t ifHCInOctets;
2559 uint64_t Reserved5;
2560 uint64_t etherStatsFragments;
2561 uint64_t ifHCInUcastPkts;
2562 uint64_t ifHCInMulticastPkts;
2563 uint64_t ifHCInBroadcastPkts;
2564 uint64_t dot3StatsFCSErrors;
2565 uint64_t dot3StatsAlignmentErrors;
2566 uint64_t xonPauseFramesReceived;
2567 uint64_t xoffPauseFramesReceived;
2568 uint64_t macControlFramesReceived;
2569 uint64_t xoffStateEntered;
2570 uint64_t dot3StatsFramesTooLong;
2571 uint64_t etherStatsJabbers;
2572 uint64_t etherStatsUndersizePkts;
2573 /* Receive List Placement control */
2574 uint64_t FramesDroppedDueToFilters;
2575 uint64_t DmaWriteQueueFull;
2576 uint64_t DmaWriteHighPriQueueFull;
2577 uint64_t NoMoreRxBDs;
2578 uint64_t InputDiscards;
2579 uint64_t InputErrors;
2580 uint64_t RecvThresholdHit;
2581};
2582
2583struct bge_stats {
2584 uint8_t Reserved0[256];
2585
2586 /* Statistics maintained by Receive MAC. */
2587 struct bge_rx_mac_stats rxstats;
2588
2589 bge_hostaddr Unused1[37];
2590
2591 /* Statistics maintained by Transmit MAC. */
2592 struct bge_tx_mac_stats txstats;
2593
2594 bge_hostaddr Unused2[31];
2595
2596 /* Statistics maintained by Receive List Placement. */
2597 bge_hostaddr COSIfHCInPkts[16];
2598 bge_hostaddr COSFramesDroppedDueToFilters;
2599 bge_hostaddr nicDmaWriteQueueFull;
2600 bge_hostaddr nicDmaWriteHighPriQueueFull;
2601 bge_hostaddr nicNoMoreRxBDs;
2602 bge_hostaddr ifInDiscards;
2603 bge_hostaddr ifInErrors;
2604 bge_hostaddr nicRecvThresholdHit;
2605
2606 bge_hostaddr Unused3[9];
2607
2608 /* Statistics maintained by Send Data Initiator. */
2609 bge_hostaddr COSIfHCOutPkts[16];
2610 bge_hostaddr nicDmaReadQueueFull;
2611 bge_hostaddr nicDmaReadHighPriQueueFull;
2612 bge_hostaddr nicSendDataCompQueueFull;
2613
2614 /* Statistics maintained by Host Coalescing. */
2615 bge_hostaddr nicRingSetSendProdIndex;
2616 bge_hostaddr nicRingStatusUpdate;
2617 bge_hostaddr nicInterrupts;
2618 bge_hostaddr nicAvoidedInterrupts;
2619 bge_hostaddr nicSendThresholdHit;
2620
2621 uint8_t Reserved4[320];
2622};
2623
2624/*
2625 * Tigon general information block. This resides in host memory
2626 * and contains the status counters, ring control blocks and
2627 * producer pointers.
2628 */
2629
2630struct bge_gib {
2631 struct bge_stats bge_stats;
2632 struct bge_rcb bge_tx_rcb[16];
2633 struct bge_rcb bge_std_rx_rcb;
2634 struct bge_rcb bge_jumbo_rx_rcb;
2635 struct bge_rcb bge_mini_rx_rcb;
2636 struct bge_rcb bge_return_rcb;
2637};
2638
2639#define BGE_FRAMELEN 1518
2640#define BGE_MAX_FRAMELEN 1536
2641#define BGE_JUMBO_FRAMELEN 9018
2642#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2643#define BGE_MIN_FRAMELEN 60
2644
2645/*
2646 * Other utility macros.
2647 */
2648#define BGE_INC(x, y) (x) = (x + 1) % y
2649
2650/*
2651 * Register access macros. The Tigon always uses memory mapped register
2652 * accesses and all registers must be accessed with 32 bit operations.
2653 */
2654
2655#define CSR_WRITE_4(sc, reg, val) \
2656 bus_write_4(sc->bge_res, reg, val)
2657
2658#define CSR_READ_4(sc, reg) \
2659 bus_read_4(sc->bge_res, reg)
2660
2661#define BGE_SETBIT(sc, reg, x) \
2662 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2663#define BGE_CLRBIT(sc, reg, x) \
2664 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2665
2666#define PCI_SETBIT(dev, reg, x, s) \
2667 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2668#define PCI_CLRBIT(dev, reg, x, s) \
2669 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2670
2671/*
2672 * Memory management stuff.
2673 */
2674
2675#define BGE_NSEG_JUMBO 4
2676#define BGE_NSEG_NEW 32
2677#define BGE_TSOSEG_SZ 4096
2678
2679/* Maximum DMA address for controllers that have 40bit DMA address bug. */
2680#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
2681#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR
2682#else
2683#define BGE_DMA_MAXADDR 0xFFFFFFFFFF
2684#endif
2685
2686#ifdef PAE
2687#define BGE_DMA_BNDRY 0x80000000
2688#else
2689#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
2690#define BGE_DMA_BNDRY 0x100000000
2691#else
2692#define BGE_DMA_BNDRY 0
2693#endif
2694#endif
2695
2696/*
2697 * Ring structures. Most of these reside in host memory and we tell
2698 * the NIC where they are via the ring control blocks. The exceptions
2699 * are the tx and command rings, which live in NIC memory and which
2700 * we access via the shared memory window.
2701 */
2702
2703struct bge_ring_data {
2704 struct bge_rx_bd *bge_rx_std_ring;
2705 bus_addr_t bge_rx_std_ring_paddr;
2706 struct bge_extrx_bd *bge_rx_jumbo_ring;
2707 bus_addr_t bge_rx_jumbo_ring_paddr;
2708 struct bge_rx_bd *bge_rx_return_ring;
2709 bus_addr_t bge_rx_return_ring_paddr;
2710 struct bge_tx_bd *bge_tx_ring;
2711 bus_addr_t bge_tx_ring_paddr;
2712 struct bge_status_block *bge_status_block;
2713 bus_addr_t bge_status_block_paddr;
2714 struct bge_stats *bge_stats;
2715 bus_addr_t bge_stats_paddr;
2716 struct bge_gib bge_info;
2717};
2718
2719#define BGE_STD_RX_RING_SZ \
2720 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2721#define BGE_JUMBO_RX_RING_SZ \
2722 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2723#define BGE_TX_RING_SZ \
2724 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2725#define BGE_RX_RTN_RING_SZ(x) \
2726 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2727
2728#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2729
2730#define BGE_STATS_SZ sizeof (struct bge_stats)
2731
2732/*
2733 * Mbuf pointers. We need these to keep track of the virtual addresses
2734 * of our mbuf chains since we can only convert from physical to virtual,
2735 * not the other way around.
2736 */
2737struct bge_chain_data {
2738 bus_dma_tag_t bge_parent_tag;
2739 bus_dma_tag_t bge_buffer_tag;
2740 bus_dma_tag_t bge_rx_std_ring_tag;
2741 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2742 bus_dma_tag_t bge_rx_return_ring_tag;
2743 bus_dma_tag_t bge_tx_ring_tag;
2744 bus_dma_tag_t bge_status_tag;
2745 bus_dma_tag_t bge_stats_tag;
2746 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */
2747 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */
2748 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */
2749 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2750 bus_dmamap_t bge_rx_std_sparemap;
2751 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2752 bus_dmamap_t bge_rx_jumbo_sparemap;
2753 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2754 bus_dmamap_t bge_rx_std_ring_map;
2755 bus_dmamap_t bge_rx_jumbo_ring_map;
2756 bus_dmamap_t bge_tx_ring_map;
2757 bus_dmamap_t bge_rx_return_ring_map;
2758 bus_dmamap_t bge_status_map;
2759 bus_dmamap_t bge_stats_map;
2760 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2761 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2762 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2763 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT];
2764 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4];
2765};
2766
2767struct bge_dmamap_arg {
2768 bus_addr_t bge_busaddr;
2769};
2770
2771#define BGE_HWREV_TIGON 0x01
2772#define BGE_HWREV_TIGON_II 0x02
2773#define BGE_TIMEOUT 100000
2774#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2775
2776struct bge_bcom_hack {
2777 int reg;
2778 int val;
2779};
2780
2781#define ASF_ENABLE 1
2782#define ASF_NEW_HANDSHAKE 2
2783#define ASF_STACKUP 4
2784
2785struct bge_softc {
2786 struct ifnet *bge_ifp; /* interface info */
2787 device_t bge_dev;
2788 struct mtx bge_mtx;
2789 device_t bge_miibus;
2790 void *bge_intrhand;
2791 struct resource *bge_irq;
2792 struct resource *bge_res;
2793 struct ifmedia bge_ifmedia; /* TBI media info */
2794 int bge_expcap;
2795 int bge_msicap;
2796 int bge_pcixcap;
2797 uint32_t bge_flags;
2798#define BGE_FLAG_TBI 0x00000001
2799#define BGE_FLAG_JUMBO 0x00000002
2800#define BGE_FLAG_JUMBO_STD 0x00000004
2801#define BGE_FLAG_EADDR 0x00000008
2802#define BGE_FLAG_MII_SERDES 0x00000010
2803#define BGE_FLAG_CPMU_PRESENT 0x00000020
2804#define BGE_FLAG_TAGGED_STATUS 0x00000040
2805#define BGE_FLAG_MSI 0x00000100
2806#define BGE_FLAG_PCIX 0x00000200
2807#define BGE_FLAG_PCIE 0x00000400
2808#define BGE_FLAG_TSO 0x00000800
2809#define BGE_FLAG_TSO3 0x00001000
2810#define BGE_FLAG_JUMBO_FRAME 0x00002000
2811#define BGE_FLAG_5700_FAMILY 0x00010000
2812#define BGE_FLAG_5705_PLUS 0x00020000
2813#define BGE_FLAG_5714_FAMILY 0x00040000
2814#define BGE_FLAG_575X_PLUS 0x00080000
2815#define BGE_FLAG_5755_PLUS 0x00100000
2816#define BGE_FLAG_5788 0x00200000
2817#define BGE_FLAG_5717_PLUS 0x00400000
2818#define BGE_FLAG_40BIT_BUG 0x01000000
2819#define BGE_FLAG_4G_BNDRY_BUG 0x02000000
2820#define BGE_FLAG_RX_ALIGNBUG 0x04000000
2821#define BGE_FLAG_SHORT_DMA_BUG 0x08000000
2822#define BGE_FLAG_4K_RDMA_BUG 0x10000000
2823 uint32_t bge_phy_flags;
2824#define BGE_PHY_NO_WIRESPEED 0x00000001
2825#define BGE_PHY_ADC_BUG 0x00000002
2826#define BGE_PHY_5704_A0_BUG 0x00000004
2827#define BGE_PHY_JITTER_BUG 0x00000008
2828#define BGE_PHY_BER_BUG 0x00000010
2829#define BGE_PHY_ADJUST_TRIM 0x00000020
2830#define BGE_PHY_CRC_BUG 0x00000040
2831#define BGE_PHY_NO_3LED 0x00000080
2832 uint32_t bge_chipid;
2833 uint32_t bge_asicrev;
2834 uint32_t bge_chiprev;
2835 uint8_t bge_asf_mode;
2836 uint8_t bge_asf_count;
2837 struct bge_ring_data bge_ldata; /* rings */
2838 struct bge_chain_data bge_cdata; /* mbufs */
2839 uint16_t bge_tx_saved_considx;
2840 uint16_t bge_rx_saved_considx;
2841 uint16_t bge_ev_saved_considx;
2842 uint16_t bge_return_ring_cnt;
2843 uint16_t bge_std; /* current std ring head */
2844 uint16_t bge_jumbo; /* current jumo ring head */
2845 uint32_t bge_stat_ticks;
2846 uint32_t bge_rx_coal_ticks;
2847 uint32_t bge_tx_coal_ticks;
2848 uint32_t bge_tx_prodidx;
2849 uint32_t bge_rx_max_coal_bds;
2850 uint32_t bge_tx_max_coal_bds;
2851 uint32_t bge_mi_mode;
2852 int bge_if_flags;
2853 int bge_txcnt;
2854 int bge_link; /* link state */
2855 int bge_link_evt; /* pending link event */
2856 int bge_timer;
2857 int bge_forced_collapse;
2858 int bge_forced_udpcsum;
2859 int bge_csum_features;
2860 struct callout bge_stat_ch;
2861 uint32_t bge_rx_discards;
2862 uint32_t bge_tx_discards;
2863 uint32_t bge_tx_collisions;
2864#ifdef DEVICE_POLLING
2865 int rxcycles;
2866#endif /* DEVICE_POLLING */
2867 struct bge_mac_stats bge_mac_stats;
2868 struct task bge_intr_task;
2869 struct taskqueue *bge_tq;
2870};
2871
2872#define BGE_LOCK_INIT(_sc, _name) \
2873 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2874#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
2875#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2876#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
2877#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)
| 2309#define BCOM_DEVICEID_BCM5721 0x1659
2310#define BCOM_DEVICEID_BCM5722 0x165A
2311#define BCOM_DEVICEID_BCM5723 0x165B
2312#define BCOM_DEVICEID_BCM5750 0x1676
2313#define BCOM_DEVICEID_BCM5750M 0x167C
2314#define BCOM_DEVICEID_BCM5751 0x1677
2315#define BCOM_DEVICEID_BCM5751F 0x167E
2316#define BCOM_DEVICEID_BCM5751M 0x167D
2317#define BCOM_DEVICEID_BCM5752 0x1600
2318#define BCOM_DEVICEID_BCM5752M 0x1601
2319#define BCOM_DEVICEID_BCM5753 0x16F7
2320#define BCOM_DEVICEID_BCM5753F 0x16FE
2321#define BCOM_DEVICEID_BCM5753M 0x16FD
2322#define BCOM_DEVICEID_BCM5754 0x167A
2323#define BCOM_DEVICEID_BCM5754M 0x1672
2324#define BCOM_DEVICEID_BCM5755 0x167B
2325#define BCOM_DEVICEID_BCM5755M 0x1673
2326#define BCOM_DEVICEID_BCM5756 0x1674
2327#define BCOM_DEVICEID_BCM5761 0x1681
2328#define BCOM_DEVICEID_BCM5761E 0x1680
2329#define BCOM_DEVICEID_BCM5761S 0x1688
2330#define BCOM_DEVICEID_BCM5761SE 0x1689
2331#define BCOM_DEVICEID_BCM5764 0x1684
2332#define BCOM_DEVICEID_BCM5780 0x166A
2333#define BCOM_DEVICEID_BCM5780S 0x166B
2334#define BCOM_DEVICEID_BCM5781 0x16DD
2335#define BCOM_DEVICEID_BCM5782 0x1696
2336#define BCOM_DEVICEID_BCM5784 0x1698
2337#define BCOM_DEVICEID_BCM5785F 0x16a0
2338#define BCOM_DEVICEID_BCM5785G 0x1699
2339#define BCOM_DEVICEID_BCM5786 0x169A
2340#define BCOM_DEVICEID_BCM5787 0x169B
2341#define BCOM_DEVICEID_BCM5787M 0x1693
2342#define BCOM_DEVICEID_BCM5787F 0x167f
2343#define BCOM_DEVICEID_BCM5788 0x169C
2344#define BCOM_DEVICEID_BCM5789 0x169D
2345#define BCOM_DEVICEID_BCM5901 0x170D
2346#define BCOM_DEVICEID_BCM5901A2 0x170E
2347#define BCOM_DEVICEID_BCM5903M 0x16FF
2348#define BCOM_DEVICEID_BCM5906 0x1712
2349#define BCOM_DEVICEID_BCM5906M 0x1713
2350#define BCOM_DEVICEID_BCM57760 0x1690
2351#define BCOM_DEVICEID_BCM57761 0x16B0
2352#define BCOM_DEVICEID_BCM57765 0x16B4
2353#define BCOM_DEVICEID_BCM57780 0x1692
2354#define BCOM_DEVICEID_BCM57781 0x16B1
2355#define BCOM_DEVICEID_BCM57785 0x16B5
2356#define BCOM_DEVICEID_BCM57788 0x1691
2357#define BCOM_DEVICEID_BCM57790 0x1694
2358#define BCOM_DEVICEID_BCM57791 0x16B2
2359#define BCOM_DEVICEID_BCM57795 0x16B6
2360
2361/*
2362 * Alteon AceNIC PCI vendor/device ID.
2363 */
2364#define ALTEON_VENDORID 0x12AE
2365#define ALTEON_DEVICEID_ACENIC 0x0001
2366#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002
2367#define ALTEON_DEVICEID_BCM5700 0x0003
2368#define ALTEON_DEVICEID_BCM5701 0x0004
2369
2370/*
2371 * 3Com 3c996 PCI vendor/device ID.
2372 */
2373#define TC_VENDORID 0x10B7
2374#define TC_DEVICEID_3C996 0x0003
2375
2376/*
2377 * SysKonnect PCI vendor ID
2378 */
2379#define SK_VENDORID 0x1148
2380#define SK_DEVICEID_ALTIMA 0x4400
2381#define SK_SUBSYSID_9D21 0x4421
2382#define SK_SUBSYSID_9D41 0x4441
2383
2384/*
2385 * Altima PCI vendor/device ID.
2386 */
2387#define ALTIMA_VENDORID 0x173b
2388#define ALTIMA_DEVICE_AC1000 0x03e8
2389#define ALTIMA_DEVICE_AC1002 0x03e9
2390#define ALTIMA_DEVICE_AC9100 0x03ea
2391
2392/*
2393 * Dell PCI vendor ID
2394 */
2395
2396#define DELL_VENDORID 0x1028
2397
2398/*
2399 * Apple PCI vendor ID.
2400 */
2401#define APPLE_VENDORID 0x106b
2402#define APPLE_DEVICE_BCM5701 0x1645
2403
2404/*
2405 * Sun PCI vendor ID
2406 */
2407#define SUN_VENDORID 0x108e
2408
2409/*
2410 * Fujitsu vendor/device IDs
2411 */
2412#define FJTSU_VENDORID 0x10cf
2413#define FJTSU_DEVICEID_PW008GE5 0x11a1
2414#define FJTSU_DEVICEID_PW008GE4 0x11a2
2415#define FJTSU_DEVICEID_PP250450 0x11cc /* PRIMEPOWER250/450 LAN */
2416
2417/*
2418 * Offset of MAC address inside EEPROM.
2419 */
2420#define BGE_EE_MAC_OFFSET 0x7C
2421#define BGE_EE_MAC_OFFSET_5906 0x10
2422#define BGE_EE_HWCFG_OFFSET 0xC8
2423
2424#define BGE_HWCFG_VOLTAGE 0x00000003
2425#define BGE_HWCFG_PHYLED_MODE 0x0000000C
2426#define BGE_HWCFG_MEDIA 0x00000030
2427#define BGE_HWCFG_ASF 0x00000080
2428
2429#define BGE_VOLTAGE_1POINT3 0x00000000
2430#define BGE_VOLTAGE_1POINT8 0x00000001
2431
2432#define BGE_PHYLEDMODE_UNSPEC 0x00000000
2433#define BGE_PHYLEDMODE_TRIPLELED 0x00000004
2434#define BGE_PHYLEDMODE_SINGLELED 0x00000008
2435
2436#define BGE_MEDIA_UNSPEC 0x00000000
2437#define BGE_MEDIA_COPPER 0x00000010
2438#define BGE_MEDIA_FIBER 0x00000020
2439
2440#define BGE_TICKS_PER_SEC 1000000
2441
2442/*
2443 * Ring size constants.
2444 */
2445#define BGE_EVENT_RING_CNT 256
2446#define BGE_CMD_RING_CNT 64
2447#define BGE_STD_RX_RING_CNT 512
2448#define BGE_JUMBO_RX_RING_CNT 256
2449#define BGE_MINI_RX_RING_CNT 1024
2450#define BGE_RETURN_RING_CNT 1024
2451
2452/* 5705 has smaller return ring size */
2453
2454#define BGE_RETURN_RING_CNT_5705 512
2455
2456/*
2457 * Possible TX ring sizes.
2458 */
2459#define BGE_TX_RING_CNT_128 128
2460#define BGE_TX_RING_BASE_128 0x3800
2461
2462#define BGE_TX_RING_CNT_256 256
2463#define BGE_TX_RING_BASE_256 0x3000
2464
2465#define BGE_TX_RING_CNT_512 512
2466#define BGE_TX_RING_BASE_512 0x2000
2467
2468#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512
2469#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512
2470
2471/*
2472 * Tigon III statistics counters.
2473 */
2474/* Statistics maintained MAC Receive block. */
2475struct bge_rx_mac_stats {
2476 bge_hostaddr ifHCInOctets;
2477 bge_hostaddr Reserved1;
2478 bge_hostaddr etherStatsFragments;
2479 bge_hostaddr ifHCInUcastPkts;
2480 bge_hostaddr ifHCInMulticastPkts;
2481 bge_hostaddr ifHCInBroadcastPkts;
2482 bge_hostaddr dot3StatsFCSErrors;
2483 bge_hostaddr dot3StatsAlignmentErrors;
2484 bge_hostaddr xonPauseFramesReceived;
2485 bge_hostaddr xoffPauseFramesReceived;
2486 bge_hostaddr macControlFramesReceived;
2487 bge_hostaddr xoffStateEntered;
2488 bge_hostaddr dot3StatsFramesTooLong;
2489 bge_hostaddr etherStatsJabbers;
2490 bge_hostaddr etherStatsUndersizePkts;
2491 bge_hostaddr inRangeLengthError;
2492 bge_hostaddr outRangeLengthError;
2493 bge_hostaddr etherStatsPkts64Octets;
2494 bge_hostaddr etherStatsPkts65Octetsto127Octets;
2495 bge_hostaddr etherStatsPkts128Octetsto255Octets;
2496 bge_hostaddr etherStatsPkts256Octetsto511Octets;
2497 bge_hostaddr etherStatsPkts512Octetsto1023Octets;
2498 bge_hostaddr etherStatsPkts1024Octetsto1522Octets;
2499 bge_hostaddr etherStatsPkts1523Octetsto2047Octets;
2500 bge_hostaddr etherStatsPkts2048Octetsto4095Octets;
2501 bge_hostaddr etherStatsPkts4096Octetsto8191Octets;
2502 bge_hostaddr etherStatsPkts8192Octetsto9022Octets;
2503};
2504
2505
2506/* Statistics maintained MAC Transmit block. */
2507struct bge_tx_mac_stats {
2508 bge_hostaddr ifHCOutOctets;
2509 bge_hostaddr Reserved2;
2510 bge_hostaddr etherStatsCollisions;
2511 bge_hostaddr outXonSent;
2512 bge_hostaddr outXoffSent;
2513 bge_hostaddr flowControlDone;
2514 bge_hostaddr dot3StatsInternalMacTransmitErrors;
2515 bge_hostaddr dot3StatsSingleCollisionFrames;
2516 bge_hostaddr dot3StatsMultipleCollisionFrames;
2517 bge_hostaddr dot3StatsDeferredTransmissions;
2518 bge_hostaddr Reserved3;
2519 bge_hostaddr dot3StatsExcessiveCollisions;
2520 bge_hostaddr dot3StatsLateCollisions;
2521 bge_hostaddr dot3Collided2Times;
2522 bge_hostaddr dot3Collided3Times;
2523 bge_hostaddr dot3Collided4Times;
2524 bge_hostaddr dot3Collided5Times;
2525 bge_hostaddr dot3Collided6Times;
2526 bge_hostaddr dot3Collided7Times;
2527 bge_hostaddr dot3Collided8Times;
2528 bge_hostaddr dot3Collided9Times;
2529 bge_hostaddr dot3Collided10Times;
2530 bge_hostaddr dot3Collided11Times;
2531 bge_hostaddr dot3Collided12Times;
2532 bge_hostaddr dot3Collided13Times;
2533 bge_hostaddr dot3Collided14Times;
2534 bge_hostaddr dot3Collided15Times;
2535 bge_hostaddr ifHCOutUcastPkts;
2536 bge_hostaddr ifHCOutMulticastPkts;
2537 bge_hostaddr ifHCOutBroadcastPkts;
2538 bge_hostaddr dot3StatsCarrierSenseErrors;
2539 bge_hostaddr ifOutDiscards;
2540 bge_hostaddr ifOutErrors;
2541};
2542
2543/* Stats counters access through registers */
2544struct bge_mac_stats {
2545 /* TX MAC statistics */
2546 uint64_t ifHCOutOctets;
2547 uint64_t Reserved0;
2548 uint64_t etherStatsCollisions;
2549 uint64_t outXonSent;
2550 uint64_t outXoffSent;
2551 uint64_t Reserved1;
2552 uint64_t dot3StatsInternalMacTransmitErrors;
2553 uint64_t dot3StatsSingleCollisionFrames;
2554 uint64_t dot3StatsMultipleCollisionFrames;
2555 uint64_t dot3StatsDeferredTransmissions;
2556 uint64_t Reserved2;
2557 uint64_t dot3StatsExcessiveCollisions;
2558 uint64_t dot3StatsLateCollisions;
2559 uint64_t Reserved3[14];
2560 uint64_t ifHCOutUcastPkts;
2561 uint64_t ifHCOutMulticastPkts;
2562 uint64_t ifHCOutBroadcastPkts;
2563 uint64_t Reserved4[2];
2564 /* RX MAC statistics */
2565 uint64_t ifHCInOctets;
2566 uint64_t Reserved5;
2567 uint64_t etherStatsFragments;
2568 uint64_t ifHCInUcastPkts;
2569 uint64_t ifHCInMulticastPkts;
2570 uint64_t ifHCInBroadcastPkts;
2571 uint64_t dot3StatsFCSErrors;
2572 uint64_t dot3StatsAlignmentErrors;
2573 uint64_t xonPauseFramesReceived;
2574 uint64_t xoffPauseFramesReceived;
2575 uint64_t macControlFramesReceived;
2576 uint64_t xoffStateEntered;
2577 uint64_t dot3StatsFramesTooLong;
2578 uint64_t etherStatsJabbers;
2579 uint64_t etherStatsUndersizePkts;
2580 /* Receive List Placement control */
2581 uint64_t FramesDroppedDueToFilters;
2582 uint64_t DmaWriteQueueFull;
2583 uint64_t DmaWriteHighPriQueueFull;
2584 uint64_t NoMoreRxBDs;
2585 uint64_t InputDiscards;
2586 uint64_t InputErrors;
2587 uint64_t RecvThresholdHit;
2588};
2589
2590struct bge_stats {
2591 uint8_t Reserved0[256];
2592
2593 /* Statistics maintained by Receive MAC. */
2594 struct bge_rx_mac_stats rxstats;
2595
2596 bge_hostaddr Unused1[37];
2597
2598 /* Statistics maintained by Transmit MAC. */
2599 struct bge_tx_mac_stats txstats;
2600
2601 bge_hostaddr Unused2[31];
2602
2603 /* Statistics maintained by Receive List Placement. */
2604 bge_hostaddr COSIfHCInPkts[16];
2605 bge_hostaddr COSFramesDroppedDueToFilters;
2606 bge_hostaddr nicDmaWriteQueueFull;
2607 bge_hostaddr nicDmaWriteHighPriQueueFull;
2608 bge_hostaddr nicNoMoreRxBDs;
2609 bge_hostaddr ifInDiscards;
2610 bge_hostaddr ifInErrors;
2611 bge_hostaddr nicRecvThresholdHit;
2612
2613 bge_hostaddr Unused3[9];
2614
2615 /* Statistics maintained by Send Data Initiator. */
2616 bge_hostaddr COSIfHCOutPkts[16];
2617 bge_hostaddr nicDmaReadQueueFull;
2618 bge_hostaddr nicDmaReadHighPriQueueFull;
2619 bge_hostaddr nicSendDataCompQueueFull;
2620
2621 /* Statistics maintained by Host Coalescing. */
2622 bge_hostaddr nicRingSetSendProdIndex;
2623 bge_hostaddr nicRingStatusUpdate;
2624 bge_hostaddr nicInterrupts;
2625 bge_hostaddr nicAvoidedInterrupts;
2626 bge_hostaddr nicSendThresholdHit;
2627
2628 uint8_t Reserved4[320];
2629};
2630
2631/*
2632 * Tigon general information block. This resides in host memory
2633 * and contains the status counters, ring control blocks and
2634 * producer pointers.
2635 */
2636
2637struct bge_gib {
2638 struct bge_stats bge_stats;
2639 struct bge_rcb bge_tx_rcb[16];
2640 struct bge_rcb bge_std_rx_rcb;
2641 struct bge_rcb bge_jumbo_rx_rcb;
2642 struct bge_rcb bge_mini_rx_rcb;
2643 struct bge_rcb bge_return_rcb;
2644};
2645
2646#define BGE_FRAMELEN 1518
2647#define BGE_MAX_FRAMELEN 1536
2648#define BGE_JUMBO_FRAMELEN 9018
2649#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
2650#define BGE_MIN_FRAMELEN 60
2651
2652/*
2653 * Other utility macros.
2654 */
2655#define BGE_INC(x, y) (x) = (x + 1) % y
2656
2657/*
2658 * Register access macros. The Tigon always uses memory mapped register
2659 * accesses and all registers must be accessed with 32 bit operations.
2660 */
2661
2662#define CSR_WRITE_4(sc, reg, val) \
2663 bus_write_4(sc->bge_res, reg, val)
2664
2665#define CSR_READ_4(sc, reg) \
2666 bus_read_4(sc->bge_res, reg)
2667
2668#define BGE_SETBIT(sc, reg, x) \
2669 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) | (x)))
2670#define BGE_CLRBIT(sc, reg, x) \
2671 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x)))
2672
2673#define PCI_SETBIT(dev, reg, x, s) \
2674 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
2675#define PCI_CLRBIT(dev, reg, x, s) \
2676 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
2677
2678/*
2679 * Memory management stuff.
2680 */
2681
2682#define BGE_NSEG_JUMBO 4
2683#define BGE_NSEG_NEW 32
2684#define BGE_TSOSEG_SZ 4096
2685
2686/* Maximum DMA address for controllers that have 40bit DMA address bug. */
2687#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF)
2688#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR
2689#else
2690#define BGE_DMA_MAXADDR 0xFFFFFFFFFF
2691#endif
2692
2693#ifdef PAE
2694#define BGE_DMA_BNDRY 0x80000000
2695#else
2696#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
2697#define BGE_DMA_BNDRY 0x100000000
2698#else
2699#define BGE_DMA_BNDRY 0
2700#endif
2701#endif
2702
2703/*
2704 * Ring structures. Most of these reside in host memory and we tell
2705 * the NIC where they are via the ring control blocks. The exceptions
2706 * are the tx and command rings, which live in NIC memory and which
2707 * we access via the shared memory window.
2708 */
2709
2710struct bge_ring_data {
2711 struct bge_rx_bd *bge_rx_std_ring;
2712 bus_addr_t bge_rx_std_ring_paddr;
2713 struct bge_extrx_bd *bge_rx_jumbo_ring;
2714 bus_addr_t bge_rx_jumbo_ring_paddr;
2715 struct bge_rx_bd *bge_rx_return_ring;
2716 bus_addr_t bge_rx_return_ring_paddr;
2717 struct bge_tx_bd *bge_tx_ring;
2718 bus_addr_t bge_tx_ring_paddr;
2719 struct bge_status_block *bge_status_block;
2720 bus_addr_t bge_status_block_paddr;
2721 struct bge_stats *bge_stats;
2722 bus_addr_t bge_stats_paddr;
2723 struct bge_gib bge_info;
2724};
2725
2726#define BGE_STD_RX_RING_SZ \
2727 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT)
2728#define BGE_JUMBO_RX_RING_SZ \
2729 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT)
2730#define BGE_TX_RING_SZ \
2731 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT)
2732#define BGE_RX_RTN_RING_SZ(x) \
2733 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt)
2734
2735#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block)
2736
2737#define BGE_STATS_SZ sizeof (struct bge_stats)
2738
2739/*
2740 * Mbuf pointers. We need these to keep track of the virtual addresses
2741 * of our mbuf chains since we can only convert from physical to virtual,
2742 * not the other way around.
2743 */
2744struct bge_chain_data {
2745 bus_dma_tag_t bge_parent_tag;
2746 bus_dma_tag_t bge_buffer_tag;
2747 bus_dma_tag_t bge_rx_std_ring_tag;
2748 bus_dma_tag_t bge_rx_jumbo_ring_tag;
2749 bus_dma_tag_t bge_rx_return_ring_tag;
2750 bus_dma_tag_t bge_tx_ring_tag;
2751 bus_dma_tag_t bge_status_tag;
2752 bus_dma_tag_t bge_stats_tag;
2753 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag */
2754 bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag */
2755 bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag */
2756 bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT];
2757 bus_dmamap_t bge_rx_std_sparemap;
2758 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT];
2759 bus_dmamap_t bge_rx_jumbo_sparemap;
2760 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT];
2761 bus_dmamap_t bge_rx_std_ring_map;
2762 bus_dmamap_t bge_rx_jumbo_ring_map;
2763 bus_dmamap_t bge_tx_ring_map;
2764 bus_dmamap_t bge_rx_return_ring_map;
2765 bus_dmamap_t bge_status_map;
2766 bus_dmamap_t bge_stats_map;
2767 struct mbuf *bge_tx_chain[BGE_TX_RING_CNT];
2768 struct mbuf *bge_rx_std_chain[BGE_STD_RX_RING_CNT];
2769 struct mbuf *bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT];
2770 int bge_rx_std_seglen[BGE_STD_RX_RING_CNT];
2771 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4];
2772};
2773
2774struct bge_dmamap_arg {
2775 bus_addr_t bge_busaddr;
2776};
2777
2778#define BGE_HWREV_TIGON 0x01
2779#define BGE_HWREV_TIGON_II 0x02
2780#define BGE_TIMEOUT 100000
2781#define BGE_TXCONS_UNSET 0xFFFF /* impossible value */
2782
2783struct bge_bcom_hack {
2784 int reg;
2785 int val;
2786};
2787
2788#define ASF_ENABLE 1
2789#define ASF_NEW_HANDSHAKE 2
2790#define ASF_STACKUP 4
2791
2792struct bge_softc {
2793 struct ifnet *bge_ifp; /* interface info */
2794 device_t bge_dev;
2795 struct mtx bge_mtx;
2796 device_t bge_miibus;
2797 void *bge_intrhand;
2798 struct resource *bge_irq;
2799 struct resource *bge_res;
2800 struct ifmedia bge_ifmedia; /* TBI media info */
2801 int bge_expcap;
2802 int bge_msicap;
2803 int bge_pcixcap;
2804 uint32_t bge_flags;
2805#define BGE_FLAG_TBI 0x00000001
2806#define BGE_FLAG_JUMBO 0x00000002
2807#define BGE_FLAG_JUMBO_STD 0x00000004
2808#define BGE_FLAG_EADDR 0x00000008
2809#define BGE_FLAG_MII_SERDES 0x00000010
2810#define BGE_FLAG_CPMU_PRESENT 0x00000020
2811#define BGE_FLAG_TAGGED_STATUS 0x00000040
2812#define BGE_FLAG_MSI 0x00000100
2813#define BGE_FLAG_PCIX 0x00000200
2814#define BGE_FLAG_PCIE 0x00000400
2815#define BGE_FLAG_TSO 0x00000800
2816#define BGE_FLAG_TSO3 0x00001000
2817#define BGE_FLAG_JUMBO_FRAME 0x00002000
2818#define BGE_FLAG_5700_FAMILY 0x00010000
2819#define BGE_FLAG_5705_PLUS 0x00020000
2820#define BGE_FLAG_5714_FAMILY 0x00040000
2821#define BGE_FLAG_575X_PLUS 0x00080000
2822#define BGE_FLAG_5755_PLUS 0x00100000
2823#define BGE_FLAG_5788 0x00200000
2824#define BGE_FLAG_5717_PLUS 0x00400000
2825#define BGE_FLAG_40BIT_BUG 0x01000000
2826#define BGE_FLAG_4G_BNDRY_BUG 0x02000000
2827#define BGE_FLAG_RX_ALIGNBUG 0x04000000
2828#define BGE_FLAG_SHORT_DMA_BUG 0x08000000
2829#define BGE_FLAG_4K_RDMA_BUG 0x10000000
2830 uint32_t bge_phy_flags;
2831#define BGE_PHY_NO_WIRESPEED 0x00000001
2832#define BGE_PHY_ADC_BUG 0x00000002
2833#define BGE_PHY_5704_A0_BUG 0x00000004
2834#define BGE_PHY_JITTER_BUG 0x00000008
2835#define BGE_PHY_BER_BUG 0x00000010
2836#define BGE_PHY_ADJUST_TRIM 0x00000020
2837#define BGE_PHY_CRC_BUG 0x00000040
2838#define BGE_PHY_NO_3LED 0x00000080
2839 uint32_t bge_chipid;
2840 uint32_t bge_asicrev;
2841 uint32_t bge_chiprev;
2842 uint8_t bge_asf_mode;
2843 uint8_t bge_asf_count;
2844 struct bge_ring_data bge_ldata; /* rings */
2845 struct bge_chain_data bge_cdata; /* mbufs */
2846 uint16_t bge_tx_saved_considx;
2847 uint16_t bge_rx_saved_considx;
2848 uint16_t bge_ev_saved_considx;
2849 uint16_t bge_return_ring_cnt;
2850 uint16_t bge_std; /* current std ring head */
2851 uint16_t bge_jumbo; /* current jumo ring head */
2852 uint32_t bge_stat_ticks;
2853 uint32_t bge_rx_coal_ticks;
2854 uint32_t bge_tx_coal_ticks;
2855 uint32_t bge_tx_prodidx;
2856 uint32_t bge_rx_max_coal_bds;
2857 uint32_t bge_tx_max_coal_bds;
2858 uint32_t bge_mi_mode;
2859 int bge_if_flags;
2860 int bge_txcnt;
2861 int bge_link; /* link state */
2862 int bge_link_evt; /* pending link event */
2863 int bge_timer;
2864 int bge_forced_collapse;
2865 int bge_forced_udpcsum;
2866 int bge_csum_features;
2867 struct callout bge_stat_ch;
2868 uint32_t bge_rx_discards;
2869 uint32_t bge_tx_discards;
2870 uint32_t bge_tx_collisions;
2871#ifdef DEVICE_POLLING
2872 int rxcycles;
2873#endif /* DEVICE_POLLING */
2874 struct bge_mac_stats bge_mac_stats;
2875 struct task bge_intr_task;
2876 struct taskqueue *bge_tq;
2877};
2878
2879#define BGE_LOCK_INIT(_sc, _name) \
2880 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
2881#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx)
2882#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED)
2883#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx)
2884#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)
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