Cross Reference: /freebsd-11.0-release/sys/dev/bge/if_bgereg.h

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1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *	1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 213333 2010-10-01 17:46:15Z yongari $	33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 213411 2010-10-04 18:09:01Z yongari $
34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC 222* 223/* PCI Misc. Host control register / 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234* 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 239 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 240#else 241#define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 243 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 244#endif 245 246#define BGE_INIT \ 247 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250#define BGE_CHIPID_TIGON_I 0x4000 251#define BGE_CHIPID_TIGON_II 0x6000 252#define BGE_CHIPID_BCM5700_A0 0x7000 253#define BGE_CHIPID_BCM5700_A1 0x7001 254#define BGE_CHIPID_BCM5700_B0 0x7100 255#define BGE_CHIPID_BCM5700_B1 0x7101 256#define BGE_CHIPID_BCM5700_B2 0x7102 257#define BGE_CHIPID_BCM5700_B3 0x7103 258#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259#define BGE_CHIPID_BCM5700_C0 0x7200 260#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 261#define BGE_CHIPID_BCM5701_B0 0x0100 262#define BGE_CHIPID_BCM5701_B2 0x0102 263#define BGE_CHIPID_BCM5701_B5 0x0105 264#define BGE_CHIPID_BCM5703_A0 0x1000 265#define BGE_CHIPID_BCM5703_A1 0x1001 266#define BGE_CHIPID_BCM5703_A2 0x1002 267#define BGE_CHIPID_BCM5703_A3 0x1003 268#define BGE_CHIPID_BCM5703_B0 0x1100 269#define BGE_CHIPID_BCM5704_A0 0x2000 270#define BGE_CHIPID_BCM5704_A1 0x2001 271#define BGE_CHIPID_BCM5704_A2 0x2002 272#define BGE_CHIPID_BCM5704_A3 0x2003 273#define BGE_CHIPID_BCM5704_B0 0x2100 274#define BGE_CHIPID_BCM5705_A0 0x3000 275#define BGE_CHIPID_BCM5705_A1 0x3001 276#define BGE_CHIPID_BCM5705_A2 0x3002 277#define BGE_CHIPID_BCM5705_A3 0x3003 278#define BGE_CHIPID_BCM5750_A0 0x4000 279#define BGE_CHIPID_BCM5750_A1 0x4001 280#define BGE_CHIPID_BCM5750_A3 0x4000 281#define BGE_CHIPID_BCM5750_B0 0x4100 282#define BGE_CHIPID_BCM5750_B1 0x4101 283#define BGE_CHIPID_BCM5750_C0 0x4200 284#define BGE_CHIPID_BCM5750_C1 0x4201 285#define BGE_CHIPID_BCM5750_C2 0x4202 286#define BGE_CHIPID_BCM5714_A0 0x5000 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5722_A0 0xa200 299#define BGE_CHIPID_BCM5754_A0 0xb000 300#define BGE_CHIPID_BCM5754_A1 0xb001 301#define BGE_CHIPID_BCM5754_A2 0xb002 302#define BGE_CHIPID_BCM5761_A0 0x5761000 303#define BGE_CHIPID_BCM5761_A1 0x5761100 304#define BGE_CHIPID_BCM5784_A0 0x5784000 305#define BGE_CHIPID_BCM5784_A1 0x5784100 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A1 0xc001 310#define BGE_CHIPID_BCM5906_A2 0xc002 311#define BGE_CHIPID_BCM57780_A0 0x57780000 312#define BGE_CHIPID_BCM57780_A1 0x57780001 313* 314/* shorthand one / 315#define BGE_ASICREV(x) ((x) >> 12) 316#define BGE_ASICREV_BCM5701 0x00 317#define BGE_ASICREV_BCM5703 0x01 318#define BGE_ASICREV_BCM5704 0x02 319#define BGE_ASICREV_BCM5705 0x03 320#define BGE_ASICREV_BCM5750 0x04 321#define BGE_ASICREV_BCM5714_A0 0x05 322#define BGE_ASICREV_BCM5752 0x06 323#define BGE_ASICREV_BCM5700 0x07 324#define BGE_ASICREV_BCM5780 0x08 325#define BGE_ASICREV_BCM5714 0x09 326#define BGE_ASICREV_BCM5755 0x0a 327#define BGE_ASICREV_BCM5754 0x0b 328#define BGE_ASICREV_BCM5787 0x0b 329#define BGE_ASICREV_BCM5906 0x0c 330/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 331#define BGE_ASICREV_USE_PRODID_REG 0x0f 332/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 333#define BGE_ASICREV_BCM5761 0x5761 334#define BGE_ASICREV_BCM5784 0x5784 335#define BGE_ASICREV_BCM5785 0x5785 336#define BGE_ASICREV_BCM57780 0x57780 337* 338/* chip revisions / 339#define BGE_CHIPREV(x) ((x) >> 8) 340#define BGE_CHIPREV_5700_AX 0x70 341#define BGE_CHIPREV_5700_BX 0x71 342#define BGE_CHIPREV_5700_CX 0x72 343#define BGE_CHIPREV_5701_AX 0x00 344#define BGE_CHIPREV_5703_AX 0x10 345#define BGE_CHIPREV_5704_AX 0x20 346#define BGE_CHIPREV_5704_BX 0x21 347#define BGE_CHIPREV_5750_AX 0x40 348#define BGE_CHIPREV_5750_BX 0x41 349/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 350#define BGE_CHIPREV_5761_AX 0x57611 351#define BGE_CHIPREV_5784_AX 0x57841 352* 353/* PCI DMA Read/Write Control register / 354#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 366* 367#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 371 372#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 380 381#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389 390/* 391 * PCI state register -- note, this register is read only 392 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 393 * register is set. 394 / 395#define BGE_PCISTATE_FORCE_RESET 0x00000001 396#define BGE_PCISTATE_INTR_STATE 0x00000002 397#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 398#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 399#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 400#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 404* 405/* 406 * PCI Clock Control register -- note, this register is read only 407 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 408 * register is set. 409 / 410#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411#define BGE_PCICLOCKCTL_M66EN 0x00000080 412#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 420* 421 422#ifndef PCIM_CMD_MWIEN 423#define PCIM_CMD_MWIEN 0x0010 424#endif 425#ifndef PCIM_CMD_INTxDIS 426#define PCIM_CMD_INTxDIS 0x0400 427#endif 428 429/* 430 * High priority mailbox registers 431 * Each mailbox is 64-bits wide, though we only use the 432 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 433 * first. The NIC will load the mailbox after the lower 32 bit word 434 * has been updated. 435 / 436#define BGE_MBX_IRQ0_HI 0x0200 437#define BGE_MBX_IRQ0_LO 0x0204 438#define BGE_MBX_IRQ1_HI 0x0208 439#define BGE_MBX_IRQ1_LO 0x020C 440#define BGE_MBX_IRQ2_HI 0x0210 441#define BGE_MBX_IRQ2_LO 0x0214 442#define BGE_MBX_IRQ3_HI 0x0218 443#define BGE_MBX_IRQ3_LO 0x021C 444#define BGE_MBX_GEN0_HI 0x0220 445#define BGE_MBX_GEN0_LO 0x0224 446#define BGE_MBX_GEN1_HI 0x0228 447#define BGE_MBX_GEN1_LO 0x022C 448#define BGE_MBX_GEN2_HI 0x0230 449#define BGE_MBX_GEN2_LO 0x0234 450#define BGE_MBX_GEN3_HI 0x0228 451#define BGE_MBX_GEN3_LO 0x022C 452#define BGE_MBX_GEN4_HI 0x0240 453#define BGE_MBX_GEN4_LO 0x0244 454#define BGE_MBX_GEN5_HI 0x0248 455#define BGE_MBX_GEN5_LO 0x024C 456#define BGE_MBX_GEN6_HI 0x0250 457#define BGE_MBX_GEN6_LO 0x0254 458#define BGE_MBX_GEN7_HI 0x0258 459#define BGE_MBX_GEN7_LO 0x025C 460#define BGE_MBX_RELOAD_STATS_HI 0x0260 461#define BGE_MBX_RELOAD_STATS_LO 0x0264 462#define BGE_MBX_RX_STD_PROD_HI 0x0268 463#define BGE_MBX_RX_STD_PROD_LO 0x026C 464#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468#define BGE_MBX_RX_CONS0_HI 0x0280 469#define BGE_MBX_RX_CONS0_LO 0x0284 470#define BGE_MBX_RX_CONS1_HI 0x0288 471#define BGE_MBX_RX_CONS1_LO 0x028C 472#define BGE_MBX_RX_CONS2_HI 0x0290 473#define BGE_MBX_RX_CONS2_LO 0x0294 474#define BGE_MBX_RX_CONS3_HI 0x0298 475#define BGE_MBX_RX_CONS3_LO 0x029C 476#define BGE_MBX_RX_CONS4_HI 0x02A0 477#define BGE_MBX_RX_CONS4_LO 0x02A4 478#define BGE_MBX_RX_CONS5_HI 0x02A8 479#define BGE_MBX_RX_CONS5_LO 0x02AC 480#define BGE_MBX_RX_CONS6_HI 0x02B0 481#define BGE_MBX_RX_CONS6_LO 0x02B4 482#define BGE_MBX_RX_CONS7_HI 0x02B8 483#define BGE_MBX_RX_CONS7_LO 0x02BC 484#define BGE_MBX_RX_CONS8_HI 0x02C0 485#define BGE_MBX_RX_CONS8_LO 0x02C4 486#define BGE_MBX_RX_CONS9_HI 0x02C8 487#define BGE_MBX_RX_CONS9_LO 0x02CC 488#define BGE_MBX_RX_CONS10_HI 0x02D0 489#define BGE_MBX_RX_CONS10_LO 0x02D4 490#define BGE_MBX_RX_CONS11_HI 0x02D8 491#define BGE_MBX_RX_CONS11_LO 0x02DC 492#define BGE_MBX_RX_CONS12_HI 0x02E0 493#define BGE_MBX_RX_CONS12_LO 0x02E4 494#define BGE_MBX_RX_CONS13_HI 0x02E8 495#define BGE_MBX_RX_CONS13_LO 0x02EC 496#define BGE_MBX_RX_CONS14_HI 0x02F0 497#define BGE_MBX_RX_CONS14_LO 0x02F4 498#define BGE_MBX_RX_CONS15_HI 0x02F8 499#define BGE_MBX_RX_CONS15_LO 0x02FC 500#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 564* 565#define BGE_TX_RINGS_MAX 4 566#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567#define BGE_RX_RINGS_MAX 16 568 569/* Ethernet MAC control registers / 570#define BGE_MAC_MODE 0x0400 571#define BGE_MAC_STS 0x0404 572#define BGE_MAC_EVT_ENB 0x0408 573#define BGE_MAC_LED_CTL 0x040C 574#define BGE_MAC_ADDR1_LO 0x0410 575#define BGE_MAC_ADDR1_HI 0x0414 576#define BGE_MAC_ADDR2_LO 0x0418 577#define BGE_MAC_ADDR2_HI 0x041C 578#define BGE_MAC_ADDR3_LO 0x0420 579#define BGE_MAC_ADDR3_HI 0x0424 580#define BGE_MAC_ADDR4_LO 0x0428 581#define BGE_MAC_ADDR4_HI 0x042C 582#define BGE_WOL_PATPTR 0x0430 583#define BGE_WOL_PATCFG 0x0434 584#define BGE_TX_RANDOM_BACKOFF 0x0438 585#define BGE_RX_MTU 0x043C 586#define BGE_GBIT_PCS_TEST 0x0440 587#define BGE_TX_TBI_AUTONEG 0x0444 588#define BGE_RX_TBI_AUTONEG 0x0448 589#define BGE_MI_COMM 0x044C 590#define BGE_MI_STS 0x0450 591#define BGE_MI_MODE 0x0454 592#define BGE_AUTOPOLL_STS 0x0458 593#define BGE_TX_MODE 0x045C 594#define BGE_TX_STS 0x0460 595#define BGE_TX_LENGTHS 0x0464 596#define BGE_RX_MODE 0x0468 597#define BGE_RX_STS 0x046C 598#define BGE_MAR0 0x0470 599#define BGE_MAR1 0x0474 600#define BGE_MAR2 0x0478 601#define BGE_MAR3 0x047C 602#define BGE_RX_BD_RULES_CTL0 0x0480 603#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604#define BGE_RX_BD_RULES_CTL1 0x0488 605#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606#define BGE_RX_BD_RULES_CTL2 0x0490 607#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608#define BGE_RX_BD_RULES_CTL3 0x0498 609#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610#define BGE_RX_BD_RULES_CTL4 0x04A0 611#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612#define BGE_RX_BD_RULES_CTL5 0x04A8 613#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614#define BGE_RX_BD_RULES_CTL6 0x04B0 615#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616#define BGE_RX_BD_RULES_CTL7 0x04B8 617#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618#define BGE_RX_BD_RULES_CTL8 0x04C0 619#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620#define BGE_RX_BD_RULES_CTL9 0x04C8 621#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622#define BGE_RX_BD_RULES_CTL10 0x04D0 623#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624#define BGE_RX_BD_RULES_CTL11 0x04D8 625#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626#define BGE_RX_BD_RULES_CTL12 0x04E0 627#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628#define BGE_RX_BD_RULES_CTL13 0x04E8 629#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630#define BGE_RX_BD_RULES_CTL14 0x04F0 631#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632#define BGE_RX_BD_RULES_CTL15 0x04F8 633#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634#define BGE_RX_RULES_CFG 0x0500 635#define BGE_MAX_RX_FRAME_LOWAT 0x0504 636#define BGE_SERDES_CFG 0x0590 637#define BGE_SERDES_STS 0x0594 638#define BGE_SGDIG_CFG 0x05B0 639#define BGE_SGDIG_STS 0x05B4 640#define BGE_TX_MAC_STATS_OCTETS 0x0800 641#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 642#define BGE_TX_MAC_STATS_COLLS 0x0808 643#define BGE_TX_MAC_STATS_XON_SENT 0x080C 644#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 645#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 646#define BGE_TX_MAC_STATS_ERRORS 0x0818 647#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 648#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 649#define BGE_TX_MAC_STATS_DEFERRED 0x0824 650#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 651#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 652#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 653#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 654#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 655#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 656#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 657#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 658#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 659#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 660#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 661#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 662#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 663#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 664#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 665#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 666#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 667#define BGE_TX_MAC_STATS_UCAST 0x086C 668#define BGE_TX_MAC_STATS_MCAST 0x0870 669#define BGE_TX_MAC_STATS_BCAST 0x0874 670#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 671#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 672#define BGE_RX_MAC_STATS_OCTESTS 0x0880 673#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 674#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 675#define BGE_RX_MAC_STATS_UCAST 0x088C 676#define BGE_RX_MAC_STATS_MCAST 0x0890 677#define BGE_RX_MAC_STATS_BCAST 0x0894 678#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 679#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 680#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 681#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 682#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 683#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 684#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 685#define BGE_RX_MAC_STATS_JABBERS 0x08B4 686#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 687* 688/* Ethernet MAC Mode register / 689#define BGE_MACMODE_RESET 0x00000001 690#define BGE_MACMODE_HALF_DUPLEX 0x00000002 691#define BGE_MACMODE_PORTMODE 0x0000000C 692#define BGE_MACMODE_LOOPBACK 0x00000010 693#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 694#define BGE_MACMODE_TX_BURST_ENB 0x00000100 695#define BGE_MACMODE_MAX_DEFER 0x00000200 696#define BGE_MACMODE_LINK_POLARITY 0x00000400 697#define BGE_MACMODE_RX_STATS_ENB 0x00000800 698#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 699#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 700#define BGE_MACMODE_TX_STATS_ENB 0x00004000 701#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 702#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 703#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 704#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 705#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 706#define BGE_MACMODE_MIP_ENB 0x00100000 707#define BGE_MACMODE_TXDMA_ENB 0x00200000 708#define BGE_MACMODE_RXDMA_ENB 0x00400000 709#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 710* 711#define BGE_PORTMODE_NONE 0x00000000 712#define BGE_PORTMODE_MII 0x00000004 713#define BGE_PORTMODE_GMII 0x00000008 714#define BGE_PORTMODE_TBI 0x0000000C 715 716/* MAC Status register / 717#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 718#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 719#define BGE_MACSTAT_RX_CFG 0x00000004 720#define BGE_MACSTAT_CFG_CHANGED 0x00000008 721#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 722#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 723#define BGE_MACSTAT_LINK_CHANGED 0x00001000 724#define BGE_MACSTAT_MI_COMPLETE 0x00400000 725#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 726#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 727#define BGE_MACSTAT_ODI_ERROR 0x02000000 728#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 729#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 730* 731/* MAC Event Enable Register / 732#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 733#define BGE_EVTENB_LINK_CHANGED 0x00001000 734#define BGE_EVTENB_MI_COMPLETE 0x00400000 735#define BGE_EVTENB_MI_INTERRUPT 0x00800000 736#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 737#define BGE_EVTENB_ODI_ERROR 0x02000000 738#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 739#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 740* 741/* LED Control Register / 742#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 743#define BGE_LEDCTL_1000MBPS_LED 0x00000002 744#define BGE_LEDCTL_100MBPS_LED 0x00000004 745#define BGE_LEDCTL_10MBPS_LED 0x00000008 746#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 747#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 748#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 749#define BGE_LEDCTL_1000MBPS_STS 0x00000080 750#define BGE_LEDCTL_100MBPS_STS 0x00000100 751#define BGE_LEDCTL_10MBPS_STS 0x00000200 752#define BGE_LEDCTL_TRADLED_STS 0x00000400 753#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 754#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 755* 756/* TX backoff seed register / 757#define BGE_TX_BACKOFF_SEED_MASK 0x3F 758* 759/* Autopoll status register / 760#define BGE_AUTOPOLLSTS_ERROR 0x00000001 761* 762/* Transmit MAC mode register / 763#define BGE_TXMODE_RESET 0x00000001 764#define BGE_TXMODE_ENABLE 0x00000002 765#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 766#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 767#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 768* 769/* Transmit MAC status register / 770#define BGE_TXSTAT_RX_XOFFED 0x00000001 771#define BGE_TXSTAT_SENT_XOFF 0x00000002 772#define BGE_TXSTAT_SENT_XON 0x00000004 773#define BGE_TXSTAT_LINK_UP 0x00000008 774#define BGE_TXSTAT_ODI_UFLOW 0x00000010 775#define BGE_TXSTAT_ODI_OFLOW 0x00000020 776* 777/* Transmit MAC lengths register / 778#define BGE_TXLEN_SLOTTIME 0x000000FF 779#define BGE_TXLEN_IPG 0x00000F00 780#define BGE_TXLEN_CRS 0x00003000 781* 782/* Receive MAC mode register / 783#define BGE_RXMODE_RESET 0x00000001 784#define BGE_RXMODE_ENABLE 0x00000002 785#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 786#define BGE_RXMODE_RX_GIANTS 0x00000020 787#define BGE_RXMODE_RX_RUNTS 0x00000040 788#define BGE_RXMODE_8022_LENCHECK 0x00000080 789#define BGE_RXMODE_RX_PROMISC 0x00000100 790#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 791#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 792* 793/* Receive MAC status register / 794#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 795#define BGE_RXSTAT_RCVD_XOFF 0x00000002 796#define BGE_RXSTAT_RCVD_XON 0x00000004 797* 798/* Receive Rules Control register / 799#define BGE_RXRULECTL_OFFSET 0x000000FF 800#define BGE_RXRULECTL_CLASS 0x00001F00 801#define BGE_RXRULECTL_HDRTYPE 0x0000E000 802#define BGE_RXRULECTL_COMPARE_OP 0x00030000 803#define BGE_RXRULECTL_MAP 0x01000000 804#define BGE_RXRULECTL_DISCARD 0x02000000 805#define BGE_RXRULECTL_MASK 0x04000000 806#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 807#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 808#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 809#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 810* 811/* Receive Rules Mask register / 812#define BGE_RXRULEMASK_VALUE 0x0000FFFF 813#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 814* 815/* SERDES configuration register / 816#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 817#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 818#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 819#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 820#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 821#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 822#define BGE_SERDESCFG_TXMODE 0x00001000 823#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 824#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 825#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 826#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 827#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 828#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 829#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 830#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 831#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 832* 833/* SERDES status register / 834#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 835#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 836* 837/* SGDIG config (not documented) / 838#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 839#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 840#define BGE_SGDIGCFG_SEND 0x40000000 841#define BGE_SGDIGCFG_AUTO 0x80000000 842* 843/* SGDIG status (not documented) / 844#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 845#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 846#define BGE_SGDIGSTS_DONE 0x00000002 847* 848 849/* MI communication register / 850#define BGE_MICOMM_DATA 0x0000FFFF 851#define BGE_MICOMM_REG 0x001F0000 852#define BGE_MICOMM_PHY 0x03E00000 853#define BGE_MICOMM_CMD 0x0C000000 854#define BGE_MICOMM_READFAIL 0x10000000 855#define BGE_MICOMM_BUSY 0x20000000 856* 857#define BGE_MIREG(x) ((x & 0x1F) << 16) 858#define BGE_MIPHY(x) ((x & 0x1F) << 21) 859#define BGE_MICMD_WRITE 0x04000000 860#define BGE_MICMD_READ 0x08000000 861 862/* MI status register / 863#define BGE_MISTS_LINK 0x00000001 864#define BGE_MISTS_10MBPS 0x00000002 865* 866#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 867#define BGE_MIMODE_AUTOPOLL 0x00000010 868#define BGE_MIMODE_CLKCNT 0x001F0000 869 870 871/* 872 * Send data initiator control registers. 873 / 874#define BGE_SDI_MODE 0x0C00 875#define BGE_SDI_STATUS 0x0C04 876#define BGE_SDI_STATS_CTL 0x0C08 877#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 878#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 879#define BGE_LOCSTATS_COS0 0x0C80 880#define BGE_LOCSTATS_COS1 0x0C84 881#define BGE_LOCSTATS_COS2 0x0C88 882#define BGE_LOCSTATS_COS3 0x0C8C 883#define BGE_LOCSTATS_COS4 0x0C90 884#define BGE_LOCSTATS_COS5 0x0C84 885#define BGE_LOCSTATS_COS6 0x0C98 886#define BGE_LOCSTATS_COS7 0x0C9C 887#define BGE_LOCSTATS_COS8 0x0CA0 888#define BGE_LOCSTATS_COS9 0x0CA4 889#define BGE_LOCSTATS_COS10 0x0CA8 890#define BGE_LOCSTATS_COS11 0x0CAC 891#define BGE_LOCSTATS_COS12 0x0CB0 892#define BGE_LOCSTATS_COS13 0x0CB4 893#define BGE_LOCSTATS_COS14 0x0CB8 894#define BGE_LOCSTATS_COS15 0x0CBC 895#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 896#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 897#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 898#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 899#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 900#define BGE_LOCSTATS_IRQS 0x0CD4 901#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 902#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 903* 904/* Send Data Initiator mode register / 905#define BGE_SDIMODE_RESET 0x00000001 906#define BGE_SDIMODE_ENABLE 0x00000002 907#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 908* 909/* Send Data Initiator stats register / 910#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 911* 912/* Send Data Initiator stats control register / 913#define BGE_SDISTATSCTL_ENABLE 0x00000001 914#define BGE_SDISTATSCTL_FASTER 0x00000002 915#define BGE_SDISTATSCTL_CLEAR 0x00000004 916#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 917#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 918* 919/* 920 * Send Data Completion Control registers 921 / 922#define BGE_SDC_MODE 0x1000 923#define BGE_SDC_STATUS 0x1004 924* 925/* Send Data completion mode register / 926#define BGE_SDCMODE_RESET 0x00000001 927#define BGE_SDCMODE_ENABLE 0x00000002 928#define BGE_SDCMODE_ATTN 0x00000004 929#define BGE_SDCMODE_CDELAY 0x00000010 930* 931/* Send Data completion status register / 932#define BGE_SDCSTAT_ATTN 0x00000004 933* 934/* 935 * Send BD Ring Selector Control registers 936 / 937#define BGE_SRS_MODE 0x1400 938#define BGE_SRS_STATUS 0x1404 939#define BGE_SRS_HWDIAG 0x1408 940#define BGE_SRS_LOC_NIC_CONS0 0x1440 941#define BGE_SRS_LOC_NIC_CONS1 0x1444 942#define BGE_SRS_LOC_NIC_CONS2 0x1448 943#define BGE_SRS_LOC_NIC_CONS3 0x144C 944#define BGE_SRS_LOC_NIC_CONS4 0x1450 945#define BGE_SRS_LOC_NIC_CONS5 0x1454 946#define BGE_SRS_LOC_NIC_CONS6 0x1458 947#define BGE_SRS_LOC_NIC_CONS7 0x145C 948#define BGE_SRS_LOC_NIC_CONS8 0x1460 949#define BGE_SRS_LOC_NIC_CONS9 0x1464 950#define BGE_SRS_LOC_NIC_CONS10 0x1468 951#define BGE_SRS_LOC_NIC_CONS11 0x146C 952#define BGE_SRS_LOC_NIC_CONS12 0x1470 953#define BGE_SRS_LOC_NIC_CONS13 0x1474 954#define BGE_SRS_LOC_NIC_CONS14 0x1478 955#define BGE_SRS_LOC_NIC_CONS15 0x147C 956* 957/* Send BD Ring Selector Mode register / 958#define BGE_SRSMODE_RESET 0x00000001 959#define BGE_SRSMODE_ENABLE 0x00000002 960#define BGE_SRSMODE_ATTN 0x00000004 961* 962/* Send BD Ring Selector Status register / 963#define BGE_SRSSTAT_ERROR 0x00000004 964* 965/* Send BD Ring Selector HW Diagnostics register / 966#define BGE_SRSHWDIAG_STATE 0x0000000F 967#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 968#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 969#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 970* 971/* 972 * Send BD Initiator Selector Control registers 973 / 974#define BGE_SBDI_MODE 0x1800 975#define BGE_SBDI_STATUS 0x1804 976#define BGE_SBDI_LOC_NIC_PROD0 0x1808 977#define BGE_SBDI_LOC_NIC_PROD1 0x180C 978#define BGE_SBDI_LOC_NIC_PROD2 0x1810 979#define BGE_SBDI_LOC_NIC_PROD3 0x1814 980#define BGE_SBDI_LOC_NIC_PROD4 0x1818 981#define BGE_SBDI_LOC_NIC_PROD5 0x181C 982#define BGE_SBDI_LOC_NIC_PROD6 0x1820 983#define BGE_SBDI_LOC_NIC_PROD7 0x1824 984#define BGE_SBDI_LOC_NIC_PROD8 0x1828 985#define BGE_SBDI_LOC_NIC_PROD9 0x182C 986#define BGE_SBDI_LOC_NIC_PROD10 0x1830 987#define BGE_SBDI_LOC_NIC_PROD11 0x1834 988#define BGE_SBDI_LOC_NIC_PROD12 0x1838 989#define BGE_SBDI_LOC_NIC_PROD13 0x183C 990#define BGE_SBDI_LOC_NIC_PROD14 0x1840 991#define BGE_SBDI_LOC_NIC_PROD15 0x1844 992* 993/* Send BD Initiator Mode register / 994#define BGE_SBDIMODE_RESET 0x00000001 995#define BGE_SBDIMODE_ENABLE 0x00000002 996#define BGE_SBDIMODE_ATTN 0x00000004 997* 998/* Send BD Initiator Status register / 999#define BGE_SBDISTAT_ERROR 0x00000004 1000* 1001/* 1002 * Send BD Completion Control registers 1003 / 1004#define BGE_SBDC_MODE 0x1C00 1005#define BGE_SBDC_STATUS 0x1C04 1006* 1007/* Send BD Completion Control Mode register / 1008#define BGE_SBDCMODE_RESET 0x00000001 1009#define BGE_SBDCMODE_ENABLE 0x00000002 1010#define BGE_SBDCMODE_ATTN 0x00000004 1011* 1012/* Send BD Completion Control Status register / 1013#define BGE_SBDCSTAT_ATTN 0x00000004 1014* 1015/* 1016 * Receive List Placement Control registers 1017 / 1018#define BGE_RXLP_MODE 0x2000 1019#define BGE_RXLP_STATUS 0x2004 1020#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1021#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1022#define BGE_RXLP_CFG 0x2010 1023#define BGE_RXLP_STATS_CTL 0x2014 1024#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1025#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1026#define BGE_RXLP_HEAD0 0x2100 1027#define BGE_RXLP_TAIL0 0x2104 1028#define BGE_RXLP_COUNT0 0x2108 1029#define BGE_RXLP_HEAD1 0x2110 1030#define BGE_RXLP_TAIL1 0x2114 1031#define BGE_RXLP_COUNT1 0x2118 1032#define BGE_RXLP_HEAD2 0x2120 1033#define BGE_RXLP_TAIL2 0x2124 1034#define BGE_RXLP_COUNT2 0x2128 1035#define BGE_RXLP_HEAD3 0x2130 1036#define BGE_RXLP_TAIL3 0x2134 1037#define BGE_RXLP_COUNT3 0x2138 1038#define BGE_RXLP_HEAD4 0x2140 1039#define BGE_RXLP_TAIL4 0x2144 1040#define BGE_RXLP_COUNT4 0x2148 1041#define BGE_RXLP_HEAD5 0x2150 1042#define BGE_RXLP_TAIL5 0x2154 1043#define BGE_RXLP_COUNT5 0x2158 1044#define BGE_RXLP_HEAD6 0x2160 1045#define BGE_RXLP_TAIL6 0x2164 1046#define BGE_RXLP_COUNT6 0x2168 1047#define BGE_RXLP_HEAD7 0x2170 1048#define BGE_RXLP_TAIL7 0x2174 1049#define BGE_RXLP_COUNT7 0x2178 1050#define BGE_RXLP_HEAD8 0x2180 1051#define BGE_RXLP_TAIL8 0x2184 1052#define BGE_RXLP_COUNT8 0x2188 1053#define BGE_RXLP_HEAD9 0x2190 1054#define BGE_RXLP_TAIL9 0x2194 1055#define BGE_RXLP_COUNT9 0x2198 1056#define BGE_RXLP_HEAD10 0x21A0 1057#define BGE_RXLP_TAIL10 0x21A4 1058#define BGE_RXLP_COUNT10 0x21A8 1059#define BGE_RXLP_HEAD11 0x21B0 1060#define BGE_RXLP_TAIL11 0x21B4 1061#define BGE_RXLP_COUNT11 0x21B8 1062#define BGE_RXLP_HEAD12 0x21C0 1063#define BGE_RXLP_TAIL12 0x21C4 1064#define BGE_RXLP_COUNT12 0x21C8 1065#define BGE_RXLP_HEAD13 0x21D0 1066#define BGE_RXLP_TAIL13 0x21D4 1067#define BGE_RXLP_COUNT13 0x21D8 1068#define BGE_RXLP_HEAD14 0x21E0 1069#define BGE_RXLP_TAIL14 0x21E4 1070#define BGE_RXLP_COUNT14 0x21E8 1071#define BGE_RXLP_HEAD15 0x21F0 1072#define BGE_RXLP_TAIL15 0x21F4 1073#define BGE_RXLP_COUNT15 0x21F8 1074#define BGE_RXLP_LOCSTAT_COS0 0x2200 1075#define BGE_RXLP_LOCSTAT_COS1 0x2204 1076#define BGE_RXLP_LOCSTAT_COS2 0x2208 1077#define BGE_RXLP_LOCSTAT_COS3 0x220C 1078#define BGE_RXLP_LOCSTAT_COS4 0x2210 1079#define BGE_RXLP_LOCSTAT_COS5 0x2214 1080#define BGE_RXLP_LOCSTAT_COS6 0x2218 1081#define BGE_RXLP_LOCSTAT_COS7 0x221C 1082#define BGE_RXLP_LOCSTAT_COS8 0x2220 1083#define BGE_RXLP_LOCSTAT_COS9 0x2224 1084#define BGE_RXLP_LOCSTAT_COS10 0x2228 1085#define BGE_RXLP_LOCSTAT_COS11 0x222C 1086#define BGE_RXLP_LOCSTAT_COS12 0x2230 1087#define BGE_RXLP_LOCSTAT_COS13 0x2234 1088#define BGE_RXLP_LOCSTAT_COS14 0x2238 1089#define BGE_RXLP_LOCSTAT_COS15 0x223C 1090#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1091#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1092#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1093#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1094#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1095#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1096#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1097* 1098 1099/* Receive List Placement mode register / 1100#define BGE_RXLPMODE_RESET 0x00000001 1101#define BGE_RXLPMODE_ENABLE 0x00000002 1102#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1103#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1104#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1105* 1106/* Receive List Placement Status register / 1107#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1108#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1109#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1110* 1111/* 1112 * Receive Data and Receive BD Initiator Control Registers 1113 / 1114#define BGE_RDBDI_MODE 0x2400 1115#define BGE_RDBDI_STATUS 0x2404 1116#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1117#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1118#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1119#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1120#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1121#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1122#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1123#define BGE_RX_STD_RCB_NICADDR 0x245C 1124#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1125#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1126#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1127#define BGE_RX_MINI_RCB_NICADDR 0x246C 1128#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1129#define BGE_RDBDI_STD_RX_CONS 0x2474 1130#define BGE_RDBDI_MINI_RX_CONS 0x2478 1131#define BGE_RDBDI_RETURN_PROD0 0x2480 1132#define BGE_RDBDI_RETURN_PROD1 0x2484 1133#define BGE_RDBDI_RETURN_PROD2 0x2488 1134#define BGE_RDBDI_RETURN_PROD3 0x248C 1135#define BGE_RDBDI_RETURN_PROD4 0x2490 1136#define BGE_RDBDI_RETURN_PROD5 0x2494 1137#define BGE_RDBDI_RETURN_PROD6 0x2498 1138#define BGE_RDBDI_RETURN_PROD7 0x249C 1139#define BGE_RDBDI_RETURN_PROD8 0x24A0 1140#define BGE_RDBDI_RETURN_PROD9 0x24A4 1141#define BGE_RDBDI_RETURN_PROD10 0x24A8 1142#define BGE_RDBDI_RETURN_PROD11 0x24AC 1143#define BGE_RDBDI_RETURN_PROD12 0x24B0 1144#define BGE_RDBDI_RETURN_PROD13 0x24B4 1145#define BGE_RDBDI_RETURN_PROD14 0x24B8 1146#define BGE_RDBDI_RETURN_PROD15 0x24BC 1147#define BGE_RDBDI_HWDIAG 0x24C0 1148* 1149 1150/* Receive Data and Receive BD Initiator Mode register / 1151#define BGE_RDBDIMODE_RESET 0x00000001 1152#define BGE_RDBDIMODE_ENABLE 0x00000002 1153#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1154#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1155#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1156* 1157/* Receive Data and Receive BD Initiator Status register / 1158#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1159#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1160#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1161* 1162 1163/* 1164 * Receive Data Completion Control registers 1165 / 1166#define BGE_RDC_MODE 0x2800 1167* 1168/* Receive Data Completion Mode register / 1169#define BGE_RDCMODE_RESET 0x00000001 1170#define BGE_RDCMODE_ENABLE 0x00000002 1171#define BGE_RDCMODE_ATTN 0x00000004 1172* 1173/* 1174 * Receive BD Initiator Control registers 1175 / 1176#define BGE_RBDI_MODE 0x2C00 1177#define BGE_RBDI_STATUS 0x2C04 1178#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1179#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1180#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1181#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1182#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1183#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1184* 1185/* Receive BD Initiator Mode register / 1186#define BGE_RBDIMODE_RESET 0x00000001 1187#define BGE_RBDIMODE_ENABLE 0x00000002 1188#define BGE_RBDIMODE_ATTN 0x00000004 1189* 1190/* Receive BD Initiator Status register / 1191#define BGE_RBDISTAT_ATTN 0x00000004 1192* 1193/* 1194 * Receive BD Completion Control registers 1195 / 1196#define BGE_RBDC_MODE 0x3000 1197#define BGE_RBDC_STATUS 0x3004 1198#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1199#define BGE_RBDC_STD_BD_PROD 0x300C 1200#define BGE_RBDC_MINI_BD_PROD 0x3010 1201* 1202/* Receive BD completion mode register / 1203#define BGE_RBDCMODE_RESET 0x00000001 1204#define BGE_RBDCMODE_ENABLE 0x00000002 1205#define BGE_RBDCMODE_ATTN 0x00000004 1206* 1207/* Receive BD completion status register / 1208#define BGE_RBDCSTAT_ERROR 0x00000004 1209* 1210/* 1211 * Receive List Selector Control registers 1212 / 1213#define BGE_RXLS_MODE 0x3400 1214#define BGE_RXLS_STATUS 0x3404 1215* 1216/* Receive List Selector Mode register / 1217#define BGE_RXLSMODE_RESET 0x00000001 1218#define BGE_RXLSMODE_ENABLE 0x00000002 1219#define BGE_RXLSMODE_ATTN 0x00000004 1220* 1221/* Receive List Selector Status register / 1222#define BGE_RXLSSTAT_ERROR 0x00000004 1223* 1224/* 1225 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1226 / 1227#define BGE_MBCF_MODE 0x3800 1228#define BGE_MBCF_STATUS 0x3804 1229* 1230/* Mbuf Cluster Free mode register / 1231#define BGE_MBCFMODE_RESET 0x00000001 1232#define BGE_MBCFMODE_ENABLE 0x00000002 1233#define BGE_MBCFMODE_ATTN 0x00000004 1234* 1235/* Mbuf Cluster Free status register / 1236#define BGE_MBCFSTAT_ERROR 0x00000004 1237* 1238/* 1239 * Host Coalescing Control registers 1240 / 1241#define BGE_HCC_MODE 0x3C00 1242#define BGE_HCC_STATUS 0x3C04 1243#define BGE_HCC_RX_COAL_TICKS 0x3C08 1244#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1245#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1246#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1247#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1248#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1249#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1250#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1251#define BGE_HCC_STATS_TICKS 0x3C28 1252#define BGE_HCC_STATS_ADDR_HI 0x3C30 1253#define BGE_HCC_STATS_ADDR_LO 0x3C34 1254#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1255#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1256#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1257#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1258#define BGE_FLOW_ATTN 0x3C48 1259#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1260#define BGE_HCC_STD_BD_CONS 0x3C54 1261#define BGE_HCC_MINI_BD_CONS 0x3C58 1262#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1263#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1264#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1265#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1266#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1267#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1268#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1269#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1270#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1271#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1272#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1273#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1274#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1275#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1276#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1277#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1278#define BGE_HCC_TX_BD_CONS0 0x3CC0 1279#define BGE_HCC_TX_BD_CONS1 0x3CC4 1280#define BGE_HCC_TX_BD_CONS2 0x3CC8 1281#define BGE_HCC_TX_BD_CONS3 0x3CCC 1282#define BGE_HCC_TX_BD_CONS4 0x3CD0 1283#define BGE_HCC_TX_BD_CONS5 0x3CD4 1284#define BGE_HCC_TX_BD_CONS6 0x3CD8 1285#define BGE_HCC_TX_BD_CONS7 0x3CDC 1286#define BGE_HCC_TX_BD_CONS8 0x3CE0 1287#define BGE_HCC_TX_BD_CONS9 0x3CE4 1288#define BGE_HCC_TX_BD_CONS10 0x3CE8 1289#define BGE_HCC_TX_BD_CONS11 0x3CEC 1290#define BGE_HCC_TX_BD_CONS12 0x3CF0 1291#define BGE_HCC_TX_BD_CONS13 0x3CF4 1292#define BGE_HCC_TX_BD_CONS14 0x3CF8 1293#define BGE_HCC_TX_BD_CONS15 0x3CFC 1294* 1295 1296/* Host coalescing mode register / 1297#define BGE_HCCMODE_RESET 0x00000001 1298#define BGE_HCCMODE_ENABLE 0x00000002 1299#define BGE_HCCMODE_ATTN 0x00000004 1300#define BGE_HCCMODE_COAL_NOW 0x00000008 1301#define BGE_HCCMODE_MSI_BITS 0x00000070 1302#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1303* 1304#define BGE_STATBLKSZ_FULL 0x00000000 1305#define BGE_STATBLKSZ_64BYTE 0x00000080 1306#define BGE_STATBLKSZ_32BYTE 0x00000100 1307 1308/* Host coalescing status register / 1309#define BGE_HCCSTAT_ERROR 0x00000004 1310* 1311/* Flow attention register / 1312#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1313#define BGE_FLOWATTN_MEMARB 0x00000080 1314#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1315#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1316#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1317#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1318#define BGE_FLOWATTN_RDBDI 0x00080000 1319#define BGE_FLOWATTN_RXLS 0x00100000 1320#define BGE_FLOWATTN_RXLP 0x00200000 1321#define BGE_FLOWATTN_RBDC 0x00400000 1322#define BGE_FLOWATTN_RBDI 0x00800000 1323#define BGE_FLOWATTN_SDC 0x08000000 1324#define BGE_FLOWATTN_SDI 0x10000000 1325#define BGE_FLOWATTN_SRS 0x20000000 1326#define BGE_FLOWATTN_SBDC 0x40000000 1327#define BGE_FLOWATTN_SBDI 0x80000000 1328* 1329/* 1330 * Memory arbiter registers 1331 / 1332#define BGE_MARB_MODE 0x4000 1333#define BGE_MARB_STATUS 0x4004 1334#define BGE_MARB_TRAPADDR_HI 0x4008 1335#define BGE_MARB_TRAPADDR_LO 0x400C 1336* 1337/* Memory arbiter mode register / 1338#define BGE_MARBMODE_RESET 0x00000001 1339#define BGE_MARBMODE_ENABLE 0x00000002 1340#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1341#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1342#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1343#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1344#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1345#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1346#define BGE_MARBMODE_PCI_TRAP 0x00000100 1347#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1348#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1349#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1350#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1351#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1352#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1353#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1354#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1355#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1356#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1357#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1358#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1359#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1360#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1361#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1362#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1363#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1364* 1365/* Memory arbiter status register / 1366#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1367#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1368#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1369#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1370#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1371#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1372#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1373#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1374#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1375#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1376#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1377#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1378#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1379#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1380#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1381#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1382#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1383#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1384#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1385#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1386#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1387#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1388#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1389#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1390* 1391/* 1392 * Buffer manager control registers 1393 / 1394#define BGE_BMAN_MODE 0x4400 1395#define BGE_BMAN_STATUS 0x4404 1396#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1397#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1398#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1399#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1400#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1401#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1402#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1403#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1404#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1405#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1406#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1407#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1408#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1409#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1410#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1411#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1412#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1413#define BGE_BMAN_HWDIAG_1 0x444C 1414#define BGE_BMAN_HWDIAG_2 0x4450 1415#define BGE_BMAN_HWDIAG_3 0x4454 1416* 1417/* Buffer manager mode register / 1418#define BGE_BMANMODE_RESET 0x00000001 1419#define BGE_BMANMODE_ENABLE 0x00000002 1420#define BGE_BMANMODE_ATTN 0x00000004 1421#define BGE_BMANMODE_TESTMODE 0x00000008 1422#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1423* 1424/* Buffer manager status register / 1425#define BGE_BMANSTAT_ERRO 0x00000004 1426#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1427* 1428 1429/* 1430 * Read DMA Control registers 1431 / 1432#define BGE_RDMA_MODE 0x4800 1433*#define BGE_RDMA_STATUS 0x4804	34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221#define BGE_PCI_PRODID_ASICREV 0xBC 222* 223/* PCI Misc. Host control register / 224#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 225#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 226#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 227#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 228#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 229#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 230#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 231#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 232#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 233#define BGE_PCIMISCCTL_ASICREV_SHIFT 16 234* 235#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 236#if BYTE_ORDER == LITTLE_ENDIAN 237#define BGE_DMA_SWAP_OPTIONS \ 238 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 239 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 240#else 241#define BGE_DMA_SWAP_OPTIONS \ 242 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 243 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 244#endif 245 246#define BGE_INIT \ 247 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 248 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 249 250#define BGE_CHIPID_TIGON_I 0x4000 251#define BGE_CHIPID_TIGON_II 0x6000 252#define BGE_CHIPID_BCM5700_A0 0x7000 253#define BGE_CHIPID_BCM5700_A1 0x7001 254#define BGE_CHIPID_BCM5700_B0 0x7100 255#define BGE_CHIPID_BCM5700_B1 0x7101 256#define BGE_CHIPID_BCM5700_B2 0x7102 257#define BGE_CHIPID_BCM5700_B3 0x7103 258#define BGE_CHIPID_BCM5700_ALTIMA 0x7104 259#define BGE_CHIPID_BCM5700_C0 0x7200 260#define BGE_CHIPID_BCM5701_A0 0x0000 /* grrrr / 261#define BGE_CHIPID_BCM5701_B0 0x0100 262#define BGE_CHIPID_BCM5701_B2 0x0102 263#define BGE_CHIPID_BCM5701_B5 0x0105 264#define BGE_CHIPID_BCM5703_A0 0x1000 265#define BGE_CHIPID_BCM5703_A1 0x1001 266#define BGE_CHIPID_BCM5703_A2 0x1002 267#define BGE_CHIPID_BCM5703_A3 0x1003 268#define BGE_CHIPID_BCM5703_B0 0x1100 269#define BGE_CHIPID_BCM5704_A0 0x2000 270#define BGE_CHIPID_BCM5704_A1 0x2001 271#define BGE_CHIPID_BCM5704_A2 0x2002 272#define BGE_CHIPID_BCM5704_A3 0x2003 273#define BGE_CHIPID_BCM5704_B0 0x2100 274#define BGE_CHIPID_BCM5705_A0 0x3000 275#define BGE_CHIPID_BCM5705_A1 0x3001 276#define BGE_CHIPID_BCM5705_A2 0x3002 277#define BGE_CHIPID_BCM5705_A3 0x3003 278#define BGE_CHIPID_BCM5750_A0 0x4000 279#define BGE_CHIPID_BCM5750_A1 0x4001 280#define BGE_CHIPID_BCM5750_A3 0x4000 281#define BGE_CHIPID_BCM5750_B0 0x4100 282#define BGE_CHIPID_BCM5750_B1 0x4101 283#define BGE_CHIPID_BCM5750_C0 0x4200 284#define BGE_CHIPID_BCM5750_C1 0x4201 285#define BGE_CHIPID_BCM5750_C2 0x4202 286#define BGE_CHIPID_BCM5714_A0 0x5000 287#define BGE_CHIPID_BCM5752_A0 0x6000 288#define BGE_CHIPID_BCM5752_A1 0x6001 289#define BGE_CHIPID_BCM5752_A2 0x6002 290#define BGE_CHIPID_BCM5714_B0 0x8000 291#define BGE_CHIPID_BCM5714_B3 0x8003 292#define BGE_CHIPID_BCM5715_A0 0x9000 293#define BGE_CHIPID_BCM5715_A1 0x9001 294#define BGE_CHIPID_BCM5715_A3 0x9003 295#define BGE_CHIPID_BCM5755_A0 0xa000 296#define BGE_CHIPID_BCM5755_A1 0xa001 297#define BGE_CHIPID_BCM5755_A2 0xa002 298#define BGE_CHIPID_BCM5722_A0 0xa200 299#define BGE_CHIPID_BCM5754_A0 0xb000 300#define BGE_CHIPID_BCM5754_A1 0xb001 301#define BGE_CHIPID_BCM5754_A2 0xb002 302#define BGE_CHIPID_BCM5761_A0 0x5761000 303#define BGE_CHIPID_BCM5761_A1 0x5761100 304#define BGE_CHIPID_BCM5784_A0 0x5784000 305#define BGE_CHIPID_BCM5784_A1 0x5784100 306#define BGE_CHIPID_BCM5787_A0 0xb000 307#define BGE_CHIPID_BCM5787_A1 0xb001 308#define BGE_CHIPID_BCM5787_A2 0xb002 309#define BGE_CHIPID_BCM5906_A1 0xc001 310#define BGE_CHIPID_BCM5906_A2 0xc002 311#define BGE_CHIPID_BCM57780_A0 0x57780000 312#define BGE_CHIPID_BCM57780_A1 0x57780001 313* 314/* shorthand one / 315#define BGE_ASICREV(x) ((x) >> 12) 316#define BGE_ASICREV_BCM5701 0x00 317#define BGE_ASICREV_BCM5703 0x01 318#define BGE_ASICREV_BCM5704 0x02 319#define BGE_ASICREV_BCM5705 0x03 320#define BGE_ASICREV_BCM5750 0x04 321#define BGE_ASICREV_BCM5714_A0 0x05 322#define BGE_ASICREV_BCM5752 0x06 323#define BGE_ASICREV_BCM5700 0x07 324#define BGE_ASICREV_BCM5780 0x08 325#define BGE_ASICREV_BCM5714 0x09 326#define BGE_ASICREV_BCM5755 0x0a 327#define BGE_ASICREV_BCM5754 0x0b 328#define BGE_ASICREV_BCM5787 0x0b 329#define BGE_ASICREV_BCM5906 0x0c 330/ Should consult BGE_PCI_PRODID_ASICREV for ChipID / 331#define BGE_ASICREV_USE_PRODID_REG 0x0f 332/ BGE_PCI_PRODID_ASICREV ASIC rev. identifiers. / 333#define BGE_ASICREV_BCM5761 0x5761 334#define BGE_ASICREV_BCM5784 0x5784 335#define BGE_ASICREV_BCM5785 0x5785 336#define BGE_ASICREV_BCM57780 0x57780 337* 338/* chip revisions / 339#define BGE_CHIPREV(x) ((x) >> 8) 340#define BGE_CHIPREV_5700_AX 0x70 341#define BGE_CHIPREV_5700_BX 0x71 342#define BGE_CHIPREV_5700_CX 0x72 343#define BGE_CHIPREV_5701_AX 0x00 344#define BGE_CHIPREV_5703_AX 0x10 345#define BGE_CHIPREV_5704_AX 0x20 346#define BGE_CHIPREV_5704_BX 0x21 347#define BGE_CHIPREV_5750_AX 0x40 348#define BGE_CHIPREV_5750_BX 0x41 349/ BGE_PCI_PRODID_ASICREV chip rev. identifiers. / 350#define BGE_CHIPREV_5761_AX 0x57611 351#define BGE_CHIPREV_5784_AX 0x57841 352* 353/* PCI DMA Read/Write Control register / 354#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 355#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 356#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 357#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 358#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 359#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 360#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 361#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 362#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 363#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 364#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 365#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 366* 367#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 368#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 369#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 370#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 371 372#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 373#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 374#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 375#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 376#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 377#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 378#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 379#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 380 381#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 382#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 383#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 384#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 385#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 386#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 387#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 388#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 389 390/* 391 * PCI state register -- note, this register is read only 392 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 393 * register is set. 394 / 395#define BGE_PCISTATE_FORCE_RESET 0x00000001 396#define BGE_PCISTATE_INTR_STATE 0x00000002 397#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 398#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 399#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 400#define BGE_PCISTATE_WANT_EXPROM 0x00000020 401#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 402#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 403#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 404* 405/* 406 * PCI Clock Control register -- note, this register is read only 407 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 408 * register is set. 409 / 410#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 411#define BGE_PCICLOCKCTL_M66EN 0x00000080 412#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 413#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 414#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 415#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 416#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 417#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 418#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 419#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 420* 421 422#ifndef PCIM_CMD_MWIEN 423#define PCIM_CMD_MWIEN 0x0010 424#endif 425#ifndef PCIM_CMD_INTxDIS 426#define PCIM_CMD_INTxDIS 0x0400 427#endif 428 429/* 430 * High priority mailbox registers 431 * Each mailbox is 64-bits wide, though we only use the 432 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 433 * first. The NIC will load the mailbox after the lower 32 bit word 434 * has been updated. 435 / 436#define BGE_MBX_IRQ0_HI 0x0200 437#define BGE_MBX_IRQ0_LO 0x0204 438#define BGE_MBX_IRQ1_HI 0x0208 439#define BGE_MBX_IRQ1_LO 0x020C 440#define BGE_MBX_IRQ2_HI 0x0210 441#define BGE_MBX_IRQ2_LO 0x0214 442#define BGE_MBX_IRQ3_HI 0x0218 443#define BGE_MBX_IRQ3_LO 0x021C 444#define BGE_MBX_GEN0_HI 0x0220 445#define BGE_MBX_GEN0_LO 0x0224 446#define BGE_MBX_GEN1_HI 0x0228 447#define BGE_MBX_GEN1_LO 0x022C 448#define BGE_MBX_GEN2_HI 0x0230 449#define BGE_MBX_GEN2_LO 0x0234 450#define BGE_MBX_GEN3_HI 0x0228 451#define BGE_MBX_GEN3_LO 0x022C 452#define BGE_MBX_GEN4_HI 0x0240 453#define BGE_MBX_GEN4_LO 0x0244 454#define BGE_MBX_GEN5_HI 0x0248 455#define BGE_MBX_GEN5_LO 0x024C 456#define BGE_MBX_GEN6_HI 0x0250 457#define BGE_MBX_GEN6_LO 0x0254 458#define BGE_MBX_GEN7_HI 0x0258 459#define BGE_MBX_GEN7_LO 0x025C 460#define BGE_MBX_RELOAD_STATS_HI 0x0260 461#define BGE_MBX_RELOAD_STATS_LO 0x0264 462#define BGE_MBX_RX_STD_PROD_HI 0x0268 463#define BGE_MBX_RX_STD_PROD_LO 0x026C 464#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 465#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 466#define BGE_MBX_RX_MINI_PROD_HI 0x0278 467#define BGE_MBX_RX_MINI_PROD_LO 0x027C 468#define BGE_MBX_RX_CONS0_HI 0x0280 469#define BGE_MBX_RX_CONS0_LO 0x0284 470#define BGE_MBX_RX_CONS1_HI 0x0288 471#define BGE_MBX_RX_CONS1_LO 0x028C 472#define BGE_MBX_RX_CONS2_HI 0x0290 473#define BGE_MBX_RX_CONS2_LO 0x0294 474#define BGE_MBX_RX_CONS3_HI 0x0298 475#define BGE_MBX_RX_CONS3_LO 0x029C 476#define BGE_MBX_RX_CONS4_HI 0x02A0 477#define BGE_MBX_RX_CONS4_LO 0x02A4 478#define BGE_MBX_RX_CONS5_HI 0x02A8 479#define BGE_MBX_RX_CONS5_LO 0x02AC 480#define BGE_MBX_RX_CONS6_HI 0x02B0 481#define BGE_MBX_RX_CONS6_LO 0x02B4 482#define BGE_MBX_RX_CONS7_HI 0x02B8 483#define BGE_MBX_RX_CONS7_LO 0x02BC 484#define BGE_MBX_RX_CONS8_HI 0x02C0 485#define BGE_MBX_RX_CONS8_LO 0x02C4 486#define BGE_MBX_RX_CONS9_HI 0x02C8 487#define BGE_MBX_RX_CONS9_LO 0x02CC 488#define BGE_MBX_RX_CONS10_HI 0x02D0 489#define BGE_MBX_RX_CONS10_LO 0x02D4 490#define BGE_MBX_RX_CONS11_HI 0x02D8 491#define BGE_MBX_RX_CONS11_LO 0x02DC 492#define BGE_MBX_RX_CONS12_HI 0x02E0 493#define BGE_MBX_RX_CONS12_LO 0x02E4 494#define BGE_MBX_RX_CONS13_HI 0x02E8 495#define BGE_MBX_RX_CONS13_LO 0x02EC 496#define BGE_MBX_RX_CONS14_HI 0x02F0 497#define BGE_MBX_RX_CONS14_LO 0x02F4 498#define BGE_MBX_RX_CONS15_HI 0x02F8 499#define BGE_MBX_RX_CONS15_LO 0x02FC 500#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 501#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 502#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 503#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 504#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 505#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 506#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 507#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 508#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 509#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 510#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 511#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 512#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 513#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 514#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 515#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 516#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 517#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 518#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 519#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 520#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 521#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 522#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 523#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 524#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 525#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 526#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 527#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 528#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 529#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 530#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 531#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 532#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 533#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 534#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 535#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 536#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 537#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 538#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 539#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 540#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 541#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 542#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 543#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 544#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 545#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 546#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 547#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 548#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 549#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 550#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 551#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 552#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 553#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 554#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 555#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 556#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 557#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 558#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 559#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 560#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 561#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 562#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 563#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 564* 565#define BGE_TX_RINGS_MAX 4 566#define BGE_TX_RINGS_EXTSSRAM_MAX 16 567#define BGE_RX_RINGS_MAX 16 568 569/* Ethernet MAC control registers / 570#define BGE_MAC_MODE 0x0400 571#define BGE_MAC_STS 0x0404 572#define BGE_MAC_EVT_ENB 0x0408 573#define BGE_MAC_LED_CTL 0x040C 574#define BGE_MAC_ADDR1_LO 0x0410 575#define BGE_MAC_ADDR1_HI 0x0414 576#define BGE_MAC_ADDR2_LO 0x0418 577#define BGE_MAC_ADDR2_HI 0x041C 578#define BGE_MAC_ADDR3_LO 0x0420 579#define BGE_MAC_ADDR3_HI 0x0424 580#define BGE_MAC_ADDR4_LO 0x0428 581#define BGE_MAC_ADDR4_HI 0x042C 582#define BGE_WOL_PATPTR 0x0430 583#define BGE_WOL_PATCFG 0x0434 584#define BGE_TX_RANDOM_BACKOFF 0x0438 585#define BGE_RX_MTU 0x043C 586#define BGE_GBIT_PCS_TEST 0x0440 587#define BGE_TX_TBI_AUTONEG 0x0444 588#define BGE_RX_TBI_AUTONEG 0x0448 589#define BGE_MI_COMM 0x044C 590#define BGE_MI_STS 0x0450 591#define BGE_MI_MODE 0x0454 592#define BGE_AUTOPOLL_STS 0x0458 593#define BGE_TX_MODE 0x045C 594#define BGE_TX_STS 0x0460 595#define BGE_TX_LENGTHS 0x0464 596#define BGE_RX_MODE 0x0468 597#define BGE_RX_STS 0x046C 598#define BGE_MAR0 0x0470 599#define BGE_MAR1 0x0474 600#define BGE_MAR2 0x0478 601#define BGE_MAR3 0x047C 602#define BGE_RX_BD_RULES_CTL0 0x0480 603#define BGE_RX_BD_RULES_MASKVAL0 0x0484 604#define BGE_RX_BD_RULES_CTL1 0x0488 605#define BGE_RX_BD_RULES_MASKVAL1 0x048C 606#define BGE_RX_BD_RULES_CTL2 0x0490 607#define BGE_RX_BD_RULES_MASKVAL2 0x0494 608#define BGE_RX_BD_RULES_CTL3 0x0498 609#define BGE_RX_BD_RULES_MASKVAL3 0x049C 610#define BGE_RX_BD_RULES_CTL4 0x04A0 611#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 612#define BGE_RX_BD_RULES_CTL5 0x04A8 613#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 614#define BGE_RX_BD_RULES_CTL6 0x04B0 615#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 616#define BGE_RX_BD_RULES_CTL7 0x04B8 617#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 618#define BGE_RX_BD_RULES_CTL8 0x04C0 619#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 620#define BGE_RX_BD_RULES_CTL9 0x04C8 621#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 622#define BGE_RX_BD_RULES_CTL10 0x04D0 623#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 624#define BGE_RX_BD_RULES_CTL11 0x04D8 625#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 626#define BGE_RX_BD_RULES_CTL12 0x04E0 627#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 628#define BGE_RX_BD_RULES_CTL13 0x04E8 629#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 630#define BGE_RX_BD_RULES_CTL14 0x04F0 631#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 632#define BGE_RX_BD_RULES_CTL15 0x04F8 633#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 634#define BGE_RX_RULES_CFG 0x0500 635#define BGE_MAX_RX_FRAME_LOWAT 0x0504 636#define BGE_SERDES_CFG 0x0590 637#define BGE_SERDES_STS 0x0594 638#define BGE_SGDIG_CFG 0x05B0 639#define BGE_SGDIG_STS 0x05B4 640#define BGE_TX_MAC_STATS_OCTETS 0x0800 641#define BGE_TX_MAC_STATS_RESERVE_0 0x0804 642#define BGE_TX_MAC_STATS_COLLS 0x0808 643#define BGE_TX_MAC_STATS_XON_SENT 0x080C 644#define BGE_TX_MAC_STATS_XOFF_SENT 0x0810 645#define BGE_TX_MAC_STATS_RESERVE_1 0x0814 646#define BGE_TX_MAC_STATS_ERRORS 0x0818 647#define BGE_TX_MAC_STATS_SINGLE_COLL 0x081C 648#define BGE_TX_MAC_STATS_MULTI_COLL 0x0820 649#define BGE_TX_MAC_STATS_DEFERRED 0x0824 650#define BGE_TX_MAC_STATS_RESERVE_2 0x0828 651#define BGE_TX_MAC_STATS_EXCESS_COLL 0x082C 652#define BGE_TX_MAC_STATS_LATE_COLL 0x0830 653#define BGE_TX_MAC_STATS_RESERVE_3 0x0834 654#define BGE_TX_MAC_STATS_RESERVE_4 0x0838 655#define BGE_TX_MAC_STATS_RESERVE_5 0x083C 656#define BGE_TX_MAC_STATS_RESERVE_6 0x0840 657#define BGE_TX_MAC_STATS_RESERVE_7 0x0844 658#define BGE_TX_MAC_STATS_RESERVE_8 0x0848 659#define BGE_TX_MAC_STATS_RESERVE_9 0x084C 660#define BGE_TX_MAC_STATS_RESERVE_10 0x0850 661#define BGE_TX_MAC_STATS_RESERVE_11 0x0854 662#define BGE_TX_MAC_STATS_RESERVE_12 0x0858 663#define BGE_TX_MAC_STATS_RESERVE_13 0x085C 664#define BGE_TX_MAC_STATS_RESERVE_14 0x0860 665#define BGE_TX_MAC_STATS_RESERVE_15 0x0864 666#define BGE_TX_MAC_STATS_RESERVE_16 0x0868 667#define BGE_TX_MAC_STATS_UCAST 0x086C 668#define BGE_TX_MAC_STATS_MCAST 0x0870 669#define BGE_TX_MAC_STATS_BCAST 0x0874 670#define BGE_TX_MAC_STATS_RESERVE_17 0x0878 671#define BGE_TX_MAC_STATS_RESERVE_18 0x087C 672#define BGE_RX_MAC_STATS_OCTESTS 0x0880 673#define BGE_RX_MAC_STATS_RESERVE_0 0x0884 674#define BGE_RX_MAC_STATS_FRAGMENTS 0x0888 675#define BGE_RX_MAC_STATS_UCAST 0x088C 676#define BGE_RX_MAC_STATS_MCAST 0x0890 677#define BGE_RX_MAC_STATS_BCAST 0x0894 678#define BGE_RX_MAC_STATS_FCS_ERRORS 0x0898 679#define BGE_RX_MAC_STATS_ALGIN_ERRORS 0x089C 680#define BGE_RX_MAC_STATS_XON_RCVD 0x08A0 681#define BGE_RX_MAC_STATS_XOFF_RCVD 0x08A4 682#define BGE_RX_MAC_STATS_CTRL_RCVD 0x08A8 683#define BGE_RX_MAC_STATS_XOFF_ENTERED 0x08AC 684#define BGE_RX_MAC_STATS_FRAME_TOO_LONG 0x08B0 685#define BGE_RX_MAC_STATS_JABBERS 0x08B4 686#define BGE_RX_MAC_STATS_UNDERSIZE 0x08B8 687* 688/* Ethernet MAC Mode register / 689#define BGE_MACMODE_RESET 0x00000001 690#define BGE_MACMODE_HALF_DUPLEX 0x00000002 691#define BGE_MACMODE_PORTMODE 0x0000000C 692#define BGE_MACMODE_LOOPBACK 0x00000010 693#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 694#define BGE_MACMODE_TX_BURST_ENB 0x00000100 695#define BGE_MACMODE_MAX_DEFER 0x00000200 696#define BGE_MACMODE_LINK_POLARITY 0x00000400 697#define BGE_MACMODE_RX_STATS_ENB 0x00000800 698#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 699#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 700#define BGE_MACMODE_TX_STATS_ENB 0x00004000 701#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 702#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 703#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 704#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 705#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 706#define BGE_MACMODE_MIP_ENB 0x00100000 707#define BGE_MACMODE_TXDMA_ENB 0x00200000 708#define BGE_MACMODE_RXDMA_ENB 0x00400000 709#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 710* 711#define BGE_PORTMODE_NONE 0x00000000 712#define BGE_PORTMODE_MII 0x00000004 713#define BGE_PORTMODE_GMII 0x00000008 714#define BGE_PORTMODE_TBI 0x0000000C 715 716/* MAC Status register / 717#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 718#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 719#define BGE_MACSTAT_RX_CFG 0x00000004 720#define BGE_MACSTAT_CFG_CHANGED 0x00000008 721#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 722#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 723#define BGE_MACSTAT_LINK_CHANGED 0x00001000 724#define BGE_MACSTAT_MI_COMPLETE 0x00400000 725#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 726#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 727#define BGE_MACSTAT_ODI_ERROR 0x02000000 728#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 729#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 730* 731/* MAC Event Enable Register / 732#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 733#define BGE_EVTENB_LINK_CHANGED 0x00001000 734#define BGE_EVTENB_MI_COMPLETE 0x00400000 735#define BGE_EVTENB_MI_INTERRUPT 0x00800000 736#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 737#define BGE_EVTENB_ODI_ERROR 0x02000000 738#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 739#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 740* 741/* LED Control Register / 742#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 743#define BGE_LEDCTL_1000MBPS_LED 0x00000002 744#define BGE_LEDCTL_100MBPS_LED 0x00000004 745#define BGE_LEDCTL_10MBPS_LED 0x00000008 746#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 747#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 748#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 749#define BGE_LEDCTL_1000MBPS_STS 0x00000080 750#define BGE_LEDCTL_100MBPS_STS 0x00000100 751#define BGE_LEDCTL_10MBPS_STS 0x00000200 752#define BGE_LEDCTL_TRADLED_STS 0x00000400 753#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 754#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 755* 756/* TX backoff seed register / 757#define BGE_TX_BACKOFF_SEED_MASK 0x3F 758* 759/* Autopoll status register / 760#define BGE_AUTOPOLLSTS_ERROR 0x00000001 761* 762/* Transmit MAC mode register / 763#define BGE_TXMODE_RESET 0x00000001 764#define BGE_TXMODE_ENABLE 0x00000002 765#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 766#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 767#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 768* 769/* Transmit MAC status register / 770#define BGE_TXSTAT_RX_XOFFED 0x00000001 771#define BGE_TXSTAT_SENT_XOFF 0x00000002 772#define BGE_TXSTAT_SENT_XON 0x00000004 773#define BGE_TXSTAT_LINK_UP 0x00000008 774#define BGE_TXSTAT_ODI_UFLOW 0x00000010 775#define BGE_TXSTAT_ODI_OFLOW 0x00000020 776* 777/* Transmit MAC lengths register / 778#define BGE_TXLEN_SLOTTIME 0x000000FF 779#define BGE_TXLEN_IPG 0x00000F00 780#define BGE_TXLEN_CRS 0x00003000 781* 782/* Receive MAC mode register / 783#define BGE_RXMODE_RESET 0x00000001 784#define BGE_RXMODE_ENABLE 0x00000002 785#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 786#define BGE_RXMODE_RX_GIANTS 0x00000020 787#define BGE_RXMODE_RX_RUNTS 0x00000040 788#define BGE_RXMODE_8022_LENCHECK 0x00000080 789#define BGE_RXMODE_RX_PROMISC 0x00000100 790#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 791#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 792* 793/* Receive MAC status register / 794#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 795#define BGE_RXSTAT_RCVD_XOFF 0x00000002 796#define BGE_RXSTAT_RCVD_XON 0x00000004 797* 798/* Receive Rules Control register / 799#define BGE_RXRULECTL_OFFSET 0x000000FF 800#define BGE_RXRULECTL_CLASS 0x00001F00 801#define BGE_RXRULECTL_HDRTYPE 0x0000E000 802#define BGE_RXRULECTL_COMPARE_OP 0x00030000 803#define BGE_RXRULECTL_MAP 0x01000000 804#define BGE_RXRULECTL_DISCARD 0x02000000 805#define BGE_RXRULECTL_MASK 0x04000000 806#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 807#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 808#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 809#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 810* 811/* Receive Rules Mask register / 812#define BGE_RXRULEMASK_VALUE 0x0000FFFF 813#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 814* 815/* SERDES configuration register / 816#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 817#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 818#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 819#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 820#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 821#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 822#define BGE_SERDESCFG_TXMODE 0x00001000 823#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 824#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 825#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 826#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 827#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 828#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 829#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 830#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 831#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 832* 833/* SERDES status register / 834#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 835#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 836* 837/* SGDIG config (not documented) / 838#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 839#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 840#define BGE_SGDIGCFG_SEND 0x40000000 841#define BGE_SGDIGCFG_AUTO 0x80000000 842* 843/* SGDIG status (not documented) / 844#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 845#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 846#define BGE_SGDIGSTS_DONE 0x00000002 847* 848 849/* MI communication register / 850#define BGE_MICOMM_DATA 0x0000FFFF 851#define BGE_MICOMM_REG 0x001F0000 852#define BGE_MICOMM_PHY 0x03E00000 853#define BGE_MICOMM_CMD 0x0C000000 854#define BGE_MICOMM_READFAIL 0x10000000 855#define BGE_MICOMM_BUSY 0x20000000 856* 857#define BGE_MIREG(x) ((x & 0x1F) << 16) 858#define BGE_MIPHY(x) ((x & 0x1F) << 21) 859#define BGE_MICMD_WRITE 0x04000000 860#define BGE_MICMD_READ 0x08000000 861 862/* MI status register / 863#define BGE_MISTS_LINK 0x00000001 864#define BGE_MISTS_10MBPS 0x00000002 865* 866#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 867#define BGE_MIMODE_AUTOPOLL 0x00000010 868#define BGE_MIMODE_CLKCNT 0x001F0000 869 870 871/* 872 * Send data initiator control registers. 873 / 874#define BGE_SDI_MODE 0x0C00 875#define BGE_SDI_STATUS 0x0C04 876#define BGE_SDI_STATS_CTL 0x0C08 877#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 878#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 879#define BGE_LOCSTATS_COS0 0x0C80 880#define BGE_LOCSTATS_COS1 0x0C84 881#define BGE_LOCSTATS_COS2 0x0C88 882#define BGE_LOCSTATS_COS3 0x0C8C 883#define BGE_LOCSTATS_COS4 0x0C90 884#define BGE_LOCSTATS_COS5 0x0C84 885#define BGE_LOCSTATS_COS6 0x0C98 886#define BGE_LOCSTATS_COS7 0x0C9C 887#define BGE_LOCSTATS_COS8 0x0CA0 888#define BGE_LOCSTATS_COS9 0x0CA4 889#define BGE_LOCSTATS_COS10 0x0CA8 890#define BGE_LOCSTATS_COS11 0x0CAC 891#define BGE_LOCSTATS_COS12 0x0CB0 892#define BGE_LOCSTATS_COS13 0x0CB4 893#define BGE_LOCSTATS_COS14 0x0CB8 894#define BGE_LOCSTATS_COS15 0x0CBC 895#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 896#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 897#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 898#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 899#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 900#define BGE_LOCSTATS_IRQS 0x0CD4 901#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 902#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 903* 904/* Send Data Initiator mode register / 905#define BGE_SDIMODE_RESET 0x00000001 906#define BGE_SDIMODE_ENABLE 0x00000002 907#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 908* 909/* Send Data Initiator stats register / 910#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 911* 912/* Send Data Initiator stats control register / 913#define BGE_SDISTATSCTL_ENABLE 0x00000001 914#define BGE_SDISTATSCTL_FASTER 0x00000002 915#define BGE_SDISTATSCTL_CLEAR 0x00000004 916#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 917#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 918* 919/* 920 * Send Data Completion Control registers 921 / 922#define BGE_SDC_MODE 0x1000 923#define BGE_SDC_STATUS 0x1004 924* 925/* Send Data completion mode register / 926#define BGE_SDCMODE_RESET 0x00000001 927#define BGE_SDCMODE_ENABLE 0x00000002 928#define BGE_SDCMODE_ATTN 0x00000004 929#define BGE_SDCMODE_CDELAY 0x00000010 930* 931/* Send Data completion status register / 932#define BGE_SDCSTAT_ATTN 0x00000004 933* 934/* 935 * Send BD Ring Selector Control registers 936 / 937#define BGE_SRS_MODE 0x1400 938#define BGE_SRS_STATUS 0x1404 939#define BGE_SRS_HWDIAG 0x1408 940#define BGE_SRS_LOC_NIC_CONS0 0x1440 941#define BGE_SRS_LOC_NIC_CONS1 0x1444 942#define BGE_SRS_LOC_NIC_CONS2 0x1448 943#define BGE_SRS_LOC_NIC_CONS3 0x144C 944#define BGE_SRS_LOC_NIC_CONS4 0x1450 945#define BGE_SRS_LOC_NIC_CONS5 0x1454 946#define BGE_SRS_LOC_NIC_CONS6 0x1458 947#define BGE_SRS_LOC_NIC_CONS7 0x145C 948#define BGE_SRS_LOC_NIC_CONS8 0x1460 949#define BGE_SRS_LOC_NIC_CONS9 0x1464 950#define BGE_SRS_LOC_NIC_CONS10 0x1468 951#define BGE_SRS_LOC_NIC_CONS11 0x146C 952#define BGE_SRS_LOC_NIC_CONS12 0x1470 953#define BGE_SRS_LOC_NIC_CONS13 0x1474 954#define BGE_SRS_LOC_NIC_CONS14 0x1478 955#define BGE_SRS_LOC_NIC_CONS15 0x147C 956* 957/* Send BD Ring Selector Mode register / 958#define BGE_SRSMODE_RESET 0x00000001 959#define BGE_SRSMODE_ENABLE 0x00000002 960#define BGE_SRSMODE_ATTN 0x00000004 961* 962/* Send BD Ring Selector Status register / 963#define BGE_SRSSTAT_ERROR 0x00000004 964* 965/* Send BD Ring Selector HW Diagnostics register / 966#define BGE_SRSHWDIAG_STATE 0x0000000F 967#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 968#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 969#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 970* 971/* 972 * Send BD Initiator Selector Control registers 973 / 974#define BGE_SBDI_MODE 0x1800 975#define BGE_SBDI_STATUS 0x1804 976#define BGE_SBDI_LOC_NIC_PROD0 0x1808 977#define BGE_SBDI_LOC_NIC_PROD1 0x180C 978#define BGE_SBDI_LOC_NIC_PROD2 0x1810 979#define BGE_SBDI_LOC_NIC_PROD3 0x1814 980#define BGE_SBDI_LOC_NIC_PROD4 0x1818 981#define BGE_SBDI_LOC_NIC_PROD5 0x181C 982#define BGE_SBDI_LOC_NIC_PROD6 0x1820 983#define BGE_SBDI_LOC_NIC_PROD7 0x1824 984#define BGE_SBDI_LOC_NIC_PROD8 0x1828 985#define BGE_SBDI_LOC_NIC_PROD9 0x182C 986#define BGE_SBDI_LOC_NIC_PROD10 0x1830 987#define BGE_SBDI_LOC_NIC_PROD11 0x1834 988#define BGE_SBDI_LOC_NIC_PROD12 0x1838 989#define BGE_SBDI_LOC_NIC_PROD13 0x183C 990#define BGE_SBDI_LOC_NIC_PROD14 0x1840 991#define BGE_SBDI_LOC_NIC_PROD15 0x1844 992* 993/* Send BD Initiator Mode register / 994#define BGE_SBDIMODE_RESET 0x00000001 995#define BGE_SBDIMODE_ENABLE 0x00000002 996#define BGE_SBDIMODE_ATTN 0x00000004 997* 998/* Send BD Initiator Status register / 999#define BGE_SBDISTAT_ERROR 0x00000004 1000* 1001/* 1002 * Send BD Completion Control registers 1003 / 1004#define BGE_SBDC_MODE 0x1C00 1005#define BGE_SBDC_STATUS 0x1C04 1006* 1007/* Send BD Completion Control Mode register / 1008#define BGE_SBDCMODE_RESET 0x00000001 1009#define BGE_SBDCMODE_ENABLE 0x00000002 1010#define BGE_SBDCMODE_ATTN 0x00000004 1011* 1012/* Send BD Completion Control Status register / 1013#define BGE_SBDCSTAT_ATTN 0x00000004 1014* 1015/* 1016 * Receive List Placement Control registers 1017 / 1018#define BGE_RXLP_MODE 0x2000 1019#define BGE_RXLP_STATUS 0x2004 1020#define BGE_RXLP_SEL_LIST_LOCK 0x2008 1021#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 1022#define BGE_RXLP_CFG 0x2010 1023#define BGE_RXLP_STATS_CTL 0x2014 1024#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 1025#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 1026#define BGE_RXLP_HEAD0 0x2100 1027#define BGE_RXLP_TAIL0 0x2104 1028#define BGE_RXLP_COUNT0 0x2108 1029#define BGE_RXLP_HEAD1 0x2110 1030#define BGE_RXLP_TAIL1 0x2114 1031#define BGE_RXLP_COUNT1 0x2118 1032#define BGE_RXLP_HEAD2 0x2120 1033#define BGE_RXLP_TAIL2 0x2124 1034#define BGE_RXLP_COUNT2 0x2128 1035#define BGE_RXLP_HEAD3 0x2130 1036#define BGE_RXLP_TAIL3 0x2134 1037#define BGE_RXLP_COUNT3 0x2138 1038#define BGE_RXLP_HEAD4 0x2140 1039#define BGE_RXLP_TAIL4 0x2144 1040#define BGE_RXLP_COUNT4 0x2148 1041#define BGE_RXLP_HEAD5 0x2150 1042#define BGE_RXLP_TAIL5 0x2154 1043#define BGE_RXLP_COUNT5 0x2158 1044#define BGE_RXLP_HEAD6 0x2160 1045#define BGE_RXLP_TAIL6 0x2164 1046#define BGE_RXLP_COUNT6 0x2168 1047#define BGE_RXLP_HEAD7 0x2170 1048#define BGE_RXLP_TAIL7 0x2174 1049#define BGE_RXLP_COUNT7 0x2178 1050#define BGE_RXLP_HEAD8 0x2180 1051#define BGE_RXLP_TAIL8 0x2184 1052#define BGE_RXLP_COUNT8 0x2188 1053#define BGE_RXLP_HEAD9 0x2190 1054#define BGE_RXLP_TAIL9 0x2194 1055#define BGE_RXLP_COUNT9 0x2198 1056#define BGE_RXLP_HEAD10 0x21A0 1057#define BGE_RXLP_TAIL10 0x21A4 1058#define BGE_RXLP_COUNT10 0x21A8 1059#define BGE_RXLP_HEAD11 0x21B0 1060#define BGE_RXLP_TAIL11 0x21B4 1061#define BGE_RXLP_COUNT11 0x21B8 1062#define BGE_RXLP_HEAD12 0x21C0 1063#define BGE_RXLP_TAIL12 0x21C4 1064#define BGE_RXLP_COUNT12 0x21C8 1065#define BGE_RXLP_HEAD13 0x21D0 1066#define BGE_RXLP_TAIL13 0x21D4 1067#define BGE_RXLP_COUNT13 0x21D8 1068#define BGE_RXLP_HEAD14 0x21E0 1069#define BGE_RXLP_TAIL14 0x21E4 1070#define BGE_RXLP_COUNT14 0x21E8 1071#define BGE_RXLP_HEAD15 0x21F0 1072#define BGE_RXLP_TAIL15 0x21F4 1073#define BGE_RXLP_COUNT15 0x21F8 1074#define BGE_RXLP_LOCSTAT_COS0 0x2200 1075#define BGE_RXLP_LOCSTAT_COS1 0x2204 1076#define BGE_RXLP_LOCSTAT_COS2 0x2208 1077#define BGE_RXLP_LOCSTAT_COS3 0x220C 1078#define BGE_RXLP_LOCSTAT_COS4 0x2210 1079#define BGE_RXLP_LOCSTAT_COS5 0x2214 1080#define BGE_RXLP_LOCSTAT_COS6 0x2218 1081#define BGE_RXLP_LOCSTAT_COS7 0x221C 1082#define BGE_RXLP_LOCSTAT_COS8 0x2220 1083#define BGE_RXLP_LOCSTAT_COS9 0x2224 1084#define BGE_RXLP_LOCSTAT_COS10 0x2228 1085#define BGE_RXLP_LOCSTAT_COS11 0x222C 1086#define BGE_RXLP_LOCSTAT_COS12 0x2230 1087#define BGE_RXLP_LOCSTAT_COS13 0x2234 1088#define BGE_RXLP_LOCSTAT_COS14 0x2238 1089#define BGE_RXLP_LOCSTAT_COS15 0x223C 1090#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1091#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1092#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1093#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1094#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1095#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1096#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1097* 1098 1099/* Receive List Placement mode register / 1100#define BGE_RXLPMODE_RESET 0x00000001 1101#define BGE_RXLPMODE_ENABLE 0x00000002 1102#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1103#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1104#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1105* 1106/* Receive List Placement Status register / 1107#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1108#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1109#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1110* 1111/* 1112 * Receive Data and Receive BD Initiator Control Registers 1113 / 1114#define BGE_RDBDI_MODE 0x2400 1115#define BGE_RDBDI_STATUS 0x2404 1116#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1117#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1118#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1119#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1120#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1121#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1122#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1123#define BGE_RX_STD_RCB_NICADDR 0x245C 1124#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1125#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1126#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1127#define BGE_RX_MINI_RCB_NICADDR 0x246C 1128#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1129#define BGE_RDBDI_STD_RX_CONS 0x2474 1130#define BGE_RDBDI_MINI_RX_CONS 0x2478 1131#define BGE_RDBDI_RETURN_PROD0 0x2480 1132#define BGE_RDBDI_RETURN_PROD1 0x2484 1133#define BGE_RDBDI_RETURN_PROD2 0x2488 1134#define BGE_RDBDI_RETURN_PROD3 0x248C 1135#define BGE_RDBDI_RETURN_PROD4 0x2490 1136#define BGE_RDBDI_RETURN_PROD5 0x2494 1137#define BGE_RDBDI_RETURN_PROD6 0x2498 1138#define BGE_RDBDI_RETURN_PROD7 0x249C 1139#define BGE_RDBDI_RETURN_PROD8 0x24A0 1140#define BGE_RDBDI_RETURN_PROD9 0x24A4 1141#define BGE_RDBDI_RETURN_PROD10 0x24A8 1142#define BGE_RDBDI_RETURN_PROD11 0x24AC 1143#define BGE_RDBDI_RETURN_PROD12 0x24B0 1144#define BGE_RDBDI_RETURN_PROD13 0x24B4 1145#define BGE_RDBDI_RETURN_PROD14 0x24B8 1146#define BGE_RDBDI_RETURN_PROD15 0x24BC 1147#define BGE_RDBDI_HWDIAG 0x24C0 1148* 1149 1150/* Receive Data and Receive BD Initiator Mode register / 1151#define BGE_RDBDIMODE_RESET 0x00000001 1152#define BGE_RDBDIMODE_ENABLE 0x00000002 1153#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1154#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1155#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1156* 1157/* Receive Data and Receive BD Initiator Status register / 1158#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1159#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1160#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1161* 1162 1163/* 1164 * Receive Data Completion Control registers 1165 / 1166#define BGE_RDC_MODE 0x2800 1167* 1168/* Receive Data Completion Mode register / 1169#define BGE_RDCMODE_RESET 0x00000001 1170#define BGE_RDCMODE_ENABLE 0x00000002 1171#define BGE_RDCMODE_ATTN 0x00000004 1172* 1173/* 1174 * Receive BD Initiator Control registers 1175 / 1176#define BGE_RBDI_MODE 0x2C00 1177#define BGE_RBDI_STATUS 0x2C04 1178#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1179#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1180#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1181#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1182#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1183#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1184* 1185/* Receive BD Initiator Mode register / 1186#define BGE_RBDIMODE_RESET 0x00000001 1187#define BGE_RBDIMODE_ENABLE 0x00000002 1188#define BGE_RBDIMODE_ATTN 0x00000004 1189* 1190/* Receive BD Initiator Status register / 1191#define BGE_RBDISTAT_ATTN 0x00000004 1192* 1193/* 1194 * Receive BD Completion Control registers 1195 / 1196#define BGE_RBDC_MODE 0x3000 1197#define BGE_RBDC_STATUS 0x3004 1198#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1199#define BGE_RBDC_STD_BD_PROD 0x300C 1200#define BGE_RBDC_MINI_BD_PROD 0x3010 1201* 1202/* Receive BD completion mode register / 1203#define BGE_RBDCMODE_RESET 0x00000001 1204#define BGE_RBDCMODE_ENABLE 0x00000002 1205#define BGE_RBDCMODE_ATTN 0x00000004 1206* 1207/* Receive BD completion status register / 1208#define BGE_RBDCSTAT_ERROR 0x00000004 1209* 1210/* 1211 * Receive List Selector Control registers 1212 / 1213#define BGE_RXLS_MODE 0x3400 1214#define BGE_RXLS_STATUS 0x3404 1215* 1216/* Receive List Selector Mode register / 1217#define BGE_RXLSMODE_RESET 0x00000001 1218#define BGE_RXLSMODE_ENABLE 0x00000002 1219#define BGE_RXLSMODE_ATTN 0x00000004 1220* 1221/* Receive List Selector Status register / 1222#define BGE_RXLSSTAT_ERROR 0x00000004 1223* 1224/* 1225 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1226 / 1227#define BGE_MBCF_MODE 0x3800 1228#define BGE_MBCF_STATUS 0x3804 1229* 1230/* Mbuf Cluster Free mode register / 1231#define BGE_MBCFMODE_RESET 0x00000001 1232#define BGE_MBCFMODE_ENABLE 0x00000002 1233#define BGE_MBCFMODE_ATTN 0x00000004 1234* 1235/* Mbuf Cluster Free status register / 1236#define BGE_MBCFSTAT_ERROR 0x00000004 1237* 1238/* 1239 * Host Coalescing Control registers 1240 / 1241#define BGE_HCC_MODE 0x3C00 1242#define BGE_HCC_STATUS 0x3C04 1243#define BGE_HCC_RX_COAL_TICKS 0x3C08 1244#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1245#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1246#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1247#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1248#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1249#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1250#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1251#define BGE_HCC_STATS_TICKS 0x3C28 1252#define BGE_HCC_STATS_ADDR_HI 0x3C30 1253#define BGE_HCC_STATS_ADDR_LO 0x3C34 1254#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1255#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1256#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1257#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1258#define BGE_FLOW_ATTN 0x3C48 1259#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1260#define BGE_HCC_STD_BD_CONS 0x3C54 1261#define BGE_HCC_MINI_BD_CONS 0x3C58 1262#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1263#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1264#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1265#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1266#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1267#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1268#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1269#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1270#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1271#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1272#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1273#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1274#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1275#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1276#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1277#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1278#define BGE_HCC_TX_BD_CONS0 0x3CC0 1279#define BGE_HCC_TX_BD_CONS1 0x3CC4 1280#define BGE_HCC_TX_BD_CONS2 0x3CC8 1281#define BGE_HCC_TX_BD_CONS3 0x3CCC 1282#define BGE_HCC_TX_BD_CONS4 0x3CD0 1283#define BGE_HCC_TX_BD_CONS5 0x3CD4 1284#define BGE_HCC_TX_BD_CONS6 0x3CD8 1285#define BGE_HCC_TX_BD_CONS7 0x3CDC 1286#define BGE_HCC_TX_BD_CONS8 0x3CE0 1287#define BGE_HCC_TX_BD_CONS9 0x3CE4 1288#define BGE_HCC_TX_BD_CONS10 0x3CE8 1289#define BGE_HCC_TX_BD_CONS11 0x3CEC 1290#define BGE_HCC_TX_BD_CONS12 0x3CF0 1291#define BGE_HCC_TX_BD_CONS13 0x3CF4 1292#define BGE_HCC_TX_BD_CONS14 0x3CF8 1293#define BGE_HCC_TX_BD_CONS15 0x3CFC 1294* 1295 1296/* Host coalescing mode register / 1297#define BGE_HCCMODE_RESET 0x00000001 1298#define BGE_HCCMODE_ENABLE 0x00000002 1299#define BGE_HCCMODE_ATTN 0x00000004 1300#define BGE_HCCMODE_COAL_NOW 0x00000008 1301#define BGE_HCCMODE_MSI_BITS 0x00000070 1302#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1303* 1304#define BGE_STATBLKSZ_FULL 0x00000000 1305#define BGE_STATBLKSZ_64BYTE 0x00000080 1306#define BGE_STATBLKSZ_32BYTE 0x00000100 1307 1308/* Host coalescing status register / 1309#define BGE_HCCSTAT_ERROR 0x00000004 1310* 1311/* Flow attention register / 1312#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1313#define BGE_FLOWATTN_MEMARB 0x00000080 1314#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1315#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1316#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1317#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1318#define BGE_FLOWATTN_RDBDI 0x00080000 1319#define BGE_FLOWATTN_RXLS 0x00100000 1320#define BGE_FLOWATTN_RXLP 0x00200000 1321#define BGE_FLOWATTN_RBDC 0x00400000 1322#define BGE_FLOWATTN_RBDI 0x00800000 1323#define BGE_FLOWATTN_SDC 0x08000000 1324#define BGE_FLOWATTN_SDI 0x10000000 1325#define BGE_FLOWATTN_SRS 0x20000000 1326#define BGE_FLOWATTN_SBDC 0x40000000 1327#define BGE_FLOWATTN_SBDI 0x80000000 1328* 1329/* 1330 * Memory arbiter registers 1331 / 1332#define BGE_MARB_MODE 0x4000 1333#define BGE_MARB_STATUS 0x4004 1334#define BGE_MARB_TRAPADDR_HI 0x4008 1335#define BGE_MARB_TRAPADDR_LO 0x400C 1336* 1337/* Memory arbiter mode register / 1338#define BGE_MARBMODE_RESET 0x00000001 1339#define BGE_MARBMODE_ENABLE 0x00000002 1340#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1341#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1342#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1343#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1344#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1345#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1346#define BGE_MARBMODE_PCI_TRAP 0x00000100 1347#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1348#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1349#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1350#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1351#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1352#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1353#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1354#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1355#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1356#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1357#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1358#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1359#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1360#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1361#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1362#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1363#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1364* 1365/* Memory arbiter status register / 1366#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1367#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1368#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1369#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1370#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1371#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1372#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1373#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1374#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1375#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1376#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1377#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1378#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1379#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1380#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1381#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1382#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1383#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1384#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1385#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1386#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1387#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1388#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1389#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1390* 1391/* 1392 * Buffer manager control registers 1393 / 1394#define BGE_BMAN_MODE 0x4400 1395#define BGE_BMAN_STATUS 0x4404 1396#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1397#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1398#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1399#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1400#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1401#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1402#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1403#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1404#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1405#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1406#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1407#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1408#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1409#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1410#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1411#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1412#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1413#define BGE_BMAN_HWDIAG_1 0x444C 1414#define BGE_BMAN_HWDIAG_2 0x4450 1415#define BGE_BMAN_HWDIAG_3 0x4454 1416* 1417/* Buffer manager mode register / 1418#define BGE_BMANMODE_RESET 0x00000001 1419#define BGE_BMANMODE_ENABLE 0x00000002 1420#define BGE_BMANMODE_ATTN 0x00000004 1421#define BGE_BMANMODE_TESTMODE 0x00000008 1422#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1423* 1424/* Buffer manager status register / 1425#define BGE_BMANSTAT_ERRO 0x00000004 1426#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1427* 1428 1429/* 1430 * Read DMA Control registers 1431 / 1432#define BGE_RDMA_MODE 0x4800 1433*#define BGE_RDMA_STATUS 0x4804
	1434#define BGE_RDMA_RSRVCTRL 0x4900
1434 1435/* Read DMA mode register / 1436#define BGE_RDMAMODE_RESET 0x00000001 1437#define BGE_RDMAMODE_ENABLE 0x00000002 1438#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1439#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1440#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1441#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1442#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1443#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1444#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1445#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1446#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1447#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1448#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1449#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1450#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1451#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1452#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1453#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1454* 1455/* Read DMA status register / 1456#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1457#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1458#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1459#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1460#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1461#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1462#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1463#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1464*	1435 1436/* Read DMA mode register / 1437#define BGE_RDMAMODE_RESET 0x00000001 1438#define BGE_RDMAMODE_ENABLE 0x00000002 1439#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1440#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1441#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1442#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1443#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1444#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1445#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1446#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1447#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1448#define BGE_RDMAMODE_BD_SBD_CRPT_ATTN 0x00000800 1449#define BGE_RDMAMODE_MBUF_RBD_CRPT_ATTN 0x00001000 1450#define BGE_RDMAMODE_MBUF_SBD_CRPT_ATTN 0x00002000 1451#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1452#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1453#define BGE_RDMAMODE_TSO4_ENABLE 0x08000000 1454#define BGE_RDMAMODE_TSO6_ENABLE 0x10000000 1455* 1456/* Read DMA status register / 1457#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1458#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1459#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1460#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1461#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1462#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1463#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1464#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1465*
	1466/* Read DMA Reserved Control register / 1467#define BGE_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004 1468*
1465/* 1466 * Write DMA control registers 1467 / 1468#define BGE_WDMA_MODE 0x4C00 1469#define BGE_WDMA_STATUS 0x4C04 1470* 1471/* Write DMA mode register / 1472#define BGE_WDMAMODE_RESET 0x00000001 1473#define BGE_WDMAMODE_ENABLE 0x00000002 1474#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1475#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1476#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1477#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1478#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1479#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1480#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1481#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1482#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1483#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1484#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1485* 1486/* Write DMA status register / 1487#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1488#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1489#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1490#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1491#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1492#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1493#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1494#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1495* 1496 1497/* 1498 * RX CPU registers 1499 / 1500#define BGE_RXCPU_MODE 0x5000 1501#define BGE_RXCPU_STATUS 0x5004 1502#define BGE_RXCPU_PC 0x501C 1503* 1504/* RX CPU mode register / 1505#define BGE_RXCPUMODE_RESET 0x00000001 1506#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1507#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1508#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1509#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1510#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1511#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1512#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1513#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1514#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1515#define BGE_RXCPUMODE_HALTCPU 0x00000400 1516#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1517#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1518#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1519* 1520/* RX CPU status register / 1521#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1522#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1523#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1524#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1525#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1526#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1527#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1528#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1529#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1530#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1531#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1532#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1533#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1534#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1535#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1536#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1537#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1538* 1539/* 1540 * V? CPU registers 1541 / 1542#define BGE_VCPU_STATUS 0x5100 1543#define BGE_VCPU_EXT_CTRL 0x6890 1544* 1545#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1546#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1547 1548#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1549#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1550 1551/* 1552 * TX CPU registers 1553 / 1554#define BGE_TXCPU_MODE 0x5400 1555#define BGE_TXCPU_STATUS 0x5404 1556#define BGE_TXCPU_PC 0x541C 1557* 1558/* TX CPU mode register / 1559#define BGE_TXCPUMODE_RESET 0x00000001 1560#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1561#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1562#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1563#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1564#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1565#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1566#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1567#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1568#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1569#define BGE_TXCPUMODE_HALTCPU 0x00000400 1570#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1571#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1572* 1573/* TX CPU status register / 1574#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1575#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1576#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1577#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1578#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1579#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1580#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1581#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1582#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1583#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1584#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1585#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1586#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1587#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1588#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1589#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1590#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1591* 1592 1593/* 1594 * Low priority mailbox registers 1595 / 1596#define BGE_LPMBX_IRQ0_HI 0x5800 1597#define BGE_LPMBX_IRQ0_LO 0x5804 1598#define BGE_LPMBX_IRQ1_HI 0x5808 1599#define BGE_LPMBX_IRQ1_LO 0x580C 1600#define BGE_LPMBX_IRQ2_HI 0x5810 1601#define BGE_LPMBX_IRQ2_LO 0x5814 1602#define BGE_LPMBX_IRQ3_HI 0x5818 1603#define BGE_LPMBX_IRQ3_LO 0x581C 1604#define BGE_LPMBX_GEN0_HI 0x5820 1605#define BGE_LPMBX_GEN0_LO 0x5824 1606#define BGE_LPMBX_GEN1_HI 0x5828 1607#define BGE_LPMBX_GEN1_LO 0x582C 1608#define BGE_LPMBX_GEN2_HI 0x5830 1609#define BGE_LPMBX_GEN2_LO 0x5834 1610#define BGE_LPMBX_GEN3_HI 0x5828 1611#define BGE_LPMBX_GEN3_LO 0x582C 1612#define BGE_LPMBX_GEN4_HI 0x5840 1613#define BGE_LPMBX_GEN4_LO 0x5844 1614#define BGE_LPMBX_GEN5_HI 0x5848 1615#define BGE_LPMBX_GEN5_LO 0x584C 1616#define BGE_LPMBX_GEN6_HI 0x5850 1617#define BGE_LPMBX_GEN6_LO 0x5854 1618#define BGE_LPMBX_GEN7_HI 0x5858 1619#define BGE_LPMBX_GEN7_LO 0x585C 1620#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1621#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1622#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1623#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1624#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1625#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1626#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1627#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1628#define BGE_LPMBX_RX_CONS0_HI 0x5880 1629#define BGE_LPMBX_RX_CONS0_LO 0x5884 1630#define BGE_LPMBX_RX_CONS1_HI 0x5888 1631#define BGE_LPMBX_RX_CONS1_LO 0x588C 1632#define BGE_LPMBX_RX_CONS2_HI 0x5890 1633#define BGE_LPMBX_RX_CONS2_LO 0x5894 1634#define BGE_LPMBX_RX_CONS3_HI 0x5898 1635#define BGE_LPMBX_RX_CONS3_LO 0x589C 1636#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1637#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1638#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1639#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1640#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1641#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1642#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1643#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1644#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1645#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1646#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1647#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1648#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1649#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1650#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1651#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1652#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1653#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1654#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1655#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1656#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1657#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1658#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1659#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1660#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1661#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1662#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1663#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1664#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1665#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1666#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1667#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1668#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1669#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1670#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1671#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1672#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1673#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1674#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1675#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1676#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1677#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1678#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1679#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1680#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1681#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1682#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1683#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1684#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1685#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1686#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1687#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1688#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1689#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1690#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1691#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1692#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1693#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1694#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1695#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1696#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1697#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1698#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1699#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1700#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1701#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1702#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1703#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1704#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1705#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1706#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1707#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1708#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1709#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1710#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1711#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1712#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1713#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1714#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1715#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1716#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1717#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1718#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1719#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1720#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1721#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1722#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1723#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1724* 1725/* 1726 * Flow throw Queue reset register 1727 / 1728#define BGE_FTQ_RESET 0x5C00 1729* 1730#define BGE_FTQRESET_DMAREAD 0x00000002 1731#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1732#define BGE_FTQRESET_DMADONE 0x00000010 1733#define BGE_FTQRESET_SBDC 0x00000020 1734#define BGE_FTQRESET_SDI 0x00000040 1735#define BGE_FTQRESET_WDMA 0x00000080 1736#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1737#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1738#define BGE_FTQRESET_SDC 0x00000400 1739#define BGE_FTQRESET_HCC 0x00000800 1740#define BGE_FTQRESET_TXFIFO 0x00001000 1741#define BGE_FTQRESET_MBC 0x00002000 1742#define BGE_FTQRESET_RBDC 0x00004000 1743#define BGE_FTQRESET_RXLP 0x00008000 1744#define BGE_FTQRESET_RDBDI 0x00010000 1745#define BGE_FTQRESET_RDC 0x00020000 1746#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1747 1748/* 1749 * Message Signaled Interrupt registers 1750 / 1751#define BGE_MSI_MODE 0x6000 1752#define BGE_MSI_STATUS 0x6004 1753#define BGE_MSI_FIFOACCESS 0x6008 1754* 1755/* MSI mode register / 1756#define BGE_MSIMODE_RESET 0x00000001 1757#define BGE_MSIMODE_ENABLE 0x00000002 1758#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1759#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1760* 1761/* MSI status register / 1762#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1763#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1764#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1765#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1766#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1767* 1768 1769/* 1770 * DMA Completion registers 1771 / 1772#define BGE_DMAC_MODE 0x6400 1773* 1774/* DMA Completion mode register / 1775#define BGE_DMACMODE_RESET 0x00000001 1776#define BGE_DMACMODE_ENABLE 0x00000002 1777* 1778 1779/* 1780 * General control registers. 1781 / 1782#define BGE_MODE_CTL 0x6800 1783#define BGE_MISC_CFG 0x6804 1784#define BGE_MISC_LOCAL_CTL 0x6808 1785#define BGE_CPU_EVENT 0x6810 1786#define BGE_EE_ADDR 0x6838 1787#define BGE_EE_DATA 0x683C 1788#define BGE_EE_CTL 0x6840 1789#define BGE_MDI_CTL 0x6844 1790#define BGE_EE_DELAY 0x6848 1791#define BGE_FASTBOOT_PC 0x6894 1792* 1793/* 1794 * NVRAM Control registers 1795 / 1796#define BGE_NVRAM_CMD 0x7000 1797#define BGE_NVRAM_STAT 0x7004 1798#define BGE_NVRAM_WRDATA 0x7008 1799#define BGE_NVRAM_ADDR 0x700c 1800#define BGE_NVRAM_RDDATA 0x7010 1801#define BGE_NVRAM_CFG1 0x7014 1802#define BGE_NVRAM_CFG2 0x7018 1803#define BGE_NVRAM_CFG3 0x701c 1804#define BGE_NVRAM_SWARB 0x7020 1805#define BGE_NVRAM_ACCESS 0x7024 1806#define BGE_NVRAM_WRITE1 0x7028 1807* 1808#define BGE_NVRAMCMD_RESET 0x00000001 1809#define BGE_NVRAMCMD_DONE 0x00000008 1810#define BGE_NVRAMCMD_START 0x00000010 1811#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1812#define BGE_NVRAMCMD_ERASE 0x00000040 1813#define BGE_NVRAMCMD_FIRST 0x00000080 1814#define BGE_NVRAMCMD_LAST 0x00000100 1815* 1816#define BGE_NVRAM_READCMD \ 1817 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1818 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1819#define BGE_NVRAM_WRITECMD \ 1820 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1821 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1822 1823#define BGE_NVRAMSWARB_SET0 0x00000001 1824#define BGE_NVRAMSWARB_SET1 0x00000002 1825#define BGE_NVRAMSWARB_SET2 0x00000003 1826#define BGE_NVRAMSWARB_SET3 0x00000004 1827#define BGE_NVRAMSWARB_CLR0 0x00000010 1828#define BGE_NVRAMSWARB_CLR1 0x00000020 1829#define BGE_NVRAMSWARB_CLR2 0x00000040 1830#define BGE_NVRAMSWARB_CLR3 0x00000080 1831#define BGE_NVRAMSWARB_GNT0 0x00000100 1832#define BGE_NVRAMSWARB_GNT1 0x00000200 1833#define BGE_NVRAMSWARB_GNT2 0x00000400 1834#define BGE_NVRAMSWARB_GNT3 0x00000800 1835#define BGE_NVRAMSWARB_REQ0 0x00001000 1836#define BGE_NVRAMSWARB_REQ1 0x00002000 1837#define BGE_NVRAMSWARB_REQ2 0x00004000 1838#define BGE_NVRAMSWARB_REQ3 0x00008000 1839 1840#define BGE_NVRAMACC_ENABLE 0x00000001 1841#define BGE_NVRAMACC_WRENABLE 0x00000002 1842 1843/* Mode control register / 1844#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1845#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1846#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1847#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1848#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1849#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1850#define BGE_MODECTL_NO_RX_CRC 0x00000400 1851#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1852#define BGE_MODECTL_NO_TX_INTR 0x00002000 1853#define BGE_MODECTL_NO_RX_INTR 0x00004000 1854#define BGE_MODECTL_FORCE_PCI32 0x00008000 1855#define BGE_MODECTL_STACKUP 0x00010000 1856#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1857#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1858#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1859#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1860#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1861#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1862#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1863#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1864#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1865#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1866* 1867/* Misc. config register / 1868#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1869#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1870#define BGE_MISCCFG_BOARD_ID 0x0001E000 1871#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1872#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1873#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1874#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1875* 1876#define BGE_32BITTIME_66MHZ (0x41 << 1) 1877 1878/* Misc. Local Control / 1879#define BGE_MLC_INTR_STATE 0x00000001 1880#define BGE_MLC_INTR_CLR 0x00000002 1881#define BGE_MLC_INTR_SET 0x00000004 1882#define BGE_MLC_INTR_ONATTN 0x00000008 1883#define BGE_MLC_MISCIO_IN0 0x00000100 1884#define BGE_MLC_MISCIO_IN1 0x00000200 1885#define BGE_MLC_MISCIO_IN2 0x00000400 1886#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1887#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1888#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1889#define BGE_MLC_MISCIO_OUT0 0x00004000 1890#define BGE_MLC_MISCIO_OUT1 0x00008000 1891#define BGE_MLC_MISCIO_OUT2 0x00010000 1892#define BGE_MLC_EXTRAM_ENB 0x00020000 1893#define BGE_MLC_SRAM_SIZE 0x001C0000 1894#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1895#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1896#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1897#define BGE_MLC_AUTO_EEPROM 0x01000000 1898* 1899#define BGE_SSRAMSIZE_256KB 0x00000000 1900#define BGE_SSRAMSIZE_512KB 0x00040000 1901#define BGE_SSRAMSIZE_1MB 0x00080000 1902#define BGE_SSRAMSIZE_2MB 0x000C0000 1903#define BGE_SSRAMSIZE_4MB 0x00100000 1904#define BGE_SSRAMSIZE_8MB 0x00140000 1905#define BGE_SSRAMSIZE_16M 0x00180000 1906 1907/* EEPROM address register / 1908#define BGE_EEADDR_ADDRESS 0x0000FFFC 1909#define BGE_EEADDR_HALFCLK 0x01FF0000 1910#define BGE_EEADDR_START 0x02000000 1911#define BGE_EEADDR_DEVID 0x1C000000 1912#define BGE_EEADDR_RESET 0x20000000 1913#define BGE_EEADDR_DONE 0x40000000 1914#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1915* 1916#define BGE_EEDEVID(x) ((x & 7) << 26) 1917#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1918#define BGE_HALFCLK_384SCL 0x60 1919#define BGE_EE_READCMD \ 1920 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1921 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1922#define BGE_EE_WRCMD \ 1923 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1924 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1925 1926/* EEPROM Control register / 1927#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1928#define BGE_EECTL_CLKOUT 0x00000002 1929#define BGE_EECTL_CLKIN 0x00000004 1930#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1931#define BGE_EECTL_DATAOUT 0x00000010 1932#define BGE_EECTL_DATAIN 0x00000020 1933* 1934/* MDI (MII/GMII) access register / 1935#define BGE_MDI_DATA 0x00000001 1936#define BGE_MDI_DIR 0x00000002 1937#define BGE_MDI_SEL 0x00000004 1938#define BGE_MDI_CLK 0x00000008 1939* 1940#define BGE_MEMWIN_START 0x00008000 1941#define BGE_MEMWIN_END 0x0000FFFF 1942 1943 1944#define BGE_MEMWIN_READ(sc, x, val) \ 1945 do { \ 1946 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1947 (0xFFFF0000 & x), 4); \ 1948 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1949 } while(0) 1950 1951#define BGE_MEMWIN_WRITE(sc, x, val) \ 1952 do { \ 1953 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1954 (0xFFFF0000 & x), 4); \ 1955 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1956 } while(0) 1957 1958/* 1959 * This magic number is written to the firmware mailbox at 0xb50 1960 * before a software reset is issued. After the internal firmware 1961 * has completed its initialization it will write the opposite of 1962 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1963 * driver to synchronize with the firmware. 1964 / 1965#define BGE_MAGIC_NUMBER 0x4B657654 1966* 1967typedef struct { 1968 uint32_t bge_addr_hi; 1969 uint32_t bge_addr_lo; 1970} bge_hostaddr; 1971 1972#define BGE_HOSTADDR(x, y) \ 1973 do { \ 1974 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1975 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1976 } while(0) 1977 1978#define BGE_ADDR_LO(y) \ 1979 ((uint64_t) (y) & 0xFFFFFFFF) 1980#define BGE_ADDR_HI(y) \ 1981 ((uint64_t) (y) >> 32) 1982 1983/* Ring control block structure / 1984struct bge_rcb { 1985* bge_hostaddr bge_hostaddr; 1986 uint32_t bge_maxlen_flags; 1987 uint32_t bge_nicaddr; 1988}; 1989 1990#define RCB_WRITE_4(sc, rcb, offset, val) \ 1991 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1992#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1993 1994#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1995#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1996 1997struct bge_tx_bd { 1998 bge_hostaddr bge_addr; 1999#if BYTE_ORDER == LITTLE_ENDIAN 2000 uint16_t bge_flags; 2001 uint16_t bge_len; 2002 uint16_t bge_vlan_tag; 2003 uint16_t bge_mss; 2004#else 2005 uint16_t bge_len; 2006 uint16_t bge_flags; 2007 uint16_t bge_mss; 2008 uint16_t bge_vlan_tag; 2009#endif 2010}; 2011 2012#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2013#define BGE_TXBDFLAG_IP_CSUM 0x0002 2014#define BGE_TXBDFLAG_END 0x0004 2015#define BGE_TXBDFLAG_IP_FRAG 0x0008 2016#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2017#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2018#define BGE_TXBDFLAG_COAL_NOW 0x0080 2019#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2020#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2021#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2022#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2023#define BGE_TXBDFLAG_NO_CRC 0x8000 2024 2025#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2026 BGE_SEND_RING_1_TO_4 + \ 2027 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2028 2029struct bge_rx_bd { 2030 bge_hostaddr bge_addr; 2031#if BYTE_ORDER == LITTLE_ENDIAN 2032 uint16_t bge_len; 2033 uint16_t bge_idx; 2034 uint16_t bge_flags; 2035 uint16_t bge_type; 2036 uint16_t bge_tcp_udp_csum; 2037 uint16_t bge_ip_csum; 2038 uint16_t bge_vlan_tag; 2039 uint16_t bge_error_flag; 2040#else 2041 uint16_t bge_idx; 2042 uint16_t bge_len; 2043 uint16_t bge_type; 2044 uint16_t bge_flags; 2045 uint16_t bge_ip_csum; 2046 uint16_t bge_tcp_udp_csum; 2047 uint16_t bge_error_flag; 2048 uint16_t bge_vlan_tag; 2049#endif 2050 uint32_t bge_rsvd; 2051 uint32_t bge_opaque; 2052}; 2053 2054struct bge_extrx_bd { 2055 bge_hostaddr bge_addr1; 2056 bge_hostaddr bge_addr2; 2057 bge_hostaddr bge_addr3; 2058#if BYTE_ORDER == LITTLE_ENDIAN 2059 uint16_t bge_len2; 2060 uint16_t bge_len1; 2061 uint16_t bge_rsvd1; 2062 uint16_t bge_len3; 2063#else 2064 uint16_t bge_len1; 2065 uint16_t bge_len2; 2066 uint16_t bge_len3; 2067 uint16_t bge_rsvd1; 2068#endif 2069 bge_hostaddr bge_addr0; 2070#if BYTE_ORDER == LITTLE_ENDIAN 2071 uint16_t bge_len0; 2072 uint16_t bge_idx; 2073 uint16_t bge_flags; 2074 uint16_t bge_type; 2075 uint16_t bge_tcp_udp_csum; 2076 uint16_t bge_ip_csum; 2077 uint16_t bge_vlan_tag; 2078 uint16_t bge_error_flag; 2079#else 2080 uint16_t bge_idx; 2081 uint16_t bge_len0; 2082 uint16_t bge_type; 2083 uint16_t bge_flags; 2084 uint16_t bge_ip_csum; 2085 uint16_t bge_tcp_udp_csum; 2086 uint16_t bge_error_flag; 2087 uint16_t bge_vlan_tag; 2088#endif 2089 uint32_t bge_rsvd0; 2090 uint32_t bge_opaque; 2091}; 2092 2093#define BGE_RXBDFLAG_END 0x0004 2094#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2095#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2096#define BGE_RXBDFLAG_ERROR 0x0400 2097#define BGE_RXBDFLAG_MINI_RING 0x0800 2098#define BGE_RXBDFLAG_IP_CSUM 0x1000 2099#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2100#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2101 2102#define BGE_RXERRFLAG_BAD_CRC 0x0001 2103#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2104#define BGE_RXERRFLAG_LINK_LOST 0x0004 2105#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2106#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2107#define BGE_RXERRFLAG_RUNT 0x0020 2108#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2109#define BGE_RXERRFLAG_GIANT 0x0080 2110 2111struct bge_sts_idx { 2112#if BYTE_ORDER == LITTLE_ENDIAN 2113 uint16_t bge_rx_prod_idx; 2114 uint16_t bge_tx_cons_idx; 2115#else 2116 uint16_t bge_tx_cons_idx; 2117 uint16_t bge_rx_prod_idx; 2118#endif 2119}; 2120 2121struct bge_status_block { 2122 uint32_t bge_status; 2123 uint32_t bge_rsvd0; 2124#if BYTE_ORDER == LITTLE_ENDIAN 2125 uint16_t bge_rx_jumbo_cons_idx; 2126 uint16_t bge_rx_std_cons_idx; 2127 uint16_t bge_rx_mini_cons_idx; 2128 uint16_t bge_rsvd1; 2129#else 2130 uint16_t bge_rx_std_cons_idx; 2131 uint16_t bge_rx_jumbo_cons_idx; 2132 uint16_t bge_rsvd1; 2133 uint16_t bge_rx_mini_cons_idx; 2134#endif 2135 struct bge_sts_idx bge_idx[16]; 2136}; 2137 2138#define BGE_STATFLAG_UPDATED 0x00000001 2139#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2140#define BGE_STATFLAG_ERROR 0x00000004 2141 2142 2143/* 2144 * Broadcom Vendor ID 2145 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2146 * even though they're now manufactured by Broadcom) 2147 / 2148#define BCOM_VENDORID 0x14E4 2149#define BCOM_DEVICEID_BCM5700 0x1644 2150#define BCOM_DEVICEID_BCM5701 0x1645 2151#define BCOM_DEVICEID_BCM5702 0x1646 2152#define BCOM_DEVICEID_BCM5702X 0x16A6 2153#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2154#define BCOM_DEVICEID_BCM5703 0x1647 2155#define BCOM_DEVICEID_BCM5703X 0x16A7 2156#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2157#define BCOM_DEVICEID_BCM5704C 0x1648 2158#define BCOM_DEVICEID_BCM5704S 0x16A8 2159#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2160#define BCOM_DEVICEID_BCM5705 0x1653 2161#define BCOM_DEVICEID_BCM5705K 0x1654 2162#define BCOM_DEVICEID_BCM5705F 0x166E 2163#define BCOM_DEVICEID_BCM5705M 0x165D 2164#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2165#define BCOM_DEVICEID_BCM5714C 0x1668 2166#define BCOM_DEVICEID_BCM5714S 0x1669 2167#define BCOM_DEVICEID_BCM5715 0x1678 2168#define BCOM_DEVICEID_BCM5715S 0x1679 2169#define BCOM_DEVICEID_BCM5720 0x1658 2170#define BCOM_DEVICEID_BCM5721 0x1659 2171#define BCOM_DEVICEID_BCM5722 0x165A 2172#define BCOM_DEVICEID_BCM5723 0x165B 2173#define BCOM_DEVICEID_BCM5750 0x1676 2174#define BCOM_DEVICEID_BCM5750M 0x167C 2175#define BCOM_DEVICEID_BCM5751 0x1677 2176#define BCOM_DEVICEID_BCM5751F 0x167E 2177#define BCOM_DEVICEID_BCM5751M 0x167D 2178#define BCOM_DEVICEID_BCM5752 0x1600 2179#define BCOM_DEVICEID_BCM5752M 0x1601 2180#define BCOM_DEVICEID_BCM5753 0x16F7 2181#define BCOM_DEVICEID_BCM5753F 0x16FE 2182#define BCOM_DEVICEID_BCM5753M 0x16FD 2183#define BCOM_DEVICEID_BCM5754 0x167A 2184#define BCOM_DEVICEID_BCM5754M 0x1672 2185#define BCOM_DEVICEID_BCM5755 0x167B 2186#define BCOM_DEVICEID_BCM5755M 0x1673 2187#define BCOM_DEVICEID_BCM5756 0x1674 2188#define BCOM_DEVICEID_BCM5761 0x1681 2189#define BCOM_DEVICEID_BCM5761E 0x1680 2190#define BCOM_DEVICEID_BCM5761S 0x1688 2191#define BCOM_DEVICEID_BCM5761SE 0x1689 2192#define BCOM_DEVICEID_BCM5764 0x1684 2193#define BCOM_DEVICEID_BCM5780 0x166A 2194#define BCOM_DEVICEID_BCM5780S 0x166B 2195#define BCOM_DEVICEID_BCM5781 0x16DD 2196#define BCOM_DEVICEID_BCM5782 0x1696 2197#define BCOM_DEVICEID_BCM5784 0x1698 2198#define BCOM_DEVICEID_BCM5785F 0x16a0 2199#define BCOM_DEVICEID_BCM5785G 0x1699 2200#define BCOM_DEVICEID_BCM5786 0x169A 2201#define BCOM_DEVICEID_BCM5787 0x169B 2202#define BCOM_DEVICEID_BCM5787M 0x1693 2203#define BCOM_DEVICEID_BCM5787F 0x167f 2204#define BCOM_DEVICEID_BCM5788 0x169C 2205#define BCOM_DEVICEID_BCM5789 0x169D 2206#define BCOM_DEVICEID_BCM5901 0x170D 2207#define BCOM_DEVICEID_BCM5901A2 0x170E 2208#define BCOM_DEVICEID_BCM5903M 0x16FF 2209#define BCOM_DEVICEID_BCM5906 0x1712 2210#define BCOM_DEVICEID_BCM5906M 0x1713 2211#define BCOM_DEVICEID_BCM57760 0x1690 2212#define BCOM_DEVICEID_BCM57780 0x1692 2213#define BCOM_DEVICEID_BCM57788 0x1691 2214#define BCOM_DEVICEID_BCM57790 0x1694 2215* 2216/* 2217 * Alteon AceNIC PCI vendor/device ID. 2218 / 2219#define ALTEON_VENDORID 0x12AE 2220#define ALTEON_DEVICEID_ACENIC 0x0001 2221#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2222#define ALTEON_DEVICEID_BCM5700 0x0003 2223#define ALTEON_DEVICEID_BCM5701 0x0004 2224* 2225/* 2226 * 3Com 3c996 PCI vendor/device ID. 2227 / 2228#define TC_VENDORID 0x10B7 2229#define TC_DEVICEID_3C996 0x0003 2230* 2231/* 2232 * SysKonnect PCI vendor ID 2233 / 2234#define SK_VENDORID 0x1148 2235#define SK_DEVICEID_ALTIMA 0x4400 2236#define SK_SUBSYSID_9D21 0x4421 2237#define SK_SUBSYSID_9D41 0x4441 2238* 2239/* 2240 * Altima PCI vendor/device ID. 2241 / 2242#define ALTIMA_VENDORID 0x173b 2243#define ALTIMA_DEVICE_AC1000 0x03e8 2244#define ALTIMA_DEVICE_AC1002 0x03e9 2245#define ALTIMA_DEVICE_AC9100 0x03ea 2246* 2247/* 2248 * Dell PCI vendor ID 2249 / 2250* 2251#define DELL_VENDORID 0x1028 2252 2253/* 2254 * Apple PCI vendor ID. 2255 / 2256#define APPLE_VENDORID 0x106b 2257#define APPLE_DEVICE_BCM5701 0x1645 2258* 2259/* 2260 * Sun PCI vendor ID 2261 / 2262#define SUN_VENDORID 0x108e 2263* 2264/* 2265 * Fujitsu vendor/device IDs 2266 / 2267#define FJTSU_VENDORID 0x10cf 2268#define FJTSU_DEVICEID_PW008GE5 0x11a1 2269#define FJTSU_DEVICEID_PW008GE4 0x11a2 2270#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2271* 2272/* 2273 * Offset of MAC address inside EEPROM. 2274 / 2275#define BGE_EE_MAC_OFFSET 0x7C 2276#define BGE_EE_MAC_OFFSET_5906 0x10 2277#define BGE_EE_HWCFG_OFFSET 0xC8 2278* 2279#define BGE_HWCFG_VOLTAGE 0x00000003 2280#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2281#define BGE_HWCFG_MEDIA 0x00000030 2282#define BGE_HWCFG_ASF 0x00000080 2283 2284#define BGE_VOLTAGE_1POINT3 0x00000000 2285#define BGE_VOLTAGE_1POINT8 0x00000001 2286 2287#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2288#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2289#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2290 2291#define BGE_MEDIA_UNSPEC 0x00000000 2292#define BGE_MEDIA_COPPER 0x00000010 2293#define BGE_MEDIA_FIBER 0x00000020 2294 2295#define BGE_TICKS_PER_SEC 1000000 2296 2297/* 2298 * Ring size constants. 2299 / 2300#define BGE_EVENT_RING_CNT 256 2301#define BGE_CMD_RING_CNT 64 2302#define BGE_STD_RX_RING_CNT 512 2303#define BGE_JUMBO_RX_RING_CNT 256 2304#define BGE_MINI_RX_RING_CNT 1024 2305#define BGE_RETURN_RING_CNT 1024 2306* 2307/* 5705 has smaller return ring size / 2308* 2309#define BGE_RETURN_RING_CNT_5705 512 2310 2311/* 2312 * Possible TX ring sizes. 2313 / 2314#define BGE_TX_RING_CNT_128 128 2315#define BGE_TX_RING_BASE_128 0x3800 2316* 2317#define BGE_TX_RING_CNT_256 256 2318#define BGE_TX_RING_BASE_256 0x3000 2319 2320#define BGE_TX_RING_CNT_512 512 2321#define BGE_TX_RING_BASE_512 0x2000 2322 2323#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2324#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2325 2326/* 2327 * Tigon III statistics counters. 2328 / 2329/ Statistics maintained MAC Receive block. / 2330struct bge_rx_mac_stats { 2331* bge_hostaddr ifHCInOctets; 2332 bge_hostaddr Reserved1; 2333 bge_hostaddr etherStatsFragments; 2334 bge_hostaddr ifHCInUcastPkts; 2335 bge_hostaddr ifHCInMulticastPkts; 2336 bge_hostaddr ifHCInBroadcastPkts; 2337 bge_hostaddr dot3StatsFCSErrors; 2338 bge_hostaddr dot3StatsAlignmentErrors; 2339 bge_hostaddr xonPauseFramesReceived; 2340 bge_hostaddr xoffPauseFramesReceived; 2341 bge_hostaddr macControlFramesReceived; 2342 bge_hostaddr xoffStateEntered; 2343 bge_hostaddr dot3StatsFramesTooLong; 2344 bge_hostaddr etherStatsJabbers; 2345 bge_hostaddr etherStatsUndersizePkts; 2346 bge_hostaddr inRangeLengthError; 2347 bge_hostaddr outRangeLengthError; 2348 bge_hostaddr etherStatsPkts64Octets; 2349 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2350 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2351 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2352 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2353 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2354 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2355 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2356 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2357 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2358}; 2359 2360 2361/* Statistics maintained MAC Transmit block. / 2362struct bge_tx_mac_stats { 2363* bge_hostaddr ifHCOutOctets; 2364 bge_hostaddr Reserved2; 2365 bge_hostaddr etherStatsCollisions; 2366 bge_hostaddr outXonSent; 2367 bge_hostaddr outXoffSent; 2368 bge_hostaddr flowControlDone; 2369 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2370 bge_hostaddr dot3StatsSingleCollisionFrames; 2371 bge_hostaddr dot3StatsMultipleCollisionFrames; 2372 bge_hostaddr dot3StatsDeferredTransmissions; 2373 bge_hostaddr Reserved3; 2374 bge_hostaddr dot3StatsExcessiveCollisions; 2375 bge_hostaddr dot3StatsLateCollisions; 2376 bge_hostaddr dot3Collided2Times; 2377 bge_hostaddr dot3Collided3Times; 2378 bge_hostaddr dot3Collided4Times; 2379 bge_hostaddr dot3Collided5Times; 2380 bge_hostaddr dot3Collided6Times; 2381 bge_hostaddr dot3Collided7Times; 2382 bge_hostaddr dot3Collided8Times; 2383 bge_hostaddr dot3Collided9Times; 2384 bge_hostaddr dot3Collided10Times; 2385 bge_hostaddr dot3Collided11Times; 2386 bge_hostaddr dot3Collided12Times; 2387 bge_hostaddr dot3Collided13Times; 2388 bge_hostaddr dot3Collided14Times; 2389 bge_hostaddr dot3Collided15Times; 2390 bge_hostaddr ifHCOutUcastPkts; 2391 bge_hostaddr ifHCOutMulticastPkts; 2392 bge_hostaddr ifHCOutBroadcastPkts; 2393 bge_hostaddr dot3StatsCarrierSenseErrors; 2394 bge_hostaddr ifOutDiscards; 2395 bge_hostaddr ifOutErrors; 2396}; 2397 2398/* Stats counters access through registers / 2399struct bge_mac_stats { 2400* /* TX MAC statistics / 2401* uint64_t ifHCOutOctets; 2402 uint64_t Reserved0; 2403 uint64_t etherStatsCollisions; 2404 uint64_t outXonSent; 2405 uint64_t outXoffSent; 2406 uint64_t Reserved1; 2407 uint64_t dot3StatsInternalMacTransmitErrors; 2408 uint64_t dot3StatsSingleCollisionFrames; 2409 uint64_t dot3StatsMultipleCollisionFrames; 2410 uint64_t dot3StatsDeferredTransmissions; 2411 uint64_t Reserved2; 2412 uint64_t dot3StatsExcessiveCollisions; 2413 uint64_t dot3StatsLateCollisions; 2414 uint64_t Reserved3[14]; 2415 uint64_t ifHCOutUcastPkts; 2416 uint64_t ifHCOutMulticastPkts; 2417 uint64_t ifHCOutBroadcastPkts; 2418 uint64_t Reserved4[2]; 2419 /* RX MAC statistics / 2420* uint64_t ifHCInOctets; 2421 uint64_t Reserved5; 2422 uint64_t etherStatsFragments; 2423 uint64_t ifHCInUcastPkts; 2424 uint64_t ifHCInMulticastPkts; 2425 uint64_t ifHCInBroadcastPkts; 2426 uint64_t dot3StatsFCSErrors; 2427 uint64_t dot3StatsAlignmentErrors; 2428 uint64_t xonPauseFramesReceived; 2429 uint64_t xoffPauseFramesReceived; 2430 uint64_t macControlFramesReceived; 2431 uint64_t xoffStateEntered; 2432 uint64_t dot3StatsFramesTooLong; 2433 uint64_t etherStatsJabbers; 2434 uint64_t etherStatsUndersizePkts; 2435 /* Receive List Placement control / 2436* uint64_t FramesDroppedDueToFilters; 2437 uint64_t DmaWriteQueueFull; 2438 uint64_t DmaWriteHighPriQueueFull; 2439 uint64_t NoMoreRxBDs; 2440 uint64_t InputDiscards; 2441 uint64_t InputErrors; 2442 uint64_t RecvThresholdHit; 2443}; 2444 2445struct bge_stats { 2446 uint8_t Reserved0[256]; 2447 2448 /* Statistics maintained by Receive MAC. / 2449* struct bge_rx_mac_stats rxstats; 2450 2451 bge_hostaddr Unused1[37]; 2452 2453 /* Statistics maintained by Transmit MAC. / 2454* struct bge_tx_mac_stats txstats; 2455 2456 bge_hostaddr Unused2[31]; 2457 2458 /* Statistics maintained by Receive List Placement. / 2459* bge_hostaddr COSIfHCInPkts[16]; 2460 bge_hostaddr COSFramesDroppedDueToFilters; 2461 bge_hostaddr nicDmaWriteQueueFull; 2462 bge_hostaddr nicDmaWriteHighPriQueueFull; 2463 bge_hostaddr nicNoMoreRxBDs; 2464 bge_hostaddr ifInDiscards; 2465 bge_hostaddr ifInErrors; 2466 bge_hostaddr nicRecvThresholdHit; 2467 2468 bge_hostaddr Unused3[9]; 2469 2470 /* Statistics maintained by Send Data Initiator. / 2471* bge_hostaddr COSIfHCOutPkts[16]; 2472 bge_hostaddr nicDmaReadQueueFull; 2473 bge_hostaddr nicDmaReadHighPriQueueFull; 2474 bge_hostaddr nicSendDataCompQueueFull; 2475 2476 /* Statistics maintained by Host Coalescing. / 2477* bge_hostaddr nicRingSetSendProdIndex; 2478 bge_hostaddr nicRingStatusUpdate; 2479 bge_hostaddr nicInterrupts; 2480 bge_hostaddr nicAvoidedInterrupts; 2481 bge_hostaddr nicSendThresholdHit; 2482 2483 uint8_t Reserved4[320]; 2484}; 2485 2486/* 2487 * Tigon general information block. This resides in host memory 2488 * and contains the status counters, ring control blocks and 2489 * producer pointers. 2490 / 2491* 2492struct bge_gib { 2493 struct bge_stats bge_stats; 2494 struct bge_rcb bge_tx_rcb[16]; 2495 struct bge_rcb bge_std_rx_rcb; 2496 struct bge_rcb bge_jumbo_rx_rcb; 2497 struct bge_rcb bge_mini_rx_rcb; 2498 struct bge_rcb bge_return_rcb; 2499}; 2500 2501#define BGE_FRAMELEN 1518 2502#define BGE_MAX_FRAMELEN 1536 2503#define BGE_JUMBO_FRAMELEN 9018 2504#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2505#define BGE_MIN_FRAMELEN 60 2506 2507/* 2508 * Other utility macros. 2509 / 2510#define BGE_INC(x, y) (x) = (x + 1) % y 2511* 2512/* 2513 * Register access macros. The Tigon always uses memory mapped register 2514 * accesses and all registers must be accessed with 32 bit operations. 2515 / 2516* 2517#define CSR_WRITE_4(sc, reg, val) \ 2518 bus_write_4(sc->bge_res, reg, val) 2519 2520#define CSR_READ_4(sc, reg) \ 2521 bus_read_4(sc->bge_res, reg) 2522 2523#define BGE_SETBIT(sc, reg, x) \ 2524 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2525#define BGE_CLRBIT(sc, reg, x) \ 2526 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2527 2528#define PCI_SETBIT(dev, reg, x, s) \ 2529 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2530#define PCI_CLRBIT(dev, reg, x, s) \ 2531 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2532 2533/* 2534 * Memory management stuff. 2535 / 2536* 2537#define BGE_NSEG_JUMBO 4 2538#define BGE_NSEG_NEW 32 2539#define BGE_TSOSEG_SZ 4096 2540 2541/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2542#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2543#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2544#else 2545#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2546#endif 2547* 2548#ifdef PAE 2549#define BGE_DMA_BNDRY 0x80000000 2550#else 2551#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2552#define BGE_DMA_BNDRY 0x100000000 2553#else 2554#define BGE_DMA_BNDRY 0 2555#endif 2556#endif 2557 2558/* 2559 * Ring structures. Most of these reside in host memory and we tell 2560 * the NIC where they are via the ring control blocks. The exceptions 2561 * are the tx and command rings, which live in NIC memory and which 2562 * we access via the shared memory window. 2563 / 2564* 2565struct bge_ring_data { 2566 struct bge_rx_bd bge_rx_std_ring; 2567* bus_addr_t bge_rx_std_ring_paddr; 2568 struct bge_extrx_bd bge_rx_jumbo_ring; 2569* bus_addr_t bge_rx_jumbo_ring_paddr; 2570 struct bge_rx_bd bge_rx_return_ring; 2571* bus_addr_t bge_rx_return_ring_paddr; 2572 struct bge_tx_bd bge_tx_ring; 2573* bus_addr_t bge_tx_ring_paddr; 2574 struct bge_status_block bge_status_block; 2575* bus_addr_t bge_status_block_paddr; 2576 struct bge_stats bge_stats; 2577* bus_addr_t bge_stats_paddr; 2578 struct bge_gib bge_info; 2579}; 2580 2581#define BGE_STD_RX_RING_SZ \ 2582 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2583#define BGE_JUMBO_RX_RING_SZ \ 2584 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2585#define BGE_TX_RING_SZ \ 2586 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2587#define BGE_RX_RTN_RING_SZ(x) \ 2588 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2589 2590#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2591 2592#define BGE_STATS_SZ sizeof (struct bge_stats) 2593 2594/* 2595 * Mbuf pointers. We need these to keep track of the virtual addresses 2596 * of our mbuf chains since we can only convert from physical to virtual, 2597 * not the other way around. 2598 / 2599struct bge_chain_data { 2600* bus_dma_tag_t bge_parent_tag; 2601 bus_dma_tag_t bge_buffer_tag; 2602 bus_dma_tag_t bge_rx_std_ring_tag; 2603 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2604 bus_dma_tag_t bge_rx_return_ring_tag; 2605 bus_dma_tag_t bge_tx_ring_tag; 2606 bus_dma_tag_t bge_status_tag; 2607 bus_dma_tag_t bge_stats_tag; 2608 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2609* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2610* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2611* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2612 bus_dmamap_t bge_rx_std_sparemap; 2613 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2614 bus_dmamap_t bge_rx_jumbo_sparemap; 2615 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2616 bus_dmamap_t bge_rx_std_ring_map; 2617 bus_dmamap_t bge_rx_jumbo_ring_map; 2618 bus_dmamap_t bge_tx_ring_map; 2619 bus_dmamap_t bge_rx_return_ring_map; 2620 bus_dmamap_t bge_status_map; 2621 bus_dmamap_t bge_stats_map; 2622 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2623* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2624* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2625* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2626 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2627}; 2628 2629struct bge_dmamap_arg { 2630 bus_addr_t bge_busaddr; 2631}; 2632 2633#define BGE_HWREV_TIGON 0x01 2634#define BGE_HWREV_TIGON_II 0x02 2635#define BGE_TIMEOUT 100000 2636#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2637* 2638struct bge_bcom_hack { 2639 int reg; 2640 int val; 2641}; 2642 2643#define ASF_ENABLE 1 2644#define ASF_NEW_HANDSHAKE 2 2645#define ASF_STACKUP 4 2646 2647struct bge_softc { 2648 struct ifnet bge_ifp; / interface info / 2649* device_t bge_dev; 2650 struct mtx bge_mtx; 2651 device_t bge_miibus; 2652 void bge_intrhand; 2653* struct resource bge_irq; 2654* struct resource bge_res; 2655* struct ifmedia bge_ifmedia; /* TBI media info / 2656* int bge_expcap; 2657 int bge_msicap; 2658 int bge_pcixcap; 2659 uint32_t bge_flags; 2660#define BGE_FLAG_TBI 0x00000001 2661#define BGE_FLAG_JUMBO 0x00000002 2662#define BGE_FLAG_WIRESPEED 0x00000004 2663#define BGE_FLAG_EADDR 0x00000008 2664#define BGE_FLAG_MII_SERDES 0x00000010 2665#define BGE_FLAG_MSI 0x00000100 2666#define BGE_FLAG_PCIX 0x00000200 2667#define BGE_FLAG_PCIE 0x00000400 2668#define BGE_FLAG_TSO 0x00000800 2669#define BGE_FLAG_5700_FAMILY 0x00001000 2670#define BGE_FLAG_5705_PLUS 0x00002000 2671#define BGE_FLAG_5714_FAMILY 0x00004000 2672#define BGE_FLAG_575X_PLUS 0x00008000 2673#define BGE_FLAG_5755_PLUS 0x00010000 2674#define BGE_FLAG_40BIT_BUG 0x00020000 2675#define BGE_FLAG_4G_BNDRY_BUG 0x00040000 2676#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2677#define BGE_FLAG_NO_3LED 0x00200000 2678#define BGE_FLAG_ADC_BUG 0x00400000 2679#define BGE_FLAG_5704_A0_BUG 0x00800000 2680#define BGE_FLAG_JITTER_BUG 0x01000000 2681#define BGE_FLAG_BER_BUG 0x02000000 2682#define BGE_FLAG_ADJUST_TRIM 0x04000000 2683#define BGE_FLAG_CRC_BUG 0x08000000 2684#define BGE_FLAG_5788 0x20000000 2685 uint32_t bge_chipid; 2686 uint32_t bge_asicrev; 2687 uint32_t bge_chiprev; 2688 uint8_t bge_asf_mode; 2689 uint8_t bge_asf_count; 2690 struct bge_ring_data bge_ldata; /* rings / 2691* struct bge_chain_data bge_cdata; /* mbufs / 2692* uint16_t bge_tx_saved_considx; 2693 uint16_t bge_rx_saved_considx; 2694 uint16_t bge_ev_saved_considx; 2695 uint16_t bge_return_ring_cnt; 2696 uint16_t bge_std; /* current std ring head / 2697* uint16_t bge_jumbo; /* current jumo ring head / 2698* uint32_t bge_stat_ticks; 2699 uint32_t bge_rx_coal_ticks; 2700 uint32_t bge_tx_coal_ticks; 2701 uint32_t bge_tx_prodidx; 2702 uint32_t bge_rx_max_coal_bds; 2703 uint32_t bge_tx_max_coal_bds; 2704 uint32_t bge_tx_buf_ratio; 2705 int bge_if_flags; 2706 int bge_txcnt; 2707 int bge_link; /* link state / 2708* int bge_link_evt; /* pending link event / 2709* int bge_timer; 2710 int bge_forced_collapse; 2711 int bge_forced_udpcsum; 2712 int bge_csum_features; 2713 struct callout bge_stat_ch; 2714 uint32_t bge_rx_discards; 2715 uint32_t bge_tx_discards; 2716 uint32_t bge_tx_collisions; 2717#ifdef DEVICE_POLLING 2718 int rxcycles; 2719#endif /* DEVICE_POLLING / 2720* struct bge_mac_stats bge_mac_stats; 2721 struct task bge_intr_task; 2722 struct taskqueue bge_tq; 2723}; 2724* 2725#define BGE_LOCK_INIT(_sc, _name) \ 2726 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2727#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2728#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2729#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2730#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)	1469/* 1470 * Write DMA control registers 1471 / 1472#define BGE_WDMA_MODE 0x4C00 1473#define BGE_WDMA_STATUS 0x4C04 1474* 1475/* Write DMA mode register / 1476#define BGE_WDMAMODE_RESET 0x00000001 1477#define BGE_WDMAMODE_ENABLE 0x00000002 1478#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1479#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1480#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1481#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1482#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1483#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1484#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1485#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1486#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1487#define BGE_WDMAMODE_STATUS_TAG_FIX 0x20000000 1488#define BGE_WDMAMODE_BURST_ALL_DATA 0xC0000000 1489* 1490/* Write DMA status register / 1491#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1492#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1493#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1494#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1495#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1496#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1497#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1498#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1499* 1500 1501/* 1502 * RX CPU registers 1503 / 1504#define BGE_RXCPU_MODE 0x5000 1505#define BGE_RXCPU_STATUS 0x5004 1506#define BGE_RXCPU_PC 0x501C 1507* 1508/* RX CPU mode register / 1509#define BGE_RXCPUMODE_RESET 0x00000001 1510#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1511#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1512#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1513#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1514#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1515#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1516#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1517#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1518#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1519#define BGE_RXCPUMODE_HALTCPU 0x00000400 1520#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1521#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1522#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1523* 1524/* RX CPU status register / 1525#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1526#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1527#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1528#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1529#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1530#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1531#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1532#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1533#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1534#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1535#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1536#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1537#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1538#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1539#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1540#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1541#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1542* 1543/* 1544 * V? CPU registers 1545 / 1546#define BGE_VCPU_STATUS 0x5100 1547#define BGE_VCPU_EXT_CTRL 0x6890 1548* 1549#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1550#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1551 1552#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1553#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1554 1555/* 1556 * TX CPU registers 1557 / 1558#define BGE_TXCPU_MODE 0x5400 1559#define BGE_TXCPU_STATUS 0x5404 1560#define BGE_TXCPU_PC 0x541C 1561* 1562/* TX CPU mode register / 1563#define BGE_TXCPUMODE_RESET 0x00000001 1564#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1565#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1566#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1567#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1568#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1569#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1570#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1571#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1572#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1573#define BGE_TXCPUMODE_HALTCPU 0x00000400 1574#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1575#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1576* 1577/* TX CPU status register / 1578#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1579#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1580#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1581#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1582#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1583#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1584#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1585#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1586#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1587#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1588#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1589#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1590#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1591#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1592#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1593#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1594#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1595* 1596 1597/* 1598 * Low priority mailbox registers 1599 / 1600#define BGE_LPMBX_IRQ0_HI 0x5800 1601#define BGE_LPMBX_IRQ0_LO 0x5804 1602#define BGE_LPMBX_IRQ1_HI 0x5808 1603#define BGE_LPMBX_IRQ1_LO 0x580C 1604#define BGE_LPMBX_IRQ2_HI 0x5810 1605#define BGE_LPMBX_IRQ2_LO 0x5814 1606#define BGE_LPMBX_IRQ3_HI 0x5818 1607#define BGE_LPMBX_IRQ3_LO 0x581C 1608#define BGE_LPMBX_GEN0_HI 0x5820 1609#define BGE_LPMBX_GEN0_LO 0x5824 1610#define BGE_LPMBX_GEN1_HI 0x5828 1611#define BGE_LPMBX_GEN1_LO 0x582C 1612#define BGE_LPMBX_GEN2_HI 0x5830 1613#define BGE_LPMBX_GEN2_LO 0x5834 1614#define BGE_LPMBX_GEN3_HI 0x5828 1615#define BGE_LPMBX_GEN3_LO 0x582C 1616#define BGE_LPMBX_GEN4_HI 0x5840 1617#define BGE_LPMBX_GEN4_LO 0x5844 1618#define BGE_LPMBX_GEN5_HI 0x5848 1619#define BGE_LPMBX_GEN5_LO 0x584C 1620#define BGE_LPMBX_GEN6_HI 0x5850 1621#define BGE_LPMBX_GEN6_LO 0x5854 1622#define BGE_LPMBX_GEN7_HI 0x5858 1623#define BGE_LPMBX_GEN7_LO 0x585C 1624#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1625#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1626#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1627#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1628#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1629#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1630#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1631#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1632#define BGE_LPMBX_RX_CONS0_HI 0x5880 1633#define BGE_LPMBX_RX_CONS0_LO 0x5884 1634#define BGE_LPMBX_RX_CONS1_HI 0x5888 1635#define BGE_LPMBX_RX_CONS1_LO 0x588C 1636#define BGE_LPMBX_RX_CONS2_HI 0x5890 1637#define BGE_LPMBX_RX_CONS2_LO 0x5894 1638#define BGE_LPMBX_RX_CONS3_HI 0x5898 1639#define BGE_LPMBX_RX_CONS3_LO 0x589C 1640#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1641#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1642#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1643#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1644#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1645#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1646#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1647#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1648#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1649#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1650#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1651#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1652#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1653#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1654#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1655#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1656#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1657#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1658#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1659#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1660#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1661#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1662#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1663#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1664#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1665#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1666#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1667#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1668#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1669#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1670#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1671#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1672#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1673#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1674#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1675#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1676#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1677#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1678#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1679#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1680#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1681#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1682#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1683#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1684#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1685#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1686#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1687#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1688#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1689#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1690#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1691#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1692#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1693#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1694#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1695#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1696#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1697#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1698#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1699#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1700#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1701#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1702#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1703#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1704#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1705#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1706#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1707#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1708#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1709#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1710#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1711#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1712#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1713#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1714#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1715#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1716#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1717#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1718#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1719#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1720#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1721#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1722#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1723#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1724#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1725#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1726#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1727#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1728* 1729/* 1730 * Flow throw Queue reset register 1731 / 1732#define BGE_FTQ_RESET 0x5C00 1733* 1734#define BGE_FTQRESET_DMAREAD 0x00000002 1735#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1736#define BGE_FTQRESET_DMADONE 0x00000010 1737#define BGE_FTQRESET_SBDC 0x00000020 1738#define BGE_FTQRESET_SDI 0x00000040 1739#define BGE_FTQRESET_WDMA 0x00000080 1740#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1741#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1742#define BGE_FTQRESET_SDC 0x00000400 1743#define BGE_FTQRESET_HCC 0x00000800 1744#define BGE_FTQRESET_TXFIFO 0x00001000 1745#define BGE_FTQRESET_MBC 0x00002000 1746#define BGE_FTQRESET_RBDC 0x00004000 1747#define BGE_FTQRESET_RXLP 0x00008000 1748#define BGE_FTQRESET_RDBDI 0x00010000 1749#define BGE_FTQRESET_RDC 0x00020000 1750#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1751 1752/* 1753 * Message Signaled Interrupt registers 1754 / 1755#define BGE_MSI_MODE 0x6000 1756#define BGE_MSI_STATUS 0x6004 1757#define BGE_MSI_FIFOACCESS 0x6008 1758* 1759/* MSI mode register / 1760#define BGE_MSIMODE_RESET 0x00000001 1761#define BGE_MSIMODE_ENABLE 0x00000002 1762#define BGE_MSIMODE_ONE_SHOT_DISABLE 0x00000020 1763#define BGE_MSIMODE_MULTIVEC_ENABLE 0x00000080 1764* 1765/* MSI status register / 1766#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1767#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1768#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1769#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1770#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1771* 1772 1773/* 1774 * DMA Completion registers 1775 / 1776#define BGE_DMAC_MODE 0x6400 1777* 1778/* DMA Completion mode register / 1779#define BGE_DMACMODE_RESET 0x00000001 1780#define BGE_DMACMODE_ENABLE 0x00000002 1781* 1782 1783/* 1784 * General control registers. 1785 / 1786#define BGE_MODE_CTL 0x6800 1787#define BGE_MISC_CFG 0x6804 1788#define BGE_MISC_LOCAL_CTL 0x6808 1789#define BGE_CPU_EVENT 0x6810 1790#define BGE_EE_ADDR 0x6838 1791#define BGE_EE_DATA 0x683C 1792#define BGE_EE_CTL 0x6840 1793#define BGE_MDI_CTL 0x6844 1794#define BGE_EE_DELAY 0x6848 1795#define BGE_FASTBOOT_PC 0x6894 1796* 1797/* 1798 * NVRAM Control registers 1799 / 1800#define BGE_NVRAM_CMD 0x7000 1801#define BGE_NVRAM_STAT 0x7004 1802#define BGE_NVRAM_WRDATA 0x7008 1803#define BGE_NVRAM_ADDR 0x700c 1804#define BGE_NVRAM_RDDATA 0x7010 1805#define BGE_NVRAM_CFG1 0x7014 1806#define BGE_NVRAM_CFG2 0x7018 1807#define BGE_NVRAM_CFG3 0x701c 1808#define BGE_NVRAM_SWARB 0x7020 1809#define BGE_NVRAM_ACCESS 0x7024 1810#define BGE_NVRAM_WRITE1 0x7028 1811* 1812#define BGE_NVRAMCMD_RESET 0x00000001 1813#define BGE_NVRAMCMD_DONE 0x00000008 1814#define BGE_NVRAMCMD_START 0x00000010 1815#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1816#define BGE_NVRAMCMD_ERASE 0x00000040 1817#define BGE_NVRAMCMD_FIRST 0x00000080 1818#define BGE_NVRAMCMD_LAST 0x00000100 1819* 1820#define BGE_NVRAM_READCMD \ 1821 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1822 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1823#define BGE_NVRAM_WRITECMD \ 1824 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1825 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1826 1827#define BGE_NVRAMSWARB_SET0 0x00000001 1828#define BGE_NVRAMSWARB_SET1 0x00000002 1829#define BGE_NVRAMSWARB_SET2 0x00000003 1830#define BGE_NVRAMSWARB_SET3 0x00000004 1831#define BGE_NVRAMSWARB_CLR0 0x00000010 1832#define BGE_NVRAMSWARB_CLR1 0x00000020 1833#define BGE_NVRAMSWARB_CLR2 0x00000040 1834#define BGE_NVRAMSWARB_CLR3 0x00000080 1835#define BGE_NVRAMSWARB_GNT0 0x00000100 1836#define BGE_NVRAMSWARB_GNT1 0x00000200 1837#define BGE_NVRAMSWARB_GNT2 0x00000400 1838#define BGE_NVRAMSWARB_GNT3 0x00000800 1839#define BGE_NVRAMSWARB_REQ0 0x00001000 1840#define BGE_NVRAMSWARB_REQ1 0x00002000 1841#define BGE_NVRAMSWARB_REQ2 0x00004000 1842#define BGE_NVRAMSWARB_REQ3 0x00008000 1843 1844#define BGE_NVRAMACC_ENABLE 0x00000001 1845#define BGE_NVRAMACC_WRENABLE 0x00000002 1846 1847/* Mode control register / 1848#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1849#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1850#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1851#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1852#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1853#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1854#define BGE_MODECTL_NO_RX_CRC 0x00000400 1855#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1856#define BGE_MODECTL_NO_TX_INTR 0x00002000 1857#define BGE_MODECTL_NO_RX_INTR 0x00004000 1858#define BGE_MODECTL_FORCE_PCI32 0x00008000 1859#define BGE_MODECTL_STACKUP 0x00010000 1860#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1861#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1862#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1863#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1864#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1865#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1866#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1867#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1868#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1869#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1870* 1871/* Misc. config register / 1872#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1873#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1874#define BGE_MISCCFG_BOARD_ID 0x0001E000 1875#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1876#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1877#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1878#define BGE_MISCCFG_GPHY_PD_OVERRIDE 0x04000000 1879* 1880#define BGE_32BITTIME_66MHZ (0x41 << 1) 1881 1882/* Misc. Local Control / 1883#define BGE_MLC_INTR_STATE 0x00000001 1884#define BGE_MLC_INTR_CLR 0x00000002 1885#define BGE_MLC_INTR_SET 0x00000004 1886#define BGE_MLC_INTR_ONATTN 0x00000008 1887#define BGE_MLC_MISCIO_IN0 0x00000100 1888#define BGE_MLC_MISCIO_IN1 0x00000200 1889#define BGE_MLC_MISCIO_IN2 0x00000400 1890#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1891#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1892#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1893#define BGE_MLC_MISCIO_OUT0 0x00004000 1894#define BGE_MLC_MISCIO_OUT1 0x00008000 1895#define BGE_MLC_MISCIO_OUT2 0x00010000 1896#define BGE_MLC_EXTRAM_ENB 0x00020000 1897#define BGE_MLC_SRAM_SIZE 0x001C0000 1898#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1899#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1900#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1901#define BGE_MLC_AUTO_EEPROM 0x01000000 1902* 1903#define BGE_SSRAMSIZE_256KB 0x00000000 1904#define BGE_SSRAMSIZE_512KB 0x00040000 1905#define BGE_SSRAMSIZE_1MB 0x00080000 1906#define BGE_SSRAMSIZE_2MB 0x000C0000 1907#define BGE_SSRAMSIZE_4MB 0x00100000 1908#define BGE_SSRAMSIZE_8MB 0x00140000 1909#define BGE_SSRAMSIZE_16M 0x00180000 1910 1911/* EEPROM address register / 1912#define BGE_EEADDR_ADDRESS 0x0000FFFC 1913#define BGE_EEADDR_HALFCLK 0x01FF0000 1914#define BGE_EEADDR_START 0x02000000 1915#define BGE_EEADDR_DEVID 0x1C000000 1916#define BGE_EEADDR_RESET 0x20000000 1917#define BGE_EEADDR_DONE 0x40000000 1918#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1919* 1920#define BGE_EEDEVID(x) ((x & 7) << 26) 1921#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1922#define BGE_HALFCLK_384SCL 0x60 1923#define BGE_EE_READCMD \ 1924 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1925 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1926#define BGE_EE_WRCMD \ 1927 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1928 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1929 1930/* EEPROM Control register / 1931#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1932#define BGE_EECTL_CLKOUT 0x00000002 1933#define BGE_EECTL_CLKIN 0x00000004 1934#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1935#define BGE_EECTL_DATAOUT 0x00000010 1936#define BGE_EECTL_DATAIN 0x00000020 1937* 1938/* MDI (MII/GMII) access register / 1939#define BGE_MDI_DATA 0x00000001 1940#define BGE_MDI_DIR 0x00000002 1941#define BGE_MDI_SEL 0x00000004 1942#define BGE_MDI_CLK 0x00000008 1943* 1944#define BGE_MEMWIN_START 0x00008000 1945#define BGE_MEMWIN_END 0x0000FFFF 1946 1947 1948#define BGE_MEMWIN_READ(sc, x, val) \ 1949 do { \ 1950 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1951 (0xFFFF0000 & x), 4); \ 1952 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1953 } while(0) 1954 1955#define BGE_MEMWIN_WRITE(sc, x, val) \ 1956 do { \ 1957 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1958 (0xFFFF0000 & x), 4); \ 1959 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1960 } while(0) 1961 1962/* 1963 * This magic number is written to the firmware mailbox at 0xb50 1964 * before a software reset is issued. After the internal firmware 1965 * has completed its initialization it will write the opposite of 1966 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1967 * driver to synchronize with the firmware. 1968 / 1969#define BGE_MAGIC_NUMBER 0x4B657654 1970* 1971typedef struct { 1972 uint32_t bge_addr_hi; 1973 uint32_t bge_addr_lo; 1974} bge_hostaddr; 1975 1976#define BGE_HOSTADDR(x, y) \ 1977 do { \ 1978 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1979 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1980 } while(0) 1981 1982#define BGE_ADDR_LO(y) \ 1983 ((uint64_t) (y) & 0xFFFFFFFF) 1984#define BGE_ADDR_HI(y) \ 1985 ((uint64_t) (y) >> 32) 1986 1987/* Ring control block structure / 1988struct bge_rcb { 1989* bge_hostaddr bge_hostaddr; 1990 uint32_t bge_maxlen_flags; 1991 uint32_t bge_nicaddr; 1992}; 1993 1994#define RCB_WRITE_4(sc, rcb, offset, val) \ 1995 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1996#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1997 1998#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1999#define BGE_RCB_FLAG_RING_DISABLED 0x0002 2000 2001struct bge_tx_bd { 2002 bge_hostaddr bge_addr; 2003#if BYTE_ORDER == LITTLE_ENDIAN 2004 uint16_t bge_flags; 2005 uint16_t bge_len; 2006 uint16_t bge_vlan_tag; 2007 uint16_t bge_mss; 2008#else 2009 uint16_t bge_len; 2010 uint16_t bge_flags; 2011 uint16_t bge_mss; 2012 uint16_t bge_vlan_tag; 2013#endif 2014}; 2015 2016#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 2017#define BGE_TXBDFLAG_IP_CSUM 0x0002 2018#define BGE_TXBDFLAG_END 0x0004 2019#define BGE_TXBDFLAG_IP_FRAG 0x0008 2020#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 2021#define BGE_TXBDFLAG_VLAN_TAG 0x0040 2022#define BGE_TXBDFLAG_COAL_NOW 0x0080 2023#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 2024#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 2025#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 2026#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 2027#define BGE_TXBDFLAG_NO_CRC 0x8000 2028 2029#define BGE_NIC_TXRING_ADDR(ringno, size) \ 2030 BGE_SEND_RING_1_TO_4 + \ 2031 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 2032 2033struct bge_rx_bd { 2034 bge_hostaddr bge_addr; 2035#if BYTE_ORDER == LITTLE_ENDIAN 2036 uint16_t bge_len; 2037 uint16_t bge_idx; 2038 uint16_t bge_flags; 2039 uint16_t bge_type; 2040 uint16_t bge_tcp_udp_csum; 2041 uint16_t bge_ip_csum; 2042 uint16_t bge_vlan_tag; 2043 uint16_t bge_error_flag; 2044#else 2045 uint16_t bge_idx; 2046 uint16_t bge_len; 2047 uint16_t bge_type; 2048 uint16_t bge_flags; 2049 uint16_t bge_ip_csum; 2050 uint16_t bge_tcp_udp_csum; 2051 uint16_t bge_error_flag; 2052 uint16_t bge_vlan_tag; 2053#endif 2054 uint32_t bge_rsvd; 2055 uint32_t bge_opaque; 2056}; 2057 2058struct bge_extrx_bd { 2059 bge_hostaddr bge_addr1; 2060 bge_hostaddr bge_addr2; 2061 bge_hostaddr bge_addr3; 2062#if BYTE_ORDER == LITTLE_ENDIAN 2063 uint16_t bge_len2; 2064 uint16_t bge_len1; 2065 uint16_t bge_rsvd1; 2066 uint16_t bge_len3; 2067#else 2068 uint16_t bge_len1; 2069 uint16_t bge_len2; 2070 uint16_t bge_len3; 2071 uint16_t bge_rsvd1; 2072#endif 2073 bge_hostaddr bge_addr0; 2074#if BYTE_ORDER == LITTLE_ENDIAN 2075 uint16_t bge_len0; 2076 uint16_t bge_idx; 2077 uint16_t bge_flags; 2078 uint16_t bge_type; 2079 uint16_t bge_tcp_udp_csum; 2080 uint16_t bge_ip_csum; 2081 uint16_t bge_vlan_tag; 2082 uint16_t bge_error_flag; 2083#else 2084 uint16_t bge_idx; 2085 uint16_t bge_len0; 2086 uint16_t bge_type; 2087 uint16_t bge_flags; 2088 uint16_t bge_ip_csum; 2089 uint16_t bge_tcp_udp_csum; 2090 uint16_t bge_error_flag; 2091 uint16_t bge_vlan_tag; 2092#endif 2093 uint32_t bge_rsvd0; 2094 uint32_t bge_opaque; 2095}; 2096 2097#define BGE_RXBDFLAG_END 0x0004 2098#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2099#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2100#define BGE_RXBDFLAG_ERROR 0x0400 2101#define BGE_RXBDFLAG_MINI_RING 0x0800 2102#define BGE_RXBDFLAG_IP_CSUM 0x1000 2103#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2104#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2105 2106#define BGE_RXERRFLAG_BAD_CRC 0x0001 2107#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2108#define BGE_RXERRFLAG_LINK_LOST 0x0004 2109#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2110#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2111#define BGE_RXERRFLAG_RUNT 0x0020 2112#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2113#define BGE_RXERRFLAG_GIANT 0x0080 2114 2115struct bge_sts_idx { 2116#if BYTE_ORDER == LITTLE_ENDIAN 2117 uint16_t bge_rx_prod_idx; 2118 uint16_t bge_tx_cons_idx; 2119#else 2120 uint16_t bge_tx_cons_idx; 2121 uint16_t bge_rx_prod_idx; 2122#endif 2123}; 2124 2125struct bge_status_block { 2126 uint32_t bge_status; 2127 uint32_t bge_rsvd0; 2128#if BYTE_ORDER == LITTLE_ENDIAN 2129 uint16_t bge_rx_jumbo_cons_idx; 2130 uint16_t bge_rx_std_cons_idx; 2131 uint16_t bge_rx_mini_cons_idx; 2132 uint16_t bge_rsvd1; 2133#else 2134 uint16_t bge_rx_std_cons_idx; 2135 uint16_t bge_rx_jumbo_cons_idx; 2136 uint16_t bge_rsvd1; 2137 uint16_t bge_rx_mini_cons_idx; 2138#endif 2139 struct bge_sts_idx bge_idx[16]; 2140}; 2141 2142#define BGE_STATFLAG_UPDATED 0x00000001 2143#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2144#define BGE_STATFLAG_ERROR 0x00000004 2145 2146 2147/* 2148 * Broadcom Vendor ID 2149 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2150 * even though they're now manufactured by Broadcom) 2151 / 2152#define BCOM_VENDORID 0x14E4 2153#define BCOM_DEVICEID_BCM5700 0x1644 2154#define BCOM_DEVICEID_BCM5701 0x1645 2155#define BCOM_DEVICEID_BCM5702 0x1646 2156#define BCOM_DEVICEID_BCM5702X 0x16A6 2157#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2158#define BCOM_DEVICEID_BCM5703 0x1647 2159#define BCOM_DEVICEID_BCM5703X 0x16A7 2160#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2161#define BCOM_DEVICEID_BCM5704C 0x1648 2162#define BCOM_DEVICEID_BCM5704S 0x16A8 2163#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2164#define BCOM_DEVICEID_BCM5705 0x1653 2165#define BCOM_DEVICEID_BCM5705K 0x1654 2166#define BCOM_DEVICEID_BCM5705F 0x166E 2167#define BCOM_DEVICEID_BCM5705M 0x165D 2168#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2169#define BCOM_DEVICEID_BCM5714C 0x1668 2170#define BCOM_DEVICEID_BCM5714S 0x1669 2171#define BCOM_DEVICEID_BCM5715 0x1678 2172#define BCOM_DEVICEID_BCM5715S 0x1679 2173#define BCOM_DEVICEID_BCM5720 0x1658 2174#define BCOM_DEVICEID_BCM5721 0x1659 2175#define BCOM_DEVICEID_BCM5722 0x165A 2176#define BCOM_DEVICEID_BCM5723 0x165B 2177#define BCOM_DEVICEID_BCM5750 0x1676 2178#define BCOM_DEVICEID_BCM5750M 0x167C 2179#define BCOM_DEVICEID_BCM5751 0x1677 2180#define BCOM_DEVICEID_BCM5751F 0x167E 2181#define BCOM_DEVICEID_BCM5751M 0x167D 2182#define BCOM_DEVICEID_BCM5752 0x1600 2183#define BCOM_DEVICEID_BCM5752M 0x1601 2184#define BCOM_DEVICEID_BCM5753 0x16F7 2185#define BCOM_DEVICEID_BCM5753F 0x16FE 2186#define BCOM_DEVICEID_BCM5753M 0x16FD 2187#define BCOM_DEVICEID_BCM5754 0x167A 2188#define BCOM_DEVICEID_BCM5754M 0x1672 2189#define BCOM_DEVICEID_BCM5755 0x167B 2190#define BCOM_DEVICEID_BCM5755M 0x1673 2191#define BCOM_DEVICEID_BCM5756 0x1674 2192#define BCOM_DEVICEID_BCM5761 0x1681 2193#define BCOM_DEVICEID_BCM5761E 0x1680 2194#define BCOM_DEVICEID_BCM5761S 0x1688 2195#define BCOM_DEVICEID_BCM5761SE 0x1689 2196#define BCOM_DEVICEID_BCM5764 0x1684 2197#define BCOM_DEVICEID_BCM5780 0x166A 2198#define BCOM_DEVICEID_BCM5780S 0x166B 2199#define BCOM_DEVICEID_BCM5781 0x16DD 2200#define BCOM_DEVICEID_BCM5782 0x1696 2201#define BCOM_DEVICEID_BCM5784 0x1698 2202#define BCOM_DEVICEID_BCM5785F 0x16a0 2203#define BCOM_DEVICEID_BCM5785G 0x1699 2204#define BCOM_DEVICEID_BCM5786 0x169A 2205#define BCOM_DEVICEID_BCM5787 0x169B 2206#define BCOM_DEVICEID_BCM5787M 0x1693 2207#define BCOM_DEVICEID_BCM5787F 0x167f 2208#define BCOM_DEVICEID_BCM5788 0x169C 2209#define BCOM_DEVICEID_BCM5789 0x169D 2210#define BCOM_DEVICEID_BCM5901 0x170D 2211#define BCOM_DEVICEID_BCM5901A2 0x170E 2212#define BCOM_DEVICEID_BCM5903M 0x16FF 2213#define BCOM_DEVICEID_BCM5906 0x1712 2214#define BCOM_DEVICEID_BCM5906M 0x1713 2215#define BCOM_DEVICEID_BCM57760 0x1690 2216#define BCOM_DEVICEID_BCM57780 0x1692 2217#define BCOM_DEVICEID_BCM57788 0x1691 2218#define BCOM_DEVICEID_BCM57790 0x1694 2219* 2220/* 2221 * Alteon AceNIC PCI vendor/device ID. 2222 / 2223#define ALTEON_VENDORID 0x12AE 2224#define ALTEON_DEVICEID_ACENIC 0x0001 2225#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2226#define ALTEON_DEVICEID_BCM5700 0x0003 2227#define ALTEON_DEVICEID_BCM5701 0x0004 2228* 2229/* 2230 * 3Com 3c996 PCI vendor/device ID. 2231 / 2232#define TC_VENDORID 0x10B7 2233#define TC_DEVICEID_3C996 0x0003 2234* 2235/* 2236 * SysKonnect PCI vendor ID 2237 / 2238#define SK_VENDORID 0x1148 2239#define SK_DEVICEID_ALTIMA 0x4400 2240#define SK_SUBSYSID_9D21 0x4421 2241#define SK_SUBSYSID_9D41 0x4441 2242* 2243/* 2244 * Altima PCI vendor/device ID. 2245 / 2246#define ALTIMA_VENDORID 0x173b 2247#define ALTIMA_DEVICE_AC1000 0x03e8 2248#define ALTIMA_DEVICE_AC1002 0x03e9 2249#define ALTIMA_DEVICE_AC9100 0x03ea 2250* 2251/* 2252 * Dell PCI vendor ID 2253 / 2254* 2255#define DELL_VENDORID 0x1028 2256 2257/* 2258 * Apple PCI vendor ID. 2259 / 2260#define APPLE_VENDORID 0x106b 2261#define APPLE_DEVICE_BCM5701 0x1645 2262* 2263/* 2264 * Sun PCI vendor ID 2265 / 2266#define SUN_VENDORID 0x108e 2267* 2268/* 2269 * Fujitsu vendor/device IDs 2270 / 2271#define FJTSU_VENDORID 0x10cf 2272#define FJTSU_DEVICEID_PW008GE5 0x11a1 2273#define FJTSU_DEVICEID_PW008GE4 0x11a2 2274#define FJTSU_DEVICEID_PP250450 0x11cc / PRIMEPOWER250/450 LAN / 2275* 2276/* 2277 * Offset of MAC address inside EEPROM. 2278 / 2279#define BGE_EE_MAC_OFFSET 0x7C 2280#define BGE_EE_MAC_OFFSET_5906 0x10 2281#define BGE_EE_HWCFG_OFFSET 0xC8 2282* 2283#define BGE_HWCFG_VOLTAGE 0x00000003 2284#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2285#define BGE_HWCFG_MEDIA 0x00000030 2286#define BGE_HWCFG_ASF 0x00000080 2287 2288#define BGE_VOLTAGE_1POINT3 0x00000000 2289#define BGE_VOLTAGE_1POINT8 0x00000001 2290 2291#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2292#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2293#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2294 2295#define BGE_MEDIA_UNSPEC 0x00000000 2296#define BGE_MEDIA_COPPER 0x00000010 2297#define BGE_MEDIA_FIBER 0x00000020 2298 2299#define BGE_TICKS_PER_SEC 1000000 2300 2301/* 2302 * Ring size constants. 2303 / 2304#define BGE_EVENT_RING_CNT 256 2305#define BGE_CMD_RING_CNT 64 2306#define BGE_STD_RX_RING_CNT 512 2307#define BGE_JUMBO_RX_RING_CNT 256 2308#define BGE_MINI_RX_RING_CNT 1024 2309#define BGE_RETURN_RING_CNT 1024 2310* 2311/* 5705 has smaller return ring size / 2312* 2313#define BGE_RETURN_RING_CNT_5705 512 2314 2315/* 2316 * Possible TX ring sizes. 2317 / 2318#define BGE_TX_RING_CNT_128 128 2319#define BGE_TX_RING_BASE_128 0x3800 2320* 2321#define BGE_TX_RING_CNT_256 256 2322#define BGE_TX_RING_BASE_256 0x3000 2323 2324#define BGE_TX_RING_CNT_512 512 2325#define BGE_TX_RING_BASE_512 0x2000 2326 2327#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2328#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2329 2330/* 2331 * Tigon III statistics counters. 2332 / 2333/ Statistics maintained MAC Receive block. / 2334struct bge_rx_mac_stats { 2335* bge_hostaddr ifHCInOctets; 2336 bge_hostaddr Reserved1; 2337 bge_hostaddr etherStatsFragments; 2338 bge_hostaddr ifHCInUcastPkts; 2339 bge_hostaddr ifHCInMulticastPkts; 2340 bge_hostaddr ifHCInBroadcastPkts; 2341 bge_hostaddr dot3StatsFCSErrors; 2342 bge_hostaddr dot3StatsAlignmentErrors; 2343 bge_hostaddr xonPauseFramesReceived; 2344 bge_hostaddr xoffPauseFramesReceived; 2345 bge_hostaddr macControlFramesReceived; 2346 bge_hostaddr xoffStateEntered; 2347 bge_hostaddr dot3StatsFramesTooLong; 2348 bge_hostaddr etherStatsJabbers; 2349 bge_hostaddr etherStatsUndersizePkts; 2350 bge_hostaddr inRangeLengthError; 2351 bge_hostaddr outRangeLengthError; 2352 bge_hostaddr etherStatsPkts64Octets; 2353 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2354 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2355 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2356 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2357 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2358 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2359 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2360 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2361 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2362}; 2363 2364 2365/* Statistics maintained MAC Transmit block. / 2366struct bge_tx_mac_stats { 2367* bge_hostaddr ifHCOutOctets; 2368 bge_hostaddr Reserved2; 2369 bge_hostaddr etherStatsCollisions; 2370 bge_hostaddr outXonSent; 2371 bge_hostaddr outXoffSent; 2372 bge_hostaddr flowControlDone; 2373 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2374 bge_hostaddr dot3StatsSingleCollisionFrames; 2375 bge_hostaddr dot3StatsMultipleCollisionFrames; 2376 bge_hostaddr dot3StatsDeferredTransmissions; 2377 bge_hostaddr Reserved3; 2378 bge_hostaddr dot3StatsExcessiveCollisions; 2379 bge_hostaddr dot3StatsLateCollisions; 2380 bge_hostaddr dot3Collided2Times; 2381 bge_hostaddr dot3Collided3Times; 2382 bge_hostaddr dot3Collided4Times; 2383 bge_hostaddr dot3Collided5Times; 2384 bge_hostaddr dot3Collided6Times; 2385 bge_hostaddr dot3Collided7Times; 2386 bge_hostaddr dot3Collided8Times; 2387 bge_hostaddr dot3Collided9Times; 2388 bge_hostaddr dot3Collided10Times; 2389 bge_hostaddr dot3Collided11Times; 2390 bge_hostaddr dot3Collided12Times; 2391 bge_hostaddr dot3Collided13Times; 2392 bge_hostaddr dot3Collided14Times; 2393 bge_hostaddr dot3Collided15Times; 2394 bge_hostaddr ifHCOutUcastPkts; 2395 bge_hostaddr ifHCOutMulticastPkts; 2396 bge_hostaddr ifHCOutBroadcastPkts; 2397 bge_hostaddr dot3StatsCarrierSenseErrors; 2398 bge_hostaddr ifOutDiscards; 2399 bge_hostaddr ifOutErrors; 2400}; 2401 2402/* Stats counters access through registers / 2403struct bge_mac_stats { 2404* /* TX MAC statistics / 2405* uint64_t ifHCOutOctets; 2406 uint64_t Reserved0; 2407 uint64_t etherStatsCollisions; 2408 uint64_t outXonSent; 2409 uint64_t outXoffSent; 2410 uint64_t Reserved1; 2411 uint64_t dot3StatsInternalMacTransmitErrors; 2412 uint64_t dot3StatsSingleCollisionFrames; 2413 uint64_t dot3StatsMultipleCollisionFrames; 2414 uint64_t dot3StatsDeferredTransmissions; 2415 uint64_t Reserved2; 2416 uint64_t dot3StatsExcessiveCollisions; 2417 uint64_t dot3StatsLateCollisions; 2418 uint64_t Reserved3[14]; 2419 uint64_t ifHCOutUcastPkts; 2420 uint64_t ifHCOutMulticastPkts; 2421 uint64_t ifHCOutBroadcastPkts; 2422 uint64_t Reserved4[2]; 2423 /* RX MAC statistics / 2424* uint64_t ifHCInOctets; 2425 uint64_t Reserved5; 2426 uint64_t etherStatsFragments; 2427 uint64_t ifHCInUcastPkts; 2428 uint64_t ifHCInMulticastPkts; 2429 uint64_t ifHCInBroadcastPkts; 2430 uint64_t dot3StatsFCSErrors; 2431 uint64_t dot3StatsAlignmentErrors; 2432 uint64_t xonPauseFramesReceived; 2433 uint64_t xoffPauseFramesReceived; 2434 uint64_t macControlFramesReceived; 2435 uint64_t xoffStateEntered; 2436 uint64_t dot3StatsFramesTooLong; 2437 uint64_t etherStatsJabbers; 2438 uint64_t etherStatsUndersizePkts; 2439 /* Receive List Placement control / 2440* uint64_t FramesDroppedDueToFilters; 2441 uint64_t DmaWriteQueueFull; 2442 uint64_t DmaWriteHighPriQueueFull; 2443 uint64_t NoMoreRxBDs; 2444 uint64_t InputDiscards; 2445 uint64_t InputErrors; 2446 uint64_t RecvThresholdHit; 2447}; 2448 2449struct bge_stats { 2450 uint8_t Reserved0[256]; 2451 2452 /* Statistics maintained by Receive MAC. / 2453* struct bge_rx_mac_stats rxstats; 2454 2455 bge_hostaddr Unused1[37]; 2456 2457 /* Statistics maintained by Transmit MAC. / 2458* struct bge_tx_mac_stats txstats; 2459 2460 bge_hostaddr Unused2[31]; 2461 2462 /* Statistics maintained by Receive List Placement. / 2463* bge_hostaddr COSIfHCInPkts[16]; 2464 bge_hostaddr COSFramesDroppedDueToFilters; 2465 bge_hostaddr nicDmaWriteQueueFull; 2466 bge_hostaddr nicDmaWriteHighPriQueueFull; 2467 bge_hostaddr nicNoMoreRxBDs; 2468 bge_hostaddr ifInDiscards; 2469 bge_hostaddr ifInErrors; 2470 bge_hostaddr nicRecvThresholdHit; 2471 2472 bge_hostaddr Unused3[9]; 2473 2474 /* Statistics maintained by Send Data Initiator. / 2475* bge_hostaddr COSIfHCOutPkts[16]; 2476 bge_hostaddr nicDmaReadQueueFull; 2477 bge_hostaddr nicDmaReadHighPriQueueFull; 2478 bge_hostaddr nicSendDataCompQueueFull; 2479 2480 /* Statistics maintained by Host Coalescing. / 2481* bge_hostaddr nicRingSetSendProdIndex; 2482 bge_hostaddr nicRingStatusUpdate; 2483 bge_hostaddr nicInterrupts; 2484 bge_hostaddr nicAvoidedInterrupts; 2485 bge_hostaddr nicSendThresholdHit; 2486 2487 uint8_t Reserved4[320]; 2488}; 2489 2490/* 2491 * Tigon general information block. This resides in host memory 2492 * and contains the status counters, ring control blocks and 2493 * producer pointers. 2494 / 2495* 2496struct bge_gib { 2497 struct bge_stats bge_stats; 2498 struct bge_rcb bge_tx_rcb[16]; 2499 struct bge_rcb bge_std_rx_rcb; 2500 struct bge_rcb bge_jumbo_rx_rcb; 2501 struct bge_rcb bge_mini_rx_rcb; 2502 struct bge_rcb bge_return_rcb; 2503}; 2504 2505#define BGE_FRAMELEN 1518 2506#define BGE_MAX_FRAMELEN 1536 2507#define BGE_JUMBO_FRAMELEN 9018 2508#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2509#define BGE_MIN_FRAMELEN 60 2510 2511/* 2512 * Other utility macros. 2513 / 2514#define BGE_INC(x, y) (x) = (x + 1) % y 2515* 2516/* 2517 * Register access macros. The Tigon always uses memory mapped register 2518 * accesses and all registers must be accessed with 32 bit operations. 2519 / 2520* 2521#define CSR_WRITE_4(sc, reg, val) \ 2522 bus_write_4(sc->bge_res, reg, val) 2523 2524#define CSR_READ_4(sc, reg) \ 2525 bus_read_4(sc->bge_res, reg) 2526 2527#define BGE_SETBIT(sc, reg, x) \ 2528 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2529#define BGE_CLRBIT(sc, reg, x) \ 2530 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2531 2532#define PCI_SETBIT(dev, reg, x, s) \ 2533 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2534#define PCI_CLRBIT(dev, reg, x, s) \ 2535 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2536 2537/* 2538 * Memory management stuff. 2539 / 2540* 2541#define BGE_NSEG_JUMBO 4 2542#define BGE_NSEG_NEW 32 2543#define BGE_TSOSEG_SZ 4096 2544 2545/* Maximum DMA address for controllers that have 40bit DMA address bug. / 2546#if (BUS_SPACE_MAXADDR < 0xFFFFFFFFFF) 2547#define BGE_DMA_MAXADDR BUS_SPACE_MAXADDR 2548#else 2549#define BGE_DMA_MAXADDR 0xFFFFFFFFFF 2550#endif 2551* 2552#ifdef PAE 2553#define BGE_DMA_BNDRY 0x80000000 2554#else 2555#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 2556#define BGE_DMA_BNDRY 0x100000000 2557#else 2558#define BGE_DMA_BNDRY 0 2559#endif 2560#endif 2561 2562/* 2563 * Ring structures. Most of these reside in host memory and we tell 2564 * the NIC where they are via the ring control blocks. The exceptions 2565 * are the tx and command rings, which live in NIC memory and which 2566 * we access via the shared memory window. 2567 / 2568* 2569struct bge_ring_data { 2570 struct bge_rx_bd bge_rx_std_ring; 2571* bus_addr_t bge_rx_std_ring_paddr; 2572 struct bge_extrx_bd bge_rx_jumbo_ring; 2573* bus_addr_t bge_rx_jumbo_ring_paddr; 2574 struct bge_rx_bd bge_rx_return_ring; 2575* bus_addr_t bge_rx_return_ring_paddr; 2576 struct bge_tx_bd bge_tx_ring; 2577* bus_addr_t bge_tx_ring_paddr; 2578 struct bge_status_block bge_status_block; 2579* bus_addr_t bge_status_block_paddr; 2580 struct bge_stats bge_stats; 2581* bus_addr_t bge_stats_paddr; 2582 struct bge_gib bge_info; 2583}; 2584 2585#define BGE_STD_RX_RING_SZ \ 2586 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2587#define BGE_JUMBO_RX_RING_SZ \ 2588 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2589#define BGE_TX_RING_SZ \ 2590 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2591#define BGE_RX_RTN_RING_SZ(x) \ 2592 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2593 2594#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2595 2596#define BGE_STATS_SZ sizeof (struct bge_stats) 2597 2598/* 2599 * Mbuf pointers. We need these to keep track of the virtual addresses 2600 * of our mbuf chains since we can only convert from physical to virtual, 2601 * not the other way around. 2602 / 2603struct bge_chain_data { 2604* bus_dma_tag_t bge_parent_tag; 2605 bus_dma_tag_t bge_buffer_tag; 2606 bus_dma_tag_t bge_rx_std_ring_tag; 2607 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2608 bus_dma_tag_t bge_rx_return_ring_tag; 2609 bus_dma_tag_t bge_tx_ring_tag; 2610 bus_dma_tag_t bge_status_tag; 2611 bus_dma_tag_t bge_stats_tag; 2612 bus_dma_tag_t bge_rx_mtag; /* Rx mbuf mapping tag / 2613* bus_dma_tag_t bge_tx_mtag; /* Tx mbuf mapping tag / 2614* bus_dma_tag_t bge_mtag_jumbo; /* Jumbo mbuf mapping tag / 2615* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2616 bus_dmamap_t bge_rx_std_sparemap; 2617 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2618 bus_dmamap_t bge_rx_jumbo_sparemap; 2619 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2620 bus_dmamap_t bge_rx_std_ring_map; 2621 bus_dmamap_t bge_rx_jumbo_ring_map; 2622 bus_dmamap_t bge_tx_ring_map; 2623 bus_dmamap_t bge_rx_return_ring_map; 2624 bus_dmamap_t bge_status_map; 2625 bus_dmamap_t bge_stats_map; 2626 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2627* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2628* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2629* int bge_rx_std_seglen[BGE_STD_RX_RING_CNT]; 2630 int bge_rx_jumbo_seglen[BGE_JUMBO_RX_RING_CNT][4]; 2631}; 2632 2633struct bge_dmamap_arg { 2634 bus_addr_t bge_busaddr; 2635}; 2636 2637#define BGE_HWREV_TIGON 0x01 2638#define BGE_HWREV_TIGON_II 0x02 2639#define BGE_TIMEOUT 100000 2640#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2641* 2642struct bge_bcom_hack { 2643 int reg; 2644 int val; 2645}; 2646 2647#define ASF_ENABLE 1 2648#define ASF_NEW_HANDSHAKE 2 2649#define ASF_STACKUP 4 2650 2651struct bge_softc { 2652 struct ifnet bge_ifp; / interface info / 2653* device_t bge_dev; 2654 struct mtx bge_mtx; 2655 device_t bge_miibus; 2656 void bge_intrhand; 2657* struct resource bge_irq; 2658* struct resource bge_res; 2659* struct ifmedia bge_ifmedia; /* TBI media info / 2660* int bge_expcap; 2661 int bge_msicap; 2662 int bge_pcixcap; 2663 uint32_t bge_flags; 2664#define BGE_FLAG_TBI 0x00000001 2665#define BGE_FLAG_JUMBO 0x00000002 2666#define BGE_FLAG_WIRESPEED 0x00000004 2667#define BGE_FLAG_EADDR 0x00000008 2668#define BGE_FLAG_MII_SERDES 0x00000010 2669#define BGE_FLAG_MSI 0x00000100 2670#define BGE_FLAG_PCIX 0x00000200 2671#define BGE_FLAG_PCIE 0x00000400 2672#define BGE_FLAG_TSO 0x00000800 2673#define BGE_FLAG_5700_FAMILY 0x00001000 2674#define BGE_FLAG_5705_PLUS 0x00002000 2675#define BGE_FLAG_5714_FAMILY 0x00004000 2676#define BGE_FLAG_575X_PLUS 0x00008000 2677#define BGE_FLAG_5755_PLUS 0x00010000 2678#define BGE_FLAG_40BIT_BUG 0x00020000 2679#define BGE_FLAG_4G_BNDRY_BUG 0x00040000 2680#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2681#define BGE_FLAG_NO_3LED 0x00200000 2682#define BGE_FLAG_ADC_BUG 0x00400000 2683#define BGE_FLAG_5704_A0_BUG 0x00800000 2684#define BGE_FLAG_JITTER_BUG 0x01000000 2685#define BGE_FLAG_BER_BUG 0x02000000 2686#define BGE_FLAG_ADJUST_TRIM 0x04000000 2687#define BGE_FLAG_CRC_BUG 0x08000000 2688#define BGE_FLAG_5788 0x20000000 2689 uint32_t bge_chipid; 2690 uint32_t bge_asicrev; 2691 uint32_t bge_chiprev; 2692 uint8_t bge_asf_mode; 2693 uint8_t bge_asf_count; 2694 struct bge_ring_data bge_ldata; /* rings / 2695* struct bge_chain_data bge_cdata; /* mbufs / 2696* uint16_t bge_tx_saved_considx; 2697 uint16_t bge_rx_saved_considx; 2698 uint16_t bge_ev_saved_considx; 2699 uint16_t bge_return_ring_cnt; 2700 uint16_t bge_std; /* current std ring head / 2701* uint16_t bge_jumbo; /* current jumo ring head / 2702* uint32_t bge_stat_ticks; 2703 uint32_t bge_rx_coal_ticks; 2704 uint32_t bge_tx_coal_ticks; 2705 uint32_t bge_tx_prodidx; 2706 uint32_t bge_rx_max_coal_bds; 2707 uint32_t bge_tx_max_coal_bds; 2708 uint32_t bge_tx_buf_ratio; 2709 int bge_if_flags; 2710 int bge_txcnt; 2711 int bge_link; /* link state / 2712* int bge_link_evt; /* pending link event / 2713* int bge_timer; 2714 int bge_forced_collapse; 2715 int bge_forced_udpcsum; 2716 int bge_csum_features; 2717 struct callout bge_stat_ch; 2718 uint32_t bge_rx_discards; 2719 uint32_t bge_tx_discards; 2720 uint32_t bge_tx_collisions; 2721#ifdef DEVICE_POLLING 2722 int rxcycles; 2723#endif /* DEVICE_POLLING / 2724* struct bge_mac_stats bge_mac_stats; 2725 struct task bge_intr_task; 2726 struct taskqueue bge_tq; 2727}; 2728* 2729#define BGE_LOCK_INIT(_sc, _name) \ 2730 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2731#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2732#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2733#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2734#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)