Cross Reference: /freebsd-11.0-release/sys/dev/bge/if_bgereg.h

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1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *	1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 190194 2009-03-21 00:23:07Z marius $	33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 190319 2009-03-23 14:36:50Z marius $
34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221* 222/* PCI Misc. Host control register / 223#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 224#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 225#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 226#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 227#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 228#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 229#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 230#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 231#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 232* 233#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 234#if BYTE_ORDER == LITTLE_ENDIAN 235#define BGE_DMA_SWAP_OPTIONS \ 236 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 237 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 238#else 239#define BGE_DMA_SWAP_OPTIONS \ 240 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 241 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 242#endif 243 244#define BGE_INIT \ 245 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 246 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 247 248#define BGE_CHIPID_TIGON_I 0x40000000 249#define BGE_CHIPID_TIGON_II 0x60000000 250#define BGE_CHIPID_BCM5700_A0 0x70000000 251#define BGE_CHIPID_BCM5700_A1 0x70010000 252#define BGE_CHIPID_BCM5700_B0 0x71000000 253#define BGE_CHIPID_BCM5700_B1 0x71010000 254#define BGE_CHIPID_BCM5700_B2 0x71020000 255#define BGE_CHIPID_BCM5700_B3 0x71030000 256#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 257#define BGE_CHIPID_BCM5700_C0 0x72000000 258#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr / 259#define BGE_CHIPID_BCM5701_B0 0x01000000 260#define BGE_CHIPID_BCM5701_B2 0x01020000 261#define BGE_CHIPID_BCM5701_B5 0x01050000 262#define BGE_CHIPID_BCM5703_A0 0x10000000 263#define BGE_CHIPID_BCM5703_A1 0x10010000 264#define BGE_CHIPID_BCM5703_A2 0x10020000 265#define BGE_CHIPID_BCM5703_A3 0x10030000 266#define BGE_CHIPID_BCM5703_B0 0x11000000 267#define BGE_CHIPID_BCM5704_A0 0x20000000 268#define BGE_CHIPID_BCM5704_A1 0x20010000 269#define BGE_CHIPID_BCM5704_A2 0x20020000 270#define BGE_CHIPID_BCM5704_A3 0x20030000 271#define BGE_CHIPID_BCM5704_B0 0x21000000 272#define BGE_CHIPID_BCM5705_A0 0x30000000 273#define BGE_CHIPID_BCM5705_A1 0x30010000 274#define BGE_CHIPID_BCM5705_A2 0x30020000 275#define BGE_CHIPID_BCM5705_A3 0x30030000 276#define BGE_CHIPID_BCM5750_A0 0x40000000 277#define BGE_CHIPID_BCM5750_A1 0x40010000 278#define BGE_CHIPID_BCM5750_A3 0x40030000 279#define BGE_CHIPID_BCM5750_B0 0x41000000 280#define BGE_CHIPID_BCM5750_B1 0x41010000 281#define BGE_CHIPID_BCM5750_C0 0x42000000 282#define BGE_CHIPID_BCM5750_C1 0x42010000 283#define BGE_CHIPID_BCM5750_C2 0x42020000 284#define BGE_CHIPID_BCM5714_A0 0x50000000 285#define BGE_CHIPID_BCM5752_A0 0x60000000 286#define BGE_CHIPID_BCM5752_A1 0x60010000 287#define BGE_CHIPID_BCM5752_A2 0x60020000 288#define BGE_CHIPID_BCM5714_B0 0x80000000 289#define BGE_CHIPID_BCM5714_B3 0x80030000 290#define BGE_CHIPID_BCM5715_A0 0x90000000 291#define BGE_CHIPID_BCM5715_A1 0x90010000 292#define BGE_CHIPID_BCM5715_A3 0x90030000 293#define BGE_CHIPID_BCM5755_A0 0xa0000000 294#define BGE_CHIPID_BCM5755_A1 0xa0010000 295#define BGE_CHIPID_BCM5755_A2 0xa0020000 296#define BGE_CHIPID_BCM5722_A0 0xa2000000 297#define BGE_CHIPID_BCM5754_A0 0xb0000000 298#define BGE_CHIPID_BCM5754_A1 0xb0010000 299#define BGE_CHIPID_BCM5754_A2 0xb0020000 300#define BGE_CHIPID_BCM5787_A0 0xb0000000 301#define BGE_CHIPID_BCM5787_A1 0xb0010000 302#define BGE_CHIPID_BCM5787_A2 0xb0020000 303#define BGE_CHIPID_BCM5906_A1 0xc0010000 304#define BGE_CHIPID_BCM5906_A2 0xc0020000 305* 306/* shorthand one / 307#define BGE_ASICREV(x) ((x) >> 28) 308#define BGE_ASICREV_BCM5701 0x00 309#define BGE_ASICREV_BCM5703 0x01 310#define BGE_ASICREV_BCM5704 0x02 311#define BGE_ASICREV_BCM5705 0x03 312#define BGE_ASICREV_BCM5750 0x04 313#define BGE_ASICREV_BCM5714_A0 0x05 314#define BGE_ASICREV_BCM5752 0x06 315#define BGE_ASICREV_BCM5700 0x07 316#define BGE_ASICREV_BCM5780 0x08 317#define BGE_ASICREV_BCM5714 0x09 318#define BGE_ASICREV_BCM5755 0x0a 319#define BGE_ASICREV_BCM5754 0x0b 320#define BGE_ASICREV_BCM5787 0x0b 321#define BGE_ASICREV_BCM5906 0x0c 322* 323/* chip revisions / 324#define BGE_CHIPREV(x) ((x) >> 24) 325#define BGE_CHIPREV_5700_AX 0x70 326#define BGE_CHIPREV_5700_BX 0x71 327#define BGE_CHIPREV_5700_CX 0x72 328#define BGE_CHIPREV_5701_AX 0x00 329#define BGE_CHIPREV_5703_AX 0x10 330#define BGE_CHIPREV_5704_AX 0x20 331#define BGE_CHIPREV_5704_BX 0x21 332#define BGE_CHIPREV_5750_AX 0x40 333#define BGE_CHIPREV_5750_BX 0x41 334* 335/* PCI DMA Read/Write Control register / 336#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 337#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 338#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 339#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 340#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 341#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 342#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 343#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 344#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 345#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 346#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 347#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 348* 349#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 350#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 351#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 352#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 353 354#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 355#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 356#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 357#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 358#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 359#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 360#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 361#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 362 363#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 364#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 365#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 366#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 367#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 368#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 369#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 370#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 371 372/* 373 * PCI state register -- note, this register is read only 374 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 375 * register is set. 376 / 377#define BGE_PCISTATE_FORCE_RESET 0x00000001 378#define BGE_PCISTATE_INTR_STATE 0x00000002 379#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 380#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 381#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 382#define BGE_PCISTATE_WANT_EXPROM 0x00000020 383#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 384#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 385#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 386* 387/* 388 * PCI Clock Control register -- note, this register is read only 389 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 390 * register is set. 391 / 392#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 393#define BGE_PCICLOCKCTL_M66EN 0x00000080 394#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 395#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 396#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 397#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 398#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 399#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 400#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 401#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 402* 403 404#ifndef PCIM_CMD_MWIEN 405#define PCIM_CMD_MWIEN 0x0010 406#endif	34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 79#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 80#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 81#define BGE_UNMAPPED 0x00001000 82#define BGE_UNMAPPED_END 0x00001FFF 83#define BGE_DMA_DESCRIPTORS 0x00002000 84#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 85#define BGE_SEND_RING_1_TO_4 0x00004000 86#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 87 88/ Firmware interface / 89#define BGE_FW_DRV_ALIVE 0x00000001 90#define BGE_FW_PAUSE 0x00000002 91 92/ Mappings for internal memory configuration / 93#define BGE_STD_RX_RINGS 0x00006000 94#define BGE_STD_RX_RINGS_END 0x00006FFF 95#define BGE_JUMBO_RX_RINGS 0x00007000 96#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 97#define BGE_BUFFPOOL_1 0x00008000 98#define BGE_BUFFPOOL_1_END 0x0000FFFF 99#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 100#define BGE_BUFFPOOL_2_END 0x00017FFF 101#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 102#define BGE_BUFFPOOL_3_END 0x0001FFFF 103* 104/* Mappings for external SSRAM configurations / 105#define BGE_SEND_RING_5_TO_6 0x00006000 106#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 107#define BGE_SEND_RING_7_TO_8 0x00007000 108#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 109#define BGE_SEND_RING_9_TO_16 0x00008000 110#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 111#define BGE_EXT_STD_RX_RINGS 0x0000C000 112#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 113#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 114#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 115#define BGE_MINI_RX_RINGS 0x0000E000 116#define BGE_MINI_RX_RINGS_END 0x0000FFFF 117#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 118#define BGE_AVAIL_REGION1_END 0x00017FFF 119#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 120#define BGE_AVAIL_REGION2_END 0x0001FFFF 121#define BGE_EXT_SSRAM 0x00020000 122#define BGE_EXT_SSRAM_END 0x000FFFFF 123* 124 125/* 126 * BCM570x register offsets. These are memory mapped registers 127 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 128 * Each register must be accessed using 32 bit operations. 129 * 130 * All registers are accessed through a 32K shared memory block. 131 * The first group of registers are actually copies of the PCI 132 * configuration space registers. 133 / 134* 135/* 136 * PCI registers defined in the PCI 2.2 spec. 137 / 138#define BGE_PCI_VID 0x00 139#define BGE_PCI_DID 0x02 140#define BGE_PCI_CMD 0x04 141#define BGE_PCI_STS 0x06 142#define BGE_PCI_REV 0x08 143#define BGE_PCI_CLASS 0x09 144#define BGE_PCI_CACHESZ 0x0C 145#define BGE_PCI_LATTIMER 0x0D 146#define BGE_PCI_HDRTYPE 0x0E 147#define BGE_PCI_BIST 0x0F 148#define BGE_PCI_BAR0 0x10 149#define BGE_PCI_BAR1 0x14 150#define BGE_PCI_SUBSYS 0x2C 151#define BGE_PCI_SUBVID 0x2E 152#define BGE_PCI_ROMBASE 0x30 153#define BGE_PCI_CAPPTR 0x34 154#define BGE_PCI_INTLINE 0x3C 155#define BGE_PCI_INTPIN 0x3D 156#define BGE_PCI_MINGNT 0x3E 157#define BGE_PCI_MAXLAT 0x3F 158#define BGE_PCI_PCIXCAP 0x40 159#define BGE_PCI_NEXTPTR_PM 0x41 160#define BGE_PCI_PCIX_CMD 0x42 161#define BGE_PCI_PCIX_STS 0x44 162#define BGE_PCI_PWRMGMT_CAPID 0x48 163#define BGE_PCI_NEXTPTR_VPD 0x49 164#define BGE_PCI_PWRMGMT_CAPS 0x4A 165#define BGE_PCI_PWRMGMT_CMD 0x4C 166#define BGE_PCI_PWRMGMT_STS 0x4D 167#define BGE_PCI_PWRMGMT_DATA 0x4F 168#define BGE_PCI_VPD_CAPID 0x50 169#define BGE_PCI_NEXTPTR_MSI 0x51 170#define BGE_PCI_VPD_ADDR 0x52 171#define BGE_PCI_VPD_DATA 0x54 172#define BGE_PCI_MSI_CAPID 0x58 173#define BGE_PCI_NEXTPTR_NONE 0x59 174#define BGE_PCI_MSI_CTL 0x5A 175#define BGE_PCI_MSI_ADDR_HI 0x5C 176#define BGE_PCI_MSI_ADDR_LO 0x60 177#define BGE_PCI_MSI_DATA 0x64 178* 179/* 180 * PCI Express definitions 181 * According to 182 * PCI Express base specification, REV. 1.0a 183 / 184* 185/* PCI Express device control, 16bits / 186#define BGE_PCIE_DEVCTL 0x08 187#define BGE_PCIE_DEVCTL_MAX_READRQ_MASK 0x7000 188#define BGE_PCIE_DEVCTL_MAX_READRQ_128 0x0000 189#define BGE_PCIE_DEVCTL_MAX_READRQ_256 0x1000 190#define BGE_PCIE_DEVCTL_MAX_READRQ_512 0x2000 191#define BGE_PCIE_DEVCTL_MAX_READRQ_1024 0x3000 192#define BGE_PCIE_DEVCTL_MAX_READRQ_2048 0x4000 193#define BGE_PCIE_DEVCTL_MAX_READRQ_4096 0x5000 194* 195/* PCI MSI. ??? / 196#define BGE_PCIE_CAPID_REG 0xD0 197#define BGE_PCIE_CAPID 0x10 198* 199/* 200 * PCI registers specific to the BCM570x family. 201 / 202#define BGE_PCI_MISC_CTL 0x68 203#define BGE_PCI_DMA_RW_CTL 0x6C 204#define BGE_PCI_PCISTATE 0x70 205#define BGE_PCI_CLKCTL 0x74 206#define BGE_PCI_REG_BASEADDR 0x78 207#define BGE_PCI_MEMWIN_BASEADDR 0x7C 208#define BGE_PCI_REG_DATA 0x80 209#define BGE_PCI_MEMWIN_DATA 0x84 210#define BGE_PCI_MODECTL 0x88 211#define BGE_PCI_MISC_CFG 0x8C 212#define BGE_PCI_MISC_LOCALCTL 0x90 213#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 214#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 215#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 216#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 217#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 218#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 219#define BGE_PCI_ISR_MBX_HI 0xB0 220#define BGE_PCI_ISR_MBX_LO 0xB4 221* 222/* PCI Misc. Host control register / 223#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 224#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 225#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 226#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 227#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 228#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 229#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 230#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 231#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 232* 233#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 234#if BYTE_ORDER == LITTLE_ENDIAN 235#define BGE_DMA_SWAP_OPTIONS \ 236 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 237 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 238#else 239#define BGE_DMA_SWAP_OPTIONS \ 240 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 241 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 242#endif 243 244#define BGE_INIT \ 245 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 246 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 247 248#define BGE_CHIPID_TIGON_I 0x40000000 249#define BGE_CHIPID_TIGON_II 0x60000000 250#define BGE_CHIPID_BCM5700_A0 0x70000000 251#define BGE_CHIPID_BCM5700_A1 0x70010000 252#define BGE_CHIPID_BCM5700_B0 0x71000000 253#define BGE_CHIPID_BCM5700_B1 0x71010000 254#define BGE_CHIPID_BCM5700_B2 0x71020000 255#define BGE_CHIPID_BCM5700_B3 0x71030000 256#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 257#define BGE_CHIPID_BCM5700_C0 0x72000000 258#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr / 259#define BGE_CHIPID_BCM5701_B0 0x01000000 260#define BGE_CHIPID_BCM5701_B2 0x01020000 261#define BGE_CHIPID_BCM5701_B5 0x01050000 262#define BGE_CHIPID_BCM5703_A0 0x10000000 263#define BGE_CHIPID_BCM5703_A1 0x10010000 264#define BGE_CHIPID_BCM5703_A2 0x10020000 265#define BGE_CHIPID_BCM5703_A3 0x10030000 266#define BGE_CHIPID_BCM5703_B0 0x11000000 267#define BGE_CHIPID_BCM5704_A0 0x20000000 268#define BGE_CHIPID_BCM5704_A1 0x20010000 269#define BGE_CHIPID_BCM5704_A2 0x20020000 270#define BGE_CHIPID_BCM5704_A3 0x20030000 271#define BGE_CHIPID_BCM5704_B0 0x21000000 272#define BGE_CHIPID_BCM5705_A0 0x30000000 273#define BGE_CHIPID_BCM5705_A1 0x30010000 274#define BGE_CHIPID_BCM5705_A2 0x30020000 275#define BGE_CHIPID_BCM5705_A3 0x30030000 276#define BGE_CHIPID_BCM5750_A0 0x40000000 277#define BGE_CHIPID_BCM5750_A1 0x40010000 278#define BGE_CHIPID_BCM5750_A3 0x40030000 279#define BGE_CHIPID_BCM5750_B0 0x41000000 280#define BGE_CHIPID_BCM5750_B1 0x41010000 281#define BGE_CHIPID_BCM5750_C0 0x42000000 282#define BGE_CHIPID_BCM5750_C1 0x42010000 283#define BGE_CHIPID_BCM5750_C2 0x42020000 284#define BGE_CHIPID_BCM5714_A0 0x50000000 285#define BGE_CHIPID_BCM5752_A0 0x60000000 286#define BGE_CHIPID_BCM5752_A1 0x60010000 287#define BGE_CHIPID_BCM5752_A2 0x60020000 288#define BGE_CHIPID_BCM5714_B0 0x80000000 289#define BGE_CHIPID_BCM5714_B3 0x80030000 290#define BGE_CHIPID_BCM5715_A0 0x90000000 291#define BGE_CHIPID_BCM5715_A1 0x90010000 292#define BGE_CHIPID_BCM5715_A3 0x90030000 293#define BGE_CHIPID_BCM5755_A0 0xa0000000 294#define BGE_CHIPID_BCM5755_A1 0xa0010000 295#define BGE_CHIPID_BCM5755_A2 0xa0020000 296#define BGE_CHIPID_BCM5722_A0 0xa2000000 297#define BGE_CHIPID_BCM5754_A0 0xb0000000 298#define BGE_CHIPID_BCM5754_A1 0xb0010000 299#define BGE_CHIPID_BCM5754_A2 0xb0020000 300#define BGE_CHIPID_BCM5787_A0 0xb0000000 301#define BGE_CHIPID_BCM5787_A1 0xb0010000 302#define BGE_CHIPID_BCM5787_A2 0xb0020000 303#define BGE_CHIPID_BCM5906_A1 0xc0010000 304#define BGE_CHIPID_BCM5906_A2 0xc0020000 305* 306/* shorthand one / 307#define BGE_ASICREV(x) ((x) >> 28) 308#define BGE_ASICREV_BCM5701 0x00 309#define BGE_ASICREV_BCM5703 0x01 310#define BGE_ASICREV_BCM5704 0x02 311#define BGE_ASICREV_BCM5705 0x03 312#define BGE_ASICREV_BCM5750 0x04 313#define BGE_ASICREV_BCM5714_A0 0x05 314#define BGE_ASICREV_BCM5752 0x06 315#define BGE_ASICREV_BCM5700 0x07 316#define BGE_ASICREV_BCM5780 0x08 317#define BGE_ASICREV_BCM5714 0x09 318#define BGE_ASICREV_BCM5755 0x0a 319#define BGE_ASICREV_BCM5754 0x0b 320#define BGE_ASICREV_BCM5787 0x0b 321#define BGE_ASICREV_BCM5906 0x0c 322* 323/* chip revisions / 324#define BGE_CHIPREV(x) ((x) >> 24) 325#define BGE_CHIPREV_5700_AX 0x70 326#define BGE_CHIPREV_5700_BX 0x71 327#define BGE_CHIPREV_5700_CX 0x72 328#define BGE_CHIPREV_5701_AX 0x00 329#define BGE_CHIPREV_5703_AX 0x10 330#define BGE_CHIPREV_5704_AX 0x20 331#define BGE_CHIPREV_5704_BX 0x21 332#define BGE_CHIPREV_5750_AX 0x40 333#define BGE_CHIPREV_5750_BX 0x41 334* 335/* PCI DMA Read/Write Control register / 336#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 337#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 338#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 339#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x0000C000 340#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL 0x00004000 341#define BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL 0x00008000 342#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 343#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 344#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 345#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 346#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 347#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 348* 349#define BGE_PCIDMARWCTL_RD_WAT_SHIFT(x) ((x) << 16) 350#define BGE_PCIDMARWCTL_WR_WAT_SHIFT(x) ((x) << 19) 351#define BGE_PCIDMARWCTL_RD_CMD_SHIFT(x) ((x) << 24) 352#define BGE_PCIDMARWCTL_WR_CMD_SHIFT(x) ((x) << 28) 353 354#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 355#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 356#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 357#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 358#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 359#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 360#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 361#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 362 363#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 364#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 365#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 366#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 367#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 368#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 369#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 370#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 371 372/* 373 * PCI state register -- note, this register is read only 374 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 375 * register is set. 376 / 377#define BGE_PCISTATE_FORCE_RESET 0x00000001 378#define BGE_PCISTATE_INTR_STATE 0x00000002 379#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 380#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 66/133, 0 = 33/66 / 381#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 382#define BGE_PCISTATE_WANT_EXPROM 0x00000020 383#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 384#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 385#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 386* 387/* 388 * PCI Clock Control register -- note, this register is read only 389 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 390 * register is set. 391 / 392#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 393#define BGE_PCICLOCKCTL_M66EN 0x00000080 394#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 395#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 396#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 397#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 398#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 399#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 400#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 401#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 402* 403 404#ifndef PCIM_CMD_MWIEN 405#define PCIM_CMD_MWIEN 0x0010 406#endif
	407#ifndef PCIM_CMD_INTxDIS 408#define PCIM_CMD_INTxDIS 0x0400 409#endif
407 408/* 409 * High priority mailbox registers 410 * Each mailbox is 64-bits wide, though we only use the 411 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 412 * first. The NIC will load the mailbox after the lower 32 bit word 413 * has been updated. 414 / 415#define BGE_MBX_IRQ0_HI 0x0200 416#define BGE_MBX_IRQ0_LO 0x0204 417#define BGE_MBX_IRQ1_HI 0x0208 418#define BGE_MBX_IRQ1_LO 0x020C 419#define BGE_MBX_IRQ2_HI 0x0210 420#define BGE_MBX_IRQ2_LO 0x0214 421#define BGE_MBX_IRQ3_HI 0x0218 422#define BGE_MBX_IRQ3_LO 0x021C 423#define BGE_MBX_GEN0_HI 0x0220 424#define BGE_MBX_GEN0_LO 0x0224 425#define BGE_MBX_GEN1_HI 0x0228 426#define BGE_MBX_GEN1_LO 0x022C 427#define BGE_MBX_GEN2_HI 0x0230 428#define BGE_MBX_GEN2_LO 0x0234 429#define BGE_MBX_GEN3_HI 0x0228 430#define BGE_MBX_GEN3_LO 0x022C 431#define BGE_MBX_GEN4_HI 0x0240 432#define BGE_MBX_GEN4_LO 0x0244 433#define BGE_MBX_GEN5_HI 0x0248 434#define BGE_MBX_GEN5_LO 0x024C 435#define BGE_MBX_GEN6_HI 0x0250 436#define BGE_MBX_GEN6_LO 0x0254 437#define BGE_MBX_GEN7_HI 0x0258 438#define BGE_MBX_GEN7_LO 0x025C 439#define BGE_MBX_RELOAD_STATS_HI 0x0260 440#define BGE_MBX_RELOAD_STATS_LO 0x0264 441#define BGE_MBX_RX_STD_PROD_HI 0x0268 442#define BGE_MBX_RX_STD_PROD_LO 0x026C 443#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 444#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 445#define BGE_MBX_RX_MINI_PROD_HI 0x0278 446#define BGE_MBX_RX_MINI_PROD_LO 0x027C 447#define BGE_MBX_RX_CONS0_HI 0x0280 448#define BGE_MBX_RX_CONS0_LO 0x0284 449#define BGE_MBX_RX_CONS1_HI 0x0288 450#define BGE_MBX_RX_CONS1_LO 0x028C 451#define BGE_MBX_RX_CONS2_HI 0x0290 452#define BGE_MBX_RX_CONS2_LO 0x0294 453#define BGE_MBX_RX_CONS3_HI 0x0298 454#define BGE_MBX_RX_CONS3_LO 0x029C 455#define BGE_MBX_RX_CONS4_HI 0x02A0 456#define BGE_MBX_RX_CONS4_LO 0x02A4 457#define BGE_MBX_RX_CONS5_HI 0x02A8 458#define BGE_MBX_RX_CONS5_LO 0x02AC 459#define BGE_MBX_RX_CONS6_HI 0x02B0 460#define BGE_MBX_RX_CONS6_LO 0x02B4 461#define BGE_MBX_RX_CONS7_HI 0x02B8 462#define BGE_MBX_RX_CONS7_LO 0x02BC 463#define BGE_MBX_RX_CONS8_HI 0x02C0 464#define BGE_MBX_RX_CONS8_LO 0x02C4 465#define BGE_MBX_RX_CONS9_HI 0x02C8 466#define BGE_MBX_RX_CONS9_LO 0x02CC 467#define BGE_MBX_RX_CONS10_HI 0x02D0 468#define BGE_MBX_RX_CONS10_LO 0x02D4 469#define BGE_MBX_RX_CONS11_HI 0x02D8 470#define BGE_MBX_RX_CONS11_LO 0x02DC 471#define BGE_MBX_RX_CONS12_HI 0x02E0 472#define BGE_MBX_RX_CONS12_LO 0x02E4 473#define BGE_MBX_RX_CONS13_HI 0x02E8 474#define BGE_MBX_RX_CONS13_LO 0x02EC 475#define BGE_MBX_RX_CONS14_HI 0x02F0 476#define BGE_MBX_RX_CONS14_LO 0x02F4 477#define BGE_MBX_RX_CONS15_HI 0x02F8 478#define BGE_MBX_RX_CONS15_LO 0x02FC 479#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 480#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 481#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 482#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 483#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 484#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 485#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 486#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 487#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 488#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 489#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 490#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 491#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 492#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 493#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 494#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 495#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 496#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 497#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 498#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 499#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 500#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 501#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 502#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 503#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 504#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 505#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 506#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 507#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 508#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 509#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 510#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 511#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 512#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 513#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 514#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 515#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 516#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 517#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 518#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 519#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 520#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 521#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 522#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 523#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 524#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 525#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 526#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 527#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 528#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 529#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 530#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 531#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 532#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 533#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 534#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 535#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 536#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 537#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 538#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 539#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 540#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 541#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 542#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 543* 544#define BGE_TX_RINGS_MAX 4 545#define BGE_TX_RINGS_EXTSSRAM_MAX 16 546#define BGE_RX_RINGS_MAX 16 547 548/* Ethernet MAC control registers / 549#define BGE_MAC_MODE 0x0400 550#define BGE_MAC_STS 0x0404 551#define BGE_MAC_EVT_ENB 0x0408 552#define BGE_MAC_LED_CTL 0x040C 553#define BGE_MAC_ADDR1_LO 0x0410 554#define BGE_MAC_ADDR1_HI 0x0414 555#define BGE_MAC_ADDR2_LO 0x0418 556#define BGE_MAC_ADDR2_HI 0x041C 557#define BGE_MAC_ADDR3_LO 0x0420 558#define BGE_MAC_ADDR3_HI 0x0424 559#define BGE_MAC_ADDR4_LO 0x0428 560#define BGE_MAC_ADDR4_HI 0x042C 561#define BGE_WOL_PATPTR 0x0430 562#define BGE_WOL_PATCFG 0x0434 563#define BGE_TX_RANDOM_BACKOFF 0x0438 564#define BGE_RX_MTU 0x043C 565#define BGE_GBIT_PCS_TEST 0x0440 566#define BGE_TX_TBI_AUTONEG 0x0444 567#define BGE_RX_TBI_AUTONEG 0x0448 568#define BGE_MI_COMM 0x044C 569#define BGE_MI_STS 0x0450 570#define BGE_MI_MODE 0x0454 571#define BGE_AUTOPOLL_STS 0x0458 572#define BGE_TX_MODE 0x045C 573#define BGE_TX_STS 0x0460 574#define BGE_TX_LENGTHS 0x0464 575#define BGE_RX_MODE 0x0468 576#define BGE_RX_STS 0x046C 577#define BGE_MAR0 0x0470 578#define BGE_MAR1 0x0474 579#define BGE_MAR2 0x0478 580#define BGE_MAR3 0x047C 581#define BGE_RX_BD_RULES_CTL0 0x0480 582#define BGE_RX_BD_RULES_MASKVAL0 0x0484 583#define BGE_RX_BD_RULES_CTL1 0x0488 584#define BGE_RX_BD_RULES_MASKVAL1 0x048C 585#define BGE_RX_BD_RULES_CTL2 0x0490 586#define BGE_RX_BD_RULES_MASKVAL2 0x0494 587#define BGE_RX_BD_RULES_CTL3 0x0498 588#define BGE_RX_BD_RULES_MASKVAL3 0x049C 589#define BGE_RX_BD_RULES_CTL4 0x04A0 590#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 591#define BGE_RX_BD_RULES_CTL5 0x04A8 592#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 593#define BGE_RX_BD_RULES_CTL6 0x04B0 594#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 595#define BGE_RX_BD_RULES_CTL7 0x04B8 596#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 597#define BGE_RX_BD_RULES_CTL8 0x04C0 598#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 599#define BGE_RX_BD_RULES_CTL9 0x04C8 600#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 601#define BGE_RX_BD_RULES_CTL10 0x04D0 602#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 603#define BGE_RX_BD_RULES_CTL11 0x04D8 604#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 605#define BGE_RX_BD_RULES_CTL12 0x04E0 606#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 607#define BGE_RX_BD_RULES_CTL13 0x04E8 608#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 609#define BGE_RX_BD_RULES_CTL14 0x04F0 610#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 611#define BGE_RX_BD_RULES_CTL15 0x04F8 612#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 613#define BGE_RX_RULES_CFG 0x0500 614#define BGE_SERDES_CFG 0x0590 615#define BGE_SERDES_STS 0x0594 616#define BGE_SGDIG_CFG 0x05B0 617#define BGE_SGDIG_STS 0x05B4 618#define BGE_MAC_STATS 0x0800 619* 620/* Ethernet MAC Mode register / 621#define BGE_MACMODE_RESET 0x00000001 622#define BGE_MACMODE_HALF_DUPLEX 0x00000002 623#define BGE_MACMODE_PORTMODE 0x0000000C 624#define BGE_MACMODE_LOOPBACK 0x00000010 625#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 626#define BGE_MACMODE_TX_BURST_ENB 0x00000100 627#define BGE_MACMODE_MAX_DEFER 0x00000200 628#define BGE_MACMODE_LINK_POLARITY 0x00000400 629#define BGE_MACMODE_RX_STATS_ENB 0x00000800 630#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 631#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 632#define BGE_MACMODE_TX_STATS_ENB 0x00004000 633#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 634#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 635#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 636#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 637#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 638#define BGE_MACMODE_MIP_ENB 0x00100000 639#define BGE_MACMODE_TXDMA_ENB 0x00200000 640#define BGE_MACMODE_RXDMA_ENB 0x00400000 641#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 642* 643#define BGE_PORTMODE_NONE 0x00000000 644#define BGE_PORTMODE_MII 0x00000004 645#define BGE_PORTMODE_GMII 0x00000008 646#define BGE_PORTMODE_TBI 0x0000000C 647 648/* MAC Status register / 649#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 650#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 651#define BGE_MACSTAT_RX_CFG 0x00000004 652#define BGE_MACSTAT_CFG_CHANGED 0x00000008 653#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 654#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 655#define BGE_MACSTAT_LINK_CHANGED 0x00001000 656#define BGE_MACSTAT_MI_COMPLETE 0x00400000 657#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 658#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 659#define BGE_MACSTAT_ODI_ERROR 0x02000000 660#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 661#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 662* 663/* MAC Event Enable Register / 664#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 665#define BGE_EVTENB_LINK_CHANGED 0x00001000 666#define BGE_EVTENB_MI_COMPLETE 0x00400000 667#define BGE_EVTENB_MI_INTERRUPT 0x00800000 668#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 669#define BGE_EVTENB_ODI_ERROR 0x02000000 670#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 671#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 672* 673/* LED Control Register / 674#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 675#define BGE_LEDCTL_1000MBPS_LED 0x00000002 676#define BGE_LEDCTL_100MBPS_LED 0x00000004 677#define BGE_LEDCTL_10MBPS_LED 0x00000008 678#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 679#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 680#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 681#define BGE_LEDCTL_1000MBPS_STS 0x00000080 682#define BGE_LEDCTL_100MBPS_STS 0x00000100 683#define BGE_LEDCTL_10MBPS_STS 0x00000200 684#define BGE_LEDCTL_TRADLED_STS 0x00000400 685#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 686#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 687* 688/* TX backoff seed register / 689#define BGE_TX_BACKOFF_SEED_MASK 0x3F 690* 691/* Autopoll status register / 692#define BGE_AUTOPOLLSTS_ERROR 0x00000001 693* 694/* Transmit MAC mode register / 695#define BGE_TXMODE_RESET 0x00000001 696#define BGE_TXMODE_ENABLE 0x00000002 697#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 698#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 699#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 700* 701/* Transmit MAC status register / 702#define BGE_TXSTAT_RX_XOFFED 0x00000001 703#define BGE_TXSTAT_SENT_XOFF 0x00000002 704#define BGE_TXSTAT_SENT_XON 0x00000004 705#define BGE_TXSTAT_LINK_UP 0x00000008 706#define BGE_TXSTAT_ODI_UFLOW 0x00000010 707#define BGE_TXSTAT_ODI_OFLOW 0x00000020 708* 709/* Transmit MAC lengths register / 710#define BGE_TXLEN_SLOTTIME 0x000000FF 711#define BGE_TXLEN_IPG 0x00000F00 712#define BGE_TXLEN_CRS 0x00003000 713* 714/* Receive MAC mode register / 715#define BGE_RXMODE_RESET 0x00000001 716#define BGE_RXMODE_ENABLE 0x00000002 717#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 718#define BGE_RXMODE_RX_GIANTS 0x00000020 719#define BGE_RXMODE_RX_RUNTS 0x00000040 720#define BGE_RXMODE_8022_LENCHECK 0x00000080 721#define BGE_RXMODE_RX_PROMISC 0x00000100 722#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 723#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 724* 725/* Receive MAC status register / 726#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 727#define BGE_RXSTAT_RCVD_XOFF 0x00000002 728#define BGE_RXSTAT_RCVD_XON 0x00000004 729* 730/* Receive Rules Control register / 731#define BGE_RXRULECTL_OFFSET 0x000000FF 732#define BGE_RXRULECTL_CLASS 0x00001F00 733#define BGE_RXRULECTL_HDRTYPE 0x0000E000 734#define BGE_RXRULECTL_COMPARE_OP 0x00030000 735#define BGE_RXRULECTL_MAP 0x01000000 736#define BGE_RXRULECTL_DISCARD 0x02000000 737#define BGE_RXRULECTL_MASK 0x04000000 738#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 739#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 740#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 741#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 742* 743/* Receive Rules Mask register / 744#define BGE_RXRULEMASK_VALUE 0x0000FFFF 745#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 746* 747/* SERDES configuration register / 748#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 749#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 750#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 751#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 752#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 753#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 754#define BGE_SERDESCFG_TXMODE 0x00001000 755#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 756#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 757#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 758#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 759#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 760#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 761#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 762#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 763#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 764* 765/* SERDES status register / 766#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 767#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 768* 769/* SGDIG config (not documented) / 770#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 771#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 772#define BGE_SGDIGCFG_SEND 0x40000000 773#define BGE_SGDIGCFG_AUTO 0x80000000 774* 775/* SGDIG status (not documented) / 776#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 777#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 778#define BGE_SGDIGSTS_DONE 0x00000002 779* 780 781/* MI communication register / 782#define BGE_MICOMM_DATA 0x0000FFFF 783#define BGE_MICOMM_REG 0x001F0000 784#define BGE_MICOMM_PHY 0x03E00000 785#define BGE_MICOMM_CMD 0x0C000000 786#define BGE_MICOMM_READFAIL 0x10000000 787#define BGE_MICOMM_BUSY 0x20000000 788* 789#define BGE_MIREG(x) ((x & 0x1F) << 16) 790#define BGE_MIPHY(x) ((x & 0x1F) << 21) 791#define BGE_MICMD_WRITE 0x04000000 792#define BGE_MICMD_READ 0x08000000 793 794/* MI status register / 795#define BGE_MISTS_LINK 0x00000001 796#define BGE_MISTS_10MBPS 0x00000002 797* 798#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 799#define BGE_MIMODE_AUTOPOLL 0x00000010 800#define BGE_MIMODE_CLKCNT 0x001F0000 801 802 803/* 804 * Send data initiator control registers. 805 / 806#define BGE_SDI_MODE 0x0C00 807#define BGE_SDI_STATUS 0x0C04 808#define BGE_SDI_STATS_CTL 0x0C08 809#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 810#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 811#define BGE_LOCSTATS_COS0 0x0C80 812#define BGE_LOCSTATS_COS1 0x0C84 813#define BGE_LOCSTATS_COS2 0x0C88 814#define BGE_LOCSTATS_COS3 0x0C8C 815#define BGE_LOCSTATS_COS4 0x0C90 816#define BGE_LOCSTATS_COS5 0x0C84 817#define BGE_LOCSTATS_COS6 0x0C98 818#define BGE_LOCSTATS_COS7 0x0C9C 819#define BGE_LOCSTATS_COS8 0x0CA0 820#define BGE_LOCSTATS_COS9 0x0CA4 821#define BGE_LOCSTATS_COS10 0x0CA8 822#define BGE_LOCSTATS_COS11 0x0CAC 823#define BGE_LOCSTATS_COS12 0x0CB0 824#define BGE_LOCSTATS_COS13 0x0CB4 825#define BGE_LOCSTATS_COS14 0x0CB8 826#define BGE_LOCSTATS_COS15 0x0CBC 827#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 828#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 829#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 830#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 831#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 832#define BGE_LOCSTATS_IRQS 0x0CD4 833#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 834#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 835* 836/* Send Data Initiator mode register / 837#define BGE_SDIMODE_RESET 0x00000001 838#define BGE_SDIMODE_ENABLE 0x00000002 839#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 840* 841/* Send Data Initiator stats register / 842#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 843* 844/* Send Data Initiator stats control register / 845#define BGE_SDISTATSCTL_ENABLE 0x00000001 846#define BGE_SDISTATSCTL_FASTER 0x00000002 847#define BGE_SDISTATSCTL_CLEAR 0x00000004 848#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 849#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 850* 851/* 852 * Send Data Completion Control registers 853 / 854#define BGE_SDC_MODE 0x1000 855#define BGE_SDC_STATUS 0x1004 856* 857/* Send Data completion mode register / 858#define BGE_SDCMODE_RESET 0x00000001 859#define BGE_SDCMODE_ENABLE 0x00000002 860#define BGE_SDCMODE_ATTN 0x00000004 861* 862/* Send Data completion status register / 863#define BGE_SDCSTAT_ATTN 0x00000004 864* 865/* 866 * Send BD Ring Selector Control registers 867 / 868#define BGE_SRS_MODE 0x1400 869#define BGE_SRS_STATUS 0x1404 870#define BGE_SRS_HWDIAG 0x1408 871#define BGE_SRS_LOC_NIC_CONS0 0x1440 872#define BGE_SRS_LOC_NIC_CONS1 0x1444 873#define BGE_SRS_LOC_NIC_CONS2 0x1448 874#define BGE_SRS_LOC_NIC_CONS3 0x144C 875#define BGE_SRS_LOC_NIC_CONS4 0x1450 876#define BGE_SRS_LOC_NIC_CONS5 0x1454 877#define BGE_SRS_LOC_NIC_CONS6 0x1458 878#define BGE_SRS_LOC_NIC_CONS7 0x145C 879#define BGE_SRS_LOC_NIC_CONS8 0x1460 880#define BGE_SRS_LOC_NIC_CONS9 0x1464 881#define BGE_SRS_LOC_NIC_CONS10 0x1468 882#define BGE_SRS_LOC_NIC_CONS11 0x146C 883#define BGE_SRS_LOC_NIC_CONS12 0x1470 884#define BGE_SRS_LOC_NIC_CONS13 0x1474 885#define BGE_SRS_LOC_NIC_CONS14 0x1478 886#define BGE_SRS_LOC_NIC_CONS15 0x147C 887* 888/* Send BD Ring Selector Mode register / 889#define BGE_SRSMODE_RESET 0x00000001 890#define BGE_SRSMODE_ENABLE 0x00000002 891#define BGE_SRSMODE_ATTN 0x00000004 892* 893/* Send BD Ring Selector Status register / 894#define BGE_SRSSTAT_ERROR 0x00000004 895* 896/* Send BD Ring Selector HW Diagnostics register / 897#define BGE_SRSHWDIAG_STATE 0x0000000F 898#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 899#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 900#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 901* 902/* 903 * Send BD Initiator Selector Control registers 904 / 905#define BGE_SBDI_MODE 0x1800 906#define BGE_SBDI_STATUS 0x1804 907#define BGE_SBDI_LOC_NIC_PROD0 0x1808 908#define BGE_SBDI_LOC_NIC_PROD1 0x180C 909#define BGE_SBDI_LOC_NIC_PROD2 0x1810 910#define BGE_SBDI_LOC_NIC_PROD3 0x1814 911#define BGE_SBDI_LOC_NIC_PROD4 0x1818 912#define BGE_SBDI_LOC_NIC_PROD5 0x181C 913#define BGE_SBDI_LOC_NIC_PROD6 0x1820 914#define BGE_SBDI_LOC_NIC_PROD7 0x1824 915#define BGE_SBDI_LOC_NIC_PROD8 0x1828 916#define BGE_SBDI_LOC_NIC_PROD9 0x182C 917#define BGE_SBDI_LOC_NIC_PROD10 0x1830 918#define BGE_SBDI_LOC_NIC_PROD11 0x1834 919#define BGE_SBDI_LOC_NIC_PROD12 0x1838 920#define BGE_SBDI_LOC_NIC_PROD13 0x183C 921#define BGE_SBDI_LOC_NIC_PROD14 0x1840 922#define BGE_SBDI_LOC_NIC_PROD15 0x1844 923* 924/* Send BD Initiator Mode register / 925#define BGE_SBDIMODE_RESET 0x00000001 926#define BGE_SBDIMODE_ENABLE 0x00000002 927#define BGE_SBDIMODE_ATTN 0x00000004 928* 929/* Send BD Initiator Status register / 930#define BGE_SBDISTAT_ERROR 0x00000004 931* 932/* 933 * Send BD Completion Control registers 934 / 935#define BGE_SBDC_MODE 0x1C00 936#define BGE_SBDC_STATUS 0x1C04 937* 938/* Send BD Completion Control Mode register / 939#define BGE_SBDCMODE_RESET 0x00000001 940#define BGE_SBDCMODE_ENABLE 0x00000002 941#define BGE_SBDCMODE_ATTN 0x00000004 942* 943/* Send BD Completion Control Status register / 944#define BGE_SBDCSTAT_ATTN 0x00000004 945* 946/* 947 * Receive List Placement Control registers 948 / 949#define BGE_RXLP_MODE 0x2000 950#define BGE_RXLP_STATUS 0x2004 951#define BGE_RXLP_SEL_LIST_LOCK 0x2008 952#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 953#define BGE_RXLP_CFG 0x2010 954#define BGE_RXLP_STATS_CTL 0x2014 955#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 956#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 957#define BGE_RXLP_HEAD0 0x2100 958#define BGE_RXLP_TAIL0 0x2104 959#define BGE_RXLP_COUNT0 0x2108 960#define BGE_RXLP_HEAD1 0x2110 961#define BGE_RXLP_TAIL1 0x2114 962#define BGE_RXLP_COUNT1 0x2118 963#define BGE_RXLP_HEAD2 0x2120 964#define BGE_RXLP_TAIL2 0x2124 965#define BGE_RXLP_COUNT2 0x2128 966#define BGE_RXLP_HEAD3 0x2130 967#define BGE_RXLP_TAIL3 0x2134 968#define BGE_RXLP_COUNT3 0x2138 969#define BGE_RXLP_HEAD4 0x2140 970#define BGE_RXLP_TAIL4 0x2144 971#define BGE_RXLP_COUNT4 0x2148 972#define BGE_RXLP_HEAD5 0x2150 973#define BGE_RXLP_TAIL5 0x2154 974#define BGE_RXLP_COUNT5 0x2158 975#define BGE_RXLP_HEAD6 0x2160 976#define BGE_RXLP_TAIL6 0x2164 977#define BGE_RXLP_COUNT6 0x2168 978#define BGE_RXLP_HEAD7 0x2170 979#define BGE_RXLP_TAIL7 0x2174 980#define BGE_RXLP_COUNT7 0x2178 981#define BGE_RXLP_HEAD8 0x2180 982#define BGE_RXLP_TAIL8 0x2184 983#define BGE_RXLP_COUNT8 0x2188 984#define BGE_RXLP_HEAD9 0x2190 985#define BGE_RXLP_TAIL9 0x2194 986#define BGE_RXLP_COUNT9 0x2198 987#define BGE_RXLP_HEAD10 0x21A0 988#define BGE_RXLP_TAIL10 0x21A4 989#define BGE_RXLP_COUNT10 0x21A8 990#define BGE_RXLP_HEAD11 0x21B0 991#define BGE_RXLP_TAIL11 0x21B4 992#define BGE_RXLP_COUNT11 0x21B8 993#define BGE_RXLP_HEAD12 0x21C0 994#define BGE_RXLP_TAIL12 0x21C4 995#define BGE_RXLP_COUNT12 0x21C8 996#define BGE_RXLP_HEAD13 0x21D0 997#define BGE_RXLP_TAIL13 0x21D4 998#define BGE_RXLP_COUNT13 0x21D8 999#define BGE_RXLP_HEAD14 0x21E0 1000#define BGE_RXLP_TAIL14 0x21E4 1001#define BGE_RXLP_COUNT14 0x21E8 1002#define BGE_RXLP_HEAD15 0x21F0 1003#define BGE_RXLP_TAIL15 0x21F4 1004#define BGE_RXLP_COUNT15 0x21F8 1005#define BGE_RXLP_LOCSTAT_COS0 0x2200 1006#define BGE_RXLP_LOCSTAT_COS1 0x2204 1007#define BGE_RXLP_LOCSTAT_COS2 0x2208 1008#define BGE_RXLP_LOCSTAT_COS3 0x220C 1009#define BGE_RXLP_LOCSTAT_COS4 0x2210 1010#define BGE_RXLP_LOCSTAT_COS5 0x2214 1011#define BGE_RXLP_LOCSTAT_COS6 0x2218 1012#define BGE_RXLP_LOCSTAT_COS7 0x221C 1013#define BGE_RXLP_LOCSTAT_COS8 0x2220 1014#define BGE_RXLP_LOCSTAT_COS9 0x2224 1015#define BGE_RXLP_LOCSTAT_COS10 0x2228 1016#define BGE_RXLP_LOCSTAT_COS11 0x222C 1017#define BGE_RXLP_LOCSTAT_COS12 0x2230 1018#define BGE_RXLP_LOCSTAT_COS13 0x2234 1019#define BGE_RXLP_LOCSTAT_COS14 0x2238 1020#define BGE_RXLP_LOCSTAT_COS15 0x223C 1021#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1022#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1023#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1024#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1025#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1026#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1027#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1028* 1029 1030/* Receive List Placement mode register / 1031#define BGE_RXLPMODE_RESET 0x00000001 1032#define BGE_RXLPMODE_ENABLE 0x00000002 1033#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1034#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1035#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1036* 1037/* Receive List Placement Status register / 1038#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1039#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1040#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1041* 1042/* 1043 * Receive Data and Receive BD Initiator Control Registers 1044 / 1045#define BGE_RDBDI_MODE 0x2400 1046#define BGE_RDBDI_STATUS 0x2404 1047#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1048#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1049#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1050#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1051#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1052#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1053#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1054#define BGE_RX_STD_RCB_NICADDR 0x245C 1055#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1056#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1057#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1058#define BGE_RX_MINI_RCB_NICADDR 0x246C 1059#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1060#define BGE_RDBDI_STD_RX_CONS 0x2474 1061#define BGE_RDBDI_MINI_RX_CONS 0x2478 1062#define BGE_RDBDI_RETURN_PROD0 0x2480 1063#define BGE_RDBDI_RETURN_PROD1 0x2484 1064#define BGE_RDBDI_RETURN_PROD2 0x2488 1065#define BGE_RDBDI_RETURN_PROD3 0x248C 1066#define BGE_RDBDI_RETURN_PROD4 0x2490 1067#define BGE_RDBDI_RETURN_PROD5 0x2494 1068#define BGE_RDBDI_RETURN_PROD6 0x2498 1069#define BGE_RDBDI_RETURN_PROD7 0x249C 1070#define BGE_RDBDI_RETURN_PROD8 0x24A0 1071#define BGE_RDBDI_RETURN_PROD9 0x24A4 1072#define BGE_RDBDI_RETURN_PROD10 0x24A8 1073#define BGE_RDBDI_RETURN_PROD11 0x24AC 1074#define BGE_RDBDI_RETURN_PROD12 0x24B0 1075#define BGE_RDBDI_RETURN_PROD13 0x24B4 1076#define BGE_RDBDI_RETURN_PROD14 0x24B8 1077#define BGE_RDBDI_RETURN_PROD15 0x24BC 1078#define BGE_RDBDI_HWDIAG 0x24C0 1079* 1080 1081/* Receive Data and Receive BD Initiator Mode register / 1082#define BGE_RDBDIMODE_RESET 0x00000001 1083#define BGE_RDBDIMODE_ENABLE 0x00000002 1084#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1085#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1086#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1087* 1088/* Receive Data and Receive BD Initiator Status register / 1089#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1090#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1091#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1092* 1093 1094/* 1095 * Receive Data Completion Control registers 1096 / 1097#define BGE_RDC_MODE 0x2800 1098* 1099/* Receive Data Completion Mode register / 1100#define BGE_RDCMODE_RESET 0x00000001 1101#define BGE_RDCMODE_ENABLE 0x00000002 1102#define BGE_RDCMODE_ATTN 0x00000004 1103* 1104/* 1105 * Receive BD Initiator Control registers 1106 / 1107#define BGE_RBDI_MODE 0x2C00 1108#define BGE_RBDI_STATUS 0x2C04 1109#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1110#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1111#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1112#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1113#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1114#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1115* 1116/* Receive BD Initiator Mode register / 1117#define BGE_RBDIMODE_RESET 0x00000001 1118#define BGE_RBDIMODE_ENABLE 0x00000002 1119#define BGE_RBDIMODE_ATTN 0x00000004 1120* 1121/* Receive BD Initiator Status register / 1122#define BGE_RBDISTAT_ATTN 0x00000004 1123* 1124/* 1125 * Receive BD Completion Control registers 1126 / 1127#define BGE_RBDC_MODE 0x3000 1128#define BGE_RBDC_STATUS 0x3004 1129#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1130#define BGE_RBDC_STD_BD_PROD 0x300C 1131#define BGE_RBDC_MINI_BD_PROD 0x3010 1132* 1133/* Receive BD completion mode register / 1134#define BGE_RBDCMODE_RESET 0x00000001 1135#define BGE_RBDCMODE_ENABLE 0x00000002 1136#define BGE_RBDCMODE_ATTN 0x00000004 1137* 1138/* Receive BD completion status register / 1139#define BGE_RBDCSTAT_ERROR 0x00000004 1140* 1141/* 1142 * Receive List Selector Control registers 1143 / 1144#define BGE_RXLS_MODE 0x3400 1145#define BGE_RXLS_STATUS 0x3404 1146* 1147/* Receive List Selector Mode register / 1148#define BGE_RXLSMODE_RESET 0x00000001 1149#define BGE_RXLSMODE_ENABLE 0x00000002 1150#define BGE_RXLSMODE_ATTN 0x00000004 1151* 1152/* Receive List Selector Status register / 1153#define BGE_RXLSSTAT_ERROR 0x00000004 1154* 1155/* 1156 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1157 / 1158#define BGE_MBCF_MODE 0x3800 1159#define BGE_MBCF_STATUS 0x3804 1160* 1161/* Mbuf Cluster Free mode register / 1162#define BGE_MBCFMODE_RESET 0x00000001 1163#define BGE_MBCFMODE_ENABLE 0x00000002 1164#define BGE_MBCFMODE_ATTN 0x00000004 1165* 1166/* Mbuf Cluster Free status register / 1167#define BGE_MBCFSTAT_ERROR 0x00000004 1168* 1169/* 1170 * Host Coalescing Control registers 1171 / 1172#define BGE_HCC_MODE 0x3C00 1173#define BGE_HCC_STATUS 0x3C04 1174#define BGE_HCC_RX_COAL_TICKS 0x3C08 1175#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1176#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1177#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1178#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1179#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1180#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1181#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1182#define BGE_HCC_STATS_TICKS 0x3C28 1183#define BGE_HCC_STATS_ADDR_HI 0x3C30 1184#define BGE_HCC_STATS_ADDR_LO 0x3C34 1185#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1186#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1187#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1188#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1189#define BGE_FLOW_ATTN 0x3C48 1190#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1191#define BGE_HCC_STD_BD_CONS 0x3C54 1192#define BGE_HCC_MINI_BD_CONS 0x3C58 1193#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1194#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1195#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1196#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1197#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1198#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1199#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1200#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1201#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1202#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1203#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1204#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1205#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1206#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1207#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1208#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1209#define BGE_HCC_TX_BD_CONS0 0x3CC0 1210#define BGE_HCC_TX_BD_CONS1 0x3CC4 1211#define BGE_HCC_TX_BD_CONS2 0x3CC8 1212#define BGE_HCC_TX_BD_CONS3 0x3CCC 1213#define BGE_HCC_TX_BD_CONS4 0x3CD0 1214#define BGE_HCC_TX_BD_CONS5 0x3CD4 1215#define BGE_HCC_TX_BD_CONS6 0x3CD8 1216#define BGE_HCC_TX_BD_CONS7 0x3CDC 1217#define BGE_HCC_TX_BD_CONS8 0x3CE0 1218#define BGE_HCC_TX_BD_CONS9 0x3CE4 1219#define BGE_HCC_TX_BD_CONS10 0x3CE8 1220#define BGE_HCC_TX_BD_CONS11 0x3CEC 1221#define BGE_HCC_TX_BD_CONS12 0x3CF0 1222#define BGE_HCC_TX_BD_CONS13 0x3CF4 1223#define BGE_HCC_TX_BD_CONS14 0x3CF8 1224#define BGE_HCC_TX_BD_CONS15 0x3CFC 1225* 1226 1227/* Host coalescing mode register / 1228#define BGE_HCCMODE_RESET 0x00000001 1229#define BGE_HCCMODE_ENABLE 0x00000002 1230#define BGE_HCCMODE_ATTN 0x00000004 1231#define BGE_HCCMODE_COAL_NOW 0x00000008 1232#define BGE_HCCMODE_MSI_BITS 0x00000070 1233#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1234* 1235#define BGE_STATBLKSZ_FULL 0x00000000 1236#define BGE_STATBLKSZ_64BYTE 0x00000080 1237#define BGE_STATBLKSZ_32BYTE 0x00000100 1238 1239/* Host coalescing status register / 1240#define BGE_HCCSTAT_ERROR 0x00000004 1241* 1242/* Flow attention register / 1243#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1244#define BGE_FLOWATTN_MEMARB 0x00000080 1245#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1246#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1247#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1248#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1249#define BGE_FLOWATTN_RDBDI 0x00080000 1250#define BGE_FLOWATTN_RXLS 0x00100000 1251#define BGE_FLOWATTN_RXLP 0x00200000 1252#define BGE_FLOWATTN_RBDC 0x00400000 1253#define BGE_FLOWATTN_RBDI 0x00800000 1254#define BGE_FLOWATTN_SDC 0x08000000 1255#define BGE_FLOWATTN_SDI 0x10000000 1256#define BGE_FLOWATTN_SRS 0x20000000 1257#define BGE_FLOWATTN_SBDC 0x40000000 1258#define BGE_FLOWATTN_SBDI 0x80000000 1259* 1260/* 1261 * Memory arbiter registers 1262 / 1263#define BGE_MARB_MODE 0x4000 1264#define BGE_MARB_STATUS 0x4004 1265#define BGE_MARB_TRAPADDR_HI 0x4008 1266#define BGE_MARB_TRAPADDR_LO 0x400C 1267* 1268/* Memory arbiter mode register / 1269#define BGE_MARBMODE_RESET 0x00000001 1270#define BGE_MARBMODE_ENABLE 0x00000002 1271#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1272#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1273#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1274#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1275#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1276#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1277#define BGE_MARBMODE_PCI_TRAP 0x00000100 1278#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1279#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1280#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1281#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1282#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1283#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1284#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1285#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1286#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1287#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1288#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1289#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1290#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1291#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1292#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1293#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1294#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1295* 1296/* Memory arbiter status register / 1297#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1298#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1299#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1300#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1301#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1302#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1303#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1304#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1305#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1306#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1307#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1308#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1309#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1310#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1311#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1312#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1313#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1314#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1315#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1316#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1317#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1318#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1319#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1320#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1321* 1322/* 1323 * Buffer manager control registers 1324 / 1325#define BGE_BMAN_MODE 0x4400 1326#define BGE_BMAN_STATUS 0x4404 1327#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1328#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1329#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1330#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1331#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1332#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1333#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1334#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1335#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1336#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1337#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1338#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1339#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1340#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1341#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1342#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1343#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1344#define BGE_BMAN_HWDIAG_1 0x444C 1345#define BGE_BMAN_HWDIAG_2 0x4450 1346#define BGE_BMAN_HWDIAG_3 0x4454 1347* 1348/* Buffer manager mode register / 1349#define BGE_BMANMODE_RESET 0x00000001 1350#define BGE_BMANMODE_ENABLE 0x00000002 1351#define BGE_BMANMODE_ATTN 0x00000004 1352#define BGE_BMANMODE_TESTMODE 0x00000008 1353#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1354* 1355/* Buffer manager status register / 1356#define BGE_BMANSTAT_ERRO 0x00000004 1357#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1358* 1359 1360/* 1361 * Read DMA Control registers 1362 / 1363#define BGE_RDMA_MODE 0x4800 1364#define BGE_RDMA_STATUS 0x4804 1365* 1366/* Read DMA mode register / 1367#define BGE_RDMAMODE_RESET 0x00000001 1368#define BGE_RDMAMODE_ENABLE 0x00000002 1369#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1370#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1371#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1372#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1373#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1374#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1375#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1376#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1377#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1378#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1379#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1380* 1381/* Read DMA status register / 1382#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1383#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1384#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1385#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1386#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1387#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1388#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1389#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1390* 1391/* 1392 * Write DMA control registers 1393 / 1394#define BGE_WDMA_MODE 0x4C00 1395#define BGE_WDMA_STATUS 0x4C04 1396* 1397/* Write DMA mode register / 1398#define BGE_WDMAMODE_RESET 0x00000001 1399#define BGE_WDMAMODE_ENABLE 0x00000002 1400#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1401#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1402#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1403#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1404#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1405#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1406#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1407#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1408#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1409* 1410/* Write DMA status register / 1411#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1412#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1413#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1414#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1415#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1416#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1417#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1418#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1419* 1420 1421/* 1422 * RX CPU registers 1423 / 1424#define BGE_RXCPU_MODE 0x5000 1425#define BGE_RXCPU_STATUS 0x5004 1426#define BGE_RXCPU_PC 0x501C 1427* 1428/* RX CPU mode register / 1429#define BGE_RXCPUMODE_RESET 0x00000001 1430#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1431#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1432#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1433#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1434#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1435#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1436#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1437#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1438#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1439#define BGE_RXCPUMODE_HALTCPU 0x00000400 1440#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1441#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1442#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1443* 1444/* RX CPU status register / 1445#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1446#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1447#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1448#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1449#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1450#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1451#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1452#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1453#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1454#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1455#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1456#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1457#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1458#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1459#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1460#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1461#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1462* 1463/* 1464 * V? CPU registers 1465 / 1466#define BGE_VCPU_STATUS 0x5100 1467#define BGE_VCPU_EXT_CTRL 0x6890 1468* 1469#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1470#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1471 1472#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1473#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1474 1475/* 1476 * TX CPU registers 1477 / 1478#define BGE_TXCPU_MODE 0x5400 1479#define BGE_TXCPU_STATUS 0x5404 1480#define BGE_TXCPU_PC 0x541C 1481* 1482/* TX CPU mode register / 1483#define BGE_TXCPUMODE_RESET 0x00000001 1484#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1485#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1486#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1487#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1488#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1489#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1490#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1491#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1492#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1493#define BGE_TXCPUMODE_HALTCPU 0x00000400 1494#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1495#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1496* 1497/* TX CPU status register / 1498#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1499#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1500#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1501#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1502#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1503#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1504#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1505#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1506#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1507#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1508#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1509#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1510#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1511#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1512#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1513#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1514#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1515* 1516 1517/* 1518 * Low priority mailbox registers 1519 / 1520#define BGE_LPMBX_IRQ0_HI 0x5800 1521#define BGE_LPMBX_IRQ0_LO 0x5804 1522#define BGE_LPMBX_IRQ1_HI 0x5808 1523#define BGE_LPMBX_IRQ1_LO 0x580C 1524#define BGE_LPMBX_IRQ2_HI 0x5810 1525#define BGE_LPMBX_IRQ2_LO 0x5814 1526#define BGE_LPMBX_IRQ3_HI 0x5818 1527#define BGE_LPMBX_IRQ3_LO 0x581C 1528#define BGE_LPMBX_GEN0_HI 0x5820 1529#define BGE_LPMBX_GEN0_LO 0x5824 1530#define BGE_LPMBX_GEN1_HI 0x5828 1531#define BGE_LPMBX_GEN1_LO 0x582C 1532#define BGE_LPMBX_GEN2_HI 0x5830 1533#define BGE_LPMBX_GEN2_LO 0x5834 1534#define BGE_LPMBX_GEN3_HI 0x5828 1535#define BGE_LPMBX_GEN3_LO 0x582C 1536#define BGE_LPMBX_GEN4_HI 0x5840 1537#define BGE_LPMBX_GEN4_LO 0x5844 1538#define BGE_LPMBX_GEN5_HI 0x5848 1539#define BGE_LPMBX_GEN5_LO 0x584C 1540#define BGE_LPMBX_GEN6_HI 0x5850 1541#define BGE_LPMBX_GEN6_LO 0x5854 1542#define BGE_LPMBX_GEN7_HI 0x5858 1543#define BGE_LPMBX_GEN7_LO 0x585C 1544#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1545#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1546#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1547#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1548#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1549#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1550#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1551#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1552#define BGE_LPMBX_RX_CONS0_HI 0x5880 1553#define BGE_LPMBX_RX_CONS0_LO 0x5884 1554#define BGE_LPMBX_RX_CONS1_HI 0x5888 1555#define BGE_LPMBX_RX_CONS1_LO 0x588C 1556#define BGE_LPMBX_RX_CONS2_HI 0x5890 1557#define BGE_LPMBX_RX_CONS2_LO 0x5894 1558#define BGE_LPMBX_RX_CONS3_HI 0x5898 1559#define BGE_LPMBX_RX_CONS3_LO 0x589C 1560#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1561#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1562#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1563#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1564#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1565#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1566#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1567#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1568#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1569#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1570#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1571#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1572#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1573#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1574#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1575#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1576#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1577#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1578#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1579#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1580#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1581#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1582#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1583#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1584#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1585#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1586#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1587#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1588#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1589#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1590#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1591#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1592#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1593#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1594#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1595#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1596#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1597#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1598#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1599#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1600#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1601#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1602#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1603#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1604#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1605#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1606#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1607#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1608#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1609#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1610#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1611#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1612#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1613#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1614#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1615#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1616#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1617#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1618#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1619#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1620#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1621#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1622#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1623#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1624#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1625#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1626#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1627#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1628#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1629#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1630#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1631#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1632#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1633#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1634#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1635#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1636#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1637#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1638#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1639#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1640#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1641#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1642#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1643#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1644#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1645#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1646#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1647#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1648* 1649/* 1650 * Flow throw Queue reset register 1651 / 1652#define BGE_FTQ_RESET 0x5C00 1653* 1654#define BGE_FTQRESET_DMAREAD 0x00000002 1655#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1656#define BGE_FTQRESET_DMADONE 0x00000010 1657#define BGE_FTQRESET_SBDC 0x00000020 1658#define BGE_FTQRESET_SDI 0x00000040 1659#define BGE_FTQRESET_WDMA 0x00000080 1660#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1661#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1662#define BGE_FTQRESET_SDC 0x00000400 1663#define BGE_FTQRESET_HCC 0x00000800 1664#define BGE_FTQRESET_TXFIFO 0x00001000 1665#define BGE_FTQRESET_MBC 0x00002000 1666#define BGE_FTQRESET_RBDC 0x00004000 1667#define BGE_FTQRESET_RXLP 0x00008000 1668#define BGE_FTQRESET_RDBDI 0x00010000 1669#define BGE_FTQRESET_RDC 0x00020000 1670#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1671 1672/* 1673 * Message Signaled Interrupt registers 1674 / 1675#define BGE_MSI_MODE 0x6000 1676#define BGE_MSI_STATUS 0x6004 1677#define BGE_MSI_FIFOACCESS 0x6008 1678* 1679/* MSI mode register / 1680#define BGE_MSIMODE_RESET 0x00000001 1681#define BGE_MSIMODE_ENABLE 0x00000002 1682#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1683#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1684#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1685#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1686#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1687* 1688/* MSI status register / 1689#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1690#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1691#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1692#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1693#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1694* 1695 1696/* 1697 * DMA Completion registers 1698 / 1699#define BGE_DMAC_MODE 0x6400 1700* 1701/* DMA Completion mode register / 1702#define BGE_DMACMODE_RESET 0x00000001 1703#define BGE_DMACMODE_ENABLE 0x00000002 1704* 1705 1706/* 1707 * General control registers. 1708 / 1709#define BGE_MODE_CTL 0x6800 1710#define BGE_MISC_CFG 0x6804 1711#define BGE_MISC_LOCAL_CTL 0x6808 1712#define BGE_CPU_EVENT 0x6810 1713#define BGE_EE_ADDR 0x6838 1714#define BGE_EE_DATA 0x683C 1715#define BGE_EE_CTL 0x6840 1716#define BGE_MDI_CTL 0x6844 1717#define BGE_EE_DELAY 0x6848 1718#define BGE_FASTBOOT_PC 0x6894 1719* 1720/* 1721 * NVRAM Control registers 1722 / 1723#define BGE_NVRAM_CMD 0x7000 1724#define BGE_NVRAM_STAT 0x7004 1725#define BGE_NVRAM_WRDATA 0x7008 1726#define BGE_NVRAM_ADDR 0x700c 1727#define BGE_NVRAM_RDDATA 0x7010 1728#define BGE_NVRAM_CFG1 0x7014 1729#define BGE_NVRAM_CFG2 0x7018 1730#define BGE_NVRAM_CFG3 0x701c 1731#define BGE_NVRAM_SWARB 0x7020 1732#define BGE_NVRAM_ACCESS 0x7024 1733#define BGE_NVRAM_WRITE1 0x7028 1734* 1735#define BGE_NVRAMCMD_RESET 0x00000001 1736#define BGE_NVRAMCMD_DONE 0x00000008 1737#define BGE_NVRAMCMD_START 0x00000010 1738#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1739#define BGE_NVRAMCMD_ERASE 0x00000040 1740#define BGE_NVRAMCMD_FIRST 0x00000080 1741#define BGE_NVRAMCMD_LAST 0x00000100 1742* 1743#define BGE_NVRAM_READCMD \ 1744 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1745 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1746#define BGE_NVRAM_WRITECMD \ 1747 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1748 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1749 1750#define BGE_NVRAMSWARB_SET0 0x00000001 1751#define BGE_NVRAMSWARB_SET1 0x00000002 1752#define BGE_NVRAMSWARB_SET2 0x00000003 1753#define BGE_NVRAMSWARB_SET3 0x00000004 1754#define BGE_NVRAMSWARB_CLR0 0x00000010 1755#define BGE_NVRAMSWARB_CLR1 0x00000020 1756#define BGE_NVRAMSWARB_CLR2 0x00000040 1757#define BGE_NVRAMSWARB_CLR3 0x00000080 1758#define BGE_NVRAMSWARB_GNT0 0x00000100 1759#define BGE_NVRAMSWARB_GNT1 0x00000200 1760#define BGE_NVRAMSWARB_GNT2 0x00000400 1761#define BGE_NVRAMSWARB_GNT3 0x00000800 1762#define BGE_NVRAMSWARB_REQ0 0x00001000 1763#define BGE_NVRAMSWARB_REQ1 0x00002000 1764#define BGE_NVRAMSWARB_REQ2 0x00004000 1765#define BGE_NVRAMSWARB_REQ3 0x00008000 1766 1767#define BGE_NVRAMACC_ENABLE 0x00000001 1768#define BGE_NVRAMACC_WRENABLE 0x00000002 1769 1770/* Mode control register / 1771#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1772#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1773#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1774#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1775#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1776#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1777#define BGE_MODECTL_NO_RX_CRC 0x00000400 1778#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1779#define BGE_MODECTL_NO_TX_INTR 0x00002000 1780#define BGE_MODECTL_NO_RX_INTR 0x00004000 1781#define BGE_MODECTL_FORCE_PCI32 0x00008000 1782#define BGE_MODECTL_STACKUP 0x00010000 1783#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1784#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1785#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1786#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1787#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1788#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1789#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1790#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1791#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1792#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1793* 1794/* Misc. config register / 1795#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1796#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1797#define BGE_MISCCFG_BOARD_ID 0x0001E000 1798#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1799#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1800#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1801* 1802#define BGE_32BITTIME_66MHZ (0x41 << 1) 1803 1804/* Misc. Local Control / 1805#define BGE_MLC_INTR_STATE 0x00000001 1806#define BGE_MLC_INTR_CLR 0x00000002 1807#define BGE_MLC_INTR_SET 0x00000004 1808#define BGE_MLC_INTR_ONATTN 0x00000008 1809#define BGE_MLC_MISCIO_IN0 0x00000100 1810#define BGE_MLC_MISCIO_IN1 0x00000200 1811#define BGE_MLC_MISCIO_IN2 0x00000400 1812#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1813#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1814#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1815#define BGE_MLC_MISCIO_OUT0 0x00004000 1816#define BGE_MLC_MISCIO_OUT1 0x00008000 1817#define BGE_MLC_MISCIO_OUT2 0x00010000 1818#define BGE_MLC_EXTRAM_ENB 0x00020000 1819#define BGE_MLC_SRAM_SIZE 0x001C0000 1820#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1821#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1822#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1823#define BGE_MLC_AUTO_EEPROM 0x01000000 1824* 1825#define BGE_SSRAMSIZE_256KB 0x00000000 1826#define BGE_SSRAMSIZE_512KB 0x00040000 1827#define BGE_SSRAMSIZE_1MB 0x00080000 1828#define BGE_SSRAMSIZE_2MB 0x000C0000 1829#define BGE_SSRAMSIZE_4MB 0x00100000 1830#define BGE_SSRAMSIZE_8MB 0x00140000 1831#define BGE_SSRAMSIZE_16M 0x00180000 1832 1833/* EEPROM address register / 1834#define BGE_EEADDR_ADDRESS 0x0000FFFC 1835#define BGE_EEADDR_HALFCLK 0x01FF0000 1836#define BGE_EEADDR_START 0x02000000 1837#define BGE_EEADDR_DEVID 0x1C000000 1838#define BGE_EEADDR_RESET 0x20000000 1839#define BGE_EEADDR_DONE 0x40000000 1840#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1841* 1842#define BGE_EEDEVID(x) ((x & 7) << 26) 1843#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1844#define BGE_HALFCLK_384SCL 0x60 1845#define BGE_EE_READCMD \ 1846 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1847 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1848#define BGE_EE_WRCMD \ 1849 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1850 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1851 1852/* EEPROM Control register / 1853#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1854#define BGE_EECTL_CLKOUT 0x00000002 1855#define BGE_EECTL_CLKIN 0x00000004 1856#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1857#define BGE_EECTL_DATAOUT 0x00000010 1858#define BGE_EECTL_DATAIN 0x00000020 1859* 1860/* MDI (MII/GMII) access register / 1861#define BGE_MDI_DATA 0x00000001 1862#define BGE_MDI_DIR 0x00000002 1863#define BGE_MDI_SEL 0x00000004 1864#define BGE_MDI_CLK 0x00000008 1865* 1866#define BGE_MEMWIN_START 0x00008000 1867#define BGE_MEMWIN_END 0x0000FFFF 1868 1869 1870#define BGE_MEMWIN_READ(sc, x, val) \ 1871 do { \ 1872 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1873 (0xFFFF0000 & x), 4); \ 1874 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1875 } while(0) 1876 1877#define BGE_MEMWIN_WRITE(sc, x, val) \ 1878 do { \ 1879 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1880 (0xFFFF0000 & x), 4); \ 1881 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1882 } while(0) 1883 1884/* 1885 * This magic number is written to the firmware mailbox at 0xb50 1886 * before a software reset is issued. After the internal firmware 1887 * has completed its initialization it will write the opposite of 1888 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1889 * driver to synchronize with the firmware. 1890 / 1891#define BGE_MAGIC_NUMBER 0x4B657654 1892* 1893typedef struct { 1894 uint32_t bge_addr_hi; 1895 uint32_t bge_addr_lo; 1896} bge_hostaddr; 1897 1898#define BGE_HOSTADDR(x, y) \ 1899 do { \ 1900 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1901 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1902 } while(0) 1903 1904#define BGE_ADDR_LO(y) \ 1905 ((uint64_t) (y) & 0xFFFFFFFF) 1906#define BGE_ADDR_HI(y) \ 1907 ((uint64_t) (y) >> 32) 1908 1909/* Ring control block structure / 1910struct bge_rcb { 1911* bge_hostaddr bge_hostaddr; 1912 uint32_t bge_maxlen_flags; 1913 uint32_t bge_nicaddr; 1914}; 1915 1916#define RCB_WRITE_4(sc, rcb, offset, val) \ 1917 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1918#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1919 1920#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1921#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1922 1923struct bge_tx_bd { 1924 bge_hostaddr bge_addr; 1925#if BYTE_ORDER == LITTLE_ENDIAN 1926 uint16_t bge_flags; 1927 uint16_t bge_len; 1928 uint16_t bge_vlan_tag; 1929 uint16_t bge_rsvd; 1930#else 1931 uint16_t bge_len; 1932 uint16_t bge_flags; 1933 uint16_t bge_rsvd; 1934 uint16_t bge_vlan_tag; 1935#endif 1936}; 1937 1938#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1939#define BGE_TXBDFLAG_IP_CSUM 0x0002 1940#define BGE_TXBDFLAG_END 0x0004 1941#define BGE_TXBDFLAG_IP_FRAG 0x0008 1942#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1943#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1944#define BGE_TXBDFLAG_COAL_NOW 0x0080 1945#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1946#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1947#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1948#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1949#define BGE_TXBDFLAG_NO_CRC 0x8000 1950 1951#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1952 BGE_SEND_RING_1_TO_4 + \ 1953 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1954 1955struct bge_rx_bd { 1956 bge_hostaddr bge_addr; 1957#if BYTE_ORDER == LITTLE_ENDIAN 1958 uint16_t bge_len; 1959 uint16_t bge_idx; 1960 uint16_t bge_flags; 1961 uint16_t bge_type; 1962 uint16_t bge_tcp_udp_csum; 1963 uint16_t bge_ip_csum; 1964 uint16_t bge_vlan_tag; 1965 uint16_t bge_error_flag; 1966#else 1967 uint16_t bge_idx; 1968 uint16_t bge_len; 1969 uint16_t bge_type; 1970 uint16_t bge_flags; 1971 uint16_t bge_ip_csum; 1972 uint16_t bge_tcp_udp_csum; 1973 uint16_t bge_error_flag; 1974 uint16_t bge_vlan_tag; 1975#endif 1976 uint32_t bge_rsvd; 1977 uint32_t bge_opaque; 1978}; 1979 1980struct bge_extrx_bd { 1981 bge_hostaddr bge_addr1; 1982 bge_hostaddr bge_addr2; 1983 bge_hostaddr bge_addr3; 1984#if BYTE_ORDER == LITTLE_ENDIAN 1985 uint16_t bge_len2; 1986 uint16_t bge_len1; 1987 uint16_t bge_rsvd1; 1988 uint16_t bge_len3; 1989#else 1990 uint16_t bge_len1; 1991 uint16_t bge_len2; 1992 uint16_t bge_len3; 1993 uint16_t bge_rsvd1; 1994#endif 1995 bge_hostaddr bge_addr0; 1996#if BYTE_ORDER == LITTLE_ENDIAN 1997 uint16_t bge_len0; 1998 uint16_t bge_idx; 1999 uint16_t bge_flags; 2000 uint16_t bge_type; 2001 uint16_t bge_tcp_udp_csum; 2002 uint16_t bge_ip_csum; 2003 uint16_t bge_vlan_tag; 2004 uint16_t bge_error_flag; 2005#else 2006 uint16_t bge_idx; 2007 uint16_t bge_len0; 2008 uint16_t bge_type; 2009 uint16_t bge_flags; 2010 uint16_t bge_ip_csum; 2011 uint16_t bge_tcp_udp_csum; 2012 uint16_t bge_error_flag; 2013 uint16_t bge_vlan_tag; 2014#endif 2015 uint32_t bge_rsvd0; 2016 uint32_t bge_opaque; 2017}; 2018 2019#define BGE_RXBDFLAG_END 0x0004 2020#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2021#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2022#define BGE_RXBDFLAG_ERROR 0x0400 2023#define BGE_RXBDFLAG_MINI_RING 0x0800 2024#define BGE_RXBDFLAG_IP_CSUM 0x1000 2025#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2026#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2027 2028#define BGE_RXERRFLAG_BAD_CRC 0x0001 2029#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2030#define BGE_RXERRFLAG_LINK_LOST 0x0004 2031#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2032#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2033#define BGE_RXERRFLAG_RUNT 0x0020 2034#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2035#define BGE_RXERRFLAG_GIANT 0x0080 2036 2037struct bge_sts_idx { 2038#if BYTE_ORDER == LITTLE_ENDIAN 2039 uint16_t bge_rx_prod_idx; 2040 uint16_t bge_tx_cons_idx; 2041#else 2042 uint16_t bge_tx_cons_idx; 2043 uint16_t bge_rx_prod_idx; 2044#endif 2045}; 2046 2047struct bge_status_block { 2048 uint32_t bge_status; 2049 uint32_t bge_rsvd0; 2050#if BYTE_ORDER == LITTLE_ENDIAN 2051 uint16_t bge_rx_jumbo_cons_idx; 2052 uint16_t bge_rx_std_cons_idx; 2053 uint16_t bge_rx_mini_cons_idx; 2054 uint16_t bge_rsvd1; 2055#else 2056 uint16_t bge_rx_std_cons_idx; 2057 uint16_t bge_rx_jumbo_cons_idx; 2058 uint16_t bge_rsvd1; 2059 uint16_t bge_rx_mini_cons_idx; 2060#endif 2061 struct bge_sts_idx bge_idx[16]; 2062}; 2063 2064#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2065#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2066 2067#define BGE_STATFLAG_UPDATED 0x00000001 2068#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2069#define BGE_STATFLAG_ERROR 0x00000004 2070 2071 2072/* 2073 * Broadcom Vendor ID 2074 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2075 * even though they're now manufactured by Broadcom) 2076 / 2077#define BCOM_VENDORID 0x14E4 2078#define BCOM_DEVICEID_BCM5700 0x1644 2079#define BCOM_DEVICEID_BCM5701 0x1645 2080#define BCOM_DEVICEID_BCM5702 0x1646 2081#define BCOM_DEVICEID_BCM5702X 0x16A6 2082#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2083#define BCOM_DEVICEID_BCM5703 0x1647 2084#define BCOM_DEVICEID_BCM5703X 0x16A7 2085#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2086#define BCOM_DEVICEID_BCM5704C 0x1648 2087#define BCOM_DEVICEID_BCM5704S 0x16A8 2088#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2089#define BCOM_DEVICEID_BCM5705 0x1653 2090#define BCOM_DEVICEID_BCM5705K 0x1654 2091#define BCOM_DEVICEID_BCM5705F 0x166E 2092#define BCOM_DEVICEID_BCM5705M 0x165D 2093#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2094#define BCOM_DEVICEID_BCM5714C 0x1668 2095#define BCOM_DEVICEID_BCM5714S 0x1669 2096#define BCOM_DEVICEID_BCM5715 0x1678 2097#define BCOM_DEVICEID_BCM5715S 0x1679 2098#define BCOM_DEVICEID_BCM5720 0x1658 2099#define BCOM_DEVICEID_BCM5721 0x1659 2100#define BCOM_DEVICEID_BCM5722 0x165A 2101#define BCOM_DEVICEID_BCM5750 0x1676 2102#define BCOM_DEVICEID_BCM5750M 0x167C 2103#define BCOM_DEVICEID_BCM5751 0x1677 2104#define BCOM_DEVICEID_BCM5751F 0x167E 2105#define BCOM_DEVICEID_BCM5751M 0x167D 2106#define BCOM_DEVICEID_BCM5752 0x1600 2107#define BCOM_DEVICEID_BCM5752M 0x1601 2108#define BCOM_DEVICEID_BCM5753 0x16F7 2109#define BCOM_DEVICEID_BCM5753F 0x16FE 2110#define BCOM_DEVICEID_BCM5753M 0x16FD 2111#define BCOM_DEVICEID_BCM5754 0x167A 2112#define BCOM_DEVICEID_BCM5754M 0x1672 2113#define BCOM_DEVICEID_BCM5755 0x167B 2114#define BCOM_DEVICEID_BCM5755M 0x1673 2115#define BCOM_DEVICEID_BCM5780 0x166A 2116#define BCOM_DEVICEID_BCM5780S 0x166B 2117#define BCOM_DEVICEID_BCM5781 0x16DD 2118#define BCOM_DEVICEID_BCM5782 0x1696 2119#define BCOM_DEVICEID_BCM5786 0x169A 2120#define BCOM_DEVICEID_BCM5787 0x169B 2121#define BCOM_DEVICEID_BCM5787M 0x1693 2122#define BCOM_DEVICEID_BCM5788 0x169C 2123#define BCOM_DEVICEID_BCM5789 0x169D 2124#define BCOM_DEVICEID_BCM5901 0x170D 2125#define BCOM_DEVICEID_BCM5901A2 0x170E 2126#define BCOM_DEVICEID_BCM5903M 0x16FF 2127#define BCOM_DEVICEID_BCM5906 0x1712 2128#define BCOM_DEVICEID_BCM5906M 0x1713 2129* 2130/* 2131 * Alteon AceNIC PCI vendor/device ID. 2132 / 2133#define ALTEON_VENDORID 0x12AE 2134#define ALTEON_DEVICEID_ACENIC 0x0001 2135#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2136#define ALTEON_DEVICEID_BCM5700 0x0003 2137#define ALTEON_DEVICEID_BCM5701 0x0004 2138* 2139/* 2140 * 3Com 3c996 PCI vendor/device ID. 2141 / 2142#define TC_VENDORID 0x10B7 2143#define TC_DEVICEID_3C996 0x0003 2144* 2145/* 2146 * SysKonnect PCI vendor ID 2147 / 2148#define SK_VENDORID 0x1148 2149#define SK_DEVICEID_ALTIMA 0x4400 2150#define SK_SUBSYSID_9D21 0x4421 2151#define SK_SUBSYSID_9D41 0x4441 2152* 2153/* 2154 * Altima PCI vendor/device ID. 2155 / 2156#define ALTIMA_VENDORID 0x173b 2157#define ALTIMA_DEVICE_AC1000 0x03e8 2158#define ALTIMA_DEVICE_AC1002 0x03e9 2159#define ALTIMA_DEVICE_AC9100 0x03ea 2160* 2161/* 2162 * Dell PCI vendor ID 2163 / 2164* 2165#define DELL_VENDORID 0x1028 2166 2167/* 2168 * Apple PCI vendor ID. 2169 / 2170#define APPLE_VENDORID 0x106b 2171#define APPLE_DEVICE_BCM5701 0x1645 2172* 2173/* 2174 * Sun PCI vendor ID 2175 / 2176#define SUN_VENDORID 0x108e 2177* 2178/* 2179 * Offset of MAC address inside EEPROM. 2180 / 2181#define BGE_EE_MAC_OFFSET 0x7C 2182#define BGE_EE_MAC_OFFSET_5906 0x10 2183#define BGE_EE_HWCFG_OFFSET 0xC8 2184* 2185#define BGE_HWCFG_VOLTAGE 0x00000003 2186#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2187#define BGE_HWCFG_MEDIA 0x00000030 2188#define BGE_HWCFG_ASF 0x00000080 2189 2190#define BGE_VOLTAGE_1POINT3 0x00000000 2191#define BGE_VOLTAGE_1POINT8 0x00000001 2192 2193#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2194#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2195#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2196 2197#define BGE_MEDIA_UNSPEC 0x00000000 2198#define BGE_MEDIA_COPPER 0x00000010 2199#define BGE_MEDIA_FIBER 0x00000020 2200 2201#define BGE_TICKS_PER_SEC 1000000 2202 2203/* 2204 * Ring size constants. 2205 / 2206#define BGE_EVENT_RING_CNT 256 2207#define BGE_CMD_RING_CNT 64 2208#define BGE_STD_RX_RING_CNT 512 2209#define BGE_JUMBO_RX_RING_CNT 256 2210#define BGE_MINI_RX_RING_CNT 1024 2211#define BGE_RETURN_RING_CNT 1024 2212* 2213/* 5705 has smaller return ring size / 2214* 2215#define BGE_RETURN_RING_CNT_5705 512 2216 2217/* 2218 * Possible TX ring sizes. 2219 / 2220#define BGE_TX_RING_CNT_128 128 2221#define BGE_TX_RING_BASE_128 0x3800 2222* 2223#define BGE_TX_RING_CNT_256 256 2224#define BGE_TX_RING_BASE_256 0x3000 2225 2226#define BGE_TX_RING_CNT_512 512 2227#define BGE_TX_RING_BASE_512 0x2000 2228 2229#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2230#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2231 2232/* 2233 * Tigon III statistics counters. 2234 / 2235/ Statistics maintained MAC Receive block. / 2236struct bge_rx_mac_stats { 2237* bge_hostaddr ifHCInOctets; 2238 bge_hostaddr Reserved1; 2239 bge_hostaddr etherStatsFragments; 2240 bge_hostaddr ifHCInUcastPkts; 2241 bge_hostaddr ifHCInMulticastPkts; 2242 bge_hostaddr ifHCInBroadcastPkts; 2243 bge_hostaddr dot3StatsFCSErrors; 2244 bge_hostaddr dot3StatsAlignmentErrors; 2245 bge_hostaddr xonPauseFramesReceived; 2246 bge_hostaddr xoffPauseFramesReceived; 2247 bge_hostaddr macControlFramesReceived; 2248 bge_hostaddr xoffStateEntered; 2249 bge_hostaddr dot3StatsFramesTooLong; 2250 bge_hostaddr etherStatsJabbers; 2251 bge_hostaddr etherStatsUndersizePkts; 2252 bge_hostaddr inRangeLengthError; 2253 bge_hostaddr outRangeLengthError; 2254 bge_hostaddr etherStatsPkts64Octets; 2255 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2256 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2257 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2258 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2259 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2260 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2261 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2262 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2263 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2264}; 2265 2266 2267/* Statistics maintained MAC Transmit block. / 2268struct bge_tx_mac_stats { 2269* bge_hostaddr ifHCOutOctets; 2270 bge_hostaddr Reserved2; 2271 bge_hostaddr etherStatsCollisions; 2272 bge_hostaddr outXonSent; 2273 bge_hostaddr outXoffSent; 2274 bge_hostaddr flowControlDone; 2275 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2276 bge_hostaddr dot3StatsSingleCollisionFrames; 2277 bge_hostaddr dot3StatsMultipleCollisionFrames; 2278 bge_hostaddr dot3StatsDeferredTransmissions; 2279 bge_hostaddr Reserved3; 2280 bge_hostaddr dot3StatsExcessiveCollisions; 2281 bge_hostaddr dot3StatsLateCollisions; 2282 bge_hostaddr dot3Collided2Times; 2283 bge_hostaddr dot3Collided3Times; 2284 bge_hostaddr dot3Collided4Times; 2285 bge_hostaddr dot3Collided5Times; 2286 bge_hostaddr dot3Collided6Times; 2287 bge_hostaddr dot3Collided7Times; 2288 bge_hostaddr dot3Collided8Times; 2289 bge_hostaddr dot3Collided9Times; 2290 bge_hostaddr dot3Collided10Times; 2291 bge_hostaddr dot3Collided11Times; 2292 bge_hostaddr dot3Collided12Times; 2293 bge_hostaddr dot3Collided13Times; 2294 bge_hostaddr dot3Collided14Times; 2295 bge_hostaddr dot3Collided15Times; 2296 bge_hostaddr ifHCOutUcastPkts; 2297 bge_hostaddr ifHCOutMulticastPkts; 2298 bge_hostaddr ifHCOutBroadcastPkts; 2299 bge_hostaddr dot3StatsCarrierSenseErrors; 2300 bge_hostaddr ifOutDiscards; 2301 bge_hostaddr ifOutErrors; 2302}; 2303 2304/* Stats counters access through registers / 2305struct bge_mac_stats_regs { 2306* uint32_t ifHCOutOctets; 2307 uint32_t Reserved0; 2308 uint32_t etherStatsCollisions; 2309 uint32_t outXonSent; 2310 uint32_t outXoffSent; 2311 uint32_t Reserved1; 2312 uint32_t dot3StatsInternalMacTransmitErrors; 2313 uint32_t dot3StatsSingleCollisionFrames; 2314 uint32_t dot3StatsMultipleCollisionFrames; 2315 uint32_t dot3StatsDeferredTransmissions; 2316 uint32_t Reserved2; 2317 uint32_t dot3StatsExcessiveCollisions; 2318 uint32_t dot3StatsLateCollisions; 2319 uint32_t Reserved3[14]; 2320 uint32_t ifHCOutUcastPkts; 2321 uint32_t ifHCOutMulticastPkts; 2322 uint32_t ifHCOutBroadcastPkts; 2323 uint32_t Reserved4[2]; 2324 uint32_t ifHCInOctets; 2325 uint32_t Reserved5; 2326 uint32_t etherStatsFragments; 2327 uint32_t ifHCInUcastPkts; 2328 uint32_t ifHCInMulticastPkts; 2329 uint32_t ifHCInBroadcastPkts; 2330 uint32_t dot3StatsFCSErrors; 2331 uint32_t dot3StatsAlignmentErrors; 2332 uint32_t xonPauseFramesReceived; 2333 uint32_t xoffPauseFramesReceived; 2334 uint32_t macControlFramesReceived; 2335 uint32_t xoffStateEntered; 2336 uint32_t dot3StatsFramesTooLong; 2337 uint32_t etherStatsJabbers; 2338 uint32_t etherStatsUndersizePkts; 2339}; 2340 2341struct bge_stats { 2342 uint8_t Reserved0[256]; 2343 2344 /* Statistics maintained by Receive MAC. / 2345* struct bge_rx_mac_stats rxstats; 2346 2347 bge_hostaddr Unused1[37]; 2348 2349 /* Statistics maintained by Transmit MAC. / 2350* struct bge_tx_mac_stats txstats; 2351 2352 bge_hostaddr Unused2[31]; 2353 2354 /* Statistics maintained by Receive List Placement. / 2355* bge_hostaddr COSIfHCInPkts[16]; 2356 bge_hostaddr COSFramesDroppedDueToFilters; 2357 bge_hostaddr nicDmaWriteQueueFull; 2358 bge_hostaddr nicDmaWriteHighPriQueueFull; 2359 bge_hostaddr nicNoMoreRxBDs; 2360 bge_hostaddr ifInDiscards; 2361 bge_hostaddr ifInErrors; 2362 bge_hostaddr nicRecvThresholdHit; 2363 2364 bge_hostaddr Unused3[9]; 2365 2366 /* Statistics maintained by Send Data Initiator. / 2367* bge_hostaddr COSIfHCOutPkts[16]; 2368 bge_hostaddr nicDmaReadQueueFull; 2369 bge_hostaddr nicDmaReadHighPriQueueFull; 2370 bge_hostaddr nicSendDataCompQueueFull; 2371 2372 /* Statistics maintained by Host Coalescing. / 2373* bge_hostaddr nicRingSetSendProdIndex; 2374 bge_hostaddr nicRingStatusUpdate; 2375 bge_hostaddr nicInterrupts; 2376 bge_hostaddr nicAvoidedInterrupts; 2377 bge_hostaddr nicSendThresholdHit; 2378 2379 uint8_t Reserved4[320]; 2380}; 2381 2382/* 2383 * Tigon general information block. This resides in host memory 2384 * and contains the status counters, ring control blocks and 2385 * producer pointers. 2386 / 2387* 2388struct bge_gib { 2389 struct bge_stats bge_stats; 2390 struct bge_rcb bge_tx_rcb[16]; 2391 struct bge_rcb bge_std_rx_rcb; 2392 struct bge_rcb bge_jumbo_rx_rcb; 2393 struct bge_rcb bge_mini_rx_rcb; 2394 struct bge_rcb bge_return_rcb; 2395}; 2396 2397#define BGE_FRAMELEN 1518 2398#define BGE_MAX_FRAMELEN 1536 2399#define BGE_JUMBO_FRAMELEN 9018 2400#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2401#define BGE_MIN_FRAMELEN 60 2402 2403/* 2404 * Other utility macros. 2405 / 2406#define BGE_INC(x, y) (x) = (x + 1) % y 2407* 2408/* 2409 * Register access macros. The Tigon always uses memory mapped register 2410 * accesses and all registers must be accessed with 32 bit operations. 2411 / 2412* 2413#define CSR_WRITE_4(sc, reg, val) \ 2414 bus_write_4(sc->bge_res, reg, val) 2415 2416#define CSR_READ_4(sc, reg) \ 2417 bus_read_4(sc->bge_res, reg) 2418 2419#define BGE_SETBIT(sc, reg, x) \ 2420 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2421#define BGE_CLRBIT(sc, reg, x) \ 2422 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2423 2424#define PCI_SETBIT(dev, reg, x, s) \ 2425 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2426#define PCI_CLRBIT(dev, reg, x, s) \ 2427 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2428 2429/* 2430 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2431 * values are tuneable. They control the actual amount of buffers 2432 * allocated for the standard, mini and jumbo receive rings. 2433 / 2434* 2435#define BGE_SSLOTS 256 2436#define BGE_MSLOTS 256 2437#define BGE_JSLOTS 384 2438 2439#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2440#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2441 (BGE_JRAWLEN % sizeof(uint64_t)))) 2442#define BGE_JPAGESZ PAGE_SIZE 2443#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2444#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2445 2446#define BGE_NSEG_JUMBO 4 2447#define BGE_NSEG_NEW 32 2448 2449/* 2450 * Ring structures. Most of these reside in host memory and we tell 2451 * the NIC where they are via the ring control blocks. The exceptions 2452 * are the tx and command rings, which live in NIC memory and which 2453 * we access via the shared memory window. 2454 / 2455* 2456struct bge_ring_data { 2457 struct bge_rx_bd bge_rx_std_ring; 2458* bus_addr_t bge_rx_std_ring_paddr; 2459 struct bge_extrx_bd bge_rx_jumbo_ring; 2460* bus_addr_t bge_rx_jumbo_ring_paddr; 2461 struct bge_rx_bd bge_rx_return_ring; 2462* bus_addr_t bge_rx_return_ring_paddr; 2463 struct bge_tx_bd bge_tx_ring; 2464* bus_addr_t bge_tx_ring_paddr; 2465 struct bge_status_block bge_status_block; 2466* bus_addr_t bge_status_block_paddr; 2467 struct bge_stats bge_stats; 2468* bus_addr_t bge_stats_paddr; 2469 struct bge_gib bge_info; 2470}; 2471 2472#define BGE_STD_RX_RING_SZ \ 2473 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2474#define BGE_JUMBO_RX_RING_SZ \ 2475 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2476#define BGE_TX_RING_SZ \ 2477 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2478#define BGE_RX_RTN_RING_SZ(x) \ 2479 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2480 2481#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2482 2483#define BGE_STATS_SZ sizeof (struct bge_stats) 2484 2485/* 2486 * Mbuf pointers. We need these to keep track of the virtual addresses 2487 * of our mbuf chains since we can only convert from physical to virtual, 2488 * not the other way around. 2489 / 2490struct bge_chain_data { 2491* bus_dma_tag_t bge_parent_tag; 2492 bus_dma_tag_t bge_rx_std_ring_tag; 2493 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2494 bus_dma_tag_t bge_rx_return_ring_tag; 2495 bus_dma_tag_t bge_tx_ring_tag; 2496 bus_dma_tag_t bge_status_tag; 2497 bus_dma_tag_t bge_stats_tag; 2498 bus_dma_tag_t bge_mtag; /* mbuf mapping tag / 2499* bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag / 2500* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2501 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2502 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2503 bus_dmamap_t bge_rx_std_ring_map; 2504 bus_dmamap_t bge_rx_jumbo_ring_map; 2505 bus_dmamap_t bge_tx_ring_map; 2506 bus_dmamap_t bge_rx_return_ring_map; 2507 bus_dmamap_t bge_status_map; 2508 bus_dmamap_t bge_stats_map; 2509 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2510* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2511* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2512}; 2513* 2514struct bge_dmamap_arg { 2515 struct bge_softc sc; 2516* bus_addr_t bge_busaddr; 2517 uint16_t bge_flags; 2518 int bge_idx; 2519 int bge_maxsegs; 2520 struct bge_tx_bd bge_ring; 2521}; 2522* 2523#define BGE_HWREV_TIGON 0x01 2524#define BGE_HWREV_TIGON_II 0x02 2525#define BGE_TIMEOUT 100000 2526#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2527* 2528struct bge_bcom_hack { 2529 int reg; 2530 int val; 2531}; 2532 2533#define ASF_ENABLE 1 2534#define ASF_NEW_HANDSHAKE 2 2535#define ASF_STACKUP 4 2536 2537struct bge_softc { 2538 struct ifnet bge_ifp; / interface info / 2539* device_t bge_dev; 2540 struct mtx bge_mtx; 2541 device_t bge_miibus; 2542 void bge_intrhand; 2543* struct resource bge_irq; 2544* struct resource bge_res; 2545* struct ifmedia bge_ifmedia; /* TBI media info / 2546* uint32_t bge_flags; 2547#define BGE_FLAG_TBI 0x00000001 2548#define BGE_FLAG_JUMBO 0x00000002 2549#define BGE_FLAG_WIRESPEED 0x00000004 2550#define BGE_FLAG_EADDR 0x00000008 2551#define BGE_FLAG_MSI 0x00000100 2552#define BGE_FLAG_PCIX 0x00000200 2553#define BGE_FLAG_PCIE 0x00000400 2554#define BGE_FLAG_5700_FAMILY 0x00001000 2555#define BGE_FLAG_5705_PLUS 0x00002000 2556#define BGE_FLAG_5714_FAMILY 0x00004000 2557#define BGE_FLAG_575X_PLUS 0x00008000 2558#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2559#define BGE_FLAG_NO_3LED 0x00200000 2560#define BGE_FLAG_ADC_BUG 0x00400000 2561#define BGE_FLAG_5704_A0_BUG 0x00800000 2562#define BGE_FLAG_JITTER_BUG 0x01000000 2563#define BGE_FLAG_BER_BUG 0x02000000 2564#define BGE_FLAG_ADJUST_TRIM 0x04000000 2565#define BGE_FLAG_CRC_BUG 0x08000000 2566#define BGE_FLAG_5788 0x20000000 2567 uint32_t bge_chipid; 2568 uint8_t bge_asicrev; 2569 uint8_t bge_chiprev; 2570 uint8_t bge_asf_mode; 2571 uint8_t bge_asf_count; 2572 struct bge_ring_data bge_ldata; /* rings / 2573* struct bge_chain_data bge_cdata; /* mbufs / 2574* uint16_t bge_tx_saved_considx; 2575 uint16_t bge_rx_saved_considx; 2576 uint16_t bge_ev_saved_considx; 2577 uint16_t bge_return_ring_cnt; 2578 uint16_t bge_std; /* current std ring head / 2579* uint16_t bge_jumbo; /* current jumo ring head / 2580* uint32_t bge_stat_ticks; 2581 uint32_t bge_rx_coal_ticks; 2582 uint32_t bge_tx_coal_ticks; 2583 uint32_t bge_tx_prodidx; 2584 uint32_t bge_rx_max_coal_bds; 2585 uint32_t bge_tx_max_coal_bds; 2586 uint32_t bge_tx_buf_ratio; 2587 int bge_if_flags; 2588 int bge_txcnt; 2589 int bge_link; /* link state / 2590* int bge_link_evt; /* pending link event / 2591* int bge_timer; 2592 struct callout bge_stat_ch; 2593 uint32_t bge_rx_discards; 2594 uint32_t bge_tx_discards; 2595 uint32_t bge_tx_collisions; 2596#ifdef DEVICE_POLLING 2597 int rxcycles; 2598#endif /* DEVICE_POLLING / 2599}; 2600* 2601#define BGE_LOCK_INIT(_sc, _name) \ 2602 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2603#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2604#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2605#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2606#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)	410 411/* 412 * High priority mailbox registers 413 * Each mailbox is 64-bits wide, though we only use the 414 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 415 * first. The NIC will load the mailbox after the lower 32 bit word 416 * has been updated. 417 / 418#define BGE_MBX_IRQ0_HI 0x0200 419#define BGE_MBX_IRQ0_LO 0x0204 420#define BGE_MBX_IRQ1_HI 0x0208 421#define BGE_MBX_IRQ1_LO 0x020C 422#define BGE_MBX_IRQ2_HI 0x0210 423#define BGE_MBX_IRQ2_LO 0x0214 424#define BGE_MBX_IRQ3_HI 0x0218 425#define BGE_MBX_IRQ3_LO 0x021C 426#define BGE_MBX_GEN0_HI 0x0220 427#define BGE_MBX_GEN0_LO 0x0224 428#define BGE_MBX_GEN1_HI 0x0228 429#define BGE_MBX_GEN1_LO 0x022C 430#define BGE_MBX_GEN2_HI 0x0230 431#define BGE_MBX_GEN2_LO 0x0234 432#define BGE_MBX_GEN3_HI 0x0228 433#define BGE_MBX_GEN3_LO 0x022C 434#define BGE_MBX_GEN4_HI 0x0240 435#define BGE_MBX_GEN4_LO 0x0244 436#define BGE_MBX_GEN5_HI 0x0248 437#define BGE_MBX_GEN5_LO 0x024C 438#define BGE_MBX_GEN6_HI 0x0250 439#define BGE_MBX_GEN6_LO 0x0254 440#define BGE_MBX_GEN7_HI 0x0258 441#define BGE_MBX_GEN7_LO 0x025C 442#define BGE_MBX_RELOAD_STATS_HI 0x0260 443#define BGE_MBX_RELOAD_STATS_LO 0x0264 444#define BGE_MBX_RX_STD_PROD_HI 0x0268 445#define BGE_MBX_RX_STD_PROD_LO 0x026C 446#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 447#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 448#define BGE_MBX_RX_MINI_PROD_HI 0x0278 449#define BGE_MBX_RX_MINI_PROD_LO 0x027C 450#define BGE_MBX_RX_CONS0_HI 0x0280 451#define BGE_MBX_RX_CONS0_LO 0x0284 452#define BGE_MBX_RX_CONS1_HI 0x0288 453#define BGE_MBX_RX_CONS1_LO 0x028C 454#define BGE_MBX_RX_CONS2_HI 0x0290 455#define BGE_MBX_RX_CONS2_LO 0x0294 456#define BGE_MBX_RX_CONS3_HI 0x0298 457#define BGE_MBX_RX_CONS3_LO 0x029C 458#define BGE_MBX_RX_CONS4_HI 0x02A0 459#define BGE_MBX_RX_CONS4_LO 0x02A4 460#define BGE_MBX_RX_CONS5_HI 0x02A8 461#define BGE_MBX_RX_CONS5_LO 0x02AC 462#define BGE_MBX_RX_CONS6_HI 0x02B0 463#define BGE_MBX_RX_CONS6_LO 0x02B4 464#define BGE_MBX_RX_CONS7_HI 0x02B8 465#define BGE_MBX_RX_CONS7_LO 0x02BC 466#define BGE_MBX_RX_CONS8_HI 0x02C0 467#define BGE_MBX_RX_CONS8_LO 0x02C4 468#define BGE_MBX_RX_CONS9_HI 0x02C8 469#define BGE_MBX_RX_CONS9_LO 0x02CC 470#define BGE_MBX_RX_CONS10_HI 0x02D0 471#define BGE_MBX_RX_CONS10_LO 0x02D4 472#define BGE_MBX_RX_CONS11_HI 0x02D8 473#define BGE_MBX_RX_CONS11_LO 0x02DC 474#define BGE_MBX_RX_CONS12_HI 0x02E0 475#define BGE_MBX_RX_CONS12_LO 0x02E4 476#define BGE_MBX_RX_CONS13_HI 0x02E8 477#define BGE_MBX_RX_CONS13_LO 0x02EC 478#define BGE_MBX_RX_CONS14_HI 0x02F0 479#define BGE_MBX_RX_CONS14_LO 0x02F4 480#define BGE_MBX_RX_CONS15_HI 0x02F8 481#define BGE_MBX_RX_CONS15_LO 0x02FC 482#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 483#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 484#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 485#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 486#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 487#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 488#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 489#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 490#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 491#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 492#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 493#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 494#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 495#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 496#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 497#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 498#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 499#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 500#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 501#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 502#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 503#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 504#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 505#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 506#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 507#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 508#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 509#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 510#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 511#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 512#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 513#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 514#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 515#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 516#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 517#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 518#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 519#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 520#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 521#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 522#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 523#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 524#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 525#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 526#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 527#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 528#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 529#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 530#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 531#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 532#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 533#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 534#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 535#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 536#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 537#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 538#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 539#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 540#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 541#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 542#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 543#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 544#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 545#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 546* 547#define BGE_TX_RINGS_MAX 4 548#define BGE_TX_RINGS_EXTSSRAM_MAX 16 549#define BGE_RX_RINGS_MAX 16 550 551/* Ethernet MAC control registers / 552#define BGE_MAC_MODE 0x0400 553#define BGE_MAC_STS 0x0404 554#define BGE_MAC_EVT_ENB 0x0408 555#define BGE_MAC_LED_CTL 0x040C 556#define BGE_MAC_ADDR1_LO 0x0410 557#define BGE_MAC_ADDR1_HI 0x0414 558#define BGE_MAC_ADDR2_LO 0x0418 559#define BGE_MAC_ADDR2_HI 0x041C 560#define BGE_MAC_ADDR3_LO 0x0420 561#define BGE_MAC_ADDR3_HI 0x0424 562#define BGE_MAC_ADDR4_LO 0x0428 563#define BGE_MAC_ADDR4_HI 0x042C 564#define BGE_WOL_PATPTR 0x0430 565#define BGE_WOL_PATCFG 0x0434 566#define BGE_TX_RANDOM_BACKOFF 0x0438 567#define BGE_RX_MTU 0x043C 568#define BGE_GBIT_PCS_TEST 0x0440 569#define BGE_TX_TBI_AUTONEG 0x0444 570#define BGE_RX_TBI_AUTONEG 0x0448 571#define BGE_MI_COMM 0x044C 572#define BGE_MI_STS 0x0450 573#define BGE_MI_MODE 0x0454 574#define BGE_AUTOPOLL_STS 0x0458 575#define BGE_TX_MODE 0x045C 576#define BGE_TX_STS 0x0460 577#define BGE_TX_LENGTHS 0x0464 578#define BGE_RX_MODE 0x0468 579#define BGE_RX_STS 0x046C 580#define BGE_MAR0 0x0470 581#define BGE_MAR1 0x0474 582#define BGE_MAR2 0x0478 583#define BGE_MAR3 0x047C 584#define BGE_RX_BD_RULES_CTL0 0x0480 585#define BGE_RX_BD_RULES_MASKVAL0 0x0484 586#define BGE_RX_BD_RULES_CTL1 0x0488 587#define BGE_RX_BD_RULES_MASKVAL1 0x048C 588#define BGE_RX_BD_RULES_CTL2 0x0490 589#define BGE_RX_BD_RULES_MASKVAL2 0x0494 590#define BGE_RX_BD_RULES_CTL3 0x0498 591#define BGE_RX_BD_RULES_MASKVAL3 0x049C 592#define BGE_RX_BD_RULES_CTL4 0x04A0 593#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 594#define BGE_RX_BD_RULES_CTL5 0x04A8 595#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 596#define BGE_RX_BD_RULES_CTL6 0x04B0 597#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 598#define BGE_RX_BD_RULES_CTL7 0x04B8 599#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 600#define BGE_RX_BD_RULES_CTL8 0x04C0 601#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 602#define BGE_RX_BD_RULES_CTL9 0x04C8 603#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 604#define BGE_RX_BD_RULES_CTL10 0x04D0 605#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 606#define BGE_RX_BD_RULES_CTL11 0x04D8 607#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 608#define BGE_RX_BD_RULES_CTL12 0x04E0 609#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 610#define BGE_RX_BD_RULES_CTL13 0x04E8 611#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 612#define BGE_RX_BD_RULES_CTL14 0x04F0 613#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 614#define BGE_RX_BD_RULES_CTL15 0x04F8 615#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 616#define BGE_RX_RULES_CFG 0x0500 617#define BGE_SERDES_CFG 0x0590 618#define BGE_SERDES_STS 0x0594 619#define BGE_SGDIG_CFG 0x05B0 620#define BGE_SGDIG_STS 0x05B4 621#define BGE_MAC_STATS 0x0800 622* 623/* Ethernet MAC Mode register / 624#define BGE_MACMODE_RESET 0x00000001 625#define BGE_MACMODE_HALF_DUPLEX 0x00000002 626#define BGE_MACMODE_PORTMODE 0x0000000C 627#define BGE_MACMODE_LOOPBACK 0x00000010 628#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 629#define BGE_MACMODE_TX_BURST_ENB 0x00000100 630#define BGE_MACMODE_MAX_DEFER 0x00000200 631#define BGE_MACMODE_LINK_POLARITY 0x00000400 632#define BGE_MACMODE_RX_STATS_ENB 0x00000800 633#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 634#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 635#define BGE_MACMODE_TX_STATS_ENB 0x00004000 636#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 637#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 638#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 639#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 640#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 641#define BGE_MACMODE_MIP_ENB 0x00100000 642#define BGE_MACMODE_TXDMA_ENB 0x00200000 643#define BGE_MACMODE_RXDMA_ENB 0x00400000 644#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 645* 646#define BGE_PORTMODE_NONE 0x00000000 647#define BGE_PORTMODE_MII 0x00000004 648#define BGE_PORTMODE_GMII 0x00000008 649#define BGE_PORTMODE_TBI 0x0000000C 650 651/* MAC Status register / 652#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 653#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 654#define BGE_MACSTAT_RX_CFG 0x00000004 655#define BGE_MACSTAT_CFG_CHANGED 0x00000008 656#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 657#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 658#define BGE_MACSTAT_LINK_CHANGED 0x00001000 659#define BGE_MACSTAT_MI_COMPLETE 0x00400000 660#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 661#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 662#define BGE_MACSTAT_ODI_ERROR 0x02000000 663#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 664#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 665* 666/* MAC Event Enable Register / 667#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 668#define BGE_EVTENB_LINK_CHANGED 0x00001000 669#define BGE_EVTENB_MI_COMPLETE 0x00400000 670#define BGE_EVTENB_MI_INTERRUPT 0x00800000 671#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 672#define BGE_EVTENB_ODI_ERROR 0x02000000 673#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 674#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 675* 676/* LED Control Register / 677#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 678#define BGE_LEDCTL_1000MBPS_LED 0x00000002 679#define BGE_LEDCTL_100MBPS_LED 0x00000004 680#define BGE_LEDCTL_10MBPS_LED 0x00000008 681#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 682#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 683#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 684#define BGE_LEDCTL_1000MBPS_STS 0x00000080 685#define BGE_LEDCTL_100MBPS_STS 0x00000100 686#define BGE_LEDCTL_10MBPS_STS 0x00000200 687#define BGE_LEDCTL_TRADLED_STS 0x00000400 688#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 689#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 690* 691/* TX backoff seed register / 692#define BGE_TX_BACKOFF_SEED_MASK 0x3F 693* 694/* Autopoll status register / 695#define BGE_AUTOPOLLSTS_ERROR 0x00000001 696* 697/* Transmit MAC mode register / 698#define BGE_TXMODE_RESET 0x00000001 699#define BGE_TXMODE_ENABLE 0x00000002 700#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 701#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 702#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 703* 704/* Transmit MAC status register / 705#define BGE_TXSTAT_RX_XOFFED 0x00000001 706#define BGE_TXSTAT_SENT_XOFF 0x00000002 707#define BGE_TXSTAT_SENT_XON 0x00000004 708#define BGE_TXSTAT_LINK_UP 0x00000008 709#define BGE_TXSTAT_ODI_UFLOW 0x00000010 710#define BGE_TXSTAT_ODI_OFLOW 0x00000020 711* 712/* Transmit MAC lengths register / 713#define BGE_TXLEN_SLOTTIME 0x000000FF 714#define BGE_TXLEN_IPG 0x00000F00 715#define BGE_TXLEN_CRS 0x00003000 716* 717/* Receive MAC mode register / 718#define BGE_RXMODE_RESET 0x00000001 719#define BGE_RXMODE_ENABLE 0x00000002 720#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 721#define BGE_RXMODE_RX_GIANTS 0x00000020 722#define BGE_RXMODE_RX_RUNTS 0x00000040 723#define BGE_RXMODE_8022_LENCHECK 0x00000080 724#define BGE_RXMODE_RX_PROMISC 0x00000100 725#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 726#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 727* 728/* Receive MAC status register / 729#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 730#define BGE_RXSTAT_RCVD_XOFF 0x00000002 731#define BGE_RXSTAT_RCVD_XON 0x00000004 732* 733/* Receive Rules Control register / 734#define BGE_RXRULECTL_OFFSET 0x000000FF 735#define BGE_RXRULECTL_CLASS 0x00001F00 736#define BGE_RXRULECTL_HDRTYPE 0x0000E000 737#define BGE_RXRULECTL_COMPARE_OP 0x00030000 738#define BGE_RXRULECTL_MAP 0x01000000 739#define BGE_RXRULECTL_DISCARD 0x02000000 740#define BGE_RXRULECTL_MASK 0x04000000 741#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 742#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 743#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 744#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 745* 746/* Receive Rules Mask register / 747#define BGE_RXRULEMASK_VALUE 0x0000FFFF 748#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 749* 750/* SERDES configuration register / 751#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 752#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 753#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 754#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 755#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 756#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 757#define BGE_SERDESCFG_TXMODE 0x00001000 758#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 759#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 760#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 761#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 762#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 763#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 764#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 765#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 766#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 767* 768/* SERDES status register / 769#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 770#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 771* 772/* SGDIG config (not documented) / 773#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 774#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 775#define BGE_SGDIGCFG_SEND 0x40000000 776#define BGE_SGDIGCFG_AUTO 0x80000000 777* 778/* SGDIG status (not documented) / 779#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 780#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 781#define BGE_SGDIGSTS_DONE 0x00000002 782* 783 784/* MI communication register / 785#define BGE_MICOMM_DATA 0x0000FFFF 786#define BGE_MICOMM_REG 0x001F0000 787#define BGE_MICOMM_PHY 0x03E00000 788#define BGE_MICOMM_CMD 0x0C000000 789#define BGE_MICOMM_READFAIL 0x10000000 790#define BGE_MICOMM_BUSY 0x20000000 791* 792#define BGE_MIREG(x) ((x & 0x1F) << 16) 793#define BGE_MIPHY(x) ((x & 0x1F) << 21) 794#define BGE_MICMD_WRITE 0x04000000 795#define BGE_MICMD_READ 0x08000000 796 797/* MI status register / 798#define BGE_MISTS_LINK 0x00000001 799#define BGE_MISTS_10MBPS 0x00000002 800* 801#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 802#define BGE_MIMODE_AUTOPOLL 0x00000010 803#define BGE_MIMODE_CLKCNT 0x001F0000 804 805 806/* 807 * Send data initiator control registers. 808 / 809#define BGE_SDI_MODE 0x0C00 810#define BGE_SDI_STATUS 0x0C04 811#define BGE_SDI_STATS_CTL 0x0C08 812#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 813#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 814#define BGE_LOCSTATS_COS0 0x0C80 815#define BGE_LOCSTATS_COS1 0x0C84 816#define BGE_LOCSTATS_COS2 0x0C88 817#define BGE_LOCSTATS_COS3 0x0C8C 818#define BGE_LOCSTATS_COS4 0x0C90 819#define BGE_LOCSTATS_COS5 0x0C84 820#define BGE_LOCSTATS_COS6 0x0C98 821#define BGE_LOCSTATS_COS7 0x0C9C 822#define BGE_LOCSTATS_COS8 0x0CA0 823#define BGE_LOCSTATS_COS9 0x0CA4 824#define BGE_LOCSTATS_COS10 0x0CA8 825#define BGE_LOCSTATS_COS11 0x0CAC 826#define BGE_LOCSTATS_COS12 0x0CB0 827#define BGE_LOCSTATS_COS13 0x0CB4 828#define BGE_LOCSTATS_COS14 0x0CB8 829#define BGE_LOCSTATS_COS15 0x0CBC 830#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 831#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 832#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 833#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 834#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 835#define BGE_LOCSTATS_IRQS 0x0CD4 836#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 837#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 838* 839/* Send Data Initiator mode register / 840#define BGE_SDIMODE_RESET 0x00000001 841#define BGE_SDIMODE_ENABLE 0x00000002 842#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 843* 844/* Send Data Initiator stats register / 845#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 846* 847/* Send Data Initiator stats control register / 848#define BGE_SDISTATSCTL_ENABLE 0x00000001 849#define BGE_SDISTATSCTL_FASTER 0x00000002 850#define BGE_SDISTATSCTL_CLEAR 0x00000004 851#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 852#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 853* 854/* 855 * Send Data Completion Control registers 856 / 857#define BGE_SDC_MODE 0x1000 858#define BGE_SDC_STATUS 0x1004 859* 860/* Send Data completion mode register / 861#define BGE_SDCMODE_RESET 0x00000001 862#define BGE_SDCMODE_ENABLE 0x00000002 863#define BGE_SDCMODE_ATTN 0x00000004 864* 865/* Send Data completion status register / 866#define BGE_SDCSTAT_ATTN 0x00000004 867* 868/* 869 * Send BD Ring Selector Control registers 870 / 871#define BGE_SRS_MODE 0x1400 872#define BGE_SRS_STATUS 0x1404 873#define BGE_SRS_HWDIAG 0x1408 874#define BGE_SRS_LOC_NIC_CONS0 0x1440 875#define BGE_SRS_LOC_NIC_CONS1 0x1444 876#define BGE_SRS_LOC_NIC_CONS2 0x1448 877#define BGE_SRS_LOC_NIC_CONS3 0x144C 878#define BGE_SRS_LOC_NIC_CONS4 0x1450 879#define BGE_SRS_LOC_NIC_CONS5 0x1454 880#define BGE_SRS_LOC_NIC_CONS6 0x1458 881#define BGE_SRS_LOC_NIC_CONS7 0x145C 882#define BGE_SRS_LOC_NIC_CONS8 0x1460 883#define BGE_SRS_LOC_NIC_CONS9 0x1464 884#define BGE_SRS_LOC_NIC_CONS10 0x1468 885#define BGE_SRS_LOC_NIC_CONS11 0x146C 886#define BGE_SRS_LOC_NIC_CONS12 0x1470 887#define BGE_SRS_LOC_NIC_CONS13 0x1474 888#define BGE_SRS_LOC_NIC_CONS14 0x1478 889#define BGE_SRS_LOC_NIC_CONS15 0x147C 890* 891/* Send BD Ring Selector Mode register / 892#define BGE_SRSMODE_RESET 0x00000001 893#define BGE_SRSMODE_ENABLE 0x00000002 894#define BGE_SRSMODE_ATTN 0x00000004 895* 896/* Send BD Ring Selector Status register / 897#define BGE_SRSSTAT_ERROR 0x00000004 898* 899/* Send BD Ring Selector HW Diagnostics register / 900#define BGE_SRSHWDIAG_STATE 0x0000000F 901#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 902#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 903#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 904* 905/* 906 * Send BD Initiator Selector Control registers 907 / 908#define BGE_SBDI_MODE 0x1800 909#define BGE_SBDI_STATUS 0x1804 910#define BGE_SBDI_LOC_NIC_PROD0 0x1808 911#define BGE_SBDI_LOC_NIC_PROD1 0x180C 912#define BGE_SBDI_LOC_NIC_PROD2 0x1810 913#define BGE_SBDI_LOC_NIC_PROD3 0x1814 914#define BGE_SBDI_LOC_NIC_PROD4 0x1818 915#define BGE_SBDI_LOC_NIC_PROD5 0x181C 916#define BGE_SBDI_LOC_NIC_PROD6 0x1820 917#define BGE_SBDI_LOC_NIC_PROD7 0x1824 918#define BGE_SBDI_LOC_NIC_PROD8 0x1828 919#define BGE_SBDI_LOC_NIC_PROD9 0x182C 920#define BGE_SBDI_LOC_NIC_PROD10 0x1830 921#define BGE_SBDI_LOC_NIC_PROD11 0x1834 922#define BGE_SBDI_LOC_NIC_PROD12 0x1838 923#define BGE_SBDI_LOC_NIC_PROD13 0x183C 924#define BGE_SBDI_LOC_NIC_PROD14 0x1840 925#define BGE_SBDI_LOC_NIC_PROD15 0x1844 926* 927/* Send BD Initiator Mode register / 928#define BGE_SBDIMODE_RESET 0x00000001 929#define BGE_SBDIMODE_ENABLE 0x00000002 930#define BGE_SBDIMODE_ATTN 0x00000004 931* 932/* Send BD Initiator Status register / 933#define BGE_SBDISTAT_ERROR 0x00000004 934* 935/* 936 * Send BD Completion Control registers 937 / 938#define BGE_SBDC_MODE 0x1C00 939#define BGE_SBDC_STATUS 0x1C04 940* 941/* Send BD Completion Control Mode register / 942#define BGE_SBDCMODE_RESET 0x00000001 943#define BGE_SBDCMODE_ENABLE 0x00000002 944#define BGE_SBDCMODE_ATTN 0x00000004 945* 946/* Send BD Completion Control Status register / 947#define BGE_SBDCSTAT_ATTN 0x00000004 948* 949/* 950 * Receive List Placement Control registers 951 / 952#define BGE_RXLP_MODE 0x2000 953#define BGE_RXLP_STATUS 0x2004 954#define BGE_RXLP_SEL_LIST_LOCK 0x2008 955#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 956#define BGE_RXLP_CFG 0x2010 957#define BGE_RXLP_STATS_CTL 0x2014 958#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 959#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 960#define BGE_RXLP_HEAD0 0x2100 961#define BGE_RXLP_TAIL0 0x2104 962#define BGE_RXLP_COUNT0 0x2108 963#define BGE_RXLP_HEAD1 0x2110 964#define BGE_RXLP_TAIL1 0x2114 965#define BGE_RXLP_COUNT1 0x2118 966#define BGE_RXLP_HEAD2 0x2120 967#define BGE_RXLP_TAIL2 0x2124 968#define BGE_RXLP_COUNT2 0x2128 969#define BGE_RXLP_HEAD3 0x2130 970#define BGE_RXLP_TAIL3 0x2134 971#define BGE_RXLP_COUNT3 0x2138 972#define BGE_RXLP_HEAD4 0x2140 973#define BGE_RXLP_TAIL4 0x2144 974#define BGE_RXLP_COUNT4 0x2148 975#define BGE_RXLP_HEAD5 0x2150 976#define BGE_RXLP_TAIL5 0x2154 977#define BGE_RXLP_COUNT5 0x2158 978#define BGE_RXLP_HEAD6 0x2160 979#define BGE_RXLP_TAIL6 0x2164 980#define BGE_RXLP_COUNT6 0x2168 981#define BGE_RXLP_HEAD7 0x2170 982#define BGE_RXLP_TAIL7 0x2174 983#define BGE_RXLP_COUNT7 0x2178 984#define BGE_RXLP_HEAD8 0x2180 985#define BGE_RXLP_TAIL8 0x2184 986#define BGE_RXLP_COUNT8 0x2188 987#define BGE_RXLP_HEAD9 0x2190 988#define BGE_RXLP_TAIL9 0x2194 989#define BGE_RXLP_COUNT9 0x2198 990#define BGE_RXLP_HEAD10 0x21A0 991#define BGE_RXLP_TAIL10 0x21A4 992#define BGE_RXLP_COUNT10 0x21A8 993#define BGE_RXLP_HEAD11 0x21B0 994#define BGE_RXLP_TAIL11 0x21B4 995#define BGE_RXLP_COUNT11 0x21B8 996#define BGE_RXLP_HEAD12 0x21C0 997#define BGE_RXLP_TAIL12 0x21C4 998#define BGE_RXLP_COUNT12 0x21C8 999#define BGE_RXLP_HEAD13 0x21D0 1000#define BGE_RXLP_TAIL13 0x21D4 1001#define BGE_RXLP_COUNT13 0x21D8 1002#define BGE_RXLP_HEAD14 0x21E0 1003#define BGE_RXLP_TAIL14 0x21E4 1004#define BGE_RXLP_COUNT14 0x21E8 1005#define BGE_RXLP_HEAD15 0x21F0 1006#define BGE_RXLP_TAIL15 0x21F4 1007#define BGE_RXLP_COUNT15 0x21F8 1008#define BGE_RXLP_LOCSTAT_COS0 0x2200 1009#define BGE_RXLP_LOCSTAT_COS1 0x2204 1010#define BGE_RXLP_LOCSTAT_COS2 0x2208 1011#define BGE_RXLP_LOCSTAT_COS3 0x220C 1012#define BGE_RXLP_LOCSTAT_COS4 0x2210 1013#define BGE_RXLP_LOCSTAT_COS5 0x2214 1014#define BGE_RXLP_LOCSTAT_COS6 0x2218 1015#define BGE_RXLP_LOCSTAT_COS7 0x221C 1016#define BGE_RXLP_LOCSTAT_COS8 0x2220 1017#define BGE_RXLP_LOCSTAT_COS9 0x2224 1018#define BGE_RXLP_LOCSTAT_COS10 0x2228 1019#define BGE_RXLP_LOCSTAT_COS11 0x222C 1020#define BGE_RXLP_LOCSTAT_COS12 0x2230 1021#define BGE_RXLP_LOCSTAT_COS13 0x2234 1022#define BGE_RXLP_LOCSTAT_COS14 0x2238 1023#define BGE_RXLP_LOCSTAT_COS15 0x223C 1024#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 1025#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 1026#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 1027#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 1028#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 1029#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 1030#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 1031* 1032 1033/* Receive List Placement mode register / 1034#define BGE_RXLPMODE_RESET 0x00000001 1035#define BGE_RXLPMODE_ENABLE 0x00000002 1036#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 1037#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 1038#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 1039* 1040/* Receive List Placement Status register / 1041#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 1042#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1043#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1044* 1045/* 1046 * Receive Data and Receive BD Initiator Control Registers 1047 / 1048#define BGE_RDBDI_MODE 0x2400 1049#define BGE_RDBDI_STATUS 0x2404 1050#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1051#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1052#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1053#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1054#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1055#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1056#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1057#define BGE_RX_STD_RCB_NICADDR 0x245C 1058#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1059#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1060#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1061#define BGE_RX_MINI_RCB_NICADDR 0x246C 1062#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1063#define BGE_RDBDI_STD_RX_CONS 0x2474 1064#define BGE_RDBDI_MINI_RX_CONS 0x2478 1065#define BGE_RDBDI_RETURN_PROD0 0x2480 1066#define BGE_RDBDI_RETURN_PROD1 0x2484 1067#define BGE_RDBDI_RETURN_PROD2 0x2488 1068#define BGE_RDBDI_RETURN_PROD3 0x248C 1069#define BGE_RDBDI_RETURN_PROD4 0x2490 1070#define BGE_RDBDI_RETURN_PROD5 0x2494 1071#define BGE_RDBDI_RETURN_PROD6 0x2498 1072#define BGE_RDBDI_RETURN_PROD7 0x249C 1073#define BGE_RDBDI_RETURN_PROD8 0x24A0 1074#define BGE_RDBDI_RETURN_PROD9 0x24A4 1075#define BGE_RDBDI_RETURN_PROD10 0x24A8 1076#define BGE_RDBDI_RETURN_PROD11 0x24AC 1077#define BGE_RDBDI_RETURN_PROD12 0x24B0 1078#define BGE_RDBDI_RETURN_PROD13 0x24B4 1079#define BGE_RDBDI_RETURN_PROD14 0x24B8 1080#define BGE_RDBDI_RETURN_PROD15 0x24BC 1081#define BGE_RDBDI_HWDIAG 0x24C0 1082* 1083 1084/* Receive Data and Receive BD Initiator Mode register / 1085#define BGE_RDBDIMODE_RESET 0x00000001 1086#define BGE_RDBDIMODE_ENABLE 0x00000002 1087#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1088#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1089#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1090* 1091/* Receive Data and Receive BD Initiator Status register / 1092#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1093#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1094#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1095* 1096 1097/* 1098 * Receive Data Completion Control registers 1099 / 1100#define BGE_RDC_MODE 0x2800 1101* 1102/* Receive Data Completion Mode register / 1103#define BGE_RDCMODE_RESET 0x00000001 1104#define BGE_RDCMODE_ENABLE 0x00000002 1105#define BGE_RDCMODE_ATTN 0x00000004 1106* 1107/* 1108 * Receive BD Initiator Control registers 1109 / 1110#define BGE_RBDI_MODE 0x2C00 1111#define BGE_RBDI_STATUS 0x2C04 1112#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1113#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1114#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1115#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1116#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1117#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1118* 1119/* Receive BD Initiator Mode register / 1120#define BGE_RBDIMODE_RESET 0x00000001 1121#define BGE_RBDIMODE_ENABLE 0x00000002 1122#define BGE_RBDIMODE_ATTN 0x00000004 1123* 1124/* Receive BD Initiator Status register / 1125#define BGE_RBDISTAT_ATTN 0x00000004 1126* 1127/* 1128 * Receive BD Completion Control registers 1129 / 1130#define BGE_RBDC_MODE 0x3000 1131#define BGE_RBDC_STATUS 0x3004 1132#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1133#define BGE_RBDC_STD_BD_PROD 0x300C 1134#define BGE_RBDC_MINI_BD_PROD 0x3010 1135* 1136/* Receive BD completion mode register / 1137#define BGE_RBDCMODE_RESET 0x00000001 1138#define BGE_RBDCMODE_ENABLE 0x00000002 1139#define BGE_RBDCMODE_ATTN 0x00000004 1140* 1141/* Receive BD completion status register / 1142#define BGE_RBDCSTAT_ERROR 0x00000004 1143* 1144/* 1145 * Receive List Selector Control registers 1146 / 1147#define BGE_RXLS_MODE 0x3400 1148#define BGE_RXLS_STATUS 0x3404 1149* 1150/* Receive List Selector Mode register / 1151#define BGE_RXLSMODE_RESET 0x00000001 1152#define BGE_RXLSMODE_ENABLE 0x00000002 1153#define BGE_RXLSMODE_ATTN 0x00000004 1154* 1155/* Receive List Selector Status register / 1156#define BGE_RXLSSTAT_ERROR 0x00000004 1157* 1158/* 1159 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1160 / 1161#define BGE_MBCF_MODE 0x3800 1162#define BGE_MBCF_STATUS 0x3804 1163* 1164/* Mbuf Cluster Free mode register / 1165#define BGE_MBCFMODE_RESET 0x00000001 1166#define BGE_MBCFMODE_ENABLE 0x00000002 1167#define BGE_MBCFMODE_ATTN 0x00000004 1168* 1169/* Mbuf Cluster Free status register / 1170#define BGE_MBCFSTAT_ERROR 0x00000004 1171* 1172/* 1173 * Host Coalescing Control registers 1174 / 1175#define BGE_HCC_MODE 0x3C00 1176#define BGE_HCC_STATUS 0x3C04 1177#define BGE_HCC_RX_COAL_TICKS 0x3C08 1178#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1179#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1180#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1181#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1182#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1183#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1184#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1185#define BGE_HCC_STATS_TICKS 0x3C28 1186#define BGE_HCC_STATS_ADDR_HI 0x3C30 1187#define BGE_HCC_STATS_ADDR_LO 0x3C34 1188#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1189#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1190#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1191#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1192#define BGE_FLOW_ATTN 0x3C48 1193#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1194#define BGE_HCC_STD_BD_CONS 0x3C54 1195#define BGE_HCC_MINI_BD_CONS 0x3C58 1196#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1197#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1198#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1199#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1200#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1201#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1202#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1203#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1204#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1205#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1206#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1207#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1208#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1209#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1210#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1211#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1212#define BGE_HCC_TX_BD_CONS0 0x3CC0 1213#define BGE_HCC_TX_BD_CONS1 0x3CC4 1214#define BGE_HCC_TX_BD_CONS2 0x3CC8 1215#define BGE_HCC_TX_BD_CONS3 0x3CCC 1216#define BGE_HCC_TX_BD_CONS4 0x3CD0 1217#define BGE_HCC_TX_BD_CONS5 0x3CD4 1218#define BGE_HCC_TX_BD_CONS6 0x3CD8 1219#define BGE_HCC_TX_BD_CONS7 0x3CDC 1220#define BGE_HCC_TX_BD_CONS8 0x3CE0 1221#define BGE_HCC_TX_BD_CONS9 0x3CE4 1222#define BGE_HCC_TX_BD_CONS10 0x3CE8 1223#define BGE_HCC_TX_BD_CONS11 0x3CEC 1224#define BGE_HCC_TX_BD_CONS12 0x3CF0 1225#define BGE_HCC_TX_BD_CONS13 0x3CF4 1226#define BGE_HCC_TX_BD_CONS14 0x3CF8 1227#define BGE_HCC_TX_BD_CONS15 0x3CFC 1228* 1229 1230/* Host coalescing mode register / 1231#define BGE_HCCMODE_RESET 0x00000001 1232#define BGE_HCCMODE_ENABLE 0x00000002 1233#define BGE_HCCMODE_ATTN 0x00000004 1234#define BGE_HCCMODE_COAL_NOW 0x00000008 1235#define BGE_HCCMODE_MSI_BITS 0x00000070 1236#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1237* 1238#define BGE_STATBLKSZ_FULL 0x00000000 1239#define BGE_STATBLKSZ_64BYTE 0x00000080 1240#define BGE_STATBLKSZ_32BYTE 0x00000100 1241 1242/* Host coalescing status register / 1243#define BGE_HCCSTAT_ERROR 0x00000004 1244* 1245/* Flow attention register / 1246#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1247#define BGE_FLOWATTN_MEMARB 0x00000080 1248#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1249#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1250#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1251#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1252#define BGE_FLOWATTN_RDBDI 0x00080000 1253#define BGE_FLOWATTN_RXLS 0x00100000 1254#define BGE_FLOWATTN_RXLP 0x00200000 1255#define BGE_FLOWATTN_RBDC 0x00400000 1256#define BGE_FLOWATTN_RBDI 0x00800000 1257#define BGE_FLOWATTN_SDC 0x08000000 1258#define BGE_FLOWATTN_SDI 0x10000000 1259#define BGE_FLOWATTN_SRS 0x20000000 1260#define BGE_FLOWATTN_SBDC 0x40000000 1261#define BGE_FLOWATTN_SBDI 0x80000000 1262* 1263/* 1264 * Memory arbiter registers 1265 / 1266#define BGE_MARB_MODE 0x4000 1267#define BGE_MARB_STATUS 0x4004 1268#define BGE_MARB_TRAPADDR_HI 0x4008 1269#define BGE_MARB_TRAPADDR_LO 0x400C 1270* 1271/* Memory arbiter mode register / 1272#define BGE_MARBMODE_RESET 0x00000001 1273#define BGE_MARBMODE_ENABLE 0x00000002 1274#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1275#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1276#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1277#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1278#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1279#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1280#define BGE_MARBMODE_PCI_TRAP 0x00000100 1281#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1282#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1283#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1284#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1285#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1286#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1287#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1288#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1289#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1290#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1291#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1292#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1293#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1294#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1295#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1296#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1297#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1298* 1299/* Memory arbiter status register / 1300#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1301#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1302#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1303#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1304#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1305#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1306#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1307#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1308#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1309#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1310#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1311#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1312#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1313#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1314#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1315#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1316#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1317#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1318#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1319#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1320#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1321#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1322#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1323#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1324* 1325/* 1326 * Buffer manager control registers 1327 / 1328#define BGE_BMAN_MODE 0x4400 1329#define BGE_BMAN_STATUS 0x4404 1330#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1331#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1332#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1333#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1334#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1335#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1336#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1337#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1338#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1339#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1340#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1341#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1342#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1343#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1344#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1345#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1346#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1347#define BGE_BMAN_HWDIAG_1 0x444C 1348#define BGE_BMAN_HWDIAG_2 0x4450 1349#define BGE_BMAN_HWDIAG_3 0x4454 1350* 1351/* Buffer manager mode register / 1352#define BGE_BMANMODE_RESET 0x00000001 1353#define BGE_BMANMODE_ENABLE 0x00000002 1354#define BGE_BMANMODE_ATTN 0x00000004 1355#define BGE_BMANMODE_TESTMODE 0x00000008 1356#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1357* 1358/* Buffer manager status register / 1359#define BGE_BMANSTAT_ERRO 0x00000004 1360#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1361* 1362 1363/* 1364 * Read DMA Control registers 1365 / 1366#define BGE_RDMA_MODE 0x4800 1367#define BGE_RDMA_STATUS 0x4804 1368* 1369/* Read DMA mode register / 1370#define BGE_RDMAMODE_RESET 0x00000001 1371#define BGE_RDMAMODE_ENABLE 0x00000002 1372#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1373#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1374#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1375#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1376#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1377#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1378#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1379#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1380#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1381#define BGE_RDMAMODE_FIFO_SIZE_128 0x00020000 1382#define BGE_RDMAMODE_FIFO_LONG_BURST 0x00030000 1383* 1384/* Read DMA status register / 1385#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1386#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1387#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1388#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1389#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1390#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1391#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1392#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1393* 1394/* 1395 * Write DMA control registers 1396 / 1397#define BGE_WDMA_MODE 0x4C00 1398#define BGE_WDMA_STATUS 0x4C04 1399* 1400/* Write DMA mode register / 1401#define BGE_WDMAMODE_RESET 0x00000001 1402#define BGE_WDMAMODE_ENABLE 0x00000002 1403#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1404#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1405#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1406#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1407#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1408#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1409#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1410#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1411#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1412* 1413/* Write DMA status register / 1414#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1415#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1416#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1417#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1418#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1419#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1420#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1421#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1422* 1423 1424/* 1425 * RX CPU registers 1426 / 1427#define BGE_RXCPU_MODE 0x5000 1428#define BGE_RXCPU_STATUS 0x5004 1429#define BGE_RXCPU_PC 0x501C 1430* 1431/* RX CPU mode register / 1432#define BGE_RXCPUMODE_RESET 0x00000001 1433#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1434#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1435#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1436#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1437#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1438#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1439#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1440#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1441#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1442#define BGE_RXCPUMODE_HALTCPU 0x00000400 1443#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1444#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1445#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1446* 1447/* RX CPU status register / 1448#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1449#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1450#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1451#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1452#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1453#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1454#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1455#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1456#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1457#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1458#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1459#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1460#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1461#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1462#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1463#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1464#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1465* 1466/* 1467 * V? CPU registers 1468 / 1469#define BGE_VCPU_STATUS 0x5100 1470#define BGE_VCPU_EXT_CTRL 0x6890 1471* 1472#define BGE_VCPU_STATUS_INIT_DONE 0x04000000 1473#define BGE_VCPU_STATUS_DRV_RESET 0x08000000 1474 1475#define BGE_VCPU_EXT_CTRL_HALT_CPU 0x00400000 1476#define BGE_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000 1477 1478/* 1479 * TX CPU registers 1480 / 1481#define BGE_TXCPU_MODE 0x5400 1482#define BGE_TXCPU_STATUS 0x5404 1483#define BGE_TXCPU_PC 0x541C 1484* 1485/* TX CPU mode register / 1486#define BGE_TXCPUMODE_RESET 0x00000001 1487#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1488#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1489#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1490#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1491#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1492#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1493#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1494#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1495#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1496#define BGE_TXCPUMODE_HALTCPU 0x00000400 1497#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1498#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1499* 1500/* TX CPU status register / 1501#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1502#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1503#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1504#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1505#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1506#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1507#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1508#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1509#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1510#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1511#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1512#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1513#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1514#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1515#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1516#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1517#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1518* 1519 1520/* 1521 * Low priority mailbox registers 1522 / 1523#define BGE_LPMBX_IRQ0_HI 0x5800 1524#define BGE_LPMBX_IRQ0_LO 0x5804 1525#define BGE_LPMBX_IRQ1_HI 0x5808 1526#define BGE_LPMBX_IRQ1_LO 0x580C 1527#define BGE_LPMBX_IRQ2_HI 0x5810 1528#define BGE_LPMBX_IRQ2_LO 0x5814 1529#define BGE_LPMBX_IRQ3_HI 0x5818 1530#define BGE_LPMBX_IRQ3_LO 0x581C 1531#define BGE_LPMBX_GEN0_HI 0x5820 1532#define BGE_LPMBX_GEN0_LO 0x5824 1533#define BGE_LPMBX_GEN1_HI 0x5828 1534#define BGE_LPMBX_GEN1_LO 0x582C 1535#define BGE_LPMBX_GEN2_HI 0x5830 1536#define BGE_LPMBX_GEN2_LO 0x5834 1537#define BGE_LPMBX_GEN3_HI 0x5828 1538#define BGE_LPMBX_GEN3_LO 0x582C 1539#define BGE_LPMBX_GEN4_HI 0x5840 1540#define BGE_LPMBX_GEN4_LO 0x5844 1541#define BGE_LPMBX_GEN5_HI 0x5848 1542#define BGE_LPMBX_GEN5_LO 0x584C 1543#define BGE_LPMBX_GEN6_HI 0x5850 1544#define BGE_LPMBX_GEN6_LO 0x5854 1545#define BGE_LPMBX_GEN7_HI 0x5858 1546#define BGE_LPMBX_GEN7_LO 0x585C 1547#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1548#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1549#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1550#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1551#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1552#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1553#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1554#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1555#define BGE_LPMBX_RX_CONS0_HI 0x5880 1556#define BGE_LPMBX_RX_CONS0_LO 0x5884 1557#define BGE_LPMBX_RX_CONS1_HI 0x5888 1558#define BGE_LPMBX_RX_CONS1_LO 0x588C 1559#define BGE_LPMBX_RX_CONS2_HI 0x5890 1560#define BGE_LPMBX_RX_CONS2_LO 0x5894 1561#define BGE_LPMBX_RX_CONS3_HI 0x5898 1562#define BGE_LPMBX_RX_CONS3_LO 0x589C 1563#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1564#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1565#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1566#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1567#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1568#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1569#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1570#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1571#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1572#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1573#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1574#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1575#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1576#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1577#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1578#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1579#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1580#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1581#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1582#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1583#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1584#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1585#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1586#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1587#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1588#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1589#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1590#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1591#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1592#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1593#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1594#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1595#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1596#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1597#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1598#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1599#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1600#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1601#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1602#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1603#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1604#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1605#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1606#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1607#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1608#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1609#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1610#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1611#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1612#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1613#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1614#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1615#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1616#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1617#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1618#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1619#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1620#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1621#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1622#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1623#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1624#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1625#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1626#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1627#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1628#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1629#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1630#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1631#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1632#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1633#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1634#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1635#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1636#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1637#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1638#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1639#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1640#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1641#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1642#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1643#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1644#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1645#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1646#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1647#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1648#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1649#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1650#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1651* 1652/* 1653 * Flow throw Queue reset register 1654 / 1655#define BGE_FTQ_RESET 0x5C00 1656* 1657#define BGE_FTQRESET_DMAREAD 0x00000002 1658#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1659#define BGE_FTQRESET_DMADONE 0x00000010 1660#define BGE_FTQRESET_SBDC 0x00000020 1661#define BGE_FTQRESET_SDI 0x00000040 1662#define BGE_FTQRESET_WDMA 0x00000080 1663#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1664#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1665#define BGE_FTQRESET_SDC 0x00000400 1666#define BGE_FTQRESET_HCC 0x00000800 1667#define BGE_FTQRESET_TXFIFO 0x00001000 1668#define BGE_FTQRESET_MBC 0x00002000 1669#define BGE_FTQRESET_RBDC 0x00004000 1670#define BGE_FTQRESET_RXLP 0x00008000 1671#define BGE_FTQRESET_RDBDI 0x00010000 1672#define BGE_FTQRESET_RDC 0x00020000 1673#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1674 1675/* 1676 * Message Signaled Interrupt registers 1677 / 1678#define BGE_MSI_MODE 0x6000 1679#define BGE_MSI_STATUS 0x6004 1680#define BGE_MSI_FIFOACCESS 0x6008 1681* 1682/* MSI mode register / 1683#define BGE_MSIMODE_RESET 0x00000001 1684#define BGE_MSIMODE_ENABLE 0x00000002 1685#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1686#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1687#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1688#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1689#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1690* 1691/* MSI status register / 1692#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1693#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1694#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1695#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1696#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1697* 1698 1699/* 1700 * DMA Completion registers 1701 / 1702#define BGE_DMAC_MODE 0x6400 1703* 1704/* DMA Completion mode register / 1705#define BGE_DMACMODE_RESET 0x00000001 1706#define BGE_DMACMODE_ENABLE 0x00000002 1707* 1708 1709/* 1710 * General control registers. 1711 / 1712#define BGE_MODE_CTL 0x6800 1713#define BGE_MISC_CFG 0x6804 1714#define BGE_MISC_LOCAL_CTL 0x6808 1715#define BGE_CPU_EVENT 0x6810 1716#define BGE_EE_ADDR 0x6838 1717#define BGE_EE_DATA 0x683C 1718#define BGE_EE_CTL 0x6840 1719#define BGE_MDI_CTL 0x6844 1720#define BGE_EE_DELAY 0x6848 1721#define BGE_FASTBOOT_PC 0x6894 1722* 1723/* 1724 * NVRAM Control registers 1725 / 1726#define BGE_NVRAM_CMD 0x7000 1727#define BGE_NVRAM_STAT 0x7004 1728#define BGE_NVRAM_WRDATA 0x7008 1729#define BGE_NVRAM_ADDR 0x700c 1730#define BGE_NVRAM_RDDATA 0x7010 1731#define BGE_NVRAM_CFG1 0x7014 1732#define BGE_NVRAM_CFG2 0x7018 1733#define BGE_NVRAM_CFG3 0x701c 1734#define BGE_NVRAM_SWARB 0x7020 1735#define BGE_NVRAM_ACCESS 0x7024 1736#define BGE_NVRAM_WRITE1 0x7028 1737* 1738#define BGE_NVRAMCMD_RESET 0x00000001 1739#define BGE_NVRAMCMD_DONE 0x00000008 1740#define BGE_NVRAMCMD_START 0x00000010 1741#define BGE_NVRAMCMD_WR 0x00000020 /* 1 = wr, 0 = rd / 1742#define BGE_NVRAMCMD_ERASE 0x00000040 1743#define BGE_NVRAMCMD_FIRST 0x00000080 1744#define BGE_NVRAMCMD_LAST 0x00000100 1745* 1746#define BGE_NVRAM_READCMD \ 1747 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1748 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE) 1749#define BGE_NVRAM_WRITECMD \ 1750 (BGE_NVRAMCMD_FIRST\|BGE_NVRAMCMD_LAST\| \ 1751 BGE_NVRAMCMD_START\|BGE_NVRAMCMD_DONE\|BGE_NVRAMCMD_WR) 1752 1753#define BGE_NVRAMSWARB_SET0 0x00000001 1754#define BGE_NVRAMSWARB_SET1 0x00000002 1755#define BGE_NVRAMSWARB_SET2 0x00000003 1756#define BGE_NVRAMSWARB_SET3 0x00000004 1757#define BGE_NVRAMSWARB_CLR0 0x00000010 1758#define BGE_NVRAMSWARB_CLR1 0x00000020 1759#define BGE_NVRAMSWARB_CLR2 0x00000040 1760#define BGE_NVRAMSWARB_CLR3 0x00000080 1761#define BGE_NVRAMSWARB_GNT0 0x00000100 1762#define BGE_NVRAMSWARB_GNT1 0x00000200 1763#define BGE_NVRAMSWARB_GNT2 0x00000400 1764#define BGE_NVRAMSWARB_GNT3 0x00000800 1765#define BGE_NVRAMSWARB_REQ0 0x00001000 1766#define BGE_NVRAMSWARB_REQ1 0x00002000 1767#define BGE_NVRAMSWARB_REQ2 0x00004000 1768#define BGE_NVRAMSWARB_REQ3 0x00008000 1769 1770#define BGE_NVRAMACC_ENABLE 0x00000001 1771#define BGE_NVRAMACC_WRENABLE 0x00000002 1772 1773/* Mode control register / 1774#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1775#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1776#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1777#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1778#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1779#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1780#define BGE_MODECTL_NO_RX_CRC 0x00000400 1781#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1782#define BGE_MODECTL_NO_TX_INTR 0x00002000 1783#define BGE_MODECTL_NO_RX_INTR 0x00004000 1784#define BGE_MODECTL_FORCE_PCI32 0x00008000 1785#define BGE_MODECTL_STACKUP 0x00010000 1786#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1787#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1788#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1789#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1790#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1791#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1792#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1793#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1794#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1795#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1796* 1797/* Misc. config register / 1798#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1799#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1800#define BGE_MISCCFG_BOARD_ID 0x0001E000 1801#define BGE_MISCCFG_BOARD_ID_5788 0x00010000 1802#define BGE_MISCCFG_BOARD_ID_5788M 0x00018000 1803#define BGE_MISCCFG_EPHY_IDDQ 0x00200000 1804* 1805#define BGE_32BITTIME_66MHZ (0x41 << 1) 1806 1807/* Misc. Local Control / 1808#define BGE_MLC_INTR_STATE 0x00000001 1809#define BGE_MLC_INTR_CLR 0x00000002 1810#define BGE_MLC_INTR_SET 0x00000004 1811#define BGE_MLC_INTR_ONATTN 0x00000008 1812#define BGE_MLC_MISCIO_IN0 0x00000100 1813#define BGE_MLC_MISCIO_IN1 0x00000200 1814#define BGE_MLC_MISCIO_IN2 0x00000400 1815#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1816#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1817#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1818#define BGE_MLC_MISCIO_OUT0 0x00004000 1819#define BGE_MLC_MISCIO_OUT1 0x00008000 1820#define BGE_MLC_MISCIO_OUT2 0x00010000 1821#define BGE_MLC_EXTRAM_ENB 0x00020000 1822#define BGE_MLC_SRAM_SIZE 0x001C0000 1823#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1824#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1825#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1826#define BGE_MLC_AUTO_EEPROM 0x01000000 1827* 1828#define BGE_SSRAMSIZE_256KB 0x00000000 1829#define BGE_SSRAMSIZE_512KB 0x00040000 1830#define BGE_SSRAMSIZE_1MB 0x00080000 1831#define BGE_SSRAMSIZE_2MB 0x000C0000 1832#define BGE_SSRAMSIZE_4MB 0x00100000 1833#define BGE_SSRAMSIZE_8MB 0x00140000 1834#define BGE_SSRAMSIZE_16M 0x00180000 1835 1836/* EEPROM address register / 1837#define BGE_EEADDR_ADDRESS 0x0000FFFC 1838#define BGE_EEADDR_HALFCLK 0x01FF0000 1839#define BGE_EEADDR_START 0x02000000 1840#define BGE_EEADDR_DEVID 0x1C000000 1841#define BGE_EEADDR_RESET 0x20000000 1842#define BGE_EEADDR_DONE 0x40000000 1843#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1844* 1845#define BGE_EEDEVID(x) ((x & 7) << 26) 1846#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1847#define BGE_HALFCLK_384SCL 0x60 1848#define BGE_EE_READCMD \ 1849 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1850 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1851#define BGE_EE_WRCMD \ 1852 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1853 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1854 1855/* EEPROM Control register / 1856#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1857#define BGE_EECTL_CLKOUT 0x00000002 1858#define BGE_EECTL_CLKIN 0x00000004 1859#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1860#define BGE_EECTL_DATAOUT 0x00000010 1861#define BGE_EECTL_DATAIN 0x00000020 1862* 1863/* MDI (MII/GMII) access register / 1864#define BGE_MDI_DATA 0x00000001 1865#define BGE_MDI_DIR 0x00000002 1866#define BGE_MDI_SEL 0x00000004 1867#define BGE_MDI_CLK 0x00000008 1868* 1869#define BGE_MEMWIN_START 0x00008000 1870#define BGE_MEMWIN_END 0x0000FFFF 1871 1872 1873#define BGE_MEMWIN_READ(sc, x, val) \ 1874 do { \ 1875 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1876 (0xFFFF0000 & x), 4); \ 1877 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1878 } while(0) 1879 1880#define BGE_MEMWIN_WRITE(sc, x, val) \ 1881 do { \ 1882 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1883 (0xFFFF0000 & x), 4); \ 1884 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1885 } while(0) 1886 1887/* 1888 * This magic number is written to the firmware mailbox at 0xb50 1889 * before a software reset is issued. After the internal firmware 1890 * has completed its initialization it will write the opposite of 1891 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1892 * driver to synchronize with the firmware. 1893 / 1894#define BGE_MAGIC_NUMBER 0x4B657654 1895* 1896typedef struct { 1897 uint32_t bge_addr_hi; 1898 uint32_t bge_addr_lo; 1899} bge_hostaddr; 1900 1901#define BGE_HOSTADDR(x, y) \ 1902 do { \ 1903 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1904 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1905 } while(0) 1906 1907#define BGE_ADDR_LO(y) \ 1908 ((uint64_t) (y) & 0xFFFFFFFF) 1909#define BGE_ADDR_HI(y) \ 1910 ((uint64_t) (y) >> 32) 1911 1912/* Ring control block structure / 1913struct bge_rcb { 1914* bge_hostaddr bge_hostaddr; 1915 uint32_t bge_maxlen_flags; 1916 uint32_t bge_nicaddr; 1917}; 1918 1919#define RCB_WRITE_4(sc, rcb, offset, val) \ 1920 bus_write_4(sc->bge_res, rcb + offsetof(struct bge_rcb, offset), val) 1921#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1922 1923#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1924#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1925 1926struct bge_tx_bd { 1927 bge_hostaddr bge_addr; 1928#if BYTE_ORDER == LITTLE_ENDIAN 1929 uint16_t bge_flags; 1930 uint16_t bge_len; 1931 uint16_t bge_vlan_tag; 1932 uint16_t bge_rsvd; 1933#else 1934 uint16_t bge_len; 1935 uint16_t bge_flags; 1936 uint16_t bge_rsvd; 1937 uint16_t bge_vlan_tag; 1938#endif 1939}; 1940 1941#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1942#define BGE_TXBDFLAG_IP_CSUM 0x0002 1943#define BGE_TXBDFLAG_END 0x0004 1944#define BGE_TXBDFLAG_IP_FRAG 0x0008 1945#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1946#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1947#define BGE_TXBDFLAG_COAL_NOW 0x0080 1948#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1949#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1950#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1951#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1952#define BGE_TXBDFLAG_NO_CRC 0x8000 1953 1954#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1955 BGE_SEND_RING_1_TO_4 + \ 1956 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1957 1958struct bge_rx_bd { 1959 bge_hostaddr bge_addr; 1960#if BYTE_ORDER == LITTLE_ENDIAN 1961 uint16_t bge_len; 1962 uint16_t bge_idx; 1963 uint16_t bge_flags; 1964 uint16_t bge_type; 1965 uint16_t bge_tcp_udp_csum; 1966 uint16_t bge_ip_csum; 1967 uint16_t bge_vlan_tag; 1968 uint16_t bge_error_flag; 1969#else 1970 uint16_t bge_idx; 1971 uint16_t bge_len; 1972 uint16_t bge_type; 1973 uint16_t bge_flags; 1974 uint16_t bge_ip_csum; 1975 uint16_t bge_tcp_udp_csum; 1976 uint16_t bge_error_flag; 1977 uint16_t bge_vlan_tag; 1978#endif 1979 uint32_t bge_rsvd; 1980 uint32_t bge_opaque; 1981}; 1982 1983struct bge_extrx_bd { 1984 bge_hostaddr bge_addr1; 1985 bge_hostaddr bge_addr2; 1986 bge_hostaddr bge_addr3; 1987#if BYTE_ORDER == LITTLE_ENDIAN 1988 uint16_t bge_len2; 1989 uint16_t bge_len1; 1990 uint16_t bge_rsvd1; 1991 uint16_t bge_len3; 1992#else 1993 uint16_t bge_len1; 1994 uint16_t bge_len2; 1995 uint16_t bge_len3; 1996 uint16_t bge_rsvd1; 1997#endif 1998 bge_hostaddr bge_addr0; 1999#if BYTE_ORDER == LITTLE_ENDIAN 2000 uint16_t bge_len0; 2001 uint16_t bge_idx; 2002 uint16_t bge_flags; 2003 uint16_t bge_type; 2004 uint16_t bge_tcp_udp_csum; 2005 uint16_t bge_ip_csum; 2006 uint16_t bge_vlan_tag; 2007 uint16_t bge_error_flag; 2008#else 2009 uint16_t bge_idx; 2010 uint16_t bge_len0; 2011 uint16_t bge_type; 2012 uint16_t bge_flags; 2013 uint16_t bge_ip_csum; 2014 uint16_t bge_tcp_udp_csum; 2015 uint16_t bge_error_flag; 2016 uint16_t bge_vlan_tag; 2017#endif 2018 uint32_t bge_rsvd0; 2019 uint32_t bge_opaque; 2020}; 2021 2022#define BGE_RXBDFLAG_END 0x0004 2023#define BGE_RXBDFLAG_JUMBO_RING 0x0020 2024#define BGE_RXBDFLAG_VLAN_TAG 0x0040 2025#define BGE_RXBDFLAG_ERROR 0x0400 2026#define BGE_RXBDFLAG_MINI_RING 0x0800 2027#define BGE_RXBDFLAG_IP_CSUM 0x1000 2028#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 2029#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 2030 2031#define BGE_RXERRFLAG_BAD_CRC 0x0001 2032#define BGE_RXERRFLAG_COLL_DETECT 0x0002 2033#define BGE_RXERRFLAG_LINK_LOST 0x0004 2034#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 2035#define BGE_RXERRFLAG_MAC_ABORT 0x0010 2036#define BGE_RXERRFLAG_RUNT 0x0020 2037#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 2038#define BGE_RXERRFLAG_GIANT 0x0080 2039 2040struct bge_sts_idx { 2041#if BYTE_ORDER == LITTLE_ENDIAN 2042 uint16_t bge_rx_prod_idx; 2043 uint16_t bge_tx_cons_idx; 2044#else 2045 uint16_t bge_tx_cons_idx; 2046 uint16_t bge_rx_prod_idx; 2047#endif 2048}; 2049 2050struct bge_status_block { 2051 uint32_t bge_status; 2052 uint32_t bge_rsvd0; 2053#if BYTE_ORDER == LITTLE_ENDIAN 2054 uint16_t bge_rx_jumbo_cons_idx; 2055 uint16_t bge_rx_std_cons_idx; 2056 uint16_t bge_rx_mini_cons_idx; 2057 uint16_t bge_rsvd1; 2058#else 2059 uint16_t bge_rx_std_cons_idx; 2060 uint16_t bge_rx_jumbo_cons_idx; 2061 uint16_t bge_rsvd1; 2062 uint16_t bge_rx_mini_cons_idx; 2063#endif 2064 struct bge_sts_idx bge_idx[16]; 2065}; 2066 2067#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 2068#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 2069 2070#define BGE_STATFLAG_UPDATED 0x00000001 2071#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 2072#define BGE_STATFLAG_ERROR 0x00000004 2073 2074 2075/* 2076 * Broadcom Vendor ID 2077 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 2078 * even though they're now manufactured by Broadcom) 2079 / 2080#define BCOM_VENDORID 0x14E4 2081#define BCOM_DEVICEID_BCM5700 0x1644 2082#define BCOM_DEVICEID_BCM5701 0x1645 2083#define BCOM_DEVICEID_BCM5702 0x1646 2084#define BCOM_DEVICEID_BCM5702X 0x16A6 2085#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 2086#define BCOM_DEVICEID_BCM5703 0x1647 2087#define BCOM_DEVICEID_BCM5703X 0x16A7 2088#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 2089#define BCOM_DEVICEID_BCM5704C 0x1648 2090#define BCOM_DEVICEID_BCM5704S 0x16A8 2091#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 2092#define BCOM_DEVICEID_BCM5705 0x1653 2093#define BCOM_DEVICEID_BCM5705K 0x1654 2094#define BCOM_DEVICEID_BCM5705F 0x166E 2095#define BCOM_DEVICEID_BCM5705M 0x165D 2096#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 2097#define BCOM_DEVICEID_BCM5714C 0x1668 2098#define BCOM_DEVICEID_BCM5714S 0x1669 2099#define BCOM_DEVICEID_BCM5715 0x1678 2100#define BCOM_DEVICEID_BCM5715S 0x1679 2101#define BCOM_DEVICEID_BCM5720 0x1658 2102#define BCOM_DEVICEID_BCM5721 0x1659 2103#define BCOM_DEVICEID_BCM5722 0x165A 2104#define BCOM_DEVICEID_BCM5750 0x1676 2105#define BCOM_DEVICEID_BCM5750M 0x167C 2106#define BCOM_DEVICEID_BCM5751 0x1677 2107#define BCOM_DEVICEID_BCM5751F 0x167E 2108#define BCOM_DEVICEID_BCM5751M 0x167D 2109#define BCOM_DEVICEID_BCM5752 0x1600 2110#define BCOM_DEVICEID_BCM5752M 0x1601 2111#define BCOM_DEVICEID_BCM5753 0x16F7 2112#define BCOM_DEVICEID_BCM5753F 0x16FE 2113#define BCOM_DEVICEID_BCM5753M 0x16FD 2114#define BCOM_DEVICEID_BCM5754 0x167A 2115#define BCOM_DEVICEID_BCM5754M 0x1672 2116#define BCOM_DEVICEID_BCM5755 0x167B 2117#define BCOM_DEVICEID_BCM5755M 0x1673 2118#define BCOM_DEVICEID_BCM5780 0x166A 2119#define BCOM_DEVICEID_BCM5780S 0x166B 2120#define BCOM_DEVICEID_BCM5781 0x16DD 2121#define BCOM_DEVICEID_BCM5782 0x1696 2122#define BCOM_DEVICEID_BCM5786 0x169A 2123#define BCOM_DEVICEID_BCM5787 0x169B 2124#define BCOM_DEVICEID_BCM5787M 0x1693 2125#define BCOM_DEVICEID_BCM5788 0x169C 2126#define BCOM_DEVICEID_BCM5789 0x169D 2127#define BCOM_DEVICEID_BCM5901 0x170D 2128#define BCOM_DEVICEID_BCM5901A2 0x170E 2129#define BCOM_DEVICEID_BCM5903M 0x16FF 2130#define BCOM_DEVICEID_BCM5906 0x1712 2131#define BCOM_DEVICEID_BCM5906M 0x1713 2132* 2133/* 2134 * Alteon AceNIC PCI vendor/device ID. 2135 / 2136#define ALTEON_VENDORID 0x12AE 2137#define ALTEON_DEVICEID_ACENIC 0x0001 2138#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2139#define ALTEON_DEVICEID_BCM5700 0x0003 2140#define ALTEON_DEVICEID_BCM5701 0x0004 2141* 2142/* 2143 * 3Com 3c996 PCI vendor/device ID. 2144 / 2145#define TC_VENDORID 0x10B7 2146#define TC_DEVICEID_3C996 0x0003 2147* 2148/* 2149 * SysKonnect PCI vendor ID 2150 / 2151#define SK_VENDORID 0x1148 2152#define SK_DEVICEID_ALTIMA 0x4400 2153#define SK_SUBSYSID_9D21 0x4421 2154#define SK_SUBSYSID_9D41 0x4441 2155* 2156/* 2157 * Altima PCI vendor/device ID. 2158 / 2159#define ALTIMA_VENDORID 0x173b 2160#define ALTIMA_DEVICE_AC1000 0x03e8 2161#define ALTIMA_DEVICE_AC1002 0x03e9 2162#define ALTIMA_DEVICE_AC9100 0x03ea 2163* 2164/* 2165 * Dell PCI vendor ID 2166 / 2167* 2168#define DELL_VENDORID 0x1028 2169 2170/* 2171 * Apple PCI vendor ID. 2172 / 2173#define APPLE_VENDORID 0x106b 2174#define APPLE_DEVICE_BCM5701 0x1645 2175* 2176/* 2177 * Sun PCI vendor ID 2178 / 2179#define SUN_VENDORID 0x108e 2180* 2181/* 2182 * Offset of MAC address inside EEPROM. 2183 / 2184#define BGE_EE_MAC_OFFSET 0x7C 2185#define BGE_EE_MAC_OFFSET_5906 0x10 2186#define BGE_EE_HWCFG_OFFSET 0xC8 2187* 2188#define BGE_HWCFG_VOLTAGE 0x00000003 2189#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2190#define BGE_HWCFG_MEDIA 0x00000030 2191#define BGE_HWCFG_ASF 0x00000080 2192 2193#define BGE_VOLTAGE_1POINT3 0x00000000 2194#define BGE_VOLTAGE_1POINT8 0x00000001 2195 2196#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2197#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2198#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2199 2200#define BGE_MEDIA_UNSPEC 0x00000000 2201#define BGE_MEDIA_COPPER 0x00000010 2202#define BGE_MEDIA_FIBER 0x00000020 2203 2204#define BGE_TICKS_PER_SEC 1000000 2205 2206/* 2207 * Ring size constants. 2208 / 2209#define BGE_EVENT_RING_CNT 256 2210#define BGE_CMD_RING_CNT 64 2211#define BGE_STD_RX_RING_CNT 512 2212#define BGE_JUMBO_RX_RING_CNT 256 2213#define BGE_MINI_RX_RING_CNT 1024 2214#define BGE_RETURN_RING_CNT 1024 2215* 2216/* 5705 has smaller return ring size / 2217* 2218#define BGE_RETURN_RING_CNT_5705 512 2219 2220/* 2221 * Possible TX ring sizes. 2222 / 2223#define BGE_TX_RING_CNT_128 128 2224#define BGE_TX_RING_BASE_128 0x3800 2225* 2226#define BGE_TX_RING_CNT_256 256 2227#define BGE_TX_RING_BASE_256 0x3000 2228 2229#define BGE_TX_RING_CNT_512 512 2230#define BGE_TX_RING_BASE_512 0x2000 2231 2232#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2233#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2234 2235/* 2236 * Tigon III statistics counters. 2237 / 2238/ Statistics maintained MAC Receive block. / 2239struct bge_rx_mac_stats { 2240* bge_hostaddr ifHCInOctets; 2241 bge_hostaddr Reserved1; 2242 bge_hostaddr etherStatsFragments; 2243 bge_hostaddr ifHCInUcastPkts; 2244 bge_hostaddr ifHCInMulticastPkts; 2245 bge_hostaddr ifHCInBroadcastPkts; 2246 bge_hostaddr dot3StatsFCSErrors; 2247 bge_hostaddr dot3StatsAlignmentErrors; 2248 bge_hostaddr xonPauseFramesReceived; 2249 bge_hostaddr xoffPauseFramesReceived; 2250 bge_hostaddr macControlFramesReceived; 2251 bge_hostaddr xoffStateEntered; 2252 bge_hostaddr dot3StatsFramesTooLong; 2253 bge_hostaddr etherStatsJabbers; 2254 bge_hostaddr etherStatsUndersizePkts; 2255 bge_hostaddr inRangeLengthError; 2256 bge_hostaddr outRangeLengthError; 2257 bge_hostaddr etherStatsPkts64Octets; 2258 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2259 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2260 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2261 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2262 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2263 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2264 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2265 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2266 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2267}; 2268 2269 2270/* Statistics maintained MAC Transmit block. / 2271struct bge_tx_mac_stats { 2272* bge_hostaddr ifHCOutOctets; 2273 bge_hostaddr Reserved2; 2274 bge_hostaddr etherStatsCollisions; 2275 bge_hostaddr outXonSent; 2276 bge_hostaddr outXoffSent; 2277 bge_hostaddr flowControlDone; 2278 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2279 bge_hostaddr dot3StatsSingleCollisionFrames; 2280 bge_hostaddr dot3StatsMultipleCollisionFrames; 2281 bge_hostaddr dot3StatsDeferredTransmissions; 2282 bge_hostaddr Reserved3; 2283 bge_hostaddr dot3StatsExcessiveCollisions; 2284 bge_hostaddr dot3StatsLateCollisions; 2285 bge_hostaddr dot3Collided2Times; 2286 bge_hostaddr dot3Collided3Times; 2287 bge_hostaddr dot3Collided4Times; 2288 bge_hostaddr dot3Collided5Times; 2289 bge_hostaddr dot3Collided6Times; 2290 bge_hostaddr dot3Collided7Times; 2291 bge_hostaddr dot3Collided8Times; 2292 bge_hostaddr dot3Collided9Times; 2293 bge_hostaddr dot3Collided10Times; 2294 bge_hostaddr dot3Collided11Times; 2295 bge_hostaddr dot3Collided12Times; 2296 bge_hostaddr dot3Collided13Times; 2297 bge_hostaddr dot3Collided14Times; 2298 bge_hostaddr dot3Collided15Times; 2299 bge_hostaddr ifHCOutUcastPkts; 2300 bge_hostaddr ifHCOutMulticastPkts; 2301 bge_hostaddr ifHCOutBroadcastPkts; 2302 bge_hostaddr dot3StatsCarrierSenseErrors; 2303 bge_hostaddr ifOutDiscards; 2304 bge_hostaddr ifOutErrors; 2305}; 2306 2307/* Stats counters access through registers / 2308struct bge_mac_stats_regs { 2309* uint32_t ifHCOutOctets; 2310 uint32_t Reserved0; 2311 uint32_t etherStatsCollisions; 2312 uint32_t outXonSent; 2313 uint32_t outXoffSent; 2314 uint32_t Reserved1; 2315 uint32_t dot3StatsInternalMacTransmitErrors; 2316 uint32_t dot3StatsSingleCollisionFrames; 2317 uint32_t dot3StatsMultipleCollisionFrames; 2318 uint32_t dot3StatsDeferredTransmissions; 2319 uint32_t Reserved2; 2320 uint32_t dot3StatsExcessiveCollisions; 2321 uint32_t dot3StatsLateCollisions; 2322 uint32_t Reserved3[14]; 2323 uint32_t ifHCOutUcastPkts; 2324 uint32_t ifHCOutMulticastPkts; 2325 uint32_t ifHCOutBroadcastPkts; 2326 uint32_t Reserved4[2]; 2327 uint32_t ifHCInOctets; 2328 uint32_t Reserved5; 2329 uint32_t etherStatsFragments; 2330 uint32_t ifHCInUcastPkts; 2331 uint32_t ifHCInMulticastPkts; 2332 uint32_t ifHCInBroadcastPkts; 2333 uint32_t dot3StatsFCSErrors; 2334 uint32_t dot3StatsAlignmentErrors; 2335 uint32_t xonPauseFramesReceived; 2336 uint32_t xoffPauseFramesReceived; 2337 uint32_t macControlFramesReceived; 2338 uint32_t xoffStateEntered; 2339 uint32_t dot3StatsFramesTooLong; 2340 uint32_t etherStatsJabbers; 2341 uint32_t etherStatsUndersizePkts; 2342}; 2343 2344struct bge_stats { 2345 uint8_t Reserved0[256]; 2346 2347 /* Statistics maintained by Receive MAC. / 2348* struct bge_rx_mac_stats rxstats; 2349 2350 bge_hostaddr Unused1[37]; 2351 2352 /* Statistics maintained by Transmit MAC. / 2353* struct bge_tx_mac_stats txstats; 2354 2355 bge_hostaddr Unused2[31]; 2356 2357 /* Statistics maintained by Receive List Placement. / 2358* bge_hostaddr COSIfHCInPkts[16]; 2359 bge_hostaddr COSFramesDroppedDueToFilters; 2360 bge_hostaddr nicDmaWriteQueueFull; 2361 bge_hostaddr nicDmaWriteHighPriQueueFull; 2362 bge_hostaddr nicNoMoreRxBDs; 2363 bge_hostaddr ifInDiscards; 2364 bge_hostaddr ifInErrors; 2365 bge_hostaddr nicRecvThresholdHit; 2366 2367 bge_hostaddr Unused3[9]; 2368 2369 /* Statistics maintained by Send Data Initiator. / 2370* bge_hostaddr COSIfHCOutPkts[16]; 2371 bge_hostaddr nicDmaReadQueueFull; 2372 bge_hostaddr nicDmaReadHighPriQueueFull; 2373 bge_hostaddr nicSendDataCompQueueFull; 2374 2375 /* Statistics maintained by Host Coalescing. / 2376* bge_hostaddr nicRingSetSendProdIndex; 2377 bge_hostaddr nicRingStatusUpdate; 2378 bge_hostaddr nicInterrupts; 2379 bge_hostaddr nicAvoidedInterrupts; 2380 bge_hostaddr nicSendThresholdHit; 2381 2382 uint8_t Reserved4[320]; 2383}; 2384 2385/* 2386 * Tigon general information block. This resides in host memory 2387 * and contains the status counters, ring control blocks and 2388 * producer pointers. 2389 / 2390* 2391struct bge_gib { 2392 struct bge_stats bge_stats; 2393 struct bge_rcb bge_tx_rcb[16]; 2394 struct bge_rcb bge_std_rx_rcb; 2395 struct bge_rcb bge_jumbo_rx_rcb; 2396 struct bge_rcb bge_mini_rx_rcb; 2397 struct bge_rcb bge_return_rcb; 2398}; 2399 2400#define BGE_FRAMELEN 1518 2401#define BGE_MAX_FRAMELEN 1536 2402#define BGE_JUMBO_FRAMELEN 9018 2403#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2404#define BGE_MIN_FRAMELEN 60 2405 2406/* 2407 * Other utility macros. 2408 / 2409#define BGE_INC(x, y) (x) = (x + 1) % y 2410* 2411/* 2412 * Register access macros. The Tigon always uses memory mapped register 2413 * accesses and all registers must be accessed with 32 bit operations. 2414 / 2415* 2416#define CSR_WRITE_4(sc, reg, val) \ 2417 bus_write_4(sc->bge_res, reg, val) 2418 2419#define CSR_READ_4(sc, reg) \ 2420 bus_read_4(sc->bge_res, reg) 2421 2422#define BGE_SETBIT(sc, reg, x) \ 2423 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2424#define BGE_CLRBIT(sc, reg, x) \ 2425 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2426 2427#define PCI_SETBIT(dev, reg, x, s) \ 2428 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2429#define PCI_CLRBIT(dev, reg, x, s) \ 2430 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2431 2432/* 2433 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2434 * values are tuneable. They control the actual amount of buffers 2435 * allocated for the standard, mini and jumbo receive rings. 2436 / 2437* 2438#define BGE_SSLOTS 256 2439#define BGE_MSLOTS 256 2440#define BGE_JSLOTS 384 2441 2442#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2443#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2444 (BGE_JRAWLEN % sizeof(uint64_t)))) 2445#define BGE_JPAGESZ PAGE_SIZE 2446#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2447#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2448 2449#define BGE_NSEG_JUMBO 4 2450#define BGE_NSEG_NEW 32 2451 2452/* 2453 * Ring structures. Most of these reside in host memory and we tell 2454 * the NIC where they are via the ring control blocks. The exceptions 2455 * are the tx and command rings, which live in NIC memory and which 2456 * we access via the shared memory window. 2457 / 2458* 2459struct bge_ring_data { 2460 struct bge_rx_bd bge_rx_std_ring; 2461* bus_addr_t bge_rx_std_ring_paddr; 2462 struct bge_extrx_bd bge_rx_jumbo_ring; 2463* bus_addr_t bge_rx_jumbo_ring_paddr; 2464 struct bge_rx_bd bge_rx_return_ring; 2465* bus_addr_t bge_rx_return_ring_paddr; 2466 struct bge_tx_bd bge_tx_ring; 2467* bus_addr_t bge_tx_ring_paddr; 2468 struct bge_status_block bge_status_block; 2469* bus_addr_t bge_status_block_paddr; 2470 struct bge_stats bge_stats; 2471* bus_addr_t bge_stats_paddr; 2472 struct bge_gib bge_info; 2473}; 2474 2475#define BGE_STD_RX_RING_SZ \ 2476 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2477#define BGE_JUMBO_RX_RING_SZ \ 2478 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2479#define BGE_TX_RING_SZ \ 2480 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2481#define BGE_RX_RTN_RING_SZ(x) \ 2482 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2483 2484#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2485 2486#define BGE_STATS_SZ sizeof (struct bge_stats) 2487 2488/* 2489 * Mbuf pointers. We need these to keep track of the virtual addresses 2490 * of our mbuf chains since we can only convert from physical to virtual, 2491 * not the other way around. 2492 / 2493struct bge_chain_data { 2494* bus_dma_tag_t bge_parent_tag; 2495 bus_dma_tag_t bge_rx_std_ring_tag; 2496 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2497 bus_dma_tag_t bge_rx_return_ring_tag; 2498 bus_dma_tag_t bge_tx_ring_tag; 2499 bus_dma_tag_t bge_status_tag; 2500 bus_dma_tag_t bge_stats_tag; 2501 bus_dma_tag_t bge_mtag; /* mbuf mapping tag / 2502* bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag / 2503* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2504 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2505 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2506 bus_dmamap_t bge_rx_std_ring_map; 2507 bus_dmamap_t bge_rx_jumbo_ring_map; 2508 bus_dmamap_t bge_tx_ring_map; 2509 bus_dmamap_t bge_rx_return_ring_map; 2510 bus_dmamap_t bge_status_map; 2511 bus_dmamap_t bge_stats_map; 2512 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2513* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2514* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2515}; 2516* 2517struct bge_dmamap_arg { 2518 struct bge_softc sc; 2519* bus_addr_t bge_busaddr; 2520 uint16_t bge_flags; 2521 int bge_idx; 2522 int bge_maxsegs; 2523 struct bge_tx_bd bge_ring; 2524}; 2525* 2526#define BGE_HWREV_TIGON 0x01 2527#define BGE_HWREV_TIGON_II 0x02 2528#define BGE_TIMEOUT 100000 2529#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2530* 2531struct bge_bcom_hack { 2532 int reg; 2533 int val; 2534}; 2535 2536#define ASF_ENABLE 1 2537#define ASF_NEW_HANDSHAKE 2 2538#define ASF_STACKUP 4 2539 2540struct bge_softc { 2541 struct ifnet bge_ifp; / interface info / 2542* device_t bge_dev; 2543 struct mtx bge_mtx; 2544 device_t bge_miibus; 2545 void bge_intrhand; 2546* struct resource bge_irq; 2547* struct resource bge_res; 2548* struct ifmedia bge_ifmedia; /* TBI media info / 2549* uint32_t bge_flags; 2550#define BGE_FLAG_TBI 0x00000001 2551#define BGE_FLAG_JUMBO 0x00000002 2552#define BGE_FLAG_WIRESPEED 0x00000004 2553#define BGE_FLAG_EADDR 0x00000008 2554#define BGE_FLAG_MSI 0x00000100 2555#define BGE_FLAG_PCIX 0x00000200 2556#define BGE_FLAG_PCIE 0x00000400 2557#define BGE_FLAG_5700_FAMILY 0x00001000 2558#define BGE_FLAG_5705_PLUS 0x00002000 2559#define BGE_FLAG_5714_FAMILY 0x00004000 2560#define BGE_FLAG_575X_PLUS 0x00008000 2561#define BGE_FLAG_RX_ALIGNBUG 0x00100000 2562#define BGE_FLAG_NO_3LED 0x00200000 2563#define BGE_FLAG_ADC_BUG 0x00400000 2564#define BGE_FLAG_5704_A0_BUG 0x00800000 2565#define BGE_FLAG_JITTER_BUG 0x01000000 2566#define BGE_FLAG_BER_BUG 0x02000000 2567#define BGE_FLAG_ADJUST_TRIM 0x04000000 2568#define BGE_FLAG_CRC_BUG 0x08000000 2569#define BGE_FLAG_5788 0x20000000 2570 uint32_t bge_chipid; 2571 uint8_t bge_asicrev; 2572 uint8_t bge_chiprev; 2573 uint8_t bge_asf_mode; 2574 uint8_t bge_asf_count; 2575 struct bge_ring_data bge_ldata; /* rings / 2576* struct bge_chain_data bge_cdata; /* mbufs / 2577* uint16_t bge_tx_saved_considx; 2578 uint16_t bge_rx_saved_considx; 2579 uint16_t bge_ev_saved_considx; 2580 uint16_t bge_return_ring_cnt; 2581 uint16_t bge_std; /* current std ring head / 2582* uint16_t bge_jumbo; /* current jumo ring head / 2583* uint32_t bge_stat_ticks; 2584 uint32_t bge_rx_coal_ticks; 2585 uint32_t bge_tx_coal_ticks; 2586 uint32_t bge_tx_prodidx; 2587 uint32_t bge_rx_max_coal_bds; 2588 uint32_t bge_tx_max_coal_bds; 2589 uint32_t bge_tx_buf_ratio; 2590 int bge_if_flags; 2591 int bge_txcnt; 2592 int bge_link; /* link state / 2593* int bge_link_evt; /* pending link event / 2594* int bge_timer; 2595 struct callout bge_stat_ch; 2596 uint32_t bge_rx_discards; 2597 uint32_t bge_tx_discards; 2598 uint32_t bge_tx_collisions; 2599#ifdef DEVICE_POLLING 2600 int rxcycles; 2601#endif /* DEVICE_POLLING / 2602}; 2603* 2604#define BGE_LOCK_INIT(_sc, _name) \ 2605 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2606#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2607#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2608#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2609#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)