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if_bgereg.h (164769)	if_bgereg.h (164780)
1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *	1/- 2 Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 164769 2006-11-30 13:40:39Z glebius $	33 * $FreeBSD: head/sys/dev/bge/if_bgereg.h 164780 2006-12-01 01:08:52Z jkim $
34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_FW_DRV_ALIVE 0x00000001 79#define BGE_FW_PAUSE 0x00000002 80#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 81#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 82#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 83#define BGE_UNMAPPED 0x00001000 84#define BGE_UNMAPPED_END 0x00001FFF 85#define BGE_DMA_DESCRIPTORS 0x00002000 86#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 87#define BGE_SEND_RING_1_TO_4 0x00004000 88#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 89 90/ Mappings for internal memory configuration / 91#define BGE_STD_RX_RINGS 0x00006000 92#define BGE_STD_RX_RINGS_END 0x00006FFF 93#define BGE_JUMBO_RX_RINGS 0x00007000 94#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 95#define BGE_BUFFPOOL_1 0x00008000 96#define BGE_BUFFPOOL_1_END 0x0000FFFF 97#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 98#define BGE_BUFFPOOL_2_END 0x00017FFF 99#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 100#define BGE_BUFFPOOL_3_END 0x0001FFFF 101* 102/* Mappings for external SSRAM configurations / 103#define BGE_SEND_RING_5_TO_6 0x00006000 104#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 105#define BGE_SEND_RING_7_TO_8 0x00007000 106#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 107#define BGE_SEND_RING_9_TO_16 0x00008000 108#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 109#define BGE_EXT_STD_RX_RINGS 0x0000C000 110#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 111#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 112#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 113#define BGE_MINI_RX_RINGS 0x0000E000 114#define BGE_MINI_RX_RINGS_END 0x0000FFFF 115#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 116#define BGE_AVAIL_REGION1_END 0x00017FFF 117#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 118#define BGE_AVAIL_REGION2_END 0x0001FFFF 119#define BGE_EXT_SSRAM 0x00020000 120#define BGE_EXT_SSRAM_END 0x000FFFFF 121* 122 123/* 124 * BCM570x register offsets. These are memory mapped registers 125 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 126 * Each register must be accessed using 32 bit operations. 127 * 128 * All registers are accessed through a 32K shared memory block. 129 * The first group of registers are actually copies of the PCI 130 * configuration space registers. 131 / 132* 133/* 134 * PCI registers defined in the PCI 2.2 spec. 135 / 136#define BGE_PCI_VID 0x00 137#define BGE_PCI_DID 0x02 138#define BGE_PCI_CMD 0x04 139#define BGE_PCI_STS 0x06 140#define BGE_PCI_REV 0x08 141#define BGE_PCI_CLASS 0x09 142#define BGE_PCI_CACHESZ 0x0C 143#define BGE_PCI_LATTIMER 0x0D 144#define BGE_PCI_HDRTYPE 0x0E 145#define BGE_PCI_BIST 0x0F 146#define BGE_PCI_BAR0 0x10 147#define BGE_PCI_BAR1 0x14 148#define BGE_PCI_SUBSYS 0x2C 149#define BGE_PCI_SUBVID 0x2E 150#define BGE_PCI_ROMBASE 0x30 151#define BGE_PCI_CAPPTR 0x34 152#define BGE_PCI_INTLINE 0x3C 153#define BGE_PCI_INTPIN 0x3D 154#define BGE_PCI_MINGNT 0x3E 155#define BGE_PCI_MAXLAT 0x3F 156#define BGE_PCI_PCIXCAP 0x40 157#define BGE_PCI_NEXTPTR_PM 0x41 158#define BGE_PCI_PCIX_CMD 0x42 159#define BGE_PCI_PCIX_STS 0x44 160#define BGE_PCI_PWRMGMT_CAPID 0x48 161#define BGE_PCI_NEXTPTR_VPD 0x49 162#define BGE_PCI_PWRMGMT_CAPS 0x4A 163#define BGE_PCI_PWRMGMT_CMD 0x4C 164#define BGE_PCI_PWRMGMT_STS 0x4D 165#define BGE_PCI_PWRMGMT_DATA 0x4F 166#define BGE_PCI_VPD_CAPID 0x50 167#define BGE_PCI_NEXTPTR_MSI 0x51 168#define BGE_PCI_VPD_ADDR 0x52 169#define BGE_PCI_VPD_DATA 0x54 170#define BGE_PCI_MSI_CAPID 0x58 171#define BGE_PCI_NEXTPTR_NONE 0x59 172#define BGE_PCI_MSI_CTL 0x5A 173#define BGE_PCI_MSI_ADDR_HI 0x5C 174#define BGE_PCI_MSI_ADDR_LO 0x60 175#define BGE_PCI_MSI_DATA 0x64 176* 177/* PCI MSI. ??? / 178#define BGE_PCIE_CAPID_REG 0xD0 179#define BGE_PCIE_CAPID 0x10 180* 181/* 182 * PCI registers specific to the BCM570x family. 183 / 184#define BGE_PCI_MISC_CTL 0x68 185#define BGE_PCI_DMA_RW_CTL 0x6C 186#define BGE_PCI_PCISTATE 0x70 187#define BGE_PCI_CLKCTL 0x74 188#define BGE_PCI_REG_BASEADDR 0x78 189#define BGE_PCI_MEMWIN_BASEADDR 0x7C 190#define BGE_PCI_REG_DATA 0x80 191#define BGE_PCI_MEMWIN_DATA 0x84 192#define BGE_PCI_MODECTL 0x88 193#define BGE_PCI_MISC_CFG 0x8C 194#define BGE_PCI_MISC_LOCALCTL 0x90 195#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 196#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 197#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 198#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 199#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 200#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 201#define BGE_PCI_ISR_MBX_HI 0xB0 202#define BGE_PCI_ISR_MBX_LO 0xB4 203* 204/* PCI Misc. Host control register / 205#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 206#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 207#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 208#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 209#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 210#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 211#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 212#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 213#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 214* 215#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 216#if BYTE_ORDER == LITTLE_ENDIAN 217#define BGE_DMA_SWAP_OPTIONS \ 218 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 219 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 220#else 221#define BGE_DMA_SWAP_OPTIONS \ 222 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 223 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 224#endif 225 226#define BGE_INIT \ 227 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 228 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 229 230#define BGE_CHIPID_TIGON_I 0x40000000 231#define BGE_CHIPID_TIGON_II 0x60000000 232#define BGE_CHIPID_BCM5700_A0 0x70000000 233#define BGE_CHIPID_BCM5700_A1 0x70010000 234#define BGE_CHIPID_BCM5700_B0 0x71000000 235#define BGE_CHIPID_BCM5700_B1 0x71010000 236#define BGE_CHIPID_BCM5700_B2 0x71020000 237#define BGE_CHIPID_BCM5700_B3 0x71030000 238#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 239#define BGE_CHIPID_BCM5700_C0 0x72000000 240#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr / 241#define BGE_CHIPID_BCM5701_B0 0x01000000 242#define BGE_CHIPID_BCM5701_B2 0x01020000 243#define BGE_CHIPID_BCM5701_B5 0x01050000 244#define BGE_CHIPID_BCM5703_A0 0x10000000 245#define BGE_CHIPID_BCM5703_A1 0x10010000 246#define BGE_CHIPID_BCM5703_A2 0x10020000 247#define BGE_CHIPID_BCM5703_A3 0x10030000 248#define BGE_CHIPID_BCM5703_B0 0x11000000 249#define BGE_CHIPID_BCM5704_A0 0x20000000 250#define BGE_CHIPID_BCM5704_A1 0x20010000 251#define BGE_CHIPID_BCM5704_A2 0x20020000 252#define BGE_CHIPID_BCM5704_A3 0x20030000 253#define BGE_CHIPID_BCM5704_B0 0x21000000 254#define BGE_CHIPID_BCM5705_A0 0x30000000 255#define BGE_CHIPID_BCM5705_A1 0x30010000 256#define BGE_CHIPID_BCM5705_A2 0x30020000 257#define BGE_CHIPID_BCM5705_A3 0x30030000 258#define BGE_CHIPID_BCM5750_A0 0x40000000 259#define BGE_CHIPID_BCM5750_A1 0x40010000 260#define BGE_CHIPID_BCM5750_A3 0x40030000 261#define BGE_CHIPID_BCM5750_B0 0x40100000 262#define BGE_CHIPID_BCM5750_B1 0x41010000 263#define BGE_CHIPID_BCM5750_C0 0x42000000 264#define BGE_CHIPID_BCM5750_C1 0x42010000 265#define BGE_CHIPID_BCM5750_C2 0x42020000 266#define BGE_CHIPID_BCM5714_A0 0x50000000 267#define BGE_CHIPID_BCM5752_A0 0x60000000 268#define BGE_CHIPID_BCM5752_A1 0x60010000 269#define BGE_CHIPID_BCM5752_A2 0x60020000 270#define BGE_CHIPID_BCM5714_B0 0x80000000 271#define BGE_CHIPID_BCM5714_B3 0x80030000 272#define BGE_CHIPID_BCM5715_A0 0x90000000 273#define BGE_CHIPID_BCM5715_A1 0x90010000 274* 275/* shorthand one / 276#define BGE_ASICREV(x) ((x) >> 28) 277#define BGE_ASICREV_BCM5701 0x00 278#define BGE_ASICREV_BCM5703 0x01 279#define BGE_ASICREV_BCM5704 0x02 280#define BGE_ASICREV_BCM5705 0x03 281#define BGE_ASICREV_BCM5750 0x04 282#define BGE_ASICREV_BCM5714_A0 0x05 283#define BGE_ASICREV_BCM5752 0x06 284#define BGE_ASICREV_BCM5700 0x07 285#define BGE_ASICREV_BCM5780 0x08 286#define BGE_ASICREV_BCM5714 0x09 287#define BGE_ASICREV_BCM5755 0x0a 288#define BGE_ASICREV_BCM5787 0x0b 289* 290/* chip revisions / 291#define BGE_CHIPREV(x) ((x) >> 24) 292#define BGE_CHIPREV_5700_AX 0x70 293#define BGE_CHIPREV_5700_BX 0x71 294#define BGE_CHIPREV_5700_CX 0x72 295#define BGE_CHIPREV_5701_AX 0x00 296* 297/* PCI DMA Read/Write Control register / 298#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 299#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 300#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 301#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 302#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 303# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 304#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 305# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 306#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 307#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 308#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 309# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 310#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 311# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 312* 313#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 314#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 315#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 316#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 317#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 318#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 319#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 320#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 321 322#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 323#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 324#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 325#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 326#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 327#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 328#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 329#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 330 331/* 332 * PCI state register -- note, this register is read only 333 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 334 * register is set. 335 / 336#define BGE_PCISTATE_FORCE_RESET 0x00000001 337#define BGE_PCISTATE_INTR_STATE 0x00000002 338#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 339#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 33/66, 0 = 66/133 / 340#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 341#define BGE_PCISTATE_WANT_EXPROM 0x00000020 342#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 343#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 344#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 345* 346/* 347 * PCI Clock Control register -- note, this register is read only 348 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 349 * register is set. 350 / 351#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 352#define BGE_PCICLOCKCTL_M66EN 0x00000080 353#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 354#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 355#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 356#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 357#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 358#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 359#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 360#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 361* 362 363#ifndef PCIM_CMD_MWIEN 364#define PCIM_CMD_MWIEN 0x0010 365#endif 366 367/* 368 * High priority mailbox registers 369 * Each mailbox is 64-bits wide, though we only use the 370 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 371 * first. The NIC will load the mailbox after the lower 32 bit word 372 * has been updated. 373 / 374#define BGE_MBX_IRQ0_HI 0x0200 375#define BGE_MBX_IRQ0_LO 0x0204 376#define BGE_MBX_IRQ1_HI 0x0208 377#define BGE_MBX_IRQ1_LO 0x020C 378#define BGE_MBX_IRQ2_HI 0x0210 379#define BGE_MBX_IRQ2_LO 0x0214 380#define BGE_MBX_IRQ3_HI 0x0218 381#define BGE_MBX_IRQ3_LO 0x021C 382#define BGE_MBX_GEN0_HI 0x0220 383#define BGE_MBX_GEN0_LO 0x0224 384#define BGE_MBX_GEN1_HI 0x0228 385#define BGE_MBX_GEN1_LO 0x022C 386#define BGE_MBX_GEN2_HI 0x0230 387#define BGE_MBX_GEN2_LO 0x0234 388#define BGE_MBX_GEN3_HI 0x0228 389#define BGE_MBX_GEN3_LO 0x022C 390#define BGE_MBX_GEN4_HI 0x0240 391#define BGE_MBX_GEN4_LO 0x0244 392#define BGE_MBX_GEN5_HI 0x0248 393#define BGE_MBX_GEN5_LO 0x024C 394#define BGE_MBX_GEN6_HI 0x0250 395#define BGE_MBX_GEN6_LO 0x0254 396#define BGE_MBX_GEN7_HI 0x0258 397#define BGE_MBX_GEN7_LO 0x025C 398#define BGE_MBX_RELOAD_STATS_HI 0x0260 399#define BGE_MBX_RELOAD_STATS_LO 0x0264 400#define BGE_MBX_RX_STD_PROD_HI 0x0268 401#define BGE_MBX_RX_STD_PROD_LO 0x026C 402#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 403#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 404#define BGE_MBX_RX_MINI_PROD_HI 0x0278 405#define BGE_MBX_RX_MINI_PROD_LO 0x027C 406#define BGE_MBX_RX_CONS0_HI 0x0280 407#define BGE_MBX_RX_CONS0_LO 0x0284 408#define BGE_MBX_RX_CONS1_HI 0x0288 409#define BGE_MBX_RX_CONS1_LO 0x028C 410#define BGE_MBX_RX_CONS2_HI 0x0290 411#define BGE_MBX_RX_CONS2_LO 0x0294 412#define BGE_MBX_RX_CONS3_HI 0x0298 413#define BGE_MBX_RX_CONS3_LO 0x029C 414#define BGE_MBX_RX_CONS4_HI 0x02A0 415#define BGE_MBX_RX_CONS4_LO 0x02A4 416#define BGE_MBX_RX_CONS5_HI 0x02A8 417#define BGE_MBX_RX_CONS5_LO 0x02AC 418#define BGE_MBX_RX_CONS6_HI 0x02B0 419#define BGE_MBX_RX_CONS6_LO 0x02B4 420#define BGE_MBX_RX_CONS7_HI 0x02B8 421#define BGE_MBX_RX_CONS7_LO 0x02BC 422#define BGE_MBX_RX_CONS8_HI 0x02C0 423#define BGE_MBX_RX_CONS8_LO 0x02C4 424#define BGE_MBX_RX_CONS9_HI 0x02C8 425#define BGE_MBX_RX_CONS9_LO 0x02CC 426#define BGE_MBX_RX_CONS10_HI 0x02D0 427#define BGE_MBX_RX_CONS10_LO 0x02D4 428#define BGE_MBX_RX_CONS11_HI 0x02D8 429#define BGE_MBX_RX_CONS11_LO 0x02DC 430#define BGE_MBX_RX_CONS12_HI 0x02E0 431#define BGE_MBX_RX_CONS12_LO 0x02E4 432#define BGE_MBX_RX_CONS13_HI 0x02E8 433#define BGE_MBX_RX_CONS13_LO 0x02EC 434#define BGE_MBX_RX_CONS14_HI 0x02F0 435#define BGE_MBX_RX_CONS14_LO 0x02F4 436#define BGE_MBX_RX_CONS15_HI 0x02F8 437#define BGE_MBX_RX_CONS15_LO 0x02FC 438#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 439#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 440#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 441#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 442#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 443#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 444#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 445#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 446#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 447#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 448#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 449#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 450#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 451#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 452#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 453#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 454#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 455#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 456#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 457#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 458#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 459#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 460#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 461#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 462#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 463#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 464#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 465#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 466#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 467#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 468#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 469#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 470#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 471#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 472#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 473#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 474#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 475#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 476#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 477#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 478#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 479#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 480#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 481#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 482#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 483#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 484#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 485#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 486#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 487#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 488#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 489#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 490#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 491#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 492#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 493#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 494#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 495#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 496#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 497#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 498#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 499#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 500#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 501#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 502* 503#define BGE_TX_RINGS_MAX 4 504#define BGE_TX_RINGS_EXTSSRAM_MAX 16 505#define BGE_RX_RINGS_MAX 16 506 507/* Ethernet MAC control registers / 508#define BGE_MAC_MODE 0x0400 509#define BGE_MAC_STS 0x0404 510#define BGE_MAC_EVT_ENB 0x0408 511#define BGE_MAC_LED_CTL 0x040C 512#define BGE_MAC_ADDR1_LO 0x0410 513#define BGE_MAC_ADDR1_HI 0x0414 514#define BGE_MAC_ADDR2_LO 0x0418 515#define BGE_MAC_ADDR2_HI 0x041C 516#define BGE_MAC_ADDR3_LO 0x0420 517#define BGE_MAC_ADDR3_HI 0x0424 518#define BGE_MAC_ADDR4_LO 0x0428 519#define BGE_MAC_ADDR4_HI 0x042C 520#define BGE_WOL_PATPTR 0x0430 521#define BGE_WOL_PATCFG 0x0434 522#define BGE_TX_RANDOM_BACKOFF 0x0438 523#define BGE_RX_MTU 0x043C 524#define BGE_GBIT_PCS_TEST 0x0440 525#define BGE_TX_TBI_AUTONEG 0x0444 526#define BGE_RX_TBI_AUTONEG 0x0448 527#define BGE_MI_COMM 0x044C 528#define BGE_MI_STS 0x0450 529#define BGE_MI_MODE 0x0454 530#define BGE_AUTOPOLL_STS 0x0458 531#define BGE_TX_MODE 0x045C 532#define BGE_TX_STS 0x0460 533#define BGE_TX_LENGTHS 0x0464 534#define BGE_RX_MODE 0x0468 535#define BGE_RX_STS 0x046C 536#define BGE_MAR0 0x0470 537#define BGE_MAR1 0x0474 538#define BGE_MAR2 0x0478 539#define BGE_MAR3 0x047C 540#define BGE_RX_BD_RULES_CTL0 0x0480 541#define BGE_RX_BD_RULES_MASKVAL0 0x0484 542#define BGE_RX_BD_RULES_CTL1 0x0488 543#define BGE_RX_BD_RULES_MASKVAL1 0x048C 544#define BGE_RX_BD_RULES_CTL2 0x0490 545#define BGE_RX_BD_RULES_MASKVAL2 0x0494 546#define BGE_RX_BD_RULES_CTL3 0x0498 547#define BGE_RX_BD_RULES_MASKVAL3 0x049C 548#define BGE_RX_BD_RULES_CTL4 0x04A0 549#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 550#define BGE_RX_BD_RULES_CTL5 0x04A8 551#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 552#define BGE_RX_BD_RULES_CTL6 0x04B0 553#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 554#define BGE_RX_BD_RULES_CTL7 0x04B8 555#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 556#define BGE_RX_BD_RULES_CTL8 0x04C0 557#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 558#define BGE_RX_BD_RULES_CTL9 0x04C8 559#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 560#define BGE_RX_BD_RULES_CTL10 0x04D0 561#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 562#define BGE_RX_BD_RULES_CTL11 0x04D8 563#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 564#define BGE_RX_BD_RULES_CTL12 0x04E0 565#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 566#define BGE_RX_BD_RULES_CTL13 0x04E8 567#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 568#define BGE_RX_BD_RULES_CTL14 0x04F0 569#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 570#define BGE_RX_BD_RULES_CTL15 0x04F8 571#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 572#define BGE_RX_RULES_CFG 0x0500 573#define BGE_SERDES_CFG 0x0590 574#define BGE_SERDES_STS 0x0594 575#define BGE_SGDIG_CFG 0x05B0 576*#define BGE_SGDIG_STS 0x05B4	34 / 35 36/ 37 * BCM570x memory map. The internal memory layout varies somewhat 38 * depending on whether or not we have external SSRAM attached. 39 * The BCM5700 can have up to 16MB of external memory. The BCM5701 40 * is apparently not designed to use external SSRAM. The mappings 41 * up to the first 4 send rings are the same for both internal and 42 * external memory configurations. Note that mini RX ring space is 43 * only available with external SSRAM configurations, which means 44 * the mini RX ring is not supported on the BCM5701. 45 * 46 * The NIC's memory can be accessed by the host in one of 3 ways: 47 * 48 * 1) Indirect register access. The MEMWIN_BASEADDR and MEMWIN_DATA 49 * registers in PCI config space can be used to read any 32-bit 50 * address within the NIC's memory. 51 * 52 * 2) Memory window access. The MEMWIN_BASEADDR register in PCI config 53 * space can be used in conjunction with the memory window in the 54 * device register space at offset 0x8000 to read any 32K chunk 55 * of NIC memory. 56 * 57 * 3) Flat mode. If the 'flat mode' bit in the PCI state register is 58 * set, the device I/O mapping consumes 32MB of host address space, 59 * allowing all of the registers and internal NIC memory to be 60 * accessed directly. NIC memory addresses are offset by 0x01000000. 61 * Flat mode consumes so much host address space that it is not 62 * recommended. 63 / 64#define BGE_PAGE_ZERO 0x00000000 65#define BGE_PAGE_ZERO_END 0x000000FF 66#define BGE_SEND_RING_RCB 0x00000100 67#define BGE_SEND_RING_RCB_END 0x000001FF 68#define BGE_RX_RETURN_RING_RCB 0x00000200 69#define BGE_RX_RETURN_RING_RCB_END 0x000002FF 70#define BGE_STATS_BLOCK 0x00000300 71#define BGE_STATS_BLOCK_END 0x00000AFF 72#define BGE_STATUS_BLOCK 0x00000B00 73#define BGE_STATUS_BLOCK_END 0x00000B4F 74#define BGE_SOFTWARE_GENCOMM 0x00000B50 75#define BGE_SOFTWARE_GENCOMM_SIG 0x00000B54 76#define BGE_SOFTWARE_GENCOMM_NICCFG 0x00000B58 77#define BGE_SOFTWARE_GENCOMM_FW 0x00000B78 78#define BGE_FW_DRV_ALIVE 0x00000001 79#define BGE_FW_PAUSE 0x00000002 80#define BGE_SOFTWARE_GENNCOMM_FW_LEN 0x00000B7C 81#define BGE_SOFTWARE_GENNCOMM_FW_DATA 0x00000B80 82#define BGE_SOFTWARE_GENCOMM_END 0x00000FFF 83#define BGE_UNMAPPED 0x00001000 84#define BGE_UNMAPPED_END 0x00001FFF 85#define BGE_DMA_DESCRIPTORS 0x00002000 86#define BGE_DMA_DESCRIPTORS_END 0x00003FFF 87#define BGE_SEND_RING_1_TO_4 0x00004000 88#define BGE_SEND_RING_1_TO_4_END 0x00005FFF 89 90/ Mappings for internal memory configuration / 91#define BGE_STD_RX_RINGS 0x00006000 92#define BGE_STD_RX_RINGS_END 0x00006FFF 93#define BGE_JUMBO_RX_RINGS 0x00007000 94#define BGE_JUMBO_RX_RINGS_END 0x00007FFF 95#define BGE_BUFFPOOL_1 0x00008000 96#define BGE_BUFFPOOL_1_END 0x0000FFFF 97#define BGE_BUFFPOOL_2 0x00010000 / or expansion ROM / 98#define BGE_BUFFPOOL_2_END 0x00017FFF 99#define BGE_BUFFPOOL_3 0x00018000 / or expansion ROM / 100#define BGE_BUFFPOOL_3_END 0x0001FFFF 101* 102/* Mappings for external SSRAM configurations / 103#define BGE_SEND_RING_5_TO_6 0x00006000 104#define BGE_SEND_RING_5_TO_6_END 0x00006FFF 105#define BGE_SEND_RING_7_TO_8 0x00007000 106#define BGE_SEND_RING_7_TO_8_END 0x00007FFF 107#define BGE_SEND_RING_9_TO_16 0x00008000 108#define BGE_SEND_RING_9_TO_16_END 0x0000BFFF 109#define BGE_EXT_STD_RX_RINGS 0x0000C000 110#define BGE_EXT_STD_RX_RINGS_END 0x0000CFFF 111#define BGE_EXT_JUMBO_RX_RINGS 0x0000D000 112#define BGE_EXT_JUMBO_RX_RINGS_END 0x0000DFFF 113#define BGE_MINI_RX_RINGS 0x0000E000 114#define BGE_MINI_RX_RINGS_END 0x0000FFFF 115#define BGE_AVAIL_REGION1 0x00010000 / or expansion ROM / 116#define BGE_AVAIL_REGION1_END 0x00017FFF 117#define BGE_AVAIL_REGION2 0x00018000 / or expansion ROM / 118#define BGE_AVAIL_REGION2_END 0x0001FFFF 119#define BGE_EXT_SSRAM 0x00020000 120#define BGE_EXT_SSRAM_END 0x000FFFFF 121* 122 123/* 124 * BCM570x register offsets. These are memory mapped registers 125 * which can be accessed with the CSR_READ_4()/CSR_WRITE_4() macros. 126 * Each register must be accessed using 32 bit operations. 127 * 128 * All registers are accessed through a 32K shared memory block. 129 * The first group of registers are actually copies of the PCI 130 * configuration space registers. 131 / 132* 133/* 134 * PCI registers defined in the PCI 2.2 spec. 135 / 136#define BGE_PCI_VID 0x00 137#define BGE_PCI_DID 0x02 138#define BGE_PCI_CMD 0x04 139#define BGE_PCI_STS 0x06 140#define BGE_PCI_REV 0x08 141#define BGE_PCI_CLASS 0x09 142#define BGE_PCI_CACHESZ 0x0C 143#define BGE_PCI_LATTIMER 0x0D 144#define BGE_PCI_HDRTYPE 0x0E 145#define BGE_PCI_BIST 0x0F 146#define BGE_PCI_BAR0 0x10 147#define BGE_PCI_BAR1 0x14 148#define BGE_PCI_SUBSYS 0x2C 149#define BGE_PCI_SUBVID 0x2E 150#define BGE_PCI_ROMBASE 0x30 151#define BGE_PCI_CAPPTR 0x34 152#define BGE_PCI_INTLINE 0x3C 153#define BGE_PCI_INTPIN 0x3D 154#define BGE_PCI_MINGNT 0x3E 155#define BGE_PCI_MAXLAT 0x3F 156#define BGE_PCI_PCIXCAP 0x40 157#define BGE_PCI_NEXTPTR_PM 0x41 158#define BGE_PCI_PCIX_CMD 0x42 159#define BGE_PCI_PCIX_STS 0x44 160#define BGE_PCI_PWRMGMT_CAPID 0x48 161#define BGE_PCI_NEXTPTR_VPD 0x49 162#define BGE_PCI_PWRMGMT_CAPS 0x4A 163#define BGE_PCI_PWRMGMT_CMD 0x4C 164#define BGE_PCI_PWRMGMT_STS 0x4D 165#define BGE_PCI_PWRMGMT_DATA 0x4F 166#define BGE_PCI_VPD_CAPID 0x50 167#define BGE_PCI_NEXTPTR_MSI 0x51 168#define BGE_PCI_VPD_ADDR 0x52 169#define BGE_PCI_VPD_DATA 0x54 170#define BGE_PCI_MSI_CAPID 0x58 171#define BGE_PCI_NEXTPTR_NONE 0x59 172#define BGE_PCI_MSI_CTL 0x5A 173#define BGE_PCI_MSI_ADDR_HI 0x5C 174#define BGE_PCI_MSI_ADDR_LO 0x60 175#define BGE_PCI_MSI_DATA 0x64 176* 177/* PCI MSI. ??? / 178#define BGE_PCIE_CAPID_REG 0xD0 179#define BGE_PCIE_CAPID 0x10 180* 181/* 182 * PCI registers specific to the BCM570x family. 183 / 184#define BGE_PCI_MISC_CTL 0x68 185#define BGE_PCI_DMA_RW_CTL 0x6C 186#define BGE_PCI_PCISTATE 0x70 187#define BGE_PCI_CLKCTL 0x74 188#define BGE_PCI_REG_BASEADDR 0x78 189#define BGE_PCI_MEMWIN_BASEADDR 0x7C 190#define BGE_PCI_REG_DATA 0x80 191#define BGE_PCI_MEMWIN_DATA 0x84 192#define BGE_PCI_MODECTL 0x88 193#define BGE_PCI_MISC_CFG 0x8C 194#define BGE_PCI_MISC_LOCALCTL 0x90 195#define BGE_PCI_UNDI_RX_STD_PRODIDX_HI 0x98 196#define BGE_PCI_UNDI_RX_STD_PRODIDX_LO 0x9C 197#define BGE_PCI_UNDI_RX_RTN_CONSIDX_HI 0xA0 198#define BGE_PCI_UNDI_RX_RTN_CONSIDX_LO 0xA4 199#define BGE_PCI_UNDI_TX_BD_PRODIDX_HI 0xA8 200#define BGE_PCI_UNDI_TX_BD_PRODIDX_LO 0xAC 201#define BGE_PCI_ISR_MBX_HI 0xB0 202#define BGE_PCI_ISR_MBX_LO 0xB4 203* 204/* PCI Misc. Host control register / 205#define BGE_PCIMISCCTL_CLEAR_INTA 0x00000001 206#define BGE_PCIMISCCTL_MASK_PCI_INTR 0x00000002 207#define BGE_PCIMISCCTL_ENDIAN_BYTESWAP 0x00000004 208#define BGE_PCIMISCCTL_ENDIAN_WORDSWAP 0x00000008 209#define BGE_PCIMISCCTL_PCISTATE_RW 0x00000010 210#define BGE_PCIMISCCTL_CLOCKCTL_RW 0x00000020 211#define BGE_PCIMISCCTL_REG_WORDSWAP 0x00000040 212#define BGE_PCIMISCCTL_INDIRECT_ACCESS 0x00000080 213#define BGE_PCIMISCCTL_ASICREV 0xFFFF0000 214* 215#define BGE_HIF_SWAP_OPTIONS (BGE_PCIMISCCTL_ENDIAN_WORDSWAP) 216#if BYTE_ORDER == LITTLE_ENDIAN 217#define BGE_DMA_SWAP_OPTIONS \ 218 BGE_MODECTL_WORDSWAP_NONFRAME\| \ 219 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 220#else 221#define BGE_DMA_SWAP_OPTIONS \ 222 BGE_MODECTL_WORDSWAP_NONFRAME\|BGE_MODECTL_BYTESWAP_NONFRAME\| \ 223 BGE_MODECTL_BYTESWAP_DATA\|BGE_MODECTL_WORDSWAP_DATA 224#endif 225 226#define BGE_INIT \ 227 (BGE_HIF_SWAP_OPTIONS\|BGE_PCIMISCCTL_CLEAR_INTA\| \ 228 BGE_PCIMISCCTL_MASK_PCI_INTR\|BGE_PCIMISCCTL_INDIRECT_ACCESS) 229 230#define BGE_CHIPID_TIGON_I 0x40000000 231#define BGE_CHIPID_TIGON_II 0x60000000 232#define BGE_CHIPID_BCM5700_A0 0x70000000 233#define BGE_CHIPID_BCM5700_A1 0x70010000 234#define BGE_CHIPID_BCM5700_B0 0x71000000 235#define BGE_CHIPID_BCM5700_B1 0x71010000 236#define BGE_CHIPID_BCM5700_B2 0x71020000 237#define BGE_CHIPID_BCM5700_B3 0x71030000 238#define BGE_CHIPID_BCM5700_ALTIMA 0x71040000 239#define BGE_CHIPID_BCM5700_C0 0x72000000 240#define BGE_CHIPID_BCM5701_A0 0x00000000 /* grrrr / 241#define BGE_CHIPID_BCM5701_B0 0x01000000 242#define BGE_CHIPID_BCM5701_B2 0x01020000 243#define BGE_CHIPID_BCM5701_B5 0x01050000 244#define BGE_CHIPID_BCM5703_A0 0x10000000 245#define BGE_CHIPID_BCM5703_A1 0x10010000 246#define BGE_CHIPID_BCM5703_A2 0x10020000 247#define BGE_CHIPID_BCM5703_A3 0x10030000 248#define BGE_CHIPID_BCM5703_B0 0x11000000 249#define BGE_CHIPID_BCM5704_A0 0x20000000 250#define BGE_CHIPID_BCM5704_A1 0x20010000 251#define BGE_CHIPID_BCM5704_A2 0x20020000 252#define BGE_CHIPID_BCM5704_A3 0x20030000 253#define BGE_CHIPID_BCM5704_B0 0x21000000 254#define BGE_CHIPID_BCM5705_A0 0x30000000 255#define BGE_CHIPID_BCM5705_A1 0x30010000 256#define BGE_CHIPID_BCM5705_A2 0x30020000 257#define BGE_CHIPID_BCM5705_A3 0x30030000 258#define BGE_CHIPID_BCM5750_A0 0x40000000 259#define BGE_CHIPID_BCM5750_A1 0x40010000 260#define BGE_CHIPID_BCM5750_A3 0x40030000 261#define BGE_CHIPID_BCM5750_B0 0x40100000 262#define BGE_CHIPID_BCM5750_B1 0x41010000 263#define BGE_CHIPID_BCM5750_C0 0x42000000 264#define BGE_CHIPID_BCM5750_C1 0x42010000 265#define BGE_CHIPID_BCM5750_C2 0x42020000 266#define BGE_CHIPID_BCM5714_A0 0x50000000 267#define BGE_CHIPID_BCM5752_A0 0x60000000 268#define BGE_CHIPID_BCM5752_A1 0x60010000 269#define BGE_CHIPID_BCM5752_A2 0x60020000 270#define BGE_CHIPID_BCM5714_B0 0x80000000 271#define BGE_CHIPID_BCM5714_B3 0x80030000 272#define BGE_CHIPID_BCM5715_A0 0x90000000 273#define BGE_CHIPID_BCM5715_A1 0x90010000 274* 275/* shorthand one / 276#define BGE_ASICREV(x) ((x) >> 28) 277#define BGE_ASICREV_BCM5701 0x00 278#define BGE_ASICREV_BCM5703 0x01 279#define BGE_ASICREV_BCM5704 0x02 280#define BGE_ASICREV_BCM5705 0x03 281#define BGE_ASICREV_BCM5750 0x04 282#define BGE_ASICREV_BCM5714_A0 0x05 283#define BGE_ASICREV_BCM5752 0x06 284#define BGE_ASICREV_BCM5700 0x07 285#define BGE_ASICREV_BCM5780 0x08 286#define BGE_ASICREV_BCM5714 0x09 287#define BGE_ASICREV_BCM5755 0x0a 288#define BGE_ASICREV_BCM5787 0x0b 289* 290/* chip revisions / 291#define BGE_CHIPREV(x) ((x) >> 24) 292#define BGE_CHIPREV_5700_AX 0x70 293#define BGE_CHIPREV_5700_BX 0x71 294#define BGE_CHIPREV_5700_CX 0x72 295#define BGE_CHIPREV_5701_AX 0x00 296* 297/* PCI DMA Read/Write Control register / 298#define BGE_PCIDMARWCTL_MINDMA 0x000000FF 299#define BGE_PCIDMARWCTL_RDADRR_BNDRY 0x00000700 300#define BGE_PCIDMARWCTL_WRADDR_BNDRY 0x00003800 301#define BGE_PCIDMARWCTL_ONEDMA_ATONCE 0x00004000 302#define BGE_PCIDMARWCTL_RD_WAT 0x00070000 303# define BGE_PCIDMARWCTL_RD_WAT_SHIFT 16 304#define BGE_PCIDMARWCTL_WR_WAT 0x00380000 305# define BGE_PCIDMARWCTL_WR_WAT_SHIFT 19 306#define BGE_PCIDMARWCTL_USE_MRM 0x00400000 307#define BGE_PCIDMARWCTL_ASRT_ALL_BE 0x00800000 308#define BGE_PCIDMARWCTL_DFLT_PCI_RD_CMD 0x0F000000 309# define BGE_PCIDMA_RWCTL_PCI_RD_CMD_SHIFT 24 310#define BGE_PCIDMARWCTL_DFLT_PCI_WR_CMD 0xF0000000 311# define BGE_PCIDMA_RWCTL_PCI_WR_CMD_SHIFT 28 312* 313#define BGE_PCI_READ_BNDRY_DISABLE 0x00000000 314#define BGE_PCI_READ_BNDRY_16BYTES 0x00000100 315#define BGE_PCI_READ_BNDRY_32BYTES 0x00000200 316#define BGE_PCI_READ_BNDRY_64BYTES 0x00000300 317#define BGE_PCI_READ_BNDRY_128BYTES 0x00000400 318#define BGE_PCI_READ_BNDRY_256BYTES 0x00000500 319#define BGE_PCI_READ_BNDRY_512BYTES 0x00000600 320#define BGE_PCI_READ_BNDRY_1024BYTES 0x00000700 321 322#define BGE_PCI_WRITE_BNDRY_DISABLE 0x00000000 323#define BGE_PCI_WRITE_BNDRY_16BYTES 0x00000800 324#define BGE_PCI_WRITE_BNDRY_32BYTES 0x00001000 325#define BGE_PCI_WRITE_BNDRY_64BYTES 0x00001800 326#define BGE_PCI_WRITE_BNDRY_128BYTES 0x00002000 327#define BGE_PCI_WRITE_BNDRY_256BYTES 0x00002800 328#define BGE_PCI_WRITE_BNDRY_512BYTES 0x00003000 329#define BGE_PCI_WRITE_BNDRY_1024BYTES 0x00003800 330 331/* 332 * PCI state register -- note, this register is read only 333 * unless the PCISTATE_WR bit of the PCI Misc. Host Control 334 * register is set. 335 / 336#define BGE_PCISTATE_FORCE_RESET 0x00000001 337#define BGE_PCISTATE_INTR_STATE 0x00000002 338#define BGE_PCISTATE_PCI_BUSMODE 0x00000004 / 1 = PCI, 0 = PCI-X / 339#define BGE_PCISTATE_PCI_BUSSPEED 0x00000008 / 1 = 33/66, 0 = 66/133 / 340#define BGE_PCISTATE_32BIT_BUS 0x00000010 / 1 = 32bit, 0 = 64bit / 341#define BGE_PCISTATE_WANT_EXPROM 0x00000020 342#define BGE_PCISTATE_EXPROM_RETRY 0x00000040 343#define BGE_PCISTATE_FLATVIEW_MODE 0x00000100 344#define BGE_PCISTATE_PCI_TGT_RETRY_MAX 0x00000E00 345* 346/* 347 * PCI Clock Control register -- note, this register is read only 348 * unless the CLOCKCTL_RW bit of the PCI Misc. Host Control 349 * register is set. 350 / 351#define BGE_PCICLOCKCTL_DETECTED_SPEED 0x0000000F 352#define BGE_PCICLOCKCTL_M66EN 0x00000080 353#define BGE_PCICLOCKCTL_LOWPWR_CLKMODE 0x00000200 354#define BGE_PCICLOCKCTL_RXCPU_CLK_DIS 0x00000400 355#define BGE_PCICLOCKCTL_TXCPU_CLK_DIS 0x00000800 356#define BGE_PCICLOCKCTL_ALTCLK 0x00001000 357#define BGE_PCICLOCKCTL_ALTCLK_SRC 0x00002000 358#define BGE_PCICLOCKCTL_PCIPLL_DISABLE 0x00004000 359#define BGE_PCICLOCKCTL_SYSPLL_DISABLE 0x00008000 360#define BGE_PCICLOCKCTL_BIST_ENABLE 0x00010000 361* 362 363#ifndef PCIM_CMD_MWIEN 364#define PCIM_CMD_MWIEN 0x0010 365#endif 366 367/* 368 * High priority mailbox registers 369 * Each mailbox is 64-bits wide, though we only use the 370 * lower 32 bits. To write a 64-bit value, write the upper 32 bits 371 * first. The NIC will load the mailbox after the lower 32 bit word 372 * has been updated. 373 / 374#define BGE_MBX_IRQ0_HI 0x0200 375#define BGE_MBX_IRQ0_LO 0x0204 376#define BGE_MBX_IRQ1_HI 0x0208 377#define BGE_MBX_IRQ1_LO 0x020C 378#define BGE_MBX_IRQ2_HI 0x0210 379#define BGE_MBX_IRQ2_LO 0x0214 380#define BGE_MBX_IRQ3_HI 0x0218 381#define BGE_MBX_IRQ3_LO 0x021C 382#define BGE_MBX_GEN0_HI 0x0220 383#define BGE_MBX_GEN0_LO 0x0224 384#define BGE_MBX_GEN1_HI 0x0228 385#define BGE_MBX_GEN1_LO 0x022C 386#define BGE_MBX_GEN2_HI 0x0230 387#define BGE_MBX_GEN2_LO 0x0234 388#define BGE_MBX_GEN3_HI 0x0228 389#define BGE_MBX_GEN3_LO 0x022C 390#define BGE_MBX_GEN4_HI 0x0240 391#define BGE_MBX_GEN4_LO 0x0244 392#define BGE_MBX_GEN5_HI 0x0248 393#define BGE_MBX_GEN5_LO 0x024C 394#define BGE_MBX_GEN6_HI 0x0250 395#define BGE_MBX_GEN6_LO 0x0254 396#define BGE_MBX_GEN7_HI 0x0258 397#define BGE_MBX_GEN7_LO 0x025C 398#define BGE_MBX_RELOAD_STATS_HI 0x0260 399#define BGE_MBX_RELOAD_STATS_LO 0x0264 400#define BGE_MBX_RX_STD_PROD_HI 0x0268 401#define BGE_MBX_RX_STD_PROD_LO 0x026C 402#define BGE_MBX_RX_JUMBO_PROD_HI 0x0270 403#define BGE_MBX_RX_JUMBO_PROD_LO 0x0274 404#define BGE_MBX_RX_MINI_PROD_HI 0x0278 405#define BGE_MBX_RX_MINI_PROD_LO 0x027C 406#define BGE_MBX_RX_CONS0_HI 0x0280 407#define BGE_MBX_RX_CONS0_LO 0x0284 408#define BGE_MBX_RX_CONS1_HI 0x0288 409#define BGE_MBX_RX_CONS1_LO 0x028C 410#define BGE_MBX_RX_CONS2_HI 0x0290 411#define BGE_MBX_RX_CONS2_LO 0x0294 412#define BGE_MBX_RX_CONS3_HI 0x0298 413#define BGE_MBX_RX_CONS3_LO 0x029C 414#define BGE_MBX_RX_CONS4_HI 0x02A0 415#define BGE_MBX_RX_CONS4_LO 0x02A4 416#define BGE_MBX_RX_CONS5_HI 0x02A8 417#define BGE_MBX_RX_CONS5_LO 0x02AC 418#define BGE_MBX_RX_CONS6_HI 0x02B0 419#define BGE_MBX_RX_CONS6_LO 0x02B4 420#define BGE_MBX_RX_CONS7_HI 0x02B8 421#define BGE_MBX_RX_CONS7_LO 0x02BC 422#define BGE_MBX_RX_CONS8_HI 0x02C0 423#define BGE_MBX_RX_CONS8_LO 0x02C4 424#define BGE_MBX_RX_CONS9_HI 0x02C8 425#define BGE_MBX_RX_CONS9_LO 0x02CC 426#define BGE_MBX_RX_CONS10_HI 0x02D0 427#define BGE_MBX_RX_CONS10_LO 0x02D4 428#define BGE_MBX_RX_CONS11_HI 0x02D8 429#define BGE_MBX_RX_CONS11_LO 0x02DC 430#define BGE_MBX_RX_CONS12_HI 0x02E0 431#define BGE_MBX_RX_CONS12_LO 0x02E4 432#define BGE_MBX_RX_CONS13_HI 0x02E8 433#define BGE_MBX_RX_CONS13_LO 0x02EC 434#define BGE_MBX_RX_CONS14_HI 0x02F0 435#define BGE_MBX_RX_CONS14_LO 0x02F4 436#define BGE_MBX_RX_CONS15_HI 0x02F8 437#define BGE_MBX_RX_CONS15_LO 0x02FC 438#define BGE_MBX_TX_HOST_PROD0_HI 0x0300 439#define BGE_MBX_TX_HOST_PROD0_LO 0x0304 440#define BGE_MBX_TX_HOST_PROD1_HI 0x0308 441#define BGE_MBX_TX_HOST_PROD1_LO 0x030C 442#define BGE_MBX_TX_HOST_PROD2_HI 0x0310 443#define BGE_MBX_TX_HOST_PROD2_LO 0x0314 444#define BGE_MBX_TX_HOST_PROD3_HI 0x0318 445#define BGE_MBX_TX_HOST_PROD3_LO 0x031C 446#define BGE_MBX_TX_HOST_PROD4_HI 0x0320 447#define BGE_MBX_TX_HOST_PROD4_LO 0x0324 448#define BGE_MBX_TX_HOST_PROD5_HI 0x0328 449#define BGE_MBX_TX_HOST_PROD5_LO 0x032C 450#define BGE_MBX_TX_HOST_PROD6_HI 0x0330 451#define BGE_MBX_TX_HOST_PROD6_LO 0x0334 452#define BGE_MBX_TX_HOST_PROD7_HI 0x0338 453#define BGE_MBX_TX_HOST_PROD7_LO 0x033C 454#define BGE_MBX_TX_HOST_PROD8_HI 0x0340 455#define BGE_MBX_TX_HOST_PROD8_LO 0x0344 456#define BGE_MBX_TX_HOST_PROD9_HI 0x0348 457#define BGE_MBX_TX_HOST_PROD9_LO 0x034C 458#define BGE_MBX_TX_HOST_PROD10_HI 0x0350 459#define BGE_MBX_TX_HOST_PROD10_LO 0x0354 460#define BGE_MBX_TX_HOST_PROD11_HI 0x0358 461#define BGE_MBX_TX_HOST_PROD11_LO 0x035C 462#define BGE_MBX_TX_HOST_PROD12_HI 0x0360 463#define BGE_MBX_TX_HOST_PROD12_LO 0x0364 464#define BGE_MBX_TX_HOST_PROD13_HI 0x0368 465#define BGE_MBX_TX_HOST_PROD13_LO 0x036C 466#define BGE_MBX_TX_HOST_PROD14_HI 0x0370 467#define BGE_MBX_TX_HOST_PROD14_LO 0x0374 468#define BGE_MBX_TX_HOST_PROD15_HI 0x0378 469#define BGE_MBX_TX_HOST_PROD15_LO 0x037C 470#define BGE_MBX_TX_NIC_PROD0_HI 0x0380 471#define BGE_MBX_TX_NIC_PROD0_LO 0x0384 472#define BGE_MBX_TX_NIC_PROD1_HI 0x0388 473#define BGE_MBX_TX_NIC_PROD1_LO 0x038C 474#define BGE_MBX_TX_NIC_PROD2_HI 0x0390 475#define BGE_MBX_TX_NIC_PROD2_LO 0x0394 476#define BGE_MBX_TX_NIC_PROD3_HI 0x0398 477#define BGE_MBX_TX_NIC_PROD3_LO 0x039C 478#define BGE_MBX_TX_NIC_PROD4_HI 0x03A0 479#define BGE_MBX_TX_NIC_PROD4_LO 0x03A4 480#define BGE_MBX_TX_NIC_PROD5_HI 0x03A8 481#define BGE_MBX_TX_NIC_PROD5_LO 0x03AC 482#define BGE_MBX_TX_NIC_PROD6_HI 0x03B0 483#define BGE_MBX_TX_NIC_PROD6_LO 0x03B4 484#define BGE_MBX_TX_NIC_PROD7_HI 0x03B8 485#define BGE_MBX_TX_NIC_PROD7_LO 0x03BC 486#define BGE_MBX_TX_NIC_PROD8_HI 0x03C0 487#define BGE_MBX_TX_NIC_PROD8_LO 0x03C4 488#define BGE_MBX_TX_NIC_PROD9_HI 0x03C8 489#define BGE_MBX_TX_NIC_PROD9_LO 0x03CC 490#define BGE_MBX_TX_NIC_PROD10_HI 0x03D0 491#define BGE_MBX_TX_NIC_PROD10_LO 0x03D4 492#define BGE_MBX_TX_NIC_PROD11_HI 0x03D8 493#define BGE_MBX_TX_NIC_PROD11_LO 0x03DC 494#define BGE_MBX_TX_NIC_PROD12_HI 0x03E0 495#define BGE_MBX_TX_NIC_PROD12_LO 0x03E4 496#define BGE_MBX_TX_NIC_PROD13_HI 0x03E8 497#define BGE_MBX_TX_NIC_PROD13_LO 0x03EC 498#define BGE_MBX_TX_NIC_PROD14_HI 0x03F0 499#define BGE_MBX_TX_NIC_PROD14_LO 0x03F4 500#define BGE_MBX_TX_NIC_PROD15_HI 0x03F8 501#define BGE_MBX_TX_NIC_PROD15_LO 0x03FC 502* 503#define BGE_TX_RINGS_MAX 4 504#define BGE_TX_RINGS_EXTSSRAM_MAX 16 505#define BGE_RX_RINGS_MAX 16 506 507/* Ethernet MAC control registers / 508#define BGE_MAC_MODE 0x0400 509#define BGE_MAC_STS 0x0404 510#define BGE_MAC_EVT_ENB 0x0408 511#define BGE_MAC_LED_CTL 0x040C 512#define BGE_MAC_ADDR1_LO 0x0410 513#define BGE_MAC_ADDR1_HI 0x0414 514#define BGE_MAC_ADDR2_LO 0x0418 515#define BGE_MAC_ADDR2_HI 0x041C 516#define BGE_MAC_ADDR3_LO 0x0420 517#define BGE_MAC_ADDR3_HI 0x0424 518#define BGE_MAC_ADDR4_LO 0x0428 519#define BGE_MAC_ADDR4_HI 0x042C 520#define BGE_WOL_PATPTR 0x0430 521#define BGE_WOL_PATCFG 0x0434 522#define BGE_TX_RANDOM_BACKOFF 0x0438 523#define BGE_RX_MTU 0x043C 524#define BGE_GBIT_PCS_TEST 0x0440 525#define BGE_TX_TBI_AUTONEG 0x0444 526#define BGE_RX_TBI_AUTONEG 0x0448 527#define BGE_MI_COMM 0x044C 528#define BGE_MI_STS 0x0450 529#define BGE_MI_MODE 0x0454 530#define BGE_AUTOPOLL_STS 0x0458 531#define BGE_TX_MODE 0x045C 532#define BGE_TX_STS 0x0460 533#define BGE_TX_LENGTHS 0x0464 534#define BGE_RX_MODE 0x0468 535#define BGE_RX_STS 0x046C 536#define BGE_MAR0 0x0470 537#define BGE_MAR1 0x0474 538#define BGE_MAR2 0x0478 539#define BGE_MAR3 0x047C 540#define BGE_RX_BD_RULES_CTL0 0x0480 541#define BGE_RX_BD_RULES_MASKVAL0 0x0484 542#define BGE_RX_BD_RULES_CTL1 0x0488 543#define BGE_RX_BD_RULES_MASKVAL1 0x048C 544#define BGE_RX_BD_RULES_CTL2 0x0490 545#define BGE_RX_BD_RULES_MASKVAL2 0x0494 546#define BGE_RX_BD_RULES_CTL3 0x0498 547#define BGE_RX_BD_RULES_MASKVAL3 0x049C 548#define BGE_RX_BD_RULES_CTL4 0x04A0 549#define BGE_RX_BD_RULES_MASKVAL4 0x04A4 550#define BGE_RX_BD_RULES_CTL5 0x04A8 551#define BGE_RX_BD_RULES_MASKVAL5 0x04AC 552#define BGE_RX_BD_RULES_CTL6 0x04B0 553#define BGE_RX_BD_RULES_MASKVAL6 0x04B4 554#define BGE_RX_BD_RULES_CTL7 0x04B8 555#define BGE_RX_BD_RULES_MASKVAL7 0x04BC 556#define BGE_RX_BD_RULES_CTL8 0x04C0 557#define BGE_RX_BD_RULES_MASKVAL8 0x04C4 558#define BGE_RX_BD_RULES_CTL9 0x04C8 559#define BGE_RX_BD_RULES_MASKVAL9 0x04CC 560#define BGE_RX_BD_RULES_CTL10 0x04D0 561#define BGE_RX_BD_RULES_MASKVAL10 0x04D4 562#define BGE_RX_BD_RULES_CTL11 0x04D8 563#define BGE_RX_BD_RULES_MASKVAL11 0x04DC 564#define BGE_RX_BD_RULES_CTL12 0x04E0 565#define BGE_RX_BD_RULES_MASKVAL12 0x04E4 566#define BGE_RX_BD_RULES_CTL13 0x04E8 567#define BGE_RX_BD_RULES_MASKVAL13 0x04EC 568#define BGE_RX_BD_RULES_CTL14 0x04F0 569#define BGE_RX_BD_RULES_MASKVAL14 0x04F4 570#define BGE_RX_BD_RULES_CTL15 0x04F8 571#define BGE_RX_BD_RULES_MASKVAL15 0x04FC 572#define BGE_RX_RULES_CFG 0x0500 573#define BGE_SERDES_CFG 0x0590 574#define BGE_SERDES_STS 0x0594 575#define BGE_SGDIG_CFG 0x05B0 576*#define BGE_SGDIG_STS 0x05B4
577#define BGE_RX_STATS 0x0800 578#define BGE_TX_STATS 0x0880	577#define BGE_MAC_STATS 0x0800
579 580/* Ethernet MAC Mode register / 581#define BGE_MACMODE_RESET 0x00000001 582#define BGE_MACMODE_HALF_DUPLEX 0x00000002 583#define BGE_MACMODE_PORTMODE 0x0000000C 584#define BGE_MACMODE_LOOPBACK 0x00000010 585#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 586#define BGE_MACMODE_TX_BURST_ENB 0x00000100 587#define BGE_MACMODE_MAX_DEFER 0x00000200 588#define BGE_MACMODE_LINK_POLARITY 0x00000400 589#define BGE_MACMODE_RX_STATS_ENB 0x00000800 590#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 591#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 592#define BGE_MACMODE_TX_STATS_ENB 0x00004000 593#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 594#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 595#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 596#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 597#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 598#define BGE_MACMODE_MIP_ENB 0x00100000 599#define BGE_MACMODE_TXDMA_ENB 0x00200000 600#define BGE_MACMODE_RXDMA_ENB 0x00400000 601#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 602* 603#define BGE_PORTMODE_NONE 0x00000000 604#define BGE_PORTMODE_MII 0x00000004 605#define BGE_PORTMODE_GMII 0x00000008 606#define BGE_PORTMODE_TBI 0x0000000C 607 608/* MAC Status register / 609#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 610#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 611#define BGE_MACSTAT_RX_CFG 0x00000004 612#define BGE_MACSTAT_CFG_CHANGED 0x00000008 613#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 614#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 615#define BGE_MACSTAT_LINK_CHANGED 0x00001000 616#define BGE_MACSTAT_MI_COMPLETE 0x00400000 617#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 618#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 619#define BGE_MACSTAT_ODI_ERROR 0x02000000 620#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 621#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 622* 623/* MAC Event Enable Register / 624#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 625#define BGE_EVTENB_LINK_CHANGED 0x00001000 626#define BGE_EVTENB_MI_COMPLETE 0x00400000 627#define BGE_EVTENB_MI_INTERRUPT 0x00800000 628#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 629#define BGE_EVTENB_ODI_ERROR 0x02000000 630#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 631#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 632* 633/* LED Control Register / 634#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 635#define BGE_LEDCTL_1000MBPS_LED 0x00000002 636#define BGE_LEDCTL_100MBPS_LED 0x00000004 637#define BGE_LEDCTL_10MBPS_LED 0x00000008 638#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 639#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 640#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 641#define BGE_LEDCTL_1000MBPS_STS 0x00000080 642#define BGE_LEDCTL_100MBPS_STS 0x00000100 643#define BGE_LEDCTL_10MBPS_STS 0x00000200 644#define BGE_LEDCTL_TRADLED_STS 0x00000400 645#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 646#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 647* 648/* TX backoff seed register / 649#define BGE_TX_BACKOFF_SEED_MASK 0x3F 650* 651/* Autopoll status register / 652#define BGE_AUTOPOLLSTS_ERROR 0x00000001 653* 654/* Transmit MAC mode register / 655#define BGE_TXMODE_RESET 0x00000001 656#define BGE_TXMODE_ENABLE 0x00000002 657#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 658#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 659#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 660* 661/* Transmit MAC status register / 662#define BGE_TXSTAT_RX_XOFFED 0x00000001 663#define BGE_TXSTAT_SENT_XOFF 0x00000002 664#define BGE_TXSTAT_SENT_XON 0x00000004 665#define BGE_TXSTAT_LINK_UP 0x00000008 666#define BGE_TXSTAT_ODI_UFLOW 0x00000010 667#define BGE_TXSTAT_ODI_OFLOW 0x00000020 668* 669/* Transmit MAC lengths register / 670#define BGE_TXLEN_SLOTTIME 0x000000FF 671#define BGE_TXLEN_IPG 0x00000F00 672#define BGE_TXLEN_CRS 0x00003000 673* 674/* Receive MAC mode register / 675#define BGE_RXMODE_RESET 0x00000001 676#define BGE_RXMODE_ENABLE 0x00000002 677#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 678#define BGE_RXMODE_RX_GIANTS 0x00000020 679#define BGE_RXMODE_RX_RUNTS 0x00000040 680#define BGE_RXMODE_8022_LENCHECK 0x00000080 681#define BGE_RXMODE_RX_PROMISC 0x00000100 682#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 683#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 684* 685/* Receive MAC status register / 686#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 687#define BGE_RXSTAT_RCVD_XOFF 0x00000002 688#define BGE_RXSTAT_RCVD_XON 0x00000004 689* 690/* Receive Rules Control register / 691#define BGE_RXRULECTL_OFFSET 0x000000FF 692#define BGE_RXRULECTL_CLASS 0x00001F00 693#define BGE_RXRULECTL_HDRTYPE 0x0000E000 694#define BGE_RXRULECTL_COMPARE_OP 0x00030000 695#define BGE_RXRULECTL_MAP 0x01000000 696#define BGE_RXRULECTL_DISCARD 0x02000000 697#define BGE_RXRULECTL_MASK 0x04000000 698#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 699#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 700#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 701#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 702* 703/* Receive Rules Mask register / 704#define BGE_RXRULEMASK_VALUE 0x0000FFFF 705#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 706* 707/* SERDES configuration register / 708#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 709#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 710#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 711#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 712#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 713#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 714#define BGE_SERDESCFG_TXMODE 0x00001000 715#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 716#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 717#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 718#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 719#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 720#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 721#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 722#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 723#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 724* 725/* SERDES status register / 726#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 727#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 728* 729/* SGDIG config (not documented) / 730#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 731#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 732#define BGE_SGDIGCFG_SEND 0x40000000 733#define BGE_SGDIGCFG_AUTO 0x80000000 734* 735/* SGDIG status (not documented) / 736#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 737#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 738#define BGE_SGDIGSTS_DONE 0x00000002 739* 740 741/* MI communication register / 742#define BGE_MICOMM_DATA 0x0000FFFF 743#define BGE_MICOMM_REG 0x001F0000 744#define BGE_MICOMM_PHY 0x03E00000 745#define BGE_MICOMM_CMD 0x0C000000 746#define BGE_MICOMM_READFAIL 0x10000000 747#define BGE_MICOMM_BUSY 0x20000000 748* 749#define BGE_MIREG(x) ((x & 0x1F) << 16) 750#define BGE_MIPHY(x) ((x & 0x1F) << 21) 751#define BGE_MICMD_WRITE 0x04000000 752#define BGE_MICMD_READ 0x08000000 753 754/* MI status register / 755#define BGE_MISTS_LINK 0x00000001 756#define BGE_MISTS_10MBPS 0x00000002 757* 758#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 759#define BGE_MIMODE_AUTOPOLL 0x00000010 760#define BGE_MIMODE_CLKCNT 0x001F0000 761 762 763/* 764 * Send data initiator control registers. 765 / 766#define BGE_SDI_MODE 0x0C00 767#define BGE_SDI_STATUS 0x0C04 768#define BGE_SDI_STATS_CTL 0x0C08 769#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 770#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 771#define BGE_LOCSTATS_COS0 0x0C80 772#define BGE_LOCSTATS_COS1 0x0C84 773#define BGE_LOCSTATS_COS2 0x0C88 774#define BGE_LOCSTATS_COS3 0x0C8C 775#define BGE_LOCSTATS_COS4 0x0C90 776#define BGE_LOCSTATS_COS5 0x0C84 777#define BGE_LOCSTATS_COS6 0x0C98 778#define BGE_LOCSTATS_COS7 0x0C9C 779#define BGE_LOCSTATS_COS8 0x0CA0 780#define BGE_LOCSTATS_COS9 0x0CA4 781#define BGE_LOCSTATS_COS10 0x0CA8 782#define BGE_LOCSTATS_COS11 0x0CAC 783#define BGE_LOCSTATS_COS12 0x0CB0 784#define BGE_LOCSTATS_COS13 0x0CB4 785#define BGE_LOCSTATS_COS14 0x0CB8 786#define BGE_LOCSTATS_COS15 0x0CBC 787#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 788#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 789#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 790#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 791#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 792#define BGE_LOCSTATS_IRQS 0x0CD4 793#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 794#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 795* 796/* Send Data Initiator mode register / 797#define BGE_SDIMODE_RESET 0x00000001 798#define BGE_SDIMODE_ENABLE 0x00000002 799#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 800* 801/* Send Data Initiator stats register / 802#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 803* 804/* Send Data Initiator stats control register / 805#define BGE_SDISTATSCTL_ENABLE 0x00000001 806#define BGE_SDISTATSCTL_FASTER 0x00000002 807#define BGE_SDISTATSCTL_CLEAR 0x00000004 808#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 809#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 810* 811/* 812 * Send Data Completion Control registers 813 / 814#define BGE_SDC_MODE 0x1000 815#define BGE_SDC_STATUS 0x1004 816* 817/* Send Data completion mode register / 818#define BGE_SDCMODE_RESET 0x00000001 819#define BGE_SDCMODE_ENABLE 0x00000002 820#define BGE_SDCMODE_ATTN 0x00000004 821* 822/* Send Data completion status register / 823#define BGE_SDCSTAT_ATTN 0x00000004 824* 825/* 826 * Send BD Ring Selector Control registers 827 / 828#define BGE_SRS_MODE 0x1400 829#define BGE_SRS_STATUS 0x1404 830#define BGE_SRS_HWDIAG 0x1408 831#define BGE_SRS_LOC_NIC_CONS0 0x1440 832#define BGE_SRS_LOC_NIC_CONS1 0x1444 833#define BGE_SRS_LOC_NIC_CONS2 0x1448 834#define BGE_SRS_LOC_NIC_CONS3 0x144C 835#define BGE_SRS_LOC_NIC_CONS4 0x1450 836#define BGE_SRS_LOC_NIC_CONS5 0x1454 837#define BGE_SRS_LOC_NIC_CONS6 0x1458 838#define BGE_SRS_LOC_NIC_CONS7 0x145C 839#define BGE_SRS_LOC_NIC_CONS8 0x1460 840#define BGE_SRS_LOC_NIC_CONS9 0x1464 841#define BGE_SRS_LOC_NIC_CONS10 0x1468 842#define BGE_SRS_LOC_NIC_CONS11 0x146C 843#define BGE_SRS_LOC_NIC_CONS12 0x1470 844#define BGE_SRS_LOC_NIC_CONS13 0x1474 845#define BGE_SRS_LOC_NIC_CONS14 0x1478 846#define BGE_SRS_LOC_NIC_CONS15 0x147C 847* 848/* Send BD Ring Selector Mode register / 849#define BGE_SRSMODE_RESET 0x00000001 850#define BGE_SRSMODE_ENABLE 0x00000002 851#define BGE_SRSMODE_ATTN 0x00000004 852* 853/* Send BD Ring Selector Status register / 854#define BGE_SRSSTAT_ERROR 0x00000004 855* 856/* Send BD Ring Selector HW Diagnostics register / 857#define BGE_SRSHWDIAG_STATE 0x0000000F 858#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 859#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 860#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 861* 862/* 863 * Send BD Initiator Selector Control registers 864 / 865#define BGE_SBDI_MODE 0x1800 866#define BGE_SBDI_STATUS 0x1804 867#define BGE_SBDI_LOC_NIC_PROD0 0x1808 868#define BGE_SBDI_LOC_NIC_PROD1 0x180C 869#define BGE_SBDI_LOC_NIC_PROD2 0x1810 870#define BGE_SBDI_LOC_NIC_PROD3 0x1814 871#define BGE_SBDI_LOC_NIC_PROD4 0x1818 872#define BGE_SBDI_LOC_NIC_PROD5 0x181C 873#define BGE_SBDI_LOC_NIC_PROD6 0x1820 874#define BGE_SBDI_LOC_NIC_PROD7 0x1824 875#define BGE_SBDI_LOC_NIC_PROD8 0x1828 876#define BGE_SBDI_LOC_NIC_PROD9 0x182C 877#define BGE_SBDI_LOC_NIC_PROD10 0x1830 878#define BGE_SBDI_LOC_NIC_PROD11 0x1834 879#define BGE_SBDI_LOC_NIC_PROD12 0x1838 880#define BGE_SBDI_LOC_NIC_PROD13 0x183C 881#define BGE_SBDI_LOC_NIC_PROD14 0x1840 882#define BGE_SBDI_LOC_NIC_PROD15 0x1844 883* 884/* Send BD Initiator Mode register / 885#define BGE_SBDIMODE_RESET 0x00000001 886#define BGE_SBDIMODE_ENABLE 0x00000002 887#define BGE_SBDIMODE_ATTN 0x00000004 888* 889/* Send BD Initiator Status register / 890#define BGE_SBDISTAT_ERROR 0x00000004 891* 892/* 893 * Send BD Completion Control registers 894 / 895#define BGE_SBDC_MODE 0x1C00 896#define BGE_SBDC_STATUS 0x1C04 897* 898/* Send BD Completion Control Mode register / 899#define BGE_SBDCMODE_RESET 0x00000001 900#define BGE_SBDCMODE_ENABLE 0x00000002 901#define BGE_SBDCMODE_ATTN 0x00000004 902* 903/* Send BD Completion Control Status register / 904#define BGE_SBDCSTAT_ATTN 0x00000004 905* 906/* 907 * Receive List Placement Control registers 908 / 909#define BGE_RXLP_MODE 0x2000 910#define BGE_RXLP_STATUS 0x2004 911#define BGE_RXLP_SEL_LIST_LOCK 0x2008 912#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 913#define BGE_RXLP_CFG 0x2010 914#define BGE_RXLP_STATS_CTL 0x2014 915#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 916#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 917#define BGE_RXLP_HEAD0 0x2100 918#define BGE_RXLP_TAIL0 0x2104 919#define BGE_RXLP_COUNT0 0x2108 920#define BGE_RXLP_HEAD1 0x2110 921#define BGE_RXLP_TAIL1 0x2114 922#define BGE_RXLP_COUNT1 0x2118 923#define BGE_RXLP_HEAD2 0x2120 924#define BGE_RXLP_TAIL2 0x2124 925#define BGE_RXLP_COUNT2 0x2128 926#define BGE_RXLP_HEAD3 0x2130 927#define BGE_RXLP_TAIL3 0x2134 928#define BGE_RXLP_COUNT3 0x2138 929#define BGE_RXLP_HEAD4 0x2140 930#define BGE_RXLP_TAIL4 0x2144 931#define BGE_RXLP_COUNT4 0x2148 932#define BGE_RXLP_HEAD5 0x2150 933#define BGE_RXLP_TAIL5 0x2154 934#define BGE_RXLP_COUNT5 0x2158 935#define BGE_RXLP_HEAD6 0x2160 936#define BGE_RXLP_TAIL6 0x2164 937#define BGE_RXLP_COUNT6 0x2168 938#define BGE_RXLP_HEAD7 0x2170 939#define BGE_RXLP_TAIL7 0x2174 940#define BGE_RXLP_COUNT7 0x2178 941#define BGE_RXLP_HEAD8 0x2180 942#define BGE_RXLP_TAIL8 0x2184 943#define BGE_RXLP_COUNT8 0x2188 944#define BGE_RXLP_HEAD9 0x2190 945#define BGE_RXLP_TAIL9 0x2194 946#define BGE_RXLP_COUNT9 0x2198 947#define BGE_RXLP_HEAD10 0x21A0 948#define BGE_RXLP_TAIL10 0x21A4 949#define BGE_RXLP_COUNT10 0x21A8 950#define BGE_RXLP_HEAD11 0x21B0 951#define BGE_RXLP_TAIL11 0x21B4 952#define BGE_RXLP_COUNT11 0x21B8 953#define BGE_RXLP_HEAD12 0x21C0 954#define BGE_RXLP_TAIL12 0x21C4 955#define BGE_RXLP_COUNT12 0x21C8 956#define BGE_RXLP_HEAD13 0x21D0 957#define BGE_RXLP_TAIL13 0x21D4 958#define BGE_RXLP_COUNT13 0x21D8 959#define BGE_RXLP_HEAD14 0x21E0 960#define BGE_RXLP_TAIL14 0x21E4 961#define BGE_RXLP_COUNT14 0x21E8 962#define BGE_RXLP_HEAD15 0x21F0 963#define BGE_RXLP_TAIL15 0x21F4 964#define BGE_RXLP_COUNT15 0x21F8 965#define BGE_RXLP_LOCSTAT_COS0 0x2200 966#define BGE_RXLP_LOCSTAT_COS1 0x2204 967#define BGE_RXLP_LOCSTAT_COS2 0x2208 968#define BGE_RXLP_LOCSTAT_COS3 0x220C 969#define BGE_RXLP_LOCSTAT_COS4 0x2210 970#define BGE_RXLP_LOCSTAT_COS5 0x2214 971#define BGE_RXLP_LOCSTAT_COS6 0x2218 972#define BGE_RXLP_LOCSTAT_COS7 0x221C 973#define BGE_RXLP_LOCSTAT_COS8 0x2220 974#define BGE_RXLP_LOCSTAT_COS9 0x2224 975#define BGE_RXLP_LOCSTAT_COS10 0x2228 976#define BGE_RXLP_LOCSTAT_COS11 0x222C 977#define BGE_RXLP_LOCSTAT_COS12 0x2230 978#define BGE_RXLP_LOCSTAT_COS13 0x2234 979#define BGE_RXLP_LOCSTAT_COS14 0x2238 980#define BGE_RXLP_LOCSTAT_COS15 0x223C 981#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 982#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 983#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 984#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 985#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 986#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 987#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 988* 989 990/* Receive List Placement mode register / 991#define BGE_RXLPMODE_RESET 0x00000001 992#define BGE_RXLPMODE_ENABLE 0x00000002 993#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 994#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 995#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 996* 997/* Receive List Placement Status register / 998#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 999#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 1000#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1001* 1002/* 1003 * Receive Data and Receive BD Initiator Control Registers 1004 / 1005#define BGE_RDBDI_MODE 0x2400 1006#define BGE_RDBDI_STATUS 0x2404 1007#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1008#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1009#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1010#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1011#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1012#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1013#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1014#define BGE_RX_STD_RCB_NICADDR 0x245C 1015#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1016#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1017#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1018#define BGE_RX_MINI_RCB_NICADDR 0x246C 1019#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1020#define BGE_RDBDI_STD_RX_CONS 0x2474 1021#define BGE_RDBDI_MINI_RX_CONS 0x2478 1022#define BGE_RDBDI_RETURN_PROD0 0x2480 1023#define BGE_RDBDI_RETURN_PROD1 0x2484 1024#define BGE_RDBDI_RETURN_PROD2 0x2488 1025#define BGE_RDBDI_RETURN_PROD3 0x248C 1026#define BGE_RDBDI_RETURN_PROD4 0x2490 1027#define BGE_RDBDI_RETURN_PROD5 0x2494 1028#define BGE_RDBDI_RETURN_PROD6 0x2498 1029#define BGE_RDBDI_RETURN_PROD7 0x249C 1030#define BGE_RDBDI_RETURN_PROD8 0x24A0 1031#define BGE_RDBDI_RETURN_PROD9 0x24A4 1032#define BGE_RDBDI_RETURN_PROD10 0x24A8 1033#define BGE_RDBDI_RETURN_PROD11 0x24AC 1034#define BGE_RDBDI_RETURN_PROD12 0x24B0 1035#define BGE_RDBDI_RETURN_PROD13 0x24B4 1036#define BGE_RDBDI_RETURN_PROD14 0x24B8 1037#define BGE_RDBDI_RETURN_PROD15 0x24BC 1038#define BGE_RDBDI_HWDIAG 0x24C0 1039* 1040 1041/* Receive Data and Receive BD Initiator Mode register / 1042#define BGE_RDBDIMODE_RESET 0x00000001 1043#define BGE_RDBDIMODE_ENABLE 0x00000002 1044#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1045#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1046#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1047* 1048/* Receive Data and Receive BD Initiator Status register / 1049#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1050#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1051#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1052* 1053 1054/* 1055 * Receive Data Completion Control registers 1056 / 1057#define BGE_RDC_MODE 0x2800 1058* 1059/* Receive Data Completion Mode register / 1060#define BGE_RDCMODE_RESET 0x00000001 1061#define BGE_RDCMODE_ENABLE 0x00000002 1062#define BGE_RDCMODE_ATTN 0x00000004 1063* 1064/* 1065 * Receive BD Initiator Control registers 1066 / 1067#define BGE_RBDI_MODE 0x2C00 1068#define BGE_RBDI_STATUS 0x2C04 1069#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1070#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1071#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1072#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1073#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1074#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1075* 1076/* Receive BD Initiator Mode register / 1077#define BGE_RBDIMODE_RESET 0x00000001 1078#define BGE_RBDIMODE_ENABLE 0x00000002 1079#define BGE_RBDIMODE_ATTN 0x00000004 1080* 1081/* Receive BD Initiator Status register / 1082#define BGE_RBDISTAT_ATTN 0x00000004 1083* 1084/* 1085 * Receive BD Completion Control registers 1086 / 1087#define BGE_RBDC_MODE 0x3000 1088#define BGE_RBDC_STATUS 0x3004 1089#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1090#define BGE_RBDC_STD_BD_PROD 0x300C 1091#define BGE_RBDC_MINI_BD_PROD 0x3010 1092* 1093/* Receive BD completion mode register / 1094#define BGE_RBDCMODE_RESET 0x00000001 1095#define BGE_RBDCMODE_ENABLE 0x00000002 1096#define BGE_RBDCMODE_ATTN 0x00000004 1097* 1098/* Receive BD completion status register / 1099#define BGE_RBDCSTAT_ERROR 0x00000004 1100* 1101/* 1102 * Receive List Selector Control registers 1103 / 1104#define BGE_RXLS_MODE 0x3400 1105#define BGE_RXLS_STATUS 0x3404 1106* 1107/* Receive List Selector Mode register / 1108#define BGE_RXLSMODE_RESET 0x00000001 1109#define BGE_RXLSMODE_ENABLE 0x00000002 1110#define BGE_RXLSMODE_ATTN 0x00000004 1111* 1112/* Receive List Selector Status register / 1113#define BGE_RXLSSTAT_ERROR 0x00000004 1114* 1115/* 1116 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1117 / 1118#define BGE_MBCF_MODE 0x3800 1119#define BGE_MBCF_STATUS 0x3804 1120* 1121/* Mbuf Cluster Free mode register / 1122#define BGE_MBCFMODE_RESET 0x00000001 1123#define BGE_MBCFMODE_ENABLE 0x00000002 1124#define BGE_MBCFMODE_ATTN 0x00000004 1125* 1126/* Mbuf Cluster Free status register / 1127#define BGE_MBCFSTAT_ERROR 0x00000004 1128* 1129/* 1130 * Host Coalescing Control registers 1131 / 1132#define BGE_HCC_MODE 0x3C00 1133#define BGE_HCC_STATUS 0x3C04 1134#define BGE_HCC_RX_COAL_TICKS 0x3C08 1135#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1136#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1137#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1138#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1139#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1140#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1141#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1142#define BGE_HCC_STATS_TICKS 0x3C28 1143#define BGE_HCC_STATS_ADDR_HI 0x3C30 1144#define BGE_HCC_STATS_ADDR_LO 0x3C34 1145#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1146#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1147#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1148#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1149#define BGE_FLOW_ATTN 0x3C48 1150#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1151#define BGE_HCC_STD_BD_CONS 0x3C54 1152#define BGE_HCC_MINI_BD_CONS 0x3C58 1153#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1154#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1155#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1156#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1157#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1158#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1159#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1160#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1161#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1162#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1163#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1164#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1165#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1166#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1167#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1168#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1169#define BGE_HCC_TX_BD_CONS0 0x3CC0 1170#define BGE_HCC_TX_BD_CONS1 0x3CC4 1171#define BGE_HCC_TX_BD_CONS2 0x3CC8 1172#define BGE_HCC_TX_BD_CONS3 0x3CCC 1173#define BGE_HCC_TX_BD_CONS4 0x3CD0 1174#define BGE_HCC_TX_BD_CONS5 0x3CD4 1175#define BGE_HCC_TX_BD_CONS6 0x3CD8 1176#define BGE_HCC_TX_BD_CONS7 0x3CDC 1177#define BGE_HCC_TX_BD_CONS8 0x3CE0 1178#define BGE_HCC_TX_BD_CONS9 0x3CE4 1179#define BGE_HCC_TX_BD_CONS10 0x3CE8 1180#define BGE_HCC_TX_BD_CONS11 0x3CEC 1181#define BGE_HCC_TX_BD_CONS12 0x3CF0 1182#define BGE_HCC_TX_BD_CONS13 0x3CF4 1183#define BGE_HCC_TX_BD_CONS14 0x3CF8 1184#define BGE_HCC_TX_BD_CONS15 0x3CFC 1185* 1186 1187/* Host coalescing mode register / 1188#define BGE_HCCMODE_RESET 0x00000001 1189#define BGE_HCCMODE_ENABLE 0x00000002 1190#define BGE_HCCMODE_ATTN 0x00000004 1191#define BGE_HCCMODE_COAL_NOW 0x00000008 1192#define BGE_HCCMODE_MSI_BITS 0x00000070 1193#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1194* 1195#define BGE_STATBLKSZ_FULL 0x00000000 1196#define BGE_STATBLKSZ_64BYTE 0x00000080 1197#define BGE_STATBLKSZ_32BYTE 0x00000100 1198 1199/* Host coalescing status register / 1200#define BGE_HCCSTAT_ERROR 0x00000004 1201* 1202/* Flow attention register / 1203#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1204#define BGE_FLOWATTN_MEMARB 0x00000080 1205#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1206#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1207#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1208#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1209#define BGE_FLOWATTN_RDBDI 0x00080000 1210#define BGE_FLOWATTN_RXLS 0x00100000 1211#define BGE_FLOWATTN_RXLP 0x00200000 1212#define BGE_FLOWATTN_RBDC 0x00400000 1213#define BGE_FLOWATTN_RBDI 0x00800000 1214#define BGE_FLOWATTN_SDC 0x08000000 1215#define BGE_FLOWATTN_SDI 0x10000000 1216#define BGE_FLOWATTN_SRS 0x20000000 1217#define BGE_FLOWATTN_SBDC 0x40000000 1218#define BGE_FLOWATTN_SBDI 0x80000000 1219* 1220/* 1221 * Memory arbiter registers 1222 / 1223#define BGE_MARB_MODE 0x4000 1224#define BGE_MARB_STATUS 0x4004 1225#define BGE_MARB_TRAPADDR_HI 0x4008 1226#define BGE_MARB_TRAPADDR_LO 0x400C 1227* 1228/* Memory arbiter mode register / 1229#define BGE_MARBMODE_RESET 0x00000001 1230#define BGE_MARBMODE_ENABLE 0x00000002 1231#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1232#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1233#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1234#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1235#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1236#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1237#define BGE_MARBMODE_PCI_TRAP 0x00000100 1238#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1239#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1240#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1241#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1242#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1243#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1244#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1245#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1246#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1247#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1248#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1249#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1250#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1251#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1252#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1253#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1254#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1255* 1256/* Memory arbiter status register / 1257#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1258#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1259#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1260#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1261#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1262#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1263#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1264#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1265#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1266#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1267#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1268#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1269#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1270#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1271#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1272#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1273#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1274#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1275#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1276#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1277#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1278#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1279#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1280#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1281* 1282/* 1283 * Buffer manager control registers 1284 / 1285#define BGE_BMAN_MODE 0x4400 1286#define BGE_BMAN_STATUS 0x4404 1287#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1288#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1289#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1290#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1291#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1292#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1293#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1294#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1295#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1296#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1297#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1298#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1299#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1300#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1301#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1302#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1303#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1304#define BGE_BMAN_HWDIAG_1 0x444C 1305#define BGE_BMAN_HWDIAG_2 0x4450 1306#define BGE_BMAN_HWDIAG_3 0x4454 1307* 1308/* Buffer manager mode register / 1309#define BGE_BMANMODE_RESET 0x00000001 1310#define BGE_BMANMODE_ENABLE 0x00000002 1311#define BGE_BMANMODE_ATTN 0x00000004 1312#define BGE_BMANMODE_TESTMODE 0x00000008 1313#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1314* 1315/* Buffer manager status register / 1316#define BGE_BMANSTAT_ERRO 0x00000004 1317#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1318* 1319 1320/* 1321 * Read DMA Control registers 1322 / 1323#define BGE_RDMA_MODE 0x4800 1324#define BGE_RDMA_STATUS 0x4804 1325* 1326/* Read DMA mode register / 1327#define BGE_RDMAMODE_RESET 0x00000001 1328#define BGE_RDMAMODE_ENABLE 0x00000002 1329#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1330#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1331#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1332#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1333#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1334#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1335#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1336#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1337#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1338* 1339/* Read DMA status register / 1340#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1341#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1342#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1343#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1344#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1345#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1346#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1347#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1348* 1349/* 1350 * Write DMA control registers 1351 / 1352#define BGE_WDMA_MODE 0x4C00 1353#define BGE_WDMA_STATUS 0x4C04 1354* 1355/* Write DMA mode register / 1356#define BGE_WDMAMODE_RESET 0x00000001 1357#define BGE_WDMAMODE_ENABLE 0x00000002 1358#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1359#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1360#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1361#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1362#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1363#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1364#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1365#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1366#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1367* 1368/* Write DMA status register / 1369#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1370#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1371#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1372#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1373#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1374#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1375#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1376#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1377* 1378 1379/* 1380 * RX CPU registers 1381 / 1382#define BGE_RXCPU_MODE 0x5000 1383#define BGE_RXCPU_STATUS 0x5004 1384#define BGE_RXCPU_PC 0x501C 1385* 1386/* RX CPU mode register / 1387#define BGE_RXCPUMODE_RESET 0x00000001 1388#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1389#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1390#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1391#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1392#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1393#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1394#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1395#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1396#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1397#define BGE_RXCPUMODE_HALTCPU 0x00000400 1398#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1399#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1400#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1401* 1402/* RX CPU status register / 1403#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1404#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1405#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1406#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1407#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1408#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1409#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1410#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1411#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1412#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1413#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1414#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1415#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1416#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1417#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1418#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1419#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1420* 1421 1422/* 1423 * TX CPU registers 1424 / 1425#define BGE_TXCPU_MODE 0x5400 1426#define BGE_TXCPU_STATUS 0x5404 1427#define BGE_TXCPU_PC 0x541C 1428* 1429/* TX CPU mode register / 1430#define BGE_TXCPUMODE_RESET 0x00000001 1431#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1432#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1433#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1434#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1435#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1436#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1437#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1438#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1439#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1440#define BGE_TXCPUMODE_HALTCPU 0x00000400 1441#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1442#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1443* 1444/* TX CPU status register / 1445#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1446#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1447#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1448#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1449#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1450#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1451#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1452#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1453#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1454#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1455#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1456#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1457#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1458#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1459#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1460#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1461#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1462* 1463 1464/* 1465 * Low priority mailbox registers 1466 / 1467#define BGE_LPMBX_IRQ0_HI 0x5800 1468#define BGE_LPMBX_IRQ0_LO 0x5804 1469#define BGE_LPMBX_IRQ1_HI 0x5808 1470#define BGE_LPMBX_IRQ1_LO 0x580C 1471#define BGE_LPMBX_IRQ2_HI 0x5810 1472#define BGE_LPMBX_IRQ2_LO 0x5814 1473#define BGE_LPMBX_IRQ3_HI 0x5818 1474#define BGE_LPMBX_IRQ3_LO 0x581C 1475#define BGE_LPMBX_GEN0_HI 0x5820 1476#define BGE_LPMBX_GEN0_LO 0x5824 1477#define BGE_LPMBX_GEN1_HI 0x5828 1478#define BGE_LPMBX_GEN1_LO 0x582C 1479#define BGE_LPMBX_GEN2_HI 0x5830 1480#define BGE_LPMBX_GEN2_LO 0x5834 1481#define BGE_LPMBX_GEN3_HI 0x5828 1482#define BGE_LPMBX_GEN3_LO 0x582C 1483#define BGE_LPMBX_GEN4_HI 0x5840 1484#define BGE_LPMBX_GEN4_LO 0x5844 1485#define BGE_LPMBX_GEN5_HI 0x5848 1486#define BGE_LPMBX_GEN5_LO 0x584C 1487#define BGE_LPMBX_GEN6_HI 0x5850 1488#define BGE_LPMBX_GEN6_LO 0x5854 1489#define BGE_LPMBX_GEN7_HI 0x5858 1490#define BGE_LPMBX_GEN7_LO 0x585C 1491#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1492#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1493#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1494#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1495#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1496#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1497#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1498#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1499#define BGE_LPMBX_RX_CONS0_HI 0x5880 1500#define BGE_LPMBX_RX_CONS0_LO 0x5884 1501#define BGE_LPMBX_RX_CONS1_HI 0x5888 1502#define BGE_LPMBX_RX_CONS1_LO 0x588C 1503#define BGE_LPMBX_RX_CONS2_HI 0x5890 1504#define BGE_LPMBX_RX_CONS2_LO 0x5894 1505#define BGE_LPMBX_RX_CONS3_HI 0x5898 1506#define BGE_LPMBX_RX_CONS3_LO 0x589C 1507#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1508#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1509#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1510#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1511#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1512#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1513#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1514#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1515#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1516#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1517#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1518#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1519#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1520#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1521#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1522#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1523#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1524#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1525#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1526#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1527#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1528#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1529#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1530#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1531#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1532#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1533#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1534#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1535#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1536#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1537#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1538#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1539#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1540#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1541#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1542#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1543#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1544#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1545#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1546#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1547#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1548#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1549#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1550#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1551#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1552#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1553#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1554#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1555#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1556#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1557#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1558#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1559#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1560#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1561#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1562#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1563#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1564#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1565#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1566#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1567#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1568#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1569#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1570#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1571#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1572#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1573#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1574#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1575#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1576#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1577#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1578#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1579#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1580#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1581#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1582#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1583#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1584#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1585#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1586#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1587#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1588#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1589#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1590#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1591#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1592#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1593#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1594#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1595* 1596/* 1597 * Flow throw Queue reset register 1598 / 1599#define BGE_FTQ_RESET 0x5C00 1600* 1601#define BGE_FTQRESET_DMAREAD 0x00000002 1602#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1603#define BGE_FTQRESET_DMADONE 0x00000010 1604#define BGE_FTQRESET_SBDC 0x00000020 1605#define BGE_FTQRESET_SDI 0x00000040 1606#define BGE_FTQRESET_WDMA 0x00000080 1607#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1608#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1609#define BGE_FTQRESET_SDC 0x00000400 1610#define BGE_FTQRESET_HCC 0x00000800 1611#define BGE_FTQRESET_TXFIFO 0x00001000 1612#define BGE_FTQRESET_MBC 0x00002000 1613#define BGE_FTQRESET_RBDC 0x00004000 1614#define BGE_FTQRESET_RXLP 0x00008000 1615#define BGE_FTQRESET_RDBDI 0x00010000 1616#define BGE_FTQRESET_RDC 0x00020000 1617#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1618 1619/* 1620 * Message Signaled Interrupt registers 1621 / 1622#define BGE_MSI_MODE 0x6000 1623#define BGE_MSI_STATUS 0x6004 1624#define BGE_MSI_FIFOACCESS 0x6008 1625* 1626/* MSI mode register / 1627#define BGE_MSIMODE_RESET 0x00000001 1628#define BGE_MSIMODE_ENABLE 0x00000002 1629#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1630#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1631#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1632#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1633#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1634* 1635/* MSI status register / 1636#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1637#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1638#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1639#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1640#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1641* 1642 1643/* 1644 * DMA Completion registers 1645 / 1646#define BGE_DMAC_MODE 0x6400 1647* 1648/* DMA Completion mode register / 1649#define BGE_DMACMODE_RESET 0x00000001 1650#define BGE_DMACMODE_ENABLE 0x00000002 1651* 1652 1653/* 1654 * General control registers. 1655 / 1656#define BGE_MODE_CTL 0x6800 1657#define BGE_MISC_CFG 0x6804 1658#define BGE_MISC_LOCAL_CTL 0x6808 1659#define BGE_CPU_EVENT 0x6810 1660#define BGE_EE_ADDR 0x6838 1661#define BGE_EE_DATA 0x683C 1662#define BGE_EE_CTL 0x6840 1663#define BGE_MDI_CTL 0x6844 1664#define BGE_EE_DELAY 0x6848 1665* 1666/* Mode control register / 1667#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1668#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1669#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1670#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1671#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1672#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1673#define BGE_MODECTL_NO_RX_CRC 0x00000400 1674#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1675#define BGE_MODECTL_NO_TX_INTR 0x00002000 1676#define BGE_MODECTL_NO_RX_INTR 0x00004000 1677#define BGE_MODECTL_FORCE_PCI32 0x00008000 1678#define BGE_MODECTL_STACKUP 0x00010000 1679#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1680#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1681#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1682#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1683#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1684#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1685#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1686#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1687#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1688#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1689* 1690/* Misc. config register / 1691#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1692#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1693* 1694#define BGE_32BITTIME_66MHZ (0x41 << 1) 1695 1696/* Misc. Local Control / 1697#define BGE_MLC_INTR_STATE 0x00000001 1698#define BGE_MLC_INTR_CLR 0x00000002 1699#define BGE_MLC_INTR_SET 0x00000004 1700#define BGE_MLC_INTR_ONATTN 0x00000008 1701#define BGE_MLC_MISCIO_IN0 0x00000100 1702#define BGE_MLC_MISCIO_IN1 0x00000200 1703#define BGE_MLC_MISCIO_IN2 0x00000400 1704#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1705#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1706#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1707#define BGE_MLC_MISCIO_OUT0 0x00004000 1708#define BGE_MLC_MISCIO_OUT1 0x00008000 1709#define BGE_MLC_MISCIO_OUT2 0x00010000 1710#define BGE_MLC_EXTRAM_ENB 0x00020000 1711#define BGE_MLC_SRAM_SIZE 0x001C0000 1712#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1713#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1714#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1715#define BGE_MLC_AUTO_EEPROM 0x01000000 1716* 1717#define BGE_SSRAMSIZE_256KB 0x00000000 1718#define BGE_SSRAMSIZE_512KB 0x00040000 1719#define BGE_SSRAMSIZE_1MB 0x00080000 1720#define BGE_SSRAMSIZE_2MB 0x000C0000 1721#define BGE_SSRAMSIZE_4MB 0x00100000 1722#define BGE_SSRAMSIZE_8MB 0x00140000 1723#define BGE_SSRAMSIZE_16M 0x00180000 1724 1725/* EEPROM address register / 1726#define BGE_EEADDR_ADDRESS 0x0000FFFC 1727#define BGE_EEADDR_HALFCLK 0x01FF0000 1728#define BGE_EEADDR_START 0x02000000 1729#define BGE_EEADDR_DEVID 0x1C000000 1730#define BGE_EEADDR_RESET 0x20000000 1731#define BGE_EEADDR_DONE 0x40000000 1732#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1733* 1734#define BGE_EEDEVID(x) ((x & 7) << 26) 1735#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1736#define BGE_HALFCLK_384SCL 0x60 1737#define BGE_EE_READCMD \ 1738 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1739 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1740#define BGE_EE_WRCMD \ 1741 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1742 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1743 1744/* EEPROM Control register / 1745#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1746#define BGE_EECTL_CLKOUT 0x00000002 1747#define BGE_EECTL_CLKIN 0x00000004 1748#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1749#define BGE_EECTL_DATAOUT 0x00000010 1750#define BGE_EECTL_DATAIN 0x00000020 1751* 1752/* MDI (MII/GMII) access register / 1753#define BGE_MDI_DATA 0x00000001 1754#define BGE_MDI_DIR 0x00000002 1755#define BGE_MDI_SEL 0x00000004 1756#define BGE_MDI_CLK 0x00000008 1757* 1758#define BGE_MEMWIN_START 0x00008000 1759#define BGE_MEMWIN_END 0x0000FFFF 1760 1761 1762#define BGE_MEMWIN_READ(sc, x, val) \ 1763 do { \ 1764 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1765 (0xFFFF0000 & x), 4); \ 1766 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1767 } while(0) 1768 1769#define BGE_MEMWIN_WRITE(sc, x, val) \ 1770 do { \ 1771 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1772 (0xFFFF0000 & x), 4); \ 1773 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1774 } while(0) 1775 1776/* 1777 * This magic number is written to the firmware mailbox at 0xb50 1778 * before a software reset is issued. After the internal firmware 1779 * has completed its initialization it will write the opposite of 1780 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1781 * driver to synchronize with the firmware. 1782 / 1783#define BGE_MAGIC_NUMBER 0x4B657654 1784* 1785typedef struct { 1786 uint32_t bge_addr_hi; 1787 uint32_t bge_addr_lo; 1788} bge_hostaddr; 1789 1790#define BGE_HOSTADDR(x, y) \ 1791 do { \ 1792 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1793 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1794 } while(0) 1795 1796#define BGE_ADDR_LO(y) \ 1797 ((uint64_t) (y) & 0xFFFFFFFF) 1798#define BGE_ADDR_HI(y) \ 1799 ((uint64_t) (y) >> 32) 1800 1801/* Ring control block structure / 1802struct bge_rcb { 1803* bge_hostaddr bge_hostaddr; 1804 uint32_t bge_maxlen_flags; 1805 uint32_t bge_nicaddr; 1806}; 1807 1808#define RCB_WRITE_4(sc, rcb, offset, val) \ 1809 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1810 rcb + offsetof(struct bge_rcb, offset), val) 1811#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1812 1813#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1814#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1815 1816struct bge_tx_bd { 1817 bge_hostaddr bge_addr; 1818#if BYTE_ORDER == LITTLE_ENDIAN 1819 uint16_t bge_flags; 1820 uint16_t bge_len; 1821 uint16_t bge_vlan_tag; 1822 uint16_t bge_rsvd; 1823#else 1824 uint16_t bge_len; 1825 uint16_t bge_flags; 1826 uint16_t bge_rsvd; 1827 uint16_t bge_vlan_tag; 1828#endif 1829}; 1830 1831#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1832#define BGE_TXBDFLAG_IP_CSUM 0x0002 1833#define BGE_TXBDFLAG_END 0x0004 1834#define BGE_TXBDFLAG_IP_FRAG 0x0008 1835#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1836#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1837#define BGE_TXBDFLAG_COAL_NOW 0x0080 1838#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1839#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1840#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1841#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1842#define BGE_TXBDFLAG_NO_CRC 0x8000 1843 1844#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1845 BGE_SEND_RING_1_TO_4 + \ 1846 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1847 1848struct bge_rx_bd { 1849 bge_hostaddr bge_addr; 1850#if BYTE_ORDER == LITTLE_ENDIAN 1851 uint16_t bge_len; 1852 uint16_t bge_idx; 1853 uint16_t bge_flags; 1854 uint16_t bge_type; 1855 uint16_t bge_tcp_udp_csum; 1856 uint16_t bge_ip_csum; 1857 uint16_t bge_vlan_tag; 1858 uint16_t bge_error_flag; 1859#else 1860 uint16_t bge_idx; 1861 uint16_t bge_len; 1862 uint16_t bge_type; 1863 uint16_t bge_flags; 1864 uint16_t bge_ip_csum; 1865 uint16_t bge_tcp_udp_csum; 1866 uint16_t bge_error_flag; 1867 uint16_t bge_vlan_tag; 1868#endif 1869 uint32_t bge_rsvd; 1870 uint32_t bge_opaque; 1871}; 1872 1873struct bge_extrx_bd { 1874 bge_hostaddr bge_addr1; 1875 bge_hostaddr bge_addr2; 1876 bge_hostaddr bge_addr3; 1877#if BYTE_ORDER == LITTLE_ENDIAN 1878 uint16_t bge_len2; 1879 uint16_t bge_len1; 1880 uint16_t bge_rsvd1; 1881 uint16_t bge_len3; 1882#else 1883 uint16_t bge_len1; 1884 uint16_t bge_len2; 1885 uint16_t bge_len3; 1886 uint16_t bge_rsvd1; 1887#endif 1888 bge_hostaddr bge_addr0; 1889#if BYTE_ORDER == LITTLE_ENDIAN 1890 uint16_t bge_len0; 1891 uint16_t bge_idx; 1892 uint16_t bge_flags; 1893 uint16_t bge_type; 1894 uint16_t bge_tcp_udp_csum; 1895 uint16_t bge_ip_csum; 1896 uint16_t bge_vlan_tag; 1897 uint16_t bge_error_flag; 1898#else 1899 uint16_t bge_idx; 1900 uint16_t bge_len0; 1901 uint16_t bge_type; 1902 uint16_t bge_flags; 1903 uint16_t bge_ip_csum; 1904 uint16_t bge_tcp_udp_csum; 1905 uint16_t bge_error_flag; 1906 uint16_t bge_vlan_tag; 1907#endif 1908 uint32_t bge_rsvd0; 1909 uint32_t bge_opaque; 1910}; 1911 1912#define BGE_RXBDFLAG_END 0x0004 1913#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1914#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1915#define BGE_RXBDFLAG_ERROR 0x0400 1916#define BGE_RXBDFLAG_MINI_RING 0x0800 1917#define BGE_RXBDFLAG_IP_CSUM 0x1000 1918#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1919#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1920 1921#define BGE_RXERRFLAG_BAD_CRC 0x0001 1922#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1923#define BGE_RXERRFLAG_LINK_LOST 0x0004 1924#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1925#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1926#define BGE_RXERRFLAG_RUNT 0x0020 1927#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1928#define BGE_RXERRFLAG_GIANT 0x0080 1929 1930struct bge_sts_idx { 1931#if BYTE_ORDER == LITTLE_ENDIAN 1932 uint16_t bge_rx_prod_idx; 1933 uint16_t bge_tx_cons_idx; 1934#else 1935 uint16_t bge_tx_cons_idx; 1936 uint16_t bge_rx_prod_idx; 1937#endif 1938}; 1939 1940struct bge_status_block { 1941 uint32_t bge_status; 1942 uint32_t bge_rsvd0; 1943#if BYTE_ORDER == LITTLE_ENDIAN 1944 uint16_t bge_rx_jumbo_cons_idx; 1945 uint16_t bge_rx_std_cons_idx; 1946 uint16_t bge_rx_mini_cons_idx; 1947 uint16_t bge_rsvd1; 1948#else 1949 uint16_t bge_rx_std_cons_idx; 1950 uint16_t bge_rx_jumbo_cons_idx; 1951 uint16_t bge_rsvd1; 1952 uint16_t bge_rx_mini_cons_idx; 1953#endif 1954 struct bge_sts_idx bge_idx[16]; 1955}; 1956 1957#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1958#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1959 1960#define BGE_STATFLAG_UPDATED 0x00000001 1961#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1962#define BGE_STATFLAG_ERROR 0x00000004 1963 1964 1965/* 1966 * Broadcom Vendor ID 1967 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1968 * even though they're now manufactured by Broadcom) 1969 / 1970#define BCOM_VENDORID 0x14E4 1971#define BCOM_DEVICEID_BCM5700 0x1644 1972#define BCOM_DEVICEID_BCM5701 0x1645 1973#define BCOM_DEVICEID_BCM5702 0x1646 1974#define BCOM_DEVICEID_BCM5702X 0x16A6 1975#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1976#define BCOM_DEVICEID_BCM5703 0x1647 1977#define BCOM_DEVICEID_BCM5703X 0x16A7 1978#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 1979#define BCOM_DEVICEID_BCM5704C 0x1648 1980#define BCOM_DEVICEID_BCM5704S 0x16A8 1981#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 1982#define BCOM_DEVICEID_BCM5705 0x1653 1983#define BCOM_DEVICEID_BCM5705K 0x1654 1984#define BCOM_DEVICEID_BCM5705F 0x166E 1985#define BCOM_DEVICEID_BCM5705M 0x165D 1986#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1987#define BCOM_DEVICEID_BCM5714C 0x1668 1988#define BCOM_DEVICEID_BCM5714S 0x1669 1989#define BCOM_DEVICEID_BCM5715 0x1678 1990#define BCOM_DEVICEID_BCM5715S 0x1679 1991#define BCOM_DEVICEID_BCM5720 0x1658 1992#define BCOM_DEVICEID_BCM5721 0x1659 1993#define BCOM_DEVICEID_BCM5750 0x1676 1994#define BCOM_DEVICEID_BCM5750M 0x167C 1995#define BCOM_DEVICEID_BCM5751 0x1677 1996#define BCOM_DEVICEID_BCM5751F 0x167E 1997#define BCOM_DEVICEID_BCM5751M 0x167D 1998#define BCOM_DEVICEID_BCM5752 0x1600 1999#define BCOM_DEVICEID_BCM5752M 0x1601 2000#define BCOM_DEVICEID_BCM5753 0x16F7 2001#define BCOM_DEVICEID_BCM5753F 0x16FE 2002#define BCOM_DEVICEID_BCM5753M 0x16FD 2003#define BCOM_DEVICEID_BCM5754 0x167A 2004#define BCOM_DEVICEID_BCM5754M 0x1672 2005#define BCOM_DEVICEID_BCM5755 0x167B 2006#define BCOM_DEVICEID_BCM5755M 0x1673 2007#define BCOM_DEVICEID_BCM5780 0x166A 2008#define BCOM_DEVICEID_BCM5780S 0x166B 2009#define BCOM_DEVICEID_BCM5781 0x16DD 2010#define BCOM_DEVICEID_BCM5782 0x1696 2011#define BCOM_DEVICEID_BCM5786 0x169A 2012#define BCOM_DEVICEID_BCM5787 0x169B 2013#define BCOM_DEVICEID_BCM5787M 0x1693 2014#define BCOM_DEVICEID_BCM5788 0x169C 2015#define BCOM_DEVICEID_BCM5789 0x169D 2016#define BCOM_DEVICEID_BCM5901 0x170D 2017#define BCOM_DEVICEID_BCM5901A2 0x170E 2018#define BCOM_DEVICEID_BCM5903M 0x16FF 2019* 2020/* 2021 * Alteon AceNIC PCI vendor/device ID. 2022 / 2023#define ALTEON_VENDORID 0x12AE 2024#define ALTEON_DEVICEID_ACENIC 0x0001 2025#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2026#define ALTEON_DEVICEID_BCM5700 0x0003 2027#define ALTEON_DEVICEID_BCM5701 0x0004 2028* 2029/* 2030 * 3Com 3c996 PCI vendor/device ID. 2031 / 2032#define TC_VENDORID 0x10B7 2033#define TC_DEVICEID_3C996 0x0003 2034* 2035/* 2036 * SysKonnect PCI vendor ID 2037 / 2038#define SK_VENDORID 0x1148 2039#define SK_DEVICEID_ALTIMA 0x4400 2040#define SK_SUBSYSID_9D21 0x4421 2041#define SK_SUBSYSID_9D41 0x4441 2042* 2043/* 2044 * Altima PCI vendor/device ID. 2045 / 2046#define ALTIMA_VENDORID 0x173b 2047#define ALTIMA_DEVICE_AC1000 0x03e8 2048#define ALTIMA_DEVICE_AC1002 0x03e9 2049#define ALTIMA_DEVICE_AC9100 0x03ea 2050* 2051/* 2052 * Dell PCI vendor ID 2053 / 2054* 2055#define DELL_VENDORID 0x1028 2056 2057/* 2058 * Apple PCI vendor ID. 2059 / 2060#define APPLE_VENDORID 0x106b 2061#define APPLE_DEVICE_BCM5701 0x1645 2062* 2063/* 2064 * Offset of MAC address inside EEPROM. 2065 / 2066#define BGE_EE_MAC_OFFSET 0x7C 2067#define BGE_EE_HWCFG_OFFSET 0xC8 2068* 2069#define BGE_HWCFG_VOLTAGE 0x00000003 2070#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2071#define BGE_HWCFG_MEDIA 0x00000030 2072#define BGE_HWCFG_ASF 0x00000080 2073 2074#define BGE_VOLTAGE_1POINT3 0x00000000 2075#define BGE_VOLTAGE_1POINT8 0x00000001 2076 2077#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2078#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2079#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2080 2081#define BGE_MEDIA_UNSPEC 0x00000000 2082#define BGE_MEDIA_COPPER 0x00000010 2083#define BGE_MEDIA_FIBER 0x00000020 2084 2085#define BGE_PCI_READ_CMD 0x06000000 2086#define BGE_PCI_WRITE_CMD 0x70000000 2087 2088#define BGE_TICKS_PER_SEC 1000000 2089 2090/* 2091 * Ring size constants. 2092 / 2093#define BGE_EVENT_RING_CNT 256 2094#define BGE_CMD_RING_CNT 64 2095#define BGE_STD_RX_RING_CNT 512 2096#define BGE_JUMBO_RX_RING_CNT 256 2097#define BGE_MINI_RX_RING_CNT 1024 2098#define BGE_RETURN_RING_CNT 1024 2099* 2100/* 5705 has smaller return ring size / 2101* 2102#define BGE_RETURN_RING_CNT_5705 512 2103 2104/* 2105 * Possible TX ring sizes. 2106 / 2107#define BGE_TX_RING_CNT_128 128 2108#define BGE_TX_RING_BASE_128 0x3800 2109* 2110#define BGE_TX_RING_CNT_256 256 2111#define BGE_TX_RING_BASE_256 0x3000 2112 2113#define BGE_TX_RING_CNT_512 512 2114#define BGE_TX_RING_BASE_512 0x2000 2115 2116#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2117#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2118 2119/* 2120 * Tigon III statistics counters. 2121 / 2122/ Statistics maintained MAC Receive block. / 2123struct bge_rx_mac_stats { 2124* bge_hostaddr ifHCInOctets; 2125 bge_hostaddr Reserved1; 2126 bge_hostaddr etherStatsFragments; 2127 bge_hostaddr ifHCInUcastPkts; 2128 bge_hostaddr ifHCInMulticastPkts; 2129 bge_hostaddr ifHCInBroadcastPkts; 2130 bge_hostaddr dot3StatsFCSErrors; 2131 bge_hostaddr dot3StatsAlignmentErrors; 2132 bge_hostaddr xonPauseFramesReceived; 2133 bge_hostaddr xoffPauseFramesReceived; 2134 bge_hostaddr macControlFramesReceived; 2135 bge_hostaddr xoffStateEntered; 2136 bge_hostaddr dot3StatsFramesTooLong; 2137 bge_hostaddr etherStatsJabbers; 2138 bge_hostaddr etherStatsUndersizePkts; 2139 bge_hostaddr inRangeLengthError; 2140 bge_hostaddr outRangeLengthError; 2141 bge_hostaddr etherStatsPkts64Octets; 2142 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2143 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2144 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2145 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2146 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2147 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2148 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2149 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2150 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2151}; 2152 2153 2154/* Statistics maintained MAC Transmit block. / 2155struct bge_tx_mac_stats { 2156* bge_hostaddr ifHCOutOctets; 2157 bge_hostaddr Reserved2; 2158 bge_hostaddr etherStatsCollisions; 2159 bge_hostaddr outXonSent; 2160 bge_hostaddr outXoffSent; 2161 bge_hostaddr flowControlDone; 2162 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2163 bge_hostaddr dot3StatsSingleCollisionFrames; 2164 bge_hostaddr dot3StatsMultipleCollisionFrames; 2165 bge_hostaddr dot3StatsDeferredTransmissions; 2166 bge_hostaddr Reserved3; 2167 bge_hostaddr dot3StatsExcessiveCollisions; 2168 bge_hostaddr dot3StatsLateCollisions; 2169 bge_hostaddr dot3Collided2Times; 2170 bge_hostaddr dot3Collided3Times; 2171 bge_hostaddr dot3Collided4Times; 2172 bge_hostaddr dot3Collided5Times; 2173 bge_hostaddr dot3Collided6Times; 2174 bge_hostaddr dot3Collided7Times; 2175 bge_hostaddr dot3Collided8Times; 2176 bge_hostaddr dot3Collided9Times; 2177 bge_hostaddr dot3Collided10Times; 2178 bge_hostaddr dot3Collided11Times; 2179 bge_hostaddr dot3Collided12Times; 2180 bge_hostaddr dot3Collided13Times; 2181 bge_hostaddr dot3Collided14Times; 2182 bge_hostaddr dot3Collided15Times; 2183 bge_hostaddr ifHCOutUcastPkts; 2184 bge_hostaddr ifHCOutMulticastPkts; 2185 bge_hostaddr ifHCOutBroadcastPkts; 2186 bge_hostaddr dot3StatsCarrierSenseErrors; 2187 bge_hostaddr ifOutDiscards; 2188 bge_hostaddr ifOutErrors; 2189}; 2190 2191/* Stats counters access through registers / 2192struct bge_mac_stats_regs { 2193* uint32_t ifHCOutOctets; 2194 uint32_t Reserved0; 2195 uint32_t etherStatsCollisions; 2196 uint32_t outXonSent; 2197 uint32_t outXoffSent; 2198 uint32_t Reserved1; 2199 uint32_t dot3StatsInternalMacTransmitErrors; 2200 uint32_t dot3StatsSingleCollisionFrames; 2201 uint32_t dot3StatsMultipleCollisionFrames; 2202 uint32_t dot3StatsDeferredTransmissions; 2203 uint32_t Reserved2; 2204 uint32_t dot3StatsExcessiveCollisions; 2205 uint32_t dot3StatsLateCollisions; 2206 uint32_t Reserved3[14]; 2207 uint32_t ifHCOutUcastPkts; 2208 uint32_t ifHCOutMulticastPkts; 2209 uint32_t ifHCOutBroadcastPkts; 2210 uint32_t Reserved4[2]; 2211 uint32_t ifHCInOctets; 2212 uint32_t Reserved5; 2213 uint32_t etherStatsFragments; 2214 uint32_t ifHCInUcastPkts; 2215 uint32_t ifHCInMulticastPkts; 2216 uint32_t ifHCInBroadcastPkts; 2217 uint32_t dot3StatsFCSErrors; 2218 uint32_t dot3StatsAlignmentErrors; 2219 uint32_t xonPauseFramesReceived; 2220 uint32_t xoffPauseFramesReceived; 2221 uint32_t macControlFramesReceived; 2222 uint32_t xoffStateEntered; 2223 uint32_t dot3StatsFramesTooLong; 2224 uint32_t etherStatsJabbers; 2225 uint32_t etherStatsUndersizePkts; 2226}; 2227 2228struct bge_stats { 2229 uint8_t Reserved0[256]; 2230 2231 /* Statistics maintained by Receive MAC. / 2232* struct bge_rx_mac_stats rxstats; 2233 2234 bge_hostaddr Unused1[37]; 2235 2236 /* Statistics maintained by Transmit MAC. / 2237* struct bge_tx_mac_stats txstats; 2238 2239 bge_hostaddr Unused2[31]; 2240 2241 /* Statistics maintained by Receive List Placement. / 2242* bge_hostaddr COSIfHCInPkts[16]; 2243 bge_hostaddr COSFramesDroppedDueToFilters; 2244 bge_hostaddr nicDmaWriteQueueFull; 2245 bge_hostaddr nicDmaWriteHighPriQueueFull; 2246 bge_hostaddr nicNoMoreRxBDs; 2247 bge_hostaddr ifInDiscards; 2248 bge_hostaddr ifInErrors; 2249 bge_hostaddr nicRecvThresholdHit; 2250 2251 bge_hostaddr Unused3[9]; 2252 2253 /* Statistics maintained by Send Data Initiator. / 2254* bge_hostaddr COSIfHCOutPkts[16]; 2255 bge_hostaddr nicDmaReadQueueFull; 2256 bge_hostaddr nicDmaReadHighPriQueueFull; 2257 bge_hostaddr nicSendDataCompQueueFull; 2258 2259 /* Statistics maintained by Host Coalescing. / 2260* bge_hostaddr nicRingSetSendProdIndex; 2261 bge_hostaddr nicRingStatusUpdate; 2262 bge_hostaddr nicInterrupts; 2263 bge_hostaddr nicAvoidedInterrupts; 2264 bge_hostaddr nicSendThresholdHit; 2265 2266 uint8_t Reserved4[320]; 2267}; 2268 2269/* 2270 * Tigon general information block. This resides in host memory 2271 * and contains the status counters, ring control blocks and 2272 * producer pointers. 2273 / 2274* 2275struct bge_gib { 2276 struct bge_stats bge_stats; 2277 struct bge_rcb bge_tx_rcb[16]; 2278 struct bge_rcb bge_std_rx_rcb; 2279 struct bge_rcb bge_jumbo_rx_rcb; 2280 struct bge_rcb bge_mini_rx_rcb; 2281 struct bge_rcb bge_return_rcb; 2282}; 2283 2284#define BGE_FRAMELEN 1518 2285#define BGE_MAX_FRAMELEN 1536 2286#define BGE_JUMBO_FRAMELEN 9018 2287#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2288#define BGE_MIN_FRAMELEN 60 2289 2290/* 2291 * Other utility macros. 2292 / 2293#define BGE_INC(x, y) (x) = (x + 1) % y 2294* 2295/* 2296 * Vital product data and structures. 2297 / 2298#define BGE_VPD_FLAG 0x8000 2299* 2300/* VPD structures / 2301struct vpd_res { 2302* uint8_t vr_id; 2303 uint8_t vr_len; 2304 uint8_t vr_pad; 2305}; 2306 2307struct vpd_key { 2308 char vk_key[2]; 2309 uint8_t vk_len; 2310}; 2311 2312#define VPD_RES_ID 0x82 /* ID string / 2313#define VPD_RES_READ 0x90 / start of read only area / 2314#define VPD_RES_WRITE 0x81 / start of read/write area / 2315#define VPD_RES_END 0x78 / end tag / 2316* 2317 2318/* 2319 * Register access macros. The Tigon always uses memory mapped register 2320 * accesses and all registers must be accessed with 32 bit operations. 2321 / 2322* 2323#define CSR_WRITE_4(sc, reg, val) \ 2324 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2325 2326#define CSR_READ_4(sc, reg) \ 2327 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2328 2329#define BGE_SETBIT(sc, reg, x) \ 2330 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2331#define BGE_CLRBIT(sc, reg, x) \ 2332 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2333 2334#define PCI_SETBIT(dev, reg, x, s) \ 2335 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2336#define PCI_CLRBIT(dev, reg, x, s) \ 2337 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2338 2339/* 2340 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2341 * values are tuneable. They control the actual amount of buffers 2342 * allocated for the standard, mini and jumbo receive rings. 2343 / 2344* 2345#define BGE_SSLOTS 256 2346#define BGE_MSLOTS 256 2347#define BGE_JSLOTS 384 2348 2349#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2350#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2351 (BGE_JRAWLEN % sizeof(uint64_t)))) 2352#define BGE_JPAGESZ PAGE_SIZE 2353#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2354#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2355 2356#define BGE_NSEG_JUMBO 4 2357#define BGE_NSEG_NEW 32 2358 2359/* 2360 * Ring structures. Most of these reside in host memory and we tell 2361 * the NIC where they are via the ring control blocks. The exceptions 2362 * are the tx and command rings, which live in NIC memory and which 2363 * we access via the shared memory window. 2364 / 2365* 2366struct bge_ring_data { 2367 struct bge_rx_bd bge_rx_std_ring; 2368* bus_addr_t bge_rx_std_ring_paddr; 2369 struct bge_extrx_bd bge_rx_jumbo_ring; 2370* bus_addr_t bge_rx_jumbo_ring_paddr; 2371 struct bge_rx_bd bge_rx_return_ring; 2372* bus_addr_t bge_rx_return_ring_paddr; 2373 struct bge_tx_bd bge_tx_ring; 2374* bus_addr_t bge_tx_ring_paddr; 2375 struct bge_status_block bge_status_block; 2376* bus_addr_t bge_status_block_paddr; 2377 struct bge_stats bge_stats; 2378* bus_addr_t bge_stats_paddr; 2379 struct bge_gib bge_info; 2380}; 2381 2382#define BGE_STD_RX_RING_SZ \ 2383 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2384#define BGE_JUMBO_RX_RING_SZ \ 2385 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2386#define BGE_TX_RING_SZ \ 2387 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2388#define BGE_RX_RTN_RING_SZ(x) \ 2389 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2390 2391#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2392 2393#define BGE_STATS_SZ sizeof (struct bge_stats) 2394 2395/* 2396 * Mbuf pointers. We need these to keep track of the virtual addresses 2397 * of our mbuf chains since we can only convert from physical to virtual, 2398 * not the other way around. 2399 / 2400struct bge_chain_data { 2401* bus_dma_tag_t bge_parent_tag; 2402 bus_dma_tag_t bge_rx_std_ring_tag; 2403 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2404 bus_dma_tag_t bge_rx_return_ring_tag; 2405 bus_dma_tag_t bge_tx_ring_tag; 2406 bus_dma_tag_t bge_status_tag; 2407 bus_dma_tag_t bge_stats_tag; 2408 bus_dma_tag_t bge_mtag; /* mbuf mapping tag / 2409* bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag / 2410* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2411 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2412 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2413 bus_dmamap_t bge_rx_std_ring_map; 2414 bus_dmamap_t bge_rx_jumbo_ring_map; 2415 bus_dmamap_t bge_tx_ring_map; 2416 bus_dmamap_t bge_rx_return_ring_map; 2417 bus_dmamap_t bge_status_map; 2418 bus_dmamap_t bge_stats_map; 2419 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2420* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2421* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2422}; 2423* 2424struct bge_dmamap_arg { 2425 struct bge_softc sc; 2426* bus_addr_t bge_busaddr; 2427 uint16_t bge_flags; 2428 int bge_idx; 2429 int bge_maxsegs; 2430 struct bge_tx_bd bge_ring; 2431}; 2432* 2433#define BGE_HWREV_TIGON 0x01 2434#define BGE_HWREV_TIGON_II 0x02 2435#define BGE_TIMEOUT 100000 2436#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2437* 2438struct bge_bcom_hack { 2439 int reg; 2440 int val; 2441}; 2442 2443#define ASF_ENABLE 1 2444#define ASF_NEW_HANDSHAKE 2 2445#define ASF_STACKUP 4 2446 2447struct bge_softc { 2448 struct ifnet bge_ifp; / interface info / 2449* device_t bge_dev; 2450 struct mtx bge_mtx; 2451 device_t bge_miibus; 2452 bus_space_handle_t bge_bhandle; 2453 bus_space_tag_t bge_btag; 2454 void bge_intrhand; 2455* struct resource bge_irq; 2456* struct resource bge_res; 2457* struct ifmedia bge_ifmedia; /* TBI media info / 2458* uint32_t bge_flags; 2459#define BGE_FLAG_EXTRAM 0x00000001 /* Has external SSRAM. / 2460#define BGE_FLAG_TBI 0x00000002 2461#define BGE_FLAG_RX_ALIGNBUG 0x00000004 2462#define BGE_FLAG_NO3LED 0x00000008 2463#define BGE_FLAG_PCIX 0x00000010 2464#define BGE_FLAG_PCIE 0x00000020 2465* uint32_t bge_chipid; 2466 uint8_t bge_asicrev; 2467 uint8_t bge_chiprev; 2468 uint8_t bge_asf_mode; 2469 uint8_t bge_asf_count; 2470 struct bge_ring_data bge_ldata; /* rings / 2471* struct bge_chain_data bge_cdata; /* mbufs / 2472* uint16_t bge_tx_saved_considx; 2473 uint16_t bge_rx_saved_considx; 2474 uint16_t bge_ev_saved_considx; 2475 uint16_t bge_return_ring_cnt; 2476 uint16_t bge_std; /* current std ring head / 2477* uint16_t bge_jumbo; /* current jumo ring head / 2478* uint32_t bge_stat_ticks; 2479 uint32_t bge_rx_coal_ticks; 2480 uint32_t bge_tx_coal_ticks; 2481 uint32_t bge_tx_prodidx; 2482 uint32_t bge_rx_max_coal_bds; 2483 uint32_t bge_tx_max_coal_bds; 2484 uint32_t bge_tx_buf_ratio; 2485 int bge_if_flags; 2486 int bge_txcnt; 2487 int bge_link; /* link state / 2488* int bge_link_evt; /* pending link event / 2489* int bge_timer; 2490 struct callout bge_stat_ch; 2491 char bge_vpd_prodname; 2492* char *bge_vpd_readonly;	578 579/* Ethernet MAC Mode register / 580#define BGE_MACMODE_RESET 0x00000001 581#define BGE_MACMODE_HALF_DUPLEX 0x00000002 582#define BGE_MACMODE_PORTMODE 0x0000000C 583#define BGE_MACMODE_LOOPBACK 0x00000010 584#define BGE_MACMODE_RX_TAGGEDPKT 0x00000080 585#define BGE_MACMODE_TX_BURST_ENB 0x00000100 586#define BGE_MACMODE_MAX_DEFER 0x00000200 587#define BGE_MACMODE_LINK_POLARITY 0x00000400 588#define BGE_MACMODE_RX_STATS_ENB 0x00000800 589#define BGE_MACMODE_RX_STATS_CLEAR 0x00001000 590#define BGE_MACMODE_RX_STATS_FLUSH 0x00002000 591#define BGE_MACMODE_TX_STATS_ENB 0x00004000 592#define BGE_MACMODE_TX_STATS_CLEAR 0x00008000 593#define BGE_MACMODE_TX_STATS_FLUSH 0x00010000 594#define BGE_MACMODE_TBI_SEND_CFGS 0x00020000 595#define BGE_MACMODE_MAGIC_PKT_ENB 0x00040000 596#define BGE_MACMODE_ACPI_PWRON_ENB 0x00080000 597#define BGE_MACMODE_MIP_ENB 0x00100000 598#define BGE_MACMODE_TXDMA_ENB 0x00200000 599#define BGE_MACMODE_RXDMA_ENB 0x00400000 600#define BGE_MACMODE_FRMHDR_DMA_ENB 0x00800000 601* 602#define BGE_PORTMODE_NONE 0x00000000 603#define BGE_PORTMODE_MII 0x00000004 604#define BGE_PORTMODE_GMII 0x00000008 605#define BGE_PORTMODE_TBI 0x0000000C 606 607/* MAC Status register / 608#define BGE_MACSTAT_TBI_PCS_SYNCHED 0x00000001 609#define BGE_MACSTAT_TBI_SIGNAL_DETECT 0x00000002 610#define BGE_MACSTAT_RX_CFG 0x00000004 611#define BGE_MACSTAT_CFG_CHANGED 0x00000008 612#define BGE_MACSTAT_SYNC_CHANGED 0x00000010 613#define BGE_MACSTAT_PORT_DECODE_ERROR 0x00000400 614#define BGE_MACSTAT_LINK_CHANGED 0x00001000 615#define BGE_MACSTAT_MI_COMPLETE 0x00400000 616#define BGE_MACSTAT_MI_INTERRUPT 0x00800000 617#define BGE_MACSTAT_AUTOPOLL_ERROR 0x01000000 618#define BGE_MACSTAT_ODI_ERROR 0x02000000 619#define BGE_MACSTAT_RXSTAT_OFLOW 0x04000000 620#define BGE_MACSTAT_TXSTAT_OFLOW 0x08000000 621* 622/* MAC Event Enable Register / 623#define BGE_EVTENB_PORT_DECODE_ERROR 0x00000400 624#define BGE_EVTENB_LINK_CHANGED 0x00001000 625#define BGE_EVTENB_MI_COMPLETE 0x00400000 626#define BGE_EVTENB_MI_INTERRUPT 0x00800000 627#define BGE_EVTENB_AUTOPOLL_ERROR 0x01000000 628#define BGE_EVTENB_ODI_ERROR 0x02000000 629#define BGE_EVTENB_RXSTAT_OFLOW 0x04000000 630#define BGE_EVTENB_TXSTAT_OFLOW 0x08000000 631* 632/* LED Control Register / 633#define BGE_LEDCTL_LINKLED_OVERRIDE 0x00000001 634#define BGE_LEDCTL_1000MBPS_LED 0x00000002 635#define BGE_LEDCTL_100MBPS_LED 0x00000004 636#define BGE_LEDCTL_10MBPS_LED 0x00000008 637#define BGE_LEDCTL_TRAFLED_OVERRIDE 0x00000010 638#define BGE_LEDCTL_TRAFLED_BLINK 0x00000020 639#define BGE_LEDCTL_TREFLED_BLINK_2 0x00000040 640#define BGE_LEDCTL_1000MBPS_STS 0x00000080 641#define BGE_LEDCTL_100MBPS_STS 0x00000100 642#define BGE_LEDCTL_10MBPS_STS 0x00000200 643#define BGE_LEDCTL_TRADLED_STS 0x00000400 644#define BGE_LEDCTL_BLINKPERIOD 0x7FF80000 645#define BGE_LEDCTL_BLINKPERIOD_OVERRIDE 0x80000000 646* 647/* TX backoff seed register / 648#define BGE_TX_BACKOFF_SEED_MASK 0x3F 649* 650/* Autopoll status register / 651#define BGE_AUTOPOLLSTS_ERROR 0x00000001 652* 653/* Transmit MAC mode register / 654#define BGE_TXMODE_RESET 0x00000001 655#define BGE_TXMODE_ENABLE 0x00000002 656#define BGE_TXMODE_FLOWCTL_ENABLE 0x00000010 657#define BGE_TXMODE_BIGBACKOFF_ENABLE 0x00000020 658#define BGE_TXMODE_LONGPAUSE_ENABLE 0x00000040 659* 660/* Transmit MAC status register / 661#define BGE_TXSTAT_RX_XOFFED 0x00000001 662#define BGE_TXSTAT_SENT_XOFF 0x00000002 663#define BGE_TXSTAT_SENT_XON 0x00000004 664#define BGE_TXSTAT_LINK_UP 0x00000008 665#define BGE_TXSTAT_ODI_UFLOW 0x00000010 666#define BGE_TXSTAT_ODI_OFLOW 0x00000020 667* 668/* Transmit MAC lengths register / 669#define BGE_TXLEN_SLOTTIME 0x000000FF 670#define BGE_TXLEN_IPG 0x00000F00 671#define BGE_TXLEN_CRS 0x00003000 672* 673/* Receive MAC mode register / 674#define BGE_RXMODE_RESET 0x00000001 675#define BGE_RXMODE_ENABLE 0x00000002 676#define BGE_RXMODE_FLOWCTL_ENABLE 0x00000004 677#define BGE_RXMODE_RX_GIANTS 0x00000020 678#define BGE_RXMODE_RX_RUNTS 0x00000040 679#define BGE_RXMODE_8022_LENCHECK 0x00000080 680#define BGE_RXMODE_RX_PROMISC 0x00000100 681#define BGE_RXMODE_RX_NO_CRC_CHECK 0x00000200 682#define BGE_RXMODE_RX_KEEP_VLAN_DIAG 0x00000400 683* 684/* Receive MAC status register / 685#define BGE_RXSTAT_REMOTE_XOFFED 0x00000001 686#define BGE_RXSTAT_RCVD_XOFF 0x00000002 687#define BGE_RXSTAT_RCVD_XON 0x00000004 688* 689/* Receive Rules Control register / 690#define BGE_RXRULECTL_OFFSET 0x000000FF 691#define BGE_RXRULECTL_CLASS 0x00001F00 692#define BGE_RXRULECTL_HDRTYPE 0x0000E000 693#define BGE_RXRULECTL_COMPARE_OP 0x00030000 694#define BGE_RXRULECTL_MAP 0x01000000 695#define BGE_RXRULECTL_DISCARD 0x02000000 696#define BGE_RXRULECTL_MASK 0x04000000 697#define BGE_RXRULECTL_ACTIVATE_PROC3 0x08000000 698#define BGE_RXRULECTL_ACTIVATE_PROC2 0x10000000 699#define BGE_RXRULECTL_ACTIVATE_PROC1 0x20000000 700#define BGE_RXRULECTL_ANDWITHNEXT 0x40000000 701* 702/* Receive Rules Mask register / 703#define BGE_RXRULEMASK_VALUE 0x0000FFFF 704#define BGE_RXRULEMASK_MASKVAL 0xFFFF0000 705* 706/* SERDES configuration register / 707#define BGE_SERDESCFG_RXR 0x00000007 / phase interpolator / 708#define BGE_SERDESCFG_RXG 0x00000018 / rx gain setting / 709#define BGE_SERDESCFG_RXEDGESEL 0x00000040 / rising/falling egde / 710#define BGE_SERDESCFG_TX_BIAS 0x00000380 / TXDAC bias setting / 711#define BGE_SERDESCFG_IBMAX 0x00000400 / bias current +25% / 712#define BGE_SERDESCFG_IBMIN 0x00000800 / bias current -25% / 713#define BGE_SERDESCFG_TXMODE 0x00001000 714#define BGE_SERDESCFG_TXEDGESEL 0x00002000 / rising/falling edge / 715#define BGE_SERDESCFG_MODE 0x00004000 / TXCP/TXCN disabled / 716#define BGE_SERDESCFG_PLLTEST 0x00008000 / PLL test mode / 717#define BGE_SERDESCFG_CDET 0x00010000 / comma detect enable / 718#define BGE_SERDESCFG_TBILOOP 0x00020000 / local loopback / 719#define BGE_SERDESCFG_REMLOOP 0x00040000 / remote loopback / 720#define BGE_SERDESCFG_INVPHASE 0x00080000 / Reverse 125Mhz clock / 721#define BGE_SERDESCFG_12REGCTL 0x00300000 / 1.2v regulator ctl / 722#define BGE_SERDESCFG_REGCTL 0x00C00000 / regulator ctl (2.5v) / 723* 724/* SERDES status register / 725#define BGE_SERDESSTS_RXSTAT 0x0000000F / receive status bits / 726#define BGE_SERDESSTS_CDET 0x00000010 / comma code detected / 727* 728/* SGDIG config (not documented) / 729#define BGE_SGDIGCFG_PAUSE_CAP 0x00000800 730#define BGE_SGDIGCFG_ASYM_PAUSE 0x00001000 731#define BGE_SGDIGCFG_SEND 0x40000000 732#define BGE_SGDIGCFG_AUTO 0x80000000 733* 734/* SGDIG status (not documented) / 735#define BGE_SGDIGSTS_PAUSE_CAP 0x00080000 736#define BGE_SGDIGSTS_ASYM_PAUSE 0x00100000 737#define BGE_SGDIGSTS_DONE 0x00000002 738* 739 740/* MI communication register / 741#define BGE_MICOMM_DATA 0x0000FFFF 742#define BGE_MICOMM_REG 0x001F0000 743#define BGE_MICOMM_PHY 0x03E00000 744#define BGE_MICOMM_CMD 0x0C000000 745#define BGE_MICOMM_READFAIL 0x10000000 746#define BGE_MICOMM_BUSY 0x20000000 747* 748#define BGE_MIREG(x) ((x & 0x1F) << 16) 749#define BGE_MIPHY(x) ((x & 0x1F) << 21) 750#define BGE_MICMD_WRITE 0x04000000 751#define BGE_MICMD_READ 0x08000000 752 753/* MI status register / 754#define BGE_MISTS_LINK 0x00000001 755#define BGE_MISTS_10MBPS 0x00000002 756* 757#define BGE_MIMODE_SHORTPREAMBLE 0x00000002 758#define BGE_MIMODE_AUTOPOLL 0x00000010 759#define BGE_MIMODE_CLKCNT 0x001F0000 760 761 762/* 763 * Send data initiator control registers. 764 / 765#define BGE_SDI_MODE 0x0C00 766#define BGE_SDI_STATUS 0x0C04 767#define BGE_SDI_STATS_CTL 0x0C08 768#define BGE_SDI_STATS_ENABLE_MASK 0x0C0C 769#define BGE_SDI_STATS_INCREMENT_MASK 0x0C10 770#define BGE_LOCSTATS_COS0 0x0C80 771#define BGE_LOCSTATS_COS1 0x0C84 772#define BGE_LOCSTATS_COS2 0x0C88 773#define BGE_LOCSTATS_COS3 0x0C8C 774#define BGE_LOCSTATS_COS4 0x0C90 775#define BGE_LOCSTATS_COS5 0x0C84 776#define BGE_LOCSTATS_COS6 0x0C98 777#define BGE_LOCSTATS_COS7 0x0C9C 778#define BGE_LOCSTATS_COS8 0x0CA0 779#define BGE_LOCSTATS_COS9 0x0CA4 780#define BGE_LOCSTATS_COS10 0x0CA8 781#define BGE_LOCSTATS_COS11 0x0CAC 782#define BGE_LOCSTATS_COS12 0x0CB0 783#define BGE_LOCSTATS_COS13 0x0CB4 784#define BGE_LOCSTATS_COS14 0x0CB8 785#define BGE_LOCSTATS_COS15 0x0CBC 786#define BGE_LOCSTATS_DMA_RQ_FULL 0x0CC0 787#define BGE_LOCSTATS_DMA_HIPRIO_RQ_FULL 0x0CC4 788#define BGE_LOCSTATS_SDC_QUEUE_FULL 0x0CC8 789#define BGE_LOCSTATS_NIC_SENDPROD_SET 0x0CCC 790#define BGE_LOCSTATS_STATS_UPDATED 0x0CD0 791#define BGE_LOCSTATS_IRQS 0x0CD4 792#define BGE_LOCSTATS_AVOIDED_IRQS 0x0CD8 793#define BGE_LOCSTATS_TX_THRESH_HIT 0x0CDC 794* 795/* Send Data Initiator mode register / 796#define BGE_SDIMODE_RESET 0x00000001 797#define BGE_SDIMODE_ENABLE 0x00000002 798#define BGE_SDIMODE_STATS_OFLOW_ATTN 0x00000004 799* 800/* Send Data Initiator stats register / 801#define BGE_SDISTAT_STATS_OFLOW_ATTN 0x00000004 802* 803/* Send Data Initiator stats control register / 804#define BGE_SDISTATSCTL_ENABLE 0x00000001 805#define BGE_SDISTATSCTL_FASTER 0x00000002 806#define BGE_SDISTATSCTL_CLEAR 0x00000004 807#define BGE_SDISTATSCTL_FORCEFLUSH 0x00000008 808#define BGE_SDISTATSCTL_FORCEZERO 0x00000010 809* 810/* 811 * Send Data Completion Control registers 812 / 813#define BGE_SDC_MODE 0x1000 814#define BGE_SDC_STATUS 0x1004 815* 816/* Send Data completion mode register / 817#define BGE_SDCMODE_RESET 0x00000001 818#define BGE_SDCMODE_ENABLE 0x00000002 819#define BGE_SDCMODE_ATTN 0x00000004 820* 821/* Send Data completion status register / 822#define BGE_SDCSTAT_ATTN 0x00000004 823* 824/* 825 * Send BD Ring Selector Control registers 826 / 827#define BGE_SRS_MODE 0x1400 828#define BGE_SRS_STATUS 0x1404 829#define BGE_SRS_HWDIAG 0x1408 830#define BGE_SRS_LOC_NIC_CONS0 0x1440 831#define BGE_SRS_LOC_NIC_CONS1 0x1444 832#define BGE_SRS_LOC_NIC_CONS2 0x1448 833#define BGE_SRS_LOC_NIC_CONS3 0x144C 834#define BGE_SRS_LOC_NIC_CONS4 0x1450 835#define BGE_SRS_LOC_NIC_CONS5 0x1454 836#define BGE_SRS_LOC_NIC_CONS6 0x1458 837#define BGE_SRS_LOC_NIC_CONS7 0x145C 838#define BGE_SRS_LOC_NIC_CONS8 0x1460 839#define BGE_SRS_LOC_NIC_CONS9 0x1464 840#define BGE_SRS_LOC_NIC_CONS10 0x1468 841#define BGE_SRS_LOC_NIC_CONS11 0x146C 842#define BGE_SRS_LOC_NIC_CONS12 0x1470 843#define BGE_SRS_LOC_NIC_CONS13 0x1474 844#define BGE_SRS_LOC_NIC_CONS14 0x1478 845#define BGE_SRS_LOC_NIC_CONS15 0x147C 846* 847/* Send BD Ring Selector Mode register / 848#define BGE_SRSMODE_RESET 0x00000001 849#define BGE_SRSMODE_ENABLE 0x00000002 850#define BGE_SRSMODE_ATTN 0x00000004 851* 852/* Send BD Ring Selector Status register / 853#define BGE_SRSSTAT_ERROR 0x00000004 854* 855/* Send BD Ring Selector HW Diagnostics register / 856#define BGE_SRSHWDIAG_STATE 0x0000000F 857#define BGE_SRSHWDIAG_CURRINGNUM 0x000000F0 858#define BGE_SRSHWDIAG_STAGEDRINGNUM 0x00000F00 859#define BGE_SRSHWDIAG_RINGNUM_IN_MBX 0x0000F000 860* 861/* 862 * Send BD Initiator Selector Control registers 863 / 864#define BGE_SBDI_MODE 0x1800 865#define BGE_SBDI_STATUS 0x1804 866#define BGE_SBDI_LOC_NIC_PROD0 0x1808 867#define BGE_SBDI_LOC_NIC_PROD1 0x180C 868#define BGE_SBDI_LOC_NIC_PROD2 0x1810 869#define BGE_SBDI_LOC_NIC_PROD3 0x1814 870#define BGE_SBDI_LOC_NIC_PROD4 0x1818 871#define BGE_SBDI_LOC_NIC_PROD5 0x181C 872#define BGE_SBDI_LOC_NIC_PROD6 0x1820 873#define BGE_SBDI_LOC_NIC_PROD7 0x1824 874#define BGE_SBDI_LOC_NIC_PROD8 0x1828 875#define BGE_SBDI_LOC_NIC_PROD9 0x182C 876#define BGE_SBDI_LOC_NIC_PROD10 0x1830 877#define BGE_SBDI_LOC_NIC_PROD11 0x1834 878#define BGE_SBDI_LOC_NIC_PROD12 0x1838 879#define BGE_SBDI_LOC_NIC_PROD13 0x183C 880#define BGE_SBDI_LOC_NIC_PROD14 0x1840 881#define BGE_SBDI_LOC_NIC_PROD15 0x1844 882* 883/* Send BD Initiator Mode register / 884#define BGE_SBDIMODE_RESET 0x00000001 885#define BGE_SBDIMODE_ENABLE 0x00000002 886#define BGE_SBDIMODE_ATTN 0x00000004 887* 888/* Send BD Initiator Status register / 889#define BGE_SBDISTAT_ERROR 0x00000004 890* 891/* 892 * Send BD Completion Control registers 893 / 894#define BGE_SBDC_MODE 0x1C00 895#define BGE_SBDC_STATUS 0x1C04 896* 897/* Send BD Completion Control Mode register / 898#define BGE_SBDCMODE_RESET 0x00000001 899#define BGE_SBDCMODE_ENABLE 0x00000002 900#define BGE_SBDCMODE_ATTN 0x00000004 901* 902/* Send BD Completion Control Status register / 903#define BGE_SBDCSTAT_ATTN 0x00000004 904* 905/* 906 * Receive List Placement Control registers 907 / 908#define BGE_RXLP_MODE 0x2000 909#define BGE_RXLP_STATUS 0x2004 910#define BGE_RXLP_SEL_LIST_LOCK 0x2008 911#define BGE_RXLP_SEL_NON_EMPTY_BITS 0x200C 912#define BGE_RXLP_CFG 0x2010 913#define BGE_RXLP_STATS_CTL 0x2014 914#define BGE_RXLP_STATS_ENABLE_MASK 0x2018 915#define BGE_RXLP_STATS_INCREMENT_MASK 0x201C 916#define BGE_RXLP_HEAD0 0x2100 917#define BGE_RXLP_TAIL0 0x2104 918#define BGE_RXLP_COUNT0 0x2108 919#define BGE_RXLP_HEAD1 0x2110 920#define BGE_RXLP_TAIL1 0x2114 921#define BGE_RXLP_COUNT1 0x2118 922#define BGE_RXLP_HEAD2 0x2120 923#define BGE_RXLP_TAIL2 0x2124 924#define BGE_RXLP_COUNT2 0x2128 925#define BGE_RXLP_HEAD3 0x2130 926#define BGE_RXLP_TAIL3 0x2134 927#define BGE_RXLP_COUNT3 0x2138 928#define BGE_RXLP_HEAD4 0x2140 929#define BGE_RXLP_TAIL4 0x2144 930#define BGE_RXLP_COUNT4 0x2148 931#define BGE_RXLP_HEAD5 0x2150 932#define BGE_RXLP_TAIL5 0x2154 933#define BGE_RXLP_COUNT5 0x2158 934#define BGE_RXLP_HEAD6 0x2160 935#define BGE_RXLP_TAIL6 0x2164 936#define BGE_RXLP_COUNT6 0x2168 937#define BGE_RXLP_HEAD7 0x2170 938#define BGE_RXLP_TAIL7 0x2174 939#define BGE_RXLP_COUNT7 0x2178 940#define BGE_RXLP_HEAD8 0x2180 941#define BGE_RXLP_TAIL8 0x2184 942#define BGE_RXLP_COUNT8 0x2188 943#define BGE_RXLP_HEAD9 0x2190 944#define BGE_RXLP_TAIL9 0x2194 945#define BGE_RXLP_COUNT9 0x2198 946#define BGE_RXLP_HEAD10 0x21A0 947#define BGE_RXLP_TAIL10 0x21A4 948#define BGE_RXLP_COUNT10 0x21A8 949#define BGE_RXLP_HEAD11 0x21B0 950#define BGE_RXLP_TAIL11 0x21B4 951#define BGE_RXLP_COUNT11 0x21B8 952#define BGE_RXLP_HEAD12 0x21C0 953#define BGE_RXLP_TAIL12 0x21C4 954#define BGE_RXLP_COUNT12 0x21C8 955#define BGE_RXLP_HEAD13 0x21D0 956#define BGE_RXLP_TAIL13 0x21D4 957#define BGE_RXLP_COUNT13 0x21D8 958#define BGE_RXLP_HEAD14 0x21E0 959#define BGE_RXLP_TAIL14 0x21E4 960#define BGE_RXLP_COUNT14 0x21E8 961#define BGE_RXLP_HEAD15 0x21F0 962#define BGE_RXLP_TAIL15 0x21F4 963#define BGE_RXLP_COUNT15 0x21F8 964#define BGE_RXLP_LOCSTAT_COS0 0x2200 965#define BGE_RXLP_LOCSTAT_COS1 0x2204 966#define BGE_RXLP_LOCSTAT_COS2 0x2208 967#define BGE_RXLP_LOCSTAT_COS3 0x220C 968#define BGE_RXLP_LOCSTAT_COS4 0x2210 969#define BGE_RXLP_LOCSTAT_COS5 0x2214 970#define BGE_RXLP_LOCSTAT_COS6 0x2218 971#define BGE_RXLP_LOCSTAT_COS7 0x221C 972#define BGE_RXLP_LOCSTAT_COS8 0x2220 973#define BGE_RXLP_LOCSTAT_COS9 0x2224 974#define BGE_RXLP_LOCSTAT_COS10 0x2228 975#define BGE_RXLP_LOCSTAT_COS11 0x222C 976#define BGE_RXLP_LOCSTAT_COS12 0x2230 977#define BGE_RXLP_LOCSTAT_COS13 0x2234 978#define BGE_RXLP_LOCSTAT_COS14 0x2238 979#define BGE_RXLP_LOCSTAT_COS15 0x223C 980#define BGE_RXLP_LOCSTAT_FILTDROP 0x2240 981#define BGE_RXLP_LOCSTAT_DMA_WRQ_FULL 0x2244 982#define BGE_RXLP_LOCSTAT_DMA_HPWRQ_FULL 0x2248 983#define BGE_RXLP_LOCSTAT_OUT_OF_BDS 0x224C 984#define BGE_RXLP_LOCSTAT_IFIN_DROPS 0x2250 985#define BGE_RXLP_LOCSTAT_IFIN_ERRORS 0x2254 986#define BGE_RXLP_LOCSTAT_RXTHRESH_HIT 0x2258 987* 988 989/* Receive List Placement mode register / 990#define BGE_RXLPMODE_RESET 0x00000001 991#define BGE_RXLPMODE_ENABLE 0x00000002 992#define BGE_RXLPMODE_CLASS0_ATTN 0x00000004 993#define BGE_RXLPMODE_MAPOUTRANGE_ATTN 0x00000008 994#define BGE_RXLPMODE_STATSOFLOW_ATTN 0x00000010 995* 996/* Receive List Placement Status register / 997#define BGE_RXLPSTAT_CLASS0_ATTN 0x00000004 998#define BGE_RXLPSTAT_MAPOUTRANGE_ATTN 0x00000008 999#define BGE_RXLPSTAT_STATSOFLOW_ATTN 0x00000010 1000* 1001/* 1002 * Receive Data and Receive BD Initiator Control Registers 1003 / 1004#define BGE_RDBDI_MODE 0x2400 1005#define BGE_RDBDI_STATUS 0x2404 1006#define BGE_RX_JUMBO_RCB_HADDR_HI 0x2440 1007#define BGE_RX_JUMBO_RCB_HADDR_LO 0x2444 1008#define BGE_RX_JUMBO_RCB_MAXLEN_FLAGS 0x2448 1009#define BGE_RX_JUMBO_RCB_NICADDR 0x244C 1010#define BGE_RX_STD_RCB_HADDR_HI 0x2450 1011#define BGE_RX_STD_RCB_HADDR_LO 0x2454 1012#define BGE_RX_STD_RCB_MAXLEN_FLAGS 0x2458 1013#define BGE_RX_STD_RCB_NICADDR 0x245C 1014#define BGE_RX_MINI_RCB_HADDR_HI 0x2460 1015#define BGE_RX_MINI_RCB_HADDR_LO 0x2464 1016#define BGE_RX_MINI_RCB_MAXLEN_FLAGS 0x2468 1017#define BGE_RX_MINI_RCB_NICADDR 0x246C 1018#define BGE_RDBDI_JUMBO_RX_CONS 0x2470 1019#define BGE_RDBDI_STD_RX_CONS 0x2474 1020#define BGE_RDBDI_MINI_RX_CONS 0x2478 1021#define BGE_RDBDI_RETURN_PROD0 0x2480 1022#define BGE_RDBDI_RETURN_PROD1 0x2484 1023#define BGE_RDBDI_RETURN_PROD2 0x2488 1024#define BGE_RDBDI_RETURN_PROD3 0x248C 1025#define BGE_RDBDI_RETURN_PROD4 0x2490 1026#define BGE_RDBDI_RETURN_PROD5 0x2494 1027#define BGE_RDBDI_RETURN_PROD6 0x2498 1028#define BGE_RDBDI_RETURN_PROD7 0x249C 1029#define BGE_RDBDI_RETURN_PROD8 0x24A0 1030#define BGE_RDBDI_RETURN_PROD9 0x24A4 1031#define BGE_RDBDI_RETURN_PROD10 0x24A8 1032#define BGE_RDBDI_RETURN_PROD11 0x24AC 1033#define BGE_RDBDI_RETURN_PROD12 0x24B0 1034#define BGE_RDBDI_RETURN_PROD13 0x24B4 1035#define BGE_RDBDI_RETURN_PROD14 0x24B8 1036#define BGE_RDBDI_RETURN_PROD15 0x24BC 1037#define BGE_RDBDI_HWDIAG 0x24C0 1038* 1039 1040/* Receive Data and Receive BD Initiator Mode register / 1041#define BGE_RDBDIMODE_RESET 0x00000001 1042#define BGE_RDBDIMODE_ENABLE 0x00000002 1043#define BGE_RDBDIMODE_JUMBO_ATTN 0x00000004 1044#define BGE_RDBDIMODE_GIANT_ATTN 0x00000008 1045#define BGE_RDBDIMODE_BADRINGSZ_ATTN 0x00000010 1046* 1047/* Receive Data and Receive BD Initiator Status register / 1048#define BGE_RDBDISTAT_JUMBO_ATTN 0x00000004 1049#define BGE_RDBDISTAT_GIANT_ATTN 0x00000008 1050#define BGE_RDBDISTAT_BADRINGSZ_ATTN 0x00000010 1051* 1052 1053/* 1054 * Receive Data Completion Control registers 1055 / 1056#define BGE_RDC_MODE 0x2800 1057* 1058/* Receive Data Completion Mode register / 1059#define BGE_RDCMODE_RESET 0x00000001 1060#define BGE_RDCMODE_ENABLE 0x00000002 1061#define BGE_RDCMODE_ATTN 0x00000004 1062* 1063/* 1064 * Receive BD Initiator Control registers 1065 / 1066#define BGE_RBDI_MODE 0x2C00 1067#define BGE_RBDI_STATUS 0x2C04 1068#define BGE_RBDI_NIC_JUMBO_BD_PROD 0x2C08 1069#define BGE_RBDI_NIC_STD_BD_PROD 0x2C0C 1070#define BGE_RBDI_NIC_MINI_BD_PROD 0x2C10 1071#define BGE_RBDI_MINI_REPL_THRESH 0x2C14 1072#define BGE_RBDI_STD_REPL_THRESH 0x2C18 1073#define BGE_RBDI_JUMBO_REPL_THRESH 0x2C1C 1074* 1075/* Receive BD Initiator Mode register / 1076#define BGE_RBDIMODE_RESET 0x00000001 1077#define BGE_RBDIMODE_ENABLE 0x00000002 1078#define BGE_RBDIMODE_ATTN 0x00000004 1079* 1080/* Receive BD Initiator Status register / 1081#define BGE_RBDISTAT_ATTN 0x00000004 1082* 1083/* 1084 * Receive BD Completion Control registers 1085 / 1086#define BGE_RBDC_MODE 0x3000 1087#define BGE_RBDC_STATUS 0x3004 1088#define BGE_RBDC_JUMBO_BD_PROD 0x3008 1089#define BGE_RBDC_STD_BD_PROD 0x300C 1090#define BGE_RBDC_MINI_BD_PROD 0x3010 1091* 1092/* Receive BD completion mode register / 1093#define BGE_RBDCMODE_RESET 0x00000001 1094#define BGE_RBDCMODE_ENABLE 0x00000002 1095#define BGE_RBDCMODE_ATTN 0x00000004 1096* 1097/* Receive BD completion status register / 1098#define BGE_RBDCSTAT_ERROR 0x00000004 1099* 1100/* 1101 * Receive List Selector Control registers 1102 / 1103#define BGE_RXLS_MODE 0x3400 1104#define BGE_RXLS_STATUS 0x3404 1105* 1106/* Receive List Selector Mode register / 1107#define BGE_RXLSMODE_RESET 0x00000001 1108#define BGE_RXLSMODE_ENABLE 0x00000002 1109#define BGE_RXLSMODE_ATTN 0x00000004 1110* 1111/* Receive List Selector Status register / 1112#define BGE_RXLSSTAT_ERROR 0x00000004 1113* 1114/* 1115 * Mbuf Cluster Free registers (has nothing to do with BSD mbufs) 1116 / 1117#define BGE_MBCF_MODE 0x3800 1118#define BGE_MBCF_STATUS 0x3804 1119* 1120/* Mbuf Cluster Free mode register / 1121#define BGE_MBCFMODE_RESET 0x00000001 1122#define BGE_MBCFMODE_ENABLE 0x00000002 1123#define BGE_MBCFMODE_ATTN 0x00000004 1124* 1125/* Mbuf Cluster Free status register / 1126#define BGE_MBCFSTAT_ERROR 0x00000004 1127* 1128/* 1129 * Host Coalescing Control registers 1130 / 1131#define BGE_HCC_MODE 0x3C00 1132#define BGE_HCC_STATUS 0x3C04 1133#define BGE_HCC_RX_COAL_TICKS 0x3C08 1134#define BGE_HCC_TX_COAL_TICKS 0x3C0C 1135#define BGE_HCC_RX_MAX_COAL_BDS 0x3C10 1136#define BGE_HCC_TX_MAX_COAL_BDS 0x3C14 1137#define BGE_HCC_RX_COAL_TICKS_INT 0x3C18 / ticks during interrupt / 1138#define BGE_HCC_TX_COAL_TICKS_INT 0x3C1C / ticks during interrupt / 1139#define BGE_HCC_RX_MAX_COAL_BDS_INT 0x3C20 / BDs during interrupt / 1140#define BGE_HCC_TX_MAX_COAL_BDS_INT 0x3C24 / BDs during interrupt / 1141#define BGE_HCC_STATS_TICKS 0x3C28 1142#define BGE_HCC_STATS_ADDR_HI 0x3C30 1143#define BGE_HCC_STATS_ADDR_LO 0x3C34 1144#define BGE_HCC_STATUSBLK_ADDR_HI 0x3C38 1145#define BGE_HCC_STATUSBLK_ADDR_LO 0x3C3C 1146#define BGE_HCC_STATS_BASEADDR 0x3C40 / address in NIC memory / 1147#define BGE_HCC_STATUSBLK_BASEADDR 0x3C44 / address in NIC memory / 1148#define BGE_FLOW_ATTN 0x3C48 1149#define BGE_HCC_JUMBO_BD_CONS 0x3C50 1150#define BGE_HCC_STD_BD_CONS 0x3C54 1151#define BGE_HCC_MINI_BD_CONS 0x3C58 1152#define BGE_HCC_RX_RETURN_PROD0 0x3C80 1153#define BGE_HCC_RX_RETURN_PROD1 0x3C84 1154#define BGE_HCC_RX_RETURN_PROD2 0x3C88 1155#define BGE_HCC_RX_RETURN_PROD3 0x3C8C 1156#define BGE_HCC_RX_RETURN_PROD4 0x3C90 1157#define BGE_HCC_RX_RETURN_PROD5 0x3C94 1158#define BGE_HCC_RX_RETURN_PROD6 0x3C98 1159#define BGE_HCC_RX_RETURN_PROD7 0x3C9C 1160#define BGE_HCC_RX_RETURN_PROD8 0x3CA0 1161#define BGE_HCC_RX_RETURN_PROD9 0x3CA4 1162#define BGE_HCC_RX_RETURN_PROD10 0x3CA8 1163#define BGE_HCC_RX_RETURN_PROD11 0x3CAC 1164#define BGE_HCC_RX_RETURN_PROD12 0x3CB0 1165#define BGE_HCC_RX_RETURN_PROD13 0x3CB4 1166#define BGE_HCC_RX_RETURN_PROD14 0x3CB8 1167#define BGE_HCC_RX_RETURN_PROD15 0x3CBC 1168#define BGE_HCC_TX_BD_CONS0 0x3CC0 1169#define BGE_HCC_TX_BD_CONS1 0x3CC4 1170#define BGE_HCC_TX_BD_CONS2 0x3CC8 1171#define BGE_HCC_TX_BD_CONS3 0x3CCC 1172#define BGE_HCC_TX_BD_CONS4 0x3CD0 1173#define BGE_HCC_TX_BD_CONS5 0x3CD4 1174#define BGE_HCC_TX_BD_CONS6 0x3CD8 1175#define BGE_HCC_TX_BD_CONS7 0x3CDC 1176#define BGE_HCC_TX_BD_CONS8 0x3CE0 1177#define BGE_HCC_TX_BD_CONS9 0x3CE4 1178#define BGE_HCC_TX_BD_CONS10 0x3CE8 1179#define BGE_HCC_TX_BD_CONS11 0x3CEC 1180#define BGE_HCC_TX_BD_CONS12 0x3CF0 1181#define BGE_HCC_TX_BD_CONS13 0x3CF4 1182#define BGE_HCC_TX_BD_CONS14 0x3CF8 1183#define BGE_HCC_TX_BD_CONS15 0x3CFC 1184* 1185 1186/* Host coalescing mode register / 1187#define BGE_HCCMODE_RESET 0x00000001 1188#define BGE_HCCMODE_ENABLE 0x00000002 1189#define BGE_HCCMODE_ATTN 0x00000004 1190#define BGE_HCCMODE_COAL_NOW 0x00000008 1191#define BGE_HCCMODE_MSI_BITS 0x00000070 1192#define BGE_HCCMODE_STATBLK_SIZE 0x00000180 1193* 1194#define BGE_STATBLKSZ_FULL 0x00000000 1195#define BGE_STATBLKSZ_64BYTE 0x00000080 1196#define BGE_STATBLKSZ_32BYTE 0x00000100 1197 1198/* Host coalescing status register / 1199#define BGE_HCCSTAT_ERROR 0x00000004 1200* 1201/* Flow attention register / 1202#define BGE_FLOWATTN_MB_LOWAT 0x00000040 1203#define BGE_FLOWATTN_MEMARB 0x00000080 1204#define BGE_FLOWATTN_HOSTCOAL 0x00008000 1205#define BGE_FLOWATTN_DMADONE_DISCARD 0x00010000 1206#define BGE_FLOWATTN_RCB_INVAL 0x00020000 1207#define BGE_FLOWATTN_RXDATA_CORRUPT 0x00040000 1208#define BGE_FLOWATTN_RDBDI 0x00080000 1209#define BGE_FLOWATTN_RXLS 0x00100000 1210#define BGE_FLOWATTN_RXLP 0x00200000 1211#define BGE_FLOWATTN_RBDC 0x00400000 1212#define BGE_FLOWATTN_RBDI 0x00800000 1213#define BGE_FLOWATTN_SDC 0x08000000 1214#define BGE_FLOWATTN_SDI 0x10000000 1215#define BGE_FLOWATTN_SRS 0x20000000 1216#define BGE_FLOWATTN_SBDC 0x40000000 1217#define BGE_FLOWATTN_SBDI 0x80000000 1218* 1219/* 1220 * Memory arbiter registers 1221 / 1222#define BGE_MARB_MODE 0x4000 1223#define BGE_MARB_STATUS 0x4004 1224#define BGE_MARB_TRAPADDR_HI 0x4008 1225#define BGE_MARB_TRAPADDR_LO 0x400C 1226* 1227/* Memory arbiter mode register / 1228#define BGE_MARBMODE_RESET 0x00000001 1229#define BGE_MARBMODE_ENABLE 0x00000002 1230#define BGE_MARBMODE_TX_ADDR_TRAP 0x00000004 1231#define BGE_MARBMODE_RX_ADDR_TRAP 0x00000008 1232#define BGE_MARBMODE_DMAW1_TRAP 0x00000010 1233#define BGE_MARBMODE_DMAR1_TRAP 0x00000020 1234#define BGE_MARBMODE_RXRISC_TRAP 0x00000040 1235#define BGE_MARBMODE_TXRISC_TRAP 0x00000080 1236#define BGE_MARBMODE_PCI_TRAP 0x00000100 1237#define BGE_MARBMODE_DMAR2_TRAP 0x00000200 1238#define BGE_MARBMODE_RXQ_TRAP 0x00000400 1239#define BGE_MARBMODE_RXDI1_TRAP 0x00000800 1240#define BGE_MARBMODE_RXDI2_TRAP 0x00001000 1241#define BGE_MARBMODE_DC_GRPMEM_TRAP 0x00002000 1242#define BGE_MARBMODE_HCOAL_TRAP 0x00004000 1243#define BGE_MARBMODE_MBUF_TRAP 0x00008000 1244#define BGE_MARBMODE_TXDI_TRAP 0x00010000 1245#define BGE_MARBMODE_SDC_DMAC_TRAP 0x00020000 1246#define BGE_MARBMODE_TXBD_TRAP 0x00040000 1247#define BGE_MARBMODE_BUFFMAN_TRAP 0x00080000 1248#define BGE_MARBMODE_DMAW2_TRAP 0x00100000 1249#define BGE_MARBMODE_XTSSRAM_ROFLO_TRAP 0x00200000 1250#define BGE_MARBMODE_XTSSRAM_RUFLO_TRAP 0x00400000 1251#define BGE_MARBMODE_XTSSRAM_WOFLO_TRAP 0x00800000 1252#define BGE_MARBMODE_XTSSRAM_WUFLO_TRAP 0x01000000 1253#define BGE_MARBMODE_XTSSRAM_PERR_TRAP 0x02000000 1254* 1255/* Memory arbiter status register / 1256#define BGE_MARBSTAT_TX_ADDR_TRAP 0x00000004 1257#define BGE_MARBSTAT_RX_ADDR_TRAP 0x00000008 1258#define BGE_MARBSTAT_DMAW1_TRAP 0x00000010 1259#define BGE_MARBSTAT_DMAR1_TRAP 0x00000020 1260#define BGE_MARBSTAT_RXRISC_TRAP 0x00000040 1261#define BGE_MARBSTAT_TXRISC_TRAP 0x00000080 1262#define BGE_MARBSTAT_PCI_TRAP 0x00000100 1263#define BGE_MARBSTAT_DMAR2_TRAP 0x00000200 1264#define BGE_MARBSTAT_RXQ_TRAP 0x00000400 1265#define BGE_MARBSTAT_RXDI1_TRAP 0x00000800 1266#define BGE_MARBSTAT_RXDI2_TRAP 0x00001000 1267#define BGE_MARBSTAT_DC_GRPMEM_TRAP 0x00002000 1268#define BGE_MARBSTAT_HCOAL_TRAP 0x00004000 1269#define BGE_MARBSTAT_MBUF_TRAP 0x00008000 1270#define BGE_MARBSTAT_TXDI_TRAP 0x00010000 1271#define BGE_MARBSTAT_SDC_DMAC_TRAP 0x00020000 1272#define BGE_MARBSTAT_TXBD_TRAP 0x00040000 1273#define BGE_MARBSTAT_BUFFMAN_TRAP 0x00080000 1274#define BGE_MARBSTAT_DMAW2_TRAP 0x00100000 1275#define BGE_MARBSTAT_XTSSRAM_ROFLO_TRAP 0x00200000 1276#define BGE_MARBSTAT_XTSSRAM_RUFLO_TRAP 0x00400000 1277#define BGE_MARBSTAT_XTSSRAM_WOFLO_TRAP 0x00800000 1278#define BGE_MARBSTAT_XTSSRAM_WUFLO_TRAP 0x01000000 1279#define BGE_MARBSTAT_XTSSRAM_PERR_TRAP 0x02000000 1280* 1281/* 1282 * Buffer manager control registers 1283 / 1284#define BGE_BMAN_MODE 0x4400 1285#define BGE_BMAN_STATUS 0x4404 1286#define BGE_BMAN_MBUFPOOL_BASEADDR 0x4408 1287#define BGE_BMAN_MBUFPOOL_LEN 0x440C 1288#define BGE_BMAN_MBUFPOOL_READDMA_LOWAT 0x4410 1289#define BGE_BMAN_MBUFPOOL_MACRX_LOWAT 0x4414 1290#define BGE_BMAN_MBUFPOOL_HIWAT 0x4418 1291#define BGE_BMAN_RXCPU_MBALLOC_REQ 0x441C 1292#define BGE_BMAN_RXCPU_MBALLOC_RESP 0x4420 1293#define BGE_BMAN_TXCPU_MBALLOC_REQ 0x4424 1294#define BGE_BMAN_TXCPU_MBALLOC_RESP 0x4428 1295#define BGE_BMAN_DMA_DESCPOOL_BASEADDR 0x442C 1296#define BGE_BMAN_DMA_DESCPOOL_LEN 0x4430 1297#define BGE_BMAN_DMA_DESCPOOL_LOWAT 0x4434 1298#define BGE_BMAN_DMA_DESCPOOL_HIWAT 0x4438 1299#define BGE_BMAN_RXCPU_DMAALLOC_REQ 0x443C 1300#define BGE_BMAN_RXCPU_DMAALLOC_RESP 0x4440 1301#define BGE_BMAN_TXCPU_DMAALLOC_REQ 0x4444 1302#define BGE_BMAN_TXCPU_DMALLLOC_RESP 0x4448 1303#define BGE_BMAN_HWDIAG_1 0x444C 1304#define BGE_BMAN_HWDIAG_2 0x4450 1305#define BGE_BMAN_HWDIAG_3 0x4454 1306* 1307/* Buffer manager mode register / 1308#define BGE_BMANMODE_RESET 0x00000001 1309#define BGE_BMANMODE_ENABLE 0x00000002 1310#define BGE_BMANMODE_ATTN 0x00000004 1311#define BGE_BMANMODE_TESTMODE 0x00000008 1312#define BGE_BMANMODE_LOMBUF_ATTN 0x00000010 1313* 1314/* Buffer manager status register / 1315#define BGE_BMANSTAT_ERRO 0x00000004 1316#define BGE_BMANSTAT_LOWMBUF_ERROR 0x00000010 1317* 1318 1319/* 1320 * Read DMA Control registers 1321 / 1322#define BGE_RDMA_MODE 0x4800 1323#define BGE_RDMA_STATUS 0x4804 1324* 1325/* Read DMA mode register / 1326#define BGE_RDMAMODE_RESET 0x00000001 1327#define BGE_RDMAMODE_ENABLE 0x00000002 1328#define BGE_RDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1329#define BGE_RDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1330#define BGE_RDMAMODE_PCI_PERR_ATTN 0x00000010 1331#define BGE_RDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1332#define BGE_RDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1333#define BGE_RDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1334#define BGE_RDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1335#define BGE_RDMAMODE_LOCWRITE_TOOBIG 0x00000200 1336#define BGE_RDMAMODE_ALL_ATTNS 0x000003FC 1337* 1338/* Read DMA status register / 1339#define BGE_RDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1340#define BGE_RDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1341#define BGE_RDMASTAT_PCI_PERR_ATTN 0x00000010 1342#define BGE_RDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1343#define BGE_RDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1344#define BGE_RDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1345#define BGE_RDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1346#define BGE_RDMASTAT_LOCWRITE_TOOBIG 0x00000200 1347* 1348/* 1349 * Write DMA control registers 1350 / 1351#define BGE_WDMA_MODE 0x4C00 1352#define BGE_WDMA_STATUS 0x4C04 1353* 1354/* Write DMA mode register / 1355#define BGE_WDMAMODE_RESET 0x00000001 1356#define BGE_WDMAMODE_ENABLE 0x00000002 1357#define BGE_WDMAMODE_PCI_TGT_ABRT_ATTN 0x00000004 1358#define BGE_WDMAMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1359#define BGE_WDMAMODE_PCI_PERR_ATTN 0x00000010 1360#define BGE_WDMAMODE_PCI_ADDROFLOW_ATTN 0x00000020 1361#define BGE_WDMAMODE_PCI_FIFOOFLOW_ATTN 0x00000040 1362#define BGE_WDMAMODE_PCI_FIFOUFLOW_ATTN 0x00000080 1363#define BGE_WDMAMODE_PCI_FIFOOREAD_ATTN 0x00000100 1364#define BGE_WDMAMODE_LOCREAD_TOOBIG 0x00000200 1365#define BGE_WDMAMODE_ALL_ATTNS 0x000003FC 1366* 1367/* Write DMA status register / 1368#define BGE_WDMASTAT_PCI_TGT_ABRT_ATTN 0x00000004 1369#define BGE_WDMASTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1370#define BGE_WDMASTAT_PCI_PERR_ATTN 0x00000010 1371#define BGE_WDMASTAT_PCI_ADDROFLOW_ATTN 0x00000020 1372#define BGE_WDMASTAT_PCI_FIFOOFLOW_ATTN 0x00000040 1373#define BGE_WDMASTAT_PCI_FIFOUFLOW_ATTN 0x00000080 1374#define BGE_WDMASTAT_PCI_FIFOOREAD_ATTN 0x00000100 1375#define BGE_WDMASTAT_LOCREAD_TOOBIG 0x00000200 1376* 1377 1378/* 1379 * RX CPU registers 1380 / 1381#define BGE_RXCPU_MODE 0x5000 1382#define BGE_RXCPU_STATUS 0x5004 1383#define BGE_RXCPU_PC 0x501C 1384* 1385/* RX CPU mode register / 1386#define BGE_RXCPUMODE_RESET 0x00000001 1387#define BGE_RXCPUMODE_SINGLESTEP 0x00000002 1388#define BGE_RXCPUMODE_P0_DATAHLT_ENB 0x00000004 1389#define BGE_RXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1390#define BGE_RXCPUMODE_WR_POSTBUF_ENB 0x00000010 1391#define BGE_RXCPUMODE_DATACACHE_ENB 0x00000020 1392#define BGE_RXCPUMODE_ROMFAIL 0x00000040 1393#define BGE_RXCPUMODE_WATCHDOG_ENB 0x00000080 1394#define BGE_RXCPUMODE_INSTRCACHE_PRF 0x00000100 1395#define BGE_RXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1396#define BGE_RXCPUMODE_HALTCPU 0x00000400 1397#define BGE_RXCPUMODE_INVDATAHLT_ENB 0x00000800 1398#define BGE_RXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1399#define BGE_RXCPUMODE_RADDRTRAPHLT_ENB 0x00002000 1400* 1401/* RX CPU status register / 1402#define BGE_RXCPUSTAT_HW_BREAKPOINT 0x00000001 1403#define BGE_RXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1404#define BGE_RXCPUSTAT_INVALID_INSTR 0x00000004 1405#define BGE_RXCPUSTAT_P0_DATAREF 0x00000008 1406#define BGE_RXCPUSTAT_P0_INSTRREF 0x00000010 1407#define BGE_RXCPUSTAT_INVALID_DATAACC 0x00000020 1408#define BGE_RXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1409#define BGE_RXCPUSTAT_BAD_MEMALIGN 0x00000080 1410#define BGE_RXCPUSTAT_MADDR_TRAP 0x00000100 1411#define BGE_RXCPUSTAT_REGADDR_TRAP 0x00000200 1412#define BGE_RXCPUSTAT_DATAACC_STALL 0x00001000 1413#define BGE_RXCPUSTAT_INSTRFETCH_STALL 0x00002000 1414#define BGE_RXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1415#define BGE_RXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1416#define BGE_RXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1417#define BGE_RXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1418#define BGE_RXCPUSTAT_BLOCKING_READ 0x80000000 1419* 1420 1421/* 1422 * TX CPU registers 1423 / 1424#define BGE_TXCPU_MODE 0x5400 1425#define BGE_TXCPU_STATUS 0x5404 1426#define BGE_TXCPU_PC 0x541C 1427* 1428/* TX CPU mode register / 1429#define BGE_TXCPUMODE_RESET 0x00000001 1430#define BGE_TXCPUMODE_SINGLESTEP 0x00000002 1431#define BGE_TXCPUMODE_P0_DATAHLT_ENB 0x00000004 1432#define BGE_TXCPUMODE_P0_INSTRHLT_ENB 0x00000008 1433#define BGE_TXCPUMODE_WR_POSTBUF_ENB 0x00000010 1434#define BGE_TXCPUMODE_DATACACHE_ENB 0x00000020 1435#define BGE_TXCPUMODE_ROMFAIL 0x00000040 1436#define BGE_TXCPUMODE_WATCHDOG_ENB 0x00000080 1437#define BGE_TXCPUMODE_INSTRCACHE_PRF 0x00000100 1438#define BGE_TXCPUMODE_INSTRCACHE_FLUSH 0x00000200 1439#define BGE_TXCPUMODE_HALTCPU 0x00000400 1440#define BGE_TXCPUMODE_INVDATAHLT_ENB 0x00000800 1441#define BGE_TXCPUMODE_MADDRTRAPHLT_ENB 0x00001000 1442* 1443/* TX CPU status register / 1444#define BGE_TXCPUSTAT_HW_BREAKPOINT 0x00000001 1445#define BGE_TXCPUSTAT_HLTINSTR_EXECUTED 0x00000002 1446#define BGE_TXCPUSTAT_INVALID_INSTR 0x00000004 1447#define BGE_TXCPUSTAT_P0_DATAREF 0x00000008 1448#define BGE_TXCPUSTAT_P0_INSTRREF 0x00000010 1449#define BGE_TXCPUSTAT_INVALID_DATAACC 0x00000020 1450#define BGE_TXCPUSTAT_INVALID_INSTRFTCH 0x00000040 1451#define BGE_TXCPUSTAT_BAD_MEMALIGN 0x00000080 1452#define BGE_TXCPUSTAT_MADDR_TRAP 0x00000100 1453#define BGE_TXCPUSTAT_REGADDR_TRAP 0x00000200 1454#define BGE_TXCPUSTAT_DATAACC_STALL 0x00001000 1455#define BGE_TXCPUSTAT_INSTRFETCH_STALL 0x00002000 1456#define BGE_TXCPUSTAT_MA_WR_FIFOOFLOW 0x08000000 1457#define BGE_TXCPUSTAT_MA_RD_FIFOOFLOW 0x10000000 1458#define BGE_TXCPUSTAT_MA_DATAMASK_OFLOW 0x20000000 1459#define BGE_TXCPUSTAT_MA_REQ_FIFOOFLOW 0x40000000 1460#define BGE_TXCPUSTAT_BLOCKING_READ 0x80000000 1461* 1462 1463/* 1464 * Low priority mailbox registers 1465 / 1466#define BGE_LPMBX_IRQ0_HI 0x5800 1467#define BGE_LPMBX_IRQ0_LO 0x5804 1468#define BGE_LPMBX_IRQ1_HI 0x5808 1469#define BGE_LPMBX_IRQ1_LO 0x580C 1470#define BGE_LPMBX_IRQ2_HI 0x5810 1471#define BGE_LPMBX_IRQ2_LO 0x5814 1472#define BGE_LPMBX_IRQ3_HI 0x5818 1473#define BGE_LPMBX_IRQ3_LO 0x581C 1474#define BGE_LPMBX_GEN0_HI 0x5820 1475#define BGE_LPMBX_GEN0_LO 0x5824 1476#define BGE_LPMBX_GEN1_HI 0x5828 1477#define BGE_LPMBX_GEN1_LO 0x582C 1478#define BGE_LPMBX_GEN2_HI 0x5830 1479#define BGE_LPMBX_GEN2_LO 0x5834 1480#define BGE_LPMBX_GEN3_HI 0x5828 1481#define BGE_LPMBX_GEN3_LO 0x582C 1482#define BGE_LPMBX_GEN4_HI 0x5840 1483#define BGE_LPMBX_GEN4_LO 0x5844 1484#define BGE_LPMBX_GEN5_HI 0x5848 1485#define BGE_LPMBX_GEN5_LO 0x584C 1486#define BGE_LPMBX_GEN6_HI 0x5850 1487#define BGE_LPMBX_GEN6_LO 0x5854 1488#define BGE_LPMBX_GEN7_HI 0x5858 1489#define BGE_LPMBX_GEN7_LO 0x585C 1490#define BGE_LPMBX_RELOAD_STATS_HI 0x5860 1491#define BGE_LPMBX_RELOAD_STATS_LO 0x5864 1492#define BGE_LPMBX_RX_STD_PROD_HI 0x5868 1493#define BGE_LPMBX_RX_STD_PROD_LO 0x586C 1494#define BGE_LPMBX_RX_JUMBO_PROD_HI 0x5870 1495#define BGE_LPMBX_RX_JUMBO_PROD_LO 0x5874 1496#define BGE_LPMBX_RX_MINI_PROD_HI 0x5878 1497#define BGE_LPMBX_RX_MINI_PROD_LO 0x587C 1498#define BGE_LPMBX_RX_CONS0_HI 0x5880 1499#define BGE_LPMBX_RX_CONS0_LO 0x5884 1500#define BGE_LPMBX_RX_CONS1_HI 0x5888 1501#define BGE_LPMBX_RX_CONS1_LO 0x588C 1502#define BGE_LPMBX_RX_CONS2_HI 0x5890 1503#define BGE_LPMBX_RX_CONS2_LO 0x5894 1504#define BGE_LPMBX_RX_CONS3_HI 0x5898 1505#define BGE_LPMBX_RX_CONS3_LO 0x589C 1506#define BGE_LPMBX_RX_CONS4_HI 0x58A0 1507#define BGE_LPMBX_RX_CONS4_LO 0x58A4 1508#define BGE_LPMBX_RX_CONS5_HI 0x58A8 1509#define BGE_LPMBX_RX_CONS5_LO 0x58AC 1510#define BGE_LPMBX_RX_CONS6_HI 0x58B0 1511#define BGE_LPMBX_RX_CONS6_LO 0x58B4 1512#define BGE_LPMBX_RX_CONS7_HI 0x58B8 1513#define BGE_LPMBX_RX_CONS7_LO 0x58BC 1514#define BGE_LPMBX_RX_CONS8_HI 0x58C0 1515#define BGE_LPMBX_RX_CONS8_LO 0x58C4 1516#define BGE_LPMBX_RX_CONS9_HI 0x58C8 1517#define BGE_LPMBX_RX_CONS9_LO 0x58CC 1518#define BGE_LPMBX_RX_CONS10_HI 0x58D0 1519#define BGE_LPMBX_RX_CONS10_LO 0x58D4 1520#define BGE_LPMBX_RX_CONS11_HI 0x58D8 1521#define BGE_LPMBX_RX_CONS11_LO 0x58DC 1522#define BGE_LPMBX_RX_CONS12_HI 0x58E0 1523#define BGE_LPMBX_RX_CONS12_LO 0x58E4 1524#define BGE_LPMBX_RX_CONS13_HI 0x58E8 1525#define BGE_LPMBX_RX_CONS13_LO 0x58EC 1526#define BGE_LPMBX_RX_CONS14_HI 0x58F0 1527#define BGE_LPMBX_RX_CONS14_LO 0x58F4 1528#define BGE_LPMBX_RX_CONS15_HI 0x58F8 1529#define BGE_LPMBX_RX_CONS15_LO 0x58FC 1530#define BGE_LPMBX_TX_HOST_PROD0_HI 0x5900 1531#define BGE_LPMBX_TX_HOST_PROD0_LO 0x5904 1532#define BGE_LPMBX_TX_HOST_PROD1_HI 0x5908 1533#define BGE_LPMBX_TX_HOST_PROD1_LO 0x590C 1534#define BGE_LPMBX_TX_HOST_PROD2_HI 0x5910 1535#define BGE_LPMBX_TX_HOST_PROD2_LO 0x5914 1536#define BGE_LPMBX_TX_HOST_PROD3_HI 0x5918 1537#define BGE_LPMBX_TX_HOST_PROD3_LO 0x591C 1538#define BGE_LPMBX_TX_HOST_PROD4_HI 0x5920 1539#define BGE_LPMBX_TX_HOST_PROD4_LO 0x5924 1540#define BGE_LPMBX_TX_HOST_PROD5_HI 0x5928 1541#define BGE_LPMBX_TX_HOST_PROD5_LO 0x592C 1542#define BGE_LPMBX_TX_HOST_PROD6_HI 0x5930 1543#define BGE_LPMBX_TX_HOST_PROD6_LO 0x5934 1544#define BGE_LPMBX_TX_HOST_PROD7_HI 0x5938 1545#define BGE_LPMBX_TX_HOST_PROD7_LO 0x593C 1546#define BGE_LPMBX_TX_HOST_PROD8_HI 0x5940 1547#define BGE_LPMBX_TX_HOST_PROD8_LO 0x5944 1548#define BGE_LPMBX_TX_HOST_PROD9_HI 0x5948 1549#define BGE_LPMBX_TX_HOST_PROD9_LO 0x594C 1550#define BGE_LPMBX_TX_HOST_PROD10_HI 0x5950 1551#define BGE_LPMBX_TX_HOST_PROD10_LO 0x5954 1552#define BGE_LPMBX_TX_HOST_PROD11_HI 0x5958 1553#define BGE_LPMBX_TX_HOST_PROD11_LO 0x595C 1554#define BGE_LPMBX_TX_HOST_PROD12_HI 0x5960 1555#define BGE_LPMBX_TX_HOST_PROD12_LO 0x5964 1556#define BGE_LPMBX_TX_HOST_PROD13_HI 0x5968 1557#define BGE_LPMBX_TX_HOST_PROD13_LO 0x596C 1558#define BGE_LPMBX_TX_HOST_PROD14_HI 0x5970 1559#define BGE_LPMBX_TX_HOST_PROD14_LO 0x5974 1560#define BGE_LPMBX_TX_HOST_PROD15_HI 0x5978 1561#define BGE_LPMBX_TX_HOST_PROD15_LO 0x597C 1562#define BGE_LPMBX_TX_NIC_PROD0_HI 0x5980 1563#define BGE_LPMBX_TX_NIC_PROD0_LO 0x5984 1564#define BGE_LPMBX_TX_NIC_PROD1_HI 0x5988 1565#define BGE_LPMBX_TX_NIC_PROD1_LO 0x598C 1566#define BGE_LPMBX_TX_NIC_PROD2_HI 0x5990 1567#define BGE_LPMBX_TX_NIC_PROD2_LO 0x5994 1568#define BGE_LPMBX_TX_NIC_PROD3_HI 0x5998 1569#define BGE_LPMBX_TX_NIC_PROD3_LO 0x599C 1570#define BGE_LPMBX_TX_NIC_PROD4_HI 0x59A0 1571#define BGE_LPMBX_TX_NIC_PROD4_LO 0x59A4 1572#define BGE_LPMBX_TX_NIC_PROD5_HI 0x59A8 1573#define BGE_LPMBX_TX_NIC_PROD5_LO 0x59AC 1574#define BGE_LPMBX_TX_NIC_PROD6_HI 0x59B0 1575#define BGE_LPMBX_TX_NIC_PROD6_LO 0x59B4 1576#define BGE_LPMBX_TX_NIC_PROD7_HI 0x59B8 1577#define BGE_LPMBX_TX_NIC_PROD7_LO 0x59BC 1578#define BGE_LPMBX_TX_NIC_PROD8_HI 0x59C0 1579#define BGE_LPMBX_TX_NIC_PROD8_LO 0x59C4 1580#define BGE_LPMBX_TX_NIC_PROD9_HI 0x59C8 1581#define BGE_LPMBX_TX_NIC_PROD9_LO 0x59CC 1582#define BGE_LPMBX_TX_NIC_PROD10_HI 0x59D0 1583#define BGE_LPMBX_TX_NIC_PROD10_LO 0x59D4 1584#define BGE_LPMBX_TX_NIC_PROD11_HI 0x59D8 1585#define BGE_LPMBX_TX_NIC_PROD11_LO 0x59DC 1586#define BGE_LPMBX_TX_NIC_PROD12_HI 0x59E0 1587#define BGE_LPMBX_TX_NIC_PROD12_LO 0x59E4 1588#define BGE_LPMBX_TX_NIC_PROD13_HI 0x59E8 1589#define BGE_LPMBX_TX_NIC_PROD13_LO 0x59EC 1590#define BGE_LPMBX_TX_NIC_PROD14_HI 0x59F0 1591#define BGE_LPMBX_TX_NIC_PROD14_LO 0x59F4 1592#define BGE_LPMBX_TX_NIC_PROD15_HI 0x59F8 1593#define BGE_LPMBX_TX_NIC_PROD15_LO 0x59FC 1594* 1595/* 1596 * Flow throw Queue reset register 1597 / 1598#define BGE_FTQ_RESET 0x5C00 1599* 1600#define BGE_FTQRESET_DMAREAD 0x00000002 1601#define BGE_FTQRESET_DMAHIPRIO_RD 0x00000004 1602#define BGE_FTQRESET_DMADONE 0x00000010 1603#define BGE_FTQRESET_SBDC 0x00000020 1604#define BGE_FTQRESET_SDI 0x00000040 1605#define BGE_FTQRESET_WDMA 0x00000080 1606#define BGE_FTQRESET_DMAHIPRIO_WR 0x00000100 1607#define BGE_FTQRESET_TYPE1_SOFTWARE 0x00000200 1608#define BGE_FTQRESET_SDC 0x00000400 1609#define BGE_FTQRESET_HCC 0x00000800 1610#define BGE_FTQRESET_TXFIFO 0x00001000 1611#define BGE_FTQRESET_MBC 0x00002000 1612#define BGE_FTQRESET_RBDC 0x00004000 1613#define BGE_FTQRESET_RXLP 0x00008000 1614#define BGE_FTQRESET_RDBDI 0x00010000 1615#define BGE_FTQRESET_RDC 0x00020000 1616#define BGE_FTQRESET_TYPE2_SOFTWARE 0x00040000 1617 1618/* 1619 * Message Signaled Interrupt registers 1620 / 1621#define BGE_MSI_MODE 0x6000 1622#define BGE_MSI_STATUS 0x6004 1623#define BGE_MSI_FIFOACCESS 0x6008 1624* 1625/* MSI mode register / 1626#define BGE_MSIMODE_RESET 0x00000001 1627#define BGE_MSIMODE_ENABLE 0x00000002 1628#define BGE_MSIMODE_PCI_TGT_ABRT_ATTN 0x00000004 1629#define BGE_MSIMODE_PCI_MSTR_ABRT_ATTN 0x00000008 1630#define BGE_MSIMODE_PCI_PERR_ATTN 0x00000010 1631#define BGE_MSIMODE_MSI_FIFOUFLOW_ATTN 0x00000020 1632#define BGE_MSIMODE_MSI_FIFOOFLOW_ATTN 0x00000040 1633* 1634/* MSI status register / 1635#define BGE_MSISTAT_PCI_TGT_ABRT_ATTN 0x00000004 1636#define BGE_MSISTAT_PCI_MSTR_ABRT_ATTN 0x00000008 1637#define BGE_MSISTAT_PCI_PERR_ATTN 0x00000010 1638#define BGE_MSISTAT_MSI_FIFOUFLOW_ATTN 0x00000020 1639#define BGE_MSISTAT_MSI_FIFOOFLOW_ATTN 0x00000040 1640* 1641 1642/* 1643 * DMA Completion registers 1644 / 1645#define BGE_DMAC_MODE 0x6400 1646* 1647/* DMA Completion mode register / 1648#define BGE_DMACMODE_RESET 0x00000001 1649#define BGE_DMACMODE_ENABLE 0x00000002 1650* 1651 1652/* 1653 * General control registers. 1654 / 1655#define BGE_MODE_CTL 0x6800 1656#define BGE_MISC_CFG 0x6804 1657#define BGE_MISC_LOCAL_CTL 0x6808 1658#define BGE_CPU_EVENT 0x6810 1659#define BGE_EE_ADDR 0x6838 1660#define BGE_EE_DATA 0x683C 1661#define BGE_EE_CTL 0x6840 1662#define BGE_MDI_CTL 0x6844 1663#define BGE_EE_DELAY 0x6848 1664* 1665/* Mode control register / 1666#define BGE_MODECTL_INT_SNDCOAL_ONLY 0x00000001 1667#define BGE_MODECTL_BYTESWAP_NONFRAME 0x00000002 1668#define BGE_MODECTL_WORDSWAP_NONFRAME 0x00000004 1669#define BGE_MODECTL_BYTESWAP_DATA 0x00000010 1670#define BGE_MODECTL_WORDSWAP_DATA 0x00000020 1671#define BGE_MODECTL_NO_FRAME_CRACKING 0x00000200 1672#define BGE_MODECTL_NO_RX_CRC 0x00000400 1673#define BGE_MODECTL_RX_BADFRAMES 0x00000800 1674#define BGE_MODECTL_NO_TX_INTR 0x00002000 1675#define BGE_MODECTL_NO_RX_INTR 0x00004000 1676#define BGE_MODECTL_FORCE_PCI32 0x00008000 1677#define BGE_MODECTL_STACKUP 0x00010000 1678#define BGE_MODECTL_HOST_SEND_BDS 0x00020000 1679#define BGE_MODECTL_TX_NO_PHDR_CSUM 0x00100000 1680#define BGE_MODECTL_RX_NO_PHDR_CSUM 0x00800000 1681#define BGE_MODECTL_TX_ATTN_INTR 0x01000000 1682#define BGE_MODECTL_RX_ATTN_INTR 0x02000000 1683#define BGE_MODECTL_MAC_ATTN_INTR 0x04000000 1684#define BGE_MODECTL_DMA_ATTN_INTR 0x08000000 1685#define BGE_MODECTL_FLOWCTL_ATTN_INTR 0x10000000 1686#define BGE_MODECTL_4X_SENDRING_SZ 0x20000000 1687#define BGE_MODECTL_FW_PROCESS_MCASTS 0x40000000 1688* 1689/* Misc. config register / 1690#define BGE_MISCCFG_RESET_CORE_CLOCKS 0x00000001 1691#define BGE_MISCCFG_TIMER_PRESCALER 0x000000FE 1692* 1693#define BGE_32BITTIME_66MHZ (0x41 << 1) 1694 1695/* Misc. Local Control / 1696#define BGE_MLC_INTR_STATE 0x00000001 1697#define BGE_MLC_INTR_CLR 0x00000002 1698#define BGE_MLC_INTR_SET 0x00000004 1699#define BGE_MLC_INTR_ONATTN 0x00000008 1700#define BGE_MLC_MISCIO_IN0 0x00000100 1701#define BGE_MLC_MISCIO_IN1 0x00000200 1702#define BGE_MLC_MISCIO_IN2 0x00000400 1703#define BGE_MLC_MISCIO_OUTEN0 0x00000800 1704#define BGE_MLC_MISCIO_OUTEN1 0x00001000 1705#define BGE_MLC_MISCIO_OUTEN2 0x00002000 1706#define BGE_MLC_MISCIO_OUT0 0x00004000 1707#define BGE_MLC_MISCIO_OUT1 0x00008000 1708#define BGE_MLC_MISCIO_OUT2 0x00010000 1709#define BGE_MLC_EXTRAM_ENB 0x00020000 1710#define BGE_MLC_SRAM_SIZE 0x001C0000 1711#define BGE_MLC_BANK_SEL 0x00200000 / 0 = 2 banks, 1 == 1 / 1712#define BGE_MLC_SSRAM_TYPE 0x00400000 / 1 = ZBT, 0 = standard / 1713#define BGE_MLC_SSRAM_CYC_DESEL 0x00800000 1714#define BGE_MLC_AUTO_EEPROM 0x01000000 1715* 1716#define BGE_SSRAMSIZE_256KB 0x00000000 1717#define BGE_SSRAMSIZE_512KB 0x00040000 1718#define BGE_SSRAMSIZE_1MB 0x00080000 1719#define BGE_SSRAMSIZE_2MB 0x000C0000 1720#define BGE_SSRAMSIZE_4MB 0x00100000 1721#define BGE_SSRAMSIZE_8MB 0x00140000 1722#define BGE_SSRAMSIZE_16M 0x00180000 1723 1724/* EEPROM address register / 1725#define BGE_EEADDR_ADDRESS 0x0000FFFC 1726#define BGE_EEADDR_HALFCLK 0x01FF0000 1727#define BGE_EEADDR_START 0x02000000 1728#define BGE_EEADDR_DEVID 0x1C000000 1729#define BGE_EEADDR_RESET 0x20000000 1730#define BGE_EEADDR_DONE 0x40000000 1731#define BGE_EEADDR_RW 0x80000000 / 1 = rd, 0 = wr / 1732* 1733#define BGE_EEDEVID(x) ((x & 7) << 26) 1734#define BGE_EEHALFCLK(x) ((x & 0x1FF) << 16) 1735#define BGE_HALFCLK_384SCL 0x60 1736#define BGE_EE_READCMD \ 1737 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1738 BGE_EEADDR_START\|BGE_EEADDR_RW\|BGE_EEADDR_DONE) 1739#define BGE_EE_WRCMD \ 1740 (BGE_EEHALFCLK(BGE_HALFCLK_384SCL)\|BGE_EEDEVID(0)\| \ 1741 BGE_EEADDR_START\|BGE_EEADDR_DONE) 1742 1743/* EEPROM Control register / 1744#define BGE_EECTL_CLKOUT_TRISTATE 0x00000001 1745#define BGE_EECTL_CLKOUT 0x00000002 1746#define BGE_EECTL_CLKIN 0x00000004 1747#define BGE_EECTL_DATAOUT_TRISTATE 0x00000008 1748#define BGE_EECTL_DATAOUT 0x00000010 1749#define BGE_EECTL_DATAIN 0x00000020 1750* 1751/* MDI (MII/GMII) access register / 1752#define BGE_MDI_DATA 0x00000001 1753#define BGE_MDI_DIR 0x00000002 1754#define BGE_MDI_SEL 0x00000004 1755#define BGE_MDI_CLK 0x00000008 1756* 1757#define BGE_MEMWIN_START 0x00008000 1758#define BGE_MEMWIN_END 0x0000FFFF 1759 1760 1761#define BGE_MEMWIN_READ(sc, x, val) \ 1762 do { \ 1763 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1764 (0xFFFF0000 & x), 4); \ 1765 val = CSR_READ_4(sc, BGE_MEMWIN_START + (x & 0xFFFF)); \ 1766 } while(0) 1767 1768#define BGE_MEMWIN_WRITE(sc, x, val) \ 1769 do { \ 1770 pci_write_config(sc->bge_dev, BGE_PCI_MEMWIN_BASEADDR, \ 1771 (0xFFFF0000 & x), 4); \ 1772 CSR_WRITE_4(sc, BGE_MEMWIN_START + (x & 0xFFFF), val); \ 1773 } while(0) 1774 1775/* 1776 * This magic number is written to the firmware mailbox at 0xb50 1777 * before a software reset is issued. After the internal firmware 1778 * has completed its initialization it will write the opposite of 1779 * this value, ~BGE_MAGIC_NUMBER, to the same location, allowing the 1780 * driver to synchronize with the firmware. 1781 / 1782#define BGE_MAGIC_NUMBER 0x4B657654 1783* 1784typedef struct { 1785 uint32_t bge_addr_hi; 1786 uint32_t bge_addr_lo; 1787} bge_hostaddr; 1788 1789#define BGE_HOSTADDR(x, y) \ 1790 do { \ 1791 (x).bge_addr_lo = ((uint64_t) (y) & 0xffffffff); \ 1792 (x).bge_addr_hi = ((uint64_t) (y) >> 32); \ 1793 } while(0) 1794 1795#define BGE_ADDR_LO(y) \ 1796 ((uint64_t) (y) & 0xFFFFFFFF) 1797#define BGE_ADDR_HI(y) \ 1798 ((uint64_t) (y) >> 32) 1799 1800/* Ring control block structure / 1801struct bge_rcb { 1802* bge_hostaddr bge_hostaddr; 1803 uint32_t bge_maxlen_flags; 1804 uint32_t bge_nicaddr; 1805}; 1806 1807#define RCB_WRITE_4(sc, rcb, offset, val) \ 1808 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, \ 1809 rcb + offsetof(struct bge_rcb, offset), val) 1810#define BGE_RCB_MAXLEN_FLAGS(maxlen, flags) ((maxlen) << 16 \| (flags)) 1811 1812#define BGE_RCB_FLAG_USE_EXT_RX_BD 0x0001 1813#define BGE_RCB_FLAG_RING_DISABLED 0x0002 1814 1815struct bge_tx_bd { 1816 bge_hostaddr bge_addr; 1817#if BYTE_ORDER == LITTLE_ENDIAN 1818 uint16_t bge_flags; 1819 uint16_t bge_len; 1820 uint16_t bge_vlan_tag; 1821 uint16_t bge_rsvd; 1822#else 1823 uint16_t bge_len; 1824 uint16_t bge_flags; 1825 uint16_t bge_rsvd; 1826 uint16_t bge_vlan_tag; 1827#endif 1828}; 1829 1830#define BGE_TXBDFLAG_TCP_UDP_CSUM 0x0001 1831#define BGE_TXBDFLAG_IP_CSUM 0x0002 1832#define BGE_TXBDFLAG_END 0x0004 1833#define BGE_TXBDFLAG_IP_FRAG 0x0008 1834#define BGE_TXBDFLAG_IP_FRAG_END 0x0010 1835#define BGE_TXBDFLAG_VLAN_TAG 0x0040 1836#define BGE_TXBDFLAG_COAL_NOW 0x0080 1837#define BGE_TXBDFLAG_CPU_PRE_DMA 0x0100 1838#define BGE_TXBDFLAG_CPU_POST_DMA 0x0200 1839#define BGE_TXBDFLAG_INSERT_SRC_ADDR 0x1000 1840#define BGE_TXBDFLAG_CHOOSE_SRC_ADDR 0x6000 1841#define BGE_TXBDFLAG_NO_CRC 0x8000 1842 1843#define BGE_NIC_TXRING_ADDR(ringno, size) \ 1844 BGE_SEND_RING_1_TO_4 + \ 1845 ((ringno * sizeof(struct bge_tx_bd) * size) / 4) 1846 1847struct bge_rx_bd { 1848 bge_hostaddr bge_addr; 1849#if BYTE_ORDER == LITTLE_ENDIAN 1850 uint16_t bge_len; 1851 uint16_t bge_idx; 1852 uint16_t bge_flags; 1853 uint16_t bge_type; 1854 uint16_t bge_tcp_udp_csum; 1855 uint16_t bge_ip_csum; 1856 uint16_t bge_vlan_tag; 1857 uint16_t bge_error_flag; 1858#else 1859 uint16_t bge_idx; 1860 uint16_t bge_len; 1861 uint16_t bge_type; 1862 uint16_t bge_flags; 1863 uint16_t bge_ip_csum; 1864 uint16_t bge_tcp_udp_csum; 1865 uint16_t bge_error_flag; 1866 uint16_t bge_vlan_tag; 1867#endif 1868 uint32_t bge_rsvd; 1869 uint32_t bge_opaque; 1870}; 1871 1872struct bge_extrx_bd { 1873 bge_hostaddr bge_addr1; 1874 bge_hostaddr bge_addr2; 1875 bge_hostaddr bge_addr3; 1876#if BYTE_ORDER == LITTLE_ENDIAN 1877 uint16_t bge_len2; 1878 uint16_t bge_len1; 1879 uint16_t bge_rsvd1; 1880 uint16_t bge_len3; 1881#else 1882 uint16_t bge_len1; 1883 uint16_t bge_len2; 1884 uint16_t bge_len3; 1885 uint16_t bge_rsvd1; 1886#endif 1887 bge_hostaddr bge_addr0; 1888#if BYTE_ORDER == LITTLE_ENDIAN 1889 uint16_t bge_len0; 1890 uint16_t bge_idx; 1891 uint16_t bge_flags; 1892 uint16_t bge_type; 1893 uint16_t bge_tcp_udp_csum; 1894 uint16_t bge_ip_csum; 1895 uint16_t bge_vlan_tag; 1896 uint16_t bge_error_flag; 1897#else 1898 uint16_t bge_idx; 1899 uint16_t bge_len0; 1900 uint16_t bge_type; 1901 uint16_t bge_flags; 1902 uint16_t bge_ip_csum; 1903 uint16_t bge_tcp_udp_csum; 1904 uint16_t bge_error_flag; 1905 uint16_t bge_vlan_tag; 1906#endif 1907 uint32_t bge_rsvd0; 1908 uint32_t bge_opaque; 1909}; 1910 1911#define BGE_RXBDFLAG_END 0x0004 1912#define BGE_RXBDFLAG_JUMBO_RING 0x0020 1913#define BGE_RXBDFLAG_VLAN_TAG 0x0040 1914#define BGE_RXBDFLAG_ERROR 0x0400 1915#define BGE_RXBDFLAG_MINI_RING 0x0800 1916#define BGE_RXBDFLAG_IP_CSUM 0x1000 1917#define BGE_RXBDFLAG_TCP_UDP_CSUM 0x2000 1918#define BGE_RXBDFLAG_TCP_UDP_IS_TCP 0x4000 1919 1920#define BGE_RXERRFLAG_BAD_CRC 0x0001 1921#define BGE_RXERRFLAG_COLL_DETECT 0x0002 1922#define BGE_RXERRFLAG_LINK_LOST 0x0004 1923#define BGE_RXERRFLAG_PHY_DECODE_ERR 0x0008 1924#define BGE_RXERRFLAG_MAC_ABORT 0x0010 1925#define BGE_RXERRFLAG_RUNT 0x0020 1926#define BGE_RXERRFLAG_TRUNC_NO_RSRCS 0x0040 1927#define BGE_RXERRFLAG_GIANT 0x0080 1928 1929struct bge_sts_idx { 1930#if BYTE_ORDER == LITTLE_ENDIAN 1931 uint16_t bge_rx_prod_idx; 1932 uint16_t bge_tx_cons_idx; 1933#else 1934 uint16_t bge_tx_cons_idx; 1935 uint16_t bge_rx_prod_idx; 1936#endif 1937}; 1938 1939struct bge_status_block { 1940 uint32_t bge_status; 1941 uint32_t bge_rsvd0; 1942#if BYTE_ORDER == LITTLE_ENDIAN 1943 uint16_t bge_rx_jumbo_cons_idx; 1944 uint16_t bge_rx_std_cons_idx; 1945 uint16_t bge_rx_mini_cons_idx; 1946 uint16_t bge_rsvd1; 1947#else 1948 uint16_t bge_rx_std_cons_idx; 1949 uint16_t bge_rx_jumbo_cons_idx; 1950 uint16_t bge_rsvd1; 1951 uint16_t bge_rx_mini_cons_idx; 1952#endif 1953 struct bge_sts_idx bge_idx[16]; 1954}; 1955 1956#define BGE_TX_CONSIDX(x, i) x->bge_idx[i].bge_tx_considx 1957#define BGE_RX_PRODIDX(x, i) x->bge_idx[i].bge_rx_prodidx 1958 1959#define BGE_STATFLAG_UPDATED 0x00000001 1960#define BGE_STATFLAG_LINKSTATE_CHANGED 0x00000002 1961#define BGE_STATFLAG_ERROR 0x00000004 1962 1963 1964/* 1965 * Broadcom Vendor ID 1966 * (Note: the BCM570x still defaults to the Alteon PCI vendor ID 1967 * even though they're now manufactured by Broadcom) 1968 / 1969#define BCOM_VENDORID 0x14E4 1970#define BCOM_DEVICEID_BCM5700 0x1644 1971#define BCOM_DEVICEID_BCM5701 0x1645 1972#define BCOM_DEVICEID_BCM5702 0x1646 1973#define BCOM_DEVICEID_BCM5702X 0x16A6 1974#define BCOM_DEVICEID_BCM5702_ALT 0x16C6 1975#define BCOM_DEVICEID_BCM5703 0x1647 1976#define BCOM_DEVICEID_BCM5703X 0x16A7 1977#define BCOM_DEVICEID_BCM5703_ALT 0x16C7 1978#define BCOM_DEVICEID_BCM5704C 0x1648 1979#define BCOM_DEVICEID_BCM5704S 0x16A8 1980#define BCOM_DEVICEID_BCM5704S_ALT 0x1649 1981#define BCOM_DEVICEID_BCM5705 0x1653 1982#define BCOM_DEVICEID_BCM5705K 0x1654 1983#define BCOM_DEVICEID_BCM5705F 0x166E 1984#define BCOM_DEVICEID_BCM5705M 0x165D 1985#define BCOM_DEVICEID_BCM5705M_ALT 0x165E 1986#define BCOM_DEVICEID_BCM5714C 0x1668 1987#define BCOM_DEVICEID_BCM5714S 0x1669 1988#define BCOM_DEVICEID_BCM5715 0x1678 1989#define BCOM_DEVICEID_BCM5715S 0x1679 1990#define BCOM_DEVICEID_BCM5720 0x1658 1991#define BCOM_DEVICEID_BCM5721 0x1659 1992#define BCOM_DEVICEID_BCM5750 0x1676 1993#define BCOM_DEVICEID_BCM5750M 0x167C 1994#define BCOM_DEVICEID_BCM5751 0x1677 1995#define BCOM_DEVICEID_BCM5751F 0x167E 1996#define BCOM_DEVICEID_BCM5751M 0x167D 1997#define BCOM_DEVICEID_BCM5752 0x1600 1998#define BCOM_DEVICEID_BCM5752M 0x1601 1999#define BCOM_DEVICEID_BCM5753 0x16F7 2000#define BCOM_DEVICEID_BCM5753F 0x16FE 2001#define BCOM_DEVICEID_BCM5753M 0x16FD 2002#define BCOM_DEVICEID_BCM5754 0x167A 2003#define BCOM_DEVICEID_BCM5754M 0x1672 2004#define BCOM_DEVICEID_BCM5755 0x167B 2005#define BCOM_DEVICEID_BCM5755M 0x1673 2006#define BCOM_DEVICEID_BCM5780 0x166A 2007#define BCOM_DEVICEID_BCM5780S 0x166B 2008#define BCOM_DEVICEID_BCM5781 0x16DD 2009#define BCOM_DEVICEID_BCM5782 0x1696 2010#define BCOM_DEVICEID_BCM5786 0x169A 2011#define BCOM_DEVICEID_BCM5787 0x169B 2012#define BCOM_DEVICEID_BCM5787M 0x1693 2013#define BCOM_DEVICEID_BCM5788 0x169C 2014#define BCOM_DEVICEID_BCM5789 0x169D 2015#define BCOM_DEVICEID_BCM5901 0x170D 2016#define BCOM_DEVICEID_BCM5901A2 0x170E 2017#define BCOM_DEVICEID_BCM5903M 0x16FF 2018* 2019/* 2020 * Alteon AceNIC PCI vendor/device ID. 2021 / 2022#define ALTEON_VENDORID 0x12AE 2023#define ALTEON_DEVICEID_ACENIC 0x0001 2024#define ALTEON_DEVICEID_ACENIC_COPPER 0x0002 2025#define ALTEON_DEVICEID_BCM5700 0x0003 2026#define ALTEON_DEVICEID_BCM5701 0x0004 2027* 2028/* 2029 * 3Com 3c996 PCI vendor/device ID. 2030 / 2031#define TC_VENDORID 0x10B7 2032#define TC_DEVICEID_3C996 0x0003 2033* 2034/* 2035 * SysKonnect PCI vendor ID 2036 / 2037#define SK_VENDORID 0x1148 2038#define SK_DEVICEID_ALTIMA 0x4400 2039#define SK_SUBSYSID_9D21 0x4421 2040#define SK_SUBSYSID_9D41 0x4441 2041* 2042/* 2043 * Altima PCI vendor/device ID. 2044 / 2045#define ALTIMA_VENDORID 0x173b 2046#define ALTIMA_DEVICE_AC1000 0x03e8 2047#define ALTIMA_DEVICE_AC1002 0x03e9 2048#define ALTIMA_DEVICE_AC9100 0x03ea 2049* 2050/* 2051 * Dell PCI vendor ID 2052 / 2053* 2054#define DELL_VENDORID 0x1028 2055 2056/* 2057 * Apple PCI vendor ID. 2058 / 2059#define APPLE_VENDORID 0x106b 2060#define APPLE_DEVICE_BCM5701 0x1645 2061* 2062/* 2063 * Offset of MAC address inside EEPROM. 2064 / 2065#define BGE_EE_MAC_OFFSET 0x7C 2066#define BGE_EE_HWCFG_OFFSET 0xC8 2067* 2068#define BGE_HWCFG_VOLTAGE 0x00000003 2069#define BGE_HWCFG_PHYLED_MODE 0x0000000C 2070#define BGE_HWCFG_MEDIA 0x00000030 2071#define BGE_HWCFG_ASF 0x00000080 2072 2073#define BGE_VOLTAGE_1POINT3 0x00000000 2074#define BGE_VOLTAGE_1POINT8 0x00000001 2075 2076#define BGE_PHYLEDMODE_UNSPEC 0x00000000 2077#define BGE_PHYLEDMODE_TRIPLELED 0x00000004 2078#define BGE_PHYLEDMODE_SINGLELED 0x00000008 2079 2080#define BGE_MEDIA_UNSPEC 0x00000000 2081#define BGE_MEDIA_COPPER 0x00000010 2082#define BGE_MEDIA_FIBER 0x00000020 2083 2084#define BGE_PCI_READ_CMD 0x06000000 2085#define BGE_PCI_WRITE_CMD 0x70000000 2086 2087#define BGE_TICKS_PER_SEC 1000000 2088 2089/* 2090 * Ring size constants. 2091 / 2092#define BGE_EVENT_RING_CNT 256 2093#define BGE_CMD_RING_CNT 64 2094#define BGE_STD_RX_RING_CNT 512 2095#define BGE_JUMBO_RX_RING_CNT 256 2096#define BGE_MINI_RX_RING_CNT 1024 2097#define BGE_RETURN_RING_CNT 1024 2098* 2099/* 5705 has smaller return ring size / 2100* 2101#define BGE_RETURN_RING_CNT_5705 512 2102 2103/* 2104 * Possible TX ring sizes. 2105 / 2106#define BGE_TX_RING_CNT_128 128 2107#define BGE_TX_RING_BASE_128 0x3800 2108* 2109#define BGE_TX_RING_CNT_256 256 2110#define BGE_TX_RING_BASE_256 0x3000 2111 2112#define BGE_TX_RING_CNT_512 512 2113#define BGE_TX_RING_BASE_512 0x2000 2114 2115#define BGE_TX_RING_CNT BGE_TX_RING_CNT_512 2116#define BGE_TX_RING_BASE BGE_TX_RING_BASE_512 2117 2118/* 2119 * Tigon III statistics counters. 2120 / 2121/ Statistics maintained MAC Receive block. / 2122struct bge_rx_mac_stats { 2123* bge_hostaddr ifHCInOctets; 2124 bge_hostaddr Reserved1; 2125 bge_hostaddr etherStatsFragments; 2126 bge_hostaddr ifHCInUcastPkts; 2127 bge_hostaddr ifHCInMulticastPkts; 2128 bge_hostaddr ifHCInBroadcastPkts; 2129 bge_hostaddr dot3StatsFCSErrors; 2130 bge_hostaddr dot3StatsAlignmentErrors; 2131 bge_hostaddr xonPauseFramesReceived; 2132 bge_hostaddr xoffPauseFramesReceived; 2133 bge_hostaddr macControlFramesReceived; 2134 bge_hostaddr xoffStateEntered; 2135 bge_hostaddr dot3StatsFramesTooLong; 2136 bge_hostaddr etherStatsJabbers; 2137 bge_hostaddr etherStatsUndersizePkts; 2138 bge_hostaddr inRangeLengthError; 2139 bge_hostaddr outRangeLengthError; 2140 bge_hostaddr etherStatsPkts64Octets; 2141 bge_hostaddr etherStatsPkts65Octetsto127Octets; 2142 bge_hostaddr etherStatsPkts128Octetsto255Octets; 2143 bge_hostaddr etherStatsPkts256Octetsto511Octets; 2144 bge_hostaddr etherStatsPkts512Octetsto1023Octets; 2145 bge_hostaddr etherStatsPkts1024Octetsto1522Octets; 2146 bge_hostaddr etherStatsPkts1523Octetsto2047Octets; 2147 bge_hostaddr etherStatsPkts2048Octetsto4095Octets; 2148 bge_hostaddr etherStatsPkts4096Octetsto8191Octets; 2149 bge_hostaddr etherStatsPkts8192Octetsto9022Octets; 2150}; 2151 2152 2153/* Statistics maintained MAC Transmit block. / 2154struct bge_tx_mac_stats { 2155* bge_hostaddr ifHCOutOctets; 2156 bge_hostaddr Reserved2; 2157 bge_hostaddr etherStatsCollisions; 2158 bge_hostaddr outXonSent; 2159 bge_hostaddr outXoffSent; 2160 bge_hostaddr flowControlDone; 2161 bge_hostaddr dot3StatsInternalMacTransmitErrors; 2162 bge_hostaddr dot3StatsSingleCollisionFrames; 2163 bge_hostaddr dot3StatsMultipleCollisionFrames; 2164 bge_hostaddr dot3StatsDeferredTransmissions; 2165 bge_hostaddr Reserved3; 2166 bge_hostaddr dot3StatsExcessiveCollisions; 2167 bge_hostaddr dot3StatsLateCollisions; 2168 bge_hostaddr dot3Collided2Times; 2169 bge_hostaddr dot3Collided3Times; 2170 bge_hostaddr dot3Collided4Times; 2171 bge_hostaddr dot3Collided5Times; 2172 bge_hostaddr dot3Collided6Times; 2173 bge_hostaddr dot3Collided7Times; 2174 bge_hostaddr dot3Collided8Times; 2175 bge_hostaddr dot3Collided9Times; 2176 bge_hostaddr dot3Collided10Times; 2177 bge_hostaddr dot3Collided11Times; 2178 bge_hostaddr dot3Collided12Times; 2179 bge_hostaddr dot3Collided13Times; 2180 bge_hostaddr dot3Collided14Times; 2181 bge_hostaddr dot3Collided15Times; 2182 bge_hostaddr ifHCOutUcastPkts; 2183 bge_hostaddr ifHCOutMulticastPkts; 2184 bge_hostaddr ifHCOutBroadcastPkts; 2185 bge_hostaddr dot3StatsCarrierSenseErrors; 2186 bge_hostaddr ifOutDiscards; 2187 bge_hostaddr ifOutErrors; 2188}; 2189 2190/* Stats counters access through registers / 2191struct bge_mac_stats_regs { 2192* uint32_t ifHCOutOctets; 2193 uint32_t Reserved0; 2194 uint32_t etherStatsCollisions; 2195 uint32_t outXonSent; 2196 uint32_t outXoffSent; 2197 uint32_t Reserved1; 2198 uint32_t dot3StatsInternalMacTransmitErrors; 2199 uint32_t dot3StatsSingleCollisionFrames; 2200 uint32_t dot3StatsMultipleCollisionFrames; 2201 uint32_t dot3StatsDeferredTransmissions; 2202 uint32_t Reserved2; 2203 uint32_t dot3StatsExcessiveCollisions; 2204 uint32_t dot3StatsLateCollisions; 2205 uint32_t Reserved3[14]; 2206 uint32_t ifHCOutUcastPkts; 2207 uint32_t ifHCOutMulticastPkts; 2208 uint32_t ifHCOutBroadcastPkts; 2209 uint32_t Reserved4[2]; 2210 uint32_t ifHCInOctets; 2211 uint32_t Reserved5; 2212 uint32_t etherStatsFragments; 2213 uint32_t ifHCInUcastPkts; 2214 uint32_t ifHCInMulticastPkts; 2215 uint32_t ifHCInBroadcastPkts; 2216 uint32_t dot3StatsFCSErrors; 2217 uint32_t dot3StatsAlignmentErrors; 2218 uint32_t xonPauseFramesReceived; 2219 uint32_t xoffPauseFramesReceived; 2220 uint32_t macControlFramesReceived; 2221 uint32_t xoffStateEntered; 2222 uint32_t dot3StatsFramesTooLong; 2223 uint32_t etherStatsJabbers; 2224 uint32_t etherStatsUndersizePkts; 2225}; 2226 2227struct bge_stats { 2228 uint8_t Reserved0[256]; 2229 2230 /* Statistics maintained by Receive MAC. / 2231* struct bge_rx_mac_stats rxstats; 2232 2233 bge_hostaddr Unused1[37]; 2234 2235 /* Statistics maintained by Transmit MAC. / 2236* struct bge_tx_mac_stats txstats; 2237 2238 bge_hostaddr Unused2[31]; 2239 2240 /* Statistics maintained by Receive List Placement. / 2241* bge_hostaddr COSIfHCInPkts[16]; 2242 bge_hostaddr COSFramesDroppedDueToFilters; 2243 bge_hostaddr nicDmaWriteQueueFull; 2244 bge_hostaddr nicDmaWriteHighPriQueueFull; 2245 bge_hostaddr nicNoMoreRxBDs; 2246 bge_hostaddr ifInDiscards; 2247 bge_hostaddr ifInErrors; 2248 bge_hostaddr nicRecvThresholdHit; 2249 2250 bge_hostaddr Unused3[9]; 2251 2252 /* Statistics maintained by Send Data Initiator. / 2253* bge_hostaddr COSIfHCOutPkts[16]; 2254 bge_hostaddr nicDmaReadQueueFull; 2255 bge_hostaddr nicDmaReadHighPriQueueFull; 2256 bge_hostaddr nicSendDataCompQueueFull; 2257 2258 /* Statistics maintained by Host Coalescing. / 2259* bge_hostaddr nicRingSetSendProdIndex; 2260 bge_hostaddr nicRingStatusUpdate; 2261 bge_hostaddr nicInterrupts; 2262 bge_hostaddr nicAvoidedInterrupts; 2263 bge_hostaddr nicSendThresholdHit; 2264 2265 uint8_t Reserved4[320]; 2266}; 2267 2268/* 2269 * Tigon general information block. This resides in host memory 2270 * and contains the status counters, ring control blocks and 2271 * producer pointers. 2272 / 2273* 2274struct bge_gib { 2275 struct bge_stats bge_stats; 2276 struct bge_rcb bge_tx_rcb[16]; 2277 struct bge_rcb bge_std_rx_rcb; 2278 struct bge_rcb bge_jumbo_rx_rcb; 2279 struct bge_rcb bge_mini_rx_rcb; 2280 struct bge_rcb bge_return_rcb; 2281}; 2282 2283#define BGE_FRAMELEN 1518 2284#define BGE_MAX_FRAMELEN 1536 2285#define BGE_JUMBO_FRAMELEN 9018 2286#define BGE_JUMBO_MTU (BGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN) 2287#define BGE_MIN_FRAMELEN 60 2288 2289/* 2290 * Other utility macros. 2291 / 2292#define BGE_INC(x, y) (x) = (x + 1) % y 2293* 2294/* 2295 * Vital product data and structures. 2296 / 2297#define BGE_VPD_FLAG 0x8000 2298* 2299/* VPD structures / 2300struct vpd_res { 2301* uint8_t vr_id; 2302 uint8_t vr_len; 2303 uint8_t vr_pad; 2304}; 2305 2306struct vpd_key { 2307 char vk_key[2]; 2308 uint8_t vk_len; 2309}; 2310 2311#define VPD_RES_ID 0x82 /* ID string / 2312#define VPD_RES_READ 0x90 / start of read only area / 2313#define VPD_RES_WRITE 0x81 / start of read/write area / 2314#define VPD_RES_END 0x78 / end tag / 2315* 2316 2317/* 2318 * Register access macros. The Tigon always uses memory mapped register 2319 * accesses and all registers must be accessed with 32 bit operations. 2320 / 2321* 2322#define CSR_WRITE_4(sc, reg, val) \ 2323 bus_space_write_4(sc->bge_btag, sc->bge_bhandle, reg, val) 2324 2325#define CSR_READ_4(sc, reg) \ 2326 bus_space_read_4(sc->bge_btag, sc->bge_bhandle, reg) 2327 2328#define BGE_SETBIT(sc, reg, x) \ 2329 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) \| (x))) 2330#define BGE_CLRBIT(sc, reg, x) \ 2331 CSR_WRITE_4(sc, reg, (CSR_READ_4(sc, reg) & ~(x))) 2332 2333#define PCI_SETBIT(dev, reg, x, s) \ 2334 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) \| (x)), s) 2335#define PCI_CLRBIT(dev, reg, x, s) \ 2336 pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s) 2337 2338/* 2339 * Memory management stuff. Note: the SSLOTS, MSLOTS and JSLOTS 2340 * values are tuneable. They control the actual amount of buffers 2341 * allocated for the standard, mini and jumbo receive rings. 2342 / 2343* 2344#define BGE_SSLOTS 256 2345#define BGE_MSLOTS 256 2346#define BGE_JSLOTS 384 2347 2348#define BGE_JRAWLEN (BGE_JUMBO_FRAMELEN + ETHER_ALIGN) 2349#define BGE_JLEN (BGE_JRAWLEN + (sizeof(uint64_t) - \ 2350 (BGE_JRAWLEN % sizeof(uint64_t)))) 2351#define BGE_JPAGESZ PAGE_SIZE 2352#define BGE_RESID (BGE_JPAGESZ - (BGE_JLEN * BGE_JSLOTS) % BGE_JPAGESZ) 2353#define BGE_JMEM ((BGE_JLEN * BGE_JSLOTS) + BGE_RESID) 2354 2355#define BGE_NSEG_JUMBO 4 2356#define BGE_NSEG_NEW 32 2357 2358/* 2359 * Ring structures. Most of these reside in host memory and we tell 2360 * the NIC where they are via the ring control blocks. The exceptions 2361 * are the tx and command rings, which live in NIC memory and which 2362 * we access via the shared memory window. 2363 / 2364* 2365struct bge_ring_data { 2366 struct bge_rx_bd bge_rx_std_ring; 2367* bus_addr_t bge_rx_std_ring_paddr; 2368 struct bge_extrx_bd bge_rx_jumbo_ring; 2369* bus_addr_t bge_rx_jumbo_ring_paddr; 2370 struct bge_rx_bd bge_rx_return_ring; 2371* bus_addr_t bge_rx_return_ring_paddr; 2372 struct bge_tx_bd bge_tx_ring; 2373* bus_addr_t bge_tx_ring_paddr; 2374 struct bge_status_block bge_status_block; 2375* bus_addr_t bge_status_block_paddr; 2376 struct bge_stats bge_stats; 2377* bus_addr_t bge_stats_paddr; 2378 struct bge_gib bge_info; 2379}; 2380 2381#define BGE_STD_RX_RING_SZ \ 2382 (sizeof(struct bge_rx_bd) * BGE_STD_RX_RING_CNT) 2383#define BGE_JUMBO_RX_RING_SZ \ 2384 (sizeof(struct bge_extrx_bd) * BGE_JUMBO_RX_RING_CNT) 2385#define BGE_TX_RING_SZ \ 2386 (sizeof(struct bge_tx_bd) * BGE_TX_RING_CNT) 2387#define BGE_RX_RTN_RING_SZ(x) \ 2388 (sizeof(struct bge_rx_bd) * x->bge_return_ring_cnt) 2389 2390#define BGE_STATUS_BLK_SZ sizeof (struct bge_status_block) 2391 2392#define BGE_STATS_SZ sizeof (struct bge_stats) 2393 2394/* 2395 * Mbuf pointers. We need these to keep track of the virtual addresses 2396 * of our mbuf chains since we can only convert from physical to virtual, 2397 * not the other way around. 2398 / 2399struct bge_chain_data { 2400* bus_dma_tag_t bge_parent_tag; 2401 bus_dma_tag_t bge_rx_std_ring_tag; 2402 bus_dma_tag_t bge_rx_jumbo_ring_tag; 2403 bus_dma_tag_t bge_rx_return_ring_tag; 2404 bus_dma_tag_t bge_tx_ring_tag; 2405 bus_dma_tag_t bge_status_tag; 2406 bus_dma_tag_t bge_stats_tag; 2407 bus_dma_tag_t bge_mtag; /* mbuf mapping tag / 2408* bus_dma_tag_t bge_mtag_jumbo; /* mbuf mapping tag / 2409* bus_dmamap_t bge_tx_dmamap[BGE_TX_RING_CNT]; 2410 bus_dmamap_t bge_rx_std_dmamap[BGE_STD_RX_RING_CNT]; 2411 bus_dmamap_t bge_rx_jumbo_dmamap[BGE_JUMBO_RX_RING_CNT]; 2412 bus_dmamap_t bge_rx_std_ring_map; 2413 bus_dmamap_t bge_rx_jumbo_ring_map; 2414 bus_dmamap_t bge_tx_ring_map; 2415 bus_dmamap_t bge_rx_return_ring_map; 2416 bus_dmamap_t bge_status_map; 2417 bus_dmamap_t bge_stats_map; 2418 struct mbuf bge_tx_chain[BGE_TX_RING_CNT]; 2419* struct mbuf bge_rx_std_chain[BGE_STD_RX_RING_CNT]; 2420* struct mbuf bge_rx_jumbo_chain[BGE_JUMBO_RX_RING_CNT]; 2421}; 2422* 2423struct bge_dmamap_arg { 2424 struct bge_softc sc; 2425* bus_addr_t bge_busaddr; 2426 uint16_t bge_flags; 2427 int bge_idx; 2428 int bge_maxsegs; 2429 struct bge_tx_bd bge_ring; 2430}; 2431* 2432#define BGE_HWREV_TIGON 0x01 2433#define BGE_HWREV_TIGON_II 0x02 2434#define BGE_TIMEOUT 100000 2435#define BGE_TXCONS_UNSET 0xFFFF /* impossible value / 2436* 2437struct bge_bcom_hack { 2438 int reg; 2439 int val; 2440}; 2441 2442#define ASF_ENABLE 1 2443#define ASF_NEW_HANDSHAKE 2 2444#define ASF_STACKUP 4 2445 2446struct bge_softc { 2447 struct ifnet bge_ifp; / interface info / 2448* device_t bge_dev; 2449 struct mtx bge_mtx; 2450 device_t bge_miibus; 2451 bus_space_handle_t bge_bhandle; 2452 bus_space_tag_t bge_btag; 2453 void bge_intrhand; 2454* struct resource bge_irq; 2455* struct resource bge_res; 2456* struct ifmedia bge_ifmedia; /* TBI media info / 2457* uint32_t bge_flags; 2458#define BGE_FLAG_EXTRAM 0x00000001 /* Has external SSRAM. / 2459#define BGE_FLAG_TBI 0x00000002 2460#define BGE_FLAG_RX_ALIGNBUG 0x00000004 2461#define BGE_FLAG_NO3LED 0x00000008 2462#define BGE_FLAG_PCIX 0x00000010 2463#define BGE_FLAG_PCIE 0x00000020 2464* uint32_t bge_chipid; 2465 uint8_t bge_asicrev; 2466 uint8_t bge_chiprev; 2467 uint8_t bge_asf_mode; 2468 uint8_t bge_asf_count; 2469 struct bge_ring_data bge_ldata; /* rings / 2470* struct bge_chain_data bge_cdata; /* mbufs / 2471* uint16_t bge_tx_saved_considx; 2472 uint16_t bge_rx_saved_considx; 2473 uint16_t bge_ev_saved_considx; 2474 uint16_t bge_return_ring_cnt; 2475 uint16_t bge_std; /* current std ring head / 2476* uint16_t bge_jumbo; /* current jumo ring head / 2477* uint32_t bge_stat_ticks; 2478 uint32_t bge_rx_coal_ticks; 2479 uint32_t bge_tx_coal_ticks; 2480 uint32_t bge_tx_prodidx; 2481 uint32_t bge_rx_max_coal_bds; 2482 uint32_t bge_tx_max_coal_bds; 2483 uint32_t bge_tx_buf_ratio; 2484 int bge_if_flags; 2485 int bge_txcnt; 2486 int bge_link; /* link state / 2487* int bge_link_evt; /* pending link event / 2488* int bge_timer; 2489 struct callout bge_stat_ch; 2490 char bge_vpd_prodname; 2491* char *bge_vpd_readonly;
2493 u_long bge_rx_discards; 2494 u_long bge_tx_discards; 2495 u_long bge_tx_collisions;	2492 uint32_t bge_rx_discards; 2493 uint32_t bge_tx_discards; 2494 uint32_t bge_tx_collisions;
2496#ifdef DEVICE_POLLING 2497 int rxcycles; 2498#endif /* DEVICE_POLLING / 2499}; 2500* 2501#define BGE_LOCK_INIT(_sc, _name) \ 2502 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2503#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2504#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2505#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2506#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)	2495#ifdef DEVICE_POLLING 2496 int rxcycles; 2497#endif /* DEVICE_POLLING / 2498}; 2499* 2500#define BGE_LOCK_INIT(_sc, _name) \ 2501 mtx_init(&(_sc)->bge_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF) 2502#define BGE_LOCK(_sc) mtx_lock(&(_sc)->bge_mtx) 2503#define BGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bge_mtx, MA_OWNED) 2504#define BGE_UNLOCK(_sc) mtx_unlock(&(_sc)->bge_mtx) 2505#define BGE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bge_mtx)