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if_bge.c (153373) if_bge.c (153437)
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 18 unchanged lines hidden (view full) ---

27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 153373 2005-12-13 06:14:14Z marcel $");
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 153437 2005-12-15 05:48:49Z yongari $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

--- 375 unchanged lines hidden (view full) ---

419 if (nseg > ctx->bge_maxsegs) {
420 ctx->bge_maxsegs = 0;
421 return;
422 }
423
424 idx = ctx->bge_idx;
425 while(1) {
426 d = &ctx->bge_ring[idx];
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

--- 375 unchanged lines hidden (view full) ---

419 if (nseg > ctx->bge_maxsegs) {
420 ctx->bge_maxsegs = 0;
421 return;
422 }
423
424 idx = ctx->bge_idx;
425 while(1) {
426 d = &ctx->bge_ring[idx];
427 d->bge_addr.bge_addr_lo =
428 htole32(BGE_ADDR_LO(segs[i].ds_addr));
429 d->bge_addr.bge_addr_hi =
430 htole32(BGE_ADDR_HI(segs[i].ds_addr));
431 d->bge_len = htole16(segs[i].ds_len);
432 d->bge_flags = htole16(ctx->bge_flags);
427 d->bge_addr.bge_addr_lo = BGE_ADDR_LO(segs[i].ds_addr);
428 d->bge_addr.bge_addr_hi = BGE_ADDR_HI(segs[i].ds_addr);
429 d->bge_len = segs[i].ds_len;
430 d->bge_flags = ctx->bge_flags;
433 i++;
434 if (i == nseg)
435 break;
436 BGE_INC(idx, BGE_TX_RING_CNT);
437 }
438
431 i++;
432 if (i == nseg)
433 break;
434 BGE_INC(idx, BGE_TX_RING_CNT);
435 }
436
439 d->bge_flags |= htole16(BGE_TXBDFLAG_END);
437 d->bge_flags |= BGE_TXBDFLAG_END;
440 ctx->bge_maxsegs = nseg;
441 ctx->bge_idx = idx;
442
443 return;
444}
445
446#ifdef notdef
447static u_int8_t

--- 335 unchanged lines hidden (view full) ---

783 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
784 if (error || ctx.bge_maxsegs == 0) {
785 if (m == NULL) {
786 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
787 m_freem(m_new);
788 }
789 return(ENOMEM);
790 }
438 ctx->bge_maxsegs = nseg;
439 ctx->bge_idx = idx;
440
441 return;
442}
443
444#ifdef notdef
445static u_int8_t

--- 335 unchanged lines hidden (view full) ---

781 m_new->m_len, bge_dma_map_addr, &ctx, BUS_DMA_NOWAIT);
782 if (error || ctx.bge_maxsegs == 0) {
783 if (m == NULL) {
784 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
785 m_freem(m_new);
786 }
787 return(ENOMEM);
788 }
791 r->bge_addr.bge_addr_lo = htole32(BGE_ADDR_LO(ctx.bge_busaddr));
792 r->bge_addr.bge_addr_hi = htole32(BGE_ADDR_HI(ctx.bge_busaddr));
793 r->bge_flags = htole16(BGE_RXBDFLAG_END);
794 r->bge_len = htole16(m_new->m_len);
795 r->bge_idx = htole16(i);
789 r->bge_addr.bge_addr_lo = BGE_ADDR_LO(ctx.bge_busaddr);
790 r->bge_addr.bge_addr_hi = BGE_ADDR_HI(ctx.bge_busaddr);
791 r->bge_flags = BGE_RXBDFLAG_END;
792 r->bge_len = m_new->m_len;
793 r->bge_idx = i;
796
797 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
798 sc->bge_cdata.bge_rx_std_dmamap[i],
799 BUS_DMASYNC_PREREAD);
800
801 return(0);
802}
803

--- 44 unchanged lines hidden (view full) ---

848 KASSERT(nsegs == BGE_NSEG_JUMBO, ("%s: %d segments", __func__, nsegs));
849
850 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
851
852 /*
853 * Fill in the extended RX buffer descriptor.
854 */
855 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
794
795 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
796 sc->bge_cdata.bge_rx_std_dmamap[i],
797 BUS_DMASYNC_PREREAD);
798
799 return(0);
800}
801

--- 44 unchanged lines hidden (view full) ---

846 KASSERT(nsegs == BGE_NSEG_JUMBO, ("%s: %d segments", __func__, nsegs));
847
848 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
849
850 /*
851 * Fill in the extended RX buffer descriptor.
852 */
853 r = &sc->bge_ldata.bge_rx_jumbo_ring[i];
856 r->bge_addr0.bge_addr_lo = htole32(BGE_ADDR_LO(segs[0].ds_addr));
857 r->bge_addr0.bge_addr_hi = htole32(BGE_ADDR_HI(segs[0].ds_addr));
858 r->bge_len0 = htole16(segs[0].ds_len);
859 r->bge_addr1.bge_addr_lo = htole32(BGE_ADDR_LO(segs[1].ds_addr));
860 r->bge_addr1.bge_addr_hi = htole32(BGE_ADDR_HI(segs[1].ds_addr));
861 r->bge_len1 = htole16(segs[1].ds_len);
862 r->bge_addr2.bge_addr_lo = htole32(BGE_ADDR_LO(segs[2].ds_addr));
863 r->bge_addr2.bge_addr_hi = htole32(BGE_ADDR_HI(segs[2].ds_addr));
864 r->bge_len2 = htole16(segs[2].ds_len);
865 r->bge_len3 = htole16(0);
866 r->bge_flags = htole16(BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END);
867 r->bge_idx = htole16(i);
854 r->bge_addr0.bge_addr_lo = BGE_ADDR_LO(segs[0].ds_addr);
855 r->bge_addr0.bge_addr_hi = BGE_ADDR_HI(segs[0].ds_addr);
856 r->bge_len0 = segs[0].ds_len;
857 r->bge_addr1.bge_addr_lo = BGE_ADDR_LO(segs[1].ds_addr);
858 r->bge_addr1.bge_addr_hi = BGE_ADDR_HI(segs[1].ds_addr);
859 r->bge_len1 = segs[1].ds_len;
860 r->bge_addr2.bge_addr_lo = BGE_ADDR_LO(segs[2].ds_addr);
861 r->bge_addr2.bge_addr_hi = BGE_ADDR_HI(segs[2].ds_addr);
862 r->bge_len2 = segs[2].ds_len;
863 r->bge_len3 = 0;
864 r->bge_flags = BGE_RXBDFLAG_JUMBO_RING|BGE_RXBDFLAG_END;
865 r->bge_idx = i;
868
869 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
870 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
871 BUS_DMASYNC_PREREAD);
872
873 return (0);
874}
875

--- 181 unchanged lines hidden (view full) ---

1057 */
1058static int
1059bge_chipinit(sc)
1060 struct bge_softc *sc;
1061{
1062 int i;
1063 u_int32_t dma_rw_ctl;
1064
866
867 bus_dmamap_sync(sc->bge_cdata.bge_mtag,
868 sc->bge_cdata.bge_rx_jumbo_dmamap[i],
869 BUS_DMASYNC_PREREAD);
870
871 return (0);
872}
873

--- 181 unchanged lines hidden (view full) ---

1055 */
1056static int
1057bge_chipinit(sc)
1058 struct bge_softc *sc;
1059{
1060 int i;
1061 u_int32_t dma_rw_ctl;
1062
1065 /* Set endianness before we access any non-PCI registers. */
1066#if BYTE_ORDER == BIG_ENDIAN
1067 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1068 BGE_BIGENDIAN_INIT, 4);
1069#else
1070 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1071 BGE_LITTLEENDIAN_INIT, 4);
1072#endif
1063 /* Set endian type before we access any non-PCI registers. */
1064 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, BGE_INIT, 4);
1073
1074 /*
1075 * Check the 'ROM failed' bit on the RX CPU to see if
1076 * self-tests passed.
1077 */
1078 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1079 printf("bge%d: RX CPU self-diagnostics failed!\n",
1080 sc->bge_unit);

--- 62 unchanged lines hidden (view full) ---

1143 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1144 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1145 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1146 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1147
1148 /*
1149 * Set up general mode register.
1150 */
1065
1066 /*
1067 * Check the 'ROM failed' bit on the RX CPU to see if
1068 * self-tests passed.
1069 */
1070 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
1071 printf("bge%d: RX CPU self-diagnostics failed!\n",
1072 sc->bge_unit);

--- 62 unchanged lines hidden (view full) ---

1135 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1136 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1137 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1138 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1139
1140 /*
1141 * Set up general mode register.
1142 */
1151 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1152 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1143 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
1153 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1154 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1155
1156 /*
1157 * Disable memory write invalidate. Apparently it is not supported
1158 * properly by these devices.
1159 */
1160 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);

--- 15 unchanged lines hidden (view full) ---

1176 return(0);
1177}
1178
1179static int
1180bge_blockinit(sc)
1181 struct bge_softc *sc;
1182{
1183 struct bge_rcb *rcb;
1144 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1145 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1146
1147 /*
1148 * Disable memory write invalidate. Apparently it is not supported
1149 * properly by these devices.
1150 */
1151 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);

--- 15 unchanged lines hidden (view full) ---

1167 return(0);
1168}
1169
1170static int
1171bge_blockinit(sc)
1172 struct bge_softc *sc;
1173{
1174 struct bge_rcb *rcb;
1184 volatile struct bge_rcb *vrcb;
1175 bus_size_t vrcb;
1176 bge_hostaddr taddr;
1185 int i;
1186
1187 /*
1188 * Initialize the memory window pointer register so that
1189 * we can access the first 32K of internal NIC RAM. This will
1190 * allow us to set up the TX send ring RCBs and the RX return
1191 * ring RCBs, plus other things which live in NIC memory.
1192 */

--- 151 unchanged lines hidden (view full) ---

1344 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1345 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1346
1347 /*
1348 * Disable all unused send rings by setting the 'ring disabled'
1349 * bit in the flags field of all the TX send ring control blocks.
1350 * These are located in NIC memory.
1351 */
1177 int i;
1178
1179 /*
1180 * Initialize the memory window pointer register so that
1181 * we can access the first 32K of internal NIC RAM. This will
1182 * allow us to set up the TX send ring RCBs and the RX return
1183 * ring RCBs, plus other things which live in NIC memory.
1184 */

--- 151 unchanged lines hidden (view full) ---

1336 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1337 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1338
1339 /*
1340 * Disable all unused send rings by setting the 'ring disabled'
1341 * bit in the flags field of all the TX send ring control blocks.
1342 * These are located in NIC memory.
1343 */
1352 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1353 BGE_SEND_RING_RCB);
1344 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1354 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1345 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1355 vrcb->bge_maxlen_flags =
1356 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1357 vrcb->bge_nicaddr = 0;
1358 vrcb++;
1346 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1347 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED));
1348 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1349 vrcb += sizeof(struct bge_rcb);
1359 }
1360
1361 /* Configure TX RCB 0 (we use only the first ring) */
1350 }
1351
1352 /* Configure TX RCB 0 (we use only the first ring) */
1362 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1363 BGE_SEND_RING_RCB);
1364 vrcb->bge_hostaddr.bge_addr_lo =
1365 htole32(BGE_ADDR_LO(sc->bge_ldata.bge_tx_ring_paddr));
1366 vrcb->bge_hostaddr.bge_addr_hi =
1367 htole32(BGE_ADDR_HI(sc->bge_ldata.bge_tx_ring_paddr));
1368 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1353 vrcb = BGE_MEMWIN_START + BGE_SEND_RING_RCB;
1354 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_tx_ring_paddr);
1355 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1356 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1357 RCB_WRITE_4(sc, vrcb, bge_nicaddr,
1358 BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT));
1369 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1370 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1359 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1360 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1371 vrcb->bge_maxlen_flags =
1372 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1361 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1362 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0));
1373
1374 /* Disable all unused RX return rings */
1363
1364 /* Disable all unused RX return rings */
1375 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1376 BGE_RX_RETURN_RING_RCB);
1365 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1377 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1366 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1378 vrcb->bge_hostaddr.bge_addr_hi = 0;
1379 vrcb->bge_hostaddr.bge_addr_lo = 0;
1380 vrcb->bge_maxlen_flags =
1367 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, 0);
1368 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, 0);
1369 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1381 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1370 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1382 BGE_RCB_FLAG_RING_DISABLED);
1383 vrcb->bge_nicaddr = 0;
1371 BGE_RCB_FLAG_RING_DISABLED));
1372 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0);
1384 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1385 (i * (sizeof(u_int64_t))), 0);
1373 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1374 (i * (sizeof(u_int64_t))), 0);
1386 vrcb++;
1375 vrcb += sizeof(struct bge_rcb);
1387 }
1388
1389 /* Initialize RX ring indexes */
1390 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1391 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1392 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1393
1394 /*
1395 * Set up RX return ring 0
1396 * Note that the NIC address for RX return rings is 0x00000000.
1397 * The return rings live entirely within the host, so the
1398 * nicaddr field in the RCB isn't used.
1399 */
1376 }
1377
1378 /* Initialize RX ring indexes */
1379 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1380 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1381 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1382
1383 /*
1384 * Set up RX return ring 0
1385 * Note that the NIC address for RX return rings is 0x00000000.
1386 * The return rings live entirely within the host, so the
1387 * nicaddr field in the RCB isn't used.
1388 */
1400 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1401 BGE_RX_RETURN_RING_RCB);
1402 vrcb->bge_hostaddr.bge_addr_lo =
1403 BGE_ADDR_LO(sc->bge_ldata.bge_rx_return_ring_paddr);
1404 vrcb->bge_hostaddr.bge_addr_hi =
1405 BGE_ADDR_HI(sc->bge_ldata.bge_rx_return_ring_paddr);
1389 vrcb = BGE_MEMWIN_START + BGE_RX_RETURN_RING_RCB;
1390 BGE_HOSTADDR(taddr, sc->bge_ldata.bge_rx_return_ring_paddr);
1391 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_hi, taddr.bge_addr_hi);
1392 RCB_WRITE_4(sc, vrcb, bge_hostaddr.bge_addr_lo, taddr.bge_addr_lo);
1406 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
1407 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
1393 bus_dmamap_sync(sc->bge_cdata.bge_rx_return_ring_tag,
1394 sc->bge_cdata.bge_rx_return_ring_map, BUS_DMASYNC_PREWRITE);
1408 vrcb->bge_nicaddr = 0x00000000;
1409 vrcb->bge_maxlen_flags =
1410 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1395 RCB_WRITE_4(sc, vrcb, bge_nicaddr, 0x00000000);
1396 RCB_WRITE_4(sc, vrcb, bge_maxlen_flags,
1397 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0));
1411
1412 /* Set random backoff seed for TX */
1413 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1414 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1415 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1416 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1417 BGE_TX_BACKOFF_SEED_MASK);
1418

--- 710 unchanged lines hidden (view full) ---

2129 if (sc->bge_res == NULL) {
2130 printf ("bge%d: couldn't map memory\n", unit);
2131 error = ENXIO;
2132 goto fail;
2133 }
2134
2135 sc->bge_btag = rman_get_bustag(sc->bge_res);
2136 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1398
1399 /* Set random backoff seed for TX */
1400 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1401 IF_LLADDR(sc->bge_ifp)[0] + IF_LLADDR(sc->bge_ifp)[1] +
1402 IF_LLADDR(sc->bge_ifp)[2] + IF_LLADDR(sc->bge_ifp)[3] +
1403 IF_LLADDR(sc->bge_ifp)[4] + IF_LLADDR(sc->bge_ifp)[5] +
1404 BGE_TX_BACKOFF_SEED_MASK);
1405

--- 710 unchanged lines hidden (view full) ---

2116 if (sc->bge_res == NULL) {
2117 printf ("bge%d: couldn't map memory\n", unit);
2118 error = ENXIO;
2119 goto fail;
2120 }
2121
2122 sc->bge_btag = rman_get_bustag(sc->bge_res);
2123 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
2137 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
2138
2139 /* Allocate interrupt */
2140 rid = 0;
2141
2142 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2143 RF_SHAREABLE | RF_ACTIVE);
2144
2145 if (sc->bge_irq == NULL) {

--- 286 unchanged lines hidden (view full) ---

2432
2433 /* Save some important PCI state. */
2434 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2435 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2436 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2437
2438 pci_write_config(dev, BGE_PCI_MISC_CTL,
2439 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2124
2125 /* Allocate interrupt */
2126 rid = 0;
2127
2128 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
2129 RF_SHAREABLE | RF_ACTIVE);
2130
2131 if (sc->bge_irq == NULL) {

--- 286 unchanged lines hidden (view full) ---

2418
2419 /* Save some important PCI state. */
2420 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
2421 command = pci_read_config(dev, BGE_PCI_CMD, 4);
2422 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
2423
2424 pci_write_config(dev, BGE_PCI_MISC_CTL,
2425 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2440 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2426 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2441
2442 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2443
2444 /* XXX: Broadcom Linux driver. */
2445 if (sc->bge_pcie) {
2446 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2447 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2448 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {

--- 19 unchanged lines hidden (view full) ---

2468 }
2469 /* Set PCIE max payload size and clear error status. */
2470 pci_write_config(dev, 0xd8, 0xf5000, 4);
2471 }
2472
2473 /* Reset some of the PCI state that got zapped by reset */
2474 pci_write_config(dev, BGE_PCI_MISC_CTL,
2475 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2427
2428 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
2429
2430 /* XXX: Broadcom Linux driver. */
2431 if (sc->bge_pcie) {
2432 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
2433 CSR_WRITE_4(sc, 0x7e2c, 0x20);
2434 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {

--- 19 unchanged lines hidden (view full) ---

2454 }
2455 /* Set PCIE max payload size and clear error status. */
2456 pci_write_config(dev, 0xd8, 0xf5000, 4);
2457 }
2458
2459 /* Reset some of the PCI state that got zapped by reset */
2460 pci_write_config(dev, BGE_PCI_MISC_CTL,
2461 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
2476 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2462 BGE_HIF_SWAP_OPTIONS|BGE_PCIMISCCTL_PCISTATE_RW, 4);
2477 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2478 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2479 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2480
2481 /* Enable memory arbiter. */
2482 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2483 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2484 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);

--- 31 unchanged lines hidden (view full) ---

2516 */
2517 for (i = 0; i < BGE_TIMEOUT; i++) {
2518 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2519 break;
2520 DELAY(10);
2521 }
2522
2523 /* Fix up byte swapping */
2463 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
2464 pci_write_config(dev, BGE_PCI_CMD, command, 4);
2465 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
2466
2467 /* Enable memory arbiter. */
2468 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2469 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2470 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);

--- 31 unchanged lines hidden (view full) ---

2502 */
2503 for (i = 0; i < BGE_TIMEOUT; i++) {
2504 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
2505 break;
2506 DELAY(10);
2507 }
2508
2509 /* Fix up byte swapping */
2524 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
2510 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_DMA_SWAP_OPTIONS|
2525 BGE_MODECTL_BYTESWAP_DATA);
2526
2527 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2528
2529 /*
2530 * The 5704 in TBI mode apparently needs some special
2531 * adjustment to insure the SERDES drive level is set
2532 * to 1.2V.

--- 423 unchanged lines hidden (view full) ---

2956 return;
2957}
2958
2959static void
2960bge_stats_update(sc)
2961 struct bge_softc *sc;
2962{
2963 struct ifnet *ifp;
2511 BGE_MODECTL_BYTESWAP_DATA);
2512
2513 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
2514
2515 /*
2516 * The 5704 in TBI mode apparently needs some special
2517 * adjustment to insure the SERDES drive level is set
2518 * to 1.2V.

--- 423 unchanged lines hidden (view full) ---

2942 return;
2943}
2944
2945static void
2946bge_stats_update(sc)
2947 struct bge_softc *sc;
2948{
2949 struct ifnet *ifp;
2964 struct bge_stats *stats;
2950 bus_size_t stats;
2965
2966 ifp = sc->bge_ifp;
2967
2951
2952 ifp = sc->bge_ifp;
2953
2968 stats = (struct bge_stats *)(sc->bge_vhandle +
2969 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2954 stats = BGE_MEMWIN_START + BGE_STATS_BLOCK;
2970
2955
2956#define READ_STAT(sc, stats, stat) \
2957 CSR_READ_4(sc, stats + offsetof(struct bge_stats, stat))
2958
2971 ifp->if_collisions +=
2959 ifp->if_collisions +=
2972 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2973 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2974 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2975 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2960 (READ_STAT(sc, stats,
2961 txstats.dot3StatsSingleCollisionFrames.bge_addr_lo) +
2962 READ_STAT(sc, stats,
2963 txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo) +
2964 READ_STAT(sc, stats,
2965 txstats.dot3StatsExcessiveCollisions.bge_addr_lo) +
2966 READ_STAT(sc, stats,
2967 txstats.dot3StatsLateCollisions.bge_addr_lo)) -
2976 ifp->if_collisions;
2977
2968 ifp->if_collisions;
2969
2970#undef READ_STAT
2971
2978#ifdef notdef
2979 ifp->if_collisions +=
2980 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2981 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2982 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2983 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2984 ifp->if_collisions;
2985#endif

--- 57 unchanged lines hidden (view full) ---

3043 */
3044 sc->bge_cdata.bge_tx_dmamap[*txidx] =
3045 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx];
3046 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map;
3047 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head;
3048 sc->bge_txcnt += ctx.bge_maxsegs;
3049 f = &sc->bge_ldata.bge_tx_ring[*txidx];
3050 if (mtag != NULL) {
2972#ifdef notdef
2973 ifp->if_collisions +=
2974 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2975 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2976 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2977 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2978 ifp->if_collisions;
2979#endif

--- 57 unchanged lines hidden (view full) ---

3037 */
3038 sc->bge_cdata.bge_tx_dmamap[*txidx] =
3039 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx];
3040 sc->bge_cdata.bge_tx_dmamap[ctx.bge_idx] = map;
3041 sc->bge_cdata.bge_tx_chain[ctx.bge_idx] = m_head;
3042 sc->bge_txcnt += ctx.bge_maxsegs;
3043 f = &sc->bge_ldata.bge_tx_ring[*txidx];
3044 if (mtag != NULL) {
3051 f->bge_flags |= htole16(BGE_TXBDFLAG_VLAN_TAG);
3052 f->bge_vlan_tag = htole16(VLAN_TAG_VALUE(mtag));
3045 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
3046 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag);
3053 } else {
3054 f->bge_vlan_tag = 0;
3055 }
3056
3057 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT);
3058 *txidx = ctx.bge_idx;
3059
3060 return(0);

--- 708 unchanged lines hidden --- 		3047 } else {
3048 f->bge_vlan_tag = 0;
3049 }
3050
3051 BGE_INC(ctx.bge_idx, BGE_TX_RING_CNT);
3052 *txidx = ctx.bge_idx;
3053
3054 return(0);

--- 708 unchanged lines hidden ---