Deleted Added
sdiff udiff text old ( 114590 ) new ( 114615 )
full compact
if_bge.c (114590) if_bge.c (114615)
1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 50 unchanged lines hidden (view full) ---

59 * Without external SSRAM, you can only have at most 4 TX rings,
60 * and the use of the mini RX ring is disabled. This seems to imply
61 * that these features are simply not available on the BCM5701. As a
62 * result, this driver does not implement any support for the mini RX
63 * ring.
64 */
65
66#include <sys/cdefs.h>
1/*
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

--- 50 unchanged lines hidden (view full) ---

59 * Without external SSRAM, you can only have at most 4 TX rings,
60 * and the use of the mini RX ring is disabled. This seems to imply
61 * that these features are simply not available on the BCM5701. As a
62 * result, this driver does not implement any support for the mini RX
63 * ring.
64 */
65
66#include <sys/cdefs.h>
67__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 114590 2003-05-03 19:06:50Z ps $");
67__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 114615 2003-05-03 22:58:45Z ps $");
68
69#include <sys/param.h>
70#include <sys/systm.h>
71#include <sys/sockio.h>
72#include <sys/mbuf.h>
73#include <sys/malloc.h>
74#include <sys/kernel.h>
75#include <sys/socket.h>

--- 922 unchanged lines hidden (view full) ---

998 * Do endian, PCI and DMA initialization. Also check the on-board ROM
999 * self-test results.
1000 */
1001static int
1002bge_chipinit(sc)
1003 struct bge_softc *sc;
1004{
1005 int i;
68
69#include <sys/param.h>
70#include <sys/systm.h>
71#include <sys/sockio.h>
72#include <sys/mbuf.h>
73#include <sys/malloc.h>
74#include <sys/kernel.h>
75#include <sys/socket.h>

--- 922 unchanged lines hidden (view full) ---

998 * Do endian, PCI and DMA initialization. Also check the on-board ROM
999 * self-test results.
1000 */
1001static int
1002bge_chipinit(sc)
1003 struct bge_softc *sc;
1004{
1005 int i;
1006 u_int32_t dma_rw_ctl;
1006
1007 /* Set endianness before we access any non-PCI registers. */
1008#if BYTE_ORDER == BIG_ENDIAN
1009 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1010 BGE_BIGENDIAN_INIT, 4);
1011#else
1012 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1013 BGE_LITTLEENDIAN_INIT, 4);

--- 23 unchanged lines hidden (view full) ---

1037 for (i = BGE_STATUS_BLOCK;
1038 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1039 BGE_MEMWIN_WRITE(sc, i, 0);
1040
1041 /* Set up the PCI DMA control register. */
1042 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1043 BGE_PCISTATE_PCI_BUSMODE) {
1044 /* Conventional PCI bus */
1007
1008 /* Set endianness before we access any non-PCI registers. */
1009#if BYTE_ORDER == BIG_ENDIAN
1010 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1011 BGE_BIGENDIAN_INIT, 4);
1012#else
1013 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
1014 BGE_LITTLEENDIAN_INIT, 4);

--- 23 unchanged lines hidden (view full) ---

1038 for (i = BGE_STATUS_BLOCK;
1039 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t))
1040 BGE_MEMWIN_WRITE(sc, i, 0);
1041
1042 /* Set up the PCI DMA control register. */
1043 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1044 BGE_PCISTATE_PCI_BUSMODE) {
1045 /* Conventional PCI bus */
1045 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1046 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4);
1046 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1047 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1048 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1049 (0x0F);
1047 } else {
1048 /* PCI-X bus */
1050 } else {
1051 /* PCI-X bus */
1049 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL,
1050 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4);
1052 /*
1053 * The 5704 uses a different encoding of read/write
1054 * watermarks.
1055 */
1056 if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704)
1057 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1058 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1059 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1060 else
1061 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1062 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1063 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1064 (0x0F);
1065
1066 /*
1067 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1068 * for hardware bugs.
1069 */
1070 if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5703 ||
1071 BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704) {
1072 u_int32_t tmp;
1073
1074 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1075 if (tmp == 0x6 || tmp == 0x7)
1076 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1077 }
1051 }
1052
1078 }
1079
1080 if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5703 ||
1081 BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5704)
1082 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1083 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1084
1053 /*
1054 * Set up general mode register.
1055 */
1056 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1057 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1058 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1059 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1060 BGE_MODECTL_RX_NO_PHDR_CSUM);

--- 349 unchanged lines hidden (view full) ---

1410 BGE_MACSTAT_CFG_CHANGED);
1411 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1412
1413 /* Enable PHY auto polling (for MII/GMII only) */
1414 if (sc->bge_tbi) {
1415 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1416 } else {
1417 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1085 /*
1086 * Set up general mode register.
1087 */
1088 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1089 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1090 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1091 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM|
1092 BGE_MODECTL_RX_NO_PHDR_CSUM);

--- 349 unchanged lines hidden (view full) ---

1442 BGE_MACSTAT_CFG_CHANGED);
1443 CSR_WRITE_4(sc, BGE_MI_STS, 0);
1444
1445 /* Enable PHY auto polling (for MII/GMII only) */
1446 if (sc->bge_tbi) {
1447 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1448 } else {
1449 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1418 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1450 if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5700)
1419 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1420 BGE_EVTENB_MI_INTERRUPT);
1421 }
1422
1423 /* Enable link state change attentions. */
1424 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1425
1426 return(0);

--- 188 unchanged lines hidden (view full) ---

1615 ifp->if_capenable = ifp->if_capabilities;
1616
1617 /* Save ASIC rev. */
1618
1619 sc->bge_asicrev =
1620 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1621 BGE_PCIMISCCTL_ASICREV;
1622
1451 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1452 BGE_EVTENB_MI_INTERRUPT);
1453 }
1454
1455 /* Enable link state change attentions. */
1456 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1457
1458 return(0);

--- 188 unchanged lines hidden (view full) ---

1647 ifp->if_capenable = ifp->if_capabilities;
1648
1649 /* Save ASIC rev. */
1650
1651 sc->bge_asicrev =
1652 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1653 BGE_PCIMISCCTL_ASICREV;
1654
1623 /* Pretend all 5700s are the same */
1624 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700)
1625 sc->bge_asicrev = BGE_ASICREV_BCM5700;
1626
1627 /*
1628 * Figure out what sort of media we have by checking the
1629 * hardware config word in the first 32k of NIC internal memory,
1630 * or fall back to examining the EEPROM if necessary.
1631 * Note: on some BCM5700 cards, this value appears to be unset.
1632 * If that's the case, we have to rely on identifying the NIC
1633 * by its PCI subsystem ID, as we do below for the SysKonnect
1634 * SK-9D41.

--- 397 unchanged lines hidden (view full) ---

2032 * according to all avaibable information. Hence, we have
2033 * to enable MII interrupts in order to properly obtain
2034 * async link changes. Unfortunately, this also means that
2035 * we have to read the MAC status register to detect link
2036 * changes, thereby adding an additional register access to
2037 * the interrupt handler.
2038 */
2039
1655 /*
1656 * Figure out what sort of media we have by checking the
1657 * hardware config word in the first 32k of NIC internal memory,
1658 * or fall back to examining the EEPROM if necessary.
1659 * Note: on some BCM5700 cards, this value appears to be unset.
1660 * If that's the case, we have to rely on identifying the NIC
1661 * by its PCI subsystem ID, as we do below for the SysKonnect
1662 * SK-9D41.

--- 397 unchanged lines hidden (view full) ---

2060 * according to all avaibable information. Hence, we have
2061 * to enable MII interrupts in order to properly obtain
2062 * async link changes. Unfortunately, this also means that
2063 * we have to read the MAC status register to detect link
2064 * changes, thereby adding an additional register access to
2065 * the interrupt handler.
2066 */
2067
2040 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2068 if (BGE_ASICREV(sc->bge_asicrev) == BGE_ASICREV_BCM5700) {
2041 u_int32_t status;
2042
2043 status = CSR_READ_4(sc, BGE_MAC_STS);
2044 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2045 sc->bge_link = 0;
2046 untimeout(bge_tick, sc, sc->bge_stat_ch);
2047 bge_tick(sc);
2048 /* Clear the interrupt */

--- 679 unchanged lines hidden --- 		2069 u_int32_t status;
2070
2071 status = CSR_READ_4(sc, BGE_MAC_STS);
2072 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2073 sc->bge_link = 0;
2074 untimeout(bge_tick, sc, sc->bge_stat_ch);
2075 bge_tick(sc);
2076 /* Clear the interrupt */

--- 679 unchanged lines hidden ---