146 { SK_VENDORID, SK_DEVICEID_ALTIMA, 147 "SysKonnect Gigabit Ethernet" }, 148 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 149 "Altima AC1000 Gigabit Ethernet" }, 150 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC9100, 151 "Altima AC9100 Gigabit Ethernet" }, 152 { 0, 0, NULL } 153}; 154 155static int bge_probe (device_t); 156static int bge_attach (device_t); 157static int bge_detach (device_t); 158static void bge_release_resources 159 (struct bge_softc *); 160static void bge_txeof (struct bge_softc *); 161static void bge_rxeof (struct bge_softc *); 162 163static void bge_tick (void *); 164static void bge_stats_update (struct bge_softc *); 165static int bge_encap (struct bge_softc *, struct mbuf *, 166 u_int32_t *); 167 168static void bge_intr (void *); 169static void bge_start (struct ifnet *); 170static int bge_ioctl (struct ifnet *, u_long, caddr_t); 171static void bge_init (void *); 172static void bge_stop (struct bge_softc *); 173static void bge_watchdog (struct ifnet *); 174static void bge_shutdown (device_t); 175static int bge_ifmedia_upd (struct ifnet *); 176static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 177 178static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 179static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 180 181static u_int32_t bge_crc (caddr_t); 182static void bge_setmulti (struct bge_softc *); 183 184static void bge_handle_events (struct bge_softc *); 185static int bge_alloc_jumbo_mem (struct bge_softc *); 186static void bge_free_jumbo_mem (struct bge_softc *); 187static void *bge_jalloc (struct bge_softc *); 188static void bge_jfree (void *, void *); 189static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 190static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 191static int bge_init_rx_ring_std (struct bge_softc *); 192static void bge_free_rx_ring_std (struct bge_softc *); 193static int bge_init_rx_ring_jumbo (struct bge_softc *); 194static void bge_free_rx_ring_jumbo (struct bge_softc *); 195static void bge_free_tx_ring (struct bge_softc *); 196static int bge_init_tx_ring (struct bge_softc *); 197 198static int bge_chipinit (struct bge_softc *); 199static int bge_blockinit (struct bge_softc *); 200 201#ifdef notdef 202static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 203static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 204static void bge_vpd_read (struct bge_softc *); 205#endif 206 207static u_int32_t bge_readmem_ind 208 (struct bge_softc *, int); 209static void bge_writemem_ind (struct bge_softc *, int, int); 210#ifdef notdef 211static u_int32_t bge_readreg_ind 212 (struct bge_softc *, int); 213#endif 214static void bge_writereg_ind (struct bge_softc *, int, int); 215 216static int bge_miibus_readreg (device_t, int, int); 217static int bge_miibus_writereg (device_t, int, int, int); 218static void bge_miibus_statchg (device_t); 219 220static void bge_reset (struct bge_softc *); 221static void bge_phy_hack (struct bge_softc *); 222 223static device_method_t bge_methods[] = { 224 /* Device interface */ 225 DEVMETHOD(device_probe, bge_probe), 226 DEVMETHOD(device_attach, bge_attach), 227 DEVMETHOD(device_detach, bge_detach), 228 DEVMETHOD(device_shutdown, bge_shutdown), 229 230 /* bus interface */ 231 DEVMETHOD(bus_print_child, bus_generic_print_child), 232 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 233 234 /* MII interface */ 235 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 236 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 237 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 238 239 { 0, 0 } 240}; 241 242static driver_t bge_driver = { 243 "bge", 244 bge_methods, 245 sizeof(struct bge_softc) 246}; 247 248static devclass_t bge_devclass; 249 250DRIVER_MODULE(bge, pci, bge_driver, bge_devclass, 0, 0); 251DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 252 253static u_int32_t 254bge_readmem_ind(sc, off) 255 struct bge_softc *sc; 256 int off; 257{ 258 device_t dev; 259 260 dev = sc->bge_dev; 261 262 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 263 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 264} 265 266static void 267bge_writemem_ind(sc, off, val) 268 struct bge_softc *sc; 269 int off, val; 270{ 271 device_t dev; 272 273 dev = sc->bge_dev; 274 275 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 276 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 277 278 return; 279} 280 281#ifdef notdef 282static u_int32_t 283bge_readreg_ind(sc, off) 284 struct bge_softc *sc; 285 int off; 286{ 287 device_t dev; 288 289 dev = sc->bge_dev; 290 291 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 292 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 293} 294#endif 295 296static void 297bge_writereg_ind(sc, off, val) 298 struct bge_softc *sc; 299 int off, val; 300{ 301 device_t dev; 302 303 dev = sc->bge_dev; 304 305 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 306 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 307 308 return; 309} 310 311#ifdef notdef 312static u_int8_t 313bge_vpd_readbyte(sc, addr) 314 struct bge_softc *sc; 315 int addr; 316{ 317 int i; 318 device_t dev; 319 u_int32_t val; 320 321 dev = sc->bge_dev; 322 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 323 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 324 DELAY(10); 325 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 326 break; 327 } 328 329 if (i == BGE_TIMEOUT) { 330 printf("bge%d: VPD read timed out\n", sc->bge_unit); 331 return(0); 332 } 333 334 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 335 336 return((val >> ((addr % 4) * 8)) & 0xFF); 337} 338 339static void 340bge_vpd_read_res(sc, res, addr) 341 struct bge_softc *sc; 342 struct vpd_res *res; 343 int addr; 344{ 345 int i; 346 u_int8_t *ptr; 347 348 ptr = (u_int8_t *)res; 349 for (i = 0; i < sizeof(struct vpd_res); i++) 350 ptr[i] = bge_vpd_readbyte(sc, i + addr); 351 352 return; 353} 354 355static void 356bge_vpd_read(sc) 357 struct bge_softc *sc; 358{ 359 int pos = 0, i; 360 struct vpd_res res; 361 362 if (sc->bge_vpd_prodname != NULL) 363 free(sc->bge_vpd_prodname, M_DEVBUF); 364 if (sc->bge_vpd_readonly != NULL) 365 free(sc->bge_vpd_readonly, M_DEVBUF); 366 sc->bge_vpd_prodname = NULL; 367 sc->bge_vpd_readonly = NULL; 368 369 bge_vpd_read_res(sc, &res, pos); 370 371 if (res.vr_id != VPD_RES_ID) { 372 printf("bge%d: bad VPD resource id: expected %x got %x\n", 373 sc->bge_unit, VPD_RES_ID, res.vr_id); 374 return; 375 } 376 377 pos += sizeof(res); 378 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 379 for (i = 0; i < res.vr_len; i++) 380 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 381 sc->bge_vpd_prodname[i] = '\0'; 382 pos += i; 383 384 bge_vpd_read_res(sc, &res, pos); 385 386 if (res.vr_id != VPD_RES_READ) { 387 printf("bge%d: bad VPD resource id: expected %x got %x\n", 388 sc->bge_unit, VPD_RES_READ, res.vr_id); 389 return; 390 } 391 392 pos += sizeof(res); 393 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 394 for (i = 0; i < res.vr_len + 1; i++) 395 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 396 397 return; 398} 399#endif 400 401/* 402 * Read a byte of data stored in the EEPROM at address 'addr.' The 403 * BCM570x supports both the traditional bitbang interface and an 404 * auto access interface for reading the EEPROM. We use the auto 405 * access method. 406 */ 407static u_int8_t 408bge_eeprom_getbyte(sc, addr, dest) 409 struct bge_softc *sc; 410 int addr; 411 u_int8_t *dest; 412{ 413 int i; 414 u_int32_t byte = 0; 415 416 /* 417 * Enable use of auto EEPROM access so we can avoid 418 * having to use the bitbang method. 419 */ 420 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 421 422 /* Reset the EEPROM, load the clock period. */ 423 CSR_WRITE_4(sc, BGE_EE_ADDR, 424 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 425 DELAY(20); 426 427 /* Issue the read EEPROM command. */ 428 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 429 430 /* Wait for completion */ 431 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 432 DELAY(10); 433 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 434 break; 435 } 436 437 if (i == BGE_TIMEOUT) { 438 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 439 return(0); 440 } 441 442 /* Get result. */ 443 byte = CSR_READ_4(sc, BGE_EE_DATA); 444 445 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 446 447 return(0); 448} 449 450/* 451 * Read a sequence of bytes from the EEPROM. 452 */ 453static int 454bge_read_eeprom(sc, dest, off, cnt) 455 struct bge_softc *sc; 456 caddr_t dest; 457 int off; 458 int cnt; 459{ 460 int err = 0, i; 461 u_int8_t byte = 0; 462 463 for (i = 0; i < cnt; i++) { 464 err = bge_eeprom_getbyte(sc, off + i, &byte); 465 if (err) 466 break; 467 *(dest + i) = byte; 468 } 469 470 return(err ? 1 : 0); 471} 472 473static int 474bge_miibus_readreg(dev, phy, reg) 475 device_t dev; 476 int phy, reg; 477{ 478 struct bge_softc *sc; 479 struct ifnet *ifp; 480 u_int32_t val; 481 int i; 482 483 sc = device_get_softc(dev); 484 ifp = &sc->arpcom.ac_if; 485 486 if (phy != 1) 487 switch(sc->bge_asicrev) { 488 case BGE_ASICREV_BCM5701_B5: 489 case BGE_ASICREV_BCM5703_A2:
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491 return(0); 492 } 493 494 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 495 BGE_MIPHY(phy)|BGE_MIREG(reg)); 496 497 for (i = 0; i < BGE_TIMEOUT; i++) { 498 val = CSR_READ_4(sc, BGE_MI_COMM); 499 if (!(val & BGE_MICOMM_BUSY)) 500 break; 501 } 502 503 if (i == BGE_TIMEOUT) { 504 printf("bge%d: PHY read timed out\n", sc->bge_unit); 505 return(0); 506 } 507 508 val = CSR_READ_4(sc, BGE_MI_COMM); 509 510 if (val & BGE_MICOMM_READFAIL) 511 return(0); 512 513 return(val & 0xFFFF); 514} 515 516static int 517bge_miibus_writereg(dev, phy, reg, val) 518 device_t dev; 519 int phy, reg, val; 520{ 521 struct bge_softc *sc; 522 int i; 523 524 sc = device_get_softc(dev); 525 526 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 527 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 528 529 for (i = 0; i < BGE_TIMEOUT; i++) { 530 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 531 break; 532 } 533 534 if (i == BGE_TIMEOUT) { 535 printf("bge%d: PHY read timed out\n", sc->bge_unit); 536 return(0); 537 } 538 539 return(0); 540} 541 542static void 543bge_miibus_statchg(dev) 544 device_t dev; 545{ 546 struct bge_softc *sc; 547 struct mii_data *mii; 548 549 sc = device_get_softc(dev); 550 mii = device_get_softc(sc->bge_miibus); 551 552 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 553 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) { 554 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 555 } else { 556 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 557 } 558 559 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 560 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 561 } else { 562 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 563 } 564 565 bge_phy_hack(sc); 566 567 return; 568} 569 570/* 571 * Handle events that have triggered interrupts. 572 */ 573static void 574bge_handle_events(sc) 575 struct bge_softc *sc; 576{ 577 578 return; 579} 580 581/* 582 * Memory management for jumbo frames. 583 */ 584 585static int 586bge_alloc_jumbo_mem(sc) 587 struct bge_softc *sc; 588{ 589 caddr_t ptr; 590 register int i; 591 struct bge_jpool_entry *entry; 592 593 /* Grab a big chunk o' storage. */ 594 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 595 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 596 597 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 598 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 599 return(ENOBUFS); 600 } 601 602 SLIST_INIT(&sc->bge_jfree_listhead); 603 SLIST_INIT(&sc->bge_jinuse_listhead); 604 605 /* 606 * Now divide it up into 9K pieces and save the addresses 607 * in an array. 608 */ 609 ptr = sc->bge_cdata.bge_jumbo_buf; 610 for (i = 0; i < BGE_JSLOTS; i++) { 611 sc->bge_cdata.bge_jslots[i] = ptr; 612 ptr += BGE_JLEN; 613 entry = malloc(sizeof(struct bge_jpool_entry), 614 M_DEVBUF, M_NOWAIT); 615 if (entry == NULL) { 616 contigfree(sc->bge_cdata.bge_jumbo_buf, 617 BGE_JMEM, M_DEVBUF); 618 sc->bge_cdata.bge_jumbo_buf = NULL; 619 printf("bge%d: no memory for jumbo " 620 "buffer queue!\n", sc->bge_unit); 621 return(ENOBUFS); 622 } 623 entry->slot = i; 624 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 625 entry, jpool_entries); 626 } 627 628 return(0); 629} 630 631static void 632bge_free_jumbo_mem(sc) 633 struct bge_softc *sc; 634{ 635 int i; 636 struct bge_jpool_entry *entry; 637 638 for (i = 0; i < BGE_JSLOTS; i++) { 639 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 640 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 641 free(entry, M_DEVBUF); 642 } 643 644 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 645 646 return; 647} 648 649/* 650 * Allocate a jumbo buffer. 651 */ 652static void * 653bge_jalloc(sc) 654 struct bge_softc *sc; 655{ 656 struct bge_jpool_entry *entry; 657 658 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 659 660 if (entry == NULL) { 661 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 662 return(NULL); 663 } 664 665 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 666 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 667 return(sc->bge_cdata.bge_jslots[entry->slot]); 668} 669 670/* 671 * Release a jumbo buffer. 672 */ 673static void 674bge_jfree(buf, args) 675 void *buf; 676 void *args; 677{ 678 struct bge_jpool_entry *entry; 679 struct bge_softc *sc; 680 int i; 681 682 /* Extract the softc struct pointer. */ 683 sc = (struct bge_softc *)args; 684 685 if (sc == NULL) 686 panic("bge_jfree: can't find softc pointer!"); 687 688 /* calculate the slot this buffer belongs to */ 689 690 i = ((vm_offset_t)buf 691 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 692 693 if ((i < 0) || (i >= BGE_JSLOTS)) 694 panic("bge_jfree: asked to free buffer that we don't manage!"); 695 696 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 697 if (entry == NULL) 698 panic("bge_jfree: buffer not in use!"); 699 entry->slot = i; 700 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 701 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 702 703 return; 704} 705 706 707/* 708 * Intialize a standard receive ring descriptor. 709 */ 710static int 711bge_newbuf_std(sc, i, m) 712 struct bge_softc *sc; 713 int i; 714 struct mbuf *m; 715{ 716 struct mbuf *m_new = NULL; 717 struct bge_rx_bd *r; 718 719 if (m == NULL) { 720 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 721 if (m_new == NULL) { 722 return(ENOBUFS); 723 } 724 725 MCLGET(m_new, M_DONTWAIT); 726 if (!(m_new->m_flags & M_EXT)) { 727 m_freem(m_new); 728 return(ENOBUFS); 729 } 730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 731 } else { 732 m_new = m; 733 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 734 m_new->m_data = m_new->m_ext.ext_buf; 735 } 736 737 if (!sc->bge_rx_alignment_bug) 738 m_adj(m_new, ETHER_ALIGN); 739 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 740 r = &sc->bge_rdata->bge_rx_std_ring[i]; 741 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 742 r->bge_flags = BGE_RXBDFLAG_END; 743 r->bge_len = m_new->m_len; 744 r->bge_idx = i; 745 746 return(0); 747} 748 749/* 750 * Initialize a jumbo receive ring descriptor. This allocates 751 * a jumbo buffer from the pool managed internally by the driver. 752 */ 753static int 754bge_newbuf_jumbo(sc, i, m) 755 struct bge_softc *sc; 756 int i; 757 struct mbuf *m; 758{ 759 struct mbuf *m_new = NULL; 760 struct bge_rx_bd *r; 761 762 if (m == NULL) { 763 caddr_t *buf = NULL; 764 765 /* Allocate the mbuf. */ 766 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 767 if (m_new == NULL) { 768 return(ENOBUFS); 769 } 770 771 /* Allocate the jumbo buffer */ 772 buf = bge_jalloc(sc); 773 if (buf == NULL) { 774 m_freem(m_new); 775 printf("bge%d: jumbo allocation failed " 776 "-- packet dropped!\n", sc->bge_unit); 777 return(ENOBUFS); 778 } 779 780 /* Attach the buffer to the mbuf. */ 781 m_new->m_data = (void *) buf; 782 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 783 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 784 (struct bge_softc *)sc, 0, EXT_NET_DRV); 785 } else { 786 m_new = m; 787 m_new->m_data = m_new->m_ext.ext_buf; 788 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 789 } 790 791 if (!sc->bge_rx_alignment_bug) 792 m_adj(m_new, ETHER_ALIGN); 793 /* Set up the descriptor. */ 794 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 795 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 796 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 797 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 798 r->bge_len = m_new->m_len; 799 r->bge_idx = i; 800 801 return(0); 802} 803 804/* 805 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 806 * that's 1MB or memory, which is a lot. For now, we fill only the first 807 * 256 ring entries and hope that our CPU is fast enough to keep up with 808 * the NIC. 809 */ 810static int 811bge_init_rx_ring_std(sc) 812 struct bge_softc *sc; 813{ 814 int i; 815 816 for (i = 0; i < BGE_SSLOTS; i++) { 817 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 818 return(ENOBUFS); 819 }; 820 821 sc->bge_std = i - 1; 822 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 823 824 return(0); 825} 826 827static void 828bge_free_rx_ring_std(sc) 829 struct bge_softc *sc; 830{ 831 int i; 832 833 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 834 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 835 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 836 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 837 } 838 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 839 sizeof(struct bge_rx_bd)); 840 } 841 842 return; 843} 844 845static int 846bge_init_rx_ring_jumbo(sc) 847 struct bge_softc *sc; 848{ 849 int i; 850 struct bge_rcb *rcb; 851 852 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 853 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 854 return(ENOBUFS); 855 }; 856 857 sc->bge_jumbo = i - 1; 858 859 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 860 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0); 861 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 862 863 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 864 865 return(0); 866} 867 868static void 869bge_free_rx_ring_jumbo(sc) 870 struct bge_softc *sc; 871{ 872 int i; 873 874 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 875 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 876 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 877 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 878 } 879 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 880 sizeof(struct bge_rx_bd)); 881 } 882 883 return; 884} 885 886static void 887bge_free_tx_ring(sc) 888 struct bge_softc *sc; 889{ 890 int i; 891 892 if (sc->bge_rdata->bge_tx_ring == NULL) 893 return; 894 895 for (i = 0; i < BGE_TX_RING_CNT; i++) { 896 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 897 m_freem(sc->bge_cdata.bge_tx_chain[i]); 898 sc->bge_cdata.bge_tx_chain[i] = NULL; 899 } 900 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 901 sizeof(struct bge_tx_bd)); 902 } 903 904 return; 905} 906 907static int 908bge_init_tx_ring(sc) 909 struct bge_softc *sc; 910{ 911 sc->bge_txcnt = 0; 912 sc->bge_tx_saved_considx = 0; 913 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 914 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 915 916 return(0); 917} 918 919#define BGE_POLY 0xEDB88320 920 921static u_int32_t 922bge_crc(addr) 923 caddr_t addr; 924{ 925 u_int32_t idx, bit, data, crc; 926 927 /* Compute CRC for the address value. */ 928 crc = 0xFFFFFFFF; /* initial value */ 929 930 for (idx = 0; idx < 6; idx++) { 931 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 932 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 933 } 934 935 return(crc & 0x7F); 936} 937 938static void 939bge_setmulti(sc) 940 struct bge_softc *sc; 941{ 942 struct ifnet *ifp; 943 struct ifmultiaddr *ifma; 944 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 945 int h, i; 946 947 ifp = &sc->arpcom.ac_if; 948 949 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 950 for (i = 0; i < 4; i++) 951 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 952 return; 953 } 954 955 /* First, zot all the existing filters. */ 956 for (i = 0; i < 4; i++) 957 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 958 959 /* Now program new ones. */ 960 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 961 if (ifma->ifma_addr->sa_family != AF_LINK) 962 continue; 963 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 964 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 965 } 966 967 for (i = 0; i < 4; i++) 968 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 969 970 return; 971} 972 973/* 974 * Do endian, PCI and DMA initialization. Also check the on-board ROM 975 * self-test results. 976 */ 977static int 978bge_chipinit(sc) 979 struct bge_softc *sc; 980{ 981 int i; 982 983 /* Set endianness before we access any non-PCI registers. */ 984#if BYTE_ORDER == BIG_ENDIAN 985 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 986 BGE_BIGENDIAN_INIT, 4); 987#else 988 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 989 BGE_LITTLEENDIAN_INIT, 4); 990#endif 991 992 /* 993 * Check the 'ROM failed' bit on the RX CPU to see if 994 * self-tests passed. 995 */ 996 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 997 printf("bge%d: RX CPU self-diagnostics failed!\n", 998 sc->bge_unit); 999 return(ENODEV); 1000 } 1001 1002 /* Clear the MAC control register */ 1003 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1004 1005 /* 1006 * Clear the MAC statistics block in the NIC's 1007 * internal memory. 1008 */ 1009 for (i = BGE_STATS_BLOCK; 1010 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1011 BGE_MEMWIN_WRITE(sc, i, 0); 1012 1013 for (i = BGE_STATUS_BLOCK; 1014 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1015 BGE_MEMWIN_WRITE(sc, i, 0); 1016 1017 /* Set up the PCI DMA control register. */ 1018 if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) & 1019 BGE_PCISTATE_PCI_BUSMODE) { 1020 /* Conventional PCI bus */ 1021 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1022 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x3F000F, 4); 1023 } else { 1024 /* PCI-X bus */ 1025 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1026 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x1B000F, 4); 1027 } 1028 1029 /* 1030 * Set up general mode register. 1031 */ 1032 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1033 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1034 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1035 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1036 BGE_MODECTL_RX_NO_PHDR_CSUM); 1037 1038 /* 1039 * Disable memory write invalidate. Apparently it is not supported 1040 * properly by these devices. 1041 */ 1042 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4); 1043 1044#ifdef __brokenalpha__ 1045 /* 1046 * Must insure that we do not cross an 8K (bytes) boundary 1047 * for DMA reads. Our highest limit is 1K bytes. This is a 1048 * restriction on some ALPHA platforms with early revision 1049 * 21174 PCI chipsets, such as the AlphaPC 164lx 1050 */ 1051 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1052 BGE_PCI_READ_BNDRY_1024BYTES, 4); 1053#endif 1054 1055 /* Set the timer prescaler (always 66Mhz) */ 1056 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1057 1058 return(0); 1059} 1060 1061static int 1062bge_blockinit(sc) 1063 struct bge_softc *sc; 1064{ 1065 struct bge_rcb *rcb; 1066 volatile struct bge_rcb *vrcb; 1067 int i; 1068 1069 /* 1070 * Initialize the memory window pointer register so that 1071 * we can access the first 32K of internal NIC RAM. This will 1072 * allow us to set up the TX send ring RCBs and the RX return 1073 * ring RCBs, plus other things which live in NIC memory. 1074 */ 1075 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1076 1077 /* Configure mbuf memory pool */ 1078 if (sc->bge_extram) { 1079 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1080 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1081 } else { 1082 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1083 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1084 } 1085 1086 /* Configure DMA resource pool */ 1087 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1088 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1089 1090 /* Configure mbuf pool watermarks */ 1091 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50); 1092 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20); 1093 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60); 1094 1095 /* Configure DMA resource watermarks */ 1096 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1097 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1098 1099 /* Enable buffer manager */ 1100 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1101 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1102 1103 /* Poll for buffer manager start indication */ 1104 for (i = 0; i < BGE_TIMEOUT; i++) { 1105 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1106 break; 1107 DELAY(10); 1108 } 1109 1110 if (i == BGE_TIMEOUT) { 1111 printf("bge%d: buffer manager failed to start\n", 1112 sc->bge_unit); 1113 return(ENXIO); 1114 } 1115 1116 /* Enable flow-through queues */ 1117 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1118 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1119 1120 /* Wait until queue initialization is complete */ 1121 for (i = 0; i < BGE_TIMEOUT; i++) { 1122 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1123 break; 1124 DELAY(10); 1125 } 1126 1127 if (i == BGE_TIMEOUT) { 1128 printf("bge%d: flow-through queue init failed\n", 1129 sc->bge_unit); 1130 return(ENXIO); 1131 } 1132 1133 /* Initialize the standard RX ring control block */ 1134 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1135 BGE_HOSTADDR(rcb->bge_hostaddr) = 1136 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1137 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0); 1138 if (sc->bge_extram) 1139 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1140 else 1141 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1142 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi); 1143 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo); 1144 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1145 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr); 1146 1147 /* 1148 * Initialize the jumbo RX ring control block 1149 * We set the 'ring disabled' bit in the flags 1150 * field until we're actually ready to start 1151 * using this ring (i.e. once we set the MTU 1152 * high enough to require it). 1153 */ 1154 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1155 BGE_HOSTADDR(rcb->bge_hostaddr) = 1156 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1157 rcb->bge_maxlen_flags = 1158 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, BGE_RCB_FLAG_RING_DISABLED); 1159 if (sc->bge_extram) 1160 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1161 else 1162 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1163 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, 1164 rcb->bge_hostaddr.bge_addr_hi); 1165 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, 1166 rcb->bge_hostaddr.bge_addr_lo); 1167 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1168 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr); 1169 1170 /* Set up dummy disabled mini ring RCB */ 1171 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1172 rcb->bge_maxlen_flags = 1173 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1174 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags); 1175 1176 /* 1177 * Set the BD ring replentish thresholds. The recommended 1178 * values are 1/8th the number of descriptors allocated to 1179 * each ring. 1180 */ 1181 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1182 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1183 1184 /* 1185 * Disable all unused send rings by setting the 'ring disabled' 1186 * bit in the flags field of all the TX send ring control blocks. 1187 * These are located in NIC memory. 1188 */ 1189 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1190 BGE_SEND_RING_RCB); 1191 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1192 vrcb->bge_maxlen_flags = 1193 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED); 1194 vrcb->bge_nicaddr = 0; 1195 vrcb++; 1196 } 1197 1198 /* Configure TX RCB 0 (we use only the first ring) */ 1199 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1200 BGE_SEND_RING_RCB); 1201 vrcb->bge_hostaddr.bge_addr_hi = 0; 1202 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1203 vtophys(&sc->bge_rdata->bge_tx_ring); 1204 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1205 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0); 1206 1207 /* Disable all unused RX return rings */ 1208 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1209 BGE_RX_RETURN_RING_RCB); 1210 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1211 vrcb->bge_hostaddr.bge_addr_hi = 0; 1212 vrcb->bge_hostaddr.bge_addr_lo = 0; 1213 vrcb->bge_maxlen_flags = 1214 BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 1215 BGE_RCB_FLAG_RING_DISABLED); 1216 vrcb->bge_nicaddr = 0; 1217 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1218 (i * (sizeof(u_int64_t))), 0); 1219 vrcb++; 1220 } 1221 1222 /* Initialize RX ring indexes */ 1223 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1224 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1225 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1226 1227 /* 1228 * Set up RX return ring 0 1229 * Note that the NIC address for RX return rings is 0x00000000. 1230 * The return rings live entirely within the host, so the 1231 * nicaddr field in the RCB isn't used. 1232 */ 1233 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1234 BGE_RX_RETURN_RING_RCB); 1235 vrcb->bge_hostaddr.bge_addr_hi = 0; 1236 BGE_HOSTADDR(vrcb->bge_hostaddr) = 1237 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1238 vrcb->bge_nicaddr = 0x00000000; 1239 vrcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(BGE_RETURN_RING_CNT, 0); 1240 1241 /* Set random backoff seed for TX */ 1242 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1243 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1244 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1245 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1246 BGE_TX_BACKOFF_SEED_MASK); 1247 1248 /* Set inter-packet gap */ 1249 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1250 1251 /* 1252 * Specify which ring to use for packets that don't match 1253 * any RX rules. 1254 */ 1255 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1256 1257 /* 1258 * Configure number of RX lists. One interrupt distribution 1259 * list, sixteen active lists, one bad frames class. 1260 */ 1261 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1262 1263 /* Inialize RX list placement stats mask. */ 1264 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1265 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1266 1267 /* Disable host coalescing until we get it set up */ 1268 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1269 1270 /* Poll to make sure it's shut down. */ 1271 for (i = 0; i < BGE_TIMEOUT; i++) { 1272 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1273 break; 1274 DELAY(10); 1275 } 1276 1277 if (i == BGE_TIMEOUT) { 1278 printf("bge%d: host coalescing engine failed to idle\n", 1279 sc->bge_unit); 1280 return(ENXIO); 1281 } 1282 1283 /* Set up host coalescing defaults */ 1284 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1285 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1286 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1287 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1288 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1289 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1290 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1291 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1292 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1293 1294 /* Set up address of statistics block */ 1295 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1296 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1297 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1298 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1299 1300 /* Set up address of status block */ 1301 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1302 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1303 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1304 vtophys(&sc->bge_rdata->bge_status_block)); 1305 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1306 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1307 1308 /* Turn on host coalescing state machine */ 1309 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1310 1311 /* Turn on RX BD completion state machine and enable attentions */ 1312 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1313 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1314 1315 /* Turn on RX list placement state machine */ 1316 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1317 1318 /* Turn on RX list selector state machine. */ 1319 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1320 1321 /* Turn on DMA, clear stats */ 1322 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1323 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1324 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1325 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1326 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1327 1328 /* Set misc. local control, enable interrupts on attentions */ 1329 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1330 1331#ifdef notdef 1332 /* Assert GPIO pins for PHY reset */ 1333 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1334 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1335 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1336 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1337#endif 1338 1339 /* Turn on DMA completion state machine */ 1340 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1341 1342 /* Turn on write DMA state machine */ 1343 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1344 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1345 1346 /* Turn on read DMA state machine */ 1347 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1348 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1349 1350 /* Turn on RX data completion state machine */ 1351 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1352 1353 /* Turn on RX BD initiator state machine */ 1354 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1355 1356 /* Turn on RX data and RX BD initiator state machine */ 1357 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1358 1359 /* Turn on Mbuf cluster free state machine */ 1360 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1361 1362 /* Turn on send BD completion state machine */ 1363 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1364 1365 /* Turn on send data completion state machine */ 1366 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1367 1368 /* Turn on send data initiator state machine */ 1369 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1370 1371 /* Turn on send BD initiator state machine */ 1372 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1373 1374 /* Turn on send BD selector state machine */ 1375 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1376 1377 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1378 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1379 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1380 1381 /* init LED register */ 1382 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1383 1384 /* ack/clear link change events */ 1385 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1386 BGE_MACSTAT_CFG_CHANGED); 1387 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1388 1389 /* Enable PHY auto polling (for MII/GMII only) */ 1390 if (sc->bge_tbi) { 1391 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK); 1392 } else { 1393 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16); 1394 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1395 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1396 BGE_EVTENB_MI_INTERRUPT); 1397 } 1398 1399 /* Enable link state change attentions. */ 1400 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1401 1402 return(0); 1403} 1404 1405/* 1406 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1407 * against our list and return its name if we find a match. Note 1408 * that since the Broadcom controller contains VPD support, we 1409 * can get the device name string from the controller itself instead 1410 * of the compiled-in string. This is a little slow, but it guarantees 1411 * we'll always announce the right product name. 1412 */ 1413static int 1414bge_probe(dev) 1415 device_t dev; 1416{ 1417 struct bge_type *t; 1418 struct bge_softc *sc; 1419 char *descbuf; 1420 1421 t = bge_devs; 1422 1423 sc = device_get_softc(dev); 1424 bzero(sc, sizeof(struct bge_softc)); 1425 sc->bge_unit = device_get_unit(dev); 1426 sc->bge_dev = dev; 1427 1428 while(t->bge_name != NULL) { 1429 if ((pci_get_vendor(dev) == t->bge_vid) && 1430 (pci_get_device(dev) == t->bge_did)) { 1431#ifdef notdef 1432 bge_vpd_read(sc); 1433 device_set_desc(dev, sc->bge_vpd_prodname); 1434#endif 1435 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 1436 if (descbuf == NULL) 1437 return(ENOMEM); 1438 snprintf(descbuf, BGE_DEVDESC_MAX, 1439 "%s, ASIC rev. %#04x", t->bge_name, 1440 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16); 1441 device_set_desc_copy(dev, descbuf); 1442 free(descbuf, M_TEMP); 1443 return(0); 1444 } 1445 t++; 1446 } 1447 1448 return(ENXIO); 1449} 1450 1451static int 1452bge_attach(dev) 1453 device_t dev; 1454{ 1455 int s; 1456 struct ifnet *ifp; 1457 struct bge_softc *sc; 1458 u_int32_t hwcfg = 0; 1459 u_int32_t mac_addr = 0; 1460 int unit, error = 0, rid; 1461 1462 s = splimp(); 1463 1464 sc = device_get_softc(dev); 1465 unit = device_get_unit(dev); 1466 sc->bge_dev = dev; 1467 sc->bge_unit = unit; 1468 1469 /* 1470 * Map control/status registers. 1471 */ 1472 pci_enable_busmaster(dev); 1473 1474 rid = BGE_PCI_BAR0; 1475 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1476 0, ~0, 1, RF_ACTIVE|PCI_RF_DENSE); 1477 1478 if (sc->bge_res == NULL) { 1479 printf ("bge%d: couldn't map memory\n", unit); 1480 error = ENXIO; 1481 goto fail; 1482 } 1483 1484 sc->bge_btag = rman_get_bustag(sc->bge_res); 1485 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1486 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1487 1488 /* Allocate interrupt */ 1489 rid = 0; 1490 1491 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1492 RF_SHAREABLE | RF_ACTIVE); 1493 1494 if (sc->bge_irq == NULL) { 1495 printf("bge%d: couldn't map interrupt\n", unit); 1496 error = ENXIO; 1497 goto fail; 1498 } 1499 1500 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1501 bge_intr, sc, &sc->bge_intrhand); 1502 1503 if (error) { 1504 bge_release_resources(sc); 1505 printf("bge%d: couldn't set up irq\n", unit); 1506 goto fail; 1507 } 1508 1509 sc->bge_unit = unit; 1510 1511 /* Try to reset the chip. */ 1512 bge_reset(sc); 1513 1514 if (bge_chipinit(sc)) { 1515 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1516 bge_release_resources(sc); 1517 error = ENXIO; 1518 goto fail; 1519 } 1520 1521 /* 1522 * Get station address from the EEPROM. 1523 */ 1524 mac_addr = bge_readmem_ind(sc, 0x0c14); 1525 if ((mac_addr >> 16) == 0x484b) { 1526 sc->arpcom.ac_enaddr[0] = (u_char)(mac_addr >> 8); 1527 sc->arpcom.ac_enaddr[1] = (u_char)mac_addr; 1528 mac_addr = bge_readmem_ind(sc, 0x0c18); 1529 sc->arpcom.ac_enaddr[2] = (u_char)(mac_addr >> 24); 1530 sc->arpcom.ac_enaddr[3] = (u_char)(mac_addr >> 16); 1531 sc->arpcom.ac_enaddr[4] = (u_char)(mac_addr >> 8); 1532 sc->arpcom.ac_enaddr[5] = (u_char)mac_addr; 1533 } else if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1534 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1535 printf("bge%d: failed to read station address\n", unit); 1536 bge_release_resources(sc); 1537 error = ENXIO; 1538 goto fail; 1539 } 1540 1541 /* 1542 * A Broadcom chip was detected. Inform the world. 1543 */ 1544 printf("bge%d: Ethernet address: %6D\n", unit, 1545 sc->arpcom.ac_enaddr, ":"); 1546 1547 /* Allocate the general information block and ring buffers. */ 1548 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1549 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1550 1551 if (sc->bge_rdata == NULL) { 1552 bge_release_resources(sc); 1553 error = ENXIO; 1554 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1555 goto fail; 1556 } 1557 1558 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1559 1560 /* Try to allocate memory for jumbo buffers. */ 1561 if (bge_alloc_jumbo_mem(sc)) { 1562 printf("bge%d: jumbo buffer allocation " 1563 "failed\n", sc->bge_unit); 1564 bge_release_resources(sc); 1565 error = ENXIO; 1566 goto fail; 1567 } 1568 1569 /* Set default tuneable values. */ 1570 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1571 sc->bge_rx_coal_ticks = 150; 1572 sc->bge_tx_coal_ticks = 150; 1573 sc->bge_rx_max_coal_bds = 64; 1574 sc->bge_tx_max_coal_bds = 128; 1575 1576 /* Set up ifnet structure */ 1577 ifp = &sc->arpcom.ac_if; 1578 ifp->if_softc = sc; 1579 ifp->if_unit = sc->bge_unit; 1580 ifp->if_name = "bge"; 1581 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1582 ifp->if_ioctl = bge_ioctl; 1583 ifp->if_output = ether_output; 1584 ifp->if_start = bge_start; 1585 ifp->if_watchdog = bge_watchdog; 1586 ifp->if_init = bge_init; 1587 ifp->if_mtu = ETHERMTU; 1588 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1589 ifp->if_hwassist = BGE_CSUM_FEATURES; 1590 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU; 1591 ifp->if_capenable = ifp->if_capabilities; 1592 1593 /* Save ASIC rev. */ 1594 1595 sc->bge_asicrev = 1596 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1597 BGE_PCIMISCCTL_ASICREV; 1598 1599 /* Pretend all 5700s are the same */ 1600 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1601 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1602 1603 /* 1604 * Figure out what sort of media we have by checking the 1605 * hardware config word in the first 32k of NIC internal memory, 1606 * or fall back to examining the EEPROM if necessary. 1607 * Note: on some BCM5700 cards, this value appears to be unset. 1608 * If that's the case, we have to rely on identifying the NIC 1609 * by its PCI subsystem ID, as we do below for the SysKonnect 1610 * SK-9D41. 1611 */ 1612 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER) 1613 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG); 1614 else { 1615 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1616 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1617 hwcfg = ntohl(hwcfg); 1618 } 1619 1620 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1621 sc->bge_tbi = 1; 1622 1623 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1624 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1625 sc->bge_tbi = 1; 1626 1627 if (sc->bge_tbi) { 1628 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1629 bge_ifmedia_upd, bge_ifmedia_sts); 1630 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1631 ifmedia_add(&sc->bge_ifmedia, 1632 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1633 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1634 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1635 } else { 1636 /* 1637 * Do transceiver setup. 1638 */ 1639 if (mii_phy_probe(dev, &sc->bge_miibus, 1640 bge_ifmedia_upd, bge_ifmedia_sts)) { 1641 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1642 bge_release_resources(sc); 1643 bge_free_jumbo_mem(sc); 1644 error = ENXIO; 1645 goto fail; 1646 } 1647 } 1648 1649 /* 1650 * When using the BCM5701 in PCI-X mode, data corruption has 1651 * been observed in the first few bytes of some received packets. 1652 * Aligning the packet buffer in memory eliminates the corruption. 1653 * Unfortunately, this misaligns the packet payloads. On platforms 1654 * which do not support unaligned accesses, we will realign the 1655 * payloads by copying the received packets. 1656 */ 1657 switch (sc->bge_asicrev) { 1658 case BGE_ASICREV_BCM5701_A0: 1659 case BGE_ASICREV_BCM5701_B0: 1660 case BGE_ASICREV_BCM5701_B2: 1661 case BGE_ASICREV_BCM5701_B5: 1662 /* If in PCI-X mode, work around the alignment bug. */ 1663 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) & 1664 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) == 1665 BGE_PCISTATE_PCI_BUSSPEED) 1666 sc->bge_rx_alignment_bug = 1; 1667 break; 1668 } 1669 1670 /* 1671 * Call MI attach routine. 1672 */ 1673 ether_ifattach(ifp, sc->arpcom.ac_enaddr); 1674 callout_handle_init(&sc->bge_stat_ch); 1675 1676fail: 1677 splx(s); 1678 1679 return(error); 1680} 1681 1682static int 1683bge_detach(dev) 1684 device_t dev; 1685{ 1686 struct bge_softc *sc; 1687 struct ifnet *ifp; 1688 int s; 1689 1690 s = splimp(); 1691 1692 sc = device_get_softc(dev); 1693 ifp = &sc->arpcom.ac_if; 1694 1695 ether_ifdetach(ifp); 1696 bge_stop(sc); 1697 bge_reset(sc); 1698 1699 if (sc->bge_tbi) { 1700 ifmedia_removeall(&sc->bge_ifmedia); 1701 } else { 1702 bus_generic_detach(dev); 1703 device_delete_child(dev, sc->bge_miibus); 1704 } 1705 1706 bge_release_resources(sc); 1707 bge_free_jumbo_mem(sc); 1708 1709 splx(s); 1710 1711 return(0); 1712} 1713 1714static void 1715bge_release_resources(sc) 1716 struct bge_softc *sc; 1717{ 1718 device_t dev; 1719 1720 dev = sc->bge_dev; 1721 1722 if (sc->bge_vpd_prodname != NULL) 1723 free(sc->bge_vpd_prodname, M_DEVBUF); 1724 1725 if (sc->bge_vpd_readonly != NULL) 1726 free(sc->bge_vpd_readonly, M_DEVBUF); 1727 1728 if (sc->bge_intrhand != NULL) 1729 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1730 1731 if (sc->bge_irq != NULL) 1732 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1733 1734 if (sc->bge_res != NULL) 1735 bus_release_resource(dev, SYS_RES_MEMORY, 1736 BGE_PCI_BAR0, sc->bge_res); 1737 1738 if (sc->bge_rdata != NULL) 1739 contigfree(sc->bge_rdata, 1740 sizeof(struct bge_ring_data), M_DEVBUF); 1741 1742 return; 1743} 1744 1745static void 1746bge_reset(sc) 1747 struct bge_softc *sc; 1748{ 1749 device_t dev; 1750 u_int32_t cachesize, command, pcistate; 1751 int i, val = 0; 1752 1753 dev = sc->bge_dev; 1754 1755 /* Save some important PCI state. */ 1756 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1757 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1758 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1759 1760 pci_write_config(dev, BGE_PCI_MISC_CTL, 1761 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1762 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1763 1764 /* Issue global reset */ 1765 bge_writereg_ind(sc, BGE_MISC_CFG, 1766 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1767 1768 DELAY(1000); 1769 1770 /* Reset some of the PCI state that got zapped by reset */ 1771 pci_write_config(dev, BGE_PCI_MISC_CTL, 1772 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1773 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1774 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1775 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1776 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1777 1778 /* 1779 * Prevent PXE restart: write a magic number to the 1780 * general communications memory at 0xB50. 1781 */ 1782 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1783 /* 1784 * Poll the value location we just wrote until 1785 * we see the 1's complement of the magic number. 1786 * This indicates that the firmware initialization 1787 * is complete. 1788 */ 1789 for (i = 0; i < BGE_TIMEOUT; i++) { 1790 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1791 if (val == ~BGE_MAGIC_NUMBER) 1792 break; 1793 DELAY(10); 1794 } 1795 1796 if (i == BGE_TIMEOUT) { 1797 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1798 return; 1799 } 1800 1801 /* 1802 * XXX Wait for the value of the PCISTATE register to 1803 * return to its original pre-reset state. This is a 1804 * fairly good indicator of reset completion. If we don't 1805 * wait for the reset to fully complete, trying to read 1806 * from the device's non-PCI registers may yield garbage 1807 * results. 1808 */ 1809 for (i = 0; i < BGE_TIMEOUT; i++) { 1810 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1811 break; 1812 DELAY(10); 1813 } 1814 1815 /* Enable memory arbiter. */ 1816 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1817 1818 /* Fix up byte swapping */ 1819 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1820 BGE_MODECTL_BYTESWAP_DATA); 1821 1822 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1823 1824 DELAY(10000); 1825 1826 return; 1827} 1828 1829/* 1830 * Frame reception handling. This is called if there's a frame 1831 * on the receive return list. 1832 * 1833 * Note: we have to be able to handle two possibilities here: 1834 * 1) the frame is from the jumbo recieve ring 1835 * 2) the frame is from the standard receive ring 1836 */ 1837 1838static void 1839bge_rxeof(sc) 1840 struct bge_softc *sc; 1841{ 1842 struct ifnet *ifp; 1843 int stdcnt = 0, jumbocnt = 0; 1844 1845 ifp = &sc->arpcom.ac_if; 1846 1847 while(sc->bge_rx_saved_considx != 1848 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1849 struct bge_rx_bd *cur_rx; 1850 u_int32_t rxidx; 1851 struct ether_header *eh; 1852 struct mbuf *m = NULL; 1853 u_int16_t vlan_tag = 0; 1854 int have_tag = 0; 1855 1856 cur_rx = 1857 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1858 1859 rxidx = cur_rx->bge_idx; 1860 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1861 1862 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1863 have_tag = 1; 1864 vlan_tag = cur_rx->bge_vlan_tag; 1865 } 1866 1867 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1868 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1869 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1870 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1871 jumbocnt++; 1872 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1873 ifp->if_ierrors++; 1874 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1875 continue; 1876 } 1877 if (bge_newbuf_jumbo(sc, 1878 sc->bge_jumbo, NULL) == ENOBUFS) { 1879 ifp->if_ierrors++; 1880 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1881 continue; 1882 } 1883 } else { 1884 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1885 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1886 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1887 stdcnt++; 1888 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1889 ifp->if_ierrors++; 1890 bge_newbuf_std(sc, sc->bge_std, m); 1891 continue; 1892 } 1893 if (bge_newbuf_std(sc, sc->bge_std, 1894 NULL) == ENOBUFS) { 1895 ifp->if_ierrors++; 1896 bge_newbuf_std(sc, sc->bge_std, m); 1897 continue; 1898 } 1899 } 1900 1901 ifp->if_ipackets++; 1902#ifndef __i386__ 1903 /* 1904 * The i386 allows unaligned accesses, but for other 1905 * platforms we must make sure the payload is aligned. 1906 */ 1907 if (sc->bge_rx_alignment_bug) { 1908 bcopy(m->m_data, m->m_data + ETHER_ALIGN, 1909 cur_rx->bge_len); 1910 m->m_data += ETHER_ALIGN; 1911 } 1912#endif 1913 eh = mtod(m, struct ether_header *); 1914 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1915 m->m_pkthdr.rcvif = ifp; 1916 1917#if 0 /* currently broken for some packets, possibly related to TCP options */ 1918 if (ifp->if_hwassist) { 1919 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1920 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1921 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1922 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1923 m->m_pkthdr.csum_data = 1924 cur_rx->bge_tcp_udp_csum; 1925 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1926 } 1927 } 1928#endif 1929 1930 /* 1931 * If we received a packet with a vlan tag, 1932 * attach that information to the packet. 1933 */ 1934 if (have_tag) 1935 VLAN_INPUT_TAG(ifp, m, vlan_tag, continue); 1936 1937 (*ifp->if_input)(ifp, m); 1938 } 1939 1940 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1941 if (stdcnt) 1942 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1943 if (jumbocnt) 1944 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1945 1946 return; 1947} 1948 1949static void 1950bge_txeof(sc) 1951 struct bge_softc *sc; 1952{ 1953 struct bge_tx_bd *cur_tx = NULL; 1954 struct ifnet *ifp; 1955 1956 ifp = &sc->arpcom.ac_if; 1957 1958 /* 1959 * Go through our tx ring and free mbufs for those 1960 * frames that have been sent. 1961 */ 1962 while (sc->bge_tx_saved_considx != 1963 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1964 u_int32_t idx = 0; 1965 1966 idx = sc->bge_tx_saved_considx; 1967 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1968 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1969 ifp->if_opackets++; 1970 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1971 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1972 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1973 } 1974 sc->bge_txcnt--; 1975 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1976 ifp->if_timer = 0; 1977 } 1978 1979 if (cur_tx != NULL) 1980 ifp->if_flags &= ~IFF_OACTIVE; 1981 1982 return; 1983} 1984 1985static void 1986bge_intr(xsc) 1987 void *xsc; 1988{ 1989 struct bge_softc *sc; 1990 struct ifnet *ifp; 1991 1992 sc = xsc; 1993 ifp = &sc->arpcom.ac_if; 1994 1995#ifdef notdef 1996 /* Avoid this for now -- checking this register is expensive. */ 1997 /* Make sure this is really our interrupt. */ 1998 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1999 return; 2000#endif 2001 /* Ack interrupt and stop others from occuring. */ 2002 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2003 2004 /* 2005 * Process link state changes. 2006 * Grrr. The link status word in the status block does 2007 * not work correctly on the BCM5700 rev AX and BX chips, 2008 * according to all avaibable information. Hence, we have 2009 * to enable MII interrupts in order to properly obtain 2010 * async link changes. Unfortunately, this also means that 2011 * we have to read the MAC status register to detect link 2012 * changes, thereby adding an additional register access to 2013 * the interrupt handler. 2014 */ 2015 2016 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2017 u_int32_t status; 2018 2019 status = CSR_READ_4(sc, BGE_MAC_STS); 2020 if (status & BGE_MACSTAT_MI_INTERRUPT) { 2021 sc->bge_link = 0; 2022 untimeout(bge_tick, sc, sc->bge_stat_ch); 2023 bge_tick(sc); 2024 /* Clear the interrupt */ 2025 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2026 BGE_EVTENB_MI_INTERRUPT); 2027 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2028 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2029 BRGPHY_INTRS); 2030 } 2031 } else { 2032 if (sc->bge_rdata->bge_status_block.bge_status & 2033 BGE_STATFLAG_LINKSTATE_CHANGED) { 2034 sc->bge_link = 0; 2035 untimeout(bge_tick, sc, sc->bge_stat_ch); 2036 bge_tick(sc); 2037 /* Clear the interrupt */ 2038 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2039 BGE_MACSTAT_CFG_CHANGED); 2040 } 2041 } 2042 2043 if (ifp->if_flags & IFF_RUNNING) { 2044 /* Check RX return ring producer/consumer */ 2045 bge_rxeof(sc); 2046 2047 /* Check TX ring producer/consumer */ 2048 bge_txeof(sc); 2049 } 2050 2051 bge_handle_events(sc); 2052 2053 /* Re-enable interrupts. */ 2054 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2055 2056 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2057 bge_start(ifp); 2058 2059 return; 2060} 2061 2062static void 2063bge_tick(xsc) 2064 void *xsc; 2065{ 2066 struct bge_softc *sc; 2067 struct mii_data *mii = NULL; 2068 struct ifmedia *ifm = NULL; 2069 struct ifnet *ifp; 2070 int s; 2071 2072 sc = xsc; 2073 ifp = &sc->arpcom.ac_if; 2074 2075 s = splimp(); 2076 2077 bge_stats_update(sc); 2078 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2079 if (sc->bge_link) { 2080 splx(s); 2081 return; 2082 } 2083 2084 if (sc->bge_tbi) { 2085 ifm = &sc->bge_ifmedia; 2086 if (CSR_READ_4(sc, BGE_MAC_STS) & 2087 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2088 sc->bge_link++; 2089 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2090 printf("bge%d: gigabit link up\n", sc->bge_unit); 2091 if (ifp->if_snd.ifq_head != NULL) 2092 bge_start(ifp); 2093 } 2094 splx(s); 2095 return; 2096 } 2097 2098 mii = device_get_softc(sc->bge_miibus); 2099 mii_tick(mii); 2100 2101 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2102 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2103 sc->bge_link++; 2104 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 2105 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2106 printf("bge%d: gigabit link up\n", 2107 sc->bge_unit); 2108 if (ifp->if_snd.ifq_head != NULL) 2109 bge_start(ifp); 2110 } 2111 2112 splx(s); 2113 2114 return; 2115} 2116 2117static void 2118bge_stats_update(sc) 2119 struct bge_softc *sc; 2120{ 2121 struct ifnet *ifp; 2122 struct bge_stats *stats; 2123 2124 ifp = &sc->arpcom.ac_if; 2125 2126 stats = (struct bge_stats *)(sc->bge_vhandle + 2127 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2128 2129 ifp->if_collisions += 2130 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2131 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2132 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2133 stats->dot3StatsLateCollisions.bge_addr_lo) - 2134 ifp->if_collisions; 2135 2136#ifdef notdef 2137 ifp->if_collisions += 2138 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2139 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2140 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2141 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2142 ifp->if_collisions; 2143#endif 2144 2145 return; 2146} 2147 2148/* 2149 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2150 * pointers to descriptors. 2151 */ 2152static int 2153bge_encap(sc, m_head, txidx) 2154 struct bge_softc *sc; 2155 struct mbuf *m_head; 2156 u_int32_t *txidx; 2157{ 2158 struct bge_tx_bd *f = NULL; 2159 struct mbuf *m; 2160 u_int32_t frag, cur, cnt = 0; 2161 u_int16_t csum_flags = 0; 2162 struct m_tag *mtag; 2163 2164 m = m_head; 2165 cur = frag = *txidx; 2166 2167 if (m_head->m_pkthdr.csum_flags) { 2168 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2169 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2170 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2171 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2172 if (m_head->m_flags & M_LASTFRAG) 2173 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2174 else if (m_head->m_flags & M_FRAG) 2175 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2176 } 2177 2178 mtag = VLAN_OUTPUT_TAG(&sc->arpcom.ac_if, m); 2179 2180 /* 2181 * Start packing the mbufs in this chain into 2182 * the fragment pointers. Stop when we run out 2183 * of fragments or hit the end of the mbuf chain. 2184 */ 2185 for (m = m_head; m != NULL; m = m->m_next) { 2186 if (m->m_len != 0) { 2187 f = &sc->bge_rdata->bge_tx_ring[frag]; 2188 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2189 break; 2190 BGE_HOSTADDR(f->bge_addr) = 2191 vtophys(mtod(m, vm_offset_t)); 2192 f->bge_len = m->m_len; 2193 f->bge_flags = csum_flags; 2194 if (mtag != NULL) { 2195 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2196 f->bge_vlan_tag = VLAN_TAG_VALUE(mtag); 2197 } else { 2198 f->bge_vlan_tag = 0; 2199 } 2200 /* 2201 * Sanity check: avoid coming within 16 descriptors 2202 * of the end of the ring. 2203 */ 2204 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2205 return(ENOBUFS); 2206 cur = frag; 2207 BGE_INC(frag, BGE_TX_RING_CNT); 2208 cnt++; 2209 } 2210 } 2211 2212 if (m != NULL) 2213 return(ENOBUFS); 2214 2215 if (frag == sc->bge_tx_saved_considx) 2216 return(ENOBUFS); 2217 2218 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2219 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2220 sc->bge_txcnt += cnt; 2221 2222 *txidx = frag; 2223 2224 return(0); 2225} 2226 2227/* 2228 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2229 * to the mbuf data regions directly in the transmit descriptors. 2230 */ 2231static void 2232bge_start(ifp) 2233 struct ifnet *ifp; 2234{ 2235 struct bge_softc *sc; 2236 struct mbuf *m_head = NULL; 2237 u_int32_t prodidx = 0; 2238 2239 sc = ifp->if_softc; 2240 2241 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2242 return; 2243 2244 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2245 2246 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2247 IF_DEQUEUE(&ifp->if_snd, m_head); 2248 if (m_head == NULL) 2249 break; 2250 2251 /* 2252 * XXX 2253 * safety overkill. If this is a fragmented packet chain 2254 * with delayed TCP/UDP checksums, then only encapsulate 2255 * it if we have enough descriptors to handle the entire 2256 * chain at once. 2257 * (paranoia -- may not actually be needed) 2258 */ 2259 if (m_head->m_flags & M_FIRSTFRAG && 2260 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2261 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2262 m_head->m_pkthdr.csum_data + 16) { 2263 IF_PREPEND(&ifp->if_snd, m_head); 2264 ifp->if_flags |= IFF_OACTIVE; 2265 break; 2266 } 2267 } 2268 2269 /* 2270 * Pack the data into the transmit ring. If we 2271 * don't have room, set the OACTIVE flag and wait 2272 * for the NIC to drain the ring. 2273 */ 2274 if (bge_encap(sc, m_head, &prodidx)) { 2275 IF_PREPEND(&ifp->if_snd, m_head); 2276 ifp->if_flags |= IFF_OACTIVE; 2277 break; 2278 } 2279 2280 /* 2281 * If there's a BPF listener, bounce a copy of this frame 2282 * to him. 2283 */ 2284 BPF_MTAP(ifp, m_head); 2285 } 2286 2287 /* Transmit */ 2288 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2289 2290 /* 2291 * Set a timeout in case the chip goes out to lunch. 2292 */ 2293 ifp->if_timer = 5; 2294 2295 return; 2296} 2297 2298/* 2299 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2300 * program its internal DSP. Failing to do this can result in 2301 * massive packet loss at 1Gb speeds. 2302 */ 2303static void 2304bge_phy_hack(sc) 2305 struct bge_softc *sc; 2306{ 2307 struct bge_bcom_hack bhack[] = { 2308 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2309 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2310 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2311 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2312 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2313 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2314 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2315 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2316 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2317 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2318 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2319 { 0, 0 } }; 2320 u_int16_t vid, did; 2321 int i; 2322 2323 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2324 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2325 2326 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2327 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2328 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2329 i = 0; 2330 while(bhack[i].reg) { 2331 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2332 bhack[i].val); 2333 i++; 2334 } 2335 } 2336 2337 return; 2338} 2339 2340static void 2341bge_init(xsc) 2342 void *xsc; 2343{ 2344 struct bge_softc *sc = xsc; 2345 struct ifnet *ifp; 2346 u_int16_t *m; 2347 int s; 2348 2349 s = splimp(); 2350 2351 ifp = &sc->arpcom.ac_if; 2352 2353 if (ifp->if_flags & IFF_RUNNING) { 2354 splx(s); 2355 return; 2356 } 2357 2358 /* Cancel pending I/O and flush buffers. */ 2359 bge_stop(sc); 2360 bge_reset(sc); 2361 bge_chipinit(sc); 2362 2363 /* 2364 * Init the various state machines, ring 2365 * control blocks and firmware. 2366 */ 2367 if (bge_blockinit(sc)) { 2368 printf("bge%d: initialization failure\n", sc->bge_unit); 2369 splx(s); 2370 return; 2371 } 2372 2373 ifp = &sc->arpcom.ac_if; 2374 2375 /* Specify MTU. */ 2376 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2377 ETHER_HDR_LEN + ETHER_CRC_LEN); 2378 2379 /* Load our MAC address. */ 2380 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2381 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2382 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2383 2384 /* Enable or disable promiscuous mode as needed. */ 2385 if (ifp->if_flags & IFF_PROMISC) { 2386 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2387 } else { 2388 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2389 } 2390 2391 /* Program multicast filter. */ 2392 bge_setmulti(sc); 2393 2394 /* Init RX ring. */ 2395 bge_init_rx_ring_std(sc); 2396 2397 /* Init jumbo RX ring. */ 2398 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2399 bge_init_rx_ring_jumbo(sc); 2400 2401 /* Init our RX return ring index */ 2402 sc->bge_rx_saved_considx = 0; 2403 2404 /* Init TX ring. */ 2405 bge_init_tx_ring(sc); 2406 2407 /* Turn on transmitter */ 2408 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2409 2410 /* Turn on receiver */ 2411 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2412 2413 /* Tell firmware we're alive. */ 2414 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2415 2416 /* Enable host interrupts. */ 2417 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2418 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2419 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2420 2421 bge_ifmedia_upd(ifp); 2422 2423 ifp->if_flags |= IFF_RUNNING; 2424 ifp->if_flags &= ~IFF_OACTIVE; 2425 2426 splx(s); 2427 2428 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2429 2430 return; 2431} 2432 2433/* 2434 * Set media options. 2435 */ 2436static int 2437bge_ifmedia_upd(ifp) 2438 struct ifnet *ifp; 2439{ 2440 struct bge_softc *sc; 2441 struct mii_data *mii; 2442 struct ifmedia *ifm; 2443 2444 sc = ifp->if_softc; 2445 ifm = &sc->bge_ifmedia; 2446 2447 /* If this is a 1000baseX NIC, enable the TBI port. */ 2448 if (sc->bge_tbi) { 2449 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2450 return(EINVAL); 2451 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2452 case IFM_AUTO: 2453 break; 2454 case IFM_1000_SX: 2455 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2456 BGE_CLRBIT(sc, BGE_MAC_MODE, 2457 BGE_MACMODE_HALF_DUPLEX); 2458 } else { 2459 BGE_SETBIT(sc, BGE_MAC_MODE, 2460 BGE_MACMODE_HALF_DUPLEX); 2461 } 2462 break; 2463 default: 2464 return(EINVAL); 2465 } 2466 return(0); 2467 } 2468 2469 mii = device_get_softc(sc->bge_miibus); 2470 sc->bge_link = 0; 2471 if (mii->mii_instance) { 2472 struct mii_softc *miisc; 2473 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2474 miisc = LIST_NEXT(miisc, mii_list)) 2475 mii_phy_reset(miisc); 2476 } 2477 bge_phy_hack(sc); 2478 mii_mediachg(mii); 2479 2480 return(0); 2481} 2482 2483/* 2484 * Report current media status. 2485 */ 2486static void 2487bge_ifmedia_sts(ifp, ifmr) 2488 struct ifnet *ifp; 2489 struct ifmediareq *ifmr; 2490{ 2491 struct bge_softc *sc; 2492 struct mii_data *mii; 2493 2494 sc = ifp->if_softc; 2495 2496 if (sc->bge_tbi) { 2497 ifmr->ifm_status = IFM_AVALID; 2498 ifmr->ifm_active = IFM_ETHER; 2499 if (CSR_READ_4(sc, BGE_MAC_STS) & 2500 BGE_MACSTAT_TBI_PCS_SYNCHED) 2501 ifmr->ifm_status |= IFM_ACTIVE; 2502 ifmr->ifm_active |= IFM_1000_SX; 2503 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2504 ifmr->ifm_active |= IFM_HDX; 2505 else 2506 ifmr->ifm_active |= IFM_FDX; 2507 return; 2508 } 2509 2510 mii = device_get_softc(sc->bge_miibus); 2511 mii_pollstat(mii); 2512 ifmr->ifm_active = mii->mii_media_active; 2513 ifmr->ifm_status = mii->mii_media_status; 2514 2515 return; 2516} 2517 2518static int 2519bge_ioctl(ifp, command, data) 2520 struct ifnet *ifp; 2521 u_long command; 2522 caddr_t data; 2523{ 2524 struct bge_softc *sc = ifp->if_softc; 2525 struct ifreq *ifr = (struct ifreq *) data; 2526 int s, mask, error = 0; 2527 struct mii_data *mii; 2528 2529 s = splimp(); 2530 2531 switch(command) { 2532 case SIOCSIFMTU: 2533 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2534 error = EINVAL; 2535 else { 2536 ifp->if_mtu = ifr->ifr_mtu; 2537 ifp->if_flags &= ~IFF_RUNNING; 2538 bge_init(sc); 2539 } 2540 break; 2541 case SIOCSIFFLAGS: 2542 if (ifp->if_flags & IFF_UP) { 2543 /* 2544 * If only the state of the PROMISC flag changed, 2545 * then just use the 'set promisc mode' command 2546 * instead of reinitializing the entire NIC. Doing 2547 * a full re-init means reloading the firmware and 2548 * waiting for it to start up, which may take a 2549 * second or two. 2550 */ 2551 if (ifp->if_flags & IFF_RUNNING && 2552 ifp->if_flags & IFF_PROMISC && 2553 !(sc->bge_if_flags & IFF_PROMISC)) { 2554 BGE_SETBIT(sc, BGE_RX_MODE, 2555 BGE_RXMODE_RX_PROMISC); 2556 } else if (ifp->if_flags & IFF_RUNNING && 2557 !(ifp->if_flags & IFF_PROMISC) && 2558 sc->bge_if_flags & IFF_PROMISC) { 2559 BGE_CLRBIT(sc, BGE_RX_MODE, 2560 BGE_RXMODE_RX_PROMISC); 2561 } else 2562 bge_init(sc); 2563 } else { 2564 if (ifp->if_flags & IFF_RUNNING) { 2565 bge_stop(sc); 2566 } 2567 } 2568 sc->bge_if_flags = ifp->if_flags; 2569 error = 0; 2570 break; 2571 case SIOCADDMULTI: 2572 case SIOCDELMULTI: 2573 if (ifp->if_flags & IFF_RUNNING) { 2574 bge_setmulti(sc); 2575 error = 0; 2576 } 2577 break; 2578 case SIOCSIFMEDIA: 2579 case SIOCGIFMEDIA: 2580 if (sc->bge_tbi) { 2581 error = ifmedia_ioctl(ifp, ifr, 2582 &sc->bge_ifmedia, command); 2583 } else { 2584 mii = device_get_softc(sc->bge_miibus); 2585 error = ifmedia_ioctl(ifp, ifr, 2586 &mii->mii_media, command); 2587 } 2588 break; 2589 case SIOCSIFCAP: 2590 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2591 if (mask & IFCAP_HWCSUM) { 2592 if (IFCAP_HWCSUM & ifp->if_capenable) 2593 ifp->if_capenable &= ~IFCAP_HWCSUM; 2594 else 2595 ifp->if_capenable |= IFCAP_HWCSUM; 2596 } 2597 error = 0; 2598 break; 2599 default: 2600 error = ether_ioctl(ifp, command, data); 2601 break; 2602 } 2603 2604 (void)splx(s); 2605 2606 return(error); 2607} 2608 2609static void 2610bge_watchdog(ifp) 2611 struct ifnet *ifp; 2612{ 2613 struct bge_softc *sc; 2614 2615 sc = ifp->if_softc; 2616 2617 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2618 2619 ifp->if_flags &= ~IFF_RUNNING; 2620 bge_init(sc); 2621 2622 ifp->if_oerrors++; 2623 2624 return; 2625} 2626 2627/* 2628 * Stop the adapter and free any mbufs allocated to the 2629 * RX and TX lists. 2630 */ 2631static void 2632bge_stop(sc) 2633 struct bge_softc *sc; 2634{ 2635 struct ifnet *ifp; 2636 struct ifmedia_entry *ifm; 2637 struct mii_data *mii = NULL; 2638 int mtmp, itmp; 2639 2640 ifp = &sc->arpcom.ac_if; 2641 2642 if (!sc->bge_tbi) 2643 mii = device_get_softc(sc->bge_miibus); 2644 2645 untimeout(bge_tick, sc, sc->bge_stat_ch); 2646 2647 /* 2648 * Disable all of the receiver blocks 2649 */ 2650 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2651 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2652 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2653 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2654 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2655 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2656 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2657 2658 /* 2659 * Disable all of the transmit blocks 2660 */ 2661 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2662 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2663 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2664 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2665 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2666 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2667 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2668 2669 /* 2670 * Shut down all of the memory managers and related 2671 * state machines. 2672 */ 2673 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2674 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2675 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2676 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2677 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2678 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2679 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2680 2681 /* Disable host interrupts. */ 2682 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2683 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2684 2685 /* 2686 * Tell firmware we're shutting down. 2687 */ 2688 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2689 2690 /* Free the RX lists. */ 2691 bge_free_rx_ring_std(sc); 2692 2693 /* Free jumbo RX list. */ 2694 bge_free_rx_ring_jumbo(sc); 2695 2696 /* Free TX buffers. */ 2697 bge_free_tx_ring(sc); 2698 2699 /* 2700 * Isolate/power down the PHY, but leave the media selection 2701 * unchanged so that things will be put back to normal when 2702 * we bring the interface back up. 2703 */ 2704 if (!sc->bge_tbi) { 2705 itmp = ifp->if_flags; 2706 ifp->if_flags |= IFF_UP; 2707 ifm = mii->mii_media.ifm_cur; 2708 mtmp = ifm->ifm_media; 2709 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2710 mii_mediachg(mii); 2711 ifm->ifm_media = mtmp; 2712 ifp->if_flags = itmp; 2713 } 2714 2715 sc->bge_link = 0; 2716 2717 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2718 2719 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2720 2721 return; 2722} 2723 2724/* 2725 * Stop all chip I/O so that the kernel's probe routines don't 2726 * get confused by errant DMAs when rebooting. 2727 */ 2728static void 2729bge_shutdown(dev) 2730 device_t dev; 2731{ 2732 struct bge_softc *sc; 2733 2734 sc = device_get_softc(dev); 2735 2736 bge_stop(sc); 2737 bge_reset(sc); 2738 2739 return; 2740}
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