1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
| 1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2001 4 * Bill Paul <wpaul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 *
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33 * $FreeBSD: head/sys/dev/bge/if_bge.c 92934 2002-03-22 06:45:40Z wpaul $
| 33 * $FreeBSD: head/sys/dev/bge/if_bge.c 93751 2002-04-04 06:01:31Z wpaul $
|
34 */ 35 36/* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43/* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/sockio.h> 76#include <sys/mbuf.h> 77#include <sys/malloc.h> 78#include <sys/kernel.h> 79#include <sys/socket.h> 80#include <sys/queue.h> 81 82#include <net/if.h> 83#include <net/if_arp.h> 84#include <net/ethernet.h> 85#include <net/if_dl.h> 86#include <net/if_media.h> 87 88#include <net/bpf.h> 89 90#include <net/if_types.h> 91#include <net/if_vlan_var.h> 92 93#include <netinet/in_systm.h> 94#include <netinet/in.h> 95#include <netinet/ip.h> 96 97#include <vm/vm.h> /* for vtophys */ 98#include <vm/pmap.h> /* for vtophys */ 99#include <machine/clock.h> /* for DELAY */ 100#include <machine/bus_memio.h> 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include <dev/mii/miidevs.h> 109#include <dev/mii/brgphyreg.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114#include <dev/bge/if_bgereg.h> 115 116#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 117 118MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#if !defined(lint) 124static const char rcsid[] =
| 34 */ 35 36/* 37 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Engineer, Wind River Systems 41 */ 42 43/* 44 * The Broadcom BCM5700 is based on technology originally developed by 45 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet 46 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has 47 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external 48 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo 49 * frames, highly configurable RX filtering, and 16 RX and TX queues 50 * (which, along with RX filter rules, can be used for QOS applications). 51 * Other features, such as TCP segmentation, may be available as part 52 * of value-added firmware updates. Unlike the Tigon I and Tigon II, 53 * firmware images can be stored in hardware and need not be compiled 54 * into the driver. 55 * 56 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will 57 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus. 58 * 59 * The BCM5701 is a single-chip solution incorporating both the BCM5700 60 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701 61 * does not support external SSRAM. 62 * 63 * Broadcom also produces a variation of the BCM5700 under the "Altima" 64 * brand name, which is functionally similar but lacks PCI-X support. 65 * 66 * Without external SSRAM, you can only have at most 4 TX rings, 67 * and the use of the mini RX ring is disabled. This seems to imply 68 * that these features are simply not available on the BCM5701. As a 69 * result, this driver does not implement any support for the mini RX 70 * ring. 71 */ 72 73#include <sys/param.h> 74#include <sys/systm.h> 75#include <sys/sockio.h> 76#include <sys/mbuf.h> 77#include <sys/malloc.h> 78#include <sys/kernel.h> 79#include <sys/socket.h> 80#include <sys/queue.h> 81 82#include <net/if.h> 83#include <net/if_arp.h> 84#include <net/ethernet.h> 85#include <net/if_dl.h> 86#include <net/if_media.h> 87 88#include <net/bpf.h> 89 90#include <net/if_types.h> 91#include <net/if_vlan_var.h> 92 93#include <netinet/in_systm.h> 94#include <netinet/in.h> 95#include <netinet/ip.h> 96 97#include <vm/vm.h> /* for vtophys */ 98#include <vm/pmap.h> /* for vtophys */ 99#include <machine/clock.h> /* for DELAY */ 100#include <machine/bus_memio.h> 101#include <machine/bus.h> 102#include <machine/resource.h> 103#include <sys/bus.h> 104#include <sys/rman.h> 105 106#include <dev/mii/mii.h> 107#include <dev/mii/miivar.h> 108#include <dev/mii/miidevs.h> 109#include <dev/mii/brgphyreg.h> 110 111#include <pci/pcireg.h> 112#include <pci/pcivar.h> 113 114#include <dev/bge/if_bgereg.h> 115 116#define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP | CSUM_IP_FRAGS) 117 118MODULE_DEPEND(bge, miibus, 1, 1, 1); 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#if !defined(lint) 124static const char rcsid[] =
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125 "$FreeBSD: head/sys/dev/bge/if_bge.c 92934 2002-03-22 06:45:40Z wpaul $";
| 125 "$FreeBSD: head/sys/dev/bge/if_bge.c 93751 2002-04-04 06:01:31Z wpaul $";
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126#endif 127 128/* 129 * Various supported device vendors/types and their names. Note: the 130 * spec seems to indicate that the hardware still has Alteon's vendor 131 * ID burned into it, though it will always be overriden by the vendor 132 * ID in the EEPROM. Just to be safe, we cover all possibilities. 133 */ 134 135static struct bge_type bge_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 141 "Broadcom BCM5700 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 143 "Broadcom BCM5701 Gigabit Ethernet" }, 144 { SK_VENDORID, SK_DEVICEID_ALTIMA, 145 "SysKonnect Gigabit Ethernet" }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 147 "Altima AC1000 Gigabit Ethernet" }, 148 { 0, 0, NULL } 149}; 150 151static int bge_probe (device_t); 152static int bge_attach (device_t); 153static int bge_detach (device_t); 154static void bge_release_resources 155 (struct bge_softc *); 156static void bge_txeof (struct bge_softc *); 157static void bge_rxeof (struct bge_softc *); 158 159static void bge_tick (void *); 160static void bge_stats_update (struct bge_softc *); 161static int bge_encap (struct bge_softc *, struct mbuf *, 162 u_int32_t *); 163 164static void bge_intr (void *); 165static void bge_start (struct ifnet *); 166static int bge_ioctl (struct ifnet *, u_long, caddr_t); 167static void bge_init (void *); 168static void bge_stop (struct bge_softc *); 169static void bge_watchdog (struct ifnet *); 170static void bge_shutdown (device_t); 171static int bge_ifmedia_upd (struct ifnet *); 172static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 173 174static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 175static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 176 177static u_int32_t bge_crc (caddr_t); 178static void bge_setmulti (struct bge_softc *); 179 180static void bge_handle_events (struct bge_softc *); 181static int bge_alloc_jumbo_mem (struct bge_softc *); 182static void bge_free_jumbo_mem (struct bge_softc *); 183static void *bge_jalloc (struct bge_softc *); 184static void bge_jfree (caddr_t, void *); 185static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 186static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 187static int bge_init_rx_ring_std (struct bge_softc *); 188static void bge_free_rx_ring_std (struct bge_softc *); 189static int bge_init_rx_ring_jumbo (struct bge_softc *); 190static void bge_free_rx_ring_jumbo (struct bge_softc *); 191static void bge_free_tx_ring (struct bge_softc *); 192static int bge_init_tx_ring (struct bge_softc *); 193 194static int bge_chipinit (struct bge_softc *); 195static int bge_blockinit (struct bge_softc *); 196 197#ifdef notdef 198static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 199static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 200static void bge_vpd_read (struct bge_softc *); 201#endif 202 203static u_int32_t bge_readmem_ind 204 (struct bge_softc *, int); 205static void bge_writemem_ind (struct bge_softc *, int, int); 206#ifdef notdef 207static u_int32_t bge_readreg_ind 208 (struct bge_softc *, int); 209#endif 210static void bge_writereg_ind (struct bge_softc *, int, int); 211 212static int bge_miibus_readreg (device_t, int, int); 213static int bge_miibus_writereg (device_t, int, int, int); 214static void bge_miibus_statchg (device_t); 215 216static void bge_reset (struct bge_softc *); 217static void bge_phy_hack (struct bge_softc *); 218 219static device_method_t bge_methods[] = { 220 /* Device interface */ 221 DEVMETHOD(device_probe, bge_probe), 222 DEVMETHOD(device_attach, bge_attach), 223 DEVMETHOD(device_detach, bge_detach), 224 DEVMETHOD(device_shutdown, bge_shutdown), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 232 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 233 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 234 235 { 0, 0 } 236}; 237 238static driver_t bge_driver = { 239 "bge", 240 bge_methods, 241 sizeof(struct bge_softc) 242}; 243 244static devclass_t bge_devclass; 245 246DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 247DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 248 249static u_int32_t 250bge_readmem_ind(sc, off) 251 struct bge_softc *sc; 252 int off; 253{ 254 device_t dev; 255 256 dev = sc->bge_dev; 257 258 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 259 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 260} 261 262static void 263bge_writemem_ind(sc, off, val) 264 struct bge_softc *sc; 265 int off, val; 266{ 267 device_t dev; 268 269 dev = sc->bge_dev; 270 271 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 272 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 273 274 return; 275} 276 277#ifdef notdef 278static u_int32_t 279bge_readreg_ind(sc, off) 280 struct bge_softc *sc; 281 int off; 282{ 283 device_t dev; 284 285 dev = sc->bge_dev; 286 287 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 288 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 289} 290#endif 291 292static void 293bge_writereg_ind(sc, off, val) 294 struct bge_softc *sc; 295 int off, val; 296{ 297 device_t dev; 298 299 dev = sc->bge_dev; 300 301 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 302 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 303 304 return; 305} 306 307#ifdef notdef 308static u_int8_t 309bge_vpd_readbyte(sc, addr) 310 struct bge_softc *sc; 311 int addr; 312{ 313 int i; 314 device_t dev; 315 u_int32_t val; 316 317 dev = sc->bge_dev; 318 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 319 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 320 DELAY(10); 321 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 322 break; 323 } 324 325 if (i == BGE_TIMEOUT) { 326 printf("bge%d: VPD read timed out\n", sc->bge_unit); 327 return(0); 328 } 329 330 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 331 332 return((val >> ((addr % 4) * 8)) & 0xFF); 333} 334 335static void 336bge_vpd_read_res(sc, res, addr) 337 struct bge_softc *sc; 338 struct vpd_res *res; 339 int addr; 340{ 341 int i; 342 u_int8_t *ptr; 343 344 ptr = (u_int8_t *)res; 345 for (i = 0; i < sizeof(struct vpd_res); i++) 346 ptr[i] = bge_vpd_readbyte(sc, i + addr); 347 348 return; 349} 350 351static void 352bge_vpd_read(sc) 353 struct bge_softc *sc; 354{ 355 int pos = 0, i; 356 struct vpd_res res; 357 358 if (sc->bge_vpd_prodname != NULL) 359 free(sc->bge_vpd_prodname, M_DEVBUF); 360 if (sc->bge_vpd_readonly != NULL) 361 free(sc->bge_vpd_readonly, M_DEVBUF); 362 sc->bge_vpd_prodname = NULL; 363 sc->bge_vpd_readonly = NULL; 364 365 bge_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_ID) { 368 printf("bge%d: bad VPD resource id: expected %x got %x\n", 369 sc->bge_unit, VPD_RES_ID, res.vr_id); 370 return; 371 } 372 373 pos += sizeof(res); 374 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 375 for (i = 0; i < res.vr_len; i++) 376 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 377 sc->bge_vpd_prodname[i] = '\0'; 378 pos += i; 379 380 bge_vpd_read_res(sc, &res, pos); 381 382 if (res.vr_id != VPD_RES_READ) { 383 printf("bge%d: bad VPD resource id: expected %x got %x\n", 384 sc->bge_unit, VPD_RES_READ, res.vr_id); 385 return; 386 } 387 388 pos += sizeof(res); 389 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 390 for (i = 0; i < res.vr_len + 1; i++) 391 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 392 393 return; 394} 395#endif 396 397/* 398 * Read a byte of data stored in the EEPROM at address 'addr.' The 399 * BCM570x supports both the traditional bitbang interface and an 400 * auto access interface for reading the EEPROM. We use the auto 401 * access method. 402 */ 403static u_int8_t 404bge_eeprom_getbyte(sc, addr, dest) 405 struct bge_softc *sc; 406 int addr; 407 u_int8_t *dest; 408{ 409 int i; 410 u_int32_t byte = 0; 411 412 /* 413 * Enable use of auto EEPROM access so we can avoid 414 * having to use the bitbang method. 415 */ 416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 417 418 /* Reset the EEPROM, load the clock period. */ 419 CSR_WRITE_4(sc, BGE_EE_ADDR, 420 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 421 DELAY(20); 422 423 /* Issue the read EEPROM command. */ 424 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 425 426 /* Wait for completion */ 427 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 428 DELAY(10); 429 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 430 break; 431 } 432 433 if (i == BGE_TIMEOUT) { 434 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 435 return(0); 436 } 437 438 /* Get result. */ 439 byte = CSR_READ_4(sc, BGE_EE_DATA); 440 441 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 442 443 return(0); 444} 445 446/* 447 * Read a sequence of bytes from the EEPROM. 448 */ 449static int 450bge_read_eeprom(sc, dest, off, cnt) 451 struct bge_softc *sc; 452 caddr_t dest; 453 int off; 454 int cnt; 455{ 456 int err = 0, i; 457 u_int8_t byte = 0; 458 459 for (i = 0; i < cnt; i++) { 460 err = bge_eeprom_getbyte(sc, off + i, &byte); 461 if (err) 462 break; 463 *(dest + i) = byte; 464 } 465 466 return(err ? 1 : 0); 467} 468 469static int 470bge_miibus_readreg(dev, phy, reg) 471 device_t dev; 472 int phy, reg; 473{ 474 struct bge_softc *sc; 475 struct ifnet *ifp; 476 u_int32_t val; 477 int i; 478 479 sc = device_get_softc(dev); 480 ifp = &sc->arpcom.ac_if; 481 482 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 483 return(0); 484
| 126#endif 127 128/* 129 * Various supported device vendors/types and their names. Note: the 130 * spec seems to indicate that the hardware still has Alteon's vendor 131 * ID burned into it, though it will always be overriden by the vendor 132 * ID in the EEPROM. Just to be safe, we cover all possibilities. 133 */ 134 135static struct bge_type bge_devs[] = { 136 { ALT_VENDORID, ALT_DEVICEID_BCM5700, 137 "Broadcom BCM5700 Gigabit Ethernet" }, 138 { ALT_VENDORID, ALT_DEVICEID_BCM5701, 139 "Broadcom BCM5701 Gigabit Ethernet" }, 140 { BCOM_VENDORID, BCOM_DEVICEID_BCM5700, 141 "Broadcom BCM5700 Gigabit Ethernet" }, 142 { BCOM_VENDORID, BCOM_DEVICEID_BCM5701, 143 "Broadcom BCM5701 Gigabit Ethernet" }, 144 { SK_VENDORID, SK_DEVICEID_ALTIMA, 145 "SysKonnect Gigabit Ethernet" }, 146 { ALTIMA_VENDORID, ALTIMA_DEVICE_AC1000, 147 "Altima AC1000 Gigabit Ethernet" }, 148 { 0, 0, NULL } 149}; 150 151static int bge_probe (device_t); 152static int bge_attach (device_t); 153static int bge_detach (device_t); 154static void bge_release_resources 155 (struct bge_softc *); 156static void bge_txeof (struct bge_softc *); 157static void bge_rxeof (struct bge_softc *); 158 159static void bge_tick (void *); 160static void bge_stats_update (struct bge_softc *); 161static int bge_encap (struct bge_softc *, struct mbuf *, 162 u_int32_t *); 163 164static void bge_intr (void *); 165static void bge_start (struct ifnet *); 166static int bge_ioctl (struct ifnet *, u_long, caddr_t); 167static void bge_init (void *); 168static void bge_stop (struct bge_softc *); 169static void bge_watchdog (struct ifnet *); 170static void bge_shutdown (device_t); 171static int bge_ifmedia_upd (struct ifnet *); 172static void bge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 173 174static u_int8_t bge_eeprom_getbyte (struct bge_softc *, int, u_int8_t *); 175static int bge_read_eeprom (struct bge_softc *, caddr_t, int, int); 176 177static u_int32_t bge_crc (caddr_t); 178static void bge_setmulti (struct bge_softc *); 179 180static void bge_handle_events (struct bge_softc *); 181static int bge_alloc_jumbo_mem (struct bge_softc *); 182static void bge_free_jumbo_mem (struct bge_softc *); 183static void *bge_jalloc (struct bge_softc *); 184static void bge_jfree (caddr_t, void *); 185static int bge_newbuf_std (struct bge_softc *, int, struct mbuf *); 186static int bge_newbuf_jumbo (struct bge_softc *, int, struct mbuf *); 187static int bge_init_rx_ring_std (struct bge_softc *); 188static void bge_free_rx_ring_std (struct bge_softc *); 189static int bge_init_rx_ring_jumbo (struct bge_softc *); 190static void bge_free_rx_ring_jumbo (struct bge_softc *); 191static void bge_free_tx_ring (struct bge_softc *); 192static int bge_init_tx_ring (struct bge_softc *); 193 194static int bge_chipinit (struct bge_softc *); 195static int bge_blockinit (struct bge_softc *); 196 197#ifdef notdef 198static u_int8_t bge_vpd_readbyte(struct bge_softc *, int); 199static void bge_vpd_read_res (struct bge_softc *, struct vpd_res *, int); 200static void bge_vpd_read (struct bge_softc *); 201#endif 202 203static u_int32_t bge_readmem_ind 204 (struct bge_softc *, int); 205static void bge_writemem_ind (struct bge_softc *, int, int); 206#ifdef notdef 207static u_int32_t bge_readreg_ind 208 (struct bge_softc *, int); 209#endif 210static void bge_writereg_ind (struct bge_softc *, int, int); 211 212static int bge_miibus_readreg (device_t, int, int); 213static int bge_miibus_writereg (device_t, int, int, int); 214static void bge_miibus_statchg (device_t); 215 216static void bge_reset (struct bge_softc *); 217static void bge_phy_hack (struct bge_softc *); 218 219static device_method_t bge_methods[] = { 220 /* Device interface */ 221 DEVMETHOD(device_probe, bge_probe), 222 DEVMETHOD(device_attach, bge_attach), 223 DEVMETHOD(device_detach, bge_detach), 224 DEVMETHOD(device_shutdown, bge_shutdown), 225 226 /* bus interface */ 227 DEVMETHOD(bus_print_child, bus_generic_print_child), 228 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 229 230 /* MII interface */ 231 DEVMETHOD(miibus_readreg, bge_miibus_readreg), 232 DEVMETHOD(miibus_writereg, bge_miibus_writereg), 233 DEVMETHOD(miibus_statchg, bge_miibus_statchg), 234 235 { 0, 0 } 236}; 237 238static driver_t bge_driver = { 239 "bge", 240 bge_methods, 241 sizeof(struct bge_softc) 242}; 243 244static devclass_t bge_devclass; 245 246DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0); 247DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0); 248 249static u_int32_t 250bge_readmem_ind(sc, off) 251 struct bge_softc *sc; 252 int off; 253{ 254 device_t dev; 255 256 dev = sc->bge_dev; 257 258 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 259 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4)); 260} 261 262static void 263bge_writemem_ind(sc, off, val) 264 struct bge_softc *sc; 265 int off, val; 266{ 267 device_t dev; 268 269 dev = sc->bge_dev; 270 271 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4); 272 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4); 273 274 return; 275} 276 277#ifdef notdef 278static u_int32_t 279bge_readreg_ind(sc, off) 280 struct bge_softc *sc; 281 int off; 282{ 283 device_t dev; 284 285 dev = sc->bge_dev; 286 287 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 288 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4)); 289} 290#endif 291 292static void 293bge_writereg_ind(sc, off, val) 294 struct bge_softc *sc; 295 int off, val; 296{ 297 device_t dev; 298 299 dev = sc->bge_dev; 300 301 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4); 302 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4); 303 304 return; 305} 306 307#ifdef notdef 308static u_int8_t 309bge_vpd_readbyte(sc, addr) 310 struct bge_softc *sc; 311 int addr; 312{ 313 int i; 314 device_t dev; 315 u_int32_t val; 316 317 dev = sc->bge_dev; 318 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2); 319 for (i = 0; i < BGE_TIMEOUT * 10; i++) { 320 DELAY(10); 321 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG) 322 break; 323 } 324 325 if (i == BGE_TIMEOUT) { 326 printf("bge%d: VPD read timed out\n", sc->bge_unit); 327 return(0); 328 } 329 330 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4); 331 332 return((val >> ((addr % 4) * 8)) & 0xFF); 333} 334 335static void 336bge_vpd_read_res(sc, res, addr) 337 struct bge_softc *sc; 338 struct vpd_res *res; 339 int addr; 340{ 341 int i; 342 u_int8_t *ptr; 343 344 ptr = (u_int8_t *)res; 345 for (i = 0; i < sizeof(struct vpd_res); i++) 346 ptr[i] = bge_vpd_readbyte(sc, i + addr); 347 348 return; 349} 350 351static void 352bge_vpd_read(sc) 353 struct bge_softc *sc; 354{ 355 int pos = 0, i; 356 struct vpd_res res; 357 358 if (sc->bge_vpd_prodname != NULL) 359 free(sc->bge_vpd_prodname, M_DEVBUF); 360 if (sc->bge_vpd_readonly != NULL) 361 free(sc->bge_vpd_readonly, M_DEVBUF); 362 sc->bge_vpd_prodname = NULL; 363 sc->bge_vpd_readonly = NULL; 364 365 bge_vpd_read_res(sc, &res, pos); 366 367 if (res.vr_id != VPD_RES_ID) { 368 printf("bge%d: bad VPD resource id: expected %x got %x\n", 369 sc->bge_unit, VPD_RES_ID, res.vr_id); 370 return; 371 } 372 373 pos += sizeof(res); 374 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_NOWAIT); 375 for (i = 0; i < res.vr_len; i++) 376 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos); 377 sc->bge_vpd_prodname[i] = '\0'; 378 pos += i; 379 380 bge_vpd_read_res(sc, &res, pos); 381 382 if (res.vr_id != VPD_RES_READ) { 383 printf("bge%d: bad VPD resource id: expected %x got %x\n", 384 sc->bge_unit, VPD_RES_READ, res.vr_id); 385 return; 386 } 387 388 pos += sizeof(res); 389 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_NOWAIT); 390 for (i = 0; i < res.vr_len + 1; i++) 391 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos); 392 393 return; 394} 395#endif 396 397/* 398 * Read a byte of data stored in the EEPROM at address 'addr.' The 399 * BCM570x supports both the traditional bitbang interface and an 400 * auto access interface for reading the EEPROM. We use the auto 401 * access method. 402 */ 403static u_int8_t 404bge_eeprom_getbyte(sc, addr, dest) 405 struct bge_softc *sc; 406 int addr; 407 u_int8_t *dest; 408{ 409 int i; 410 u_int32_t byte = 0; 411 412 /* 413 * Enable use of auto EEPROM access so we can avoid 414 * having to use the bitbang method. 415 */ 416 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM); 417 418 /* Reset the EEPROM, load the clock period. */ 419 CSR_WRITE_4(sc, BGE_EE_ADDR, 420 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL)); 421 DELAY(20); 422 423 /* Issue the read EEPROM command. */ 424 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr); 425 426 /* Wait for completion */ 427 for(i = 0; i < BGE_TIMEOUT * 10; i++) { 428 DELAY(10); 429 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE) 430 break; 431 } 432 433 if (i == BGE_TIMEOUT) { 434 printf("bge%d: eeprom read timed out\n", sc->bge_unit); 435 return(0); 436 } 437 438 /* Get result. */ 439 byte = CSR_READ_4(sc, BGE_EE_DATA); 440 441 *dest = (byte >> ((addr % 4) * 8)) & 0xFF; 442 443 return(0); 444} 445 446/* 447 * Read a sequence of bytes from the EEPROM. 448 */ 449static int 450bge_read_eeprom(sc, dest, off, cnt) 451 struct bge_softc *sc; 452 caddr_t dest; 453 int off; 454 int cnt; 455{ 456 int err = 0, i; 457 u_int8_t byte = 0; 458 459 for (i = 0; i < cnt; i++) { 460 err = bge_eeprom_getbyte(sc, off + i, &byte); 461 if (err) 462 break; 463 *(dest + i) = byte; 464 } 465 466 return(err ? 1 : 0); 467} 468 469static int 470bge_miibus_readreg(dev, phy, reg) 471 device_t dev; 472 int phy, reg; 473{ 474 struct bge_softc *sc; 475 struct ifnet *ifp; 476 u_int32_t val; 477 int i; 478 479 sc = device_get_softc(dev); 480 ifp = &sc->arpcom.ac_if; 481 482 if (sc->bge_asicrev == BGE_ASICREV_BCM5701_B5 && phy != 1) 483 return(0); 484
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485 if (ifp->if_flags & IFF_RUNNING) 486 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 487
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488 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 489 BGE_MIPHY(phy)|BGE_MIREG(reg)); 490 491 for (i = 0; i < BGE_TIMEOUT; i++) { 492 val = CSR_READ_4(sc, BGE_MI_COMM); 493 if (!(val & BGE_MICOMM_BUSY)) 494 break; 495 } 496 497 if (i == BGE_TIMEOUT) { 498 printf("bge%d: PHY read timed out\n", sc->bge_unit); 499 return(0); 500 } 501 502 val = CSR_READ_4(sc, BGE_MI_COMM); 503
| 485 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY| 486 BGE_MIPHY(phy)|BGE_MIREG(reg)); 487 488 for (i = 0; i < BGE_TIMEOUT; i++) { 489 val = CSR_READ_4(sc, BGE_MI_COMM); 490 if (!(val & BGE_MICOMM_BUSY)) 491 break; 492 } 493 494 if (i == BGE_TIMEOUT) { 495 printf("bge%d: PHY read timed out\n", sc->bge_unit); 496 return(0); 497 } 498 499 val = CSR_READ_4(sc, BGE_MI_COMM); 500
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504 if (ifp->if_flags & IFF_RUNNING) 505 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL); 506
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507 if (val & BGE_MICOMM_READFAIL) 508 return(0); 509 510 return(val & 0xFFFF); 511} 512 513static int 514bge_miibus_writereg(dev, phy, reg, val) 515 device_t dev; 516 int phy, reg, val; 517{ 518 struct bge_softc *sc; 519 int i; 520 521 sc = device_get_softc(dev); 522 523 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 524 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 525 526 for (i = 0; i < BGE_TIMEOUT; i++) { 527 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 528 break; 529 } 530 531 if (i == BGE_TIMEOUT) { 532 printf("bge%d: PHY read timed out\n", sc->bge_unit); 533 return(0); 534 } 535 536 return(0); 537} 538 539static void 540bge_miibus_statchg(dev) 541 device_t dev; 542{ 543 struct bge_softc *sc; 544 struct mii_data *mii; 545 546 sc = device_get_softc(dev); 547 mii = device_get_softc(sc->bge_miibus); 548 549 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 550 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 551 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 552 } else { 553 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 554 } 555 556 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 557 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 558 } else { 559 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 560 } 561 562 bge_phy_hack(sc); 563 564 return; 565} 566 567/* 568 * Handle events that have triggered interrupts. 569 */ 570static void 571bge_handle_events(sc) 572 struct bge_softc *sc; 573{ 574 575 return; 576} 577 578/* 579 * Memory management for jumbo frames. 580 */ 581 582static int 583bge_alloc_jumbo_mem(sc) 584 struct bge_softc *sc; 585{ 586 caddr_t ptr; 587 register int i; 588 struct bge_jpool_entry *entry; 589 590 /* Grab a big chunk o' storage. */ 591 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 592 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 593 594 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 595 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 596 return(ENOBUFS); 597 } 598 599 SLIST_INIT(&sc->bge_jfree_listhead); 600 SLIST_INIT(&sc->bge_jinuse_listhead); 601 602 /* 603 * Now divide it up into 9K pieces and save the addresses 604 * in an array. 605 */ 606 ptr = sc->bge_cdata.bge_jumbo_buf; 607 for (i = 0; i < BGE_JSLOTS; i++) { 608 sc->bge_cdata.bge_jslots[i] = ptr; 609 ptr += BGE_JLEN; 610 entry = malloc(sizeof(struct bge_jpool_entry), 611 M_DEVBUF, M_NOWAIT); 612 if (entry == NULL) { 613 contigfree(sc->bge_cdata.bge_jumbo_buf, 614 BGE_JMEM, M_DEVBUF); 615 sc->bge_cdata.bge_jumbo_buf = NULL; 616 printf("bge%d: no memory for jumbo " 617 "buffer queue!\n", sc->bge_unit); 618 return(ENOBUFS); 619 } 620 entry->slot = i; 621 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 622 entry, jpool_entries); 623 } 624 625 return(0); 626} 627 628static void 629bge_free_jumbo_mem(sc) 630 struct bge_softc *sc; 631{ 632 int i; 633 struct bge_jpool_entry *entry; 634 635 for (i = 0; i < BGE_JSLOTS; i++) { 636 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 637 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 638 free(entry, M_DEVBUF); 639 } 640 641 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 642 643 return; 644} 645 646/* 647 * Allocate a jumbo buffer. 648 */ 649static void * 650bge_jalloc(sc) 651 struct bge_softc *sc; 652{ 653 struct bge_jpool_entry *entry; 654 655 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 656 657 if (entry == NULL) { 658 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 659 return(NULL); 660 } 661 662 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 663 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 664 return(sc->bge_cdata.bge_jslots[entry->slot]); 665} 666 667/* 668 * Release a jumbo buffer. 669 */ 670static void 671bge_jfree(buf, args) 672 caddr_t buf; 673 void *args; 674{ 675 struct bge_jpool_entry *entry; 676 struct bge_softc *sc; 677 int i; 678 679 /* Extract the softc struct pointer. */ 680 sc = (struct bge_softc *)args; 681 682 if (sc == NULL) 683 panic("bge_jfree: can't find softc pointer!"); 684 685 /* calculate the slot this buffer belongs to */ 686 687 i = ((vm_offset_t)buf 688 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 689 690 if ((i < 0) || (i >= BGE_JSLOTS)) 691 panic("bge_jfree: asked to free buffer that we don't manage!"); 692 693 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 694 if (entry == NULL) 695 panic("bge_jfree: buffer not in use!"); 696 entry->slot = i; 697 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 698 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 699 700 return; 701} 702 703 704/* 705 * Intialize a standard receive ring descriptor. 706 */ 707static int 708bge_newbuf_std(sc, i, m) 709 struct bge_softc *sc; 710 int i; 711 struct mbuf *m; 712{ 713 struct mbuf *m_new = NULL; 714 struct bge_rx_bd *r; 715 716 if (m == NULL) { 717 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 718 if (m_new == NULL) { 719 return(ENOBUFS); 720 } 721 722 MCLGET(m_new, M_DONTWAIT); 723 if (!(m_new->m_flags & M_EXT)) { 724 m_freem(m_new); 725 return(ENOBUFS); 726 } 727 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 728 } else { 729 m_new = m; 730 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 731 m_new->m_data = m_new->m_ext.ext_buf; 732 } 733 734 m_adj(m_new, ETHER_ALIGN); 735 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 736 r = &sc->bge_rdata->bge_rx_std_ring[i]; 737 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 738 r->bge_flags = BGE_RXBDFLAG_END; 739 r->bge_len = m_new->m_len; 740 r->bge_idx = i; 741 742 return(0); 743} 744 745/* 746 * Initialize a jumbo receive ring descriptor. This allocates 747 * a jumbo buffer from the pool managed internally by the driver. 748 */ 749static int 750bge_newbuf_jumbo(sc, i, m) 751 struct bge_softc *sc; 752 int i; 753 struct mbuf *m; 754{ 755 struct mbuf *m_new = NULL; 756 struct bge_rx_bd *r; 757 758 if (m == NULL) { 759 caddr_t *buf = NULL; 760 761 /* Allocate the mbuf. */ 762 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 763 if (m_new == NULL) { 764 return(ENOBUFS); 765 } 766 767 /* Allocate the jumbo buffer */ 768 buf = bge_jalloc(sc); 769 if (buf == NULL) { 770 m_freem(m_new); 771 printf("bge%d: jumbo allocation failed " 772 "-- packet dropped!\n", sc->bge_unit); 773 return(ENOBUFS); 774 } 775 776 /* Attach the buffer to the mbuf. */ 777 m_new->m_data = (void *) buf; 778 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 779 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 780 (struct bge_softc *)sc, 0, EXT_NET_DRV); 781 } else { 782 m_new = m; 783 m_new->m_data = m_new->m_ext.ext_buf; 784 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 785 } 786 787 m_adj(m_new, ETHER_ALIGN); 788 /* Set up the descriptor. */ 789 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 790 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 791 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 792 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 793 r->bge_len = m_new->m_len; 794 r->bge_idx = i; 795 796 return(0); 797} 798 799/* 800 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 801 * that's 1MB or memory, which is a lot. For now, we fill only the first 802 * 256 ring entries and hope that our CPU is fast enough to keep up with 803 * the NIC. 804 */ 805static int 806bge_init_rx_ring_std(sc) 807 struct bge_softc *sc; 808{ 809 int i; 810 811 for (i = 0; i < BGE_SSLOTS; i++) { 812 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 813 return(ENOBUFS); 814 }; 815 816 sc->bge_std = i - 1; 817 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 818 819 return(0); 820} 821 822static void 823bge_free_rx_ring_std(sc) 824 struct bge_softc *sc; 825{ 826 int i; 827 828 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 829 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 830 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 831 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 832 } 833 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 834 sizeof(struct bge_rx_bd)); 835 } 836 837 return; 838} 839 840static int 841bge_init_rx_ring_jumbo(sc) 842 struct bge_softc *sc; 843{ 844 int i; 845 struct bge_rcb *rcb; 846 struct bge_rcb_opaque *rcbo; 847 848 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 849 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 850 return(ENOBUFS); 851 }; 852 853 sc->bge_jumbo = i - 1; 854 855 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 856 rcbo = (struct bge_rcb_opaque *)rcb; 857 rcb->bge_flags = 0; 858 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 859 860 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 861 862 return(0); 863} 864 865static void 866bge_free_rx_ring_jumbo(sc) 867 struct bge_softc *sc; 868{ 869 int i; 870 871 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 872 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 873 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 874 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 875 } 876 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 877 sizeof(struct bge_rx_bd)); 878 } 879 880 return; 881} 882 883static void 884bge_free_tx_ring(sc) 885 struct bge_softc *sc; 886{ 887 int i; 888 889 if (sc->bge_rdata->bge_tx_ring == NULL) 890 return; 891 892 for (i = 0; i < BGE_TX_RING_CNT; i++) { 893 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 894 m_freem(sc->bge_cdata.bge_tx_chain[i]); 895 sc->bge_cdata.bge_tx_chain[i] = NULL; 896 } 897 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 898 sizeof(struct bge_tx_bd)); 899 } 900 901 return; 902} 903 904static int 905bge_init_tx_ring(sc) 906 struct bge_softc *sc; 907{ 908 sc->bge_txcnt = 0; 909 sc->bge_tx_saved_considx = 0; 910 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 911 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 912 913 return(0); 914} 915 916#define BGE_POLY 0xEDB88320 917 918static u_int32_t 919bge_crc(addr) 920 caddr_t addr; 921{ 922 u_int32_t idx, bit, data, crc; 923 924 /* Compute CRC for the address value. */ 925 crc = 0xFFFFFFFF; /* initial value */ 926 927 for (idx = 0; idx < 6; idx++) { 928 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 929 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 930 } 931 932 return(crc & 0x7F); 933} 934 935static void 936bge_setmulti(sc) 937 struct bge_softc *sc; 938{ 939 struct ifnet *ifp; 940 struct ifmultiaddr *ifma; 941 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 942 int h, i; 943 944 ifp = &sc->arpcom.ac_if; 945 946 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 947 for (i = 0; i < 4; i++) 948 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 949 return; 950 } 951 952 /* First, zot all the existing filters. */ 953 for (i = 0; i < 4; i++) 954 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 955 956 /* Now program new ones. */ 957 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 958 if (ifma->ifma_addr->sa_family != AF_LINK) 959 continue; 960 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 961 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 962 } 963 964 for (i = 0; i < 4; i++) 965 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 966 967 return; 968} 969 970/* 971 * Do endian, PCI and DMA initialization. Also check the on-board ROM 972 * self-test results. 973 */ 974static int 975bge_chipinit(sc) 976 struct bge_softc *sc; 977{ 978 u_int32_t cachesize; 979 int i; 980 981 /* Set endianness before we access any non-PCI registers. */ 982#if BYTE_ORDER == BIG_ENDIAN 983 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 984 BGE_BIGENDIAN_INIT, 4); 985#else 986 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 987 BGE_LITTLEENDIAN_INIT, 4); 988#endif 989 990 /* 991 * Check the 'ROM failed' bit on the RX CPU to see if 992 * self-tests passed. 993 */ 994 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 995 printf("bge%d: RX CPU self-diagnostics failed!\n", 996 sc->bge_unit); 997 return(ENODEV); 998 } 999 1000 /* Clear the MAC control register */ 1001 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1002 1003 /* 1004 * Clear the MAC statistics block in the NIC's 1005 * internal memory. 1006 */ 1007 for (i = BGE_STATS_BLOCK; 1008 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1009 BGE_MEMWIN_WRITE(sc, i, 0); 1010 1011 for (i = BGE_STATUS_BLOCK; 1012 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1013 BGE_MEMWIN_WRITE(sc, i, 0); 1014 1015 /* Set up the PCI DMA control register. */ 1016 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1017 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4); 1018 1019 /* 1020 * Set up general mode register. 1021 */ 1022 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1023 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1024 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1025 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1026 BGE_MODECTL_RX_NO_PHDR_CSUM); 1027 1028 /* Get cache line size. */ 1029 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); 1030 1031 /* 1032 * Avoid violating PCI spec on certain chip revs. 1033 */ 1034 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { 1035 switch(cachesize) { 1036 case 1: 1037 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1038 BGE_PCI_WRITE_BNDRY_16BYTES, 4); 1039 break; 1040 case 2: 1041 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1042 BGE_PCI_WRITE_BNDRY_32BYTES, 4); 1043 break; 1044 case 4: 1045 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1046 BGE_PCI_WRITE_BNDRY_64BYTES, 4); 1047 break; 1048 case 8: 1049 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1050 BGE_PCI_WRITE_BNDRY_128BYTES, 4); 1051 break; 1052 case 16: 1053 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1054 BGE_PCI_WRITE_BNDRY_256BYTES, 4); 1055 break; 1056 case 32: 1057 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1058 BGE_PCI_WRITE_BNDRY_512BYTES, 4); 1059 break; 1060 case 64: 1061 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1062 BGE_PCI_WRITE_BNDRY_1024BYTES, 4); 1063 break; 1064 default: 1065 /* Disable PCI memory write and invalidate. */ 1066 if (bootverbose) 1067 printf("bge%d: cache line size %d not " 1068 "supported; disabling PCI MWI\n", 1069 sc->bge_unit, cachesize); 1070 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1071 PCIM_CMD_MWIEN, 4); 1072 break; 1073 } 1074 } 1075 1076#ifdef __brokenalpha__ 1077 /* 1078 * Must insure that we do not cross an 8K (bytes) boundary 1079 * for DMA reads. Our highest limit is 1K bytes. This is a 1080 * restriction on some ALPHA platforms with early revision 1081 * 21174 PCI chipsets, such as the AlphaPC 164lx 1082 */ 1083 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1084#endif 1085 1086 /* Set the timer prescaler (always 66Mhz) */ 1087 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1088 1089 return(0); 1090} 1091 1092static int 1093bge_blockinit(sc) 1094 struct bge_softc *sc; 1095{ 1096 struct bge_rcb *rcb; 1097 struct bge_rcb_opaque *rcbo; 1098 int i; 1099 1100 /* 1101 * Initialize the memory window pointer register so that 1102 * we can access the first 32K of internal NIC RAM. This will 1103 * allow us to set up the TX send ring RCBs and the RX return 1104 * ring RCBs, plus other things which live in NIC memory. 1105 */ 1106 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1107 1108 /* Configure mbuf memory pool */ 1109 if (sc->bge_extram) { 1110 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1111 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1112 } else { 1113 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1114 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1115 } 1116 1117 /* Configure DMA resource pool */ 1118 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1119 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1120 1121 /* Configure mbuf pool watermarks */ 1122 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1123 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1124 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1125 1126 /* Configure DMA resource watermarks */ 1127 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1128 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1129 1130 /* Enable buffer manager */ 1131 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1132 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1133 1134 /* Poll for buffer manager start indication */ 1135 for (i = 0; i < BGE_TIMEOUT; i++) { 1136 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1137 break; 1138 DELAY(10); 1139 } 1140 1141 if (i == BGE_TIMEOUT) { 1142 printf("bge%d: buffer manager failed to start\n", 1143 sc->bge_unit); 1144 return(ENXIO); 1145 } 1146 1147 /* Enable flow-through queues */ 1148 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1149 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1150 1151 /* Wait until queue initialization is complete */ 1152 for (i = 0; i < BGE_TIMEOUT; i++) { 1153 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1154 break; 1155 DELAY(10); 1156 } 1157 1158 if (i == BGE_TIMEOUT) { 1159 printf("bge%d: flow-through queue init failed\n", 1160 sc->bge_unit); 1161 return(ENXIO); 1162 } 1163 1164 /* Initialize the standard RX ring control block */ 1165 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1166 BGE_HOSTADDR(rcb->bge_hostaddr) = 1167 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1168 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1169 if (sc->bge_extram) 1170 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1171 else 1172 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1173 rcb->bge_flags = 0; 1174 rcbo = (struct bge_rcb_opaque *)rcb; 1175 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1176 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1177 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1178 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1179 1180 /* 1181 * Initialize the jumbo RX ring control block 1182 * We set the 'ring disabled' bit in the flags 1183 * field until we're actually ready to start 1184 * using this ring (i.e. once we set the MTU 1185 * high enough to require it). 1186 */ 1187 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1188 BGE_HOSTADDR(rcb->bge_hostaddr) = 1189 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1190 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1191 if (sc->bge_extram) 1192 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1193 else 1194 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1195 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1196 1197 rcbo = (struct bge_rcb_opaque *)rcb; 1198 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1199 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1200 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1201 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1202 1203 /* Set up dummy disabled mini ring RCB */ 1204 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1205 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1206 rcbo = (struct bge_rcb_opaque *)rcb; 1207 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1208 1209 /* 1210 * Set the BD ring replentish thresholds. The recommended 1211 * values are 1/8th the number of descriptors allocated to 1212 * each ring. 1213 */ 1214 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1215 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1216 1217 /* 1218 * Disable all unused send rings by setting the 'ring disabled' 1219 * bit in the flags field of all the TX send ring control blocks. 1220 * These are located in NIC memory. 1221 */ 1222 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1223 BGE_SEND_RING_RCB); 1224 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1225 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1226 rcb->bge_max_len = 0; 1227 rcb->bge_nicaddr = 0; 1228 rcb++; 1229 } 1230 1231 /* Configure TX RCB 0 (we use only the first ring) */ 1232 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1233 BGE_SEND_RING_RCB); 1234 rcb->bge_hostaddr.bge_addr_hi = 0; 1235 BGE_HOSTADDR(rcb->bge_hostaddr) = 1236 vtophys(&sc->bge_rdata->bge_tx_ring); 1237 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1238 rcb->bge_max_len = BGE_TX_RING_CNT; 1239 rcb->bge_flags = 0; 1240 1241 /* Disable all unused RX return rings */ 1242 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1243 BGE_RX_RETURN_RING_RCB); 1244 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1245 rcb->bge_hostaddr.bge_addr_hi = 0; 1246 rcb->bge_hostaddr.bge_addr_lo = 0; 1247 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1248 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1249 rcb->bge_nicaddr = 0; 1250 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1251 (i * (sizeof(u_int64_t))), 0); 1252 rcb++; 1253 } 1254 1255 /* Initialize RX ring indexes */ 1256 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1257 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1258 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1259 1260 /* 1261 * Set up RX return ring 0 1262 * Note that the NIC address for RX return rings is 0x00000000. 1263 * The return rings live entirely within the host, so the 1264 * nicaddr field in the RCB isn't used. 1265 */ 1266 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1267 BGE_RX_RETURN_RING_RCB); 1268 rcb->bge_hostaddr.bge_addr_hi = 0; 1269 BGE_HOSTADDR(rcb->bge_hostaddr) = 1270 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1271 rcb->bge_nicaddr = 0x00000000; 1272 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1273 rcb->bge_flags = 0; 1274 1275 /* Set random backoff seed for TX */ 1276 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1277 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1278 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1279 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1280 BGE_TX_BACKOFF_SEED_MASK); 1281 1282 /* Set inter-packet gap */ 1283 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1284 1285 /* 1286 * Specify which ring to use for packets that don't match 1287 * any RX rules. 1288 */ 1289 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1290 1291 /* 1292 * Configure number of RX lists. One interrupt distribution 1293 * list, sixteen active lists, one bad frames class. 1294 */ 1295 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1296 1297 /* Inialize RX list placement stats mask. */ 1298 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1299 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1300 1301 /* Disable host coalescing until we get it set up */ 1302 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1303 1304 /* Poll to make sure it's shut down. */ 1305 for (i = 0; i < BGE_TIMEOUT; i++) { 1306 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1307 break; 1308 DELAY(10); 1309 } 1310 1311 if (i == BGE_TIMEOUT) { 1312 printf("bge%d: host coalescing engine failed to idle\n", 1313 sc->bge_unit); 1314 return(ENXIO); 1315 } 1316 1317 /* Set up host coalescing defaults */ 1318 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1319 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1320 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1321 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1322 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1323 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1324 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1325 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1326 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1327 1328 /* Set up address of statistics block */ 1329 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1330 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1331 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1332 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1333 1334 /* Set up address of status block */ 1335 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1336 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1337 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1338 vtophys(&sc->bge_rdata->bge_status_block)); 1339 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1340 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1341 1342 /* Turn on host coalescing state machine */ 1343 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1344 1345 /* Turn on RX BD completion state machine and enable attentions */ 1346 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1347 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1348 1349 /* Turn on RX list placement state machine */ 1350 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1351 1352 /* Turn on RX list selector state machine. */ 1353 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1354 1355 /* Turn on DMA, clear stats */ 1356 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1357 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1358 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1359 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1360 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1361 1362 /* Set misc. local control, enable interrupts on attentions */ 1363 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1364 1365#ifdef notdef 1366 /* Assert GPIO pins for PHY reset */ 1367 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1368 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1369 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1370 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1371#endif 1372 1373 /* Turn on DMA completion state machine */ 1374 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1375 1376 /* Turn on write DMA state machine */ 1377 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1378 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1379 1380 /* Turn on read DMA state machine */ 1381 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1382 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1383 1384 /* Turn on RX data completion state machine */ 1385 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1386 1387 /* Turn on RX BD initiator state machine */ 1388 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1389 1390 /* Turn on RX data and RX BD initiator state machine */ 1391 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1392 1393 /* Turn on Mbuf cluster free state machine */ 1394 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1395 1396 /* Turn on send BD completion state machine */ 1397 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1398 1399 /* Turn on send data completion state machine */ 1400 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1401 1402 /* Turn on send data initiator state machine */ 1403 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1404 1405 /* Turn on send BD initiator state machine */ 1406 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1407 1408 /* Turn on send BD selector state machine */ 1409 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1410 1411 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1412 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1413 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1414 1415 /* init LED register */ 1416 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1417 1418 /* ack/clear link change events */ 1419 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1420 BGE_MACSTAT_CFG_CHANGED); 1421 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1422 1423 /* Enable PHY auto polling (for MII/GMII only) */ 1424 if (sc->bge_tbi) { 1425 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
| 501 if (val & BGE_MICOMM_READFAIL) 502 return(0); 503 504 return(val & 0xFFFF); 505} 506 507static int 508bge_miibus_writereg(dev, phy, reg, val) 509 device_t dev; 510 int phy, reg, val; 511{ 512 struct bge_softc *sc; 513 int i; 514 515 sc = device_get_softc(dev); 516 517 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY| 518 BGE_MIPHY(phy)|BGE_MIREG(reg)|val); 519 520 for (i = 0; i < BGE_TIMEOUT; i++) { 521 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY)) 522 break; 523 } 524 525 if (i == BGE_TIMEOUT) { 526 printf("bge%d: PHY read timed out\n", sc->bge_unit); 527 return(0); 528 } 529 530 return(0); 531} 532 533static void 534bge_miibus_statchg(dev) 535 device_t dev; 536{ 537 struct bge_softc *sc; 538 struct mii_data *mii; 539 540 sc = device_get_softc(dev); 541 mii = device_get_softc(sc->bge_miibus); 542 543 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE); 544 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX) { 545 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII); 546 } else { 547 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII); 548 } 549 550 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 551 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 552 } else { 553 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX); 554 } 555 556 bge_phy_hack(sc); 557 558 return; 559} 560 561/* 562 * Handle events that have triggered interrupts. 563 */ 564static void 565bge_handle_events(sc) 566 struct bge_softc *sc; 567{ 568 569 return; 570} 571 572/* 573 * Memory management for jumbo frames. 574 */ 575 576static int 577bge_alloc_jumbo_mem(sc) 578 struct bge_softc *sc; 579{ 580 caddr_t ptr; 581 register int i; 582 struct bge_jpool_entry *entry; 583 584 /* Grab a big chunk o' storage. */ 585 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF, 586 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 587 588 if (sc->bge_cdata.bge_jumbo_buf == NULL) { 589 printf("bge%d: no memory for jumbo buffers!\n", sc->bge_unit); 590 return(ENOBUFS); 591 } 592 593 SLIST_INIT(&sc->bge_jfree_listhead); 594 SLIST_INIT(&sc->bge_jinuse_listhead); 595 596 /* 597 * Now divide it up into 9K pieces and save the addresses 598 * in an array. 599 */ 600 ptr = sc->bge_cdata.bge_jumbo_buf; 601 for (i = 0; i < BGE_JSLOTS; i++) { 602 sc->bge_cdata.bge_jslots[i] = ptr; 603 ptr += BGE_JLEN; 604 entry = malloc(sizeof(struct bge_jpool_entry), 605 M_DEVBUF, M_NOWAIT); 606 if (entry == NULL) { 607 contigfree(sc->bge_cdata.bge_jumbo_buf, 608 BGE_JMEM, M_DEVBUF); 609 sc->bge_cdata.bge_jumbo_buf = NULL; 610 printf("bge%d: no memory for jumbo " 611 "buffer queue!\n", sc->bge_unit); 612 return(ENOBUFS); 613 } 614 entry->slot = i; 615 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, 616 entry, jpool_entries); 617 } 618 619 return(0); 620} 621 622static void 623bge_free_jumbo_mem(sc) 624 struct bge_softc *sc; 625{ 626 int i; 627 struct bge_jpool_entry *entry; 628 629 for (i = 0; i < BGE_JSLOTS; i++) { 630 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 631 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 632 free(entry, M_DEVBUF); 633 } 634 635 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF); 636 637 return; 638} 639 640/* 641 * Allocate a jumbo buffer. 642 */ 643static void * 644bge_jalloc(sc) 645 struct bge_softc *sc; 646{ 647 struct bge_jpool_entry *entry; 648 649 entry = SLIST_FIRST(&sc->bge_jfree_listhead); 650 651 if (entry == NULL) { 652 printf("bge%d: no free jumbo buffers\n", sc->bge_unit); 653 return(NULL); 654 } 655 656 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jpool_entries); 657 SLIST_INSERT_HEAD(&sc->bge_jinuse_listhead, entry, jpool_entries); 658 return(sc->bge_cdata.bge_jslots[entry->slot]); 659} 660 661/* 662 * Release a jumbo buffer. 663 */ 664static void 665bge_jfree(buf, args) 666 caddr_t buf; 667 void *args; 668{ 669 struct bge_jpool_entry *entry; 670 struct bge_softc *sc; 671 int i; 672 673 /* Extract the softc struct pointer. */ 674 sc = (struct bge_softc *)args; 675 676 if (sc == NULL) 677 panic("bge_jfree: can't find softc pointer!"); 678 679 /* calculate the slot this buffer belongs to */ 680 681 i = ((vm_offset_t)buf 682 - (vm_offset_t)sc->bge_cdata.bge_jumbo_buf) / BGE_JLEN; 683 684 if ((i < 0) || (i >= BGE_JSLOTS)) 685 panic("bge_jfree: asked to free buffer that we don't manage!"); 686 687 entry = SLIST_FIRST(&sc->bge_jinuse_listhead); 688 if (entry == NULL) 689 panic("bge_jfree: buffer not in use!"); 690 entry->slot = i; 691 SLIST_REMOVE_HEAD(&sc->bge_jinuse_listhead, jpool_entries); 692 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jpool_entries); 693 694 return; 695} 696 697 698/* 699 * Intialize a standard receive ring descriptor. 700 */ 701static int 702bge_newbuf_std(sc, i, m) 703 struct bge_softc *sc; 704 int i; 705 struct mbuf *m; 706{ 707 struct mbuf *m_new = NULL; 708 struct bge_rx_bd *r; 709 710 if (m == NULL) { 711 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 712 if (m_new == NULL) { 713 return(ENOBUFS); 714 } 715 716 MCLGET(m_new, M_DONTWAIT); 717 if (!(m_new->m_flags & M_EXT)) { 718 m_freem(m_new); 719 return(ENOBUFS); 720 } 721 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 722 } else { 723 m_new = m; 724 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 725 m_new->m_data = m_new->m_ext.ext_buf; 726 } 727 728 m_adj(m_new, ETHER_ALIGN); 729 sc->bge_cdata.bge_rx_std_chain[i] = m_new; 730 r = &sc->bge_rdata->bge_rx_std_ring[i]; 731 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 732 r->bge_flags = BGE_RXBDFLAG_END; 733 r->bge_len = m_new->m_len; 734 r->bge_idx = i; 735 736 return(0); 737} 738 739/* 740 * Initialize a jumbo receive ring descriptor. This allocates 741 * a jumbo buffer from the pool managed internally by the driver. 742 */ 743static int 744bge_newbuf_jumbo(sc, i, m) 745 struct bge_softc *sc; 746 int i; 747 struct mbuf *m; 748{ 749 struct mbuf *m_new = NULL; 750 struct bge_rx_bd *r; 751 752 if (m == NULL) { 753 caddr_t *buf = NULL; 754 755 /* Allocate the mbuf. */ 756 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 757 if (m_new == NULL) { 758 return(ENOBUFS); 759 } 760 761 /* Allocate the jumbo buffer */ 762 buf = bge_jalloc(sc); 763 if (buf == NULL) { 764 m_freem(m_new); 765 printf("bge%d: jumbo allocation failed " 766 "-- packet dropped!\n", sc->bge_unit); 767 return(ENOBUFS); 768 } 769 770 /* Attach the buffer to the mbuf. */ 771 m_new->m_data = (void *) buf; 772 m_new->m_len = m_new->m_pkthdr.len = BGE_JUMBO_FRAMELEN; 773 MEXTADD(m_new, buf, BGE_JUMBO_FRAMELEN, bge_jfree, 774 (struct bge_softc *)sc, 0, EXT_NET_DRV); 775 } else { 776 m_new = m; 777 m_new->m_data = m_new->m_ext.ext_buf; 778 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN; 779 } 780 781 m_adj(m_new, ETHER_ALIGN); 782 /* Set up the descriptor. */ 783 r = &sc->bge_rdata->bge_rx_jumbo_ring[i]; 784 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new; 785 BGE_HOSTADDR(r->bge_addr) = vtophys(mtod(m_new, caddr_t)); 786 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING; 787 r->bge_len = m_new->m_len; 788 r->bge_idx = i; 789 790 return(0); 791} 792 793/* 794 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster, 795 * that's 1MB or memory, which is a lot. For now, we fill only the first 796 * 256 ring entries and hope that our CPU is fast enough to keep up with 797 * the NIC. 798 */ 799static int 800bge_init_rx_ring_std(sc) 801 struct bge_softc *sc; 802{ 803 int i; 804 805 for (i = 0; i < BGE_SSLOTS; i++) { 806 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS) 807 return(ENOBUFS); 808 }; 809 810 sc->bge_std = i - 1; 811 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 812 813 return(0); 814} 815 816static void 817bge_free_rx_ring_std(sc) 818 struct bge_softc *sc; 819{ 820 int i; 821 822 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) { 823 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) { 824 m_freem(sc->bge_cdata.bge_rx_std_chain[i]); 825 sc->bge_cdata.bge_rx_std_chain[i] = NULL; 826 } 827 bzero((char *)&sc->bge_rdata->bge_rx_std_ring[i], 828 sizeof(struct bge_rx_bd)); 829 } 830 831 return; 832} 833 834static int 835bge_init_rx_ring_jumbo(sc) 836 struct bge_softc *sc; 837{ 838 int i; 839 struct bge_rcb *rcb; 840 struct bge_rcb_opaque *rcbo; 841 842 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 843 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS) 844 return(ENOBUFS); 845 }; 846 847 sc->bge_jumbo = i - 1; 848 849 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 850 rcbo = (struct bge_rcb_opaque *)rcb; 851 rcb->bge_flags = 0; 852 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 853 854 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 855 856 return(0); 857} 858 859static void 860bge_free_rx_ring_jumbo(sc) 861 struct bge_softc *sc; 862{ 863 int i; 864 865 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) { 866 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) { 867 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]); 868 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL; 869 } 870 bzero((char *)&sc->bge_rdata->bge_rx_jumbo_ring[i], 871 sizeof(struct bge_rx_bd)); 872 } 873 874 return; 875} 876 877static void 878bge_free_tx_ring(sc) 879 struct bge_softc *sc; 880{ 881 int i; 882 883 if (sc->bge_rdata->bge_tx_ring == NULL) 884 return; 885 886 for (i = 0; i < BGE_TX_RING_CNT; i++) { 887 if (sc->bge_cdata.bge_tx_chain[i] != NULL) { 888 m_freem(sc->bge_cdata.bge_tx_chain[i]); 889 sc->bge_cdata.bge_tx_chain[i] = NULL; 890 } 891 bzero((char *)&sc->bge_rdata->bge_tx_ring[i], 892 sizeof(struct bge_tx_bd)); 893 } 894 895 return; 896} 897 898static int 899bge_init_tx_ring(sc) 900 struct bge_softc *sc; 901{ 902 sc->bge_txcnt = 0; 903 sc->bge_tx_saved_considx = 0; 904 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0); 905 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0); 906 907 return(0); 908} 909 910#define BGE_POLY 0xEDB88320 911 912static u_int32_t 913bge_crc(addr) 914 caddr_t addr; 915{ 916 u_int32_t idx, bit, data, crc; 917 918 /* Compute CRC for the address value. */ 919 crc = 0xFFFFFFFF; /* initial value */ 920 921 for (idx = 0; idx < 6; idx++) { 922 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 923 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? BGE_POLY : 0); 924 } 925 926 return(crc & 0x7F); 927} 928 929static void 930bge_setmulti(sc) 931 struct bge_softc *sc; 932{ 933 struct ifnet *ifp; 934 struct ifmultiaddr *ifma; 935 u_int32_t hashes[4] = { 0, 0, 0, 0 }; 936 int h, i; 937 938 ifp = &sc->arpcom.ac_if; 939 940 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 941 for (i = 0; i < 4; i++) 942 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF); 943 return; 944 } 945 946 /* First, zot all the existing filters. */ 947 for (i = 0; i < 4; i++) 948 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0); 949 950 /* Now program new ones. */ 951 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 952 if (ifma->ifma_addr->sa_family != AF_LINK) 953 continue; 954 h = bge_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 955 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F); 956 } 957 958 for (i = 0; i < 4; i++) 959 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]); 960 961 return; 962} 963 964/* 965 * Do endian, PCI and DMA initialization. Also check the on-board ROM 966 * self-test results. 967 */ 968static int 969bge_chipinit(sc) 970 struct bge_softc *sc; 971{ 972 u_int32_t cachesize; 973 int i; 974 975 /* Set endianness before we access any non-PCI registers. */ 976#if BYTE_ORDER == BIG_ENDIAN 977 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 978 BGE_BIGENDIAN_INIT, 4); 979#else 980 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL, 981 BGE_LITTLEENDIAN_INIT, 4); 982#endif 983 984 /* 985 * Check the 'ROM failed' bit on the RX CPU to see if 986 * self-tests passed. 987 */ 988 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) { 989 printf("bge%d: RX CPU self-diagnostics failed!\n", 990 sc->bge_unit); 991 return(ENODEV); 992 } 993 994 /* Clear the MAC control register */ 995 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 996 997 /* 998 * Clear the MAC statistics block in the NIC's 999 * internal memory. 1000 */ 1001 for (i = BGE_STATS_BLOCK; 1002 i < BGE_STATS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1003 BGE_MEMWIN_WRITE(sc, i, 0); 1004 1005 for (i = BGE_STATUS_BLOCK; 1006 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(u_int32_t)) 1007 BGE_MEMWIN_WRITE(sc, i, 0); 1008 1009 /* Set up the PCI DMA control register. */ 1010 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1011 BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD|0x0F, 4); 1012 1013 /* 1014 * Set up general mode register. 1015 */ 1016 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME| 1017 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA| 1018 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS| 1019 BGE_MODECTL_NO_RX_CRC|BGE_MODECTL_TX_NO_PHDR_CSUM| 1020 BGE_MODECTL_RX_NO_PHDR_CSUM); 1021 1022 /* Get cache line size. */ 1023 cachesize = pci_read_config(sc->bge_dev, BGE_PCI_CACHESZ, 1); 1024 1025 /* 1026 * Avoid violating PCI spec on certain chip revs. 1027 */ 1028 if (pci_read_config(sc->bge_dev, BGE_PCI_CMD, 4) & PCIM_CMD_MWIEN) { 1029 switch(cachesize) { 1030 case 1: 1031 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1032 BGE_PCI_WRITE_BNDRY_16BYTES, 4); 1033 break; 1034 case 2: 1035 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1036 BGE_PCI_WRITE_BNDRY_32BYTES, 4); 1037 break; 1038 case 4: 1039 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1040 BGE_PCI_WRITE_BNDRY_64BYTES, 4); 1041 break; 1042 case 8: 1043 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1044 BGE_PCI_WRITE_BNDRY_128BYTES, 4); 1045 break; 1046 case 16: 1047 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1048 BGE_PCI_WRITE_BNDRY_256BYTES, 4); 1049 break; 1050 case 32: 1051 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1052 BGE_PCI_WRITE_BNDRY_512BYTES, 4); 1053 break; 1054 case 64: 1055 PCI_SETBIT(sc->bge_dev, BGE_PCI_DMA_RW_CTL, 1056 BGE_PCI_WRITE_BNDRY_1024BYTES, 4); 1057 break; 1058 default: 1059 /* Disable PCI memory write and invalidate. */ 1060 if (bootverbose) 1061 printf("bge%d: cache line size %d not " 1062 "supported; disabling PCI MWI\n", 1063 sc->bge_unit, cachesize); 1064 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, 1065 PCIM_CMD_MWIEN, 4); 1066 break; 1067 } 1068 } 1069 1070#ifdef __brokenalpha__ 1071 /* 1072 * Must insure that we do not cross an 8K (bytes) boundary 1073 * for DMA reads. Our highest limit is 1K bytes. This is a 1074 * restriction on some ALPHA platforms with early revision 1075 * 21174 PCI chipsets, such as the AlphaPC 164lx 1076 */ 1077 PCI_SETBIT(sc, BGE_PCI_DMA_RW_CTL, BGE_PCI_READ_BNDRY_1024, 4); 1078#endif 1079 1080 /* Set the timer prescaler (always 66Mhz) */ 1081 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/); 1082 1083 return(0); 1084} 1085 1086static int 1087bge_blockinit(sc) 1088 struct bge_softc *sc; 1089{ 1090 struct bge_rcb *rcb; 1091 struct bge_rcb_opaque *rcbo; 1092 int i; 1093 1094 /* 1095 * Initialize the memory window pointer register so that 1096 * we can access the first 32K of internal NIC RAM. This will 1097 * allow us to set up the TX send ring RCBs and the RX return 1098 * ring RCBs, plus other things which live in NIC memory. 1099 */ 1100 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0); 1101 1102 /* Configure mbuf memory pool */ 1103 if (sc->bge_extram) { 1104 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_EXT_SSRAM); 1105 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1106 } else { 1107 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR, BGE_BUFFPOOL_1); 1108 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000); 1109 } 1110 1111 /* Configure DMA resource pool */ 1112 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR, BGE_DMA_DESCRIPTORS); 1113 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000); 1114 1115 /* Configure mbuf pool watermarks */ 1116 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 24); 1117 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 24); 1118 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 48); 1119 1120 /* Configure DMA resource watermarks */ 1121 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5); 1122 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10); 1123 1124 /* Enable buffer manager */ 1125 CSR_WRITE_4(sc, BGE_BMAN_MODE, 1126 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN); 1127 1128 /* Poll for buffer manager start indication */ 1129 for (i = 0; i < BGE_TIMEOUT; i++) { 1130 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE) 1131 break; 1132 DELAY(10); 1133 } 1134 1135 if (i == BGE_TIMEOUT) { 1136 printf("bge%d: buffer manager failed to start\n", 1137 sc->bge_unit); 1138 return(ENXIO); 1139 } 1140 1141 /* Enable flow-through queues */ 1142 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 1143 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 1144 1145 /* Wait until queue initialization is complete */ 1146 for (i = 0; i < BGE_TIMEOUT; i++) { 1147 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0) 1148 break; 1149 DELAY(10); 1150 } 1151 1152 if (i == BGE_TIMEOUT) { 1153 printf("bge%d: flow-through queue init failed\n", 1154 sc->bge_unit); 1155 return(ENXIO); 1156 } 1157 1158 /* Initialize the standard RX ring control block */ 1159 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb; 1160 BGE_HOSTADDR(rcb->bge_hostaddr) = 1161 vtophys(&sc->bge_rdata->bge_rx_std_ring); 1162 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1163 if (sc->bge_extram) 1164 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS; 1165 else 1166 rcb->bge_nicaddr = BGE_STD_RX_RINGS; 1167 rcb->bge_flags = 0; 1168 rcbo = (struct bge_rcb_opaque *)rcb; 1169 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcbo->bge_reg0); 1170 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcbo->bge_reg1); 1171 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1172 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcbo->bge_reg3); 1173 1174 /* 1175 * Initialize the jumbo RX ring control block 1176 * We set the 'ring disabled' bit in the flags 1177 * field until we're actually ready to start 1178 * using this ring (i.e. once we set the MTU 1179 * high enough to require it). 1180 */ 1181 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb; 1182 BGE_HOSTADDR(rcb->bge_hostaddr) = 1183 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring); 1184 rcb->bge_max_len = BGE_MAX_FRAMELEN; 1185 if (sc->bge_extram) 1186 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS; 1187 else 1188 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS; 1189 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1190 1191 rcbo = (struct bge_rcb_opaque *)rcb; 1192 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI, rcbo->bge_reg0); 1193 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO, rcbo->bge_reg1); 1194 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1195 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcbo->bge_reg3); 1196 1197 /* Set up dummy disabled mini ring RCB */ 1198 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb; 1199 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1200 rcbo = (struct bge_rcb_opaque *)rcb; 1201 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS, rcbo->bge_reg2); 1202 1203 /* 1204 * Set the BD ring replentish thresholds. The recommended 1205 * values are 1/8th the number of descriptors allocated to 1206 * each ring. 1207 */ 1208 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8); 1209 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8); 1210 1211 /* 1212 * Disable all unused send rings by setting the 'ring disabled' 1213 * bit in the flags field of all the TX send ring control blocks. 1214 * These are located in NIC memory. 1215 */ 1216 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1217 BGE_SEND_RING_RCB); 1218 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) { 1219 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1220 rcb->bge_max_len = 0; 1221 rcb->bge_nicaddr = 0; 1222 rcb++; 1223 } 1224 1225 /* Configure TX RCB 0 (we use only the first ring) */ 1226 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1227 BGE_SEND_RING_RCB); 1228 rcb->bge_hostaddr.bge_addr_hi = 0; 1229 BGE_HOSTADDR(rcb->bge_hostaddr) = 1230 vtophys(&sc->bge_rdata->bge_tx_ring); 1231 rcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT); 1232 rcb->bge_max_len = BGE_TX_RING_CNT; 1233 rcb->bge_flags = 0; 1234 1235 /* Disable all unused RX return rings */ 1236 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1237 BGE_RX_RETURN_RING_RCB); 1238 for (i = 0; i < BGE_RX_RINGS_MAX; i++) { 1239 rcb->bge_hostaddr.bge_addr_hi = 0; 1240 rcb->bge_hostaddr.bge_addr_lo = 0; 1241 rcb->bge_flags = BGE_RCB_FLAG_RING_DISABLED; 1242 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1243 rcb->bge_nicaddr = 0; 1244 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO + 1245 (i * (sizeof(u_int64_t))), 0); 1246 rcb++; 1247 } 1248 1249 /* Initialize RX ring indexes */ 1250 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0); 1251 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0); 1252 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0); 1253 1254 /* 1255 * Set up RX return ring 0 1256 * Note that the NIC address for RX return rings is 0x00000000. 1257 * The return rings live entirely within the host, so the 1258 * nicaddr field in the RCB isn't used. 1259 */ 1260 rcb = (struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START + 1261 BGE_RX_RETURN_RING_RCB); 1262 rcb->bge_hostaddr.bge_addr_hi = 0; 1263 BGE_HOSTADDR(rcb->bge_hostaddr) = 1264 vtophys(&sc->bge_rdata->bge_rx_return_ring); 1265 rcb->bge_nicaddr = 0x00000000; 1266 rcb->bge_max_len = BGE_RETURN_RING_CNT; 1267 rcb->bge_flags = 0; 1268 1269 /* Set random backoff seed for TX */ 1270 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF, 1271 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] + 1272 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] + 1273 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] + 1274 BGE_TX_BACKOFF_SEED_MASK); 1275 1276 /* Set inter-packet gap */ 1277 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620); 1278 1279 /* 1280 * Specify which ring to use for packets that don't match 1281 * any RX rules. 1282 */ 1283 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08); 1284 1285 /* 1286 * Configure number of RX lists. One interrupt distribution 1287 * list, sixteen active lists, one bad frames class. 1288 */ 1289 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181); 1290 1291 /* Inialize RX list placement stats mask. */ 1292 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF); 1293 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1); 1294 1295 /* Disable host coalescing until we get it set up */ 1296 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000); 1297 1298 /* Poll to make sure it's shut down. */ 1299 for (i = 0; i < BGE_TIMEOUT; i++) { 1300 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE)) 1301 break; 1302 DELAY(10); 1303 } 1304 1305 if (i == BGE_TIMEOUT) { 1306 printf("bge%d: host coalescing engine failed to idle\n", 1307 sc->bge_unit); 1308 return(ENXIO); 1309 } 1310 1311 /* Set up host coalescing defaults */ 1312 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks); 1313 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks); 1314 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds); 1315 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds); 1316 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0); 1317 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0); 1318 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0); 1319 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0); 1320 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks); 1321 1322 /* Set up address of statistics block */ 1323 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK); 1324 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0); 1325 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO, 1326 vtophys(&sc->bge_rdata->bge_info.bge_stats)); 1327 1328 /* Set up address of status block */ 1329 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK); 1330 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0); 1331 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO, 1332 vtophys(&sc->bge_rdata->bge_status_block)); 1333 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0; 1334 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0; 1335 1336 /* Turn on host coalescing state machine */ 1337 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 1338 1339 /* Turn on RX BD completion state machine and enable attentions */ 1340 CSR_WRITE_4(sc, BGE_RBDC_MODE, 1341 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN); 1342 1343 /* Turn on RX list placement state machine */ 1344 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 1345 1346 /* Turn on RX list selector state machine. */ 1347 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 1348 1349 /* Turn on DMA, clear stats */ 1350 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB| 1351 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR| 1352 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB| 1353 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB| 1354 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII)); 1355 1356 /* Set misc. local control, enable interrupts on attentions */ 1357 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN); 1358 1359#ifdef notdef 1360 /* Assert GPIO pins for PHY reset */ 1361 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0| 1362 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2); 1363 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0| 1364 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2); 1365#endif 1366 1367 /* Turn on DMA completion state machine */ 1368 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 1369 1370 /* Turn on write DMA state machine */ 1371 CSR_WRITE_4(sc, BGE_WDMA_MODE, 1372 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS); 1373 1374 /* Turn on read DMA state machine */ 1375 CSR_WRITE_4(sc, BGE_RDMA_MODE, 1376 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS); 1377 1378 /* Turn on RX data completion state machine */ 1379 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 1380 1381 /* Turn on RX BD initiator state machine */ 1382 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 1383 1384 /* Turn on RX data and RX BD initiator state machine */ 1385 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE); 1386 1387 /* Turn on Mbuf cluster free state machine */ 1388 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 1389 1390 /* Turn on send BD completion state machine */ 1391 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 1392 1393 /* Turn on send data completion state machine */ 1394 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 1395 1396 /* Turn on send data initiator state machine */ 1397 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 1398 1399 /* Turn on send BD initiator state machine */ 1400 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 1401 1402 /* Turn on send BD selector state machine */ 1403 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 1404 1405 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF); 1406 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL, 1407 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER); 1408 1409 /* init LED register */ 1410 CSR_WRITE_4(sc, BGE_MAC_LED_CTL, 0x00000000); 1411 1412 /* ack/clear link change events */ 1413 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 1414 BGE_MACSTAT_CFG_CHANGED); 1415 CSR_WRITE_4(sc, BGE_MI_STS, 0); 1416 1417 /* Enable PHY auto polling (for MII/GMII only) */ 1418 if (sc->bge_tbi) { 1419 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
|
1426 } else
| 1420 } else {
|
1427 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
| 1421 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
|
| 1422 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) 1423 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 1424 BGE_EVTENB_MI_INTERRUPT); 1425 }
|
1428 1429 /* Enable link state change attentions. */ 1430 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1431 1432 return(0); 1433} 1434 1435/* 1436 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1437 * against our list and return its name if we find a match. Note 1438 * that since the Broadcom controller contains VPD support, we 1439 * can get the device name string from the controller itself instead 1440 * of the compiled-in string. This is a little slow, but it guarantees 1441 * we'll always announce the right product name. 1442 */ 1443static int 1444bge_probe(dev) 1445 device_t dev; 1446{ 1447 struct bge_type *t; 1448 struct bge_softc *sc; 1449 1450 t = bge_devs; 1451 1452 sc = device_get_softc(dev); 1453 bzero(sc, sizeof(struct bge_softc)); 1454 sc->bge_unit = device_get_unit(dev); 1455 sc->bge_dev = dev; 1456 1457 while(t->bge_name != NULL) { 1458 if ((pci_get_vendor(dev) == t->bge_vid) && 1459 (pci_get_device(dev) == t->bge_did)) { 1460#ifdef notdef 1461 bge_vpd_read(sc); 1462 device_set_desc(dev, sc->bge_vpd_prodname); 1463#endif 1464 device_set_desc(dev, t->bge_name); 1465 return(0); 1466 } 1467 t++; 1468 } 1469 1470 return(ENXIO); 1471} 1472 1473static int 1474bge_attach(dev) 1475 device_t dev; 1476{ 1477 int s; 1478 u_int32_t command; 1479 struct ifnet *ifp; 1480 struct bge_softc *sc;
| 1426 1427 /* Enable link state change attentions. */ 1428 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED); 1429 1430 return(0); 1431} 1432 1433/* 1434 * Probe for a Broadcom chip. Check the PCI vendor and device IDs 1435 * against our list and return its name if we find a match. Note 1436 * that since the Broadcom controller contains VPD support, we 1437 * can get the device name string from the controller itself instead 1438 * of the compiled-in string. This is a little slow, but it guarantees 1439 * we'll always announce the right product name. 1440 */ 1441static int 1442bge_probe(dev) 1443 device_t dev; 1444{ 1445 struct bge_type *t; 1446 struct bge_softc *sc; 1447 1448 t = bge_devs; 1449 1450 sc = device_get_softc(dev); 1451 bzero(sc, sizeof(struct bge_softc)); 1452 sc->bge_unit = device_get_unit(dev); 1453 sc->bge_dev = dev; 1454 1455 while(t->bge_name != NULL) { 1456 if ((pci_get_vendor(dev) == t->bge_vid) && 1457 (pci_get_device(dev) == t->bge_did)) { 1458#ifdef notdef 1459 bge_vpd_read(sc); 1460 device_set_desc(dev, sc->bge_vpd_prodname); 1461#endif 1462 device_set_desc(dev, t->bge_name); 1463 return(0); 1464 } 1465 t++; 1466 } 1467 1468 return(ENXIO); 1469} 1470 1471static int 1472bge_attach(dev) 1473 device_t dev; 1474{ 1475 int s; 1476 u_int32_t command; 1477 struct ifnet *ifp; 1478 struct bge_softc *sc;
|
| 1479 u_int32_t hwcfg = 0;
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1481 int unit, error = 0, rid; 1482 1483 s = splimp(); 1484 1485 sc = device_get_softc(dev); 1486 unit = device_get_unit(dev); 1487 sc->bge_dev = dev; 1488 sc->bge_unit = unit; 1489 1490 /* 1491 * Map control/status registers. 1492 */ 1493 pci_enable_busmaster(dev); 1494 pci_enable_io(dev, SYS_RES_MEMORY); 1495 command = pci_read_config(dev, PCIR_COMMAND, 4); 1496 1497 if (!(command & PCIM_CMD_MEMEN)) { 1498 printf("bge%d: failed to enable memory mapping!\n", unit); 1499 error = ENXIO; 1500 goto fail; 1501 } 1502 1503 rid = BGE_PCI_BAR0; 1504 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1505 0, ~0, 1, RF_ACTIVE); 1506 1507 if (sc->bge_res == NULL) { 1508 printf ("bge%d: couldn't map memory\n", unit); 1509 error = ENXIO; 1510 goto fail; 1511 } 1512 1513 sc->bge_btag = rman_get_bustag(sc->bge_res); 1514 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1515 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1516 1517 /* 1518 * XXX FIXME: rman_get_virtual() on the alpha is currently 1519 * broken and returns a physical address instead of a kernel 1520 * virtual address. Consequently, we need to do a little 1521 * extra mangling of the vhandle on the alpha. This should 1522 * eventually be fixed! The whole idea here is to get rid 1523 * of platform dependencies. 1524 */ 1525#ifdef __alpha__ 1526 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1527 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1528 else 1529 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1530 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1531#endif 1532 1533 /* Allocate interrupt */ 1534 rid = 0; 1535 1536 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1537 RF_SHAREABLE | RF_ACTIVE); 1538 1539 if (sc->bge_irq == NULL) { 1540 printf("bge%d: couldn't map interrupt\n", unit); 1541 error = ENXIO; 1542 goto fail; 1543 } 1544 1545 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1546 bge_intr, sc, &sc->bge_intrhand); 1547 1548 if (error) { 1549 bge_release_resources(sc); 1550 printf("bge%d: couldn't set up irq\n", unit); 1551 goto fail; 1552 } 1553 1554 sc->bge_unit = unit; 1555 1556 /* Try to reset the chip. */ 1557 bge_reset(sc); 1558 1559 if (bge_chipinit(sc)) { 1560 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1561 bge_release_resources(sc); 1562 error = ENXIO; 1563 goto fail; 1564 } 1565 1566 /* 1567 * Get station address from the EEPROM. 1568 */ 1569 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1570 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1571 printf("bge%d: failed to read station address\n", unit); 1572 bge_release_resources(sc); 1573 error = ENXIO; 1574 goto fail; 1575 } 1576 1577 /* 1578 * A Broadcom chip was detected. Inform the world. 1579 */ 1580 printf("bge%d: Ethernet address: %6D\n", unit, 1581 sc->arpcom.ac_enaddr, ":"); 1582 1583 /* Allocate the general information block and ring buffers. */ 1584 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1585 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1586 1587 if (sc->bge_rdata == NULL) { 1588 bge_release_resources(sc); 1589 error = ENXIO; 1590 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1591 goto fail; 1592 } 1593 1594 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1595 1596 /* Try to allocate memory for jumbo buffers. */ 1597 if (bge_alloc_jumbo_mem(sc)) { 1598 printf("bge%d: jumbo buffer allocation " 1599 "failed\n", sc->bge_unit); 1600 bge_release_resources(sc); 1601 error = ENXIO; 1602 goto fail; 1603 } 1604 1605 /* Set default tuneable values. */ 1606 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1607 sc->bge_rx_coal_ticks = 150; 1608 sc->bge_tx_coal_ticks = 150; 1609 sc->bge_rx_max_coal_bds = 64; 1610 sc->bge_tx_max_coal_bds = 128; 1611 1612 /* Set up ifnet structure */ 1613 ifp = &sc->arpcom.ac_if; 1614 ifp->if_softc = sc; 1615 ifp->if_unit = sc->bge_unit; 1616 ifp->if_name = "bge"; 1617 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1618 ifp->if_ioctl = bge_ioctl; 1619 ifp->if_output = ether_output; 1620 ifp->if_start = bge_start; 1621 ifp->if_watchdog = bge_watchdog; 1622 ifp->if_init = bge_init; 1623 ifp->if_mtu = ETHERMTU; 1624 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1625 ifp->if_hwassist = BGE_CSUM_FEATURES; 1626 ifp->if_capabilities = IFCAP_HWCSUM; 1627 ifp->if_capenable = ifp->if_capabilities; 1628 1629 /* Save ASIC rev. */ 1630 1631 sc->bge_asicrev = 1632 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1633 BGE_PCIMISCCTL_ASICREV; 1634
| 1480 int unit, error = 0, rid; 1481 1482 s = splimp(); 1483 1484 sc = device_get_softc(dev); 1485 unit = device_get_unit(dev); 1486 sc->bge_dev = dev; 1487 sc->bge_unit = unit; 1488 1489 /* 1490 * Map control/status registers. 1491 */ 1492 pci_enable_busmaster(dev); 1493 pci_enable_io(dev, SYS_RES_MEMORY); 1494 command = pci_read_config(dev, PCIR_COMMAND, 4); 1495 1496 if (!(command & PCIM_CMD_MEMEN)) { 1497 printf("bge%d: failed to enable memory mapping!\n", unit); 1498 error = ENXIO; 1499 goto fail; 1500 } 1501 1502 rid = BGE_PCI_BAR0; 1503 sc->bge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 1504 0, ~0, 1, RF_ACTIVE); 1505 1506 if (sc->bge_res == NULL) { 1507 printf ("bge%d: couldn't map memory\n", unit); 1508 error = ENXIO; 1509 goto fail; 1510 } 1511 1512 sc->bge_btag = rman_get_bustag(sc->bge_res); 1513 sc->bge_bhandle = rman_get_bushandle(sc->bge_res); 1514 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res); 1515 1516 /* 1517 * XXX FIXME: rman_get_virtual() on the alpha is currently 1518 * broken and returns a physical address instead of a kernel 1519 * virtual address. Consequently, we need to do a little 1520 * extra mangling of the vhandle on the alpha. This should 1521 * eventually be fixed! The whole idea here is to get rid 1522 * of platform dependencies. 1523 */ 1524#ifdef __alpha__ 1525 if (pci_cvt_to_bwx(sc->bge_vhandle)) 1526 sc->bge_vhandle = pci_cvt_to_bwx(sc->bge_vhandle); 1527 else 1528 sc->bge_vhandle = pci_cvt_to_dense(sc->bge_vhandle); 1529 sc->bge_vhandle = ALPHA_PHYS_TO_K0SEG(sc->bge_vhandle); 1530#endif 1531 1532 /* Allocate interrupt */ 1533 rid = 0; 1534 1535 sc->bge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 1536 RF_SHAREABLE | RF_ACTIVE); 1537 1538 if (sc->bge_irq == NULL) { 1539 printf("bge%d: couldn't map interrupt\n", unit); 1540 error = ENXIO; 1541 goto fail; 1542 } 1543 1544 error = bus_setup_intr(dev, sc->bge_irq, INTR_TYPE_NET, 1545 bge_intr, sc, &sc->bge_intrhand); 1546 1547 if (error) { 1548 bge_release_resources(sc); 1549 printf("bge%d: couldn't set up irq\n", unit); 1550 goto fail; 1551 } 1552 1553 sc->bge_unit = unit; 1554 1555 /* Try to reset the chip. */ 1556 bge_reset(sc); 1557 1558 if (bge_chipinit(sc)) { 1559 printf("bge%d: chip initialization failed\n", sc->bge_unit); 1560 bge_release_resources(sc); 1561 error = ENXIO; 1562 goto fail; 1563 } 1564 1565 /* 1566 * Get station address from the EEPROM. 1567 */ 1568 if (bge_read_eeprom(sc, (caddr_t)&sc->arpcom.ac_enaddr, 1569 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) { 1570 printf("bge%d: failed to read station address\n", unit); 1571 bge_release_resources(sc); 1572 error = ENXIO; 1573 goto fail; 1574 } 1575 1576 /* 1577 * A Broadcom chip was detected. Inform the world. 1578 */ 1579 printf("bge%d: Ethernet address: %6D\n", unit, 1580 sc->arpcom.ac_enaddr, ":"); 1581 1582 /* Allocate the general information block and ring buffers. */ 1583 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF, 1584 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 1585 1586 if (sc->bge_rdata == NULL) { 1587 bge_release_resources(sc); 1588 error = ENXIO; 1589 printf("bge%d: no memory for list buffers!\n", sc->bge_unit); 1590 goto fail; 1591 } 1592 1593 bzero(sc->bge_rdata, sizeof(struct bge_ring_data)); 1594 1595 /* Try to allocate memory for jumbo buffers. */ 1596 if (bge_alloc_jumbo_mem(sc)) { 1597 printf("bge%d: jumbo buffer allocation " 1598 "failed\n", sc->bge_unit); 1599 bge_release_resources(sc); 1600 error = ENXIO; 1601 goto fail; 1602 } 1603 1604 /* Set default tuneable values. */ 1605 sc->bge_stat_ticks = BGE_TICKS_PER_SEC; 1606 sc->bge_rx_coal_ticks = 150; 1607 sc->bge_tx_coal_ticks = 150; 1608 sc->bge_rx_max_coal_bds = 64; 1609 sc->bge_tx_max_coal_bds = 128; 1610 1611 /* Set up ifnet structure */ 1612 ifp = &sc->arpcom.ac_if; 1613 ifp->if_softc = sc; 1614 ifp->if_unit = sc->bge_unit; 1615 ifp->if_name = "bge"; 1616 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1617 ifp->if_ioctl = bge_ioctl; 1618 ifp->if_output = ether_output; 1619 ifp->if_start = bge_start; 1620 ifp->if_watchdog = bge_watchdog; 1621 ifp->if_init = bge_init; 1622 ifp->if_mtu = ETHERMTU; 1623 ifp->if_snd.ifq_maxlen = BGE_TX_RING_CNT - 1; 1624 ifp->if_hwassist = BGE_CSUM_FEATURES; 1625 ifp->if_capabilities = IFCAP_HWCSUM; 1626 ifp->if_capenable = ifp->if_capabilities; 1627 1628 /* Save ASIC rev. */ 1629 1630 sc->bge_asicrev = 1631 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) & 1632 BGE_PCIMISCCTL_ASICREV; 1633
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| 1634 /* Pretend all 5700s are the same */ 1635 if ((sc->bge_asicrev & 0xFF000000) == BGE_ASICREV_BCM5700) 1636 sc->bge_asicrev = BGE_ASICREV_BCM5700; 1637 1638 /* 1639 * Figure out what sort of media we have by checking the 1640 * hardware config word in the EEPROM. Note: on some BCM5700 1641 * cards, this value appears to be unset. If that's the 1642 * case, we have to rely on identifying the NIC by its PCI 1643 * subsystem ID, as we do below for the SysKonnect SK-9D41. 1644 */ 1645 bge_read_eeprom(sc, (caddr_t)&hwcfg, 1646 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg)); 1647 if ((ntohl(hwcfg) & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER) 1648 sc->bge_tbi = 1; 1649
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1635 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1636 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1637 sc->bge_tbi = 1; 1638 1639 if (sc->bge_tbi) { 1640 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1641 bge_ifmedia_upd, bge_ifmedia_sts); 1642 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1643 ifmedia_add(&sc->bge_ifmedia, 1644 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1645 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1646 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1647 } else { 1648 /* 1649 * Do transceiver setup. 1650 */ 1651 if (mii_phy_probe(dev, &sc->bge_miibus, 1652 bge_ifmedia_upd, bge_ifmedia_sts)) { 1653 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1654 bge_release_resources(sc); 1655 bge_free_jumbo_mem(sc); 1656 error = ENXIO; 1657 goto fail; 1658 } 1659 } 1660 1661 /* 1662 * Call MI attach routine. 1663 */ 1664 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1665 callout_handle_init(&sc->bge_stat_ch); 1666 1667fail: 1668 splx(s); 1669 1670 return(error); 1671} 1672 1673static int 1674bge_detach(dev) 1675 device_t dev; 1676{ 1677 struct bge_softc *sc; 1678 struct ifnet *ifp; 1679 int s; 1680 1681 s = splimp(); 1682 1683 sc = device_get_softc(dev); 1684 ifp = &sc->arpcom.ac_if; 1685 1686 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1687 bge_stop(sc); 1688 bge_reset(sc); 1689 1690 if (sc->bge_tbi) { 1691 ifmedia_removeall(&sc->bge_ifmedia); 1692 } else { 1693 bus_generic_detach(dev); 1694 device_delete_child(dev, sc->bge_miibus); 1695 } 1696 1697 bge_release_resources(sc); 1698 bge_free_jumbo_mem(sc); 1699 1700 splx(s); 1701 1702 return(0); 1703} 1704 1705static void 1706bge_release_resources(sc) 1707 struct bge_softc *sc; 1708{ 1709 device_t dev; 1710 1711 dev = sc->bge_dev; 1712 1713 if (sc->bge_vpd_prodname != NULL) 1714 free(sc->bge_vpd_prodname, M_DEVBUF); 1715 1716 if (sc->bge_vpd_readonly != NULL) 1717 free(sc->bge_vpd_readonly, M_DEVBUF); 1718 1719 if (sc->bge_intrhand != NULL) 1720 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1721 1722 if (sc->bge_irq != NULL) 1723 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1724 1725 if (sc->bge_res != NULL) 1726 bus_release_resource(dev, SYS_RES_MEMORY, 1727 BGE_PCI_BAR0, sc->bge_res); 1728 1729 if (sc->bge_rdata != NULL) 1730 contigfree(sc->bge_rdata, 1731 sizeof(struct bge_ring_data), M_DEVBUF); 1732 1733 return; 1734} 1735 1736static void 1737bge_reset(sc) 1738 struct bge_softc *sc; 1739{ 1740 device_t dev; 1741 u_int32_t cachesize, command, pcistate; 1742 int i, val = 0; 1743 1744 dev = sc->bge_dev; 1745 1746 /* Save some important PCI state. */ 1747 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1748 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1749 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1750 1751 pci_write_config(dev, BGE_PCI_MISC_CTL, 1752 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1753 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1754 1755 /* Issue global reset */ 1756 bge_writereg_ind(sc, BGE_MISC_CFG, 1757 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1758 1759 DELAY(1000); 1760 1761 /* Reset some of the PCI state that got zapped by reset */ 1762 pci_write_config(dev, BGE_PCI_MISC_CTL, 1763 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1764 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1765 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1766 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1767 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1768 1769 /* 1770 * Prevent PXE restart: write a magic number to the 1771 * general communications memory at 0xB50. 1772 */ 1773 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1774 /* 1775 * Poll the value location we just wrote until 1776 * we see the 1's complement of the magic number. 1777 * This indicates that the firmware initialization 1778 * is complete. 1779 */ 1780 for (i = 0; i < BGE_TIMEOUT; i++) { 1781 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1782 if (val == ~BGE_MAGIC_NUMBER) 1783 break; 1784 DELAY(10); 1785 } 1786 1787 if (i == BGE_TIMEOUT) { 1788 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1789 return; 1790 } 1791 1792 /* 1793 * XXX Wait for the value of the PCISTATE register to 1794 * return to its original pre-reset state. This is a 1795 * fairly good indicator of reset completion. If we don't 1796 * wait for the reset to fully complete, trying to read 1797 * from the device's non-PCI registers may yield garbage 1798 * results. 1799 */ 1800 for (i = 0; i < BGE_TIMEOUT; i++) { 1801 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1802 break; 1803 DELAY(10); 1804 } 1805 1806 /* Enable memory arbiter. */ 1807 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1808 1809 /* Fix up byte swapping */ 1810 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1811 BGE_MODECTL_BYTESWAP_DATA); 1812 1813 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1814 1815 DELAY(10000); 1816 1817 return; 1818} 1819 1820/* 1821 * Frame reception handling. This is called if there's a frame 1822 * on the receive return list. 1823 * 1824 * Note: we have to be able to handle two possibilities here: 1825 * 1) the frame is from the jumbo recieve ring 1826 * 2) the frame is from the standard receive ring 1827 */ 1828 1829static void 1830bge_rxeof(sc) 1831 struct bge_softc *sc; 1832{ 1833 struct ifnet *ifp; 1834 int stdcnt = 0, jumbocnt = 0; 1835 1836 ifp = &sc->arpcom.ac_if; 1837 1838 while(sc->bge_rx_saved_considx != 1839 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1840 struct bge_rx_bd *cur_rx; 1841 u_int32_t rxidx; 1842 struct ether_header *eh; 1843 struct mbuf *m = NULL; 1844 u_int16_t vlan_tag = 0; 1845 int have_tag = 0; 1846 1847 cur_rx = 1848 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1849 1850 rxidx = cur_rx->bge_idx; 1851 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1852 1853 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1854 have_tag = 1; 1855 vlan_tag = cur_rx->bge_vlan_tag; 1856 } 1857 1858 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1859 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1860 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1861 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1862 jumbocnt++; 1863 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1864 ifp->if_ierrors++; 1865 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1866 continue; 1867 } 1868 if (bge_newbuf_jumbo(sc, 1869 sc->bge_jumbo, NULL) == ENOBUFS) { 1870 ifp->if_ierrors++; 1871 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1872 continue; 1873 } 1874 } else { 1875 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1876 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1877 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1878 stdcnt++; 1879 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1880 ifp->if_ierrors++; 1881 bge_newbuf_std(sc, sc->bge_std, m); 1882 continue; 1883 } 1884 if (bge_newbuf_std(sc, sc->bge_std, 1885 NULL) == ENOBUFS) { 1886 ifp->if_ierrors++; 1887 bge_newbuf_std(sc, sc->bge_std, m); 1888 continue; 1889 } 1890 } 1891 1892 ifp->if_ipackets++; 1893 eh = mtod(m, struct ether_header *); 1894 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1895 m->m_pkthdr.rcvif = ifp; 1896 1897 /* Remove header from mbuf and pass it on. */ 1898 m_adj(m, sizeof(struct ether_header)); 1899 1900#if 0 /* currently broken for some packets, possibly related to TCP options */ 1901 if (ifp->if_hwassist) { 1902 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1903 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1904 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1905 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1906 m->m_pkthdr.csum_data = 1907 cur_rx->bge_tcp_udp_csum; 1908 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1909 } 1910 } 1911#endif 1912 1913 /* 1914 * If we received a packet with a vlan tag, pass it 1915 * to vlan_input() instead of ether_input(). 1916 */ 1917 if (have_tag) { 1918 VLAN_INPUT_TAG(eh, m, vlan_tag); 1919 have_tag = vlan_tag = 0; 1920 continue; 1921 } 1922 1923 ether_input(ifp, eh, m); 1924 } 1925 1926 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1927 if (stdcnt) 1928 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1929 if (jumbocnt) 1930 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1931 1932 return; 1933} 1934 1935static void 1936bge_txeof(sc) 1937 struct bge_softc *sc; 1938{ 1939 struct bge_tx_bd *cur_tx = NULL; 1940 struct ifnet *ifp; 1941 1942 ifp = &sc->arpcom.ac_if; 1943 1944 /* 1945 * Go through our tx ring and free mbufs for those 1946 * frames that have been sent. 1947 */ 1948 while (sc->bge_tx_saved_considx != 1949 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1950 u_int32_t idx = 0; 1951 1952 idx = sc->bge_tx_saved_considx; 1953 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1954 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1955 ifp->if_opackets++; 1956 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1957 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1958 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1959 } 1960 sc->bge_txcnt--; 1961 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1962 ifp->if_timer = 0; 1963 } 1964 1965 if (cur_tx != NULL) 1966 ifp->if_flags &= ~IFF_OACTIVE; 1967 1968 return; 1969} 1970 1971static void 1972bge_intr(xsc) 1973 void *xsc; 1974{ 1975 struct bge_softc *sc; 1976 struct ifnet *ifp; 1977 1978 sc = xsc; 1979 ifp = &sc->arpcom.ac_if; 1980 1981#ifdef notdef 1982 /* Avoid this for now -- checking this register is expensive. */ 1983 /* Make sure this is really our interrupt. */ 1984 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 1985 return; 1986#endif 1987 /* Ack interrupt and stop others from occuring. */ 1988 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 1989
| 1650 /* The SysKonnect SK-9D41 is a 1000baseSX card. */ 1651 if ((pci_read_config(dev, BGE_PCI_SUBSYS, 4) >> 16) == SK_SUBSYSID_9D41) 1652 sc->bge_tbi = 1; 1653 1654 if (sc->bge_tbi) { 1655 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK, 1656 bge_ifmedia_upd, bge_ifmedia_sts); 1657 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL); 1658 ifmedia_add(&sc->bge_ifmedia, 1659 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL); 1660 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL); 1661 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO); 1662 } else { 1663 /* 1664 * Do transceiver setup. 1665 */ 1666 if (mii_phy_probe(dev, &sc->bge_miibus, 1667 bge_ifmedia_upd, bge_ifmedia_sts)) { 1668 printf("bge%d: MII without any PHY!\n", sc->bge_unit); 1669 bge_release_resources(sc); 1670 bge_free_jumbo_mem(sc); 1671 error = ENXIO; 1672 goto fail; 1673 } 1674 } 1675 1676 /* 1677 * Call MI attach routine. 1678 */ 1679 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 1680 callout_handle_init(&sc->bge_stat_ch); 1681 1682fail: 1683 splx(s); 1684 1685 return(error); 1686} 1687 1688static int 1689bge_detach(dev) 1690 device_t dev; 1691{ 1692 struct bge_softc *sc; 1693 struct ifnet *ifp; 1694 int s; 1695 1696 s = splimp(); 1697 1698 sc = device_get_softc(dev); 1699 ifp = &sc->arpcom.ac_if; 1700 1701 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 1702 bge_stop(sc); 1703 bge_reset(sc); 1704 1705 if (sc->bge_tbi) { 1706 ifmedia_removeall(&sc->bge_ifmedia); 1707 } else { 1708 bus_generic_detach(dev); 1709 device_delete_child(dev, sc->bge_miibus); 1710 } 1711 1712 bge_release_resources(sc); 1713 bge_free_jumbo_mem(sc); 1714 1715 splx(s); 1716 1717 return(0); 1718} 1719 1720static void 1721bge_release_resources(sc) 1722 struct bge_softc *sc; 1723{ 1724 device_t dev; 1725 1726 dev = sc->bge_dev; 1727 1728 if (sc->bge_vpd_prodname != NULL) 1729 free(sc->bge_vpd_prodname, M_DEVBUF); 1730 1731 if (sc->bge_vpd_readonly != NULL) 1732 free(sc->bge_vpd_readonly, M_DEVBUF); 1733 1734 if (sc->bge_intrhand != NULL) 1735 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand); 1736 1737 if (sc->bge_irq != NULL) 1738 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq); 1739 1740 if (sc->bge_res != NULL) 1741 bus_release_resource(dev, SYS_RES_MEMORY, 1742 BGE_PCI_BAR0, sc->bge_res); 1743 1744 if (sc->bge_rdata != NULL) 1745 contigfree(sc->bge_rdata, 1746 sizeof(struct bge_ring_data), M_DEVBUF); 1747 1748 return; 1749} 1750 1751static void 1752bge_reset(sc) 1753 struct bge_softc *sc; 1754{ 1755 device_t dev; 1756 u_int32_t cachesize, command, pcistate; 1757 int i, val = 0; 1758 1759 dev = sc->bge_dev; 1760 1761 /* Save some important PCI state. */ 1762 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4); 1763 command = pci_read_config(dev, BGE_PCI_CMD, 4); 1764 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4); 1765 1766 pci_write_config(dev, BGE_PCI_MISC_CTL, 1767 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1768 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1769 1770 /* Issue global reset */ 1771 bge_writereg_ind(sc, BGE_MISC_CFG, 1772 BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1)); 1773 1774 DELAY(1000); 1775 1776 /* Reset some of the PCI state that got zapped by reset */ 1777 pci_write_config(dev, BGE_PCI_MISC_CTL, 1778 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR| 1779 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4); 1780 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4); 1781 pci_write_config(dev, BGE_PCI_CMD, command, 4); 1782 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1)); 1783 1784 /* 1785 * Prevent PXE restart: write a magic number to the 1786 * general communications memory at 0xB50. 1787 */ 1788 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER); 1789 /* 1790 * Poll the value location we just wrote until 1791 * we see the 1's complement of the magic number. 1792 * This indicates that the firmware initialization 1793 * is complete. 1794 */ 1795 for (i = 0; i < BGE_TIMEOUT; i++) { 1796 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM); 1797 if (val == ~BGE_MAGIC_NUMBER) 1798 break; 1799 DELAY(10); 1800 } 1801 1802 if (i == BGE_TIMEOUT) { 1803 printf("bge%d: firmware handshake timed out\n", sc->bge_unit); 1804 return; 1805 } 1806 1807 /* 1808 * XXX Wait for the value of the PCISTATE register to 1809 * return to its original pre-reset state. This is a 1810 * fairly good indicator of reset completion. If we don't 1811 * wait for the reset to fully complete, trying to read 1812 * from the device's non-PCI registers may yield garbage 1813 * results. 1814 */ 1815 for (i = 0; i < BGE_TIMEOUT; i++) { 1816 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate) 1817 break; 1818 DELAY(10); 1819 } 1820 1821 /* Enable memory arbiter. */ 1822 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 1823 1824 /* Fix up byte swapping */ 1825 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME| 1826 BGE_MODECTL_BYTESWAP_DATA); 1827 1828 CSR_WRITE_4(sc, BGE_MAC_MODE, 0); 1829 1830 DELAY(10000); 1831 1832 return; 1833} 1834 1835/* 1836 * Frame reception handling. This is called if there's a frame 1837 * on the receive return list. 1838 * 1839 * Note: we have to be able to handle two possibilities here: 1840 * 1) the frame is from the jumbo recieve ring 1841 * 2) the frame is from the standard receive ring 1842 */ 1843 1844static void 1845bge_rxeof(sc) 1846 struct bge_softc *sc; 1847{ 1848 struct ifnet *ifp; 1849 int stdcnt = 0, jumbocnt = 0; 1850 1851 ifp = &sc->arpcom.ac_if; 1852 1853 while(sc->bge_rx_saved_considx != 1854 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) { 1855 struct bge_rx_bd *cur_rx; 1856 u_int32_t rxidx; 1857 struct ether_header *eh; 1858 struct mbuf *m = NULL; 1859 u_int16_t vlan_tag = 0; 1860 int have_tag = 0; 1861 1862 cur_rx = 1863 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx]; 1864 1865 rxidx = cur_rx->bge_idx; 1866 BGE_INC(sc->bge_rx_saved_considx, BGE_RETURN_RING_CNT); 1867 1868 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) { 1869 have_tag = 1; 1870 vlan_tag = cur_rx->bge_vlan_tag; 1871 } 1872 1873 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) { 1874 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT); 1875 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx]; 1876 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL; 1877 jumbocnt++; 1878 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1879 ifp->if_ierrors++; 1880 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1881 continue; 1882 } 1883 if (bge_newbuf_jumbo(sc, 1884 sc->bge_jumbo, NULL) == ENOBUFS) { 1885 ifp->if_ierrors++; 1886 bge_newbuf_jumbo(sc, sc->bge_jumbo, m); 1887 continue; 1888 } 1889 } else { 1890 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT); 1891 m = sc->bge_cdata.bge_rx_std_chain[rxidx]; 1892 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL; 1893 stdcnt++; 1894 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) { 1895 ifp->if_ierrors++; 1896 bge_newbuf_std(sc, sc->bge_std, m); 1897 continue; 1898 } 1899 if (bge_newbuf_std(sc, sc->bge_std, 1900 NULL) == ENOBUFS) { 1901 ifp->if_ierrors++; 1902 bge_newbuf_std(sc, sc->bge_std, m); 1903 continue; 1904 } 1905 } 1906 1907 ifp->if_ipackets++; 1908 eh = mtod(m, struct ether_header *); 1909 m->m_pkthdr.len = m->m_len = cur_rx->bge_len; 1910 m->m_pkthdr.rcvif = ifp; 1911 1912 /* Remove header from mbuf and pass it on. */ 1913 m_adj(m, sizeof(struct ether_header)); 1914 1915#if 0 /* currently broken for some packets, possibly related to TCP options */ 1916 if (ifp->if_hwassist) { 1917 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1918 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0) 1919 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1920 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) { 1921 m->m_pkthdr.csum_data = 1922 cur_rx->bge_tcp_udp_csum; 1923 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 1924 } 1925 } 1926#endif 1927 1928 /* 1929 * If we received a packet with a vlan tag, pass it 1930 * to vlan_input() instead of ether_input(). 1931 */ 1932 if (have_tag) { 1933 VLAN_INPUT_TAG(eh, m, vlan_tag); 1934 have_tag = vlan_tag = 0; 1935 continue; 1936 } 1937 1938 ether_input(ifp, eh, m); 1939 } 1940 1941 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx); 1942 if (stdcnt) 1943 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std); 1944 if (jumbocnt) 1945 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo); 1946 1947 return; 1948} 1949 1950static void 1951bge_txeof(sc) 1952 struct bge_softc *sc; 1953{ 1954 struct bge_tx_bd *cur_tx = NULL; 1955 struct ifnet *ifp; 1956 1957 ifp = &sc->arpcom.ac_if; 1958 1959 /* 1960 * Go through our tx ring and free mbufs for those 1961 * frames that have been sent. 1962 */ 1963 while (sc->bge_tx_saved_considx != 1964 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) { 1965 u_int32_t idx = 0; 1966 1967 idx = sc->bge_tx_saved_considx; 1968 cur_tx = &sc->bge_rdata->bge_tx_ring[idx]; 1969 if (cur_tx->bge_flags & BGE_TXBDFLAG_END) 1970 ifp->if_opackets++; 1971 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) { 1972 m_freem(sc->bge_cdata.bge_tx_chain[idx]); 1973 sc->bge_cdata.bge_tx_chain[idx] = NULL; 1974 } 1975 sc->bge_txcnt--; 1976 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT); 1977 ifp->if_timer = 0; 1978 } 1979 1980 if (cur_tx != NULL) 1981 ifp->if_flags &= ~IFF_OACTIVE; 1982 1983 return; 1984} 1985 1986static void 1987bge_intr(xsc) 1988 void *xsc; 1989{ 1990 struct bge_softc *sc; 1991 struct ifnet *ifp; 1992 1993 sc = xsc; 1994 ifp = &sc->arpcom.ac_if; 1995 1996#ifdef notdef 1997 /* Avoid this for now -- checking this register is expensive. */ 1998 /* Make sure this is really our interrupt. */ 1999 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE)) 2000 return; 2001#endif 2002 /* Ack interrupt and stop others from occuring. */ 2003 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2004
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1990 /* Process link state changes. */ 1991 if (sc->bge_rdata->bge_status_block.bge_status & 1992 BGE_STATFLAG_LINKSTATE_CHANGED) { 1993 if (sc->bge_asicrev != BGE_ASICREV_BCM5701_B5) {
| 2005 /* 2006 * Process link state changes. 2007 * Grrr. The link status word in the status block does 2008 * not work correctly on the BCM5700 rev AX and BX chips, 2009 * according to all avaibable information. Hence, we have 2010 * to enable MII interrupts in order to properly obtain 2011 * async link changes. Unfortunately, this also means that 2012 * we have to read the MAC status register to detect link 2013 * changes, thereby adding an additional register access to 2014 * the interrupt handler. 2015 */ 2016 2017 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) { 2018 u_int32_t status; 2019 2020 status = CSR_READ_4(sc, BGE_MAC_STS); 2021 if (status & BGE_MACSTAT_MI_INTERRUPT) {
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1994 sc->bge_link = 0; 1995 untimeout(bge_tick, sc, sc->bge_stat_ch); 1996 bge_tick(sc);
| 2022 sc->bge_link = 0; 2023 untimeout(bge_tick, sc, sc->bge_stat_ch); 2024 bge_tick(sc);
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| 2025 /* Clear the interrupt */ 2026 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB, 2027 BGE_EVTENB_MI_INTERRUPT); 2028 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR); 2029 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR, 2030 BRGPHY_INTRS);
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1997 }
| 2031 }
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1998 /* ack the event to clear/reset it */ 1999 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2000 BGE_MACSTAT_CFG_CHANGED); 2001 CSR_WRITE_4(sc, BGE_MI_STS, 0);
| 2032 } else { 2033 if (sc->bge_rdata->bge_status_block.bge_status & 2034 BGE_STATFLAG_LINKSTATE_CHANGED) { 2035 sc->bge_link = 0; 2036 untimeout(bge_tick, sc, sc->bge_stat_ch); 2037 bge_tick(sc); 2038 /* Clear the interrupt */ 2039 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED| 2040 BGE_MACSTAT_CFG_CHANGED); 2041 }
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2002 } 2003 2004 if (ifp->if_flags & IFF_RUNNING) { 2005 /* Check RX return ring producer/consumer */ 2006 bge_rxeof(sc); 2007 2008 /* Check TX ring producer/consumer */ 2009 bge_txeof(sc); 2010 } 2011 2012 bge_handle_events(sc); 2013 2014 /* Re-enable interrupts. */ 2015 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2016 2017 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2018 bge_start(ifp); 2019 2020 return; 2021} 2022 2023static void 2024bge_tick(xsc) 2025 void *xsc; 2026{ 2027 struct bge_softc *sc; 2028 struct mii_data *mii = NULL; 2029 struct ifmedia *ifm = NULL; 2030 struct ifnet *ifp; 2031 int s; 2032 2033 sc = xsc; 2034 ifp = &sc->arpcom.ac_if; 2035 2036 s = splimp(); 2037 2038 bge_stats_update(sc); 2039 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2040 if (sc->bge_link) 2041 return; 2042 2043 if (sc->bge_tbi) { 2044 ifm = &sc->bge_ifmedia; 2045 if (CSR_READ_4(sc, BGE_MAC_STS) & 2046 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2047 sc->bge_link++; 2048 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2049 printf("bge%d: gigabit link up\n", sc->bge_unit); 2050 if (ifp->if_snd.ifq_head != NULL) 2051 bge_start(ifp); 2052 } 2053 return; 2054 } 2055 2056 mii = device_get_softc(sc->bge_miibus); 2057 mii_tick(mii); 2058 2059 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2060 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2061 sc->bge_link++; 2062 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2063 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2064 printf("bge%d: gigabit link up\n", 2065 sc->bge_unit); 2066 if (ifp->if_snd.ifq_head != NULL) 2067 bge_start(ifp); 2068 } 2069 2070 splx(s); 2071 2072 return; 2073} 2074 2075static void 2076bge_stats_update(sc) 2077 struct bge_softc *sc; 2078{ 2079 struct ifnet *ifp; 2080 struct bge_stats *stats; 2081 2082 ifp = &sc->arpcom.ac_if; 2083 2084 stats = (struct bge_stats *)(sc->bge_vhandle + 2085 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2086 2087 ifp->if_collisions += 2088 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2089 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2090 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2091 stats->dot3StatsLateCollisions.bge_addr_lo) - 2092 ifp->if_collisions; 2093 2094#ifdef notdef 2095 ifp->if_collisions += 2096 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2097 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2098 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2099 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2100 ifp->if_collisions; 2101#endif 2102 2103 return; 2104} 2105 2106/* 2107 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2108 * pointers to descriptors. 2109 */ 2110static int 2111bge_encap(sc, m_head, txidx) 2112 struct bge_softc *sc; 2113 struct mbuf *m_head; 2114 u_int32_t *txidx; 2115{ 2116 struct bge_tx_bd *f = NULL; 2117 struct mbuf *m; 2118 u_int32_t frag, cur, cnt = 0; 2119 u_int16_t csum_flags = 0; 2120 struct ifvlan *ifv = NULL; 2121 2122 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2123 m_head->m_pkthdr.rcvif != NULL && 2124 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2125 ifv = m_head->m_pkthdr.rcvif->if_softc; 2126 2127 m = m_head; 2128 cur = frag = *txidx; 2129 2130 if (m_head->m_pkthdr.csum_flags) { 2131 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2132 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2133 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2134 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2135 if (m_head->m_flags & M_LASTFRAG) 2136 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2137 else if (m_head->m_flags & M_FRAG) 2138 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2139 } 2140 2141 /* 2142 * Start packing the mbufs in this chain into 2143 * the fragment pointers. Stop when we run out 2144 * of fragments or hit the end of the mbuf chain. 2145 */ 2146 for (m = m_head; m != NULL; m = m->m_next) { 2147 if (m->m_len != 0) { 2148 f = &sc->bge_rdata->bge_tx_ring[frag]; 2149 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2150 break; 2151 BGE_HOSTADDR(f->bge_addr) = 2152 vtophys(mtod(m, vm_offset_t)); 2153 f->bge_len = m->m_len; 2154 f->bge_flags = csum_flags; 2155 if (ifv != NULL) { 2156 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2157 f->bge_vlan_tag = ifv->ifv_tag; 2158 } else { 2159 f->bge_vlan_tag = 0; 2160 } 2161 /* 2162 * Sanity check: avoid coming within 16 descriptors 2163 * of the end of the ring. 2164 */ 2165 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2166 return(ENOBUFS); 2167 cur = frag; 2168 BGE_INC(frag, BGE_TX_RING_CNT); 2169 cnt++; 2170 } 2171 } 2172 2173 if (m != NULL) 2174 return(ENOBUFS); 2175 2176 if (frag == sc->bge_tx_saved_considx) 2177 return(ENOBUFS); 2178 2179 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2180 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2181 sc->bge_txcnt += cnt; 2182 2183 *txidx = frag; 2184 2185 return(0); 2186} 2187 2188/* 2189 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2190 * to the mbuf data regions directly in the transmit descriptors. 2191 */ 2192static void 2193bge_start(ifp) 2194 struct ifnet *ifp; 2195{ 2196 struct bge_softc *sc; 2197 struct mbuf *m_head = NULL; 2198 u_int32_t prodidx = 0; 2199 2200 sc = ifp->if_softc; 2201 2202 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2203 return; 2204 2205 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2206 2207 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2208 IF_DEQUEUE(&ifp->if_snd, m_head); 2209 if (m_head == NULL) 2210 break; 2211 2212 /* 2213 * XXX 2214 * safety overkill. If this is a fragmented packet chain 2215 * with delayed TCP/UDP checksums, then only encapsulate 2216 * it if we have enough descriptors to handle the entire 2217 * chain at once. 2218 * (paranoia -- may not actually be needed) 2219 */ 2220 if (m_head->m_flags & M_FIRSTFRAG && 2221 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2222 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2223 m_head->m_pkthdr.csum_data + 16) { 2224 IF_PREPEND(&ifp->if_snd, m_head); 2225 ifp->if_flags |= IFF_OACTIVE; 2226 break; 2227 } 2228 } 2229 2230 /* 2231 * Pack the data into the transmit ring. If we 2232 * don't have room, set the OACTIVE flag and wait 2233 * for the NIC to drain the ring. 2234 */ 2235 if (bge_encap(sc, m_head, &prodidx)) { 2236 IF_PREPEND(&ifp->if_snd, m_head); 2237 ifp->if_flags |= IFF_OACTIVE; 2238 break; 2239 } 2240 2241 /* 2242 * If there's a BPF listener, bounce a copy of this frame 2243 * to him. 2244 */ 2245 if (ifp->if_bpf) 2246 bpf_mtap(ifp, m_head); 2247 } 2248 2249 /* Transmit */ 2250 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2251 2252 /* 2253 * Set a timeout in case the chip goes out to lunch. 2254 */ 2255 ifp->if_timer = 5; 2256 2257 return; 2258} 2259 2260/* 2261 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2262 * program its internal DSP. Failing to do this can result in 2263 * massive packet loss at 1Gb speeds. 2264 */ 2265static void 2266bge_phy_hack(sc) 2267 struct bge_softc *sc; 2268{ 2269 struct bge_bcom_hack bhack[] = { 2270 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2271 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2272 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2273 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2274 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2275 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2276 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2277 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2278 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2279 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2280 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2281 { 0, 0 } }; 2282 u_int16_t vid, did; 2283 int i; 2284 2285 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2286 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2287 2288 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2289 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2290 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2291 i = 0; 2292 while(bhack[i].reg) { 2293 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2294 bhack[i].val); 2295 i++; 2296 } 2297 } 2298 2299 return; 2300} 2301 2302static void 2303bge_init(xsc) 2304 void *xsc; 2305{ 2306 struct bge_softc *sc = xsc; 2307 struct ifnet *ifp; 2308 u_int16_t *m; 2309 int s; 2310 2311 s = splimp(); 2312 2313 ifp = &sc->arpcom.ac_if; 2314 2315 if (ifp->if_flags & IFF_RUNNING) 2316 return; 2317 2318 /* Cancel pending I/O and flush buffers. */ 2319 bge_stop(sc); 2320 bge_reset(sc); 2321 bge_chipinit(sc); 2322 2323 /* 2324 * Init the various state machines, ring 2325 * control blocks and firmware. 2326 */ 2327 if (bge_blockinit(sc)) { 2328 printf("bge%d: initialization failure\n", sc->bge_unit); 2329 splx(s); 2330 return; 2331 } 2332 2333 ifp = &sc->arpcom.ac_if; 2334 2335 /* Specify MTU. */ 2336 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2337 ETHER_HDR_LEN + ETHER_CRC_LEN); 2338 2339 /* Load our MAC address. */ 2340 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2341 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2342 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2343 2344 /* Enable or disable promiscuous mode as needed. */ 2345 if (ifp->if_flags & IFF_PROMISC) { 2346 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2347 } else { 2348 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2349 } 2350 2351 /* Program multicast filter. */ 2352 bge_setmulti(sc); 2353 2354 /* Init RX ring. */ 2355 bge_init_rx_ring_std(sc); 2356 2357 /* Init jumbo RX ring. */ 2358 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2359 bge_init_rx_ring_jumbo(sc); 2360 2361 /* Init our RX return ring index */ 2362 sc->bge_rx_saved_considx = 0; 2363 2364 /* Init TX ring. */ 2365 bge_init_tx_ring(sc); 2366 2367 /* Turn on transmitter */ 2368 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2369 2370 /* Turn on receiver */ 2371 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2372 2373 /* Tell firmware we're alive. */ 2374 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2375 2376 /* Enable host interrupts. */ 2377 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2378 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2379 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2380 2381 bge_ifmedia_upd(ifp); 2382 2383 ifp->if_flags |= IFF_RUNNING; 2384 ifp->if_flags &= ~IFF_OACTIVE; 2385 2386 splx(s); 2387 2388 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2389 2390 return; 2391} 2392 2393/* 2394 * Set media options. 2395 */ 2396static int 2397bge_ifmedia_upd(ifp) 2398 struct ifnet *ifp; 2399{ 2400 struct bge_softc *sc; 2401 struct mii_data *mii; 2402 struct ifmedia *ifm; 2403 2404 sc = ifp->if_softc; 2405 ifm = &sc->bge_ifmedia; 2406 2407 /* If this is a 1000baseX NIC, enable the TBI port. */ 2408 if (sc->bge_tbi) { 2409 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2410 return(EINVAL); 2411 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2412 case IFM_AUTO: 2413 break; 2414 case IFM_1000_SX: 2415 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2416 BGE_CLRBIT(sc, BGE_MAC_MODE, 2417 BGE_MACMODE_HALF_DUPLEX); 2418 } else { 2419 BGE_SETBIT(sc, BGE_MAC_MODE, 2420 BGE_MACMODE_HALF_DUPLEX); 2421 } 2422 break; 2423 default: 2424 return(EINVAL); 2425 } 2426 return(0); 2427 } 2428 2429 mii = device_get_softc(sc->bge_miibus); 2430 sc->bge_link = 0; 2431 if (mii->mii_instance) { 2432 struct mii_softc *miisc; 2433 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2434 miisc = LIST_NEXT(miisc, mii_list)) 2435 mii_phy_reset(miisc); 2436 } 2437 bge_phy_hack(sc); 2438 mii_mediachg(mii); 2439 2440 return(0); 2441} 2442 2443/* 2444 * Report current media status. 2445 */ 2446static void 2447bge_ifmedia_sts(ifp, ifmr) 2448 struct ifnet *ifp; 2449 struct ifmediareq *ifmr; 2450{ 2451 struct bge_softc *sc; 2452 struct mii_data *mii; 2453 2454 sc = ifp->if_softc; 2455 2456 if (sc->bge_tbi) { 2457 ifmr->ifm_status = IFM_AVALID; 2458 ifmr->ifm_active = IFM_ETHER; 2459 if (CSR_READ_4(sc, BGE_MAC_STS) & 2460 BGE_MACSTAT_TBI_PCS_SYNCHED) 2461 ifmr->ifm_status |= IFM_ACTIVE; 2462 ifmr->ifm_active |= IFM_1000_SX; 2463 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2464 ifmr->ifm_active |= IFM_HDX; 2465 else 2466 ifmr->ifm_active |= IFM_FDX; 2467 return; 2468 } 2469 2470 mii = device_get_softc(sc->bge_miibus); 2471 mii_pollstat(mii); 2472 ifmr->ifm_active = mii->mii_media_active; 2473 ifmr->ifm_status = mii->mii_media_status; 2474 2475 return; 2476} 2477 2478static int 2479bge_ioctl(ifp, command, data) 2480 struct ifnet *ifp; 2481 u_long command; 2482 caddr_t data; 2483{ 2484 struct bge_softc *sc = ifp->if_softc; 2485 struct ifreq *ifr = (struct ifreq *) data; 2486 int s, mask, error = 0; 2487 struct mii_data *mii; 2488 2489 s = splimp(); 2490 2491 switch(command) { 2492 case SIOCSIFADDR: 2493 case SIOCGIFADDR: 2494 error = ether_ioctl(ifp, command, data); 2495 break; 2496 case SIOCSIFMTU: 2497 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2498 error = EINVAL; 2499 else { 2500 ifp->if_mtu = ifr->ifr_mtu; 2501 ifp->if_flags &= ~IFF_RUNNING; 2502 bge_init(sc); 2503 } 2504 break; 2505 case SIOCSIFFLAGS: 2506 if (ifp->if_flags & IFF_UP) { 2507 /* 2508 * If only the state of the PROMISC flag changed, 2509 * then just use the 'set promisc mode' command 2510 * instead of reinitializing the entire NIC. Doing 2511 * a full re-init means reloading the firmware and 2512 * waiting for it to start up, which may take a 2513 * second or two. 2514 */ 2515 if (ifp->if_flags & IFF_RUNNING && 2516 ifp->if_flags & IFF_PROMISC && 2517 !(sc->bge_if_flags & IFF_PROMISC)) { 2518 BGE_SETBIT(sc, BGE_RX_MODE, 2519 BGE_RXMODE_RX_PROMISC); 2520 } else if (ifp->if_flags & IFF_RUNNING && 2521 !(ifp->if_flags & IFF_PROMISC) && 2522 sc->bge_if_flags & IFF_PROMISC) { 2523 BGE_CLRBIT(sc, BGE_RX_MODE, 2524 BGE_RXMODE_RX_PROMISC); 2525 } else 2526 bge_init(sc); 2527 } else { 2528 if (ifp->if_flags & IFF_RUNNING) { 2529 bge_stop(sc); 2530 } 2531 } 2532 sc->bge_if_flags = ifp->if_flags; 2533 error = 0; 2534 break; 2535 case SIOCADDMULTI: 2536 case SIOCDELMULTI: 2537 if (ifp->if_flags & IFF_RUNNING) { 2538 bge_setmulti(sc); 2539 error = 0; 2540 } 2541 break; 2542 case SIOCSIFMEDIA: 2543 case SIOCGIFMEDIA: 2544 if (sc->bge_tbi) { 2545 error = ifmedia_ioctl(ifp, ifr, 2546 &sc->bge_ifmedia, command); 2547 } else { 2548 mii = device_get_softc(sc->bge_miibus); 2549 error = ifmedia_ioctl(ifp, ifr, 2550 &mii->mii_media, command); 2551 } 2552 break; 2553 case SIOCSIFCAP: 2554 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2555 if (mask & IFCAP_HWCSUM) { 2556 if (IFCAP_HWCSUM & ifp->if_capenable) 2557 ifp->if_capenable &= ~IFCAP_HWCSUM; 2558 else 2559 ifp->if_capenable |= IFCAP_HWCSUM; 2560 } 2561 error = 0; 2562 break; 2563 default: 2564 error = EINVAL; 2565 break; 2566 } 2567 2568 (void)splx(s); 2569 2570 return(error); 2571} 2572 2573static void 2574bge_watchdog(ifp) 2575 struct ifnet *ifp; 2576{ 2577 struct bge_softc *sc; 2578 2579 sc = ifp->if_softc; 2580 2581 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2582 2583 ifp->if_flags &= ~IFF_RUNNING; 2584 bge_init(sc); 2585 2586 ifp->if_oerrors++; 2587 2588 return; 2589} 2590 2591/* 2592 * Stop the adapter and free any mbufs allocated to the 2593 * RX and TX lists. 2594 */ 2595static void 2596bge_stop(sc) 2597 struct bge_softc *sc; 2598{ 2599 struct ifnet *ifp; 2600 struct ifmedia_entry *ifm; 2601 struct mii_data *mii = NULL; 2602 int mtmp, itmp; 2603 2604 ifp = &sc->arpcom.ac_if; 2605 2606 if (!sc->bge_tbi) 2607 mii = device_get_softc(sc->bge_miibus); 2608 2609 untimeout(bge_tick, sc, sc->bge_stat_ch); 2610 2611 /* 2612 * Disable all of the receiver blocks 2613 */ 2614 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2615 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2616 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2617 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2618 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2619 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2620 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2621 2622 /* 2623 * Disable all of the transmit blocks 2624 */ 2625 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2626 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2627 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2628 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2629 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2630 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2631 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2632 2633 /* 2634 * Shut down all of the memory managers and related 2635 * state machines. 2636 */ 2637 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2638 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2639 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2640 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2641 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2642 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2643 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2644 2645 /* Disable host interrupts. */ 2646 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2647 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2648 2649 /* 2650 * Tell firmware we're shutting down. 2651 */ 2652 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2653 2654 /* Free the RX lists. */ 2655 bge_free_rx_ring_std(sc); 2656 2657 /* Free jumbo RX list. */ 2658 bge_free_rx_ring_jumbo(sc); 2659 2660 /* Free TX buffers. */ 2661 bge_free_tx_ring(sc); 2662 2663 /* 2664 * Isolate/power down the PHY, but leave the media selection 2665 * unchanged so that things will be put back to normal when 2666 * we bring the interface back up. 2667 */ 2668 if (!sc->bge_tbi) { 2669 itmp = ifp->if_flags; 2670 ifp->if_flags |= IFF_UP; 2671 ifm = mii->mii_media.ifm_cur; 2672 mtmp = ifm->ifm_media; 2673 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2674 mii_mediachg(mii); 2675 ifm->ifm_media = mtmp; 2676 ifp->if_flags = itmp; 2677 } 2678 2679 sc->bge_link = 0; 2680 2681 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2682 2683 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2684 2685 return; 2686} 2687 2688/* 2689 * Stop all chip I/O so that the kernel's probe routines don't 2690 * get confused by errant DMAs when rebooting. 2691 */ 2692static void 2693bge_shutdown(dev) 2694 device_t dev; 2695{ 2696 struct bge_softc *sc; 2697 2698 sc = device_get_softc(dev); 2699 2700 bge_stop(sc); 2701 bge_reset(sc); 2702 2703 return; 2704}
| 2042 } 2043 2044 if (ifp->if_flags & IFF_RUNNING) { 2045 /* Check RX return ring producer/consumer */ 2046 bge_rxeof(sc); 2047 2048 /* Check TX ring producer/consumer */ 2049 bge_txeof(sc); 2050 } 2051 2052 bge_handle_events(sc); 2053 2054 /* Re-enable interrupts. */ 2055 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2056 2057 if (ifp->if_flags & IFF_RUNNING && ifp->if_snd.ifq_head != NULL) 2058 bge_start(ifp); 2059 2060 return; 2061} 2062 2063static void 2064bge_tick(xsc) 2065 void *xsc; 2066{ 2067 struct bge_softc *sc; 2068 struct mii_data *mii = NULL; 2069 struct ifmedia *ifm = NULL; 2070 struct ifnet *ifp; 2071 int s; 2072 2073 sc = xsc; 2074 ifp = &sc->arpcom.ac_if; 2075 2076 s = splimp(); 2077 2078 bge_stats_update(sc); 2079 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2080 if (sc->bge_link) 2081 return; 2082 2083 if (sc->bge_tbi) { 2084 ifm = &sc->bge_ifmedia; 2085 if (CSR_READ_4(sc, BGE_MAC_STS) & 2086 BGE_MACSTAT_TBI_PCS_SYNCHED) { 2087 sc->bge_link++; 2088 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF); 2089 printf("bge%d: gigabit link up\n", sc->bge_unit); 2090 if (ifp->if_snd.ifq_head != NULL) 2091 bge_start(ifp); 2092 } 2093 return; 2094 } 2095 2096 mii = device_get_softc(sc->bge_miibus); 2097 mii_tick(mii); 2098 2099 if (!sc->bge_link && mii->mii_media_status & IFM_ACTIVE && 2100 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 2101 sc->bge_link++; 2102 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_TX || 2103 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) 2104 printf("bge%d: gigabit link up\n", 2105 sc->bge_unit); 2106 if (ifp->if_snd.ifq_head != NULL) 2107 bge_start(ifp); 2108 } 2109 2110 splx(s); 2111 2112 return; 2113} 2114 2115static void 2116bge_stats_update(sc) 2117 struct bge_softc *sc; 2118{ 2119 struct ifnet *ifp; 2120 struct bge_stats *stats; 2121 2122 ifp = &sc->arpcom.ac_if; 2123 2124 stats = (struct bge_stats *)(sc->bge_vhandle + 2125 BGE_MEMWIN_START + BGE_STATS_BLOCK); 2126 2127 ifp->if_collisions += 2128 (stats->dot3StatsSingleCollisionFrames.bge_addr_lo + 2129 stats->dot3StatsMultipleCollisionFrames.bge_addr_lo + 2130 stats->dot3StatsExcessiveCollisions.bge_addr_lo + 2131 stats->dot3StatsLateCollisions.bge_addr_lo) - 2132 ifp->if_collisions; 2133 2134#ifdef notdef 2135 ifp->if_collisions += 2136 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames + 2137 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames + 2138 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions + 2139 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) - 2140 ifp->if_collisions; 2141#endif 2142 2143 return; 2144} 2145 2146/* 2147 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data 2148 * pointers to descriptors. 2149 */ 2150static int 2151bge_encap(sc, m_head, txidx) 2152 struct bge_softc *sc; 2153 struct mbuf *m_head; 2154 u_int32_t *txidx; 2155{ 2156 struct bge_tx_bd *f = NULL; 2157 struct mbuf *m; 2158 u_int32_t frag, cur, cnt = 0; 2159 u_int16_t csum_flags = 0; 2160 struct ifvlan *ifv = NULL; 2161 2162 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) && 2163 m_head->m_pkthdr.rcvif != NULL && 2164 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN) 2165 ifv = m_head->m_pkthdr.rcvif->if_softc; 2166 2167 m = m_head; 2168 cur = frag = *txidx; 2169 2170 if (m_head->m_pkthdr.csum_flags) { 2171 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 2172 csum_flags |= BGE_TXBDFLAG_IP_CSUM; 2173 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP)) 2174 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM; 2175 if (m_head->m_flags & M_LASTFRAG) 2176 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END; 2177 else if (m_head->m_flags & M_FRAG) 2178 csum_flags |= BGE_TXBDFLAG_IP_FRAG; 2179 } 2180 2181 /* 2182 * Start packing the mbufs in this chain into 2183 * the fragment pointers. Stop when we run out 2184 * of fragments or hit the end of the mbuf chain. 2185 */ 2186 for (m = m_head; m != NULL; m = m->m_next) { 2187 if (m->m_len != 0) { 2188 f = &sc->bge_rdata->bge_tx_ring[frag]; 2189 if (sc->bge_cdata.bge_tx_chain[frag] != NULL) 2190 break; 2191 BGE_HOSTADDR(f->bge_addr) = 2192 vtophys(mtod(m, vm_offset_t)); 2193 f->bge_len = m->m_len; 2194 f->bge_flags = csum_flags; 2195 if (ifv != NULL) { 2196 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG; 2197 f->bge_vlan_tag = ifv->ifv_tag; 2198 } else { 2199 f->bge_vlan_tag = 0; 2200 } 2201 /* 2202 * Sanity check: avoid coming within 16 descriptors 2203 * of the end of the ring. 2204 */ 2205 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16) 2206 return(ENOBUFS); 2207 cur = frag; 2208 BGE_INC(frag, BGE_TX_RING_CNT); 2209 cnt++; 2210 } 2211 } 2212 2213 if (m != NULL) 2214 return(ENOBUFS); 2215 2216 if (frag == sc->bge_tx_saved_considx) 2217 return(ENOBUFS); 2218 2219 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END; 2220 sc->bge_cdata.bge_tx_chain[cur] = m_head; 2221 sc->bge_txcnt += cnt; 2222 2223 *txidx = frag; 2224 2225 return(0); 2226} 2227 2228/* 2229 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 2230 * to the mbuf data regions directly in the transmit descriptors. 2231 */ 2232static void 2233bge_start(ifp) 2234 struct ifnet *ifp; 2235{ 2236 struct bge_softc *sc; 2237 struct mbuf *m_head = NULL; 2238 u_int32_t prodidx = 0; 2239 2240 sc = ifp->if_softc; 2241 2242 if (!sc->bge_link && ifp->if_snd.ifq_len < 10) 2243 return; 2244 2245 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO); 2246 2247 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) { 2248 IF_DEQUEUE(&ifp->if_snd, m_head); 2249 if (m_head == NULL) 2250 break; 2251 2252 /* 2253 * XXX 2254 * safety overkill. If this is a fragmented packet chain 2255 * with delayed TCP/UDP checksums, then only encapsulate 2256 * it if we have enough descriptors to handle the entire 2257 * chain at once. 2258 * (paranoia -- may not actually be needed) 2259 */ 2260 if (m_head->m_flags & M_FIRSTFRAG && 2261 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) { 2262 if ((BGE_TX_RING_CNT - sc->bge_txcnt) < 2263 m_head->m_pkthdr.csum_data + 16) { 2264 IF_PREPEND(&ifp->if_snd, m_head); 2265 ifp->if_flags |= IFF_OACTIVE; 2266 break; 2267 } 2268 } 2269 2270 /* 2271 * Pack the data into the transmit ring. If we 2272 * don't have room, set the OACTIVE flag and wait 2273 * for the NIC to drain the ring. 2274 */ 2275 if (bge_encap(sc, m_head, &prodidx)) { 2276 IF_PREPEND(&ifp->if_snd, m_head); 2277 ifp->if_flags |= IFF_OACTIVE; 2278 break; 2279 } 2280 2281 /* 2282 * If there's a BPF listener, bounce a copy of this frame 2283 * to him. 2284 */ 2285 if (ifp->if_bpf) 2286 bpf_mtap(ifp, m_head); 2287 } 2288 2289 /* Transmit */ 2290 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx); 2291 2292 /* 2293 * Set a timeout in case the chip goes out to lunch. 2294 */ 2295 ifp->if_timer = 5; 2296 2297 return; 2298} 2299 2300/* 2301 * If we have a BCM5400 or BCM5401 PHY, we need to properly 2302 * program its internal DSP. Failing to do this can result in 2303 * massive packet loss at 1Gb speeds. 2304 */ 2305static void 2306bge_phy_hack(sc) 2307 struct bge_softc *sc; 2308{ 2309 struct bge_bcom_hack bhack[] = { 2310 { BRGPHY_MII_AUXCTL, 0x4C20 }, 2311 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 }, 2312 { BRGPHY_MII_DSP_RW_PORT, 0x1804 }, 2313 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 }, 2314 { BRGPHY_MII_DSP_RW_PORT, 0x1204 }, 2315 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2316 { BRGPHY_MII_DSP_RW_PORT, 0x0132 }, 2317 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 }, 2318 { BRGPHY_MII_DSP_RW_PORT, 0x0232 }, 2319 { BRGPHY_MII_DSP_ADDR_REG, 0x201F }, 2320 { BRGPHY_MII_DSP_RW_PORT, 0x0A20 }, 2321 { 0, 0 } }; 2322 u_int16_t vid, did; 2323 int i; 2324 2325 vid = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR1); 2326 did = bge_miibus_readreg(sc->bge_dev, 1, MII_PHYIDR2); 2327 2328 if (MII_OUI(vid, did) == MII_OUI_xxBROADCOM && 2329 (MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5400 || 2330 MII_MODEL(did) == MII_MODEL_xxBROADCOM_BCM5401)) { 2331 i = 0; 2332 while(bhack[i].reg) { 2333 bge_miibus_writereg(sc->bge_dev, 1, bhack[i].reg, 2334 bhack[i].val); 2335 i++; 2336 } 2337 } 2338 2339 return; 2340} 2341 2342static void 2343bge_init(xsc) 2344 void *xsc; 2345{ 2346 struct bge_softc *sc = xsc; 2347 struct ifnet *ifp; 2348 u_int16_t *m; 2349 int s; 2350 2351 s = splimp(); 2352 2353 ifp = &sc->arpcom.ac_if; 2354 2355 if (ifp->if_flags & IFF_RUNNING) 2356 return; 2357 2358 /* Cancel pending I/O and flush buffers. */ 2359 bge_stop(sc); 2360 bge_reset(sc); 2361 bge_chipinit(sc); 2362 2363 /* 2364 * Init the various state machines, ring 2365 * control blocks and firmware. 2366 */ 2367 if (bge_blockinit(sc)) { 2368 printf("bge%d: initialization failure\n", sc->bge_unit); 2369 splx(s); 2370 return; 2371 } 2372 2373 ifp = &sc->arpcom.ac_if; 2374 2375 /* Specify MTU. */ 2376 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu + 2377 ETHER_HDR_LEN + ETHER_CRC_LEN); 2378 2379 /* Load our MAC address. */ 2380 m = (u_int16_t *)&sc->arpcom.ac_enaddr[0]; 2381 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0])); 2382 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2])); 2383 2384 /* Enable or disable promiscuous mode as needed. */ 2385 if (ifp->if_flags & IFF_PROMISC) { 2386 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2387 } else { 2388 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC); 2389 } 2390 2391 /* Program multicast filter. */ 2392 bge_setmulti(sc); 2393 2394 /* Init RX ring. */ 2395 bge_init_rx_ring_std(sc); 2396 2397 /* Init jumbo RX ring. */ 2398 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN)) 2399 bge_init_rx_ring_jumbo(sc); 2400 2401 /* Init our RX return ring index */ 2402 sc->bge_rx_saved_considx = 0; 2403 2404 /* Init TX ring. */ 2405 bge_init_tx_ring(sc); 2406 2407 /* Turn on transmitter */ 2408 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE); 2409 2410 /* Turn on receiver */ 2411 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2412 2413 /* Tell firmware we're alive. */ 2414 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2415 2416 /* Enable host interrupts. */ 2417 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA); 2418 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2419 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0); 2420 2421 bge_ifmedia_upd(ifp); 2422 2423 ifp->if_flags |= IFF_RUNNING; 2424 ifp->if_flags &= ~IFF_OACTIVE; 2425 2426 splx(s); 2427 2428 sc->bge_stat_ch = timeout(bge_tick, sc, hz); 2429 2430 return; 2431} 2432 2433/* 2434 * Set media options. 2435 */ 2436static int 2437bge_ifmedia_upd(ifp) 2438 struct ifnet *ifp; 2439{ 2440 struct bge_softc *sc; 2441 struct mii_data *mii; 2442 struct ifmedia *ifm; 2443 2444 sc = ifp->if_softc; 2445 ifm = &sc->bge_ifmedia; 2446 2447 /* If this is a 1000baseX NIC, enable the TBI port. */ 2448 if (sc->bge_tbi) { 2449 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2450 return(EINVAL); 2451 switch(IFM_SUBTYPE(ifm->ifm_media)) { 2452 case IFM_AUTO: 2453 break; 2454 case IFM_1000_SX: 2455 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) { 2456 BGE_CLRBIT(sc, BGE_MAC_MODE, 2457 BGE_MACMODE_HALF_DUPLEX); 2458 } else { 2459 BGE_SETBIT(sc, BGE_MAC_MODE, 2460 BGE_MACMODE_HALF_DUPLEX); 2461 } 2462 break; 2463 default: 2464 return(EINVAL); 2465 } 2466 return(0); 2467 } 2468 2469 mii = device_get_softc(sc->bge_miibus); 2470 sc->bge_link = 0; 2471 if (mii->mii_instance) { 2472 struct mii_softc *miisc; 2473 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 2474 miisc = LIST_NEXT(miisc, mii_list)) 2475 mii_phy_reset(miisc); 2476 } 2477 bge_phy_hack(sc); 2478 mii_mediachg(mii); 2479 2480 return(0); 2481} 2482 2483/* 2484 * Report current media status. 2485 */ 2486static void 2487bge_ifmedia_sts(ifp, ifmr) 2488 struct ifnet *ifp; 2489 struct ifmediareq *ifmr; 2490{ 2491 struct bge_softc *sc; 2492 struct mii_data *mii; 2493 2494 sc = ifp->if_softc; 2495 2496 if (sc->bge_tbi) { 2497 ifmr->ifm_status = IFM_AVALID; 2498 ifmr->ifm_active = IFM_ETHER; 2499 if (CSR_READ_4(sc, BGE_MAC_STS) & 2500 BGE_MACSTAT_TBI_PCS_SYNCHED) 2501 ifmr->ifm_status |= IFM_ACTIVE; 2502 ifmr->ifm_active |= IFM_1000_SX; 2503 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX) 2504 ifmr->ifm_active |= IFM_HDX; 2505 else 2506 ifmr->ifm_active |= IFM_FDX; 2507 return; 2508 } 2509 2510 mii = device_get_softc(sc->bge_miibus); 2511 mii_pollstat(mii); 2512 ifmr->ifm_active = mii->mii_media_active; 2513 ifmr->ifm_status = mii->mii_media_status; 2514 2515 return; 2516} 2517 2518static int 2519bge_ioctl(ifp, command, data) 2520 struct ifnet *ifp; 2521 u_long command; 2522 caddr_t data; 2523{ 2524 struct bge_softc *sc = ifp->if_softc; 2525 struct ifreq *ifr = (struct ifreq *) data; 2526 int s, mask, error = 0; 2527 struct mii_data *mii; 2528 2529 s = splimp(); 2530 2531 switch(command) { 2532 case SIOCSIFADDR: 2533 case SIOCGIFADDR: 2534 error = ether_ioctl(ifp, command, data); 2535 break; 2536 case SIOCSIFMTU: 2537 if (ifr->ifr_mtu > BGE_JUMBO_MTU) 2538 error = EINVAL; 2539 else { 2540 ifp->if_mtu = ifr->ifr_mtu; 2541 ifp->if_flags &= ~IFF_RUNNING; 2542 bge_init(sc); 2543 } 2544 break; 2545 case SIOCSIFFLAGS: 2546 if (ifp->if_flags & IFF_UP) { 2547 /* 2548 * If only the state of the PROMISC flag changed, 2549 * then just use the 'set promisc mode' command 2550 * instead of reinitializing the entire NIC. Doing 2551 * a full re-init means reloading the firmware and 2552 * waiting for it to start up, which may take a 2553 * second or two. 2554 */ 2555 if (ifp->if_flags & IFF_RUNNING && 2556 ifp->if_flags & IFF_PROMISC && 2557 !(sc->bge_if_flags & IFF_PROMISC)) { 2558 BGE_SETBIT(sc, BGE_RX_MODE, 2559 BGE_RXMODE_RX_PROMISC); 2560 } else if (ifp->if_flags & IFF_RUNNING && 2561 !(ifp->if_flags & IFF_PROMISC) && 2562 sc->bge_if_flags & IFF_PROMISC) { 2563 BGE_CLRBIT(sc, BGE_RX_MODE, 2564 BGE_RXMODE_RX_PROMISC); 2565 } else 2566 bge_init(sc); 2567 } else { 2568 if (ifp->if_flags & IFF_RUNNING) { 2569 bge_stop(sc); 2570 } 2571 } 2572 sc->bge_if_flags = ifp->if_flags; 2573 error = 0; 2574 break; 2575 case SIOCADDMULTI: 2576 case SIOCDELMULTI: 2577 if (ifp->if_flags & IFF_RUNNING) { 2578 bge_setmulti(sc); 2579 error = 0; 2580 } 2581 break; 2582 case SIOCSIFMEDIA: 2583 case SIOCGIFMEDIA: 2584 if (sc->bge_tbi) { 2585 error = ifmedia_ioctl(ifp, ifr, 2586 &sc->bge_ifmedia, command); 2587 } else { 2588 mii = device_get_softc(sc->bge_miibus); 2589 error = ifmedia_ioctl(ifp, ifr, 2590 &mii->mii_media, command); 2591 } 2592 break; 2593 case SIOCSIFCAP: 2594 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2595 if (mask & IFCAP_HWCSUM) { 2596 if (IFCAP_HWCSUM & ifp->if_capenable) 2597 ifp->if_capenable &= ~IFCAP_HWCSUM; 2598 else 2599 ifp->if_capenable |= IFCAP_HWCSUM; 2600 } 2601 error = 0; 2602 break; 2603 default: 2604 error = EINVAL; 2605 break; 2606 } 2607 2608 (void)splx(s); 2609 2610 return(error); 2611} 2612 2613static void 2614bge_watchdog(ifp) 2615 struct ifnet *ifp; 2616{ 2617 struct bge_softc *sc; 2618 2619 sc = ifp->if_softc; 2620 2621 printf("bge%d: watchdog timeout -- resetting\n", sc->bge_unit); 2622 2623 ifp->if_flags &= ~IFF_RUNNING; 2624 bge_init(sc); 2625 2626 ifp->if_oerrors++; 2627 2628 return; 2629} 2630 2631/* 2632 * Stop the adapter and free any mbufs allocated to the 2633 * RX and TX lists. 2634 */ 2635static void 2636bge_stop(sc) 2637 struct bge_softc *sc; 2638{ 2639 struct ifnet *ifp; 2640 struct ifmedia_entry *ifm; 2641 struct mii_data *mii = NULL; 2642 int mtmp, itmp; 2643 2644 ifp = &sc->arpcom.ac_if; 2645 2646 if (!sc->bge_tbi) 2647 mii = device_get_softc(sc->bge_miibus); 2648 2649 untimeout(bge_tick, sc, sc->bge_stat_ch); 2650 2651 /* 2652 * Disable all of the receiver blocks 2653 */ 2654 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE); 2655 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE); 2656 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE); 2657 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE); 2658 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE); 2659 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE); 2660 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE); 2661 2662 /* 2663 * Disable all of the transmit blocks 2664 */ 2665 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE); 2666 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE); 2667 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE); 2668 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE); 2669 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE); 2670 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE); 2671 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE); 2672 2673 /* 2674 * Shut down all of the memory managers and related 2675 * state machines. 2676 */ 2677 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE); 2678 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE); 2679 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE); 2680 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF); 2681 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0); 2682 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE); 2683 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE); 2684 2685 /* Disable host interrupts. */ 2686 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR); 2687 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1); 2688 2689 /* 2690 * Tell firmware we're shutting down. 2691 */ 2692 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP); 2693 2694 /* Free the RX lists. */ 2695 bge_free_rx_ring_std(sc); 2696 2697 /* Free jumbo RX list. */ 2698 bge_free_rx_ring_jumbo(sc); 2699 2700 /* Free TX buffers. */ 2701 bge_free_tx_ring(sc); 2702 2703 /* 2704 * Isolate/power down the PHY, but leave the media selection 2705 * unchanged so that things will be put back to normal when 2706 * we bring the interface back up. 2707 */ 2708 if (!sc->bge_tbi) { 2709 itmp = ifp->if_flags; 2710 ifp->if_flags |= IFF_UP; 2711 ifm = mii->mii_media.ifm_cur; 2712 mtmp = ifm->ifm_media; 2713 ifm->ifm_media = IFM_ETHER|IFM_NONE; 2714 mii_mediachg(mii); 2715 ifm->ifm_media = mtmp; 2716 ifp->if_flags = itmp; 2717 } 2718 2719 sc->bge_link = 0; 2720 2721 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET; 2722 2723 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2724 2725 return; 2726} 2727 2728/* 2729 * Stop all chip I/O so that the kernel's probe routines don't 2730 * get confused by errant DMAs when rebooting. 2731 */ 2732static void 2733bge_shutdown(dev) 2734 device_t dev; 2735{ 2736 struct bge_softc *sc; 2737 2738 sc = device_get_softc(dev); 2739 2740 bge_stop(sc); 2741 bge_reset(sc); 2742 2743 return; 2744}
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