1/*-
2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:

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27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34#include <sys/cdefs.h>
35__FBSDID("$FreeBSD: head/sys/dev/bge/if_bge.c 241343 2012-10-08 07:33:43Z yongari $");
36
37/*
38 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
39 *
40 * The Broadcom BCM5700 is based on technology originally developed by
41 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
42 * MAC chips. The BCM5700, sometimes referred to as the Tigon III, has
43 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external

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1461 }
1462
1463 /*
1464 * Set up the PCI DMA control register.
1465 */
1466 dma_rw_ctl = BGE_PCIDMARWCTL_RD_CMD_SHIFT(6) |
1467 BGE_PCIDMARWCTL_WR_CMD_SHIFT(7);
1468 if (sc->bge_flags & BGE_FLAG_PCIE) {
1469 /* Read watermark not used, 128 bytes for write. */
1470 dma_rw_ctl |= BGE_PCIDMARWCTL_WR_WAT_SHIFT(3);
1471 } else if (sc->bge_flags & BGE_FLAG_PCIX) {
1472 if (BGE_IS_5714_FAMILY(sc)) {
1473 /* 256 bytes for read and write. */
1474 dma_rw_ctl |= BGE_PCIDMARWCTL_RD_WAT_SHIFT(2) |
1475 BGE_PCIDMARWCTL_WR_WAT_SHIFT(2);
1476 dma_rw_ctl |= (sc->bge_asicrev == BGE_ASICREV_BCM5780) ?
1477 BGE_PCIDMARWCTL_ONEDMA_ATONCE_GLOBAL :
1478 BGE_PCIDMARWCTL_ONEDMA_ATONCE_LOCAL;

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3156 */
3157 if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
3158 /*
3159 * Found a PCI Express capabilities register, this
3160 * must be a PCI Express device.
3161 */
3162 sc->bge_flags |= BGE_FLAG_PCIE;
3163 sc->bge_expcap = reg;
3164 if (sc->bge_asicrev == BGE_ASICREV_BCM5719 ||
3165 sc->bge_asicrev == BGE_ASICREV_BCM5720)
3166 pci_set_max_read_req(dev, 2048);
3167 else if (pci_get_max_read_req(dev) != 4096)
3168 pci_set_max_read_req(dev, 4096);
3169 } else {
3170 /*
3171 * Check if the device is in PCI-X Mode.
3172 * (This bit is not valid on PCI Express controllers.)
3173 */
3174 if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0)
3175 sc->bge_pcixcap = reg;
3176 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &

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3637 }
3638 devctl = pci_read_config(dev,
3639 sc->bge_expcap + PCIER_DEVICE_CTL, 2);
3640 /* Clear enable no snoop and disable relaxed ordering. */
3641 devctl &= ~(PCIEM_CTL_RELAXED_ORD_ENABLE |
3642 PCIEM_CTL_NOSNOOP_ENABLE);
3643 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_CTL,
3644 devctl, 2);
3645 /* Clear error status. */
3646 pci_write_config(dev, sc->bge_expcap + PCIER_DEVICE_STA,
3647 PCIEM_STA_CORRECTABLE_ERROR |
3648 PCIEM_STA_NON_FATAL_ERROR | PCIEM_STA_FATAL_ERROR |
3649 PCIEM_STA_UNSUPPORTED_REQ, 2);
3650 }
3651
3652 /* Reset some of the PCI state that got zapped by reset. */

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