| virtio.h (275647) | virtio.h (276710) |
|---|---|
| 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * | 1/*- 2 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * --- 13 unchanged lines hidden (view full) --- 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * |
| 30 * $FreeBSD: head/sys/dev/beri/virtio/virtio.h 275647 2014-12-09 16:39:21Z br $ | 30 * $FreeBSD: head/sys/dev/beri/virtio/virtio.h 276710 2015-01-05 16:43:22Z br $ |
| 31 */ 32 33#define READ2(_sc, _reg) \ 34 bus_read_2((_sc)->res[0], _reg) 35#define READ4(_sc, _reg) \ 36 bus_read_4((_sc)->res[0], _reg) 37#define WRITE2(_sc, _reg, _val) \ 38 bus_write_2((_sc)->res[0], _reg, _val) --- 21 unchanged lines hidden (view full) --- 60 61int vq_ring_ready(struct vqueue_info *vq); 62int vq_has_descs(struct vqueue_info *vq); 63void * paddr_map(uint32_t offset, uint32_t phys, uint32_t size); 64void paddr_unmap(void *phys, uint32_t size); 65int vq_getchain(uint32_t beri_mem_offset, struct vqueue_info *vq, 66 struct iovec *iov, int n_iov, uint16_t *flags); 67void vq_relchain(struct vqueue_info *vq, struct iovec *iov, int n, uint32_t iolen); | 31 */ 32 33#define READ2(_sc, _reg) \ 34 bus_read_2((_sc)->res[0], _reg) 35#define READ4(_sc, _reg) \ 36 bus_read_4((_sc)->res[0], _reg) 37#define WRITE2(_sc, _reg, _val) \ 38 bus_write_2((_sc)->res[0], _reg, _val) --- 21 unchanged lines hidden (view full) --- 60 61int vq_ring_ready(struct vqueue_info *vq); 62int vq_has_descs(struct vqueue_info *vq); 63void * paddr_map(uint32_t offset, uint32_t phys, uint32_t size); 64void paddr_unmap(void *phys, uint32_t size); 65int vq_getchain(uint32_t beri_mem_offset, struct vqueue_info *vq, 66 struct iovec *iov, int n_iov, uint16_t *flags); 67void vq_relchain(struct vqueue_info *vq, struct iovec *iov, int n, uint32_t iolen); |
| 68struct iovec * getcopy(struct iovec *iov, int n); |
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| 68 69int setup_pio(device_t dev, char *name, device_t *pio_dev); 70int setup_offset(device_t dev, uint32_t *offset); | 69 70int setup_pio(device_t dev, char *name, device_t *pio_dev); 71int setup_offset(device_t dev, uint32_t *offset); |