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if_bcereg.h (179695) if_bcereg.h (179771)
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 179695 2008-06-10 02:19:11Z davidch $
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 179771 2008-06-13 01:16:37Z davidch $
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
35#ifdef HAVE_KERNEL_OPTION_HEADERS
36#include "opt_device_polling.h"
37#endif
38
35#include <sys/param.h>
36#include <sys/endian.h>
37#include <sys/systm.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>

--- 80 unchanged lines hidden (view full) ---

123 "\07b6" \
124 "\06b5" \
125 "\05b4" \
126 "\04b3" \
127 "\03b2" \
128 "\02b1" \
129 "\01b0"
130
39#include <sys/param.h>
40#include <sys/endian.h>
41#include <sys/systm.h>
42#include <sys/sockio.h>
43#include <sys/mbuf.h>
44#include <sys/malloc.h>
45#include <sys/kernel.h>
46#include <sys/module.h>

--- 80 unchanged lines hidden (view full) ---

127 "\07b6" \
128 "\06b5" \
129 "\05b4" \
130 "\04b3" \
131 "\03b2" \
132 "\02b1" \
133 "\01b0"
134
135/* MII Control Register 0x0 */
136#define BCE_BMCR_PRINTFB \
137 "\020" \
138 "\20Reset" \
139 "\17Loopback" \
140 "\16Spd0" \
141 "\15AnegEna" \
142 "\14PwrDn" \
143 "\13Isolate" \
144 "\12RstrtAneg" \
145 "\11FD" \
146 "\10CollTst" \
147 "\07Spd1" \
148 "\06Rsrvd" \
149 "\05Rsrvd" \
150 "\04Rsrvd" \
151 "\03Rsrvd" \
152 "\02Rsrvd" \
153 "\01Rsrvd"
131
154
155/* MII Status Register 0x1 */
156#define BCE_BMSR_PRINTFB \
157 "\020" \
158 "\20Cap100T4" \
159 "\17Cap100XFD" \
160 "\16Cap100XHD" \
161 "\15Cap10FD" \
162 "\14Cap10HD" \
163 "\13Cap100T2FD" \
164 "\12Cap100T2HD" \
165 "\11ExtStsPrsnt" \
166 "\10Rsrvd" \
167 "\07PrmblSupp" \
168 "\06AnegCmpl" \
169 "\05RemFaultDet" \
170 "\04AnegCap" \
171 "\03LnkUp" \
172 "\02JabberDet" \
173 "\01ExtCapSupp"
174
175/* MII Autoneg Advertisement Register 0x4 */
176#define BCE_ANAR_PRINTFB \
177 "\020" \
178 "\20AdvNxtPg" \
179 "\17Rsrvd" \
180 "\16AdvRemFault" \
181 "\15Rsrvd" \
182 "\14AdvAsymPause" \
183 "\13AdvPause" \
184 "\12Adv100T4" \
185 "\11Adv100FD" \
186 "\10Adv100HD" \
187 "\07Adv10FD" \
188 "\06Adv10HD" \
189 "\05Rsrvd" \
190 "\04Rsrvd" \
191 "\03Rsrvd" \
192 "\02Rsrvd" \
193 "\01Adv802.3"
194
195/* MII Autoneg Link Partner Ability Register 0x5 */
196#define BCE_ANLPAR_PRINTFB \
197 "\020" \
198 "\20CapNxtPg" \
199 "\17Ack" \
200 "\16CapRemFault" \
201 "\15Rsrvd" \
202 "\14CapAsymPause" \
203 "\13CapPause" \
204 "\12Cap100T4" \
205 "\11Cap100FD" \
206 "\10Cap100HD" \
207 "\07Cap10FD" \
208 "\06Cap10HD" \
209 "\05Rsrvd" \
210 "\04Rsrvd" \
211 "\03Rsrvd" \
212 "\02Rsrvd" \
213 "\01Cap802.3"
214
215/* 1000Base-T Control Register 0x09 */
216#define BCE_1000CTL_PRINTFB \
217 "\020" \
218 "\20Test3" \
219 "\17Test2" \
220 "\16Test1" \
221 "\15MasterSlave" \
222 "\14ForceMaster" \
223 "\13SwitchDev" \
224 "\12Adv1000TFD" \
225 "\11Adv1000THD" \
226 "\10Rsrvd" \
227 "\07Rsrvd" \
228 "\06Rsrvd" \
229 "\05Rsrvd" \
230 "\04Rsrvd" \
231 "\03Rsrvd" \
232 "\02Rsrvd" \
233 "\01Rsrvd"
234
235/* MII 1000Base-T Status Register 0x0a */
236#define BCE_1000STS_PRINTFB \
237 "\020" \
238 "\20MstrSlvFault" \
239 "\17Master" \
240 "\16LclRcvrOk" \
241 "\15RemRcvrOk" \
242 "\14Cap1000FD" \
243 "\13Cpa1000HD" \
244 "\12Rsrvd" \
245 "\11Rsrvd"
246
247/* MII Extended Status Register 0x0f */
248#define BCE_EXTSTS_PRINTFB \
249 "\020" \
250 "\20b15" \
251 "\17b14" \
252 "\16b13" \
253 "\15b12" \
254 "\14Rsrvd" \
255 "\13Rsrvd" \
256 "\12Rsrvd" \
257 "\11Rsrvd" \
258 "\10Rsrvd" \
259 "\07Rsrvd" \
260 "\06Rsrvd" \
261 "\05Rsrvd" \
262 "\04Rsrvd" \
263 "\03Rsrvd" \
264 "\02Rsrvd" \
265 "\01Rsrvd"
266
267/* MII Autoneg Link Partner Ability Register 0x19 */
268#define BCE_AUXSTS_PRINTFB \
269 "\020" \
270 "\20AnegCmpl" \
271 "\17AnegCmplAck" \
272 "\16AnegAckDet" \
273 "\15AnegAblDet" \
274 "\14AnegNextPgWait" \
275 "\13HCD" \
276 "\12HCD" \
277 "\11HCD" \
278 "\10PrlDetFault" \
279 "\07RemFault" \
280 "\06PgRcvd" \
281 "\05LnkPrtnrAnegAbl" \
282 "\04LnkPrtnrNPAbl" \
283 "\03LnkUp" \
284 "\02EnaPauseRcv" \
285 "\01EnaPausXmit"
286
287/* Remove before release. */
288/* #define BCE_DEBUG 1 */
289/* #define BCE_NVRAM_WRITE_SUPPORT */
290
132/****************************************************************************/
133/* Debugging macros and definitions. */
134/****************************************************************************/
291/****************************************************************************/
292/* Debugging macros and definitions. */
293/****************************************************************************/
135/* #define BCE_DEBUG 1 */
136
137#define BCE_CP_LOAD 0x00000001
138#define BCE_CP_SEND 0x00000002
139#define BCE_CP_RECV 0x00000004
140#define BCE_CP_INTR 0x00000008
141#define BCE_CP_UNLOAD 0x00000010
142#define BCE_CP_RESET 0x00000020
143#define BCE_CP_PHY 0x00000040
144#define BCE_CP_NVRAM 0x00000080
145#define BCE_CP_FIRMWARE 0x00000100
294
295#define BCE_CP_LOAD 0x00000001
296#define BCE_CP_SEND 0x00000002
297#define BCE_CP_RECV 0x00000004
298#define BCE_CP_INTR 0x00000008
299#define BCE_CP_UNLOAD 0x00000010
300#define BCE_CP_RESET 0x00000020
301#define BCE_CP_PHY 0x00000040
302#define BCE_CP_NVRAM 0x00000080
303#define BCE_CP_FIRMWARE 0x00000100
304#define BCE_CP_CTX 0x00000200
305#define BCE_CP_REG 0x00000400
146#define BCE_CP_MISC 0x00400000
147#define BCE_CP_SPECIAL 0x00800000
148#define BCE_CP_ALL 0x00FFFFFF
149
150#define BCE_CP_MASK 0x00FFFFFF
151
152#define BCE_LEVEL_FATAL 0x00000000
153#define BCE_LEVEL_WARN 0x01000000
154#define BCE_LEVEL_INFO 0x02000000
155#define BCE_LEVEL_VERBOSE 0x03000000
306#define BCE_CP_MISC 0x00400000
307#define BCE_CP_SPECIAL 0x00800000
308#define BCE_CP_ALL 0x00FFFFFF
309
310#define BCE_CP_MASK 0x00FFFFFF
311
312#define BCE_LEVEL_FATAL 0x00000000
313#define BCE_LEVEL_WARN 0x01000000
314#define BCE_LEVEL_INFO 0x02000000
315#define BCE_LEVEL_VERBOSE 0x03000000
156#define BCE_LEVEL_EXCESSIVE 0x04000000
316#define BCE_LEVEL_EXTREME 0x04000000
317#define BCE_LEVEL_INSANE 0x05000000
157
158#define BCE_LEVEL_MASK 0xFF000000
159
160#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN)
161#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO)
162#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
318
319#define BCE_LEVEL_MASK 0xFF000000
320
321#define BCE_WARN_LOAD (BCE_CP_LOAD | BCE_LEVEL_WARN)
322#define BCE_INFO_LOAD (BCE_CP_LOAD | BCE_LEVEL_INFO)
323#define BCE_VERBOSE_LOAD (BCE_CP_LOAD | BCE_LEVEL_VERBOSE)
163#define BCE_EXCESSIVE_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXCESSIVE)
324#define BCE_EXTREME_LOAD (BCE_CP_LOAD | BCE_LEVEL_EXTREME)
325#define BCE_INSANE_LOAD (BCE_CP_LOAD | BCE_LEVEL_INSANE)
164
165#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN)
166#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO)
167#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE)
326
327#define BCE_WARN_SEND (BCE_CP_SEND | BCE_LEVEL_WARN)
328#define BCE_INFO_SEND (BCE_CP_SEND | BCE_LEVEL_INFO)
329#define BCE_VERBOSE_SEND (BCE_CP_SEND | BCE_LEVEL_VERBOSE)
168#define BCE_EXCESSIVE_SEND (BCE_CP_SEND | BCE_LEVEL_EXCESSIVE)
330#define BCE_EXTREME_SEND (BCE_CP_SEND | BCE_LEVEL_EXTREME)
331#define BCE_INSANE_SEND (BCE_CP_SEND | BCE_LEVEL_INSANE)
169
170#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN)
171#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO)
172#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE)
332
333#define BCE_WARN_RECV (BCE_CP_RECV | BCE_LEVEL_WARN)
334#define BCE_INFO_RECV (BCE_CP_RECV | BCE_LEVEL_INFO)
335#define BCE_VERBOSE_RECV (BCE_CP_RECV | BCE_LEVEL_VERBOSE)
173#define BCE_EXCESSIVE_RECV (BCE_CP_RECV | BCE_LEVEL_EXCESSIVE)
336#define BCE_EXTREME_RECV (BCE_CP_RECV | BCE_LEVEL_EXTREME)
337#define BCE_INSANE_RECV (BCE_CP_RECV | BCE_LEVEL_INSANE)
174
175#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN)
176#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO)
177#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE)
338
339#define BCE_WARN_INTR (BCE_CP_INTR | BCE_LEVEL_WARN)
340#define BCE_INFO_INTR (BCE_CP_INTR | BCE_LEVEL_INFO)
341#define BCE_VERBOSE_INTR (BCE_CP_INTR | BCE_LEVEL_VERBOSE)
178#define BCE_EXCESSIVE_INTR (BCE_CP_INTR | BCE_LEVEL_EXCESSIVE)
342#define BCE_EXTREME_INTR (BCE_CP_INTR | BCE_LEVEL_EXTREME)
343#define BCE_INSANE_INTR (BCE_CP_INTR | BCE_LEVEL_INSANE)
179
180#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN)
181#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO)
182#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
344
345#define BCE_WARN_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_WARN)
346#define BCE_INFO_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INFO)
347#define BCE_VERBOSE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_VERBOSE)
183#define BCE_EXCESSIVE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXCESSIVE)
348#define BCE_EXTREME_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_EXTREME)
349#define BCE_INSANE_UNLOAD (BCE_CP_UNLOAD | BCE_LEVEL_INSANE)
184
185#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN)
186#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO)
187#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE)
350
351#define BCE_WARN_RESET (BCE_CP_RESET | BCE_LEVEL_WARN)
352#define BCE_INFO_RESET (BCE_CP_RESET | BCE_LEVEL_INFO)
353#define BCE_VERBOSE_RESET (BCE_CP_RESET | BCE_LEVEL_VERBOSE)
188#define BCE_EXCESSIVE_RESET (BCE_CP_RESET | BCE_LEVEL_EXCESSIVE)
354#define BCE_EXTREME_RESET (BCE_CP_RESET | BCE_LEVEL_EXTREME)
355#define BCE_INSANE_RESET (BCE_CP_RESET | BCE_LEVEL_INSANE)
189
190#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN)
191#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO)
192#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE)
356
357#define BCE_WARN_PHY (BCE_CP_PHY | BCE_LEVEL_WARN)
358#define BCE_INFO_PHY (BCE_CP_PHY | BCE_LEVEL_INFO)
359#define BCE_VERBOSE_PHY (BCE_CP_PHY | BCE_LEVEL_VERBOSE)
193#define BCE_EXCESSIVE_PHY (BCE_CP_PHY | BCE_LEVEL_EXCESSIVE)
360#define BCE_EXTREME_PHY (BCE_CP_PHY | BCE_LEVEL_EXTREME)
361#define BCE_INSANE_PHY (BCE_CP_PHY | BCE_LEVEL_INSANE)
194
195#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN)
196#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO)
197#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE)
362
363#define BCE_WARN_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_WARN)
364#define BCE_INFO_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INFO)
365#define BCE_VERBOSE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_VERBOSE)
198#define BCE_EXCESSIVE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXCESSIVE)
366#define BCE_EXTREME_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_EXTREME)
367#define BCE_INSANE_NVRAM (BCE_CP_NVRAM | BCE_LEVEL_INSANE)
199
200#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN)
201#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO)
368
369#define BCE_WARN_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_WARN)
370#define BCE_INFO_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INFO)
202#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE)
203#define BCE_EXCESSIVE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXCESSIVE)
371#define BCE_VERBOSE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_VERBOSE)
372#define BCE_EXTREME_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_EXTREME)
373#define BCE_INSANE_FIRMWARE (BCE_CP_FIRMWARE | BCE_LEVEL_INSANE)
204
374
375#define BCE_WARN_CTX (BCE_CP_CTX | BCE_LEVEL_WARN)
376#define BCE_INFO_CTX (BCE_CP_CTX | BCE_LEVEL_INFO)
377#define BCE_VERBOSE_CTX (BCE_CP_CTX | BCE_LEVEL_VERBOSE)
378#define BCE_EXTREME_CTX (BCE_CP_CTX | BCE_LEVEL_EXTREME)
379#define BCE_INSANE_CTX (BCE_CP_CTX | BCE_LEVEL_INSANE)
380
381#define BCE_WARN_REG (BCE_CP_REG | BCE_LEVEL_WARN)
382#define BCE_INFO_REG (BCE_CP_REG | BCE_LEVEL_INFO)
383#define BCE_VERBOSE_REG (BCE_CP_REG | BCE_LEVEL_VERBOSE)
384#define BCE_EXTREME_REG (BCE_CP_REG | BCE_LEVEL_EXTREME)
385#define BCE_INSANE_REG (BCE_CP_REG | BCE_LEVEL_INSANE)
386
205#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN)
206#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO)
207#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE)
387#define BCE_WARN_MISC (BCE_CP_MISC | BCE_LEVEL_WARN)
388#define BCE_INFO_MISC (BCE_CP_MISC | BCE_LEVEL_INFO)
389#define BCE_VERBOSE_MISC (BCE_CP_MISC | BCE_LEVEL_VERBOSE)
208#define BCE_EXCESSIVE_MISC (BCE_CP_MISC | BCE_LEVEL_EXCESSIVE)
390#define BCE_EXTREME_MISC (BCE_CP_MISC | BCE_LEVEL_EXTREME)
391#define BCE_INSANE_MISC (BCE_CP_MISC | BCE_LEVEL_INSANE)
209
210#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN)
211#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO)
212#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE)
392
393#define BCE_WARN_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_WARN)
394#define BCE_INFO_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INFO)
395#define BCE_VERBOSE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_VERBOSE)
213#define BCE_EXCESSIVE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXCESSIVE)
396#define BCE_EXTREME_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_EXTREME)
397#define BCE_INSANE_SPECIAL (BCE_CP_SPECIAL | BCE_LEVEL_INSANE)
214
215#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL)
216#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN)
217#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO)
218#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE)
398
399#define BCE_FATAL (BCE_CP_ALL | BCE_LEVEL_FATAL)
400#define BCE_WARN (BCE_CP_ALL | BCE_LEVEL_WARN)
401#define BCE_INFO (BCE_CP_ALL | BCE_LEVEL_INFO)
402#define BCE_VERBOSE (BCE_CP_ALL | BCE_LEVEL_VERBOSE)
219#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
403#define BCE_EXTREME (BCE_CP_ALL | BCE_LEVEL_EXTREME)
404#define BCE_INSANE (BCE_CP_ALL | BCE_LEVEL_INSANE)
220
221#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
222#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
223#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
224
225#ifdef BCE_DEBUG
226
405
406#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
407#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
408#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
409
410#ifdef BCE_DEBUG
411
227/*
228 * Calculate the time delta between two reads
412/*
413 * Calculate the time delta between two reads
229 * of the 25MHz free running clock.
230 */
231#define BCE_TIME_DELTA(start, end) (start > end ? (start - end) : \
232 (~start + end + 1))
233
234/* Print a message based on the logging level and code path. */
235#define DBPRINT(sc, level, format, args...) \
236 if (BCE_LOG_MSG(level)) { \

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257
258/* Runs a particular command based on the code path. */
259#define DBRUNCP(cp, args...) \
260 if (BCE_CODE_PATH(cp)) { \
261 args; \
262 }
263
264/* Runs a particular command based on a condition. */
414 * of the 25MHz free running clock.
415 */
416#define BCE_TIME_DELTA(start, end) (start > end ? (start - end) : \
417 (~start + end + 1))
418
419/* Print a message based on the logging level and code path. */
420#define DBPRINT(sc, level, format, args...) \
421 if (BCE_LOG_MSG(level)) { \

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442
443/* Runs a particular command based on the code path. */
444#define DBRUNCP(cp, args...) \
445 if (BCE_CODE_PATH(cp)) { \
446 args; \
447 }
448
449/* Runs a particular command based on a condition. */
265#define DBRUNIF(cond, args...) \
266 if (cond) { \
267 args; \
450#define DBRUNIF(cond, args...) \
451 if (cond) { \
452 args; \
268 }
269
453 }
454
455/* Announces function entry. */
456#if 0
457#define DBENTER(cond) \
458 u32 start_time = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN); \
459 u32 end_time; \
460 DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__);
461#endif
462
463#define DBENTER(cond) \
464 DBPRINT(sc, (cond), "%s(enter)\n", __FUNCTION__)
465
466/* Announces function exit. */
467#if 0
468#define DBEXIT(cond, val) \
469 end_time = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN); \
470 val += (u64) BCE_TIME_DELTA(start_time, end_time); \
471 DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__);
472#endif
473
474#define DBEXIT(cond) \
475 DBPRINT(sc, (cond), "%s(exit)\n", __FUNCTION__)
476
477/* Temporarily override the debug level. */
478#define DBPUSH(cond) \
479 u32 bce_debug_temp = bce_debug; \
480 bce_debug |= cond;
481
482/* Restore the previously overriden debug level. */
483#define DBPOP() \
484 bce_debug = bce_debug_temp;
485
270/* Needed for random() function which is only used in debugging. */
271#include <sys/random.h>
272
273/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
274#define DB_RANDOMFALSE(defects) (random() > defects)
275#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
276#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
277
278/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
279#define DB_RANDOMTRUE(defects) (random() < defects)
280#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
281#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
282
486/* Needed for random() function which is only used in debugging. */
487#include <sys/random.h>
488
489/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
490#define DB_RANDOMFALSE(defects) (random() > defects)
491#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
492#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
493
494/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
495#define DB_RANDOMTRUE(defects) (random() < defects)
496#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
497#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
498
499#define DB_PRINT_PHY_REG(reg, val) \
500 switch(reg) { \
501 case 0x00: DBPRINT(sc, BCE_INSANE_PHY, \
502 "%s(): phy = %d, reg = 0x%04X (BMCR ), val = 0x%b\n", \
503 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
504 BCE_BMCR_PRINTFB); break; \
505 case 0x01: DBPRINT(sc, BCE_INSANE_PHY, \
506 "%s(): phy = %d, reg = 0x%04X (BMSR ), val = 0x%b\n", \
507 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
508 BCE_BMSR_PRINTFB); break; \
509 case 0x04: DBPRINT(sc, BCE_INSANE_PHY, \
510 "%s(): phy = %d, reg = 0x%04X (ANAR ), val = 0x%b\n", \
511 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
512 BCE_ANAR_PRINTFB); break; \
513 case 0x05: DBPRINT(sc, BCE_INSANE_PHY, \
514 "%s(): phy = %d, reg = 0x%04X (ANLPAR ), val = 0x%b\n", \
515 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
516 BCE_ANLPAR_PRINTFB); break; \
517 case 0x09: DBPRINT(sc, BCE_INSANE_PHY, \
518 "%s(): phy = %d, reg = 0x%04X (1000CTL), val = 0x%b\n", \
519 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
520 BCE_1000CTL_PRINTFB); break; \
521 case 0x0a: DBPRINT(sc, BCE_INSANE_PHY, \
522 "%s(): phy = %d, reg = 0x%04X (1000STS), val = 0x%b\n", \
523 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
524 BCE_1000STS_PRINTFB); break; \
525 case 0x0f: DBPRINT(sc, BCE_INSANE_PHY, \
526 "%s(): phy = %d, reg = 0x%04X (EXTSTS ), val = 0x%b\n", \
527 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
528 BCE_EXTSTS_PRINTFB); break; \
529 case 0x19: DBPRINT(sc, BCE_INSANE_PHY, \
530 "%s(): phy = %d, reg = 0x%04X (AUXSTS ), val = 0x%b\n", \
531 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff, \
532 BCE_AUXSTS_PRINTFB); break; \
533 default: DBPRINT(sc, BCE_INSANE_PHY, \
534 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n", \
535 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff); \
536 }
537
283#else
284
285#define DBPRINT(level, format, args...)
286#define DBRUN(args...)
287#define DBRUNMSG(msg, args...)
288#define DBRUNLV(level, args...)
289#define DBRUNCP(cp, args...)
290#define DBRUNIF(cond, args...)
538#else
539
540#define DBPRINT(level, format, args...)
541#define DBRUN(args...)
542#define DBRUNMSG(msg, args...)
543#define DBRUNLV(level, args...)
544#define DBRUNCP(cp, args...)
545#define DBRUNIF(cond, args...)
546#define DBENTER(cond)
547#define DBEXIT(cond)
548#define DBPUSH(cond)
549#define DBPOP()
291#define DB_RANDOMFALSE(defects)
292#define DB_OR_RANDOMFALSE(percent)
293#define DB_AND_RANDOMFALSE(percent)
294#define DB_RANDOMTRUE(defects)
295#define DB_OR_RANDOMTRUE(percent)
296#define DB_AND_RANDOMTRUE(percent)
550#define DB_RANDOMFALSE(defects)
551#define DB_OR_RANDOMFALSE(percent)
552#define DB_AND_RANDOMFALSE(percent)
553#define DB_RANDOMTRUE(defects)
554#define DB_OR_RANDOMTRUE(percent)
555#define DB_AND_RANDOMTRUE(percent)
556#define DB_PRINT_PHY_REG(reg, val)
297
298#endif /* BCE_DEBUG */
299
300
301/****************************************************************************/
302/* Device identification definitions. */
303/****************************************************************************/
304#define BRCM_VENDORID 0x14E4
305#define BRCM_DEVICEID_BCM5706 0x164A
306#define BRCM_DEVICEID_BCM5706S 0x16AA
307#define BRCM_DEVICEID_BCM5708 0x164C
308#define BRCM_DEVICEID_BCM5708S 0x16AC
557
558#endif /* BCE_DEBUG */
559
560
561/****************************************************************************/
562/* Device identification definitions. */
563/****************************************************************************/
564#define BRCM_VENDORID 0x14E4
565#define BRCM_DEVICEID_BCM5706 0x164A
566#define BRCM_DEVICEID_BCM5706S 0x16AA
567#define BRCM_DEVICEID_BCM5708 0x164C
568#define BRCM_DEVICEID_BCM5708S 0x16AC
569#define BRCM_DEVICEID_BCM5709 0x1639
570#define BRCM_DEVICEID_BCM5709S 0x163A
571#define BRCM_DEVICEID_BCM5716 0x1654
309
310#define HP_VENDORID 0x103C
311
312#define PCI_ANY_ID (u_int16_t) (~0U)
313
314/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
315
316#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000)
317#define BCE_CHIP_NUM_5706 0x57060000
318#define BCE_CHIP_NUM_5708 0x57080000
572
573#define HP_VENDORID 0x103C
574
575#define PCI_ANY_ID (u_int16_t) (~0U)
576
577/* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
578
579#define BCE_CHIP_NUM(sc) (((sc)->bce_chipid) & 0xffff0000)
580#define BCE_CHIP_NUM_5706 0x57060000
581#define BCE_CHIP_NUM_5708 0x57080000
582#define BCE_CHIP_NUM_5709 0x57090000
583#define BCE_CHIP_NUM_5716 0x57160000
319
320#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000)
321#define BCE_CHIP_REV_Ax 0x00000000
322#define BCE_CHIP_REV_Bx 0x00001000
323#define BCE_CHIP_REV_Cx 0x00002000
324
325#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0)
326#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f)
327
328#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0)
329#define BCE_CHIP_ID_5706_A0 0x57060000
330#define BCE_CHIP_ID_5706_A1 0x57060010
331#define BCE_CHIP_ID_5706_A2 0x57060020
332#define BCE_CHIP_ID_5706_A3 0x57060030
333#define BCE_CHIP_ID_5708_A0 0x57080000
334#define BCE_CHIP_ID_5708_B0 0x57081000
335#define BCE_CHIP_ID_5708_B1 0x57081010
336#define BCE_CHIP_ID_5708_B2 0x57081020
584
585#define BCE_CHIP_REV(sc) (((sc)->bce_chipid) & 0x0000f000)
586#define BCE_CHIP_REV_Ax 0x00000000
587#define BCE_CHIP_REV_Bx 0x00001000
588#define BCE_CHIP_REV_Cx 0x00002000
589
590#define BCE_CHIP_METAL(sc) (((sc)->bce_chipid) & 0x00000ff0)
591#define BCE_CHIP_BOND(bp) (((sc)->bce_chipid) & 0x0000000f)
592
593#define BCE_CHIP_ID(sc) (((sc)->bce_chipid) & 0xfffffff0)
594#define BCE_CHIP_ID_5706_A0 0x57060000
595#define BCE_CHIP_ID_5706_A1 0x57060010
596#define BCE_CHIP_ID_5706_A2 0x57060020
597#define BCE_CHIP_ID_5706_A3 0x57060030
598#define BCE_CHIP_ID_5708_A0 0x57080000
599#define BCE_CHIP_ID_5708_B0 0x57081000
600#define BCE_CHIP_ID_5708_B1 0x57081010
601#define BCE_CHIP_ID_5708_B2 0x57081020
602#define BCE_CHIP_ID_5709_A0 0x57090000
603#define BCE_CHIP_ID_5709_A1 0x57090010
604#define BCE_CHIP_ID_5709_B0 0x57091000
605#define BCE_CHIP_ID_5709_B1 0x57091010
606#define BCE_CHIP_ID_5709_B2 0x57091020
607#define BCE_CHIP_ID_5709_C0 0x57092000
608#define BCE_CHIP_ID_5716_C0 0x57162000
337
338#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf)
339
340/* A serdes chip will have the first bit of the bond id set. */
341#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01
342
343
344/* shorthand one */

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418#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
419
420#define ST_MICRO_FLASH_PAGE_BITS 8
421#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
422#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
423#define ST_MICRO_FLASH_PAGE_SIZE 256
424#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
425
609
610#define BCE_CHIP_BOND_ID(sc) (((sc)->bce_chipid) & 0xf)
611
612/* A serdes chip will have the first bit of the bond id set. */
613#define BCE_CHIP_BOND_ID_SERDES_BIT 0x01
614
615
616/* shorthand one */

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690#define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
691
692#define ST_MICRO_FLASH_PAGE_BITS 8
693#define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
694#define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
695#define ST_MICRO_FLASH_PAGE_SIZE 256
696#define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
697
698#define BCM5709_FLASH_PAGE_BITS 8
699#define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS)
700#define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1)
701#define BCM5709_FLASH_PAGE_SIZE 256
702
426#define NVRAM_TIMEOUT_COUNT 30000
427#define BCE_FLASHDESC_MAX 64
428
429#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \
430 BCE_NVM_CFG1_BUFFER_MODE | \
431 BCE_NVM_CFG1_PROTECT_MODE | \
432 BCE_NVM_CFG1_FLASH_SIZE)
433
434#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
435
436struct flash_spec {
437 u32 strapping;
438 u32 config1;
439 u32 config2;
440 u32 config3;
441 u32 write1;
703#define NVRAM_TIMEOUT_COUNT 30000
704#define BCE_FLASHDESC_MAX 64
705
706#define FLASH_STRAP_MASK (BCE_NVM_CFG1_FLASH_MODE | \
707 BCE_NVM_CFG1_BUFFER_MODE | \
708 BCE_NVM_CFG1_PROTECT_MODE | \
709 BCE_NVM_CFG1_FLASH_SIZE)
710
711#define FLASH_BACKUP_STRAP_MASK (0xf << 26)
712
713struct flash_spec {
714 u32 strapping;
715 u32 config1;
716 u32 config2;
717 u32 config3;
718 u32 write1;
442 u32 buffered;
719#define BCE_NV_BUFFERED 0x00000001
720#define BCE_NV_TRANSLATE 0x00000002
721#define BCE_NV_WREN 0x00000004
722 u32 flags;
443 u32 page_bits;
444 u32 page_size;
445 u32 addr_mask;
446 u32 total_size;
447 u8 *name;
448};
449
450
451/****************************************************************************/
452/* Shared Memory layout */
453/* The BCE bootcode will initialize this data area with port configurtion */
454/* information which can be accessed by the driver. */
455/****************************************************************************/
456
723 u32 page_bits;
724 u32 page_size;
725 u32 addr_mask;
726 u32 total_size;
727 u8 *name;
728};
729
730
731/****************************************************************************/
732/* Shared Memory layout */
733/* The BCE bootcode will initialize this data area with port configurtion */
734/* information which can be accessed by the driver. */
735/****************************************************************************/
736
457/*
737/*
458 * This value (in milliseconds) determines the frequency of the driver
459 * issuing the PULSE message code. The firmware monitors this periodic
738 * This value (in milliseconds) determines the frequency of the driver
739 * issuing the PULSE message code. The firmware monitors this periodic
460 * pulse to determine when to switch to an OS-absent mode.
740 * pulse to determine when to switch to an OS-absent mode.
461 */
462#define DRV_PULSE_PERIOD_MS 250
463
741 */
742#define DRV_PULSE_PERIOD_MS 250
743
464/*
744/*
465 * This value (in milliseconds) determines how long the driver should
466 * wait for an acknowledgement from the firmware before timing out. Once
467 * the firmware has timed out, the driver will assume there is no firmware
468 * running and there won't be any firmware-driver synchronization during a
745 * This value (in milliseconds) determines how long the driver should
746 * wait for an acknowledgement from the firmware before timing out. Once
747 * the firmware has timed out, the driver will assume there is no firmware
748 * running and there won't be any firmware-driver synchronization during a
469 * driver reset.
749 * driver reset.
470 */
471#define FW_ACK_TIME_OUT_MS 1000
472
473
474#define BCE_DRV_RESET_SIGNATURE 0x00000000
475#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
476
477#define BCE_DRV_MB 0x00000004

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784#define BCE_PRINTF(fmt, args...) device_printf(sc->bce_dev, fmt, ##args)
785
786#define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
787#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx)
788#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED)
789#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx)
790#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx)
791
750 */
751#define FW_ACK_TIME_OUT_MS 1000
752
753
754#define BCE_DRV_RESET_SIGNATURE 0x00000000
755#define BCE_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
756
757#define BCE_DRV_MB 0x00000004

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1064#define BCE_PRINTF(fmt, args...) device_printf(sc->bce_dev, fmt, ##args)
1065
1066#define BCE_LOCK_INIT(_sc, _name) mtx_init(&(_sc)->bce_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
1067#define BCE_LOCK(_sc) mtx_lock(&(_sc)->bce_mtx)
1068#define BCE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bce_mtx, MA_OWNED)
1069#define BCE_UNLOCK(_sc) mtx_unlock(&(_sc)->bce_mtx)
1070#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx)
1071
792#define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
793#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
794#define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
1072#ifdef BCE_DEBUG
1073#define REG_WR(sc, offset, val) bce_reg_wr(sc, offset, val)
1074#define REG_WR16(sc, offset, val) bce_reg_wr16(sc, offset, val)
1075#define REG_RD(sc, offset) bce_reg_rd(sc, offset)
1076#else
1077#define REG_WR(sc, offset, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val)
1078#define REG_WR16(sc, offset, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val)
1079#define REG_RD(sc, offset) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset)
1080#endif
1081
795#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
796#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
797#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val)
798#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset)
799#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
800#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
801#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
802#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
803
804#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
805#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
806#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF)
807#define BCE_ADDR_HI(y) ((u64) (y) >> 32)
808#else
809#define BCE_ADDR_LO(y) ((u32)y)
810#define BCE_ADDR_HI(y) (0)
811#endif
812
813
1082#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
1083#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
1084#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val)
1085#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset)
1086#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
1087#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
1088#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
1089#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
1090
1091#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
1092#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
1093#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF)
1094#define BCE_ADDR_HI(y) ((u64) (y) >> 32)
1095#else
1096#define BCE_ADDR_LO(y) ((u32)y)
1097#define BCE_ADDR_HI(y) (0)
1098#endif
1099
1100
814/*
815 * The following data structures are generated from RTL code.
816 * Do not modify any values below this line.
817 */
818
819/****************************************************************************/
820/* Do not modify any of the following data structures, they are generated */
821/* from RTL code. */
822/* */
823/* Begin machine generated definitions. */
824/****************************************************************************/
825
826/*

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1117 * l2_context definition
1118 */
1119#define BCE_L2CTX_TYPE 0x00000000
1120#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
1121#define BCE_L2CTX_TYPE_TYPE (0xf<<28)
1122#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
1123#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
1124
1101/****************************************************************************/
1102/* Do not modify any of the following data structures, they are generated */
1103/* from RTL code. */
1104/* */
1105/* Begin machine generated definitions. */
1106/****************************************************************************/
1107
1108/*

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1399 * l2_context definition
1400 */
1401#define BCE_L2CTX_TYPE 0x00000000
1402#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
1403#define BCE_L2CTX_TYPE_TYPE (0xf<<28)
1404#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
1405#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
1406
1407#define BCE_L2CTX_TYPE_XI 0x00000080
1125#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
1126#define BCE_L2CTX_EST_NBD 0x00000088
1127#define BCE_L2CTX_CMD_TYPE 0x00000088
1128#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
1129#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
1130#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
1131
1132#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
1133#define BCE_L2CTX_TSCH_BSEQ 0x00000094
1134#define BCE_L2CTX_TBDR_BSEQ 0x00000098
1135#define BCE_L2CTX_TBDR_BOFF 0x0000009c
1136#define BCE_L2CTX_TBDR_BIDX 0x0000009c
1137#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
1138#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
1139#define BCE_L2CTX_TXP_BOFF 0x000000a8
1140#define BCE_L2CTX_TXP_BIDX 0x000000a8
1141#define BCE_L2CTX_TXP_BSEQ 0x000000ac
1142
1408#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
1409#define BCE_L2CTX_EST_NBD 0x00000088
1410#define BCE_L2CTX_CMD_TYPE 0x00000088
1411#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
1412#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
1413#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
1414
1415#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
1416#define BCE_L2CTX_TSCH_BSEQ 0x00000094
1417#define BCE_L2CTX_TBDR_BSEQ 0x00000098
1418#define BCE_L2CTX_TBDR_BOFF 0x0000009c
1419#define BCE_L2CTX_TBDR_BIDX 0x0000009c
1420#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
1421#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
1422#define BCE_L2CTX_TXP_BOFF 0x000000a8
1423#define BCE_L2CTX_TXP_BIDX 0x000000a8
1424#define BCE_L2CTX_TXP_BSEQ 0x000000ac
1425
1426#define BCE_L2CTX_CMD_TYPE_XI 0x00000240
1427#define BCE_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
1428#define BCE_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
1143
1429
1430
1144/*
1145 * l2_bd_chain_context definition
1146 */
1147#define BCE_L2CTX_BD_PRE_READ 0x00000000
1148#define BCE_L2CTX_CTX_SIZE 0x00000000
1149#define BCE_L2CTX_CTX_TYPE 0x00000000
1150#define BCE_L2CTX_LO_WATER_MARK_DEFAULT 32
1151#define BCE_L2CTX_LO_WATER_MARK_SCALE 4

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1433#define BCE_PCI_MSI_ADDR_H 0x00000454
1434#define BCE_PCI_MSI_ADDR_L 0x00000458
1435
1436
1437/*
1438 * misc_reg definition
1439 * offset: 0x800
1440 */
1431/*
1432 * l2_bd_chain_context definition
1433 */
1434#define BCE_L2CTX_BD_PRE_READ 0x00000000
1435#define BCE_L2CTX_CTX_SIZE 0x00000000
1436#define BCE_L2CTX_CTX_TYPE 0x00000000
1437#define BCE_L2CTX_LO_WATER_MARK_DEFAULT 32
1438#define BCE_L2CTX_LO_WATER_MARK_SCALE 4

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1720#define BCE_PCI_MSI_ADDR_H 0x00000454
1721#define BCE_PCI_MSI_ADDR_L 0x00000458
1722
1723
1724/*
1725 * misc_reg definition
1726 * offset: 0x800
1727 */
1441#define BCE_MISC_COMMAND 0x00000800
1442#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0)
1443#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1)
1444#define BCE_MISC_COMMAND_CORE_RESET (1L<<4)
1445#define BCE_MISC_COMMAND_HARD_RESET (1L<<5)
1446#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8)
1447#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
1728#define BCE_MISC_COMMAND 0x00000800
1729#define BCE_MISC_COMMAND_ENABLE_ALL (1L<<0)
1730#define BCE_MISC_COMMAND_DISABLE_ALL (1L<<1)
1731#define BCE_MISC_COMMAND_SW_RESET (1L<<4)
1732#define BCE_MISC_COMMAND_POR_RESET (1L<<5)
1733#define BCE_MISC_COMMAND_HD_RESET (1L<<6)
1734#define BCE_MISC_COMMAND_CMN_SW_RESET (1L<<7)
1735#define BCE_MISC_COMMAND_PAR_ERROR (1L<<8)
1736#define BCE_MISC_COMMAND_CS16_ERR (1L<<9)
1737#define BCE_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
1738#define BCE_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
1739#define BCE_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
1740#define BCE_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
1741#define BCE_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
1742#define BCE_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
1743#define BCE_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
1744#define BCE_MISC_COMMAND_PCIE_DIS (1L<<28)
1448
1745
1449#define BCE_MISC_CFG 0x00000804
1450#define BCE_MISC_CFG_PCI_GRC_TMOUT (1L<<0)
1451#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1)
1452#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1453#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1454#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1455#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1456#define BCE_MISC_CFG_BIST_EN (1L<<3)
1457#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1458#define BCE_MISC_CFG_BYPASS_BSCAN (1L<<5)
1459#define BCE_MISC_CFG_BYPASS_EJTAG (1L<<6)
1460#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1461#define BCE_MISC_CFG_LEDMODE (0x3L<<8)
1462#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8)
1463#define BCE_MISC_CFG_LEDMODE_GPHY1 (1L<<8)
1464#define BCE_MISC_CFG_LEDMODE_GPHY2 (2L<<8)
1746#define BCE_MISC_CFG 0x00000804
1747#define BCE_MISC_CFG_GRC_TMOUT (1L<<0)
1748#define BCE_MISC_CFG_NVM_WR_EN (0x3L<<1)
1749#define BCE_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
1750#define BCE_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
1751#define BCE_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
1752#define BCE_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
1753#define BCE_MISC_CFG_BIST_EN (1L<<3)
1754#define BCE_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
1755#define BCE_MISC_CFG_RESERVED5_TE (1L<<5)
1756#define BCE_MISC_CFG_RESERVED6_TE (1L<<6)
1757#define BCE_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
1758#define BCE_MISC_CFG_LEDMODE (0x7L<<8)
1759#define BCE_MISC_CFG_LEDMODE_MAC (0L<<8)
1760#define BCE_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
1761#define BCE_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
1762#define BCE_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
1763#define BCE_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
1764#define BCE_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
1765#define BCE_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
1766#define BCE_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
1767#define BCE_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
1768#define BCE_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
1769#define BCE_MISC_CFG_LEDMODE_XI (0xfL<<8)
1770#define BCE_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
1771#define BCE_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
1772#define BCE_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
1773#define BCE_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
1774#define BCE_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
1775#define BCE_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
1776#define BCE_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
1777#define BCE_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
1778#define BCE_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
1779#define BCE_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
1780#define BCE_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
1781#define BCE_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
1782#define BCE_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
1783#define BCE_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
1784#define BCE_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
1785#define BCE_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
1786#define BCE_MISC_CFG_PORT_SELECT_XI (1L<<13)
1787#define BCE_MISC_CFG_PARITY_MODE_XI (1L<<14)
1465
1788
1466#define BCE_MISC_ID 0x00000808
1467#define BCE_MISC_ID_BOND_ID (0xfL<<0)
1468#define BCE_MISC_ID_CHIP_METAL (0xffL<<4)
1469#define BCE_MISC_ID_CHIP_REV (0xfL<<12)
1470#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16)
1789#define BCE_MISC_ID 0x00000808
1790#define BCE_MISC_ID_BOND_ID (0xfL<<0)
1791#define BCE_MISC_ID_BOND_ID_X (0L<<0)
1792#define BCE_MISC_ID_BOND_ID_C (3L<<0)
1793#define BCE_MISC_ID_BOND_ID_S (12L<<0)
1794#define BCE_MISC_ID_CHIP_METAL (0xffL<<4)
1795#define BCE_MISC_ID_CHIP_REV (0xfL<<12)
1796#define BCE_MISC_ID_CHIP_NUM (0xffffL<<16)
1471
1797
1472#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c
1798#define BCE_MISC_ENABLE_STATUS_BITS 0x0000080c
1473#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1474#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1475#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1476#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1799#define BCE_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1800#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
1801#define BCE_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1802#define BCE_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1477#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1803#define BCE_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
1478#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1479#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1480#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1481#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1804#define BCE_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
1805#define BCE_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1806#define BCE_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1807#define BCE_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1482#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1483#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1808#define BCE_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
1809#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1484#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1810#define BCE_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1485#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1486#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1487#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1488#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1489#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1490#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1491#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1811#define BCE_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
1812#define BCE_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
1813#define BCE_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1814#define BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
1815#define BCE_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1816#define BCE_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
1817#define BCE_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
1492#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1493#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1818#define BCE_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
1819#define BCE_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1494#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1820#define BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
1495#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1496#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1497#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1821#define BCE_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1822#define BCE_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1823#define BCE_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1498#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1499#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1500#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1824#define BCE_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
1825#define BCE_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
1826#define BCE_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
1827#define BCE_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1828#define BCE_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1501
1829
1502#define BCE_MISC_ENABLE_SET_BITS 0x00000810
1503#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1504#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1505#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1506#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1507#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1508#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1509#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1510#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1511#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1512#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1513#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1514#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1515#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1516#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1517#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1518#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1519#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1520#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1521#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1522#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1523#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1524#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1525#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1526#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1527#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1528#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1529#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1530#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1830#define BCE_MISC_ENABLE_SET_BITS 0x00000810
1831#define BCE_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1832#define BCE_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
1833#define BCE_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1834#define BCE_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1835#define BCE_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
1836#define BCE_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
1837#define BCE_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1838#define BCE_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1839#define BCE_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1840#define BCE_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
1841#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1842#define BCE_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1843#define BCE_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
1844#define BCE_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
1845#define BCE_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1846#define BCE_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
1847#define BCE_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1848#define BCE_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
1849#define BCE_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
1850#define BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
1851#define BCE_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1852#define BCE_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
1853#define BCE_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1854#define BCE_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1855#define BCE_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1856#define BCE_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
1857#define BCE_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
1858#define BCE_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
1859#define BCE_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1860#define BCE_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1531
1861
1532#define BCE_MISC_ENABLE_CLR_BITS 0x00000814
1533#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1534#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1535#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1536#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1537#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1538#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1539#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1540#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1541#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1542#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1543#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1544#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1545#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1546#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1547#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1548#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1549#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1550#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1551#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1552#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1553#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1554#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1555#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1556#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1557#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1558#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1559#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1560#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1862#define BCE_MISC_ENABLE_DEFAULT 0x05ffffff
1863#define BCE_MISC_ENABLE_DEFAULT_XI 0x17ffffff
1561
1864
1865#define BCE_MISC_ENABLE_CLR_BITS 0x00000814
1866#define BCE_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1867#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
1868#define BCE_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
1869#define BCE_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
1870#define BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
1871#define BCE_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
1872#define BCE_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
1873#define BCE_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
1874#define BCE_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
1875#define BCE_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
1876#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
1877#define BCE_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
1878#define BCE_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
1879#define BCE_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
1880#define BCE_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
1881#define BCE_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
1882#define BCE_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
1883#define BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
1884#define BCE_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
1885#define BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
1886#define BCE_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1887#define BCE_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
1888#define BCE_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1889#define BCE_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1890#define BCE_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1891#define BCE_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
1892#define BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
1893#define BCE_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
1894#define BCE_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1895#define BCE_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1896
1897#define BCE_MISC_ENABLE_CLR_DEFAULT 0x17ffffff
1898
1562#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818
1563#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1564#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1565#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1566#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1567#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1568#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1569#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1570#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1571#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1572#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1573#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1574#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1575#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1576#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1577#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1578#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1579#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1899#define BCE_MISC_CLOCK_CONTROL_BITS 0x00000818
1900#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
1901#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
1902#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
1903#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
1904#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
1905#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
1906#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
1907#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
1908#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
1909#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
1910#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
1911#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
1912#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
1913#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
1914#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
1915#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
1916#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
1580#define BCE_MISC_CLOCK_CONTROL_BITS_PLAY_DEAD (1L<<11)
1917#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
1918#define BCE_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
1581#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1582#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1583#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1584#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1585#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1586#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1919#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
1920#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
1921#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
1922#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
1923#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
1924#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
1925#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
1587#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1926#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
1588#define BCE_MISC_CLOCK_CONTROL_BITS_PCI_PLL_STOP (1L<<17)
1589#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
1590#define BCE_MISC_CLOCK_CONTROL_BITS_USE_SPD_DET (1L<<19)
1591#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
1927#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
1928#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
1929#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
1930#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
1931#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
1932#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
1933#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
1934#define BCE_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
1935#define BCE_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
1592
1936
1593#define BCE_MISC_GPIO 0x0000081c
1594#define BCE_MISC_GPIO_VALUE (0xffL<<0)
1595#define BCE_MISC_GPIO_SET (0xffL<<8)
1596#define BCE_MISC_GPIO_CLR (0xffL<<16)
1597#define BCE_MISC_GPIO_FLOAT (0xffL<<24)
1937#define BCE_MISC_SPIO 0x0000081c
1938#define BCE_MISC_SPIO_VALUE (0xffL<<0)
1939#define BCE_MISC_SPIO_SET (0xffL<<8)
1940#define BCE_MISC_SPIO_CLR (0xffL<<16)
1941#define BCE_MISC_SPIO_FLOAT (0xffL<<24)
1598
1942
1599#define BCE_MISC_GPIO_INT 0x00000820
1600#define BCE_MISC_GPIO_INT_INT_STATE (0xfL<<0)
1601#define BCE_MISC_GPIO_INT_OLD_VALUE (0xfL<<8)
1602#define BCE_MISC_GPIO_INT_OLD_SET (0xfL<<16)
1603#define BCE_MISC_GPIO_INT_OLD_CLR (0xfL<<24)
1943#define BCE_MISC_SPIO_INT 0x00000820
1944#define BCE_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
1945#define BCE_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
1946#define BCE_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
1947#define BCE_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
1948#define BCE_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
1949#define BCE_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
1950#define BCE_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
1951#define BCE_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
1604
1605#define BCE_MISC_CONFIG_LFSR 0x00000824
1606#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1607
1608#define BCE_MISC_LFSR_MASK_BITS 0x00000828
1609#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1610#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1611#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)

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1629#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1630#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1631#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1632#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1633#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1634#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1635#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1636#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1952
1953#define BCE_MISC_CONFIG_LFSR 0x00000824
1954#define BCE_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
1955
1956#define BCE_MISC_LFSR_MASK_BITS 0x00000828
1957#define BCE_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
1958#define BCE_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
1959#define BCE_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)

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1977#define BCE_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
1978#define BCE_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
1979#define BCE_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
1980#define BCE_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
1981#define BCE_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
1982#define BCE_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
1983#define BCE_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
1984#define BCE_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
1985#define BCE_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
1986#define BCE_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
1637
1638#define BCE_MISC_ARB_REQ0 0x0000082c
1639#define BCE_MISC_ARB_REQ1 0x00000830
1640#define BCE_MISC_ARB_REQ2 0x00000834
1641#define BCE_MISC_ARB_REQ3 0x00000838
1642#define BCE_MISC_ARB_REQ4 0x0000083c
1643#define BCE_MISC_ARB_FREE0 0x00000840
1644#define BCE_MISC_ARB_FREE1 0x00000844

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1685#define BCE_MISC_ARB_GNT3_25 (0x7L<<4)
1686#define BCE_MISC_ARB_GNT3_26 (0x7L<<8)
1687#define BCE_MISC_ARB_GNT3_27 (0x7L<<12)
1688#define BCE_MISC_ARB_GNT3_28 (0x7L<<16)
1689#define BCE_MISC_ARB_GNT3_29 (0x7L<<20)
1690#define BCE_MISC_ARB_GNT3_30 (0x7L<<24)
1691#define BCE_MISC_ARB_GNT3_31 (0x7L<<28)
1692
1987
1988#define BCE_MISC_ARB_REQ0 0x0000082c
1989#define BCE_MISC_ARB_REQ1 0x00000830
1990#define BCE_MISC_ARB_REQ2 0x00000834
1991#define BCE_MISC_ARB_REQ3 0x00000838
1992#define BCE_MISC_ARB_REQ4 0x0000083c
1993#define BCE_MISC_ARB_FREE0 0x00000840
1994#define BCE_MISC_ARB_FREE1 0x00000844

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2035#define BCE_MISC_ARB_GNT3_25 (0x7L<<4)
2036#define BCE_MISC_ARB_GNT3_26 (0x7L<<8)
2037#define BCE_MISC_ARB_GNT3_27 (0x7L<<12)
2038#define BCE_MISC_ARB_GNT3_28 (0x7L<<16)
2039#define BCE_MISC_ARB_GNT3_29 (0x7L<<20)
2040#define BCE_MISC_ARB_GNT3_30 (0x7L<<24)
2041#define BCE_MISC_ARB_GNT3_31 (0x7L<<28)
2042
1693#define BCE_MISC_PRBS_CONTROL 0x00000878
1694#define BCE_MISC_PRBS_CONTROL_EN (1L<<0)
1695#define BCE_MISC_PRBS_CONTROL_RSTB (1L<<1)
1696#define BCE_MISC_PRBS_CONTROL_INV (1L<<2)
1697#define BCE_MISC_PRBS_CONTROL_ERR_CLR (1L<<3)
1698#define BCE_MISC_PRBS_CONTROL_ORDER (0x3L<<4)
1699#define BCE_MISC_PRBS_CONTROL_ORDER_7TH (0L<<4)
1700#define BCE_MISC_PRBS_CONTROL_ORDER_15TH (1L<<4)
1701#define BCE_MISC_PRBS_CONTROL_ORDER_23RD (2L<<4)
1702#define BCE_MISC_PRBS_CONTROL_ORDER_31ST (3L<<4)
2043#define BCE_MISC_RESERVED1 0x00000878
2044#define BCE_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
1703
2045
1704#define BCE_MISC_PRBS_STATUS 0x0000087c
1705#define BCE_MISC_PRBS_STATUS_LOCK (1L<<0)
1706#define BCE_MISC_PRBS_STATUS_STKY (1L<<1)
1707#define BCE_MISC_PRBS_STATUS_ERRORS (0x3fffL<<2)
1708#define BCE_MISC_PRBS_STATUS_STATE (0xfL<<16)
2046#define BCE_MISC_RESERVED2 0x0000087c
2047#define BCE_MISC_RESERVED2_PCIE_DIS (1L<<0)
2048#define BCE_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
1709
1710#define BCE_MISC_SM_ASF_CONTROL 0x00000880
1711#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
1712#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
1713#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
1714#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
1715#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
1716#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
1717#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
1718#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
2049
2050#define BCE_MISC_SM_ASF_CONTROL 0x00000880
2051#define BCE_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
2052#define BCE_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
2053#define BCE_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
2054#define BCE_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
2055#define BCE_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
2056#define BCE_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
2057#define BCE_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
2058#define BCE_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
1719#define BCE_MISC_SM_ASF_CONTROL_RES (0xfL<<8)
2059#define BCE_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
2060#define BCE_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
2061#define BCE_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
1720#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
1721#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
1722#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
1723#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
2062#define BCE_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
2063#define BCE_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
2064#define BCE_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
2065#define BCE_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
1724#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x3fL<<16)
1725#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x3fL<<24)
2066#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
2067#define BCE_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
1726#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
1727#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
1728
1729#define BCE_MISC_SMB_IN 0x00000884
1730#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0)
1731#define BCE_MISC_SMB_IN_RDY (1L<<8)
1732#define BCE_MISC_SMB_IN_DONE (1L<<9)
1733#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10)

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1745#define BCE_MISC_SMB_OUT_LAST (1L<<10)
1746#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11)
1747#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12)
1748#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
1749#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
1750#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
1751#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
1752#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
2068#define BCE_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
2069#define BCE_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
2070
2071#define BCE_MISC_SMB_IN 0x00000884
2072#define BCE_MISC_SMB_IN_DAT_IN (0xffL<<0)
2073#define BCE_MISC_SMB_IN_RDY (1L<<8)
2074#define BCE_MISC_SMB_IN_DONE (1L<<9)
2075#define BCE_MISC_SMB_IN_FIRSTBYTE (1L<<10)

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2087#define BCE_MISC_SMB_OUT_LAST (1L<<10)
2088#define BCE_MISC_SMB_OUT_ACC_TYPE (1L<<11)
2089#define BCE_MISC_SMB_OUT_ENB_PEC (1L<<12)
2090#define BCE_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
2091#define BCE_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
2092#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
2093#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
2094#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
1753#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1754#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
1755#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
1756#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
1757#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
2095#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
2096#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
2097#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
2098#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
2099#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
2100#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
1758#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
2101#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
1759#define BCE_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (0x6L<<20)
1760#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
1761#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
1762#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
1763#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
1764#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
1765
1766#define BCE_MISC_SMB_WATCHDOG 0x0000088c
1767#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)

--- 41 unchanged lines hidden (view full) ---

1809#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
1810#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
1811#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
1812#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
1813#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
1814#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
1815#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
1816#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
2102#define BCE_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
2103#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
2104#define BCE_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
2105#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
2106#define BCE_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
2107
2108#define BCE_MISC_SMB_WATCHDOG 0x0000088c
2109#define BCE_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)

--- 41 unchanged lines hidden (view full) ---

2151#define BCE_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
2152#define BCE_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
2153#define BCE_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
2154#define BCE_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
2155#define BCE_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
2156#define BCE_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
2157#define BCE_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
2158#define BCE_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
2159#define BCE_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
2160#define BCE_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
2161#define BCE_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
2162#define BCE_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
2163#define BCE_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
2164#define BCE_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
2165#define BCE_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
2166#define BCE_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
2167#define BCE_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
2168#define BCE_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
2169#define BCE_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
2170#define BCE_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
2171#define BCE_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
2172#define BCE_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
2173#define BCE_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
2174#define BCE_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
2175#define BCE_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
2176#define BCE_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
2177#define BCE_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
2178#define BCE_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
2179#define BCE_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
2180#define BCE_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
2181#define BCE_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
2182#define BCE_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
2183#define BCE_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
2184#define BCE_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
2185#define BCE_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
2186#define BCE_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
2187#define BCE_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
2188#define BCE_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
2189#define BCE_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
2190#define BCE_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
1817
1818#define BCE_MISC_PERR_ENA1 0x000008a8
1819#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
1820#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
1821#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
1822#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
1823#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
1824#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)

--- 18 unchanged lines hidden (view full) ---

1843#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
1844#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
1845#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
1846#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
1847#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
1848#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
1849#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
1850#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
2191
2192#define BCE_MISC_PERR_ENA1 0x000008a8
2193#define BCE_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
2194#define BCE_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
2195#define BCE_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
2196#define BCE_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
2197#define BCE_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
2198#define BCE_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)

--- 18 unchanged lines hidden (view full) ---

2217#define BCE_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
2218#define BCE_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
2219#define BCE_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
2220#define BCE_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
2221#define BCE_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
2222#define BCE_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
2223#define BCE_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
2224#define BCE_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
2225#define BCE_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
2226#define BCE_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
2227#define BCE_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
2228#define BCE_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
2229#define BCE_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
2230#define BCE_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
2231#define BCE_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
2232#define BCE_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
2233#define BCE_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
2234#define BCE_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
2235#define BCE_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
2236#define BCE_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
2237#define BCE_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
2238#define BCE_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
2239#define BCE_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
2240#define BCE_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
2241#define BCE_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
2242#define BCE_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
2243#define BCE_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
2244#define BCE_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
2245#define BCE_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
2246#define BCE_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
2247#define BCE_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
2248#define BCE_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
2249#define BCE_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
2250#define BCE_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
2251#define BCE_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
2252#define BCE_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
2253#define BCE_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
1851
1852#define BCE_MISC_PERR_ENA2 0x000008ac
1853#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
1854#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
1855#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
1856#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
1857#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
1858#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
1859#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
1860#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
1861#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
2254
2255#define BCE_MISC_PERR_ENA2 0x000008ac
2256#define BCE_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
2257#define BCE_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
2258#define BCE_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
2259#define BCE_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
2260#define BCE_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
2261#define BCE_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
2262#define BCE_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
2263#define BCE_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
2264#define BCE_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
2265#define BCE_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
2266#define BCE_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
2267#define BCE_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
2268#define BCE_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
2269#define BCE_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
2270#define BCE_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
2271#define BCE_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
1862
1863#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0
1864#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
1865#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
2272
2273#define BCE_MISC_DEBUG_VECTOR_SEL 0x000008b0
2274#define BCE_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
2275#define BCE_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
2276#define BCE_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
1866
1867#define BCE_MISC_VREG_CONTROL 0x000008b4
1868#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0)
2277
2278#define BCE_MISC_VREG_CONTROL 0x000008b4
2279#define BCE_MISC_VREG_CONTROL_1_2 (0xfL<<0)
2280#define BCE_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
2281#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
2282#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
2283#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
2284#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
2285#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
2286#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
2287#define BCE_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
2288#define BCE_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
2289#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
2290#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
2291#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
2292#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
2293#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
2294#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
2295#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
2296#define BCE_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
1869#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4)
2297#define BCE_MISC_VREG_CONTROL_2_5 (0xfL<<4)
2298#define BCE_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
2299#define BCE_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
2300#define BCE_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
2301#define BCE_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
2302#define BCE_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
2303#define BCE_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
2304#define BCE_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
2305#define BCE_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
2306#define BCE_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
2307#define BCE_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
2308#define BCE_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
2309#define BCE_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
2310#define BCE_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
2311#define BCE_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
2312#define BCE_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
2313#define BCE_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
2314#define BCE_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
2315#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
2316#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
2317#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
2318#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
2319#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
2320#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
2321#define BCE_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
2322#define BCE_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
2323#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
2324#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
2325#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
2326#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
2327#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
2328#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
2329#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
2330#define BCE_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
1870
1871#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8
1872#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
1873
2331
2332#define BCE_MISC_FINAL_CLK_CTL_VAL 0x000008b8
2333#define BCE_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
2334
1874#define BCE_MISC_UNUSED0 0x000008bc
2335#define BCE_MISC_GP_HW_CTL0 0x000008bc
2336#define BCE_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
2337#define BCE_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
2338#define BCE_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
2339#define BCE_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
2340#define BCE_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
2341#define BCE_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
2342#define BCE_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
2343#define BCE_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
2344#define BCE_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
2345#define BCE_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
2346#define BCE_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
2347#define BCE_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
2348#define BCE_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
2349#define BCE_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
2350#define BCE_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
2351#define BCE_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
2352#define BCE_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
2353#define BCE_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
2354#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
2355#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
2356#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
2357#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
2358#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
2359#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
2360#define BCE_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
2361#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
2362#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
2363#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
2364#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
2365#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
2366#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
2367#define BCE_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
2368#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
2369#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
2370#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
2371#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
2372#define BCE_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
2373#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
2374#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
2375#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
2376#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
2377#define BCE_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
2378#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
2379#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
2380#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
2381#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
2382#define BCE_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
2383#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
2384#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
2385#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
2386#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
2387#define BCE_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
1875
2388
2389#define BCE_MISC_GP_HW_CTL1 0x000008c0
2390#define BCE_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
2391#define BCE_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
2392#define BCE_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
2393#define BCE_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
2394#define BCE_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
2395#define BCE_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
1876
2396
1877/*
1878 * nvm_reg definition
1879 * offset: 0x6400
1880 */
1881#define BCE_NVM_COMMAND 0x00006400
1882#define BCE_NVM_COMMAND_RST (1L<<0)
1883#define BCE_NVM_COMMAND_DONE (1L<<3)
1884#define BCE_NVM_COMMAND_DOIT (1L<<4)
1885#define BCE_NVM_COMMAND_WR (1L<<5)
1886#define BCE_NVM_COMMAND_ERASE (1L<<6)
1887#define BCE_NVM_COMMAND_FIRST (1L<<7)
1888#define BCE_NVM_COMMAND_LAST (1L<<8)
1889#define BCE_NVM_COMMAND_WREN (1L<<16)
1890#define BCE_NVM_COMMAND_WRDI (1L<<17)
1891#define BCE_NVM_COMMAND_EWSR (1L<<18)
1892#define BCE_NVM_COMMAND_WRSR (1L<<19)
2397#define BCE_MISC_NEW_HW_CTL 0x000008c4
2398#define BCE_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
2399#define BCE_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
2400#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
2401#define BCE_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
2402#define BCE_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
2403#define BCE_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
1893
2404
1894#define BCE_NVM_STATUS 0x00006404
1895#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
1896#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
1897#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
2405#define BCE_MISC_NEW_CORE_CTL 0x000008c8
2406#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
2407#define BCE_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
2408#define BCE_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
2409#define BCE_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
2410#define BCE_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
1898
2411
1899#define BCE_NVM_WRITE 0x00006408
1900#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
1901#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
1902#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
1903#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
1904#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
1905#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
1906#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
1907#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
2412#define BCE_MISC_ECO_HW_CTL 0x000008cc
2413#define BCE_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
2414#define BCE_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
2415#define BCE_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
1908
2416
1909#define BCE_NVM_ADDR 0x0000640c
1910#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
1911#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
1912#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
1913#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
1914#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
1915#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
1916#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
1917#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
2417#define BCE_MISC_ECO_CORE_CTL 0x000008d0
2418#define BCE_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
2419#define BCE_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
1918
2420
1919#define BCE_NVM_READ 0x00006410
1920#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
1921#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
1922#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
1923#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
1924#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
1925#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
1926#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
1927#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
2421#define BCE_MISC_PPIO 0x000008d4
2422#define BCE_MISC_PPIO_VALUE (0xfL<<0)
2423#define BCE_MISC_PPIO_SET (0xfL<<8)
2424#define BCE_MISC_PPIO_CLR (0xfL<<16)
2425#define BCE_MISC_PPIO_FLOAT (0xfL<<24)
1928
2426
1929#define BCE_NVM_CFG1 0x00006414
1930#define BCE_NVM_CFG1_FLASH_MODE (1L<<0)
1931#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1)
1932#define BCE_NVM_CFG1_PASS_MODE (1L<<2)
1933#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3)
1934#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4)
1935#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
1936#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
1937#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
1938#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
1939#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24)
1940#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25)
1941#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
2427#define BCE_MISC_PPIO_INT 0x000008d8
2428#define BCE_MISC_PPIO_INT_INT_STATE (0xfL<<0)
2429#define BCE_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
2430#define BCE_MISC_PPIO_INT_OLD_SET (0xfL<<16)
2431#define BCE_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
1942
2432
1943#define BCE_NVM_CFG2 0x00006418
1944#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0)
1945#define BCE_NVM_CFG2_DUMMY (0xffL<<8)
1946#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16)
2433#define BCE_MISC_RESET_NUMS 0x000008dc
2434#define BCE_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
2435#define BCE_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
2436#define BCE_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
2437#define BCE_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
2438#define BCE_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
1947
2439
1948#define BCE_NVM_CFG3 0x0000641c
1949#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
1950#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8)
1951#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
1952#define BCE_NVM_CFG3_READ_CMD (0xffL<<24)
2440#define BCE_MISC_CS16_ERR 0x000008e0
2441#define BCE_MISC_CS16_ERR_ENA_PCI (1L<<0)
2442#define BCE_MISC_CS16_ERR_ENA_RDMA (1L<<1)
2443#define BCE_MISC_CS16_ERR_ENA_TDMA (1L<<2)
2444#define BCE_MISC_CS16_ERR_ENA_EMAC (1L<<3)
2445#define BCE_MISC_CS16_ERR_ENA_CTX (1L<<4)
2446#define BCE_MISC_CS16_ERR_ENA_TBDR (1L<<5)
2447#define BCE_MISC_CS16_ERR_ENA_RBDC (1L<<6)
2448#define BCE_MISC_CS16_ERR_ENA_COM (1L<<7)
2449#define BCE_MISC_CS16_ERR_ENA_CP (1L<<8)
2450#define BCE_MISC_CS16_ERR_STA_PCI (1L<<16)
2451#define BCE_MISC_CS16_ERR_STA_RDMA (1L<<17)
2452#define BCE_MISC_CS16_ERR_STA_TDMA (1L<<18)
2453#define BCE_MISC_CS16_ERR_STA_EMAC (1L<<19)
2454#define BCE_MISC_CS16_ERR_STA_CTX (1L<<20)
2455#define BCE_MISC_CS16_ERR_STA_TBDR (1L<<21)
2456#define BCE_MISC_CS16_ERR_STA_RBDC (1L<<22)
2457#define BCE_MISC_CS16_ERR_STA_COM (1L<<23)
2458#define BCE_MISC_CS16_ERR_STA_CP (1L<<24)
1953
2459
1954#define BCE_NVM_SW_ARB 0x00006420
1955#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
1956#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
1957#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
1958#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
1959#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
1960#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
1961#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
1962#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
1963#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8)
1964#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9)
1965#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10)
1966#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11)
1967#define BCE_NVM_SW_ARB_REQ0 (1L<<12)
1968#define BCE_NVM_SW_ARB_REQ1 (1L<<13)
1969#define BCE_NVM_SW_ARB_REQ2 (1L<<14)
1970#define BCE_NVM_SW_ARB_REQ3 (1L<<15)
2460#define BCE_MISC_SPIO_EVENT 0x000008e4
2461#define BCE_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
1971
2462
1972#define BCE_NVM_ACCESS_ENABLE 0x00006424
1973#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0)
1974#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
2463#define BCE_MISC_PPIO_EVENT 0x000008e8
2464#define BCE_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
1975
2465
1976#define BCE_NVM_WRITE1 0x00006428
1977#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0)
1978#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8)
1979#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16)
2466#define BCE_MISC_DUAL_MEDIA_CTRL 0x000008ec
2467#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
2468#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
2469#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
2470#define BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
2471#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
2472#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
2473#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
2474#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
2475#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
2476#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
2477#define BCE_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
2478#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
2479#define BCE_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
2480#define BCE_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
2481#define BCE_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
2482#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
2483#define BCE_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
2484#define BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
2485#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
2486#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
2487#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
2488#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
2489#define BCE_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
1980
2490
2491#define BCE_MISC_OTP_CMD1 0x000008f0
2492#define BCE_MISC_OTP_CMD1_FMODE (0x7L<<0)
2493#define BCE_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
2494#define BCE_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
2495#define BCE_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
2496#define BCE_MISC_OTP_CMD1_FMODE_SET (3L<<0)
2497#define BCE_MISC_OTP_CMD1_FMODE_RST (4L<<0)
2498#define BCE_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
2499#define BCE_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
2500#define BCE_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
2501#define BCE_MISC_OTP_CMD1_USEPINS (1L<<8)
2502#define BCE_MISC_OTP_CMD1_PROGSEL (1L<<9)
2503#define BCE_MISC_OTP_CMD1_PROGSTART (1L<<10)
2504#define BCE_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
2505#define BCE_MISC_OTP_CMD1_PBYP (1L<<19)
2506#define BCE_MISC_OTP_CMD1_VSEL (0xfL<<20)
2507#define BCE_MISC_OTP_CMD1_TM (0x7L<<27)
2508#define BCE_MISC_OTP_CMD1_SADBYP (1L<<30)
2509#define BCE_MISC_OTP_CMD1_DEBUG (1L<<31)
1981
2510
2511#define BCE_MISC_OTP_CMD2 0x000008f4
2512#define BCE_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
2513#define BCE_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
2514#define BCE_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
2515#define BCE_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
2516#define BCE_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
1982
2517
2518#define BCE_MISC_OTP_STATUS 0x000008f8
2519#define BCE_MISC_OTP_STATUS_DATA (0xffL<<0)
2520#define BCE_MISC_OTP_STATUS_VALID (1L<<8)
2521#define BCE_MISC_OTP_STATUS_BUSY (1L<<9)
2522#define BCE_MISC_OTP_STATUS_BUSYSM (1L<<10)
2523#define BCE_MISC_OTP_STATUS_DONE (1L<<11)
2524
2525#define BCE_MISC_OTP_SHIFT1_CMD 0x000008fc
2526#define BCE_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
2527#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
2528#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
2529#define BCE_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
2530#define BCE_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
2531
2532#define BCE_MISC_OTP_SHIFT1_DATA 0x00000900
2533#define BCE_MISC_OTP_SHIFT2_CMD 0x00000904
2534#define BCE_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
2535#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
2536#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
2537#define BCE_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
2538#define BCE_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
2539
2540#define BCE_MISC_OTP_SHIFT2_DATA 0x00000908
2541#define BCE_MISC_BIST_CS0 0x0000090c
2542#define BCE_MISC_BIST_CS0_MBIST_EN (1L<<0)
2543#define BCE_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
2544#define BCE_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
2545#define BCE_MISC_BIST_CS0_MBIST_DONE (1L<<8)
2546#define BCE_MISC_BIST_CS0_MBIST_GO (1L<<9)
2547#define BCE_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
2548
2549#define BCE_MISC_BIST_MEMSTATUS0 0x00000910
2550#define BCE_MISC_BIST_CS1 0x00000914
2551#define BCE_MISC_BIST_CS1_MBIST_EN (1L<<0)
2552#define BCE_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
2553#define BCE_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
2554#define BCE_MISC_BIST_CS1_MBIST_DONE (1L<<8)
2555#define BCE_MISC_BIST_CS1_MBIST_GO (1L<<9)
2556
2557#define BCE_MISC_BIST_MEMSTATUS1 0x00000918
2558#define BCE_MISC_BIST_CS2 0x0000091c
2559#define BCE_MISC_BIST_CS2_MBIST_EN (1L<<0)
2560#define BCE_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
2561#define BCE_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
2562#define BCE_MISC_BIST_CS2_MBIST_DONE (1L<<8)
2563#define BCE_MISC_BIST_CS2_MBIST_GO (1L<<9)
2564
2565#define BCE_MISC_BIST_MEMSTATUS2 0x00000920
2566#define BCE_MISC_BIST_CS3 0x00000924
2567#define BCE_MISC_BIST_CS3_MBIST_EN (1L<<0)
2568#define BCE_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
2569#define BCE_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
2570#define BCE_MISC_BIST_CS3_MBIST_DONE (1L<<8)
2571#define BCE_MISC_BIST_CS3_MBIST_GO (1L<<9)
2572
2573#define BCE_MISC_BIST_MEMSTATUS3 0x00000928
2574#define BCE_MISC_BIST_CS4 0x0000092c
2575#define BCE_MISC_BIST_CS4_MBIST_EN (1L<<0)
2576#define BCE_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
2577#define BCE_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
2578#define BCE_MISC_BIST_CS4_MBIST_DONE (1L<<8)
2579#define BCE_MISC_BIST_CS4_MBIST_GO (1L<<9)
2580
2581#define BCE_MISC_BIST_MEMSTATUS4 0x00000930
2582#define BCE_MISC_BIST_CS5 0x00000934
2583#define BCE_MISC_BIST_CS5_MBIST_EN (1L<<0)
2584#define BCE_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
2585#define BCE_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
2586#define BCE_MISC_BIST_CS5_MBIST_DONE (1L<<8)
2587#define BCE_MISC_BIST_CS5_MBIST_GO (1L<<9)
2588
2589#define BCE_MISC_BIST_MEMSTATUS5 0x00000938
2590#define BCE_MISC_MEM_TM0 0x0000093c
2591#define BCE_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
2592#define BCE_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
2593#define BCE_MISC_MEM_TM0_UMP_TM (0xffL<<16)
2594#define BCE_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
2595
2596#define BCE_MISC_USPLL_CTRL 0x00000940
2597#define BCE_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
2598#define BCE_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
2599#define BCE_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
2600#define BCE_MISC_USPLL_CTRL_RX (0x3L<<8)
2601#define BCE_MISC_USPLL_CTRL_VC_EN (1L<<10)
2602#define BCE_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
2603#define BCE_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
2604#define BCE_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
2605#define BCE_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
2606#define BCE_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
2607#define BCE_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
2608#define BCE_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
2609#define BCE_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
2610#define BCE_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
2611#define BCE_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
2612#define BCE_MISC_USPLL_CTRL_LOCK (1L<<29)
2613
2614#define BCE_MISC_PERR_STATUS0 0x00000944
2615#define BCE_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
2616#define BCE_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
2617#define BCE_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
2618#define BCE_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
2619#define BCE_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
2620#define BCE_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
2621#define BCE_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
2622#define BCE_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
2623#define BCE_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
2624#define BCE_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
2625#define BCE_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
2626#define BCE_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
2627#define BCE_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
2628#define BCE_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
2629#define BCE_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
2630#define BCE_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
2631#define BCE_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
2632#define BCE_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
2633#define BCE_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
2634#define BCE_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
2635#define BCE_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
2636#define BCE_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
2637#define BCE_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
2638#define BCE_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
2639#define BCE_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
2640#define BCE_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
2641#define BCE_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
2642#define BCE_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
2643#define BCE_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
2644#define BCE_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
2645#define BCE_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
2646#define BCE_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
2647
2648#define BCE_MISC_PERR_STATUS1 0x00000948
2649#define BCE_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
2650#define BCE_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
2651#define BCE_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
2652#define BCE_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
2653#define BCE_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
2654#define BCE_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
2655#define BCE_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
2656#define BCE_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
2657#define BCE_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
2658#define BCE_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
2659#define BCE_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
2660#define BCE_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
2661#define BCE_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
2662#define BCE_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
2663#define BCE_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
2664#define BCE_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
2665#define BCE_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
2666#define BCE_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
2667#define BCE_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
2668#define BCE_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
2669#define BCE_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
2670#define BCE_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
2671#define BCE_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
2672#define BCE_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
2673#define BCE_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
2674#define BCE_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
2675#define BCE_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
2676#define BCE_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
2677#define BCE_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
2678
2679#define BCE_MISC_PERR_STATUS2 0x0000094c
2680#define BCE_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
2681#define BCE_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
2682#define BCE_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
2683#define BCE_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
2684#define BCE_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
2685#define BCE_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
2686#define BCE_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
2687
2688#define BCE_MISC_LCPLL_CTRL0 0x00000950
2689#define BCE_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
2690#define BCE_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
2691#define BCE_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
2692#define BCE_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
2693#define BCE_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
2694#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
2695#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
2696#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
2697#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
2698#define BCE_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
2699#define BCE_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
2700#define BCE_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
2701#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
2702#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
2703#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
2704#define BCE_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
2705#define BCE_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
2706#define BCE_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
2707#define BCE_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
2708#define BCE_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
2709#define BCE_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
2710#define BCE_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
2711#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
2712#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
2713#define BCE_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
2714#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
2715#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
2716#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
2717#define BCE_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
2718#define BCE_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
2719#define BCE_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
2720
2721#define BCE_MISC_LCPLL_CTRL1 0x00000954
2722#define BCE_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
2723#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
2724#define BCE_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
2725#define BCE_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
2726
2727#define BCE_MISC_LCPLL_STATUS 0x00000958
2728#define BCE_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
2729#define BCE_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
2730#define BCE_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
2731#define BCE_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
2732#define BCE_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
2733#define BCE_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
2734#define BCE_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
2735#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
2736#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
2737#define BCE_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
2738
2739#define BCE_MISC_OSCFUNDS_CTRL 0x0000095c
2740#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
2741#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
2742#define BCE_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
2743#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
2744#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
2745#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
2746#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
2747#define BCE_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
2748#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
2749#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
2750#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
2751#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
2752#define BCE_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
2753#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
2754#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
2755#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
2756#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
2757#define BCE_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
2758
2759
1983/*
1984 * dma_reg definition
1985 * offset: 0xc00
1986 */
1987#define BCE_DMA_COMMAND 0x00000c00
1988#define BCE_DMA_COMMAND_ENABLE (1L<<0)
1989
1990#define BCE_DMA_STATUS 0x00000c04

--- 197 unchanged lines hidden (view full) ---

2188
2189#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14
2190
2191
2192/*
2193 * context_reg definition
2194 * offset: 0x1000
2195 */
2760/*
2761 * dma_reg definition
2762 * offset: 0xc00
2763 */
2764#define BCE_DMA_COMMAND 0x00000c00
2765#define BCE_DMA_COMMAND_ENABLE (1L<<0)
2766
2767#define BCE_DMA_STATUS 0x00000c04

--- 197 unchanged lines hidden (view full) ---

2965
2966#define BCE_DMA_FUSE_CTRL2_DATA 0x00000f14
2967
2968
2969/*
2970 * context_reg definition
2971 * offset: 0x1000
2972 */
2196#define BCE_CTX_COMMAND 0x00001000
2197#define BCE_CTX_COMMAND_ENABLED (1L<<0)
2973#define BCE_CTX_COMMAND 0x00001000
2974#define BCE_CTX_COMMAND_ENABLED (1L<<0)
2975#define BCE_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
2976#define BCE_CTX_COMMAND_DISABLE_PLRU (1L<<2)
2977#define BCE_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
2978#define BCE_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
2979#define BCE_CTX_COMMAND_MEM_INIT (1L<<13)
2980#define BCE_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
2981#define BCE_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
2982#define BCE_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
2983#define BCE_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
2984#define BCE_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
2985#define BCE_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
2986#define BCE_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
2987#define BCE_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
2988#define BCE_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
2989#define BCE_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
2990#define BCE_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
2991#define BCE_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
2992#define BCE_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
2993#define BCE_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
2198
2994
2199#define BCE_CTX_STATUS 0x00001004
2200#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0)
2201#define BCE_CTX_STATUS_READ_STAT (1L<<16)
2202#define BCE_CTX_STATUS_WRITE_STAT (1L<<17)
2203#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18)
2204#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
2995#define BCE_CTX_STATUS 0x00001004
2996#define BCE_CTX_STATUS_LOCK_WAIT (1L<<0)
2997#define BCE_CTX_STATUS_READ_STAT (1L<<16)
2998#define BCE_CTX_STATUS_WRITE_STAT (1L<<17)
2999#define BCE_CTX_STATUS_ACC_STALL_STAT (1L<<18)
3000#define BCE_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
3001#define BCE_CTX_STATUS_EXT_READ_STAT (1L<<20)
3002#define BCE_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
3003#define BCE_CTX_STATUS_MISS_STAT (1L<<22)
3004#define BCE_CTX_STATUS_HIT_STAT (1L<<23)
3005#define BCE_CTX_STATUS_DEAD_LOCK (1L<<24)
3006#define BCE_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
3007#define BCE_CTX_STATUS_INVALID_PAGE (1L<<26)
2205
3008
2206#define BCE_CTX_VIRT_ADDR 0x00001008
2207#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
3009#define BCE_CTX_VIRT_ADDR 0x00001008
3010#define BCE_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
2208
3011
2209#define BCE_CTX_PAGE_TBL 0x0000100c
2210#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
3012#define BCE_CTX_PAGE_TBL 0x0000100c
3013#define BCE_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
2211
3014
2212#define BCE_CTX_DATA_ADR 0x00001010
2213#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
3015#define BCE_CTX_DATA_ADR 0x00001010
3016#define BCE_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
2214
3017
2215#define BCE_CTX_DATA 0x00001014
2216#define BCE_CTX_LOCK 0x00001018
2217#define BCE_CTX_LOCK_TYPE (0x7L<<0)
2218#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
2219#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
2220#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
2221#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
2222#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
2223#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7)
2224#define BCE_CTX_LOCK_GRANTED (1L<<26)
2225#define BCE_CTX_LOCK_MODE (0x7L<<27)
2226#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
2227#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
2228#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27)
2229#define BCE_CTX_LOCK_STATUS (1L<<30)
2230#define BCE_CTX_LOCK_REQ (1L<<31)
3018#define BCE_CTX_DATA 0x00001014
3019#define BCE_CTX_LOCK 0x00001018
3020#define BCE_CTX_LOCK_TYPE (0x7L<<0)
3021#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
3022#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
3023#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
3024#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
3025#define BCE_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
3026#define BCE_CTX_LOCK_TYPE_VOID_XI (0L<<0)
3027#define BCE_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
3028#define BCE_CTX_LOCK_TYPE_TX_XI (2L<<0)
3029#define BCE_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
3030#define BCE_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
3031#define BCE_CTX_LOCK_CID_VALUE (0x3fffL<<7)
3032#define BCE_CTX_LOCK_GRANTED (1L<<26)
3033#define BCE_CTX_LOCK_MODE (0x7L<<27)
3034#define BCE_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
3035#define BCE_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
3036#define BCE_CTX_LOCK_MODE_SURE (0x2L<<27)
3037#define BCE_CTX_LOCK_STATUS (1L<<30)
3038#define BCE_CTX_LOCK_REQ (1L<<31)
2231
3039
2232#define BCE_CTX_ACCESS_STATUS 0x00001040
2233#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
2234#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
2235#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
2236#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
2237#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
3040#define BCE_CTX_CTX_CTRL 0x0000101c
3041#define BCE_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
3042#define BCE_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
3043#define BCE_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
3044#define BCE_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
3045#define BCE_CTX_CTX_CTRL_ATTR (1L<<26)
3046#define BCE_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
3047#define BCE_CTX_CTX_CTRL_READ_REQ (1L<<31)
2238
3048
2239#define BCE_CTX_DBG_LOCK_STATUS 0x00001044
2240#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
2241#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
3049#define BCE_CTX_CTX_DATA 0x00001020
3050#define BCE_CTX_ACCESS_STATUS 0x00001040
3051#define BCE_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
3052#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
3053#define BCE_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
3054#define BCE_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
3055#define BCE_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
3056#define BCE_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
3057#define BCE_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
3058#define BCE_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
2242
3059
2243#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080
2244#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
2245#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
2246#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
3060#define BCE_CTX_DBG_LOCK_STATUS 0x00001044
3061#define BCE_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
3062#define BCE_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
2247
3063
2248#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084
2249#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088
2250#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c
2251#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090
2252#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094
2253#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098
2254#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c
2255#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0
3064#define BCE_CTX_CACHE_CTRL_STATUS 0x00001048
3065#define BCE_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
3066#define BCE_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
3067#define BCE_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
3068#define BCE_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
3069#define BCE_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
3070#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
3071#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
3072#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
3073#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
3074#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
3075#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
3076#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
3077#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
3078#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
3079#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
3080#define BCE_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
2256
3081
3082#define BCE_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
3083#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
3084#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
3085#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
3086#define BCE_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
3087#define BCE_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
2257
3088
3089#define BCE_CTX_CACHE_STATUS 0x00001050
3090#define BCE_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
3091#define BCE_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
3092
3093#define BCE_CTX_DMA_STATUS 0x00001054
3094#define BCE_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
3095#define BCE_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
3096#define BCE_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
3097#define BCE_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
3098#define BCE_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
3099#define BCE_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
3100#define BCE_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
3101#define BCE_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
3102#define BCE_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
3103#define BCE_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
3104#define BCE_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
3105
3106#define BCE_CTX_REP_STATUS 0x00001058
3107#define BCE_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
3108#define BCE_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
3109#define BCE_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
3110#define BCE_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
3111#define BCE_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
3112
3113#define BCE_CTX_CKSUM_ERROR_STATUS 0x0000105c
3114#define BCE_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
3115#define BCE_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
3116
3117#define BCE_CTX_CHNL_LOCK_STATUS_0 0x00001080
3118#define BCE_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
3119#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
3120#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
3121#define BCE_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
3122#define BCE_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
3123
3124#define BCE_CTX_CHNL_LOCK_STATUS_1 0x00001084
3125#define BCE_CTX_CHNL_LOCK_STATUS_2 0x00001088
3126#define BCE_CTX_CHNL_LOCK_STATUS_3 0x0000108c
3127#define BCE_CTX_CHNL_LOCK_STATUS_4 0x00001090
3128#define BCE_CTX_CHNL_LOCK_STATUS_5 0x00001094
3129#define BCE_CTX_CHNL_LOCK_STATUS_6 0x00001098
3130#define BCE_CTX_CHNL_LOCK_STATUS_7 0x0000109c
3131#define BCE_CTX_CHNL_LOCK_STATUS_8 0x000010a0
3132#define BCE_CTX_CHNL_LOCK_STATUS_9 0x000010a4
3133
3134#define BCE_CTX_CACHE_DATA 0x000010c4
3135#define BCE_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
3136#define BCE_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
3137#define BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
3138#define BCE_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
3139
3140#define BCE_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
3141#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
3142#define BCE_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
3143
3144#define BCE_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
3145#define BCE_CTX_CAM_CTRL 0x000010d4
3146#define BCE_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
3147#define BCE_CTX_CAM_CTRL_RESET (1L<<27)
3148#define BCE_CTX_CAM_CTRL_INVALIDATE (1L<<28)
3149#define BCE_CTX_CAM_CTRL_SEARCH (1L<<29)
3150#define BCE_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
3151#define BCE_CTX_CAM_CTRL_READ_REQ (1L<<31)
3152
3153
2258/*
2259 * emac_reg definition
2260 * offset: 0x1400
2261 */
2262#define BCE_EMAC_MODE 0x00001400
2263#define BCE_EMAC_MODE_RESET (1L<<0)
2264#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1)
2265#define BCE_EMAC_MODE_PORT (0x3L<<2)

--- 853 unchanged lines hidden (view full) ---

3119 * offset: 0x2000
3120 */
3121#define BCE_RLUP_FTQ_CMD 0x000023f8
3122#define BCE_RLUP_FTQ_CTL 0x000023fc
3123#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3124#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3125
3126
3154/*
3155 * emac_reg definition
3156 * offset: 0x1400
3157 */
3158#define BCE_EMAC_MODE 0x00001400
3159#define BCE_EMAC_MODE_RESET (1L<<0)
3160#define BCE_EMAC_MODE_HALF_DUPLEX (1L<<1)
3161#define BCE_EMAC_MODE_PORT (0x3L<<2)

--- 853 unchanged lines hidden (view full) ---

4015 * offset: 0x2000
4016 */
4017#define BCE_RLUP_FTQ_CMD 0x000023f8
4018#define BCE_RLUP_FTQ_CTL 0x000023fc
4019#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4020#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4021
4022
4023/*
4024 * rv2pcsr_reg definition
4025 * offset: 0x2400
4026 */
4027#define BCE_RV2PCSR_FTQ_CMD 0x000027f8
4028#define BCE_RV2PCSR_FTQ_CTL 0x000027fc
4029#define BCE_RV2PCSR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4030#define BCE_RV2PCSR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3127
4031
4032
3128/*
3129 * rdma_reg definition
3130 * offset: 0x2c00
3131 */
3132#define BCE_RDMA_FTQ_CMD 0x00002ff8
3133#define BCE_RDMA_FTQ_CTL 0x00002ffc
3134#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3135#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)

--- 231 unchanged lines hidden (view full) ---

3367#define BCE_RV2P_MFTQ_CTL 0x00002bfc
3368#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
3369#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
3370#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
3371#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3372#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3373
3374
4033/*
4034 * rdma_reg definition
4035 * offset: 0x2c00
4036 */
4037#define BCE_RDMA_FTQ_CMD 0x00002ff8
4038#define BCE_RDMA_FTQ_CTL 0x00002ffc
4039#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4040#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)

--- 231 unchanged lines hidden (view full) ---

4272#define BCE_RV2P_MFTQ_CTL 0x00002bfc
4273#define BCE_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
4274#define BCE_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
4275#define BCE_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
4276#define BCE_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4277#define BCE_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4278
4279
3375
3376/*
3377 * mq_reg definition
3378 * offset: 0x3c00
3379 */
4280/*
4281 * mq_reg definition
4282 * offset: 0x3c00
4283 */
3380#define BCE_MQ_COMMAND 0x00003c00
3381#define BCE_MQ_COMMAND_ENABLED (1L<<0)
3382#define BCE_MQ_COMMAND_OVERFLOW (1L<<4)
3383#define BCE_MQ_COMMAND_WR_ERROR (1L<<5)
3384#define BCE_MQ_COMMAND_RD_ERROR (1L<<6)
4284#define BCE_MQ_COMMAND 0x00003c00
4285#define BCE_MQ_COMMAND_ENABLED (1L<<0)
4286#define BCE_MQ_COMMAND_INIT (1L<<1)
4287#define BCE_MQ_COMMAND_OVERFLOW (1L<<4)
4288#define BCE_MQ_COMMAND_WR_ERROR (1L<<5)
4289#define BCE_MQ_COMMAND_RD_ERROR (1L<<6)
4290#define BCE_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
4291#define BCE_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
4292#define BCE_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
4293#define BCE_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
3385
4294
3386#define BCE_MQ_STATUS 0x00003c04
3387#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
3388#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
3389#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18)
4295#define BCE_MQ_STATUS 0x00003c04
4296#define BCE_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
4297#define BCE_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
4298#define BCE_MQ_STATUS_PCI_STALL_STAT (1L<<18)
4299#define BCE_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
3390
4300
3391#define BCE_MQ_CONFIG 0x00003c08
3392#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
3393#define BCE_MQ_CONFIG_HALT_DIS (1L<<1)
3394#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
3395#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
3396#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
3397#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
3398#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
3399#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
3400#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
3401#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
4301#define BCE_MQ_CONFIG 0x00003c08
4302#define BCE_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
4303#define BCE_MQ_CONFIG_HALT_DIS (1L<<1)
4304#define BCE_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
4305#define BCE_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
4306#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
4307#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
4308#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
4309#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
4310#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
4311#define BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
4312#define BCE_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
4313#define BCE_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
3402
4314
3403#define BCE_MQ_ENQUEUE1 0x00003c0c
3404#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
3405#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8)
3406#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
3407#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28)
4315#define BCE_MQ_ENQUEUE1 0x00003c0c
4316#define BCE_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
4317#define BCE_MQ_ENQUEUE1_CID (0x3fffL<<8)
4318#define BCE_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
4319#define BCE_MQ_ENQUEUE1_KNL_MODE (1L<<28)
3408
4320
3409#define BCE_MQ_ENQUEUE2 0x00003c10
3410#define BCE_MQ_BAD_WR_ADDR 0x00003c14
3411#define BCE_MQ_BAD_RD_ADDR 0x00003c18
3412#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c
3413#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
4321#define BCE_MQ_ENQUEUE2 0x00003c10
4322#define BCE_MQ_BAD_WR_ADDR 0x00003c14
4323#define BCE_MQ_BAD_RD_ADDR 0x00003c18
4324#define BCE_MQ_KNL_BYP_WIND_START 0x00003c1c
4325#define BCE_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
3414
4326
3415#define BCE_MQ_KNL_WIND_END 0x00003c20
3416#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
4327#define BCE_MQ_KNL_WIND_END 0x00003c20
4328#define BCE_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
3417
4329
3418#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24
3419#define BCE_MQ_KNL_TX_MASK1 0x00003c28
3420#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c
3421#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
3422#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34
3423#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38
3424#define BCE_MQ_KNL_TX_MASK2 0x00003c3c
3425#define BCE_MQ_KNL_CMD_MASK2 0x00003c40
3426#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
3427#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48
3428#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
3429#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50
3430#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54
3431#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
3432#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
3433#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
3434#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64
3435#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68
3436#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
3437#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
3438#define BCE_MQ_MEM_WR_ADDR 0x00003c74
3439#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
4330#define BCE_MQ_KNL_WRITE_MASK1 0x00003c24
4331#define BCE_MQ_KNL_TX_MASK1 0x00003c28
4332#define BCE_MQ_KNL_CMD_MASK1 0x00003c2c
4333#define BCE_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
4334#define BCE_MQ_KNL_RX_V2P_MASK1 0x00003c34
4335#define BCE_MQ_KNL_WRITE_MASK2 0x00003c38
4336#define BCE_MQ_KNL_TX_MASK2 0x00003c3c
4337#define BCE_MQ_KNL_CMD_MASK2 0x00003c40
4338#define BCE_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
4339#define BCE_MQ_KNL_RX_V2P_MASK2 0x00003c48
4340#define BCE_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
4341#define BCE_MQ_KNL_BYP_TX_MASK1 0x00003c50
4342#define BCE_MQ_KNL_BYP_CMD_MASK1 0x00003c54
4343#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
4344#define BCE_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
4345#define BCE_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
4346#define BCE_MQ_KNL_BYP_TX_MASK2 0x00003c64
4347#define BCE_MQ_KNL_BYP_CMD_MASK2 0x00003c68
4348#define BCE_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
4349#define BCE_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
4350#define BCE_MQ_MEM_WR_ADDR 0x00003c74
4351#define BCE_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
3440
4352
3441#define BCE_MQ_MEM_WR_DATA0 0x00003c78
3442#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
4353#define BCE_MQ_MEM_WR_DATA0 0x00003c78
4354#define BCE_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
3443
4355
3444#define BCE_MQ_MEM_WR_DATA1 0x00003c7c
3445#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
4356#define BCE_MQ_MEM_WR_DATA1 0x00003c7c
4357#define BCE_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
3446
4358
3447#define BCE_MQ_MEM_WR_DATA2 0x00003c80
3448#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
4359#define BCE_MQ_MEM_WR_DATA2 0x00003c80
4360#define BCE_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
4361#define BCE_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0)
3449
4362
3450#define BCE_MQ_MEM_RD_ADDR 0x00003c84
3451#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
4363#define BCE_MQ_MEM_RD_ADDR 0x00003c84
4364#define BCE_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
3452
4365
3453#define BCE_MQ_MEM_RD_DATA0 0x00003c88
3454#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
4366#define BCE_MQ_MEM_RD_DATA0 0x00003c88
4367#define BCE_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
3455
4368
3456#define BCE_MQ_MEM_RD_DATA1 0x00003c8c
3457#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
4369#define BCE_MQ_MEM_RD_DATA1 0x00003c8c
4370#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3458
4371
3459#define BCE_MQ_MEM_RD_DATA2 0x00003c90
3460#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
4372#define BCE_MQ_MEM_RD_DATA2 0x00003c90
4373#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
4374#define BCE_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
3461
4375
4376#define BCE_MQ_CONFIG2 0x00003d00
4377#define BCE_MQ_CONFIG2_CONT_SZ (0x7L<<4)
4378#define BCE_MQ_CONFIG2_FIRST_L4L5 (0x1fL<<8)
3462
4379
4380#define BCE_MQ_MAP_L2_3 0x00003d2c
4381#define BCE_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0)
4382#define BCE_MQ_MAP_L2_3_SZ (0x3L<<8)
4383#define BCE_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10)
4384#define BCE_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23)
4385#define BCE_MQ_MAP_L2_3_ARM (0x3L<<26)
4386#define BCE_MQ_MAP_L2_3_ENA (0x1L<<31)
4387#define BCE_MQ_MAP_L2_3_DEFAULT 0x82004646
4388
4389#define BCE_MQ_MAP_L2_5 0x00003d34
4390#define BCE_MQ_MAP_L2_5_MQ_OFFSET (0xffL<<0)
4391#define BCE_MQ_MAP_L2_5_SZ (0x3L<<8)
4392#define BCE_MQ_MAP_L2_5_CTX_OFFSET (0x2ffL<<10)
4393#define BCE_MQ_MAP_L2_5_BIN_OFFSET (0x7L<<23)
4394#define BCE_MQ_MAP_L2_5_ARM (0x3L<<26)
4395#define BCE_MQ_MAP_L2_5_ENA (0x1L<<31)
4396#define BCE_MQ_MAP_L2_5_DEFAULT 0x83000b08
4397
4398
3463/*
3464 * csch_reg definition
3465 * offset: 0x4000
3466 */
4399/*
4400 * csch_reg definition
4401 * offset: 0x4000
4402 */
3467#define BCE_CSCH_COMMAND 0x00004000
3468#define BCE_CSCH_CH_FTQ_CMD 0x000043f8
3469#define BCE_CSCH_CH_FTQ_CTL 0x000043fc
3470#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3471#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4403#define BCE_CSCH_COMMAND 0x00004000
4404#define BCE_CSCH_CH_FTQ_CMD 0x000043f8
4405#define BCE_CSCH_CH_FTQ_CTL 0x000043fc
4406#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4407#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3472
3473
3474/*
3475 * tbdr_reg definition
3476 * offset: 0x5000
3477 */
4408
4409
4410/*
4411 * tbdr_reg definition
4412 * offset: 0x5000
4413 */
3478#define BCE_TBDR_COMMAND 0x00005000
3479#define BCE_TBDR_COMMAND_ENABLE (1L<<0)
3480#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
3481#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)
4414#define BCE_TBDR_COMMAND 0x00005000
4415#define BCE_TBDR_COMMAND_ENABLE (1L<<0)
4416#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
4417#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)
3482
4418
3483#define BCE_TBDR_STATUS 0x00005004
3484#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0)
3485#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1)
3486#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
3487#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
3488#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
3489#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
3490#define BCE_TBDR_STATUS_BURST_CNT (1L<<6)
4419#define BCE_TBDR_STATUS 0x00005004
4420#define BCE_TBDR_STATUS_DMA_WAIT (1L<<0)
4421#define BCE_TBDR_STATUS_FTQ_WAIT (1L<<1)
4422#define BCE_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
4423#define BCE_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
4424#define BCE_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
4425#define BCE_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
4426#define BCE_TBDR_STATUS_BURST_CNT (1L<<6)
3491
4427
3492#define BCE_TBDR_CONFIG 0x00005008
3493#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0)
3494#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8)
3495#define BCE_TBDR_CONFIG_PRIORITY (1L<<9)
3496#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
3497#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
3498#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
3499#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
3500#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
3501#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
3502#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
3503#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
3504#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
3505#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
3506#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
3507#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
3508#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
3509#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
3510#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
4428#define BCE_TBDR_CONFIG 0x00005008
4429#define BCE_TBDR_CONFIG_MAX_BDS (0xffL<<0)
4430#define BCE_TBDR_CONFIG_SWAP_MODE (1L<<8)
4431#define BCE_TBDR_CONFIG_PRIORITY (1L<<9)
4432#define BCE_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
4433#define BCE_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
4434#define BCE_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
4435#define BCE_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
4436#define BCE_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
4437#define BCE_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
4438#define BCE_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
4439#define BCE_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
4440#define BCE_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
4441#define BCE_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
4442#define BCE_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
4443#define BCE_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
4444#define BCE_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
4445#define BCE_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
4446#define BCE_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
3511
4447
3512#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c
3513#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3514#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3515#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3516#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3517#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3518#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4448#define BCE_TBDR_DEBUG_VECT_PEEK 0x0000500c
4449#define BCE_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4450#define BCE_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4451#define BCE_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4452#define BCE_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4453#define BCE_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4454#define BCE_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3519
4455
3520#define BCE_TBDR_FTQ_DATA 0x000053c0
3521#define BCE_TBDR_FTQ_CMD 0x000053f8
3522#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
3523#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10)
3524#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
3525#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
3526#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
3527#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26)
3528#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
3529#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
3530#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
3531#define BCE_TBDR_FTQ_CMD_POP (1L<<30)
3532#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31)
4456#define BCE_TBDR_FTQ_DATA 0x000053c0
4457#define BCE_TBDR_FTQ_CMD 0x000053f8
4458#define BCE_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
4459#define BCE_TBDR_FTQ_CMD_WR_TOP (1L<<10)
4460#define BCE_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
4461#define BCE_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
4462#define BCE_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
4463#define BCE_TBDR_FTQ_CMD_RD_DATA (1L<<26)
4464#define BCE_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
4465#define BCE_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
4466#define BCE_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
4467#define BCE_TBDR_FTQ_CMD_POP (1L<<30)
4468#define BCE_TBDR_FTQ_CMD_BUSY (1L<<31)
3533
4469
3534#define BCE_TBDR_FTQ_CTL 0x000053fc
3535#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0)
3536#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
3537#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3538#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3539#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4470#define BCE_TBDR_FTQ_CTL 0x000053fc
4471#define BCE_TBDR_FTQ_CTL_INTERVENE (1L<<0)
4472#define BCE_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
4473#define BCE_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4474#define BCE_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4475#define BCE_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3540
3541
4476
4477
3542
3543/*
3544 * tdma_reg definition
3545 * offset: 0x5c00
3546 */
4478/*
4479 * tdma_reg definition
4480 * offset: 0x5c00
4481 */
3547#define BCE_TDMA_COMMAND 0x00005c00
3548#define BCE_TDMA_COMMAND_ENABLED (1L<<0)
3549#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4)
3550#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
4482#define BCE_TDMA_COMMAND 0x00005c00
4483#define BCE_TDMA_COMMAND_ENABLED (1L<<0)
4484#define BCE_TDMA_COMMAND_MASTER_ABORT (1L<<4)
4485#define BCE_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
3551
4486
3552#define BCE_TDMA_STATUS 0x00005c04
3553#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0)
3554#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
3555#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
4487#define BCE_TDMA_STATUS 0x00005c04
4488#define BCE_TDMA_STATUS_DMA_WAIT (1L<<0)
4489#define BCE_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
4490#define BCE_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
3556#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3)
3557#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
3558#define BCE_TDMA_STATUS_BURST_CNT (1L<<17)
3559
3560#define BCE_TDMA_CONFIG 0x00005c08
3561#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0)
3562#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1)
3563#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)

--- 61 unchanged lines hidden (view full) ---

3625#define BCE_TDMA_FTQ_CTL 0x00005ffc
3626#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0)
3627#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
3628#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
3629#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3630#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3631
3632
4491#define BCE_TDMA_STATUS_LOCK_WAIT (1L<<3)
4492#define BCE_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
4493#define BCE_TDMA_STATUS_BURST_CNT (1L<<17)
4494
4495#define BCE_TDMA_CONFIG 0x00005c08
4496#define BCE_TDMA_CONFIG_ONE_DMA (1L<<0)
4497#define BCE_TDMA_CONFIG_ONE_RECORD (1L<<1)
4498#define BCE_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)

--- 61 unchanged lines hidden (view full) ---

4560#define BCE_TDMA_FTQ_CTL 0x00005ffc
4561#define BCE_TDMA_FTQ_CTL_INTERVENE (1L<<0)
4562#define BCE_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
4563#define BCE_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4564#define BCE_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4565#define BCE_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4566
4567
4568/*
4569 * nvm_reg definition
4570 * offset: 0x6400
4571 */
4572#define BCE_NVM_COMMAND 0x00006400
4573#define BCE_NVM_COMMAND_RST (1L<<0)
4574#define BCE_NVM_COMMAND_DONE (1L<<3)
4575#define BCE_NVM_COMMAND_DOIT (1L<<4)
4576#define BCE_NVM_COMMAND_WR (1L<<5)
4577#define BCE_NVM_COMMAND_ERASE (1L<<6)
4578#define BCE_NVM_COMMAND_FIRST (1L<<7)
4579#define BCE_NVM_COMMAND_LAST (1L<<8)
4580#define BCE_NVM_COMMAND_WREN (1L<<16)
4581#define BCE_NVM_COMMAND_WRDI (1L<<17)
4582#define BCE_NVM_COMMAND_EWSR (1L<<18)
4583#define BCE_NVM_COMMAND_WRSR (1L<<19)
3633
4584
4585#define BCE_NVM_STATUS 0x00006404
4586#define BCE_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
4587#define BCE_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
4588#define BCE_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
4589
4590#define BCE_NVM_WRITE 0x00006408
4591#define BCE_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
4592#define BCE_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
4593#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
4594#define BCE_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
4595#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
4596#define BCE_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
4597#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
4598#define BCE_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
4599
4600#define BCE_NVM_ADDR 0x0000640c
4601#define BCE_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
4602#define BCE_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
4603#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
4604#define BCE_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
4605#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
4606#define BCE_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
4607#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
4608#define BCE_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
4609
4610#define BCE_NVM_READ 0x00006410
4611#define BCE_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
4612#define BCE_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
4613#define BCE_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
4614#define BCE_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
4615#define BCE_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
4616#define BCE_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
4617#define BCE_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
4618#define BCE_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
4619
4620#define BCE_NVM_CFG1 0x00006414
4621#define BCE_NVM_CFG1_FLASH_MODE (1L<<0)
4622#define BCE_NVM_CFG1_BUFFER_MODE (1L<<1)
4623#define BCE_NVM_CFG1_PASS_MODE (1L<<2)
4624#define BCE_NVM_CFG1_BITBANG_MODE (1L<<3)
4625#define BCE_NVM_CFG1_STATUS_BIT (0x7L<<4)
4626#define BCE_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
4627#define BCE_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
4628#define BCE_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
4629#define BCE_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
4630#define BCE_NVM_CFG1_PROTECT_MODE (1L<<24)
4631#define BCE_NVM_CFG1_FLASH_SIZE (1L<<25)
4632#define BCE_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
4633
4634#define BCE_NVM_CFG2 0x00006418
4635#define BCE_NVM_CFG2_ERASE_CMD (0xffL<<0)
4636#define BCE_NVM_CFG2_DUMMY (0xffL<<8)
4637#define BCE_NVM_CFG2_STATUS_CMD (0xffL<<16)
4638
4639#define BCE_NVM_CFG3 0x0000641c
4640#define BCE_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
4641#define BCE_NVM_CFG3_WRITE_CMD (0xffL<<8)
4642#define BCE_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
4643#define BCE_NVM_CFG3_READ_CMD (0xffL<<24)
4644
4645#define BCE_NVM_SW_ARB 0x00006420
4646#define BCE_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
4647#define BCE_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
4648#define BCE_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
4649#define BCE_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
4650#define BCE_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
4651#define BCE_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
4652#define BCE_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
4653#define BCE_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
4654#define BCE_NVM_SW_ARB_ARB_ARB0 (1L<<8)
4655#define BCE_NVM_SW_ARB_ARB_ARB1 (1L<<9)
4656#define BCE_NVM_SW_ARB_ARB_ARB2 (1L<<10)
4657#define BCE_NVM_SW_ARB_ARB_ARB3 (1L<<11)
4658#define BCE_NVM_SW_ARB_REQ0 (1L<<12)
4659#define BCE_NVM_SW_ARB_REQ1 (1L<<13)
4660#define BCE_NVM_SW_ARB_REQ2 (1L<<14)
4661#define BCE_NVM_SW_ARB_REQ3 (1L<<15)
4662
4663#define BCE_NVM_ACCESS_ENABLE 0x00006424
4664#define BCE_NVM_ACCESS_ENABLE_EN (1L<<0)
4665#define BCE_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
4666
4667#define BCE_NVM_WRITE1 0x00006428
4668#define BCE_NVM_WRITE1_WREN_CMD (0xffL<<0)
4669#define BCE_NVM_WRITE1_WRDI_CMD (0xffL<<8)
4670#define BCE_NVM_WRITE1_SR_DATA (0xffL<<16)
4671
4672
3634/*
3635 * hc_reg definition
3636 * offset: 0x6800
3637 */
3638#define BCE_HC_COMMAND 0x00006800
3639#define BCE_HC_COMMAND_ENABLE (1L<<0)
3640#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4)
3641#define BCE_HC_COMMAND_COAL_NOW (1L<<16)
3642#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
3643#define BCE_HC_COMMAND_STATS_NOW (1L<<18)
3644#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19)
3645#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19)
3646#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
3647#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19)
3648#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19)
3649#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21)
4673/*
4674 * hc_reg definition
4675 * offset: 0x6800
4676 */
4677#define BCE_HC_COMMAND 0x00006800
4678#define BCE_HC_COMMAND_ENABLE (1L<<0)
4679#define BCE_HC_COMMAND_SKIP_ABORT (1L<<4)
4680#define BCE_HC_COMMAND_COAL_NOW (1L<<16)
4681#define BCE_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
4682#define BCE_HC_COMMAND_STATS_NOW (1L<<18)
4683#define BCE_HC_COMMAND_FORCE_INT (0x3L<<19)
4684#define BCE_HC_COMMAND_FORCE_INT_NULL (0L<<19)
4685#define BCE_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
4686#define BCE_HC_COMMAND_FORCE_INT_LOW (2L<<19)
4687#define BCE_HC_COMMAND_FORCE_INT_FREE (3L<<19)
4688#define BCE_HC_COMMAND_CLR_STAT_NOW (1L<<21)
4689#define BCE_HC_COMMAND_MAIN_PWR_INT (1L<<22)
4690#define BCE_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
3650
3651#define BCE_HC_STATUS 0x00006804
3652#define BCE_HC_STATUS_MASTER_ABORT (1L<<0)
3653#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
3654#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
3655#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
3656#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
3657#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)

--- 6 unchanged lines hidden (view full) ---

3664#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0)
3665#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1)
3666#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2)
3667#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3)
3668#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4)
3669#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
3670#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6)
3671#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
4691
4692#define BCE_HC_STATUS 0x00006804
4693#define BCE_HC_STATUS_MASTER_ABORT (1L<<0)
4694#define BCE_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
4695#define BCE_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
4696#define BCE_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
4697#define BCE_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
4698#define BCE_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)

--- 6 unchanged lines hidden (view full) ---

4705#define BCE_HC_CONFIG_COLLECT_STATS (1L<<0)
4706#define BCE_HC_CONFIG_RX_TMR_MODE (1L<<1)
4707#define BCE_HC_CONFIG_TX_TMR_MODE (1L<<2)
4708#define BCE_HC_CONFIG_COM_TMR_MODE (1L<<3)
4709#define BCE_HC_CONFIG_CMD_TMR_MODE (1L<<4)
4710#define BCE_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
4711#define BCE_HC_CONFIG_STATUS_PRIORITY (1L<<6)
4712#define BCE_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
4713#define BCE_HC_CONFIG_PER_MODE (1L<<16)
4714#define BCE_HC_CONFIG_ONE_SHOT (1L<<17)
4715#define BCE_HC_CONFIG_USE_INT_PARAM (1L<<18)
4716#define BCE_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
4717#define BCE_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20)
4718#define BCE_HC_CONFIG_SB_ADDR_INC (0x7L<<24)
4719#define BCE_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
4720#define BCE_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
4721#define BCE_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
4722#define BCE_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
4723#define BCE_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
4724#define BCE_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
4725#define BCE_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
4726#define BCE_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
4727#define BCE_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
4728#define BCE_HC_CONFIG_UNMASK_ALL (1L<<30)
4729#define BCE_HC_CONFIG_TX_SEL (1L<<31)
3672
3673#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c
3674#define BCE_HC_STATUS_ADDR_L 0x00006810
3675#define BCE_HC_STATUS_ADDR_H 0x00006814
3676#define BCE_HC_STATISTICS_ADDR_L 0x00006818
3677#define BCE_HC_STATISTICS_ADDR_H 0x0000681c
3678#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820
3679#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)

--- 20 unchanged lines hidden (view full) ---

3700#define BCE_HC_COM_TICKS_INT (0x3ffL<<16)
3701
3702#define BCE_HC_CMD_TICKS 0x00006838
3703#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0)
3704#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16)
3705
3706#define BCE_HC_PERIODIC_TICKS 0x0000683c
3707#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
4730
4731#define BCE_HC_ATTN_BITS_ENABLE 0x0000680c
4732#define BCE_HC_STATUS_ADDR_L 0x00006810
4733#define BCE_HC_STATUS_ADDR_H 0x00006814
4734#define BCE_HC_STATISTICS_ADDR_L 0x00006818
4735#define BCE_HC_STATISTICS_ADDR_H 0x0000681c
4736#define BCE_HC_TX_QUICK_CONS_TRIP 0x00006820
4737#define BCE_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)

--- 20 unchanged lines hidden (view full) ---

4758#define BCE_HC_COM_TICKS_INT (0x3ffL<<16)
4759
4760#define BCE_HC_CMD_TICKS 0x00006838
4761#define BCE_HC_CMD_TICKS_VALUE (0x3ffL<<0)
4762#define BCE_HC_CMD_TICKS_INT (0x3ffL<<16)
4763
4764#define BCE_HC_PERIODIC_TICKS 0x0000683c
4765#define BCE_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
4766#define BCE_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16)
3708
3709#define BCE_HC_STAT_COLLECT_TICKS 0x00006840
3710#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
3711
3712#define BCE_HC_STATS_TICKS 0x00006844
3713#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
3714
4767
4768#define BCE_HC_STAT_COLLECT_TICKS 0x00006840
4769#define BCE_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
4770
4771#define BCE_HC_STATS_TICKS 0x00006844
4772#define BCE_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
4773
4774#define BCE_HC_STATS_INTERRUPT_STATUS 0x00006848
4775#define BCE_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0)
4776#define BCE_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16)
4777
3715#define BCE_HC_STAT_MEM_DATA 0x0000684c
3716#define BCE_HC_STAT_GEN_SEL_0 0x00006850
3717#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
3718#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
3719#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
3720#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
3721#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
3722#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)

--- 112 unchanged lines hidden (view full) ---

3835#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
3836#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
3837#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
3838#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
3839#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
3840#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
3841#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
3842#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
4778#define BCE_HC_STAT_MEM_DATA 0x0000684c
4779#define BCE_HC_STAT_GEN_SEL_0 0x00006850
4780#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
4781#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
4782#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
4783#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
4784#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
4785#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)

--- 112 unchanged lines hidden (view full) ---

4898#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
4899#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
4900#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
4901#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
4902#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
4903#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
4904#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
4905#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
4906#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0)
4907#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
4908#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
4909#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
4910#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
4911#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
4912#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
4913#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
4914#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
4915#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
4916#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
4917#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
4918#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
4919#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
4920#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
4921#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
4922#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
4923#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
4924#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
4925#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
4926#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
4927#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
4928#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
4929#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
4930#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
4931#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
4932#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
4933#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
4934#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
4935#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
4936#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
4937#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
4938#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
4939#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
4940#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
4941#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
4942#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
4943#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
4944#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
4945#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
4946#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
4947#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
4948#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
4949#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
4950#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
4951#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
4952#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
4953#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
4954#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
4955#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
4956#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
4957#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
4958#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
4959#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
4960#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
4961#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
4962#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
4963#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
4964#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
4965#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
4966#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
4967#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
4968#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
4969#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
4970#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
4971#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
4972#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
4973#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
4974#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
4975#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8)
4976#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16)
4977#define BCE_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24)
3843
3844#define BCE_HC_STAT_GEN_SEL_1 0x00006854
3845#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
3846#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
3847#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
3848#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
4978
4979#define BCE_HC_STAT_GEN_SEL_1 0x00006854
4980#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
4981#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
4982#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
4983#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
4984#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0)
4985#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8)
4986#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16)
4987#define BCE_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24)
3849
3850#define BCE_HC_STAT_GEN_SEL_2 0x00006858
3851#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
3852#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
3853#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
3854#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
4988
4989#define BCE_HC_STAT_GEN_SEL_2 0x00006858
4990#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
4991#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
4992#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
4993#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
4994#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0)
4995#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8)
4996#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16)
4997#define BCE_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24)
3855
3856#define BCE_HC_STAT_GEN_SEL_3 0x0000685c
3857#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
3858#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
3859#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
3860#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
4998
4999#define BCE_HC_STAT_GEN_SEL_3 0x0000685c
5000#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
5001#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
5002#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
5003#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
5004#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0)
5005#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8)
5006#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16)
5007#define BCE_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24)
3861
3862#define BCE_HC_STAT_GEN_STAT0 0x00006888
3863#define BCE_HC_STAT_GEN_STAT1 0x0000688c
3864#define BCE_HC_STAT_GEN_STAT2 0x00006890
3865#define BCE_HC_STAT_GEN_STAT3 0x00006894
3866#define BCE_HC_STAT_GEN_STAT4 0x00006898
3867#define BCE_HC_STAT_GEN_STAT5 0x0000689c
3868#define BCE_HC_STAT_GEN_STAT6 0x000068a0

--- 17 unchanged lines hidden (view full) ---

3886#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8
3887#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec
3888#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0
3889#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4
3890#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8
3891#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc
3892#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900
3893#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904
5008
5009#define BCE_HC_STAT_GEN_STAT0 0x00006888
5010#define BCE_HC_STAT_GEN_STAT1 0x0000688c
5011#define BCE_HC_STAT_GEN_STAT2 0x00006890
5012#define BCE_HC_STAT_GEN_STAT3 0x00006894
5013#define BCE_HC_STAT_GEN_STAT4 0x00006898
5014#define BCE_HC_STAT_GEN_STAT5 0x0000689c
5015#define BCE_HC_STAT_GEN_STAT6 0x000068a0

--- 17 unchanged lines hidden (view full) ---

5033#define BCE_HC_STAT_GEN_STAT_AC8 0x000068e8
5034#define BCE_HC_STAT_GEN_STAT_AC9 0x000068ec
5035#define BCE_HC_STAT_GEN_STAT_AC10 0x000068f0
5036#define BCE_HC_STAT_GEN_STAT_AC11 0x000068f4
5037#define BCE_HC_STAT_GEN_STAT_AC12 0x000068f8
5038#define BCE_HC_STAT_GEN_STAT_AC13 0x000068fc
5039#define BCE_HC_STAT_GEN_STAT_AC14 0x00006900
5040#define BCE_HC_STAT_GEN_STAT_AC15 0x00006904
5041#define BCE_HC_STAT_GEN_STAT_AC 0x000068c8
3894#define BCE_HC_VIS 0x00006908
3895#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
3896#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
3897#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
3898#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
3899#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
3900#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
3901#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)

--- 54 unchanged lines hidden (view full) ---

3956#define BCE_HC_DEBUG_VECT_PEEK 0x00006910
3957#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
3958#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
3959#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
3960#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
3961#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
3962#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
3963
5042#define BCE_HC_VIS 0x00006908
5043#define BCE_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
5044#define BCE_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
5045#define BCE_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
5046#define BCE_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
5047#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
5048#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
5049#define BCE_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)

--- 54 unchanged lines hidden (view full) ---

5104#define BCE_HC_DEBUG_VECT_PEEK 0x00006910
5105#define BCE_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
5106#define BCE_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
5107#define BCE_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
5108#define BCE_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
5109#define BCE_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
5110#define BCE_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
5111
5112#define BCE_HC_COALESCE_NOW 0x00006914
5113#define BCE_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1)
5114#define BCE_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11)
5115#define BCE_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21)
3964
5116
5117#define BCE_HC_MSIX_BIT_VECTOR 0x00006918
5118#define BCE_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0)
3965
5119
5120#define BCE_HC_SB_CONFIG_1 0x00006a00
5121#define BCE_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
5122#define BCE_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
5123#define BCE_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
5124#define BCE_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
5125#define BCE_HC_SB_CONFIG_1_PER_MODE (1L<<16)
5126#define BCE_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
5127#define BCE_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
5128#define BCE_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20)
5129
5130#define BCE_HC_TX_QUICK_CONS_TRIP_1 0x00006a04
5131#define BCE_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5132#define BCE_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5133
5134#define BCE_HC_COMP_PROD_TRIP_1 0x00006a08
5135#define BCE_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0)
5136#define BCE_HC_COMP_PROD_TRIP_1_INT (0xffL<<16)
5137
5138#define BCE_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c
5139#define BCE_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
5140#define BCE_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
5141
5142#define BCE_HC_RX_TICKS_1 0x00006a10
5143#define BCE_HC_RX_TICKS_1_VALUE (0x3ffL<<0)
5144#define BCE_HC_RX_TICKS_1_INT (0x3ffL<<16)
5145
5146#define BCE_HC_TX_TICKS_1 0x00006a14
5147#define BCE_HC_TX_TICKS_1_VALUE (0x3ffL<<0)
5148#define BCE_HC_TX_TICKS_1_INT (0x3ffL<<16)
5149
5150#define BCE_HC_COM_TICKS_1 0x00006a18
5151#define BCE_HC_COM_TICKS_1_VALUE (0x3ffL<<0)
5152#define BCE_HC_COM_TICKS_1_INT (0x3ffL<<16)
5153
5154#define BCE_HC_CMD_TICKS_1 0x00006a1c
5155#define BCE_HC_CMD_TICKS_1_VALUE (0x3ffL<<0)
5156#define BCE_HC_CMD_TICKS_1_INT (0x3ffL<<16)
5157
5158#define BCE_HC_PERIODIC_TICKS_1 0x00006a20
5159#define BCE_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0)
5160#define BCE_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5161
5162#define BCE_HC_SB_CONFIG_2 0x00006a24
5163#define BCE_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
5164#define BCE_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
5165#define BCE_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
5166#define BCE_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
5167#define BCE_HC_SB_CONFIG_2_PER_MODE (1L<<16)
5168#define BCE_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
5169#define BCE_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
5170#define BCE_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20)
5171
5172#define BCE_HC_TX_QUICK_CONS_TRIP_2 0x00006a28
5173#define BCE_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5174#define BCE_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5175
5176#define BCE_HC_COMP_PROD_TRIP_2 0x00006a2c
5177#define BCE_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0)
5178#define BCE_HC_COMP_PROD_TRIP_2_INT (0xffL<<16)
5179
5180#define BCE_HC_RX_QUICK_CONS_TRIP_2 0x00006a30
5181#define BCE_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
5182#define BCE_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
5183
5184#define BCE_HC_RX_TICKS_2 0x00006a34
5185#define BCE_HC_RX_TICKS_2_VALUE (0x3ffL<<0)
5186#define BCE_HC_RX_TICKS_2_INT (0x3ffL<<16)
5187
5188#define BCE_HC_TX_TICKS_2 0x00006a38
5189#define BCE_HC_TX_TICKS_2_VALUE (0x3ffL<<0)
5190#define BCE_HC_TX_TICKS_2_INT (0x3ffL<<16)
5191
5192#define BCE_HC_COM_TICKS_2 0x00006a3c
5193#define BCE_HC_COM_TICKS_2_VALUE (0x3ffL<<0)
5194#define BCE_HC_COM_TICKS_2_INT (0x3ffL<<16)
5195
5196#define BCE_HC_CMD_TICKS_2 0x00006a40
5197#define BCE_HC_CMD_TICKS_2_VALUE (0x3ffL<<0)
5198#define BCE_HC_CMD_TICKS_2_INT (0x3ffL<<16)
5199
5200#define BCE_HC_PERIODIC_TICKS_2 0x00006a44
5201#define BCE_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0)
5202#define BCE_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5203
5204#define BCE_HC_SB_CONFIG_3 0x00006a48
5205#define BCE_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
5206#define BCE_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
5207#define BCE_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
5208#define BCE_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
5209#define BCE_HC_SB_CONFIG_3_PER_MODE (1L<<16)
5210#define BCE_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
5211#define BCE_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
5212#define BCE_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20)
5213
5214#define BCE_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c
5215#define BCE_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5216#define BCE_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5217
5218#define BCE_HC_COMP_PROD_TRIP_3 0x00006a50
5219#define BCE_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0)
5220#define BCE_HC_COMP_PROD_TRIP_3_INT (0xffL<<16)
5221
5222#define BCE_HC_RX_QUICK_CONS_TRIP_3 0x00006a54
5223#define BCE_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
5224#define BCE_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
5225
5226#define BCE_HC_RX_TICKS_3 0x00006a58
5227#define BCE_HC_RX_TICKS_3_VALUE (0x3ffL<<0)
5228#define BCE_HC_RX_TICKS_3_INT (0x3ffL<<16)
5229
5230#define BCE_HC_TX_TICKS_3 0x00006a5c
5231#define BCE_HC_TX_TICKS_3_VALUE (0x3ffL<<0)
5232#define BCE_HC_TX_TICKS_3_INT (0x3ffL<<16)
5233
5234#define BCE_HC_COM_TICKS_3 0x00006a60
5235#define BCE_HC_COM_TICKS_3_VALUE (0x3ffL<<0)
5236#define BCE_HC_COM_TICKS_3_INT (0x3ffL<<16)
5237
5238#define BCE_HC_CMD_TICKS_3 0x00006a64
5239#define BCE_HC_CMD_TICKS_3_VALUE (0x3ffL<<0)
5240#define BCE_HC_CMD_TICKS_3_INT (0x3ffL<<16)
5241
5242#define BCE_HC_PERIODIC_TICKS_3 0x00006a68
5243#define BCE_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0)
5244#define BCE_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5245
5246#define BCE_HC_SB_CONFIG_4 0x00006a6c
5247#define BCE_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
5248#define BCE_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
5249#define BCE_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
5250#define BCE_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
5251#define BCE_HC_SB_CONFIG_4_PER_MODE (1L<<16)
5252#define BCE_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
5253#define BCE_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
5254#define BCE_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20)
5255
5256#define BCE_HC_TX_QUICK_CONS_TRIP_4 0x00006a70
5257#define BCE_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5258#define BCE_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5259
5260#define BCE_HC_COMP_PROD_TRIP_4 0x00006a74
5261#define BCE_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0)
5262#define BCE_HC_COMP_PROD_TRIP_4_INT (0xffL<<16)
5263
5264#define BCE_HC_RX_QUICK_CONS_TRIP_4 0x00006a78
5265#define BCE_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
5266#define BCE_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
5267
5268#define BCE_HC_RX_TICKS_4 0x00006a7c
5269#define BCE_HC_RX_TICKS_4_VALUE (0x3ffL<<0)
5270#define BCE_HC_RX_TICKS_4_INT (0x3ffL<<16)
5271
5272#define BCE_HC_TX_TICKS_4 0x00006a80
5273#define BCE_HC_TX_TICKS_4_VALUE (0x3ffL<<0)
5274#define BCE_HC_TX_TICKS_4_INT (0x3ffL<<16)
5275
5276#define BCE_HC_COM_TICKS_4 0x00006a84
5277#define BCE_HC_COM_TICKS_4_VALUE (0x3ffL<<0)
5278#define BCE_HC_COM_TICKS_4_INT (0x3ffL<<16)
5279
5280#define BCE_HC_CMD_TICKS_4 0x00006a88
5281#define BCE_HC_CMD_TICKS_4_VALUE (0x3ffL<<0)
5282#define BCE_HC_CMD_TICKS_4_INT (0x3ffL<<16)
5283
5284#define BCE_HC_PERIODIC_TICKS_4 0x00006a8c
5285#define BCE_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0)
5286#define BCE_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5287
5288#define BCE_HC_SB_CONFIG_5 0x00006a90
5289#define BCE_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
5290#define BCE_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
5291#define BCE_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
5292#define BCE_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
5293#define BCE_HC_SB_CONFIG_5_PER_MODE (1L<<16)
5294#define BCE_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
5295#define BCE_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
5296#define BCE_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20)
5297
5298#define BCE_HC_TX_QUICK_CONS_TRIP_5 0x00006a94
5299#define BCE_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5300#define BCE_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5301
5302#define BCE_HC_COMP_PROD_TRIP_5 0x00006a98
5303#define BCE_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0)
5304#define BCE_HC_COMP_PROD_TRIP_5_INT (0xffL<<16)
5305
5306#define BCE_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c
5307#define BCE_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
5308#define BCE_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
5309
5310#define BCE_HC_RX_TICKS_5 0x00006aa0
5311#define BCE_HC_RX_TICKS_5_VALUE (0x3ffL<<0)
5312#define BCE_HC_RX_TICKS_5_INT (0x3ffL<<16)
5313
5314#define BCE_HC_TX_TICKS_5 0x00006aa4
5315#define BCE_HC_TX_TICKS_5_VALUE (0x3ffL<<0)
5316#define BCE_HC_TX_TICKS_5_INT (0x3ffL<<16)
5317
5318#define BCE_HC_COM_TICKS_5 0x00006aa8
5319#define BCE_HC_COM_TICKS_5_VALUE (0x3ffL<<0)
5320#define BCE_HC_COM_TICKS_5_INT (0x3ffL<<16)
5321
5322#define BCE_HC_CMD_TICKS_5 0x00006aac
5323#define BCE_HC_CMD_TICKS_5_VALUE (0x3ffL<<0)
5324#define BCE_HC_CMD_TICKS_5_INT (0x3ffL<<16)
5325
5326#define BCE_HC_PERIODIC_TICKS_5 0x00006ab0
5327#define BCE_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0)
5328#define BCE_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5329
5330#define BCE_HC_SB_CONFIG_6 0x00006ab4
5331#define BCE_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
5332#define BCE_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
5333#define BCE_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
5334#define BCE_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
5335#define BCE_HC_SB_CONFIG_6_PER_MODE (1L<<16)
5336#define BCE_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
5337#define BCE_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
5338#define BCE_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20)
5339
5340#define BCE_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8
5341#define BCE_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5342#define BCE_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5343
5344#define BCE_HC_COMP_PROD_TRIP_6 0x00006abc
5345#define BCE_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0)
5346#define BCE_HC_COMP_PROD_TRIP_6_INT (0xffL<<16)
5347
5348#define BCE_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0
5349#define BCE_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
5350#define BCE_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
5351
5352#define BCE_HC_RX_TICKS_6 0x00006ac4
5353#define BCE_HC_RX_TICKS_6_VALUE (0x3ffL<<0)
5354#define BCE_HC_RX_TICKS_6_INT (0x3ffL<<16)
5355
5356#define BCE_HC_TX_TICKS_6 0x00006ac8
5357#define BCE_HC_TX_TICKS_6_VALUE (0x3ffL<<0)
5358#define BCE_HC_TX_TICKS_6_INT (0x3ffL<<16)
5359
5360#define BCE_HC_COM_TICKS_6 0x00006acc
5361#define BCE_HC_COM_TICKS_6_VALUE (0x3ffL<<0)
5362#define BCE_HC_COM_TICKS_6_INT (0x3ffL<<16)
5363
5364#define BCE_HC_CMD_TICKS_6 0x00006ad0
5365#define BCE_HC_CMD_TICKS_6_VALUE (0x3ffL<<0)
5366#define BCE_HC_CMD_TICKS_6_INT (0x3ffL<<16)
5367
5368#define BCE_HC_PERIODIC_TICKS_6 0x00006ad4
5369#define BCE_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0)
5370#define BCE_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5371
5372#define BCE_HC_SB_CONFIG_7 0x00006ad8
5373#define BCE_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
5374#define BCE_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
5375#define BCE_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
5376#define BCE_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
5377#define BCE_HC_SB_CONFIG_7_PER_MODE (1L<<16)
5378#define BCE_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
5379#define BCE_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
5380#define BCE_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20)
5381
5382#define BCE_HC_TX_QUICK_CONS_TRIP_7 0x00006adc
5383#define BCE_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5384#define BCE_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5385
5386#define BCE_HC_COMP_PROD_TRIP_7 0x00006ae0
5387#define BCE_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0)
5388#define BCE_HC_COMP_PROD_TRIP_7_INT (0xffL<<16)
5389
5390#define BCE_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4
5391#define BCE_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
5392#define BCE_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
5393
5394#define BCE_HC_RX_TICKS_7 0x00006ae8
5395#define BCE_HC_RX_TICKS_7_VALUE (0x3ffL<<0)
5396#define BCE_HC_RX_TICKS_7_INT (0x3ffL<<16)
5397
5398#define BCE_HC_TX_TICKS_7 0x00006aec
5399#define BCE_HC_TX_TICKS_7_VALUE (0x3ffL<<0)
5400#define BCE_HC_TX_TICKS_7_INT (0x3ffL<<16)
5401
5402#define BCE_HC_COM_TICKS_7 0x00006af0
5403#define BCE_HC_COM_TICKS_7_VALUE (0x3ffL<<0)
5404#define BCE_HC_COM_TICKS_7_INT (0x3ffL<<16)
5405
5406#define BCE_HC_CMD_TICKS_7 0x00006af4
5407#define BCE_HC_CMD_TICKS_7_VALUE (0x3ffL<<0)
5408#define BCE_HC_CMD_TICKS_7_INT (0x3ffL<<16)
5409
5410#define BCE_HC_PERIODIC_TICKS_7 0x00006af8
5411#define BCE_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0)
5412#define BCE_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5413
5414#define BCE_HC_SB_CONFIG_8 0x00006afc
5415#define BCE_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
5416#define BCE_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
5417#define BCE_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
5418#define BCE_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
5419#define BCE_HC_SB_CONFIG_8_PER_MODE (1L<<16)
5420#define BCE_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
5421#define BCE_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
5422#define BCE_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20)
5423
5424#define BCE_HC_TX_QUICK_CONS_TRIP_8 0x00006b00
5425#define BCE_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5426#define BCE_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5427
5428#define BCE_HC_COMP_PROD_TRIP_8 0x00006b04
5429#define BCE_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0)
5430#define BCE_HC_COMP_PROD_TRIP_8_INT (0xffL<<16)
5431
5432#define BCE_HC_RX_QUICK_CONS_TRIP_8 0x00006b08
5433#define BCE_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
5434#define BCE_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
5435
5436#define BCE_HC_RX_TICKS_8 0x00006b0c
5437#define BCE_HC_RX_TICKS_8_VALUE (0x3ffL<<0)
5438#define BCE_HC_RX_TICKS_8_INT (0x3ffL<<16)
5439
5440#define BCE_HC_TX_TICKS_8 0x00006b10
5441#define BCE_HC_TX_TICKS_8_VALUE (0x3ffL<<0)
5442#define BCE_HC_TX_TICKS_8_INT (0x3ffL<<16)
5443
5444#define BCE_HC_COM_TICKS_8 0x00006b14
5445#define BCE_HC_COM_TICKS_8_VALUE (0x3ffL<<0)
5446#define BCE_HC_COM_TICKS_8_INT (0x3ffL<<16)
5447
5448#define BCE_HC_CMD_TICKS_8 0x00006b18
5449#define BCE_HC_CMD_TICKS_8_VALUE (0x3ffL<<0)
5450#define BCE_HC_CMD_TICKS_8_INT (0x3ffL<<16)
5451
5452#define BCE_HC_PERIODIC_TICKS_8 0x00006b1c
5453#define BCE_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
5454#define BCE_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
5455
5456
3966/*
3967 * txp_reg definition
3968 * offset: 0x40000
3969 */
3970#define BCE_TXP_CPU_MODE 0x00045000
3971#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0)
3972#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1)
3973#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)

--- 40 unchanged lines hidden (view full) ---

4014#define BCE_TXP_CPU_DATA_ACCESS 0x00045024
4015#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028
4016#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
4017#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
4018#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034
4019#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4020#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4021
5457/*
5458 * txp_reg definition
5459 * offset: 0x40000
5460 */
5461#define BCE_TXP_CPU_MODE 0x00045000
5462#define BCE_TXP_CPU_MODE_LOCAL_RST (1L<<0)
5463#define BCE_TXP_CPU_MODE_STEP_ENA (1L<<1)
5464#define BCE_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)

--- 40 unchanged lines hidden (view full) ---

5505#define BCE_TXP_CPU_DATA_ACCESS 0x00045024
5506#define BCE_TXP_CPU_INTERRUPT_ENABLE 0x00045028
5507#define BCE_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
5508#define BCE_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
5509#define BCE_TXP_CPU_HW_BREAKPOINT 0x00045034
5510#define BCE_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5511#define BCE_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5512
4022#define BCE_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
4023#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4024#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4025#define BCE_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4026#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4027#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4028#define BCE_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4029
4030#define BCE_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
4031#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4032#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4033#define BCE_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4034#define BCE_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4035
4036#define BCE_TXP_CPU_REG_FILE 0x00045200
4037#define BCE_TXP_FTQ_DATA 0x000453c0
4038#define BCE_TXP_FTQ_CMD 0x000453f8
4039#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
4040#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10)
4041#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
4042#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
4043#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25)

--- 64 unchanged lines hidden (view full) ---

4108#define BCE_TPAT_CPU_INSTRUCTION 0x00085020
4109#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024
4110#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
4111#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
4112#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
4113#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034
4114#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4115#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5513#define BCE_TXP_CPU_REG_FILE 0x00045200
5514#define BCE_TXP_FTQ_DATA 0x000453c0
5515#define BCE_TXP_FTQ_CMD 0x000453f8
5516#define BCE_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
5517#define BCE_TXP_FTQ_CMD_WR_TOP (1L<<10)
5518#define BCE_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
5519#define BCE_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
5520#define BCE_TXP_FTQ_CMD_SFT_RESET (1L<<25)

--- 64 unchanged lines hidden (view full) ---

5585#define BCE_TPAT_CPU_INSTRUCTION 0x00085020
5586#define BCE_TPAT_CPU_DATA_ACCESS 0x00085024
5587#define BCE_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
5588#define BCE_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
5589#define BCE_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
5590#define BCE_TPAT_CPU_HW_BREAKPOINT 0x00085034
5591#define BCE_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5592#define BCE_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4116
4117#define BCE_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
4118#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4119#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4120#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4121#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4122#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4123#define BCE_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4124
4125#define BCE_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
4126#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4127#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4128#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4129#define BCE_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4130
4131#define BCE_TPAT_CPU_REG_FILE 0x00085200
4132#define BCE_TPAT_FTQ_DATA 0x000853c0
4133#define BCE_TPAT_FTQ_CMD 0x000853f8
4134#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
4135#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10)
4136#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
4137#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
4138#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25)

--- 65 unchanged lines hidden (view full) ---

4204#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024
4205#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
4206#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
4207#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
4208#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034
4209#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4210#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4211
5593#define BCE_TPAT_CPU_REG_FILE 0x00085200
5594#define BCE_TPAT_FTQ_DATA 0x000853c0
5595#define BCE_TPAT_FTQ_CMD 0x000853f8
5596#define BCE_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
5597#define BCE_TPAT_FTQ_CMD_WR_TOP (1L<<10)
5598#define BCE_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
5599#define BCE_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
5600#define BCE_TPAT_FTQ_CMD_SFT_RESET (1L<<25)

--- 65 unchanged lines hidden (view full) ---

5666#define BCE_RXP_CPU_DATA_ACCESS 0x000c5024
5667#define BCE_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
5668#define BCE_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
5669#define BCE_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
5670#define BCE_RXP_CPU_HW_BREAKPOINT 0x000c5034
5671#define BCE_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5672#define BCE_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5673
4212#define BCE_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
4213#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4214#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4215#define BCE_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4216#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4217#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4218#define BCE_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4219
4220#define BCE_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
4221#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4222#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4223#define BCE_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4224#define BCE_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4225
4226#define BCE_RXP_CPU_REG_FILE 0x000c5200
4227#define BCE_RXP_CFTQ_DATA 0x000c5380
4228#define BCE_RXP_CFTQ_CMD 0x000c53b8
4229#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
4230#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10)
4231#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
4232#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
4233#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25)

--- 86 unchanged lines hidden (view full) ---

4320#define BCE_COM_CPU_DATA_ACCESS 0x00105024
4321#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028
4322#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c
4323#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
4324#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034
4325#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4326#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4327
5674#define BCE_RXP_CPU_REG_FILE 0x000c5200
5675#define BCE_RXP_CFTQ_DATA 0x000c5380
5676#define BCE_RXP_CFTQ_CMD 0x000c53b8
5677#define BCE_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
5678#define BCE_RXP_CFTQ_CMD_WR_TOP (1L<<10)
5679#define BCE_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
5680#define BCE_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
5681#define BCE_RXP_CFTQ_CMD_SFT_RESET (1L<<25)

--- 86 unchanged lines hidden (view full) ---

5768#define BCE_COM_CPU_DATA_ACCESS 0x00105024
5769#define BCE_COM_CPU_INTERRUPT_ENABLE 0x00105028
5770#define BCE_COM_CPU_INTERRUPT_VECTOR 0x0010502c
5771#define BCE_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
5772#define BCE_COM_CPU_HW_BREAKPOINT 0x00105034
5773#define BCE_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5774#define BCE_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5775
4328#define BCE_COM_CPU_DEBUG_VECT_PEEK 0x00105038
4329#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4330#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4331#define BCE_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4332#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4333#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4334#define BCE_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4335
4336#define BCE_COM_CPU_LAST_BRANCH_ADDR 0x00105048
4337#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4338#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4339#define BCE_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4340#define BCE_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4341
4342#define BCE_COM_CPU_REG_FILE 0x00105200
4343#define BCE_COM_COMXQ_FTQ_DATA 0x00105340
4344#define BCE_COM_COMXQ_FTQ_CMD 0x00105378
4345#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4346#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
4347#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4348#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4349#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 107 unchanged lines hidden (view full) ---

4457#define BCE_CP_CPU_DATA_ACCESS 0x00185024
4458#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028
4459#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c
4460#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
4461#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034
4462#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4463#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4464
5776#define BCE_COM_CPU_REG_FILE 0x00105200
5777#define BCE_COM_COMXQ_FTQ_DATA 0x00105340
5778#define BCE_COM_COMXQ_FTQ_CMD 0x00105378
5779#define BCE_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
5780#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
5781#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5782#define BCE_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5783#define BCE_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 107 unchanged lines hidden (view full) ---

5891#define BCE_CP_CPU_DATA_ACCESS 0x00185024
5892#define BCE_CP_CPU_INTERRUPT_ENABLE 0x00185028
5893#define BCE_CP_CPU_INTERRUPT_VECTOR 0x0018502c
5894#define BCE_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
5895#define BCE_CP_CPU_HW_BREAKPOINT 0x00185034
5896#define BCE_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5897#define BCE_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5898
4465#define BCE_CP_CPU_DEBUG_VECT_PEEK 0x00185038
4466#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4467#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4468#define BCE_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4469#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4470#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4471#define BCE_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4472
4473#define BCE_CP_CPU_LAST_BRANCH_ADDR 0x00185048
4474#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4475#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4476#define BCE_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4477#define BCE_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4478
4479#define BCE_CP_CPU_REG_FILE 0x00185200
4480#define BCE_CP_CPQ_FTQ_DATA 0x001853c0
4481#define BCE_CP_CPQ_FTQ_CMD 0x001853f8
4482#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4483#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
4484#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4485#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4486#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 75 unchanged lines hidden (view full) ---

4562#define BCE_MCP_CPU_DATA_ACCESS 0x00145024
4563#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028
4564#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
4565#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
4566#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034
4567#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
4568#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
4569
5899#define BCE_CP_CPU_REG_FILE 0x00185200
5900#define BCE_CP_CPQ_FTQ_DATA 0x001853c0
5901#define BCE_CP_CPQ_FTQ_CMD 0x001853f8
5902#define BCE_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
5903#define BCE_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
5904#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5905#define BCE_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5906#define BCE_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 75 unchanged lines hidden (view full) ---

5982#define BCE_MCP_CPU_DATA_ACCESS 0x00145024
5983#define BCE_MCP_CPU_INTERRUPT_ENABLE 0x00145028
5984#define BCE_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
5985#define BCE_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
5986#define BCE_MCP_CPU_HW_BREAKPOINT 0x00145034
5987#define BCE_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
5988#define BCE_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
5989
4570#define BCE_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
4571#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
4572#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
4573#define BCE_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
4574#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
4575#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
4576#define BCE_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
4577
4578#define BCE_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
4579#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
4580#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
4581#define BCE_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
4582#define BCE_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
4583
4584#define BCE_MCP_CPU_REG_FILE 0x00145200
4585#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0
4586#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8
4587#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
4588#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
4589#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
4590#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
4591#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 31 unchanged lines hidden (view full) ---

4623/* Begin firmware definitions. */
4624/****************************************************************************/
4625/* The following definitions refer to pre-defined locations in processor */
4626/* memory space which allows the driver to enable particular functionality */
4627/* within the firmware or read specfic information about the running */
4628/* firmware. */
4629/****************************************************************************/
4630
5990#define BCE_MCP_CPU_REG_FILE 0x00145200
5991#define BCE_MCP_MCPQ_FTQ_DATA 0x001453c0
5992#define BCE_MCP_MCPQ_FTQ_CMD 0x001453f8
5993#define BCE_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
5994#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
5995#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
5996#define BCE_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
5997#define BCE_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)

--- 31 unchanged lines hidden (view full) ---

6029/* Begin firmware definitions. */
6030/****************************************************************************/
6031/* The following definitions refer to pre-defined locations in processor */
6032/* memory space which allows the driver to enable particular functionality */
6033/* within the firmware or read specfic information about the running */
6034/* firmware. */
6035/****************************************************************************/
6036
4631/*
6037/*
4632 * Perfect match control register.
6038 * Perfect match control register.
4633 * 0 = Default. All received unicst packets matching MAC address
6039 * 0 = Default. All received unicst packets matching MAC address
4634 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
4635 * 0, all other perfect match registers are reserved.
6040 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
6041 * 0, all other perfect match registers are reserved.
4636 * 1 = All received unicast packets matching MAC address
6042 * 1 = All received unicast packets matching MAC address
4637 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
4638 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc.
4639 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register
4640 * are sent to receive queue 0.
4641 */
4642#define BCE_RXP_PM_CTRL 0x0e00d0
4643
4644/*
4645 * This firmware statistic records the number of frames that
4646 * were dropped because there were no buffers available in the
4647 * receive chain.
4648 */
6043 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
6044 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc.
6045 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register
6046 * are sent to receive queue 0.
6047 */
6048#define BCE_RXP_PM_CTRL 0x0e00d0
6049
6050/*
6051 * This firmware statistic records the number of frames that
6052 * were dropped because there were no buffers available in the
6053 * receive chain.
6054 */
4649#define BCE_COM_NO_BUFFERS 0x120084
6055#define BCE_COM_NO_BUFFERS 0x120084
4650/****************************************************************************/
4651/* End firmware definitions. */
4652/****************************************************************************/
4653
4654#define NUM_MC_HASH_REGISTERS 8
4655
4656
4657/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */

--- 51 unchanged lines hidden (view full) ---

4709
4710#define RX_COPY_THRESH 92
4711
4712#define DMA_READ_CHANS 5
4713#define DMA_WRITE_CHANS 3
4714
4715/* Use the natural page size of the host CPU. */
4716/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
6056/****************************************************************************/
6057/* End firmware definitions. */
6058/****************************************************************************/
6059
6060#define NUM_MC_HASH_REGISTERS 8
6061
6062
6063/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */

--- 51 unchanged lines hidden (view full) ---

6115
6116#define RX_COPY_THRESH 92
6117
6118#define DMA_READ_CHANS 5
6119#define DMA_WRITE_CHANS 3
6120
6121/* Use the natural page size of the host CPU. */
6122/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4717#define BCM_PAGE_BITS PAGE_SHIFT
6123#define BCM_PAGE_BITS PAGE_SHIFT
4718#define BCM_PAGE_SIZE PAGE_SIZE
4719#define BCM_PAGE_MASK (BCM_PAGE_SIZE - 1)
4720#define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) >> BCM_PAGE_BITS)
4721
6124#define BCM_PAGE_SIZE PAGE_SIZE
6125#define BCM_PAGE_MASK (BCM_PAGE_SIZE - 1)
6126#define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) >> BCM_PAGE_BITS)
6127
4722/*
4723 * Page count must remain a power of 2 for all
4724 * of the math to work correctly.
6128/*
6129 * Page count must remain a power of 2 for all
6130 * of the math to work correctly.
4725 */
4726#define TX_PAGES 2
4727#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4728#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4729#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4730#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4731#define MAX_TX_BD (TOTAL_TX_BD - 1)
4732
4733#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4734 (USABLE_TX_BD_PER_PAGE - 1)) ? \
4735 (x) + 2 : (x) + 1
4736
4737#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4738
4739#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4740#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4741
6131 */
6132#define TX_PAGES 2
6133#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
6134#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
6135#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
6136#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
6137#define MAX_TX_BD (TOTAL_TX_BD - 1)
6138
6139#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
6140 (USABLE_TX_BD_PER_PAGE - 1)) ? \
6141 (x) + 2 : (x) + 1
6142
6143#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
6144
6145#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
6146#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
6147
4742/*
4743 * Page count must remain a power of 2 for all
4744 * of the math to work correctly.
6148/*
6149 * Page count must remain a power of 2 for all
6150 * of the math to work correctly.
4745 */
4746#define RX_PAGES 2
4747#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4748#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4749#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4750#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4751#define MAX_RX_BD (TOTAL_RX_BD - 1)
4752

--- 46 unchanged lines hidden (view full) ---

4799
4800#define MAX_CID_CNT 0x4000
4801#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
4802#define INVALID_CID_ADDR 0xffffffff
4803
4804#define TX_CID 16
4805#define RX_CID 0
4806
6151 */
6152#define RX_PAGES 2
6153#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
6154#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
6155#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
6156#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
6157#define MAX_RX_BD (TOTAL_RX_BD - 1)
6158

--- 46 unchanged lines hidden (view full) ---

6205
6206#define MAX_CID_CNT 0x4000
6207#define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
6208#define INVALID_CID_ADDR 0xffffffff
6209
6210#define TX_CID 16
6211#define RX_CID 0
6212
4807#define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
4808#define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
4809
4810/****************************************************************************/
4811/* BCE Processor Firmwware Load Definitions */
4812/****************************************************************************/
4813
4814struct cpu_reg {
4815 u32 mode;
4816 u32 mode_value_halt;
4817 u32 mode_value_sstep;

--- 103 unchanged lines hidden (view full) ---

4921#define BCE_MAX_STD_MTU 1500
4922#define BCE_MAX_STD_ETHER_MTU 1518
4923#define BCE_MAX_STD_ETHER_MTU_VLAN 1522
4924
4925#define BCE_MAX_JUMBO_MTU 9000
4926#define BCE_MAX_JUMBO_ETHER_MTU 9018
4927#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022
4928
6213/****************************************************************************/
6214/* BCE Processor Firmwware Load Definitions */
6215/****************************************************************************/
6216
6217struct cpu_reg {
6218 u32 mode;
6219 u32 mode_value_halt;
6220 u32 mode_value_sstep;

--- 103 unchanged lines hidden (view full) ---

6324#define BCE_MAX_STD_MTU 1500
6325#define BCE_MAX_STD_ETHER_MTU 1518
6326#define BCE_MAX_STD_ETHER_MTU_VLAN 1522
6327
6328#define BCE_MAX_JUMBO_MTU 9000
6329#define BCE_MAX_JUMBO_ETHER_MTU 9018
6330#define BCE_MAX_JUMBO_ETHER_MTU_VLAN 9022
6331
6332// #define BCE_MAX_MTU ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN /* 9022 */
4929
4930/****************************************************************************/
4931/* BCE Device State Data Structure */
4932/****************************************************************************/
4933
4934#define BCE_STATUS_BLK_SZ sizeof(struct status_block)
4935#define BCE_STATS_BLK_SZ sizeof(struct statistics_block)
4936#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE

--- 8 unchanged lines hidden (view full) ---

4945 u_int8_t bce_unit; /* Interface number */
4946 struct resource *bce_res_mem; /* Device resource handle */
4947 struct ifmedia bce_ifmedia; /* TBI media info */
4948 bus_space_tag_t bce_btag; /* Device bus tag */
4949 bus_space_handle_t bce_bhandle; /* Device bus handle */
4950 vm_offset_t bce_vhandle; /* Device virtual memory handle */
4951 struct resource *bce_res_irq; /* IRQ Resource Handle */
4952 struct mtx bce_mtx; /* Mutex */
6333
6334/****************************************************************************/
6335/* BCE Device State Data Structure */
6336/****************************************************************************/
6337
6338#define BCE_STATUS_BLK_SZ sizeof(struct status_block)
6339#define BCE_STATS_BLK_SZ sizeof(struct statistics_block)
6340#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE

--- 8 unchanged lines hidden (view full) ---

6349 u_int8_t bce_unit; /* Interface number */
6350 struct resource *bce_res_mem; /* Device resource handle */
6351 struct ifmedia bce_ifmedia; /* TBI media info */
6352 bus_space_tag_t bce_btag; /* Device bus tag */
6353 bus_space_handle_t bce_bhandle; /* Device bus handle */
6354 vm_offset_t bce_vhandle; /* Device virtual memory handle */
6355 struct resource *bce_res_irq; /* IRQ Resource Handle */
6356 struct mtx bce_mtx; /* Mutex */
4953 void *bce_intrhand; /* Interrupt handler */
4954
6357
6358 /* Interrupt handler. */
6359 driver_intr_t *bce_intr;
6360 void *bce_intrhand;
6361 int bce_irq_rid;
6362 int bce_msi_count;
6363
4955 /* ASIC Chip ID. */
4956 u32 bce_chipid;
4957
4958 /* General controller flags. */
4959 u32 bce_flags;
4960#define BCE_PCIX_FLAG 0x00000001
4961#define BCE_PCI_32BIT_FLAG 0x00000002
4962#define BCE_ONE_TDMA_FLAG 0x00000004 /* Deprecated */
4963#define BCE_NO_WOL_FLAG 0x00000008
4964#define BCE_USING_DAC_FLAG 0x00000010
4965#define BCE_USING_MSI_FLAG 0x00000020
4966#define BCE_MFW_ENABLE_FLAG 0x00000040
6364 /* ASIC Chip ID. */
6365 u32 bce_chipid;
6366
6367 /* General controller flags. */
6368 u32 bce_flags;
6369#define BCE_PCIX_FLAG 0x00000001
6370#define BCE_PCI_32BIT_FLAG 0x00000002
6371#define BCE_ONE_TDMA_FLAG 0x00000004 /* Deprecated */
6372#define BCE_NO_WOL_FLAG 0x00000008
6373#define BCE_USING_DAC_FLAG 0x00000010
6374#define BCE_USING_MSI_FLAG 0x00000020
6375#define BCE_MFW_ENABLE_FLAG 0x00000040
6376#define BCE_ONE_SHOT_MSI_FLAG 0x00000080
6377#define BCE_USING_MSIX_FLAG 0x00000100
6378#define BCE_PCIE_FLAG 0x00000200
4967
6379
6380 /* Controller capability flags. */
6381 u32 bce_cap_flags;
6382#define BCE_MSI_CAPABLE_FLAG 0x00000001
6383#define BCE_MSIX_CAPABLE_FLAG 0x00000002
6384#define BCE_PCIE_CAPABLE_FLAG 0x00000004
6385#define BCE_PCIX_CAPABLE_FLAG 0x00000008
6386
4968 /* PHY specific flags. */
4969 u32 bce_phy_flags;
4970#define BCE_PHY_SERDES_FLAG 0x00000001
4971#define BCE_PHY_CRC_FIX_FLAG 0x00000002
4972#define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004
4973#define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008
4974#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300
4975#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100
4976#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200
4977
4978 /* Values that need to be shared with the PHY driver. */
4979 u32 bce_shared_hw_cfg;
4980 u32 bce_port_hw_cfg;
4981
4982 bus_addr_t max_bus_addr;
4983 u16 bus_speed_mhz; /* PCI bus speed */
6387 /* PHY specific flags. */
6388 u32 bce_phy_flags;
6389#define BCE_PHY_SERDES_FLAG 0x00000001
6390#define BCE_PHY_CRC_FIX_FLAG 0x00000002
6391#define BCE_PHY_PARALLEL_DETECT_FLAG 0x00000004
6392#define BCE_PHY_2_5G_CAPABLE_FLAG 0x00000008
6393#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300
6394#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100
6395#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200
6396
6397 /* Values that need to be shared with the PHY driver. */
6398 u32 bce_shared_hw_cfg;
6399 u32 bce_port_hw_cfg;
6400
6401 bus_addr_t max_bus_addr;
6402 u16 bus_speed_mhz; /* PCI bus speed */
6403 u16 link_width; /* PCIe link width */
6404 u16 link_speed; /* PCIe link speed */
4984 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */
4985 u32 bce_flash_size; /* Flash NVRAM size */
4986 u32 bce_shmem_base; /* Shared Memory base address */
4987 char * bce_name; /* Name string */
4988
4989 /* Tracks the version of bootcode firmware. */
4990 u32 bce_fw_ver;
4991

--- 32 unchanged lines hidden (view full) ---

5024 u16 bce_cmd_ticks;
5025 u32 bce_stats_ticks;
5026
5027 /* The address of the integrated PHY on the MII bus. */
5028 int bce_phy_addr;
5029
5030 /* The device handle for the MII bus child device. */
5031 device_t bce_miibus;
6405 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */
6406 u32 bce_flash_size; /* Flash NVRAM size */
6407 u32 bce_shmem_base; /* Shared Memory base address */
6408 char * bce_name; /* Name string */
6409
6410 /* Tracks the version of bootcode firmware. */
6411 u32 bce_fw_ver;
6412

--- 32 unchanged lines hidden (view full) ---

6445 u16 bce_cmd_ticks;
6446 u32 bce_stats_ticks;
6447
6448 /* The address of the integrated PHY on the MII bus. */
6449 int bce_phy_addr;
6450
6451 /* The device handle for the MII bus child device. */
6452 device_t bce_miibus;
5032
6453
5033 /* Driver maintained TX chain pointers and byte counter. */
5034 u16 rx_prod;
5035 u16 rx_cons;
5036 u32 rx_prod_bseq; /* Counts the bytes used. */
5037 u16 tx_prod;
5038 u16 tx_cons;
5039 u32 tx_prod_bseq; /* Counts the bytes used. */
5040 u16 pg_prod;

--- 38 unchanged lines hidden (view full) ---

5079 bus_dma_tag_t pg_bd_chain_tag;
5080 bus_dmamap_t pg_bd_chain_map[PG_PAGES];
5081 struct rx_bd *pg_bd_chain[PG_PAGES];
5082 bus_addr_t pg_bd_chain_paddr[PG_PAGES];
5083
5084 /* H/W maintained status block. */
5085 bus_dma_tag_t status_tag;
5086 bus_dmamap_t status_map;
6454 /* Driver maintained TX chain pointers and byte counter. */
6455 u16 rx_prod;
6456 u16 rx_cons;
6457 u32 rx_prod_bseq; /* Counts the bytes used. */
6458 u16 tx_prod;
6459 u16 tx_cons;
6460 u32 tx_prod_bseq; /* Counts the bytes used. */
6461 u16 pg_prod;

--- 38 unchanged lines hidden (view full) ---

6500 bus_dma_tag_t pg_bd_chain_tag;
6501 bus_dmamap_t pg_bd_chain_map[PG_PAGES];
6502 struct rx_bd *pg_bd_chain[PG_PAGES];
6503 bus_addr_t pg_bd_chain_paddr[PG_PAGES];
6504
6505 /* H/W maintained status block. */
6506 bus_dma_tag_t status_tag;
6507 bus_dmamap_t status_map;
5087 struct status_block *status_block; /* virtual address */
5088 bus_addr_t status_block_paddr; /* Physical address */
6508 struct status_block *status_block; /* Virtual address */
6509 bus_addr_t status_block_paddr; /* Physical address */
5089
5090 /* Driver maintained status block values. */
5091 u16 last_status_idx;
5092 u16 hw_rx_cons;
5093 u16 hw_tx_cons;
5094
5095 /* H/W maintained statistics block. */
5096 bus_dma_tag_t stats_tag;
5097 bus_dmamap_t stats_map;
5098 struct statistics_block *stats_block; /* Virtual address */
5099 bus_addr_t stats_block_paddr; /* Physical address */
5100
6510
6511 /* Driver maintained status block values. */
6512 u16 last_status_idx;
6513 u16 hw_rx_cons;
6514 u16 hw_tx_cons;
6515
6516 /* H/W maintained statistics block. */
6517 bus_dma_tag_t stats_tag;
6518 bus_dmamap_t stats_map;
6519 struct statistics_block *stats_block; /* Virtual address */
6520 bus_addr_t stats_block_paddr; /* Physical address */
6521
6522 /* H/W maintained context block. */
6523 int ctx_pages;
6524 bus_dma_tag_t ctx_tag;
6525 /* DRC - Fix hard coded value. */
6526 bus_dmamap_t ctx_map[4];
6527 void *ctx_block[4]; /* Virtual address */
6528 bus_addr_t ctx_paddr[4]; /* Physical address */
6529
5101 /* Bus tag for RX/TX mbufs. */
5102 bus_dma_tag_t rx_mbuf_tag;
5103 bus_dma_tag_t tx_mbuf_tag;
5104 bus_dma_tag_t pg_mbuf_tag;
5105
5106 /* S/W maintained mbuf TX chain structure. */
5107 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
5108 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];

--- 75 unchanged lines hidden (view full) ---

5184 u32 com_no_buffers;
5185
5186 /* Mbuf allocation failure counter. */
5187 u32 mbuf_alloc_failed;
5188
5189 /* TX DMA mapping failure counter. */
5190 u32 tx_dma_map_failures;
5191
6530 /* Bus tag for RX/TX mbufs. */
6531 bus_dma_tag_t rx_mbuf_tag;
6532 bus_dma_tag_t tx_mbuf_tag;
6533 bus_dma_tag_t pg_mbuf_tag;
6534
6535 /* S/W maintained mbuf TX chain structure. */
6536 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
6537 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];

--- 75 unchanged lines hidden (view full) ---

6613 u32 com_no_buffers;
6614
6615 /* Mbuf allocation failure counter. */
6616 u32 mbuf_alloc_failed;
6617
6618 /* TX DMA mapping failure counter. */
6619 u32 tx_dma_map_failures;
6620
5192 u64 rx_intr_time;
6621 u32 hc_command;
5193
5194#ifdef BCE_DEBUG
5195 /* Track the number of enqueued mbufs. */
5196 int debug_tx_mbuf_alloc;
5197 int debug_rx_mbuf_alloc;
5198 int debug_pg_mbuf_alloc;
5199
5200 /* Track how many and what type of interrupts are generated. */
5201 u32 interrupts_generated;
5202 u32 interrupts_handled;
5203 u32 rx_interrupts;
5204 u32 tx_interrupts;
5205
5206 /* Track interrupt time (25MHz clock). */
6622
6623#ifdef BCE_DEBUG
6624 /* Track the number of enqueued mbufs. */
6625 int debug_tx_mbuf_alloc;
6626 int debug_rx_mbuf_alloc;
6627 int debug_pg_mbuf_alloc;
6628
6629 /* Track how many and what type of interrupts are generated. */
6630 u32 interrupts_generated;
6631 u32 interrupts_handled;
6632 u32 rx_interrupts;
6633 u32 tx_interrupts;
6634
6635 /* Track interrupt time (25MHz clock). */
6636 u64 rx_intr_time;
5207 u64 tx_intr_time;
5208
5209 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
5210 u32 rx_empty_count; /* Number of times the RX chain was empty. */
5211
5212 u32 pg_low_watermark; /* Lowest number of pages free. */
5213 u32 pg_empty_count; /* Number of times the page chain was empty. */
5214
5215 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */
5216 u32 tx_full_count; /* Number of times the TX chain was full. */
5217
5218 /* Simulated mbuf allocation failure counter. */
6637 u64 tx_intr_time;
6638
6639 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
6640 u32 rx_empty_count; /* Number of times the RX chain was empty. */
6641
6642 u32 pg_low_watermark; /* Lowest number of pages free. */
6643 u32 pg_empty_count; /* Number of times the page chain was empty. */
6644
6645 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */
6646 u32 tx_full_count; /* Number of times the TX chain was full. */
6647
6648 /* Simulated mbuf allocation failure counter. */
5219 u32 debug_mbuf_sim_alloc_failed;
5220
6649 u32 debug_mbuf_sim_alloc_failed;
6650
5221 u32 l2fhdr_status_errors;
5222 u32 unexpected_attentions;
5223 u32 lost_status_block_updates;
5224
5225 u32 requested_tso_frames; /* Number of TSO frames enqueued. */
5226#endif
5227};
5228
5229#endif /* #ifndef _BCE_H_DEFINED */
5230
6651 u32 l2fhdr_status_errors;
6652 u32 unexpected_attentions;
6653 u32 lost_status_block_updates;
6654
6655 u32 requested_tso_frames; /* Number of TSO frames enqueued. */
6656#endif
6657};
6658
6659#endif /* #ifndef _BCE_H_DEFINED */
6660