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if_bcereg.h (176448) if_bcereg.h (178132)
1/*-
1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright

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21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 176448 2008-02-22 00:46:22Z davidch $
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 178132 2008-04-11 23:10:40Z davidch $
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
35#ifdef HAVE_KERNEL_OPTION_HEADERS
36#include "opt_device_polling.h"
37#endif
38
39#include <sys/param.h>
40#include <sys/endian.h>
41#include <sys/systm.h>
42#include <sys/sockio.h>
43#include <sys/mbuf.h>
44#include <sys/malloc.h>
45#include <sys/kernel.h>
46#include <sys/module.h>

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127 "\07b6" \
128 "\06b5" \
129 "\05b4" \
130 "\04b3" \
131 "\03b2" \
132 "\02b1" \
133 "\01b0"
134
35#include <sys/param.h>
36#include <sys/endian.h>
37#include <sys/systm.h>
38#include <sys/sockio.h>
39#include <sys/mbuf.h>
40#include <sys/malloc.h>
41#include <sys/kernel.h>
42#include <sys/module.h>

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123 "\07b6" \
124 "\06b5" \
125 "\05b4" \
126 "\04b3" \
127 "\03b2" \
128 "\02b1" \
129 "\01b0"
130
131
135/****************************************************************************/
136/* Debugging macros and definitions. */
137/****************************************************************************/
138#define BCE_CP_LOAD 0x00000001
139#define BCE_CP_SEND 0x00000002
140#define BCE_CP_RECV 0x00000004
141#define BCE_CP_INTR 0x00000008
142#define BCE_CP_UNLOAD 0x00000010

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3109#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
3110#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
3111#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
3112#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
3113#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
3114#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
3115#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
3116
132/****************************************************************************/
133/* Debugging macros and definitions. */
134/****************************************************************************/
135#define BCE_CP_LOAD 0x00000001
136#define BCE_CP_SEND 0x00000002
137#define BCE_CP_RECV 0x00000004
138#define BCE_CP_INTR 0x00000008
139#define BCE_CP_UNLOAD 0x00000010

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3106#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
3107#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
3108#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
3109#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
3110#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
3111#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
3112#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
3113
3114
3117/*
3115/*
3116 * rlup_reg definition
3117 * offset: 0x2000
3118 */
3119#define BCE_RLUP_FTQ_CMD 0x000023f8
3120#define BCE_RLUP_FTQ_CTL 0x000023fc
3121#define BCE_RLUP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3122#define BCE_RLUP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3123
3124
3125
3126/*
3127 * rdma_reg definition
3128 * offset: 0x2c00
3129 */
3130#define BCE_RDMA_FTQ_CMD 0x00002ff8
3131#define BCE_RDMA_FTQ_CTL 0x00002ffc
3132#define BCE_RDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3133#define BCE_RDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3134
3135
3136
3137/*
3118 * timer_reg definition
3119 * offset: 0x4400
3120 */
3121
3122#define BCE_TIMER_COMMAND 0x00004400
3123#define BCE_TIMER_COMMAND_ENABLED (1L<<0)
3124
3125#define BCE_TIMER_STATUS 0x00004404

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3130#define BCE_TIMER_STATUS_TMR3_CNT (1L<<11)
3131#define BCE_TIMER_STATUS_TMR4_CNT (1L<<12)
3132#define BCE_TIMER_STATUS_TMR5_CNT (1L<<13)
3133
3134#define BCE_TIMER_25MHZ_FREE_RUN 0x00004448
3135
3136
3137/*
3138 * timer_reg definition
3139 * offset: 0x4400
3140 */
3141
3142#define BCE_TIMER_COMMAND 0x00004400
3143#define BCE_TIMER_COMMAND_ENABLED (1L<<0)
3144
3145#define BCE_TIMER_STATUS 0x00004404

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3150#define BCE_TIMER_STATUS_TMR3_CNT (1L<<11)
3151#define BCE_TIMER_STATUS_TMR4_CNT (1L<<12)
3152#define BCE_TIMER_STATUS_TMR5_CNT (1L<<13)
3153
3154#define BCE_TIMER_25MHZ_FREE_RUN 0x00004448
3155
3156
3157/*
3158 * tsch_reg definition
3159 * offset: 0x4c00
3160 */
3161
3162#define BCE_TSCH_FTQ_CMD 0x00004ff8
3163#define BCE_TSCH_FTQ_CTL 0x00004ffc
3164#define BCE_TSCH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3165#define BCE_TSCH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3166
3167
3168
3169/*
3138 * rbuf_reg definition
3139 * offset: 0x200000
3140 */
3141#define BCE_RBUF_COMMAND 0x00200000
3142#define BCE_RBUF_COMMAND_ENABLED (1L<<0)
3143#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
3144#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)
3145#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4)

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3421
3422#define BCE_MQ_MEM_RD_DATA1 0x00003c8c
3423#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3424
3425#define BCE_MQ_MEM_RD_DATA2 0x00003c90
3426#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
3427
3428
3170 * rbuf_reg definition
3171 * offset: 0x200000
3172 */
3173#define BCE_RBUF_COMMAND 0x00200000
3174#define BCE_RBUF_COMMAND_ENABLED (1L<<0)
3175#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
3176#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)
3177#define BCE_RBUF_COMMAND_OVER_FREE (1L<<4)

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3453
3454#define BCE_MQ_MEM_RD_DATA1 0x00003c8c
3455#define BCE_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
3456
3457#define BCE_MQ_MEM_RD_DATA2 0x00003c90
3458#define BCE_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
3459
3460
3461/*
3462 * csch_reg definition
3463 * offset: 0x4000
3464 */
3465#define BCE_CSCH_COMMAND 0x00004000
3466#define BCE_CSCH_CH_FTQ_CMD 0x000043f8
3467#define BCE_CSCH_CH_FTQ_CTL 0x000043fc
3468#define BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
3469#define BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
3429
3470
3471
3430/*
3431 * tbdr_reg definition
3432 * offset: 0x5000
3433 */
3434#define BCE_TBDR_COMMAND 0x00005000
3435#define BCE_TBDR_COMMAND_ENABLE (1L<<0)
3436#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
3437#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)

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4453#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4454#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4455#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4456
4457#define BCE_CP_SCRATCH 0x001a0000
4458
4459
4460/*
3472/*
3473 * tbdr_reg definition
3474 * offset: 0x5000
3475 */
3476#define BCE_TBDR_COMMAND 0x00005000
3477#define BCE_TBDR_COMMAND_ENABLE (1L<<0)
3478#define BCE_TBDR_COMMAND_SOFT_RST (1L<<1)
3479#define BCE_TBDR_COMMAND_MSTR_ABORT (1L<<4)

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4495#define BCE_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
4496#define BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4497#define BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4498
4499#define BCE_CP_SCRATCH 0x001a0000
4500
4501
4502/*
4503 * tas_reg definition
4504 * offset: 0x1c0000
4505 */
4506#define BCE_TAS_FTQ_CMD 0x001c03f8
4507#define BCE_TAS_FTQ_CTL 0x001c03fc
4508#define BCE_TAS_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
4509#define BCE_TAS_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
4510
4511
4512/*
4461 * mcp_reg definition
4462 * offset: 0x140000
4463 */
4464#define BCE_MCP_CPU_MODE 0x00145000
4465#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0)
4466#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1)
4467#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4468#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)

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5129 u32 com_no_buffers;
5130
5131 /* Mbuf allocation failure counter. */
5132 u32 mbuf_alloc_failed;
5133
5134 /* TX DMA mapping failure counter. */
5135 u32 tx_dma_map_failures;
5136
4513 * mcp_reg definition
4514 * offset: 0x140000
4515 */
4516#define BCE_MCP_CPU_MODE 0x00145000
4517#define BCE_MCP_CPU_MODE_LOCAL_RST (1L<<0)
4518#define BCE_MCP_CPU_MODE_STEP_ENA (1L<<1)
4519#define BCE_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
4520#define BCE_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)

--- 660 unchanged lines hidden (view full) ---

5181 u32 com_no_buffers;
5182
5183 /* Mbuf allocation failure counter. */
5184 u32 mbuf_alloc_failed;
5185
5186 /* TX DMA mapping failure counter. */
5187 u32 tx_dma_map_failures;
5188
5189 u64 rx_intr_time;
5190
5137#ifdef BCE_DEBUG
5138 /* Track the number of enqueued mbufs. */
5139 int debug_tx_mbuf_alloc;
5140 int debug_rx_mbuf_alloc;
5141 int debug_pg_mbuf_alloc;
5142
5143 /* Track how many and what type of interrupts are generated. */
5144 u32 interrupts_generated;
5145 u32 interrupts_handled;
5146 u32 rx_interrupts;
5147 u32 tx_interrupts;
5148
5149 /* Track interrupt time (25MHz clock). */
5191#ifdef BCE_DEBUG
5192 /* Track the number of enqueued mbufs. */
5193 int debug_tx_mbuf_alloc;
5194 int debug_rx_mbuf_alloc;
5195 int debug_pg_mbuf_alloc;
5196
5197 /* Track how many and what type of interrupts are generated. */
5198 u32 interrupts_generated;
5199 u32 interrupts_handled;
5200 u32 rx_interrupts;
5201 u32 tx_interrupts;
5202
5203 /* Track interrupt time (25MHz clock). */
5150 u64 rx_intr_time;
5151 u64 tx_intr_time;
5152
5153 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
5154 u32 rx_empty_count; /* Number of times the RX chain was empty. */
5155
5156 u32 pg_low_watermark; /* Lowest number of pages free. */
5157 u32 pg_empty_count; /* Number of times the page chain was empty. */
5158

--- 16 unchanged lines hidden --- 		5204 u64 tx_intr_time;
5205
5206 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
5207 u32 rx_empty_count; /* Number of times the RX chain was empty. */
5208
5209 u32 pg_low_watermark; /* Lowest number of pages free. */
5210 u32 pg_empty_count; /* Number of times the page chain was empty. */
5211

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