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if_bcereg.h (171667) if_bcereg.h (176448)
1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
1/*-
2 * Copyright (c) 2006-2007 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright

--- 12 unchanged lines hidden (view full) ---

21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 171667 2007-07-31 00:06:04Z davidch $
29 * $FreeBSD: head/sys/dev/bce/if_bcereg.h 176448 2008-02-22 00:46:22Z davidch $
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
35#ifdef HAVE_KERNEL_OPTION_HEADERS
36#include "opt_device_polling.h"
37#endif

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92#if BYTE_ORDER == BIG_ENDIAN
93#define __BIG_ENDIAN 1
94#undef __LITTLE_ENDIAN
95#else
96#undef __BIG_ENDIAN
97#define __LITTLE_ENDIAN 1
98#endif
99
30 */
31
32#ifndef _BCE_H_DEFINED
33#define _BCE_H_DEFINED
34
35#ifdef HAVE_KERNEL_OPTION_HEADERS
36#include "opt_device_polling.h"
37#endif

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92#if BYTE_ORDER == BIG_ENDIAN
93#define __BIG_ENDIAN 1
94#undef __LITTLE_ENDIAN
95#else
96#undef __BIG_ENDIAN
97#define __LITTLE_ENDIAN 1
98#endif
99
100#define BCE_DWORD_PRINTFB \
101 "\020" \
102 "\40b31" \
103 "\37b30" \
104 "\36b29" \
105 "\35b28" \
106 "\34b27" \
107 "\33b26" \
108 "\32b25" \
109 "\31b24" \
110 "\30b23" \
111 "\27b22" \
112 "\26b21" \
113 "\25b20" \
114 "\24b19" \
115 "\23b18" \
116 "\22b17" \
117 "\21b16" \
118 "\20b15" \
119 "\17b14" \
120 "\16b13" \
121 "\15b12" \
122 "\14b11" \
123 "\13b10" \
124 "\12b9" \
125 "\11b8" \
126 "\10b7" \
127 "\07b6" \
128 "\06b5" \
129 "\05b4" \
130 "\04b3" \
131 "\03b2" \
132 "\02b1" \
133 "\01b0"
134
100/****************************************************************************/
101/* Debugging macros and definitions. */
102/****************************************************************************/
103#define BCE_CP_LOAD 0x00000001
104#define BCE_CP_SEND 0x00000002
105#define BCE_CP_RECV 0x00000004
106#define BCE_CP_INTR 0x00000008
107#define BCE_CP_UNLOAD 0x00000010

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185#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
186
187#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
188#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
189#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
190
191#ifdef BCE_DEBUG
192
135/****************************************************************************/
136/* Debugging macros and definitions. */
137/****************************************************************************/
138#define BCE_CP_LOAD 0x00000001
139#define BCE_CP_SEND 0x00000002
140#define BCE_CP_RECV 0x00000004
141#define BCE_CP_INTR 0x00000008
142#define BCE_CP_UNLOAD 0x00000010

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220#define BCE_EXCESSIVE (BCE_CP_ALL | BCE_LEVEL_EXCESSIVE)
221
222#define BCE_CODE_PATH(cp) ((cp & BCE_CP_MASK) & bce_debug)
223#define BCE_MSG_LEVEL(lv) ((lv & BCE_LEVEL_MASK) <= (bce_debug & BCE_LEVEL_MASK))
224#define BCE_LOG_MSG(m) (BCE_CODE_PATH(m) && BCE_MSG_LEVEL(m))
225
226#ifdef BCE_DEBUG
227
228/*
229 * Calculate the time delta between two reads
230 * of the 25MHz free running clock.
231 */
232#define BCE_TIME_DELTA(start, end) (start > end ? (start - end) : \
233 (~start + end + 1))
234
193/* Print a message based on the logging level and code path. */
194#define DBPRINT(sc, level, format, args...) \
195 if (BCE_LOG_MSG(level)) { \
196 device_printf(sc->bce_dev, format, ## args); \
197 }
198
235/* Print a message based on the logging level and code path. */
236#define DBPRINT(sc, level, format, args...) \
237 if (BCE_LOG_MSG(level)) { \
238 device_printf(sc->bce_dev, format, ## args); \
239 }
240
241/* Runs a particular command when debugging is enabled. */
242#define DBRUN(args...) \
243 do { \
244 args; \
245 } while (0)
246
199/* Runs a particular command based on the logging level and code path. */
247/* Runs a particular command based on the logging level and code path. */
200#define DBRUN(m, args...) \
201 if (BCE_LOG_MSG(m)) { \
202 args; \
248#define DBRUNMSG(msg, args...) \
249 if (BCE_LOG_MSG(msg)) { \
250 args; \
203 }
204
205/* Runs a particular command based on the logging level. */
206#define DBRUNLV(level, args...) \
207 if (BCE_MSG_LEVEL(level)) { \
251 }
252
253/* Runs a particular command based on the logging level. */
254#define DBRUNLV(level, args...) \
255 if (BCE_MSG_LEVEL(level)) { \
208 args; \
256 args; \
209 }
210
211/* Runs a particular command based on the code path. */
257 }
258
259/* Runs a particular command based on the code path. */
212#define DBRUNCP(cp, args...) \
213 if (BCE_CODE_PATH(cp)) { \
214 args; \
260#define DBRUNCP(cp, args...) \
261 if (BCE_CODE_PATH(cp)) { \
262 args; \
215 }
216
217/* Runs a particular command based on a condition. */
263 }
264
265/* Runs a particular command based on a condition. */
218#define DBRUNIF(cond, args...) \
219 if (cond) { \
220 args; \
266#define DBRUNIF(cond, args...) \
267 if (cond) { \
268 args; \
221 }
222
223/* Needed for random() function which is only used in debugging. */
224#include <sys/random.h>
225
226/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
227#define DB_RANDOMFALSE(defects) (random() > defects)
228#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
229#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
230
231/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
232#define DB_RANDOMTRUE(defects) (random() < defects)
233#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
234#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
235
236#else
237
238#define DBPRINT(level, format, args...)
269 }
270
271/* Needed for random() function which is only used in debugging. */
272#include <sys/random.h>
273
274/* Returns FALSE in "defects" per 2^31 - 1 calls, otherwise returns TRUE. */
275#define DB_RANDOMFALSE(defects) (random() > defects)
276#define DB_OR_RANDOMFALSE(defects) || (random() > defects)
277#define DB_AND_RANDOMFALSE(defects) && (random() > ddfects)
278
279/* Returns TRUE in "defects" per 2^31 - 1 calls, otherwise returns FALSE. */
280#define DB_RANDOMTRUE(defects) (random() < defects)
281#define DB_OR_RANDOMTRUE(defects) || (random() < defects)
282#define DB_AND_RANDOMTRUE(defects) && (random() < defects)
283
284#else
285
286#define DBPRINT(level, format, args...)
239#define DBRUN(m, args...)
287#define DBRUN(args...)
288#define DBRUNMSG(msg, args...)
240#define DBRUNLV(level, args...)
241#define DBRUNCP(cp, args...)
242#define DBRUNIF(cond, args...)
243#define DB_RANDOMFALSE(defects)
244#define DB_OR_RANDOMFALSE(percent)
245#define DB_AND_RANDOMFALSE(percent)
246#define DB_RANDOMTRUE(defects)
247#define DB_OR_RANDOMTRUE(percent)

--- 494 unchanged lines hidden (view full) ---

742#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx)
743
744#define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
745#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
746#define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
747#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
748#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
749#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val)
289#define DBRUNLV(level, args...)
290#define DBRUNCP(cp, args...)
291#define DBRUNIF(cond, args...)
292#define DB_RANDOMFALSE(defects)
293#define DB_OR_RANDOMFALSE(percent)
294#define DB_AND_RANDOMFALSE(percent)
295#define DB_RANDOMTRUE(defects)
296#define DB_OR_RANDOMTRUE(percent)

--- 494 unchanged lines hidden (view full) ---

791#define BCE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->bce_mtx)
792
793#define REG_WR(sc, reg, val) bus_space_write_4(sc->bce_btag, sc->bce_bhandle, reg, val)
794#define REG_WR16(sc, reg, val) bus_space_write_2(sc->bce_btag, sc->bce_bhandle, reg, val)
795#define REG_RD(sc, reg) bus_space_read_4(sc->bce_btag, sc->bce_bhandle, reg)
796#define REG_RD_IND(sc, offset) bce_reg_rd_ind(sc, offset)
797#define REG_WR_IND(sc, offset, val) bce_reg_wr_ind(sc, offset, val)
798#define CTX_WR(sc, cid_addr, offset, val) bce_ctx_wr(sc, cid_addr, offset, val)
799#define CTX_RD(sc, cid_addr, offset) bce_ctx_rd(sc, cid_addr, offset)
750#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
751#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
752#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
753#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
754
755#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
756#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
757#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF)

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1003 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
1004 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
1005 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
1006 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
1007 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
1008 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
1009 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
1010
800#define BCE_SETBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) | (x)))
801#define BCE_CLRBIT(sc, reg, x) REG_WR(sc, reg, (REG_RD(sc, reg) & ~(x)))
802#define PCI_SETBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
803#define PCI_CLRBIT(dev, reg, x, s) pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
804
805#define BCE_STATS(x) (u_long) stats->stat_ ## x ## _lo
806#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
807#define BCE_ADDR_LO(y) ((u64) (y) & 0xFFFFFFFF)

--- 245 unchanged lines hidden (view full) ---

1053 #define L2_FHDR_STATUS_RULE_P4 (1<<5)
1054 #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
1055 #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
1056 #define L2_FHDR_STATUS_RSS_HASH (1<<8)
1057 #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
1058 #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
1059 #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
1060
1061 #define L2_FHDR_STATUS_SPLIT (1<<16)
1011 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
1012 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
1013 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
1014 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
1015 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
1016 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
1017 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
1018

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1025#elif defined(__LITTLE_ENDIAN)
1026 u16 l2_fhdr_vlan_tag;
1027 u16 l2_fhdr_pkt_len;
1028 u16 l2_fhdr_tcp_udp_xsum;
1029 u16 l2_fhdr_ip_xsum;
1030#endif
1031};
1032
1062 #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
1063 #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
1064 #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
1065 #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
1066 #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
1067 #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
1068 #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
1069

--- 6 unchanged lines hidden (view full) ---

1076#elif defined(__LITTLE_ENDIAN)
1077 u16 l2_fhdr_vlan_tag;
1078 u16 l2_fhdr_pkt_len;
1079 u16 l2_fhdr_tcp_udp_xsum;
1080 u16 l2_fhdr_ip_xsum;
1081#endif
1082};
1083
1084#define BCE_L2FHDR_PRINTFB \
1085 "\20" \
1086 "\40UDP_XSUM_ERR" \
1087 "\37b30" \
1088 "\36b29" \
1089 "\35TCP_XSUM_ERR" \
1090 "\34b27" \
1091 "\33b26" \
1092 "\32b25" \
1093 "\31b24" \
1094 "\30b23" \
1095 "\27b22" \
1096 "\26GIANT_ERR" \
1097 "\25SHORT_ERR" \
1098 "\24ALIGN_ERR" \
1099 "\23PHY_ERR" \
1100 "\22CRC_ERR" \
1101 "\21SPLIT" \
1102 "\20UDP" \
1103 "\17TCP" \
1104 "\16IP" \
1105 "\15b12" \
1106 "\14b11" \
1107 "\13b10" \
1108 "\12b09" \
1109 "\11RSS" \
1110 "\10SNAP" \
1111 "\07VLAN" \
1112 "\06P4" \
1113 "\05P3" \
1114 "\04P2"
1033
1115
1116
1034/*
1035 * l2_context definition
1036 */
1037#define BCE_L2CTX_TYPE 0x00000000
1117/*
1118 * l2_context definition
1119 */
1120#define BCE_L2CTX_TYPE 0x00000000
1038#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
1039#define BCE_L2CTX_TYPE_TYPE (0xf<<28)
1040#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
1041#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
1121#define BCE_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
1122#define BCE_L2CTX_TYPE_TYPE (0xf<<28)
1123#define BCE_L2CTX_TYPE_TYPE_EMPTY (0<<28)
1124#define BCE_L2CTX_TYPE_TYPE_L2 (1<<28)
1042
1125
1043#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
1126#define BCE_L2CTX_TX_HOST_BIDX 0x00000088
1044#define BCE_L2CTX_EST_NBD 0x00000088
1045#define BCE_L2CTX_CMD_TYPE 0x00000088
1127#define BCE_L2CTX_EST_NBD 0x00000088
1128#define BCE_L2CTX_CMD_TYPE 0x00000088
1046#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
1047#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
1048#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
1129#define BCE_L2CTX_CMD_TYPE_TYPE (0xf<<24)
1130#define BCE_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
1131#define BCE_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
1049
1132
1050#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
1133#define BCE_L2CTX_TX_HOST_BSEQ 0x00000090
1051#define BCE_L2CTX_TSCH_BSEQ 0x00000094
1052#define BCE_L2CTX_TBDR_BSEQ 0x00000098
1053#define BCE_L2CTX_TBDR_BOFF 0x0000009c
1054#define BCE_L2CTX_TBDR_BIDX 0x0000009c
1134#define BCE_L2CTX_TSCH_BSEQ 0x00000094
1135#define BCE_L2CTX_TBDR_BSEQ 0x00000098
1136#define BCE_L2CTX_TBDR_BOFF 0x0000009c
1137#define BCE_L2CTX_TBDR_BIDX 0x0000009c
1055#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
1056#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
1138#define BCE_L2CTX_TBDR_BHADDR_HI 0x000000a0
1139#define BCE_L2CTX_TBDR_BHADDR_LO 0x000000a4
1057#define BCE_L2CTX_TXP_BOFF 0x000000a8
1058#define BCE_L2CTX_TXP_BIDX 0x000000a8
1059#define BCE_L2CTX_TXP_BSEQ 0x000000ac
1060
1061
1062/*
1063 * l2_bd_chain_context definition
1064 */
1140#define BCE_L2CTX_TXP_BOFF 0x000000a8
1141#define BCE_L2CTX_TXP_BIDX 0x000000a8
1142#define BCE_L2CTX_TXP_BSEQ 0x000000ac
1143
1144
1145/*
1146 * l2_bd_chain_context definition
1147 */
1065#define BCE_L2CTX_BD_PRE_READ 0x00000000
1148#define BCE_L2CTX_BD_PRE_READ 0x00000000
1066#define BCE_L2CTX_CTX_SIZE 0x00000000
1067#define BCE_L2CTX_CTX_TYPE 0x00000000
1149#define BCE_L2CTX_CTX_SIZE 0x00000000
1150#define BCE_L2CTX_CTX_TYPE 0x00000000
1068#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
1069#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
1070#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
1071#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
1151#define BCE_L2CTX_LO_WATER_MARK_DEFAULT 32
1152#define BCE_L2CTX_LO_WATER_MARK_SCALE 4
1153#define BCE_L2CTX_LO_WATER_MARK_DIS 0
1154#define BCE_L2CTX_HI_WATER_MARK_SHIFT 4
1155#define BCE_L2CTX_HI_WATER_MARK_SCALE 16
1156#define BCE_L2CTX_WATER_MARKS_MSK 0x000000ff
1072
1157
1073#define BCE_L2CTX_HOST_BDIDX 0x00000004
1158#define BCE_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
1159#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
1160#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
1161#define BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
1162
1163#define BCE_L2CTX_HOST_BDIDX 0x00000004
1074#define BCE_L2CTX_HOST_BSEQ 0x00000008
1075#define BCE_L2CTX_NX_BSEQ 0x0000000c
1076#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010
1077#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014
1078#define BCE_L2CTX_NX_BDIDX 0x00000018
1079
1164#define BCE_L2CTX_HOST_BSEQ 0x00000008
1165#define BCE_L2CTX_NX_BSEQ 0x0000000c
1166#define BCE_L2CTX_NX_BDHADDR_HI 0x00000010
1167#define BCE_L2CTX_NX_BDHADDR_LO 0x00000014
1168#define BCE_L2CTX_NX_BDIDX 0x00000018
1169
1170/* Page Buffer Descriptor Index */
1171#define BCE_L2CTX_HOST_PG_BDIDX 0x00000044
1172/* SKB and Page Buffer Size */
1173#define BCE_L2CTX_PG_BUF_SIZE 0x00000048
1174/* Page Chain BD Context */
1175#define BCE_L2CTX_RBDC_KEY 0x0000004c
1176#define BCE_L2CTX_RBDC_JUMBO_KEY 0x3ffe
1177/* Page Chain Next BD Host Address */
1178#define BCE_L2CTX_NX_PG_BDHADDR_HI 0x00000050
1179#define BCE_L2CTX_NX_PG_BDHADDR_LO 0x00000054
1180#define BCE_L2CTX_NX_PG_BDIDX 0x00000058
1080
1181
1182
1081/*
1082 * pci_config_l definition
1083 * offset: 0000
1084 */
1085#define BCE_PCICFG_MISC_CONFIG 0x00000068
1086#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
1087#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
1088#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)

--- 1918 unchanged lines hidden (view full) ---

3007#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
3008#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
3009#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
3010#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
3011#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
3012#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
3013#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
3014
1183/*
1184 * pci_config_l definition
1185 * offset: 0000
1186 */
1187#define BCE_PCICFG_MISC_CONFIG 0x00000068
1188#define BCE_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
1189#define BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
1190#define BCE_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)

--- 1918 unchanged lines hidden (view full) ---

3109#define BCE_RPM_ACPI_DBG_BUF_W21 0x000019e4
3110#define BCE_RPM_ACPI_DBG_BUF_W22 0x000019e8
3111#define BCE_RPM_ACPI_DBG_BUF_W23 0x000019ec
3112#define BCE_RPM_ACPI_DBG_BUF_W30 0x000019f0
3113#define BCE_RPM_ACPI_DBG_BUF_W31 0x000019f4
3114#define BCE_RPM_ACPI_DBG_BUF_W32 0x000019f8
3115#define BCE_RPM_ACPI_DBG_BUF_W33 0x000019fc
3116
3117/*
3118 * timer_reg definition
3119 * offset: 0x4400
3120 */
3015
3121
3122#define BCE_TIMER_COMMAND 0x00004400
3123#define BCE_TIMER_COMMAND_ENABLED (1L<<0)
3124
3125#define BCE_TIMER_STATUS 0x00004404
3126#define BCE_TIMER_STATUS_CMP_FTQ_WAIT (1L<<0)
3127#define BCE_TIMER_STATUS_POLL_PASS_CNT (1L<<8)
3128#define BCE_TIMER_STATUS_TMR1_CNT (1L<<9)
3129#define BCE_TIMER_STATUS_TMR2_CNT (1L<<10)
3130#define BCE_TIMER_STATUS_TMR3_CNT (1L<<11)
3131#define BCE_TIMER_STATUS_TMR4_CNT (1L<<12)
3132#define BCE_TIMER_STATUS_TMR5_CNT (1L<<13)
3133
3134#define BCE_TIMER_25MHZ_FREE_RUN 0x00004448
3135
3136
3016/*
3017 * rbuf_reg definition
3018 * offset: 0x200000
3019 */
3020#define BCE_RBUF_COMMAND 0x00200000
3021#define BCE_RBUF_COMMAND_ENABLED (1L<<0)
3022#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
3023#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)

--- 1415 unchanged lines hidden (view full) ---

4439
4440#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4
4441#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8
4442
4443/****************************************************************************/
4444/* End machine generated definitions. */
4445/****************************************************************************/
4446
3137/*
3138 * rbuf_reg definition
3139 * offset: 0x200000
3140 */
3141#define BCE_RBUF_COMMAND 0x00200000
3142#define BCE_RBUF_COMMAND_ENABLED (1L<<0)
3143#define BCE_RBUF_COMMAND_FREE_INIT (1L<<1)
3144#define BCE_RBUF_COMMAND_RAM_INIT (1L<<2)

--- 1415 unchanged lines hidden (view full) ---

4560
4561#define BCE_SHM_HDR_ADDR_0 BCE_MCP_SCRATCH + 4
4562#define BCE_SHM_HDR_ADDR_1 BCE_MCP_SCRATCH + 8
4563
4564/****************************************************************************/
4565/* End machine generated definitions. */
4566/****************************************************************************/
4567
4568/****************************************************************************/
4569/* Begin firmware definitions. */
4570/****************************************************************************/
4571/* The following definitions refer to pre-defined locations in processor */
4572/* memory space which allows the driver to enable particular functionality */
4573/* within the firmware or read specfic information about the running */
4574/* firmware. */
4575/****************************************************************************/
4576
4577/*
4578 * Perfect match control register.
4579 * 0 = Default. All received unicst packets matching MAC address
4580 * BCE_EMAC_MAC_MATCH[0:1,8:9,10:11,12:13,14:15] are sent to receive queue
4581 * 0, all other perfect match registers are reserved.
4582 * 1 = All received unicast packets matching MAC address
4583 * BCE_EMAC_MAC_MATCH[0:1] are mapped to receive queue 0,
4584 * BCE_EMAC_MAC_MATCH[2:3] is mapped to receive queue 1, etc.
4585 * 2 = All received unicast packets matching any BCE_EMAC_MAC_MATCH[] register
4586 * are sent to receive queue 0.
4587 */
4588#define BCE_RXP_PM_CTRL 0x0e00d0
4589
4590/*
4591 * This firmware statistic records the number of frames that
4592 * were dropped because there were no buffers available in the
4593 * receive chain.
4594 */
4595#define BCE_COM_NO_BUFFERS 0x120084
4596/****************************************************************************/
4597/* End firmware definitions. */
4598/****************************************************************************/
4599
4447#define NUM_MC_HASH_REGISTERS 8
4448
4449
4450/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
4451#define PHY_BCM5706_PHY_ID 0x00206160
4452
4453#define PHY_ID(id) ((id) & 0xfffffff0)
4454#define PHY_REV_ID(id) ((id) & 0xf)

--- 49 unchanged lines hidden (view full) ---

4504
4505#define DMA_READ_CHANS 5
4506#define DMA_WRITE_CHANS 3
4507
4508/* Use the natural page size of the host CPU. */
4509/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4510#define BCM_PAGE_BITS PAGE_SHIFT
4511#define BCM_PAGE_SIZE PAGE_SIZE
4600#define NUM_MC_HASH_REGISTERS 8
4601
4602
4603/* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
4604#define PHY_BCM5706_PHY_ID 0x00206160
4605
4606#define PHY_ID(id) ((id) & 0xfffffff0)
4607#define PHY_REV_ID(id) ((id) & 0xf)

--- 49 unchanged lines hidden (view full) ---

4657
4658#define DMA_READ_CHANS 5
4659#define DMA_WRITE_CHANS 3
4660
4661/* Use the natural page size of the host CPU. */
4662/* XXX: This has only been tested on amd64/i386 systems using 4KB pages. */
4663#define BCM_PAGE_BITS PAGE_SHIFT
4664#define BCM_PAGE_SIZE PAGE_SIZE
4665#define BCM_PAGE_MASK (BCM_PAGE_SIZE - 1)
4666#define BCM_PAGES(x) ((((x) + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) >> BCM_PAGE_BITS)
4512
4667
4668/*
4669 * Page count must remain a power of 2 for all
4670 * of the math to work correctly.
4671 */
4513#define TX_PAGES 2
4514#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4515#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4516#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4517#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4518#define MAX_TX_BD (TOTAL_TX_BD - 1)
4519
4672#define TX_PAGES 2
4673#define TOTAL_TX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct tx_bd))
4674#define USABLE_TX_BD_PER_PAGE (TOTAL_TX_BD_PER_PAGE - 1)
4675#define TOTAL_TX_BD (TOTAL_TX_BD_PER_PAGE * TX_PAGES)
4676#define USABLE_TX_BD (USABLE_TX_BD_PER_PAGE * TX_PAGES)
4677#define MAX_TX_BD (TOTAL_TX_BD - 1)
4678
4520#define RX_PAGES 2
4521#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4522#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4523#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4524#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4525#define MAX_RX_BD (TOTAL_RX_BD - 1)
4526
4527#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4528 (USABLE_TX_BD_PER_PAGE - 1)) ? \
4529 (x) + 2 : (x) + 1
4530
4531#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4532
4679#define NEXT_TX_BD(x) (((x) & USABLE_TX_BD_PER_PAGE) == \
4680 (USABLE_TX_BD_PER_PAGE - 1)) ? \
4681 (x) + 2 : (x) + 1
4682
4683#define TX_CHAIN_IDX(x) ((x) & MAX_TX_BD)
4684
4533#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> 8)
4685#define TX_PAGE(x) (((x) & ~USABLE_TX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4534#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4535
4686#define TX_IDX(x) ((x) & USABLE_TX_BD_PER_PAGE)
4687
4688/*
4689 * Page count must remain a power of 2 for all
4690 * of the math to work correctly.
4691 */
4692#define RX_PAGES 2
4693#define TOTAL_RX_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4694#define USABLE_RX_BD_PER_PAGE (TOTAL_RX_BD_PER_PAGE - 1)
4695#define TOTAL_RX_BD (TOTAL_RX_BD_PER_PAGE * RX_PAGES)
4696#define USABLE_RX_BD (USABLE_RX_BD_PER_PAGE * RX_PAGES)
4697#define MAX_RX_BD (TOTAL_RX_BD - 1)
4698
4536#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \
4537 (USABLE_RX_BD_PER_PAGE - 1)) ? \
4538 (x) + 2 : (x) + 1
4539
4540#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4541
4699#define NEXT_RX_BD(x) (((x) & USABLE_RX_BD_PER_PAGE) == \
4700 (USABLE_RX_BD_PER_PAGE - 1)) ? \
4701 (x) + 2 : (x) + 1
4702
4703#define RX_CHAIN_IDX(x) ((x) & MAX_RX_BD)
4704
4542#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> 8)
4705#define RX_PAGE(x) (((x) & ~USABLE_RX_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4543#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4544
4706#define RX_IDX(x) ((x) & USABLE_RX_BD_PER_PAGE)
4707
4708/*
4709 * To accomodate jumbo frames, the page chain should
4710 * be 4 times larger than the receive chain.
4711 */
4712#define PG_PAGES (RX_PAGES * 4)
4713#define TOTAL_PG_BD_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct rx_bd))
4714#define USABLE_PG_BD_PER_PAGE (TOTAL_PG_BD_PER_PAGE - 1)
4715#define TOTAL_PG_BD (TOTAL_PG_BD_PER_PAGE * PG_PAGES)
4716#define USABLE_PG_BD (USABLE_PG_BD_PER_PAGE * PG_PAGES)
4717#define MAX_PG_BD (TOTAL_PG_BD - 1)
4718
4719#define NEXT_PG_BD(x) (((x) & USABLE_PG_BD_PER_PAGE) == \
4720 (USABLE_PG_BD_PER_PAGE - 1)) ? \
4721 (x) + 2 : (x) + 1
4722
4723#define PG_CHAIN_IDX(x) ((x) & MAX_PG_BD)
4724
4725#define PG_PAGE(x) (((x) & ~USABLE_PG_BD_PER_PAGE) >> (BCM_PAGE_BITS - 4))
4726#define PG_IDX(x) ((x) & USABLE_PG_BD_PER_PAGE)
4727
4545/* Context size. */
4546#define CTX_SHIFT 7
4547#define CTX_SIZE (1 << CTX_SHIFT)
4548#define CTX_MASK (CTX_SIZE - 1)
4549#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
4550#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
4551
4552#define PHY_CTX_SHIFT 6

--- 141 unchanged lines hidden (view full) ---

4694/****************************************************************************/
4695/* BCE Device State Data Structure */
4696/****************************************************************************/
4697
4698#define BCE_STATUS_BLK_SZ sizeof(struct status_block)
4699#define BCE_STATS_BLK_SZ sizeof(struct statistics_block)
4700#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4701#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4728/* Context size. */
4729#define CTX_SHIFT 7
4730#define CTX_SIZE (1 << CTX_SHIFT)
4731#define CTX_MASK (CTX_SIZE - 1)
4732#define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
4733#define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
4734
4735#define PHY_CTX_SHIFT 6

--- 141 unchanged lines hidden (view full) ---

4877/****************************************************************************/
4878/* BCE Device State Data Structure */
4879/****************************************************************************/
4880
4881#define BCE_STATUS_BLK_SZ sizeof(struct status_block)
4882#define BCE_STATS_BLK_SZ sizeof(struct statistics_block)
4883#define BCE_TX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4884#define BCE_RX_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4885#define BCE_PG_CHAIN_PAGE_SZ BCM_PAGE_SIZE
4702
4703struct bce_softc
4704{
4705 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */
4706 struct ifnet *bce_ifp; /* Interface info */
4707 device_t bce_dev; /* Parent device handle */
4708 u_int8_t bce_unit; /* Interface number */
4709 struct resource *bce_res_mem; /* Device resource handle */

--- 27 unchanged lines hidden (view full) ---

4737#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300
4738#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100
4739#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200
4740
4741 /* Values that need to be shared with the PHY driver. */
4742 u32 bce_shared_hw_cfg;
4743 u32 bce_port_hw_cfg;
4744
4886
4887struct bce_softc
4888{
4889 /* MUST start with ifnet pointer (see definition of miibus_statchg()) */
4890 struct ifnet *bce_ifp; /* Interface info */
4891 device_t bce_dev; /* Parent device handle */
4892 u_int8_t bce_unit; /* Interface number */
4893 struct resource *bce_res_mem; /* Device resource handle */

--- 27 unchanged lines hidden (view full) ---

4921#define BCE_PHY_INT_MODE_MASK_FLAG 0x00000300
4922#define BCE_PHY_INT_MODE_AUTO_POLLING_FLAG 0x00000100
4923#define BCE_PHY_INT_MODE_LINK_READY_FLAG 0x00000200
4924
4925 /* Values that need to be shared with the PHY driver. */
4926 u32 bce_shared_hw_cfg;
4927 u32 bce_port_hw_cfg;
4928
4745 bus_addr_t max_bus_addr;
4929 bus_addr_t max_bus_addr;
4746 u16 bus_speed_mhz; /* PCI bus speed */
4747 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */
4748 u32 bce_flash_size; /* Flash NVRAM size */
4749 u32 bce_shmem_base; /* Shared Memory base address */
4750 char * bce_name; /* Name string */
4751
4752 /* Tracks the version of bootcode firmware. */
4753 u32 bce_fw_ver;

--- 41 unchanged lines hidden (view full) ---

4795
4796 /* Driver maintained TX chain pointers and byte counter. */
4797 u16 rx_prod;
4798 u16 rx_cons;
4799 u32 rx_prod_bseq; /* Counts the bytes used. */
4800 u16 tx_prod;
4801 u16 tx_cons;
4802 u32 tx_prod_bseq; /* Counts the bytes used. */
4930 u16 bus_speed_mhz; /* PCI bus speed */
4931 struct flash_spec *bce_flash_info; /* Flash NVRAM settings */
4932 u32 bce_flash_size; /* Flash NVRAM size */
4933 u32 bce_shmem_base; /* Shared Memory base address */
4934 char * bce_name; /* Name string */
4935
4936 /* Tracks the version of bootcode firmware. */
4937 u32 bce_fw_ver;

--- 41 unchanged lines hidden (view full) ---

4979
4980 /* Driver maintained TX chain pointers and byte counter. */
4981 u16 rx_prod;
4982 u16 rx_cons;
4983 u32 rx_prod_bseq; /* Counts the bytes used. */
4984 u16 tx_prod;
4985 u16 tx_cons;
4986 u32 tx_prod_bseq; /* Counts the bytes used. */
4987 u16 pg_prod;
4988 u16 pg_cons;
4803
4804 int bce_link;
4805 struct callout bce_tick_callout;
4806 struct callout bce_pulse_callout;
4807
4808 int watchdog_timer; /* ticks until chip reset */
4809
4810 /* Frame size and mbuf allocation size for RX frames. */
4811 u32 max_frame_size;
4989
4990 int bce_link;
4991 struct callout bce_tick_callout;
4992 struct callout bce_pulse_callout;
4993
4994 int watchdog_timer; /* ticks until chip reset */
4995
4996 /* Frame size and mbuf allocation size for RX frames. */
4997 u32 max_frame_size;
4812 int mbuf_alloc_size;
4998 int rx_bd_mbuf_alloc_size;
4999 int pg_bd_mbuf_alloc_size;
4813
4814 /* Receive mode settings (i.e promiscuous, multicast, etc.). */
4815 u32 rx_mode;
4816
4817#ifdef DEVICE_POLLING
4818 int bce_rxcycles; /* Counter for receive polling cycles */
4819#endif
4820

--- 7 unchanged lines hidden (view full) ---

4828 bus_addr_t tx_bd_chain_paddr[TX_PAGES];
4829
4830 /* H/W maintained RX buffer descriptor chain structure. */
4831 bus_dma_tag_t rx_bd_chain_tag;
4832 bus_dmamap_t rx_bd_chain_map[RX_PAGES];
4833 struct rx_bd *rx_bd_chain[RX_PAGES];
4834 bus_addr_t rx_bd_chain_paddr[RX_PAGES];
4835
5000
5001 /* Receive mode settings (i.e promiscuous, multicast, etc.). */
5002 u32 rx_mode;
5003
5004#ifdef DEVICE_POLLING
5005 int bce_rxcycles; /* Counter for receive polling cycles */
5006#endif
5007

--- 7 unchanged lines hidden (view full) ---

5015 bus_addr_t tx_bd_chain_paddr[TX_PAGES];
5016
5017 /* H/W maintained RX buffer descriptor chain structure. */
5018 bus_dma_tag_t rx_bd_chain_tag;
5019 bus_dmamap_t rx_bd_chain_map[RX_PAGES];
5020 struct rx_bd *rx_bd_chain[RX_PAGES];
5021 bus_addr_t rx_bd_chain_paddr[RX_PAGES];
5022
5023 /* H/W maintained page buffer descriptor chain structure. */
5024 bus_dma_tag_t pg_bd_chain_tag;
5025 bus_dmamap_t pg_bd_chain_map[PG_PAGES];
5026 struct rx_bd *pg_bd_chain[PG_PAGES];
5027 bus_addr_t pg_bd_chain_paddr[PG_PAGES];
5028
4836 /* H/W maintained status block. */
4837 bus_dma_tag_t status_tag;
4838 bus_dmamap_t status_map;
4839 struct status_block *status_block; /* virtual address */
4840 bus_addr_t status_block_paddr; /* Physical address */
4841
4842 /* Driver maintained status block values. */
4843 u16 last_status_idx;

--- 4 unchanged lines hidden (view full) ---

4848 bus_dma_tag_t stats_tag;
4849 bus_dmamap_t stats_map;
4850 struct statistics_block *stats_block; /* Virtual address */
4851 bus_addr_t stats_block_paddr; /* Physical address */
4852
4853 /* Bus tag for RX/TX mbufs. */
4854 bus_dma_tag_t rx_mbuf_tag;
4855 bus_dma_tag_t tx_mbuf_tag;
5029 /* H/W maintained status block. */
5030 bus_dma_tag_t status_tag;
5031 bus_dmamap_t status_map;
5032 struct status_block *status_block; /* virtual address */
5033 bus_addr_t status_block_paddr; /* Physical address */
5034
5035 /* Driver maintained status block values. */
5036 u16 last_status_idx;

--- 4 unchanged lines hidden (view full) ---

5041 bus_dma_tag_t stats_tag;
5042 bus_dmamap_t stats_map;
5043 struct statistics_block *stats_block; /* Virtual address */
5044 bus_addr_t stats_block_paddr; /* Physical address */
5045
5046 /* Bus tag for RX/TX mbufs. */
5047 bus_dma_tag_t rx_mbuf_tag;
5048 bus_dma_tag_t tx_mbuf_tag;
5049 bus_dma_tag_t pg_mbuf_tag;
4856
4857 /* S/W maintained mbuf TX chain structure. */
4858 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
4859 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];
4860
4861 /* S/W maintained mbuf RX chain structure. */
4862 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
4863 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
4864
5050
5051 /* S/W maintained mbuf TX chain structure. */
5052 bus_dmamap_t tx_mbuf_map[TOTAL_TX_BD];
5053 struct mbuf *tx_mbuf_ptr[TOTAL_TX_BD];
5054
5055 /* S/W maintained mbuf RX chain structure. */
5056 bus_dmamap_t rx_mbuf_map[TOTAL_RX_BD];
5057 struct mbuf *rx_mbuf_ptr[TOTAL_RX_BD];
5058
4865 /* Track the number of rx_bd and tx_bd's in use. */
5059 /* S/W maintained mbuf page chain structure. */
5060 bus_dmamap_t pg_mbuf_map[TOTAL_PG_BD];
5061 struct mbuf *pg_mbuf_ptr[TOTAL_PG_BD];
5062
5063 /* Track the number of buffer descriptors in use. */
4866 u16 free_rx_bd;
4867 u16 max_rx_bd;
4868 u16 used_tx_bd;
4869 u16 max_tx_bd;
5064 u16 free_rx_bd;
5065 u16 max_rx_bd;
5066 u16 used_tx_bd;
5067 u16 max_tx_bd;
5068 u16 free_pg_bd;
5069 u16 max_pg_bd;
4870
4871 /* Provides access to hardware statistics through sysctl. */
4872 u64 stat_IfHCInOctets;
4873 u64 stat_IfHCInBadOctets;
4874 u64 stat_IfHCOutOctets;
4875 u64 stat_IfHCOutBadOctets;
4876 u64 stat_IfHCInUcastPkts;
4877 u64 stat_IfHCInMulticastPkts;

--- 53 unchanged lines hidden (view full) ---

4931 /* Mbuf allocation failure counter. */
4932 u32 mbuf_alloc_failed;
4933
4934 /* TX DMA mapping failure counter. */
4935 u32 tx_dma_map_failures;
4936
4937#ifdef BCE_DEBUG
4938 /* Track the number of enqueued mbufs. */
5070
5071 /* Provides access to hardware statistics through sysctl. */
5072 u64 stat_IfHCInOctets;
5073 u64 stat_IfHCInBadOctets;
5074 u64 stat_IfHCOutOctets;
5075 u64 stat_IfHCOutBadOctets;
5076 u64 stat_IfHCInUcastPkts;
5077 u64 stat_IfHCInMulticastPkts;

--- 53 unchanged lines hidden (view full) ---

5131 /* Mbuf allocation failure counter. */
5132 u32 mbuf_alloc_failed;
5133
5134 /* TX DMA mapping failure counter. */
5135 u32 tx_dma_map_failures;
5136
5137#ifdef BCE_DEBUG
5138 /* Track the number of enqueued mbufs. */
4939 int tx_mbuf_alloc;
4940 int rx_mbuf_alloc;
5139 int debug_tx_mbuf_alloc;
5140 int debug_rx_mbuf_alloc;
5141 int debug_pg_mbuf_alloc;
4941
5142
4942 /* Track the distribution buffer segments. */
4943 u32 rx_mbuf_segs[BCE_MAX_SEGMENTS+1];
4944
4945 /* Track how many and what type of interrupts are generated. */
4946 u32 interrupts_generated;
4947 u32 interrupts_handled;
4948 u32 rx_interrupts;
4949 u32 tx_interrupts;
4950
5143 /* Track how many and what type of interrupts are generated. */
5144 u32 interrupts_generated;
5145 u32 interrupts_handled;
5146 u32 rx_interrupts;
5147 u32 tx_interrupts;
5148
5149 /* Track interrupt time (25MHz clock). */
5150 u64 rx_intr_time;
5151 u64 tx_intr_time;
5152
4951 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
4952 u32 rx_empty_count; /* Number of times the RX chain was empty. */
5153 u32 rx_low_watermark; /* Lowest number of rx_bd's free. */
5154 u32 rx_empty_count; /* Number of times the RX chain was empty. */
5155
5156 u32 pg_low_watermark; /* Lowest number of pages free. */
5157 u32 pg_empty_count; /* Number of times the page chain was empty. */
5158
4953 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */
4954 u32 tx_full_count; /* Number of times the TX chain was full. */
5159 u32 tx_hi_watermark; /* Greatest number of tx_bd's used. */
5160 u32 tx_full_count; /* Number of times the TX chain was full. */
4955 u32 mbuf_sim_alloc_failed; /* Mbuf simulated allocation failure counter. */
5161
5162 /* Simulated mbuf allocation failure counter. */
5163 u32 debug_mbuf_sim_alloc_failed;
5164
4956 u32 l2fhdr_status_errors;
4957 u32 unexpected_attentions;
4958 u32 lost_status_block_updates;
4959
4960 u32 requested_tso_frames; /* Number of TSO frames enqueued. */
4961#endif
4962};
4963
4964#endif /* #ifndef _BCE_H_DEFINED */
4965
5165 u32 l2fhdr_status_errors;
5166 u32 unexpected_attentions;
5167 u32 lost_status_block_updates;
5168
5169 u32 requested_tso_frames; /* Number of TSO frames enqueued. */
5170#endif
5171};
5172
5173#endif /* #ifndef _BCE_H_DEFINED */
5174