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if_bce.c (247590) if_bce.c (251142)
1/*-
2 * Copyright (c) 2006-2010 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006-2010 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 247590 2013-03-01 22:05:20Z marius $");
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 251142 2013-05-30 16:09:56Z marius $");
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 * BCM5709C A1, C0

--- 329 unchanged lines hidden (view full) ---

370static void bce_dma_free (struct bce_softc *);
371static void bce_release_resources (struct bce_softc *);
372
373/****************************************************************************/
374/* BCE Firmware Synchronization and Load */
375/****************************************************************************/
376static void bce_fw_cap_init (struct bce_softc *);
377static int bce_fw_sync (struct bce_softc *, u32);
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 * BCM5709C A1, C0

--- 329 unchanged lines hidden (view full) ---

370static void bce_dma_free (struct bce_softc *);
371static void bce_release_resources (struct bce_softc *);
372
373/****************************************************************************/
374/* BCE Firmware Synchronization and Load */
375/****************************************************************************/
376static void bce_fw_cap_init (struct bce_softc *);
377static int bce_fw_sync (struct bce_softc *, u32);
378static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32);
378static void bce_load_rv2p_fw (struct bce_softc *, const u32 *, u32,
379 u32);
379static void bce_load_cpu_fw (struct bce_softc *,
380 struct cpu_reg *, struct fw_info *);
381static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
382static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
383static void bce_start_rxp_cpu (struct bce_softc *);
384static void bce_init_rxp_cpu (struct bce_softc *);
385static void bce_init_txp_cpu (struct bce_softc *);
386static void bce_init_tpat_cpu (struct bce_softc *);

--- 627 unchanged lines hidden (view full) ---

1014 /* Disabling both TX ticks and TX trips will prevent interrupts. */
1015 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1016 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1017 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1018 __FILE__, __LINE__);
1019 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1020 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1021 }
380static void bce_load_cpu_fw (struct bce_softc *,
381 struct cpu_reg *, struct fw_info *);
382static void bce_start_cpu (struct bce_softc *, struct cpu_reg *);
383static void bce_halt_cpu (struct bce_softc *, struct cpu_reg *);
384static void bce_start_rxp_cpu (struct bce_softc *);
385static void bce_init_rxp_cpu (struct bce_softc *);
386static void bce_init_txp_cpu (struct bce_softc *);
387static void bce_init_tpat_cpu (struct bce_softc *);

--- 627 unchanged lines hidden (view full) ---

1015 /* Disabling both TX ticks and TX trips will prevent interrupts. */
1016 if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1017 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1018 "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1019 __FILE__, __LINE__);
1020 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1021 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1022 }
1022
1023}
1024
1025
1026/****************************************************************************/
1027/* Device attach function. */
1028/* */
1029/* Allocates device resources, performs secondary chip identification, */
1030/* resets and initializes the hardware, and initializes driver instance */

--- 296 unchanged lines hidden (view full) ---

1327 __FILE__, __LINE__);
1328 rc = ENXIO;
1329 goto bce_attach_fail;
1330 }
1331
1332 /* Fetch the permanent Ethernet MAC address. */
1333 bce_get_mac_addr(sc);
1334
1023}
1024
1025
1026/****************************************************************************/
1027/* Device attach function. */
1028/* */
1029/* Allocates device resources, performs secondary chip identification, */
1030/* resets and initializes the hardware, and initializes driver instance */

--- 296 unchanged lines hidden (view full) ---

1327 __FILE__, __LINE__);
1328 rc = ENXIO;
1329 goto bce_attach_fail;
1330 }
1331
1332 /* Fetch the permanent Ethernet MAC address. */
1333 bce_get_mac_addr(sc);
1334
1335 /*
1336 * Trip points control how many BDs
1337 * should be ready before generating an
1338 * interrupt while ticks control how long
1339 * a BD can sit in the chain before
1340 * generating an interrupt. Set the default
1341 * values for the RX and TX chains.
1342 */
1343
1344 /* Not used for L2. */
1345 sc->bce_comp_prod_trip_int = 0;
1346 sc->bce_comp_prod_trip = 0;
1347 sc->bce_com_ticks_int = 0;
1348 sc->bce_com_ticks = 0;
1349 sc->bce_cmd_ticks_int = 0;
1350 sc->bce_cmd_ticks = 0;
1351
1352 /* Update statistics once every second. */
1353 sc->bce_stats_ticks = 1000000 & 0xffff00;
1354
1355 /* Store data needed by PHY driver for backplane applications */
1356 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1357 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1358
1359 /* Allocate DMA memory resources. */

--- 570 unchanged lines hidden (view full) ---

1930 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1931 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1932
1933 DELAY(40);
1934 }
1935
1936 DB_PRINT_PHY_REG(reg, val);
1937 return (val & 0xffff);
1335 /* Update statistics once every second. */
1336 sc->bce_stats_ticks = 1000000 & 0xffff00;
1337
1338 /* Store data needed by PHY driver for backplane applications */
1339 sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1340 sc->bce_port_hw_cfg = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1341
1342 /* Allocate DMA memory resources. */

--- 570 unchanged lines hidden (view full) ---

1913 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1914 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1915
1916 DELAY(40);
1917 }
1918
1919 DB_PRINT_PHY_REG(reg, val);
1920 return (val & 0xffff);
1938
1939}
1940
1941
1942/****************************************************************************/
1943/* PHY register write. */
1944/* */
1945/* Implements register writes on the MII bus. */
1946/* */

--- 1085 unchanged lines hidden (view full) ---

3032 /* Use a single allocation type when header splitting enabled. */
3033 if (bce_hdr_split == TRUE) {
3034 sc->rx_bd_mbuf_alloc_size = MHLEN;
3035 /* Make sure offset is 16 byte aligned for hardware. */
3036 sc->rx_bd_mbuf_align_pad =
3037 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3038 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3039 sc->rx_bd_mbuf_align_pad;
1921}
1922
1923
1924/****************************************************************************/
1925/* PHY register write. */
1926/* */
1927/* Implements register writes on the MII bus. */
1928/* */

--- 1085 unchanged lines hidden (view full) ---

3014 /* Use a single allocation type when header splitting enabled. */
3015 if (bce_hdr_split == TRUE) {
3016 sc->rx_bd_mbuf_alloc_size = MHLEN;
3017 /* Make sure offset is 16 byte aligned for hardware. */
3018 sc->rx_bd_mbuf_align_pad =
3019 roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3020 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3021 sc->rx_bd_mbuf_align_pad;
3040 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
3041 } else {
3042 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3043 ETHER_CRC_LEN) > MCLBYTES) {
3044 /* Setup for jumbo RX buffer allocations. */
3045 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3046 sc->rx_bd_mbuf_align_pad =
3047 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3048 sc->rx_bd_mbuf_data_len =

--- 13 unchanged lines hidden (view full) ---

3062// DBPRINT(sc, BCE_INFO_LOAD,
3063 DBPRINT(sc, BCE_WARN,
3064 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3065 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3066 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3067 sc->rx_bd_mbuf_align_pad);
3068
3069 DBEXIT(BCE_VERBOSE_LOAD);
3022 } else {
3023 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3024 ETHER_CRC_LEN) > MCLBYTES) {
3025 /* Setup for jumbo RX buffer allocations. */
3026 sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3027 sc->rx_bd_mbuf_align_pad =
3028 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3029 sc->rx_bd_mbuf_data_len =

--- 13 unchanged lines hidden (view full) ---

3043// DBPRINT(sc, BCE_INFO_LOAD,
3044 DBPRINT(sc, BCE_WARN,
3045 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3046 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3047 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3048 sc->rx_bd_mbuf_align_pad);
3049
3050 DBEXIT(BCE_VERBOSE_LOAD);
3070
3071}
3072
3073/****************************************************************************/
3074/* Identifies the current media type of the controller and sets the PHY */
3075/* address. */
3076/* */
3077/* Returns: */
3078/* Nothing. */

--- 400 unchanged lines hidden (view full) ---

3479 /* ToDo: How to increment debug sim_count variable here? */
3480
3481 /* Check for an error and signal the caller that an error occurred. */
3482 if (error) {
3483 *busaddr = 0;
3484 } else {
3485 *busaddr = segs->ds_addr;
3486 }
3051}
3052
3053/****************************************************************************/
3054/* Identifies the current media type of the controller and sets the PHY */
3055/* address. */
3056/* */
3057/* Returns: */
3058/* Nothing. */

--- 400 unchanged lines hidden (view full) ---

3459 /* ToDo: How to increment debug sim_count variable here? */
3460
3461 /* Check for an error and signal the caller that an error occurred. */
3462 if (error) {
3463 *busaddr = 0;
3464 } else {
3465 *busaddr = segs->ds_addr;
3466 }
3487
3488 return;
3489}
3490
3491
3492/****************************************************************************/
3493/* Allocate any DMA memory needed by the driver. */
3494/* */
3495/* Allocates DMA memory needed for the various global structures needed by */
3496/* hardware. */

--- 291 unchanged lines hidden (view full) ---

3788 "0x%jX\n", __FUNCTION__, i,
3789 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3790 }
3791
3792 /*
3793 * Create a DMA tag for RX mbufs.
3794 */
3795 if (bce_hdr_split == TRUE)
3467}
3468
3469
3470/****************************************************************************/
3471/* Allocate any DMA memory needed by the driver. */
3472/* */
3473/* Allocates DMA memory needed for the various global structures needed by */
3474/* hardware. */

--- 291 unchanged lines hidden (view full) ---

3766 "0x%jX\n", __FUNCTION__, i,
3767 (uintmax_t) sc->rx_bd_chain_paddr[i]);
3768 }
3769
3770 /*
3771 * Create a DMA tag for RX mbufs.
3772 */
3773 if (bce_hdr_split == TRUE)
3796 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3774 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3797 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3798 else
3775 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3776 else
3799 max_size = max_seg_size = MJUM9BYTES;
3800 max_segments = 1;
3777 max_size = MJUM9BYTES;
3801
3802 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3778
3779 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3803 "(max size = 0x%jX max segments = %d, max segment "
3804 "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3805 max_segments, (uintmax_t) max_seg_size);
3780 "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3806
3807 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3808 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3781
3782 if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3783 BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3809 max_size, max_segments, max_seg_size, 0, NULL, NULL,
3810 &sc->rx_mbuf_tag)) {
3784 max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3811 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3812 __FILE__, __LINE__);
3813 rc = ENOMEM;
3814 goto bce_dma_alloc_exit;
3815 }
3816
3817 /* Create DMA maps for the RX mbuf clusters. */
3818 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {

--- 49 unchanged lines hidden (view full) ---

3868 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3869 "0x%jX\n", __FUNCTION__, i,
3870 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3871 }
3872
3873 /*
3874 * Create a DMA tag for page mbufs.
3875 */
3785 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3786 __FILE__, __LINE__);
3787 rc = ENOMEM;
3788 goto bce_dma_alloc_exit;
3789 }
3790
3791 /* Create DMA maps for the RX mbuf clusters. */
3792 for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {

--- 49 unchanged lines hidden (view full) ---

3842 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3843 "0x%jX\n", __FUNCTION__, i,
3844 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3845 }
3846
3847 /*
3848 * Create a DMA tag for page mbufs.
3849 */
3876 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3877 MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3878
3879 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3850 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3880 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3881 max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3851 sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3852 1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3882 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3883 "DMA tag!\n", __FILE__, __LINE__);
3884 rc = ENOMEM;
3885 goto bce_dma_alloc_exit;
3886 }
3887
3888 /* Create DMA maps for the page mbuf clusters. */
3889 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {

--- 133 unchanged lines hidden (view full) ---

4023
4024/****************************************************************************/
4025/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
4026/* */
4027/* Returns: */
4028/* Nothing. */
4029/****************************************************************************/
4030static void
3853 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3854 "DMA tag!\n", __FILE__, __LINE__);
3855 rc = ENOMEM;
3856 goto bce_dma_alloc_exit;
3857 }
3858
3859 /* Create DMA maps for the page mbuf clusters. */
3860 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {

--- 133 unchanged lines hidden (view full) ---

3994
3995/****************************************************************************/
3996/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
3997/* */
3998/* Returns: */
3999/* Nothing. */
4000/****************************************************************************/
4001static void
4031bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
4002bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4032 u32 rv2p_code_len, u32 rv2p_proc)
4033{
4034 int i;
4035 u32 val;
4036
4037 DBENTER(BCE_VERBOSE_RESET);
4038
4039 /* Set the page size used by RV2P. */

--- 1199 unchanged lines hidden (view full) ---

5239 BCE_ADDR_HI(sc->status_block_paddr));
5240
5241 /* Program the physical address of the statistics block. */
5242 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5243 BCE_ADDR_LO(sc->stats_block_paddr));
5244 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5245 BCE_ADDR_HI(sc->stats_block_paddr));
5246
4003 u32 rv2p_code_len, u32 rv2p_proc)
4004{
4005 int i;
4006 u32 val;
4007
4008 DBENTER(BCE_VERBOSE_RESET);
4009
4010 /* Set the page size used by RV2P. */

--- 1199 unchanged lines hidden (view full) ---

5210 BCE_ADDR_HI(sc->status_block_paddr));
5211
5212 /* Program the physical address of the statistics block. */
5213 REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5214 BCE_ADDR_LO(sc->stats_block_paddr));
5215 REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5216 BCE_ADDR_HI(sc->stats_block_paddr));
5217
5247 /* Program various host coalescing parameters. */
5218 /*
5219 * Program various host coalescing parameters.
5220 * Trip points control how many BDs should be ready before generating
5221 * an interrupt while ticks control how long a BD can sit in the chain
5222 * before generating an interrupt.
5223 */
5248 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5224 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5249 (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
5225 (sc->bce_tx_quick_cons_trip_int << 16) |
5226 sc->bce_tx_quick_cons_trip);
5250 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5227 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5251 (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
5252 REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
5253 (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
5228 (sc->bce_rx_quick_cons_trip_int << 16) |
5229 sc->bce_rx_quick_cons_trip);
5254 REG_WR(sc, BCE_HC_TX_TICKS,
5255 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5256 REG_WR(sc, BCE_HC_RX_TICKS,
5257 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5230 REG_WR(sc, BCE_HC_TX_TICKS,
5231 (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5232 REG_WR(sc, BCE_HC_RX_TICKS,
5233 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5258 REG_WR(sc, BCE_HC_COM_TICKS,
5259 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
5260 REG_WR(sc, BCE_HC_CMD_TICKS,
5261 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
5262 REG_WR(sc, BCE_HC_STATS_TICKS,
5263 (sc->bce_stats_ticks & 0xffff00));
5234 REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5264 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5235 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
5236 /* Not used for L2. */
5237 REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5238 REG_WR(sc, BCE_HC_COM_TICKS, 0);
5239 REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5265
5266 /* Configure the Host Coalescing block. */
5267 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5268 BCE_HC_CONFIG_COLLECT_STATS;
5269
5270#if 0
5271 /* ToDo: Add MSI-X support. */
5272 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {

--- 276 unchanged lines hidden (view full) ---

5549
5550 DBRUN(sc->debug_pg_mbuf_alloc++);
5551 } else {
5552 /* Reuse an existing mbuf. */
5553 m_new = m;
5554 m_new->m_data = m_new->m_ext.ext_buf;
5555 }
5556
5240
5241 /* Configure the Host Coalescing block. */
5242 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5243 BCE_HC_CONFIG_COLLECT_STATS;
5244
5245#if 0
5246 /* ToDo: Add MSI-X support. */
5247 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {

--- 276 unchanged lines hidden (view full) ---

5524
5525 DBRUN(sc->debug_pg_mbuf_alloc++);
5526 } else {
5527 /* Reuse an existing mbuf. */
5528 m_new = m;
5529 m_new->m_data = m_new->m_ext.ext_buf;
5530 }
5531
5557 m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5532 m_new->m_len = MCLBYTES;
5558
5559 /* ToDo: Consider calling m_fragment() to test error handling. */
5560
5561 /* Map the mbuf cluster into device memory. */
5562 map = sc->pg_mbuf_map[*prod_idx];
5563 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5533
5534 /* ToDo: Consider calling m_fragment() to test error handling. */
5535
5536 /* Map the mbuf cluster into device memory. */
5537 map = sc->pg_mbuf_map[*prod_idx];
5538 error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5564 sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5565 &busaddr, BUS_DMA_NOWAIT);
5539 MCLBYTES, bce_dma_map_addr, &busaddr, BUS_DMA_NOWAIT);
5566
5567 /* Handle any mapping errors. */
5568 if (error) {
5569 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5570 __FILE__, __LINE__);
5571
5572 m_freem(m_new);
5573 DBRUN(sc->debug_pg_mbuf_alloc--);

--- 7 unchanged lines hidden (view full) ---

5581 /*
5582 * The page chain uses the same rx_bd data structure
5583 * as the receive chain but doesn't require a byte sequence (bseq).
5584 */
5585 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5586
5587 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr));
5588 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr));
5540
5541 /* Handle any mapping errors. */
5542 if (error) {
5543 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5544 __FILE__, __LINE__);
5545
5546 m_freem(m_new);
5547 DBRUN(sc->debug_pg_mbuf_alloc--);

--- 7 unchanged lines hidden (view full) ---

5555 /*
5556 * The page chain uses the same rx_bd data structure
5557 * as the receive chain but doesn't require a byte sequence (bseq).
5558 */
5559 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5560
5561 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr));
5562 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr));
5589 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size);
5563 pgbd->rx_bd_len = htole32(MCLBYTES);
5590 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5591
5592 /* Save the mbuf and update our counter. */
5593 sc->pg_mbuf_ptr[*prod_idx] = m_new;
5594 sc->free_pg_bd--;
5595
5596 DBRUNMSG(BCE_INSANE_RECV,
5597 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));

--- 371 unchanged lines hidden (view full) ---

5969 m_freem(sc->rx_mbuf_ptr[i]);
5970 sc->rx_mbuf_ptr[i] = NULL;
5971 DBRUN(sc->debug_rx_mbuf_alloc--);
5972 }
5973 }
5974
5975 /* Clear each RX chain page. */
5976 for (i = 0; i < sc->rx_pages; i++)
5564 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5565
5566 /* Save the mbuf and update our counter. */
5567 sc->pg_mbuf_ptr[*prod_idx] = m_new;
5568 sc->free_pg_bd--;
5569
5570 DBRUNMSG(BCE_INSANE_RECV,
5571 bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));

--- 371 unchanged lines hidden (view full) ---

5943 m_freem(sc->rx_mbuf_ptr[i]);
5944 sc->rx_mbuf_ptr[i] = NULL;
5945 DBRUN(sc->debug_rx_mbuf_alloc--);
5946 }
5947 }
5948
5949 /* Clear each RX chain page. */
5950 for (i = 0; i < sc->rx_pages; i++)
5977 if (sc->rx_bd_chain[i] != NULL) {
5951 if (sc->rx_bd_chain[i] != NULL)
5978 bzero((char *)sc->rx_bd_chain[i],
5979 BCE_RX_CHAIN_PAGE_SZ);
5952 bzero((char *)sc->rx_bd_chain[i],
5953 BCE_RX_CHAIN_PAGE_SZ);
5980 }
5981
5982 sc->free_rx_bd = sc->max_rx_bd;
5983
5984 /* Check if we lost any mbufs in the process. */
5985 DBRUNIF((sc->debug_rx_mbuf_alloc),
5986 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5987 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5988

--- 47 unchanged lines hidden (view full) ---

6036
6037 /* Setup the MQ BIN mapping for host_pg_bidx. */
6038 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6039 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6040
6041 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6042
6043 /* Configure the rx_bd and page chain mbuf cluster size. */
5954
5955 sc->free_rx_bd = sc->max_rx_bd;
5956
5957 /* Check if we lost any mbufs in the process. */
5958 DBRUNIF((sc->debug_rx_mbuf_alloc),
5959 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5960 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5961

--- 47 unchanged lines hidden (view full) ---

6009
6010 /* Setup the MQ BIN mapping for host_pg_bidx. */
6011 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6012 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6013
6014 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6015
6016 /* Configure the rx_bd and page chain mbuf cluster size. */
6044 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
6017 val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
6045 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6046
6047 /* Configure the context reserved for jumbo support. */
6048 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6049 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6050
6051 /* Point the hardware to the first page in the page chain. */
6052 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);

--- 1105 unchanged lines hidden (view full) ---

7158 * Calculate and program the hardware Ethernet MTU
7159 * size. Be generous on the receive if we have room
7160 * and allowed by the user.
7161 */
7162 if (bce_strict_rx_mtu == TRUE)
7163 ether_mtu = ifp->if_mtu;
7164 else {
7165 if (bce_hdr_split == TRUE) {
6018 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6019
6020 /* Configure the context reserved for jumbo support. */
6021 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6022 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6023
6024 /* Point the hardware to the first page in the page chain. */
6025 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);

--- 1105 unchanged lines hidden (view full) ---

7131 * Calculate and program the hardware Ethernet MTU
7132 * size. Be generous on the receive if we have room
7133 * and allowed by the user.
7134 */
7135 if (bce_strict_rx_mtu == TRUE)
7136 ether_mtu = ifp->if_mtu;
7137 else {
7138 if (bce_hdr_split == TRUE) {
7166 if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
7167 sc->pg_bd_mbuf_alloc_size))
7168 ether_mtu = sc->rx_bd_mbuf_data_len +
7169 sc->pg_bd_mbuf_alloc_size;
7139 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7140 ether_mtu = sc->rx_bd_mbuf_data_len +
7141 MCLBYTES;
7170 else
7171 ether_mtu = ifp->if_mtu;
7172 } else {
7173 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7174 ether_mtu = sc->rx_bd_mbuf_data_len;
7175 else
7176 ether_mtu = ifp->if_mtu;
7177 }

--- 11 unchanged lines hidden (view full) ---

7189 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7190 else
7191 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7192
7193 /* Program appropriate promiscuous/multicast filtering. */
7194 bce_set_rx_mode(sc);
7195
7196 if (bce_hdr_split == TRUE) {
7142 else
7143 ether_mtu = ifp->if_mtu;
7144 } else {
7145 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7146 ether_mtu = sc->rx_bd_mbuf_data_len;
7147 else
7148 ether_mtu = ifp->if_mtu;
7149 }

--- 11 unchanged lines hidden (view full) ---

7161 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7162 else
7163 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7164
7165 /* Program appropriate promiscuous/multicast filtering. */
7166 bce_set_rx_mode(sc);
7167
7168 if (bce_hdr_split == TRUE) {
7197 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
7198 __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
7199
7200 /* Init page buffer descriptor chain. */
7201 bce_init_pg_chain(sc);
7202 }
7203
7204 /* Init RX buffer descriptor chain. */
7205 bce_init_rx_chain(sc);
7206
7207 /* Init TX buffer descriptor chain. */

--- 477 unchanged lines hidden (view full) ---

7685 /* Set the tx timeout. */
7686 sc->watchdog_timer = BCE_TX_TIMEOUT;
7687
7688 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7689 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7690
7691bce_start_locked_exit:
7692 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7169 /* Init page buffer descriptor chain. */
7170 bce_init_pg_chain(sc);
7171 }
7172
7173 /* Init RX buffer descriptor chain. */
7174 bce_init_rx_chain(sc);
7175
7176 /* Init TX buffer descriptor chain. */

--- 477 unchanged lines hidden (view full) ---

7654 /* Set the tx timeout. */
7655 sc->watchdog_timer = BCE_TX_TIMEOUT;
7656
7657 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7658 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7659
7660bce_start_locked_exit:
7661 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7693 return;
7694}
7695
7696
7697/****************************************************************************/
7698/* Main transmit routine when called from another routine without a lock. */
7699/* */
7700/* Returns: */
7701/* Nothing. */

--- 784 unchanged lines hidden (view full) ---

8486 BCE_LOCK_ASSERT(sc);
8487
8488 /* Schedule the next tick. */
8489 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8490
8491 /* Update the statistics from the hardware statistics block. */
8492 bce_stats_update(sc);
8493
7662}
7663
7664
7665/****************************************************************************/
7666/* Main transmit routine when called from another routine without a lock. */
7667/* */
7668/* Returns: */
7669/* Nothing. */

--- 784 unchanged lines hidden (view full) ---

8454 BCE_LOCK_ASSERT(sc);
8455
8456 /* Schedule the next tick. */
8457 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8458
8459 /* Update the statistics from the hardware statistics block. */
8460 bce_stats_update(sc);
8461
8494 /*
8495 * ToDo: This is a safety measure. Need to re-evaluate
8496 * high level processing logic and eliminate this code.
8497 */
8498 /* Top off the receive and page chains. */
8462 /* Ensure page and RX chains get refilled in low-memory situations. */
8499 if (bce_hdr_split == TRUE)
8500 bce_fill_pg_chain(sc);
8501 bce_fill_rx_chain(sc);
8502
8503 /* Check that chip hasn't hung. */
8504 bce_watchdog(sc);
8505
8506 /* If link is up already up then we're done. */

--- 32 unchanged lines hidden (view full) ---

8539 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8540 "pending TX traffic.\n", __FUNCTION__);
8541 bce_start_locked(ifp);
8542 }
8543 }
8544
8545bce_tick_exit:
8546 DBEXIT(BCE_EXTREME_MISC);
8463 if (bce_hdr_split == TRUE)
8464 bce_fill_pg_chain(sc);
8465 bce_fill_rx_chain(sc);
8466
8467 /* Check that chip hasn't hung. */
8468 bce_watchdog(sc);
8469
8470 /* If link is up already up then we're done. */

--- 32 unchanged lines hidden (view full) ---

8503 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8504 "pending TX traffic.\n", __FUNCTION__);
8505 bce_start_locked(ifp);
8506 }
8507 }
8508
8509bce_tick_exit:
8510 DBEXIT(BCE_EXTREME_MISC);
8547 return;
8548}
8549
8550static void
8551bce_fw_cap_init(struct bce_softc *sc)
8552{
8553 u32 ack, cap, link;
8554
8555 ack = 0;

--- 3066 unchanged lines hidden (view full) ---

11622 bce_dump_pgbd(sc, 0, NULL);
11623 }
11624
11625 bce_dump_status_block(sc);
11626 bce_dump_driver_state(sc);
11627
11628 /* Call the debugger. */
11629 breakpoint();
8511}
8512
8513static void
8514bce_fw_cap_init(struct bce_softc *sc)
8515{
8516 u32 ack, cap, link;
8517
8518 ack = 0;

--- 3066 unchanged lines hidden (view full) ---

11585 bce_dump_pgbd(sc, 0, NULL);
11586 }
11587
11588 bce_dump_status_block(sc);
11589 bce_dump_driver_state(sc);
11590
11591 /* Call the debugger. */
11592 breakpoint();
11630
11631 return;
11632}
11633#endif
11593}
11594#endif