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if_bce.c (189117) if_bce.c (189325)
1/*-
2 * Copyright (c) 2006-2009 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006-2009 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 189117 2009-02-27 19:25:06Z davidch $");
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 189325 2009-03-04 00:05:40Z davidch $");
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 * BCM5709C A1, C0
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 * BCM5709C A1, C0
41 * BCM5716 C0
41 * BCM5716C C0
42 *
43 * The following controllers are not supported by this driver:
44 * BCM5706C A0, A1 (pre-production)
45 * BCM5706S A0, A1 (pre-production)
46 * BCM5708C A0, B0 (pre-production)
47 * BCM5708S A0, B0 (pre-production)
48 * BCM5709C A0 B0, B1, B2 (pre-production)
49 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production)

--- 16 unchanged lines hidden (view full) ---

66 /* 2048 = 1 in 1,048,576 */
67 /* 65536 = 1 in 32,768 */
68 /* 1048576 = 1 in 2,048 */
69 /* 268435456 = 1 in 8 */
70 /* 536870912 = 1 in 4 */
71 /* 1073741824 = 1 in 2 */
72
73 /* Controls how often the l2_fhdr frame error check will fail. */
42 *
43 * The following controllers are not supported by this driver:
44 * BCM5706C A0, A1 (pre-production)
45 * BCM5706S A0, A1 (pre-production)
46 * BCM5708C A0, B0 (pre-production)
47 * BCM5708S A0, B0 (pre-production)
48 * BCM5709C A0 B0, B1, B2 (pre-production)
49 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production)

--- 16 unchanged lines hidden (view full) ---

66 /* 2048 = 1 in 1,048,576 */
67 /* 65536 = 1 in 32,768 */
68 /* 1048576 = 1 in 2,048 */
69 /* 268435456 = 1 in 8 */
70 /* 536870912 = 1 in 4 */
71 /* 1073741824 = 1 in 2 */
72
73 /* Controls how often the l2_fhdr frame error check will fail. */
74 int bce_debug_l2fhdr_status_check = 0;
74 int l2fhdr_error_sim_control = 0;
75
76 /* Controls how often the unexpected attention check will fail. */
75
76 /* Controls how often the unexpected attention check will fail. */
77 int bce_debug_unexpected_attention = 0;
77 int unexpected_attention_sim_control = 0;
78
79 /* Controls how often to simulate an mbuf allocation failure. */
78
79 /* Controls how often to simulate an mbuf allocation failure. */
80 int bce_debug_mbuf_allocation_failure = 0;
80 int mbuf_alloc_failed_sim_control = 0;
81
82 /* Controls how often to simulate a DMA mapping failure. */
81
82 /* Controls how often to simulate a DMA mapping failure. */
83 int bce_debug_dma_map_addr_failure = 0;
83 int dma_map_addr_failed_sim_control = 0;
84
85 /* Controls how often to simulate a bootcode failure. */
84
85 /* Controls how often to simulate a bootcode failure. */
86 int bce_debug_bootcode_running_failure = 0;
86 int bootcode_running_failure_sim_control = 0;
87#endif
88
89/****************************************************************************/
90/* BCE Build Time Options */
91/****************************************************************************/
92/* #define BCE_NVRAM_WRITE_SUPPORT 1 */
93
94

--- 395 unchanged lines hidden (view full) ---

490static int bce_msi_enable = 1;
491TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
492SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
493"MSI-X|MSI|INTx selector");
494
495/* ToDo: Add tunable to enable/disable strict MTU handling. */
496/* Currently allows "loose" RX MTU checking (i.e. sets the */
497/* H/W RX MTU to the size of the largest receive buffer, or */
87#endif
88
89/****************************************************************************/
90/* BCE Build Time Options */
91/****************************************************************************/
92/* #define BCE_NVRAM_WRITE_SUPPORT 1 */
93
94

--- 395 unchanged lines hidden (view full) ---

490static int bce_msi_enable = 1;
491TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
492SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
493"MSI-X|MSI|INTx selector");
494
495/* ToDo: Add tunable to enable/disable strict MTU handling. */
496/* Currently allows "loose" RX MTU checking (i.e. sets the */
497/* H/W RX MTU to the size of the largest receive buffer, or */
498/* 2048 bytes). */
498/* 2048 bytes). This will cause a UNH failure but is more */
499/* desireable from a functional perspective. */
499
500
501/****************************************************************************/
502/* Device probe function. */
503/* */
504/* Compares the device to the driver's list of supported devices and */
505/* reports back to the OS whether this is the right driver for the device. */
506/* */

--- 83 unchanged lines hidden (view full) ---

590 } else {
591 printf("Bus (PCI%s, %s, %dMHz); ",
592 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
593 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
594 sc->bus_speed_mhz);
595 }
596
597 /* Firmware version and device features. */
500
501
502/****************************************************************************/
503/* Device probe function. */
504/* */
505/* Compares the device to the driver's list of supported devices and */
506/* reports back to the OS whether this is the right driver for the device. */
507/* */

--- 83 unchanged lines hidden (view full) ---

591 } else {
592 printf("Bus (PCI%s, %s, %dMHz); ",
593 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
594 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
595 sc->bus_speed_mhz);
596 }
597
598 /* Firmware version and device features. */
598 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
599 printf("B/C (0x%08X); Flags( ", sc->bce_bc_ver);
599#ifdef ZERO_COPY_SOCKETS
600 printf("SPLT ");
601#endif
602 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
603 printf("MFW ");
604 if (sc->bce_flags & BCE_USING_MSI_FLAG)
605 printf("MSI ");
606 if (sc->bce_flags & BCE_USING_MSIX_FLAG)

--- 234 unchanged lines hidden (view full) ---

841 (pci_get_function(sc->bce_dev) << 2));
842 else
843 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
844
845 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
846 __FUNCTION__, sc->bce_shmem_base);
847
848 /* Fetch the bootcode revision. */
600#ifdef ZERO_COPY_SOCKETS
601 printf("SPLT ");
602#endif
603 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
604 printf("MFW ");
605 if (sc->bce_flags & BCE_USING_MSI_FLAG)
606 printf("MSI ");
607 if (sc->bce_flags & BCE_USING_MSIX_FLAG)

--- 234 unchanged lines hidden (view full) ---

842 (pci_get_function(sc->bce_dev) << 2));
843 else
844 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
845
846 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
847 __FUNCTION__, sc->bce_shmem_base);
848
849 /* Fetch the bootcode revision. */
849 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
850 sc->bce_bc_ver = REG_RD_IND(sc, sc->bce_shmem_base +
850 BCE_DEV_INFO_BC_REV);
851
852 /* Check if any management firmware is running. */
853 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
854 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
855 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
856
857 /* Get PCI bus information (speed and type). */

--- 2000 unchanged lines hidden (view full) ---

2858/* Nothing. */
2859/****************************************************************************/
2860static void
2861bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2862{
2863 bus_addr_t *busaddr = arg;
2864
2865 /* Simulate a mapping failure. */
851 BCE_DEV_INFO_BC_REV);
852
853 /* Check if any management firmware is running. */
854 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
855 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
856 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
857
858 /* Get PCI bus information (speed and type). */

--- 2000 unchanged lines hidden (view full) ---

2859/* Nothing. */
2860/****************************************************************************/
2861static void
2862bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2863{
2864 bus_addr_t *busaddr = arg;
2865
2866 /* Simulate a mapping failure. */
2866 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2867 printf("bce: %s(%d): Simulating DMA mapping error.\n",
2868 __FILE__, __LINE__);
2867 DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
2869 error = ENOMEM);
2870
2871 /* Check for an error and signal the caller that an error occurred. */
2872 if (error) {
2868 error = ENOMEM);
2869
2870 /* Check for an error and signal the caller that an error occurred. */
2871 if (error) {
2873 printf("bce %s(%d): DMA mapping error! error = %d, "
2874 "nseg = %d\n", __FILE__, __LINE__, error, nseg);
2875 *busaddr = 0;
2872 *busaddr = 0;
2876 return;
2873 } else {
2874 *busaddr = segs->ds_addr;
2877 }
2878
2875 }
2876
2879 *busaddr = segs->ds_addr;
2880 return;
2881}
2882
2883
2884/****************************************************************************/
2885/* Allocate any DMA memory needed by the driver. */
2886/* */
2887/* Allocates DMA memory needed for the various global structures needed by */

--- 379 unchanged lines hidden (view full) ---

3267 * Create a DMA tag for RX mbufs.
3268 */
3269#ifdef ZERO_COPY_SOCKETS
3270 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3271 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3272#else
3273 max_size = max_seg_size = MJUM9BYTES;
3274#endif
2877 return;
2878}
2879
2880
2881/****************************************************************************/
2882/* Allocate any DMA memory needed by the driver. */
2883/* */
2884/* Allocates DMA memory needed for the various global structures needed by */

--- 379 unchanged lines hidden (view full) ---

3264 * Create a DMA tag for RX mbufs.
3265 */
3266#ifdef ZERO_COPY_SOCKETS
3267 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3268 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3269#else
3270 max_size = max_seg_size = MJUM9BYTES;
3271#endif
3272 max_segments = 1;
3275
3273
3274 DBPRINT(sc, BCE_INFO, "%s(): Creating rx_mbuf_tag (max size = 0x%jX "
3275 "max segments = %d, max segment size = 0x%jX)\n", __FUNCTION__,
3276 (uintmax_t) max_size, max_segments, (uintmax_t) max_seg_size);
3277
3276 if (bus_dma_tag_create(sc->parent_tag,
3277 1,
3278 BCE_DMA_BOUNDARY,
3279 sc->max_bus_addr,
3280 BUS_SPACE_MAXADDR,
3281 NULL, NULL,
3282 max_size,
3278 if (bus_dma_tag_create(sc->parent_tag,
3279 1,
3280 BCE_DMA_BOUNDARY,
3281 sc->max_bus_addr,
3282 BUS_SPACE_MAXADDR,
3283 NULL, NULL,
3284 max_size,
3283 1,
3285 max_segments,
3284 max_seg_size,
3285 0,
3286 NULL, NULL,
3287 &sc->rx_mbuf_tag)) {
3288 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3289 __FILE__, __LINE__);
3290 rc = ENOMEM;
3291 goto bce_dma_alloc_exit;

--- 859 unchanged lines hidden (view full) ---

4151/****************************************************************************/
4152static void
4153bce_init_cpus(struct bce_softc *sc)
4154{
4155 DBENTER(BCE_VERBOSE_RESET);
4156
4157 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4158 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3286 max_seg_size,
3287 0,
3288 NULL, NULL,
3289 &sc->rx_mbuf_tag)) {
3290 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3291 __FILE__, __LINE__);
3292 rc = ENOMEM;
3293 goto bce_dma_alloc_exit;

--- 859 unchanged lines hidden (view full) ---

4153/****************************************************************************/
4154static void
4155bce_init_cpus(struct bce_softc *sc)
4156{
4157 DBENTER(BCE_VERBOSE_RESET);
4158
4159 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4160 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4159 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
4160 RV2P_PROC1);
4161 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
4162 RV2P_PROC2);
4161
4162 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4163 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4164 sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4165 bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4166 sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4167 } else {
4168 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4169 sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4170 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4171 sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4172 }
4173
4163 } else {
4174 } else {
4164 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
4165 RV2P_PROC1);
4166 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
4167 RV2P_PROC2);
4175 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4176 sizeof(bce_rv2p_proc1), RV2P_PROC1);
4177 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4178 sizeof(bce_rv2p_proc2), RV2P_PROC2);
4168 }
4169
4170 bce_init_rxp_cpu(sc);
4171 bce_init_txp_cpu(sc);
4172 bce_init_tpat_cpu(sc);
4173 bce_init_com_cpu(sc);
4174 bce_init_cp_cpu(sc);
4175

--- 546 unchanged lines hidden (view full) ---

4722 REG_WR(sc, BCE_HC_CONFIG, val);
4723
4724 /* Clear the internal statistics counters. */
4725 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4726
4727 /* Verify that bootcode is running. */
4728 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
4729
4179 }
4180
4181 bce_init_rxp_cpu(sc);
4182 bce_init_txp_cpu(sc);
4183 bce_init_tpat_cpu(sc);
4184 bce_init_com_cpu(sc);
4185 bce_init_cp_cpu(sc);
4186

--- 546 unchanged lines hidden (view full) ---

4733 REG_WR(sc, BCE_HC_CONFIG, val);
4734
4735 /* Clear the internal statistics counters. */
4736 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4737
4738 /* Verify that bootcode is running. */
4739 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
4740
4730 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
4741 DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
4731 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
4732 __FILE__, __LINE__);
4733 reg = 0);
4734
4735 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
4736 BCE_DEV_INFO_SIGNATURE_MAGIC) {
4737 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4738 "Expected: 08%08X\n", __FILE__, __LINE__,

--- 70 unchanged lines hidden (view full) ---

4809 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4810 sc->rx_low_watermark = sc->free_rx_bd);
4811 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4812
4813 /* Check whether this is a new mbuf allocation. */
4814 if (m == NULL) {
4815
4816 /* Simulate an mbuf allocation failure. */
4742 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
4743 __FILE__, __LINE__);
4744 reg = 0);
4745
4746 if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
4747 BCE_DEV_INFO_SIGNATURE_MAGIC) {
4748 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4749 "Expected: 08%08X\n", __FILE__, __LINE__,

--- 70 unchanged lines hidden (view full) ---

4820 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4821 sc->rx_low_watermark = sc->free_rx_bd);
4822 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4823
4824 /* Check whether this is a new mbuf allocation. */
4825 if (m == NULL) {
4826
4827 /* Simulate an mbuf allocation failure. */
4817 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4818 sc->mbuf_alloc_failed++;
4819 sc->debug_mbuf_sim_alloc_failed++;
4828 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
4829 sc->mbuf_alloc_failed_count++;
4830 sc->mbuf_alloc_failed_sim_count++;
4820 rc = ENOBUFS;
4821 goto bce_get_rx_buf_exit);
4822
4823 /* This is a new mbuf allocation. */
4824#ifdef ZERO_COPY_SOCKETS
4825 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
4826#else
4827 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
4828 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
4829 else
4830 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size);
4831#endif
4832
4833 if (m_new == NULL) {
4831 rc = ENOBUFS;
4832 goto bce_get_rx_buf_exit);
4833
4834 /* This is a new mbuf allocation. */
4835#ifdef ZERO_COPY_SOCKETS
4836 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
4837#else
4838 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
4839 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
4840 else
4841 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size);
4842#endif
4843
4844 if (m_new == NULL) {
4834 sc->mbuf_alloc_failed++;
4845 sc->mbuf_alloc_failed_count++;
4835 rc = ENOBUFS;
4836 goto bce_get_rx_buf_exit;
4837 }
4838
4839 DBRUN(sc->debug_rx_mbuf_alloc++);
4840 } else {
4841 /* Reuse an existing mbuf. */
4842 m_new = m;

--- 13 unchanged lines hidden (view full) ---

4856 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
4857 segs, &nsegs, BUS_DMA_NOWAIT);
4858
4859 /* Handle any mapping errors. */
4860 if (error) {
4861 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n",
4862 __FILE__, __LINE__, error);
4863
4846 rc = ENOBUFS;
4847 goto bce_get_rx_buf_exit;
4848 }
4849
4850 DBRUN(sc->debug_rx_mbuf_alloc++);
4851 } else {
4852 /* Reuse an existing mbuf. */
4853 m_new = m;

--- 13 unchanged lines hidden (view full) ---

4867 error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
4868 segs, &nsegs, BUS_DMA_NOWAIT);
4869
4870 /* Handle any mapping errors. */
4871 if (error) {
4872 BCE_PRINTF("%s(%d): Error mapping mbuf into RX chain (%d)!\n",
4873 __FILE__, __LINE__, error);
4874
4875 sc->dma_map_addr_rx_failed_count++;
4864 m_freem(m_new);
4876 m_freem(m_new);
4877
4865 DBRUN(sc->debug_rx_mbuf_alloc--);
4866
4867 rc = ENOBUFS;
4868 goto bce_get_rx_buf_exit;
4869 }
4870
4871 /* All mbufs must map to a single segment. */
4872 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",

--- 61 unchanged lines hidden (view full) ---

4934 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
4935 sc->pg_low_watermark = sc->free_pg_bd);
4936 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
4937
4938 /* Check whether this is a new mbuf allocation. */
4939 if (m == NULL) {
4940
4941 /* Simulate an mbuf allocation failure. */
4878 DBRUN(sc->debug_rx_mbuf_alloc--);
4879
4880 rc = ENOBUFS;
4881 goto bce_get_rx_buf_exit;
4882 }
4883
4884 /* All mbufs must map to a single segment. */
4885 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",

--- 61 unchanged lines hidden (view full) ---

4947 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
4948 sc->pg_low_watermark = sc->free_pg_bd);
4949 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
4950
4951 /* Check whether this is a new mbuf allocation. */
4952 if (m == NULL) {
4953
4954 /* Simulate an mbuf allocation failure. */
4942 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4943 sc->mbuf_alloc_failed++;
4944 sc->debug_mbuf_sim_alloc_failed++;
4955 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
4956 sc->mbuf_alloc_failed_count++;
4957 sc->mbuf_alloc_failed_sim_count++;
4945 rc = ENOBUFS;
4946 goto bce_get_pg_buf_exit);
4947
4948 /* This is a new mbuf allocation. */
4949 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
4950 if (m_new == NULL) {
4958 rc = ENOBUFS;
4959 goto bce_get_pg_buf_exit);
4960
4961 /* This is a new mbuf allocation. */
4962 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
4963 if (m_new == NULL) {
4951 sc->mbuf_alloc_failed++;
4964 sc->mbuf_alloc_failed_count++;
4952 rc = ENOBUFS;
4953 goto bce_get_pg_buf_exit;
4954 }
4955
4956 DBRUN(sc->debug_pg_mbuf_alloc++);
4957 } else {
4958 /* Reuse an existing mbuf. */
4959 m_new = m;

--- 801 unchanged lines hidden (view full) ---

5761
5762 /* Remove the mbuf from the RX chain. */
5763 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
5764 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
5765 DBRUN(sc->debug_rx_mbuf_alloc--);
5766 sc->free_rx_bd++;
5767
5768 /*
4965 rc = ENOBUFS;
4966 goto bce_get_pg_buf_exit;
4967 }
4968
4969 DBRUN(sc->debug_pg_mbuf_alloc++);
4970 } else {
4971 /* Reuse an existing mbuf. */
4972 m_new = m;

--- 801 unchanged lines hidden (view full) ---

5774
5775 /* Remove the mbuf from the RX chain. */
5776 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
5777 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
5778 DBRUN(sc->debug_rx_mbuf_alloc--);
5779 sc->free_rx_bd++;
5780
5781 /*
5769 * Frames received on the NetXteme II are prepended
5770 * with an l2_fhdr structure which provides status
5771 * information about the received frame (including
5772 * VLAN tags and checksum info). The frames are also
5773 * automatically adjusted to align the IP header
5774 * (i.e. two null bytes are inserted before the
5775 * Ethernet header). As a result the data DMA'd by
5776 * the controller into the mbuf is as follows:
5782 * Frames received on the NetXteme II are prepended with an
5783 * l2_fhdr structure which provides status information about
5784 * the received frame (including VLAN tags and checksum info).
5785 * The frames are also automatically adjusted to align the IP
5786 * header (i.e. two null bytes are inserted before the Ethernet
5787 * header). As a result the data DMA'd by the controller into
5788 * the mbuf is as follows:
5789 *
5777 * +---------+-----+---------------------+-----+
5778 * | l2_fhdr | pad | packet data | FCS |
5779 * +---------+-----+---------------------+-----+
5790 * +---------+-----+---------------------+-----+
5791 * | l2_fhdr | pad | packet data | FCS |
5792 * +---------+-----+---------------------+-----+
5780 * The l2_fhdr needs to be checked and skipped and
5781 * the FCS needs to be stripped before sending the
5782 * packet up the stack.
5793 *
5794 * The l2_fhdr needs to be checked and skipped and the FCS needs
5795 * to be stripped before sending the packet up the stack.
5783 */
5784 l2fhdr = mtod(m0, struct l2_fhdr *);
5785
5786 /* Get the packet data + FCS length and the status. */
5787 pkt_len = l2fhdr->l2_fhdr_pkt_len;
5788 status = l2fhdr->l2_fhdr_status;
5789
5790 /*

--- 98 unchanged lines hidden (view full) ---

5889
5890 /* Check that the resulting mbuf chain is valid. */
5891 DBRUN(m_sanity(m0, FALSE));
5892 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
5893 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
5894 BCE_PRINTF("Invalid Ethernet frame size!\n");
5895 m_print(m0, 128));
5896
5796 */
5797 l2fhdr = mtod(m0, struct l2_fhdr *);
5798
5799 /* Get the packet data + FCS length and the status. */
5800 pkt_len = l2fhdr->l2_fhdr_pkt_len;
5801 status = l2fhdr->l2_fhdr_status;
5802
5803 /*

--- 98 unchanged lines hidden (view full) ---

5902
5903 /* Check that the resulting mbuf chain is valid. */
5904 DBRUN(m_sanity(m0, FALSE));
5905 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
5906 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
5907 BCE_PRINTF("Invalid Ethernet frame size!\n");
5908 m_print(m0, 128));
5909
5897 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
5910 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
5898 BCE_PRINTF("Simulating l2_fhdr status error.\n");
5911 BCE_PRINTF("Simulating l2_fhdr status error.\n");
5912 sc->l2fhdr_error_sim_count++;
5899 status = status | L2_FHDR_ERRORS_PHY_DECODE);
5900
5901 /* Check the received frame for errors. */
5902 if (status & (L2_FHDR_ERRORS_BAD_CRC |
5903 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
5904 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
5905
5906 /* Log the error and release the mbuf. */
5907 ifp->if_ierrors++;
5913 status = status | L2_FHDR_ERRORS_PHY_DECODE);
5914
5915 /* Check the received frame for errors. */
5916 if (status & (L2_FHDR_ERRORS_BAD_CRC |
5917 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
5918 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
5919
5920 /* Log the error and release the mbuf. */
5921 ifp->if_ierrors++;
5908 DBRUN(sc->l2fhdr_status_errors++);
5922 sc->l2fhdr_error_count++;
5909
5910 m_freem(m0);
5911 m0 = NULL;
5912 goto bce_rx_int_next_rx;
5913 }
5914
5915 /* Send the packet to the appropriate interface. */
5916 m0->m_pkthdr.rcvif = ifp;

--- 24 unchanged lines hidden (view full) ---

5941 m0->m_pkthdr.csum_data =
5942 l2fhdr->l2_fhdr_tcp_udp_xsum;
5943 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID
5944 | CSUM_PSEUDO_HDR);
5945 }
5946 }
5947 }
5948
5923
5924 m_freem(m0);
5925 m0 = NULL;
5926 goto bce_rx_int_next_rx;
5927 }
5928
5929 /* Send the packet to the appropriate interface. */
5930 m0->m_pkthdr.rcvif = ifp;

--- 24 unchanged lines hidden (view full) ---

5955 m0->m_pkthdr.csum_data =
5956 l2fhdr->l2_fhdr_tcp_udp_xsum;
5957 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID
5958 | CSUM_PSEUDO_HDR);
5959 }
5960 }
5961 }
5962
5949 /*
5950 * If we received a packet with a vlan tag,
5951 * attach that information to the packet.
5952 */
5963 /* Attach the VLAN tag. */
5953 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
5954#if __FreeBSD_version < 700000
5955 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue);
5956#else
5957 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag;
5958 m0->m_flags |= M_VLANTAG;
5959#endif
5960 }
5961
5964 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
5965#if __FreeBSD_version < 700000
5966 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue);
5967#else
5968 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag;
5969 m0->m_flags |= M_VLANTAG;
5970#endif
5971 }
5972
5962 /* Pass the mbuf off to the upper layers. */
5973 /* Increment received packet statistics. */
5963 ifp->if_ipackets++;
5964
5965bce_rx_int_next_rx:
5966 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
5967
5968 /* If we have a packet, pass it up the stack */
5969 if (m0) {
5970 /* Make sure we don't lose our place when we release the lock. */

--- 297 unchanged lines hidden (view full) ---

6268 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6269 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6270 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6271 else
6272 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6273
6274 DBPRINT(sc, BCE_INFO_LOAD,
6275 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
5974 ifp->if_ipackets++;
5975
5976bce_rx_int_next_rx:
5977 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
5978
5979 /* If we have a packet, pass it up the stack */
5980 if (m0) {
5981 /* Make sure we don't lose our place when we release the lock. */

--- 297 unchanged lines hidden (view full) ---

6279 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6280 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6281 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6282 else
6283 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6284
6285 DBPRINT(sc, BCE_INFO_LOAD,
6286 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
6276 "rx_bd_mbuf_align_pad = %d, pg_bd_mbuf_alloc_size = %d\n",
6277 __FUNCTION__, sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
6278 sc->rx_bd_mbuf_align_pad, sc->pg_bd_mbuf_alloc_size);
6287 "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
6288 sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
6289 sc->rx_bd_mbuf_align_pad);
6279
6280 /* Program appropriate promiscuous/multicast filtering. */
6281 bce_set_rx_mode(sc);
6282
6283#ifdef ZERO_COPY_SOCKETS
6290
6291 /* Program appropriate promiscuous/multicast filtering. */
6292 bce_set_rx_mode(sc);
6293
6294#ifdef ZERO_COPY_SOCKETS
6295 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
6296 __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
6297
6284 /* Init page buffer descriptor chain. */
6285 bce_init_pg_chain(sc);
6286#endif
6287
6288 /* Init RX buffer descriptor chain. */
6289 bce_init_rx_chain(sc);
6290
6291 /* Init TX buffer descriptor chain. */

--- 192 unchanged lines hidden (view full) ---

6484
6485 /* Map the mbuf into our DMA address space. */
6486 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6487 segs, &nsegs, BUS_DMA_NOWAIT);
6488
6489 /* Check if the DMA mapping was successful */
6490 if (error == EFBIG) {
6491
6298 /* Init page buffer descriptor chain. */
6299 bce_init_pg_chain(sc);
6300#endif
6301
6302 /* Init RX buffer descriptor chain. */
6303 bce_init_rx_chain(sc);
6304
6305 /* Init TX buffer descriptor chain. */

--- 192 unchanged lines hidden (view full) ---

6498
6499 /* Map the mbuf into our DMA address space. */
6500 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6501 segs, &nsegs, BUS_DMA_NOWAIT);
6502
6503 /* Check if the DMA mapping was successful */
6504 if (error == EFBIG) {
6505
6492 /* The mbuf is too fragmented for our DMA mapping. */
6493 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n",
6494 __FUNCTION__, nsegs);
6495 DBRUN(bce_dump_mbuf(sc, m0););
6506 sc->fragmented_mbuf_count++;
6496
6497 /* Try to defrag the mbuf. */
6498 m0 = m_defrag(*m_head, M_DONTWAIT);
6499 if (m0 == NULL) {
6500 /* Defrag was unsuccessful */
6501 m_freem(*m_head);
6502 *m_head = NULL;
6507
6508 /* Try to defrag the mbuf. */
6509 m0 = m_defrag(*m_head, M_DONTWAIT);
6510 if (m0 == NULL) {
6511 /* Defrag was unsuccessful */
6512 m_freem(*m_head);
6513 *m_head = NULL;
6503 sc->mbuf_alloc_failed++;
6514 sc->mbuf_alloc_failed_count++;
6504 rc = ENOBUFS;
6505 goto bce_tx_encap_exit;
6506 }
6507
6508 /* Defrag was successful, try mapping again */
6509 *m_head = m0;
6510 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6511 segs, &nsegs, BUS_DMA_NOWAIT);
6512
6513 /* Still getting an error after a defrag. */
6514 if (error == ENOMEM) {
6515 /* Insufficient DMA buffers available. */
6515 rc = ENOBUFS;
6516 goto bce_tx_encap_exit;
6517 }
6518
6519 /* Defrag was successful, try mapping again */
6520 *m_head = m0;
6521 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6522 segs, &nsegs, BUS_DMA_NOWAIT);
6523
6524 /* Still getting an error after a defrag. */
6525 if (error == ENOMEM) {
6526 /* Insufficient DMA buffers available. */
6516 sc->tx_dma_map_failures++;
6527 sc->dma_map_addr_tx_failed_count++;
6517 rc = error;
6518 goto bce_tx_encap_exit;
6519 } else if (error != 0) {
6520 /* Still can't map the mbuf, release it and return an error. */
6521 BCE_PRINTF(
6522 "%s(%d): Unknown error mapping mbuf into TX chain!\n",
6523 __FILE__, __LINE__);
6524 m_freem(m0);
6525 *m_head = NULL;
6528 rc = error;
6529 goto bce_tx_encap_exit;
6530 } else if (error != 0) {
6531 /* Still can't map the mbuf, release it and return an error. */
6532 BCE_PRINTF(
6533 "%s(%d): Unknown error mapping mbuf into TX chain!\n",
6534 __FILE__, __LINE__);
6535 m_freem(m0);
6536 *m_head = NULL;
6526 sc->tx_dma_map_failures++;
6537 sc->dma_map_addr_tx_failed_count++;
6527 rc = ENOBUFS;
6528 goto bce_tx_encap_exit;
6529 }
6530 } else if (error == ENOMEM) {
6531 /* Insufficient DMA buffers available. */
6538 rc = ENOBUFS;
6539 goto bce_tx_encap_exit;
6540 }
6541 } else if (error == ENOMEM) {
6542 /* Insufficient DMA buffers available. */
6532 sc->tx_dma_map_failures++;
6543 sc->dma_map_addr_tx_failed_count++;
6533 rc = error;
6534 goto bce_tx_encap_exit;
6535 } else if (error != 0) {
6536 m_freem(m0);
6537 *m_head = NULL;
6544 rc = error;
6545 goto bce_tx_encap_exit;
6546 } else if (error != 0) {
6547 m_freem(m0);
6548 *m_head = NULL;
6538 sc->tx_dma_map_failures++;
6549 sc->dma_map_addr_tx_failed_count++;
6539 rc = error;
6540 goto bce_tx_encap_exit;
6541 }
6542
6543 /* Make sure there's room in the chain */
6544 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6545 bus_dmamap_unload(sc->tx_mbuf_tag, map);
6546 rc = ENOBUFS;

--- 488 unchanged lines hidden (view full) ---

7035 hw_rx_cons = bce_get_hw_rx_cons(sc);
7036 hw_tx_cons = bce_get_hw_tx_cons(sc);
7037
7038 /* Keep processing data as long as there is work to do. */
7039 for (;;) {
7040
7041 status_attn_bits = sc->status_block->status_attn_bits;
7042
6550 rc = error;
6551 goto bce_tx_encap_exit;
6552 }
6553
6554 /* Make sure there's room in the chain */
6555 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6556 bus_dmamap_unload(sc->tx_mbuf_tag, map);
6557 rc = ENOBUFS;

--- 488 unchanged lines hidden (view full) ---

7046 hw_rx_cons = bce_get_hw_rx_cons(sc);
7047 hw_tx_cons = bce_get_hw_tx_cons(sc);
7048
7049 /* Keep processing data as long as there is work to do. */
7050 for (;;) {
7051
7052 status_attn_bits = sc->status_block->status_attn_bits;
7053
7043 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
7044 BCE_PRINTF("Simulating unexpected status attention bit set.");
7045 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);
7054 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7055 BCE_PRINTF("Simulating unexpected status attention bit set.");
7056 sc->unexpected_attention_sim_count++;
7057 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);
7046
7047 /* Was it a link change interrupt? */
7048 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7049 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
7050 bce_phy_intr(sc);
7051
7052 /* Clear any transient status updates during link state change. */
7053 REG_WR(sc, BCE_HC_COMMAND,
7054 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
7055 REG_RD(sc, BCE_HC_COMMAND);
7056 }
7057
7058 /* If any other attention is asserted then the chip is toast. */
7059 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7060 (sc->status_block->status_attn_bits_ack &
7061 ~STATUS_ATTN_BITS_LINK_STATE))) {
7062
7058
7059 /* Was it a link change interrupt? */
7060 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7061 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE)) {
7062 bce_phy_intr(sc);
7063
7064 /* Clear any transient status updates during link state change. */
7065 REG_WR(sc, BCE_HC_COMMAND,
7066 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
7067 REG_RD(sc, BCE_HC_COMMAND);
7068 }
7069
7070 /* If any other attention is asserted then the chip is toast. */
7071 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7072 (sc->status_block->status_attn_bits_ack &
7073 ~STATUS_ATTN_BITS_LINK_STATE))) {
7074
7063 DBRUN(sc->unexpected_attentions++);
7075 sc->unexpected_attention_count++;
7064
7065 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n",
7066 __FILE__, __LINE__, sc->status_block->status_attn_bits);
7067
7068 DBRUNMSG(BCE_FATAL,
7076
7077 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n",
7078 __FILE__, __LINE__, sc->status_block->status_attn_bits);
7079
7080 DBRUNMSG(BCE_FATAL,
7069 if (bce_debug_unexpected_attention == 0)
7081 if (unexpected_attention_sim_control == 0)
7070 bce_breakpoint(sc));
7071
7072 bce_init_locked(sc);
7073 goto bce_intr_exit;
7074 }
7075
7076 /* Check for any completed RX frames. */
7077 if (hw_rx_cons != sc->hw_rx_cons)

--- 232 unchanged lines hidden (view full) ---

7310 stats->stat_EtherStatsFragments;
7311
7312 sc->stat_EtherStatsJabbers =
7313 stats->stat_EtherStatsJabbers;
7314
7315 sc->stat_EtherStatsUndersizePkts =
7316 stats->stat_EtherStatsUndersizePkts;
7317
7082 bce_breakpoint(sc));
7083
7084 bce_init_locked(sc);
7085 goto bce_intr_exit;
7086 }
7087
7088 /* Check for any completed RX frames. */
7089 if (hw_rx_cons != sc->hw_rx_cons)

--- 232 unchanged lines hidden (view full) ---

7322 stats->stat_EtherStatsFragments;
7323
7324 sc->stat_EtherStatsJabbers =
7325 stats->stat_EtherStatsJabbers;
7326
7327 sc->stat_EtherStatsUndersizePkts =
7328 stats->stat_EtherStatsUndersizePkts;
7329
7318 sc->stat_EtherStatsOverrsizePkts =
7319 stats->stat_EtherStatsOverrsizePkts;
7330 sc->stat_EtherStatsOversizePkts =
7331 stats->stat_EtherStatsOversizePkts;
7320
7321 sc->stat_EtherStatsPktsRx64Octets =
7322 stats->stat_EtherStatsPktsRx64Octets;
7323
7324 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
7325 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
7326
7327 sc->stat_EtherStatsPktsRx128Octetsto255Octets =

--- 87 unchanged lines hidden (view full) ---

7415 * hardware statistics.
7416 */
7417 ifp->if_collisions =
7418 (u_long) sc->stat_EtherStatsCollisions;
7419
7420 /* ToDo: This method loses soft errors. */
7421 ifp->if_ierrors =
7422 (u_long) sc->stat_EtherStatsUndersizePkts +
7332
7333 sc->stat_EtherStatsPktsRx64Octets =
7334 stats->stat_EtherStatsPktsRx64Octets;
7335
7336 sc->stat_EtherStatsPktsRx65Octetsto127Octets =
7337 stats->stat_EtherStatsPktsRx65Octetsto127Octets;
7338
7339 sc->stat_EtherStatsPktsRx128Octetsto255Octets =

--- 87 unchanged lines hidden (view full) ---

7427 * hardware statistics.
7428 */
7429 ifp->if_collisions =
7430 (u_long) sc->stat_EtherStatsCollisions;
7431
7432 /* ToDo: This method loses soft errors. */
7433 ifp->if_ierrors =
7434 (u_long) sc->stat_EtherStatsUndersizePkts +
7423 (u_long) sc->stat_EtherStatsOverrsizePkts +
7435 (u_long) sc->stat_EtherStatsOversizePkts +
7424 (u_long) sc->stat_IfInMBUFDiscards +
7425 (u_long) sc->stat_Dot3StatsAlignmentErrors +
7426 (u_long) sc->stat_Dot3StatsFCSErrors +
7427 (u_long) sc->stat_IfInRuleCheckerDiscards +
7428 (u_long) sc->stat_IfInFTQDiscards +
7429 (u_long) sc->com_no_buffers;
7430
7431 /* ToDo: This method loses soft errors. */

--- 434 unchanged lines hidden (view full) ---

7866
7867 DBENTER(BCE_VERBOSE_MISC);
7868
7869 ctx = device_get_sysctl_ctx(sc->bce_dev);
7870 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
7871
7872#ifdef BCE_DEBUG
7873 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7436 (u_long) sc->stat_IfInMBUFDiscards +
7437 (u_long) sc->stat_Dot3StatsAlignmentErrors +
7438 (u_long) sc->stat_Dot3StatsFCSErrors +
7439 (u_long) sc->stat_IfInRuleCheckerDiscards +
7440 (u_long) sc->stat_IfInFTQDiscards +
7441 (u_long) sc->com_no_buffers;
7442
7443 /* ToDo: This method loses soft errors. */

--- 434 unchanged lines hidden (view full) ---

7878
7879 DBENTER(BCE_VERBOSE_MISC);
7880
7881 ctx = device_get_sysctl_ctx(sc->bce_dev);
7882 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
7883
7884#ifdef BCE_DEBUG
7885 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7886 "l2fhdr_error_sim_control",
7887 CTLFLAG_RW, &l2fhdr_error_sim_control,
7888 0, "Debug control to force l2fhdr errors");
7889
7890 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7891 "l2fhdr_error_sim_count",
7892 CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
7893 0, "Number of simulated l2_fhdr errors");
7894#endif
7895
7896 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7897 "l2fhdr_error_count",
7898 CTLFLAG_RD, &sc->l2fhdr_error_count,
7899 0, "Number of l2_fhdr errors");
7900
7901#ifdef BCE_DEBUG
7902 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7903 "mbuf_alloc_failed_sim_control",
7904 CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
7905 0, "Debug control to force mbuf allocation failures");
7906
7907 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7908 "mbuf_alloc_failed_sim_count",
7909 CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
7910 0, "Number of simulated mbuf cluster allocation failures");
7911#endif
7912
7913 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7914 "mbuf_alloc_failed_count",
7915 CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
7916 0, "Number of mbuf allocation failures");
7917
7918 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7919 "fragmented_mbuf_count",
7920 CTLFLAG_RD, &sc->fragmented_mbuf_count,
7921 0, "Number of fragmented mbufs");
7922
7923#ifdef BCE_DEBUG
7924 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7925 "dma_map_addr_failed_sim_control",
7926 CTLFLAG_RW, &dma_map_addr_failed_sim_control,
7927 0, "Debug control to force DMA mapping failures");
7928
7929 /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
7930 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7931 "dma_map_addr_failed_sim_count",
7932 CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
7933 0, "Number of simulated DMA mapping failures");
7934
7935#endif
7936
7937 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7938 "dma_map_addr_rx_failed_count",
7939 CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
7940 0, "Number of RX DMA mapping failures");
7941
7942 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7943 "dma_map_addr_tx_failed_count",
7944 CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
7945 0, "Number of TX DMA mapping failures");
7946
7947#ifdef BCE_DEBUG
7948 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7949 "unexpected_attention_sim_control",
7950 CTLFLAG_RW, &unexpected_attention_sim_control,
7951 0, "Debug control to simulate unexpected attentions");
7952
7953 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7954 "unexpected_attention_sim_count",
7955 CTLFLAG_RW, &sc->unexpected_attention_sim_count,
7956 0, "Number of simulated unexpected attentions");
7957#endif
7958
7959 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7960 "unexpected_attention_count",
7961 CTLFLAG_RW, &sc->unexpected_attention_count,
7962 0, "Number of unexpected attentions");
7963
7964#ifdef BCE_DEBUG
7965 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7966 "debug_bootcode_running_failure",
7967 CTLFLAG_RW, &bootcode_running_failure_sim_control,
7968 0, "Debug control to force bootcode running failures");
7969
7970 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7874 "rx_low_watermark",
7875 CTLFLAG_RD, &sc->rx_low_watermark,
7876 0, "Lowest level of free rx_bd's");
7877
7878 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7879 "rx_empty_count",
7880 CTLFLAG_RD, &sc->rx_empty_count,
7881 0, "Number of times the RX chain was empty");

--- 4 unchanged lines hidden (view full) ---

7886 0, "Highest level of used tx_bd's");
7887
7888 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7889 "tx_full_count",
7890 CTLFLAG_RD, &sc->tx_full_count,
7891 0, "Number of times the TX chain was full");
7892
7893 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7971 "rx_low_watermark",
7972 CTLFLAG_RD, &sc->rx_low_watermark,
7973 0, "Lowest level of free rx_bd's");
7974
7975 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7976 "rx_empty_count",
7977 CTLFLAG_RD, &sc->rx_empty_count,
7978 0, "Number of times the RX chain was empty");

--- 4 unchanged lines hidden (view full) ---

7983 0, "Highest level of used tx_bd's");
7984
7985 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7986 "tx_full_count",
7987 CTLFLAG_RD, &sc->tx_full_count,
7988 0, "Number of times the TX chain was full");
7989
7990 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7894 "l2fhdr_status_errors",
7895 CTLFLAG_RD, &sc->l2fhdr_status_errors,
7896 0, "l2_fhdr status errors");
7897
7898 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7899 "unexpected_attentions",
7900 CTLFLAG_RD, &sc->unexpected_attentions,
7901 0, "Unexpected attentions");
7902
7903 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7904 "lost_status_block_updates",
7905 CTLFLAG_RD, &sc->lost_status_block_updates,
7906 0, "Lost status block updates");
7907
7908 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7909 "debug_mbuf_sim_alloc_failed",
7910 CTLFLAG_RD, &sc->debug_mbuf_sim_alloc_failed,
7911 0, "Simulated mbuf cluster allocation failures");
7912
7913 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7914 "requested_tso_frames",
7915 CTLFLAG_RD, &sc->requested_tso_frames,
7916 0, "Number of TSO frames received");
7917
7918 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7919 "rx_interrupts",
7920 CTLFLAG_RD, &sc->rx_interrupts,
7921 0, "Number of RX interrupts");

--- 9 unchanged lines hidden (view full) ---

7931 "RX interrupt time");
7932
7933 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7934 "tx_intr_time",
7935 CTLFLAG_RD, &sc->tx_intr_time,
7936 "TX interrupt time");
7937#endif
7938
7991 "requested_tso_frames",
7992 CTLFLAG_RD, &sc->requested_tso_frames,
7993 0, "Number of TSO frames received");
7994
7995 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7996 "rx_interrupts",
7997 CTLFLAG_RD, &sc->rx_interrupts,
7998 0, "Number of RX interrupts");

--- 9 unchanged lines hidden (view full) ---

8008 "RX interrupt time");
8009
8010 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8011 "tx_intr_time",
8012 CTLFLAG_RD, &sc->tx_intr_time,
8013 "TX interrupt time");
8014#endif
8015
7939 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7940 "mbuf_alloc_failed",
7941 CTLFLAG_RD, &sc->mbuf_alloc_failed,
7942 0, "mbuf cluster allocation failures");
7943
7944 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7945 "tx_dma_map_failures",
7946 CTLFLAG_RD, &sc->tx_dma_map_failures,
7947 0, "tx dma mapping failures");
7948
7949 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7950 "stat_IfHcInOctets",
7951 CTLFLAG_RD, &sc->stat_IfHCInOctets,
7952 "Bytes received");
7953
7954 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7955 "stat_IfHCInBadOctets",
7956 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,

--- 100 unchanged lines hidden (view full) ---

8057 0, "Jabbers");
8058
8059 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8060 "stat_EtherStatsUndersizePkts",
8061 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8062 0, "Undersize packets");
8063
8064 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8016 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8017 "stat_IfHcInOctets",
8018 CTLFLAG_RD, &sc->stat_IfHCInOctets,
8019 "Bytes received");
8020
8021 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8022 "stat_IfHCInBadOctets",
8023 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,

--- 100 unchanged lines hidden (view full) ---

8124 0, "Jabbers");
8125
8126 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8127 "stat_EtherStatsUndersizePkts",
8128 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8129 0, "Undersize packets");
8130
8131 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8065 "stat_EtherStatsOverrsizePkts",
8066 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
8067 0, "stat_EtherStatsOverrsizePkts");
8132 "stat_EtherStatsOversizePkts",
8133 CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
8134 0, "stat_EtherStatsOversizePkts");
8068
8069 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8070 "stat_EtherStatsPktsRx64Octets",
8071 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8072 0, "Bytes received in 64 byte packets");
8073
8074 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8075 "stat_EtherStatsPktsRx65Octetsto127Octets",

--- 1374 unchanged lines hidden (view full) ---

9450 if (sblk->stat_EtherStatsJabbers)
9451 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n",
9452 sblk->stat_EtherStatsJabbers);
9453
9454 if (sblk->stat_EtherStatsUndersizePkts)
9455 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n",
9456 sblk->stat_EtherStatsUndersizePkts);
9457
8135
8136 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8137 "stat_EtherStatsPktsRx64Octets",
8138 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8139 0, "Bytes received in 64 byte packets");
8140
8141 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8142 "stat_EtherStatsPktsRx65Octetsto127Octets",

--- 1374 unchanged lines hidden (view full) ---

9517 if (sblk->stat_EtherStatsJabbers)
9518 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n",
9519 sblk->stat_EtherStatsJabbers);
9520
9521 if (sblk->stat_EtherStatsUndersizePkts)
9522 BCE_PRINTF(" 0x%08X : EtherStatsUndersizePkts\n",
9523 sblk->stat_EtherStatsUndersizePkts);
9524
9458 if (sblk->stat_EtherStatsOverrsizePkts)
9525 if (sblk->stat_EtherStatsOversizePkts)
9459 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n",
9526 BCE_PRINTF(" 0x%08X : EtherStatsOverrsizePkts\n",
9460 sblk->stat_EtherStatsOverrsizePkts);
9527 sblk->stat_EtherStatsOversizePkts);
9461
9462 if (sblk->stat_EtherStatsPktsRx64Octets)
9463 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n",
9464 sblk->stat_EtherStatsPktsRx64Octets);
9465
9466 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets)
9467 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n",
9468 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);

--- 250 unchanged lines hidden (view full) ---

9719
9720 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page rx_bd's\n",
9721 sc->free_pg_bd);
9722
9723 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n",
9724 sc->pg_low_watermark, sc->max_pg_bd);
9725#endif
9726
9528
9529 if (sblk->stat_EtherStatsPktsRx64Octets)
9530 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx64Octets\n",
9531 sblk->stat_EtherStatsPktsRx64Octets);
9532
9533 if (sblk->stat_EtherStatsPktsRx65Octetsto127Octets)
9534 BCE_PRINTF(" 0x%08X : EtherStatsPktsRx65Octetsto127Octets\n",
9535 sblk->stat_EtherStatsPktsRx65Octetsto127Octets);

--- 250 unchanged lines hidden (view full) ---

9786
9787 BCE_PRINTF(" 0x%08X - (sc->free_pg_bd) free page rx_bd's\n",
9788 sc->free_pg_bd);
9789
9790 BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low watermark\n",
9791 sc->pg_low_watermark, sc->max_pg_bd);
9792#endif
9793
9727 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) "
9794 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed_count) "
9728 "mbuf alloc failures\n",
9795 "mbuf alloc failures\n",
9729 sc->mbuf_alloc_failed);
9796 sc->mbuf_alloc_failed_count);
9730
9797
9731 BCE_PRINTF(" 0x%08X - (sc->debug_mbuf_sim_alloc_failed) "
9732 "simulated mbuf alloc failures\n",
9733 sc->debug_mbuf_sim_alloc_failed);
9734
9735 BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n",
9736 sc->bce_flags);
9737
9738 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n",
9739 sc->bce_phy_flags);
9740
9741 BCE_PRINTF(
9742 "----------------------------"

--- 14 unchanged lines hidden (view full) ---

9757{
9758 u32 val;
9759
9760 BCE_PRINTF(
9761 "----------------------------"
9762 " Hardware State "
9763 "----------------------------\n");
9764
9798 BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n",
9799 sc->bce_flags);
9800
9801 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n",
9802 sc->bce_phy_flags);
9803
9804 BCE_PRINTF(
9805 "----------------------------"

--- 14 unchanged lines hidden (view full) ---

9820{
9821 u32 val;
9822
9823 BCE_PRINTF(
9824 "----------------------------"
9825 " Hardware State "
9826 "----------------------------\n");
9827
9765 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver);
9828 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_bc_ver);
9766
9767 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
9768 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
9769 val, BCE_MISC_ENABLE_STATUS_BITS);
9770
9771 val = REG_RD(sc, BCE_DMA_STATUS);
9772 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS);
9773

--- 108 unchanged lines hidden (view full) ---

9882{
9883 u32 val;
9884
9885 BCE_PRINTF(
9886 "----------------------------"
9887 " Bootcode State "
9888 "----------------------------\n");
9889
9829
9830 val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
9831 BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
9832 val, BCE_MISC_ENABLE_STATUS_BITS);
9833
9834 val = REG_RD(sc, BCE_DMA_STATUS);
9835 BCE_PRINTF("0x%08X - (0x%06X) dma_status\n", val, BCE_DMA_STATUS);
9836

--- 108 unchanged lines hidden (view full) ---

9945{
9946 u32 val;
9947
9948 BCE_PRINTF(
9949 "----------------------------"
9950 " Bootcode State "
9951 "----------------------------\n");
9952
9890 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_fw_ver);
9953 BCE_PRINTF("0x%08X - bootcode version\n", sc->bce_bc_ver);
9891
9892 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE);
9893 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
9894 val, BCE_BC_RESET_TYPE);
9895
9896 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE);
9897 BCE_PRINTF("0x%08X - (0x%06X) state\n",
9898 val, BCE_BC_STATE);

--- 338 unchanged lines hidden --- 		9954
9955 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_RESET_TYPE);
9956 BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
9957 val, BCE_BC_RESET_TYPE);
9958
9959 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE);
9960 BCE_PRINTF("0x%08X - (0x%06X) state\n",
9961 val, BCE_BC_STATE);

--- 338 unchanged lines hidden ---