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if_bce.c (179695) if_bce.c (179771)
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

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24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 179695 2008-06-10 02:19:11Z davidch $");
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 179771 2008-06-13 01:16:37Z davidch $");
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 * BCM5709C A1, C0
41 * BCM5716 C0
40 *
41 * The following controllers are not supported by this driver:
42 * BCM5706C A0, A1 (pre-production)
43 * BCM5706S A0, A1 (pre-production)
44 * BCM5708C A0, B0 (pre-production)
45 * BCM5708S A0, B0 (pre-production)
42 *
43 * The following controllers are not supported by this driver:
44 * BCM5706C A0, A1 (pre-production)
45 * BCM5706S A0, A1 (pre-production)
46 * BCM5708C A0, B0 (pre-production)
47 * BCM5708S A0, B0 (pre-production)
48 * BCM5709C A0 B0, B1, B2 (pre-production)
49 * BCM5709S A0, A1, B0, B1, B2, C0 (pre-production)
46 */
47
48#include "opt_bce.h"
49
50#include <dev/bce/if_bcereg.h>
51#include <dev/bce/if_bcefw.h>
52
53/****************************************************************************/

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83#endif
84
85/****************************************************************************/
86/* BCE Build Time Options */
87/****************************************************************************/
88#define BCE_USE_SPLIT_HEADER 1
89/* #define BCE_NVRAM_WRITE_SUPPORT 1 */
90
50 */
51
52#include "opt_bce.h"
53
54#include <dev/bce/if_bcereg.h>
55#include <dev/bce/if_bcefw.h>
56
57/****************************************************************************/

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87#endif
88
89/****************************************************************************/
90/* BCE Build Time Options */
91/****************************************************************************/
92#define BCE_USE_SPLIT_HEADER 1
93/* #define BCE_NVRAM_WRITE_SUPPORT 1 */
94
95
91/****************************************************************************/
92/* PCI Device ID Table */
93/* */
94/* Used by bce_probe() to identify the devices supported by this driver. */
95/****************************************************************************/
96#define BCE_DEVDESC_MAX 64
97
98static struct bce_type bce_devs[] = {

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112
113 /* BCM5708C controllers and OEM boards. */
114 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
115 "Broadcom NetXtreme II BCM5708 1000Base-T" },
116
117 /* BCM5708S controllers and OEM boards. */
118 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
119 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
96/****************************************************************************/
97/* PCI Device ID Table */
98/* */
99/* Used by bce_probe() to identify the devices supported by this driver. */
100/****************************************************************************/
101#define BCE_DEVDESC_MAX 64
102
103static struct bce_type bce_devs[] = {

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117
118 /* BCM5708C controllers and OEM boards. */
119 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708, PCI_ANY_ID, PCI_ANY_ID,
120 "Broadcom NetXtreme II BCM5708 1000Base-T" },
121
122 /* BCM5708S controllers and OEM boards. */
123 { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S, PCI_ANY_ID, PCI_ANY_ID,
124 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
125
126 /* BCM5709C controllers and OEM boards. */
127 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709, PCI_ANY_ID, PCI_ANY_ID,
128 "Broadcom NetXtreme II BCM5709 1000Base-T" },
129
130 /* BCM5709S controllers and OEM boards. */
131 { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S, PCI_ANY_ID, PCI_ANY_ID,
132 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
133
134 /* BCM5716 controllers and OEM boards. */
135 { BRCM_VENDORID, BRCM_DEVICEID_BCM5716, PCI_ANY_ID, PCI_ANY_ID,
136 "Broadcom NetXtreme II BCM5716 1000Base-T" },
137
120 { 0, 0, 0, 0, NULL }
121};
122
123
124/****************************************************************************/
125/* Supported Flash NVRAM device data. */
126/****************************************************************************/
127static struct flash_spec flash_table[] =
128{
138 { 0, 0, 0, 0, NULL }
139};
140
141
142/****************************************************************************/
143/* Supported Flash NVRAM device data. */
144/****************************************************************************/
145static struct flash_spec flash_table[] =
146{
147#define BUFFERED_FLAGS (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
148#define NONBUFFERED_FLAGS (BCE_NV_WREN)
149
129 /* Slow EEPROM */
130 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
150 /* Slow EEPROM */
151 {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
131 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
152 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
132 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
133 "EEPROM - slow"},
134 /* Expansion entry 0001 */
135 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
153 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
154 "EEPROM - slow"},
155 /* Expansion entry 0001 */
156 {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
136 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
157 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
137 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
138 "Entry 0001"},
139 /* Saifun SA25F010 (non-buffered flash) */
140 /* strap, cfg1, & write1 need updates */
141 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
158 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
159 "Entry 0001"},
160 /* Saifun SA25F010 (non-buffered flash) */
161 /* strap, cfg1, & write1 need updates */
162 {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
142 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
163 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
143 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
144 "Non-buffered flash (128kB)"},
145 /* Saifun SA25F020 (non-buffered flash) */
146 /* strap, cfg1, & write1 need updates */
147 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
164 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
165 "Non-buffered flash (128kB)"},
166 /* Saifun SA25F020 (non-buffered flash) */
167 /* strap, cfg1, & write1 need updates */
168 {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
148 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
169 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
149 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
150 "Non-buffered flash (256kB)"},
151 /* Expansion entry 0100 */
152 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
171 "Non-buffered flash (256kB)"},
172 /* Expansion entry 0100 */
173 {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
153 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
174 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
154 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
155 "Entry 0100"},
156 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
157 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
175 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
176 "Entry 0100"},
177 /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
178 {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
158 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
179 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
159 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
160 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
161 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
162 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
180 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
181 "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
182 /* Entry 0110: ST M45PE20 (non-buffered flash)*/
183 {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
163 0, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
184 NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
164 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
165 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
166 /* Saifun SA25F005 (non-buffered flash) */
167 /* strap, cfg1, & write1 need updates */
168 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
185 ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
186 "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
187 /* Saifun SA25F005 (non-buffered flash) */
188 /* strap, cfg1, & write1 need updates */
189 {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
169 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
190 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
170 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
171 "Non-buffered flash (64kB)"},
172 /* Fast EEPROM */
173 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
191 SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
192 "Non-buffered flash (64kB)"},
193 /* Fast EEPROM */
194 {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
174 1, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
195 BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
175 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
176 "EEPROM - fast"},
177 /* Expansion entry 1001 */
178 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
196 SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
197 "EEPROM - fast"},
198 /* Expansion entry 1001 */
199 {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
179 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
200 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
180 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
181 "Entry 1001"},
182 /* Expansion entry 1010 */
183 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
201 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
202 "Entry 1001"},
203 /* Expansion entry 1010 */
204 {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
184 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
205 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
185 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
186 "Entry 1010"},
187 /* ATMEL AT45DB011B (buffered flash) */
188 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
206 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
207 "Entry 1010"},
208 /* ATMEL AT45DB011B (buffered flash) */
209 {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
189 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
210 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
190 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
191 "Buffered flash (128kB)"},
192 /* Expansion entry 1100 */
193 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
211 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
212 "Buffered flash (128kB)"},
213 /* Expansion entry 1100 */
214 {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
194 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
215 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
195 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
196 "Entry 1100"},
197 /* Expansion entry 1101 */
198 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
216 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
217 "Entry 1100"},
218 /* Expansion entry 1101 */
219 {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
199 0, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
220 NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
200 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
201 "Entry 1101"},
202 /* Ateml Expansion entry 1110 */
203 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
221 SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
222 "Entry 1101"},
223 /* Ateml Expansion entry 1110 */
224 {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
204 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
225 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
205 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
206 "Entry 1110 (Atmel)"},
207 /* ATMEL AT45DB021B (buffered flash) */
208 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
226 BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
227 "Entry 1110 (Atmel)"},
228 /* ATMEL AT45DB021B (buffered flash) */
229 {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
209 1, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
230 BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
210 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
211 "Buffered flash (256kB)"},
212};
213
231 BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
232 "Buffered flash (256kB)"},
233};
234
235/*
236 * The BCM5709 controllers transparently handle the
237 * differences between Atmel 264 byte pages and all
238 * flash devices which use 256 byte pages, so no
239 * logical-to-physical mapping is required in the
240 * driver.
241 */
242static struct flash_spec flash_5709 = {
243 .flags = BCE_NV_BUFFERED,
244 .page_bits = BCM5709_FLASH_PAGE_BITS,
245 .page_size = BCM5709_FLASH_PAGE_SIZE,
246 .addr_mask = BCM5709_FLASH_BYTE_ADDR_MASK,
247 .total_size = BUFFERED_FLASH_TOTAL_SIZE * 2,
248 .name = "5709 buffered flash (256kB)",
249};
214
250
251
215/****************************************************************************/
216/* FreeBSD device entry points. */
217/****************************************************************************/
218static int bce_probe (device_t);
219static int bce_attach (device_t);
220static int bce_detach (device_t);
221static int bce_shutdown (device_t);
222
223
224/****************************************************************************/
225/* BCE Debug Data Structure Dump Routines */
226/****************************************************************************/
227#ifdef BCE_DEBUG
252/****************************************************************************/
253/* FreeBSD device entry points. */
254/****************************************************************************/
255static int bce_probe (device_t);
256static int bce_attach (device_t);
257static int bce_detach (device_t);
258static int bce_shutdown (device_t);
259
260
261/****************************************************************************/
262/* BCE Debug Data Structure Dump Routines */
263/****************************************************************************/
264#ifdef BCE_DEBUG
265static u32 bce_reg_rd (struct bce_softc *, u32);
266static void bce_reg_wr (struct bce_softc *, u32, u32);
267static void bce_reg_wr16 (struct bce_softc *, u32, u16);
228static u32 bce_ctx_rd (struct bce_softc *, u32, u32);
229static void bce_dump_mbuf (struct bce_softc *, struct mbuf *);
230static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int);
231static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int);
232#ifdef BCE_USE_SPLIT_HEADER
233static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int);
234#endif
235static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *);

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244static void bce_dump_rx_chain (struct bce_softc *, u16, int);
245#ifdef BCE_USE_SPLIT_HEADER
246static void bce_dump_pg_chain (struct bce_softc *, u16, int);
247#endif
248static void bce_dump_status_block (struct bce_softc *);
249static void bce_dump_stats_block (struct bce_softc *);
250static void bce_dump_driver_state (struct bce_softc *);
251static void bce_dump_hw_state (struct bce_softc *);
268static u32 bce_ctx_rd (struct bce_softc *, u32, u32);
269static void bce_dump_mbuf (struct bce_softc *, struct mbuf *);
270static void bce_dump_tx_mbuf_chain (struct bce_softc *, u16, int);
271static void bce_dump_rx_mbuf_chain (struct bce_softc *, u16, int);
272#ifdef BCE_USE_SPLIT_HEADER
273static void bce_dump_pg_mbuf_chain (struct bce_softc *, u16, int);
274#endif
275static void bce_dump_txbd (struct bce_softc *, int, struct tx_bd *);

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284static void bce_dump_rx_chain (struct bce_softc *, u16, int);
285#ifdef BCE_USE_SPLIT_HEADER
286static void bce_dump_pg_chain (struct bce_softc *, u16, int);
287#endif
288static void bce_dump_status_block (struct bce_softc *);
289static void bce_dump_stats_block (struct bce_softc *);
290static void bce_dump_driver_state (struct bce_softc *);
291static void bce_dump_hw_state (struct bce_softc *);
292static void bce_dump_mq_regs (struct bce_softc *);
252static void bce_dump_bc_state (struct bce_softc *);
293static void bce_dump_bc_state (struct bce_softc *);
294static void bce_dump_txp_state (struct bce_softc *, int);
295static void bce_dump_rxp_state (struct bce_softc *, int);
296static void bce_dump_tpat_state (struct bce_softc *, int);
297static void bce_dump_cp_state (struct bce_softc *, int);
298static void bce_dump_com_state (struct bce_softc *, int);
253static void bce_breakpoint (struct bce_softc *);
254#endif
255
256
257/****************************************************************************/
258/* BCE Register/Memory Access Routines */
259/****************************************************************************/
260static u32 bce_reg_rd_ind (struct bce_softc *, u32);

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282static int bce_nvram_erase_page (struct bce_softc *, u32);
283static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32);
284static int bce_nvram_write (struct bce_softc *, u32, u8 *, int);
285#endif
286
287/****************************************************************************/
288/* */
289/****************************************************************************/
299static void bce_breakpoint (struct bce_softc *);
300#endif
301
302
303/****************************************************************************/
304/* BCE Register/Memory Access Routines */
305/****************************************************************************/
306static u32 bce_reg_rd_ind (struct bce_softc *, u32);

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328static int bce_nvram_erase_page (struct bce_softc *, u32);
329static int bce_nvram_write_dword (struct bce_softc *, u32, u8 *, u32);
330static int bce_nvram_write (struct bce_softc *, u32, u8 *, int);
331#endif
332
333/****************************************************************************/
334/* */
335/****************************************************************************/
336static void bce_get_media (struct bce_softc *);
290static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int);
291static int bce_dma_alloc (device_t);
292static void bce_dma_free (struct bce_softc *);
293static void bce_release_resources (struct bce_softc *);
294
295/****************************************************************************/
296/* BCE Firmware Synchronization and Load */
297/****************************************************************************/
298static int bce_fw_sync (struct bce_softc *, u32);
299static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32);
300static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *);
337static void bce_dma_map_addr (void *, bus_dma_segment_t *, int, int);
338static int bce_dma_alloc (device_t);
339static void bce_dma_free (struct bce_softc *);
340static void bce_release_resources (struct bce_softc *);
341
342/****************************************************************************/
343/* BCE Firmware Synchronization and Load */
344/****************************************************************************/
345static int bce_fw_sync (struct bce_softc *, u32);
346static void bce_load_rv2p_fw (struct bce_softc *, u32 *, u32, u32);
347static void bce_load_cpu_fw (struct bce_softc *, struct cpu_reg *, struct fw_info *);
348static void bce_init_rxp_cpu (struct bce_softc *);
349static void bce_init_txp_cpu (struct bce_softc *);
350static void bce_init_tpat_cpu (struct bce_softc *);
351static void bce_init_cp_cpu (struct bce_softc *);
352static void bce_init_com_cpu (struct bce_softc *);
301static void bce_init_cpus (struct bce_softc *);
302
353static void bce_init_cpus (struct bce_softc *);
354
355static void bce_print_adapter_info (struct bce_softc *);
356static void bce_probe_pci_caps (device_t, struct bce_softc *);
303static void bce_stop (struct bce_softc *);
304static int bce_reset (struct bce_softc *, u32);
305static int bce_chipinit (struct bce_softc *);
306static int bce_blockinit (struct bce_softc *);
357static void bce_stop (struct bce_softc *);
358static int bce_reset (struct bce_softc *, u32);
359static int bce_chipinit (struct bce_softc *);
360static int bce_blockinit (struct bce_softc *);
307static int bce_get_rx_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *);
308#ifdef BCE_USE_SPLIT_HEADER
309static int bce_get_pg_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *);
310#endif
311
312static int bce_init_tx_chain (struct bce_softc *);
313static void bce_free_tx_chain (struct bce_softc *);
314
361
362static int bce_init_tx_chain (struct bce_softc *);
363static void bce_free_tx_chain (struct bce_softc *);
364
365static int bce_get_rx_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *, u32 *);
315static int bce_init_rx_chain (struct bce_softc *);
316static void bce_fill_rx_chain (struct bce_softc *);
317static void bce_free_rx_chain (struct bce_softc *);
318
319#ifdef BCE_USE_SPLIT_HEADER
366static int bce_init_rx_chain (struct bce_softc *);
367static void bce_fill_rx_chain (struct bce_softc *);
368static void bce_free_rx_chain (struct bce_softc *);
369
370#ifdef BCE_USE_SPLIT_HEADER
371static int bce_get_pg_buf (struct bce_softc *, struct mbuf *, u16 *, u16 *);
320static int bce_init_pg_chain (struct bce_softc *);
321static void bce_fill_pg_chain (struct bce_softc *);
322static void bce_free_pg_chain (struct bce_softc *);
323#endif
324
325static int bce_tx_encap (struct bce_softc *, struct mbuf **);
326static void bce_start_locked (struct ifnet *);
327static void bce_start (struct ifnet *);

--- 9 unchanged lines hidden (view full) ---

337static void bce_init_ctx (struct bce_softc *);
338static void bce_get_mac_addr (struct bce_softc *);
339static void bce_set_mac_addr (struct bce_softc *);
340static void bce_phy_intr (struct bce_softc *);
341static inline u16 bce_get_hw_rx_cons(struct bce_softc *);
342static void bce_rx_intr (struct bce_softc *);
343static void bce_tx_intr (struct bce_softc *);
344static void bce_disable_intr (struct bce_softc *);
372static int bce_init_pg_chain (struct bce_softc *);
373static void bce_fill_pg_chain (struct bce_softc *);
374static void bce_free_pg_chain (struct bce_softc *);
375#endif
376
377static int bce_tx_encap (struct bce_softc *, struct mbuf **);
378static void bce_start_locked (struct ifnet *);
379static void bce_start (struct ifnet *);

--- 9 unchanged lines hidden (view full) ---

389static void bce_init_ctx (struct bce_softc *);
390static void bce_get_mac_addr (struct bce_softc *);
391static void bce_set_mac_addr (struct bce_softc *);
392static void bce_phy_intr (struct bce_softc *);
393static inline u16 bce_get_hw_rx_cons(struct bce_softc *);
394static void bce_rx_intr (struct bce_softc *);
395static void bce_tx_intr (struct bce_softc *);
396static void bce_disable_intr (struct bce_softc *);
345static void bce_enable_intr (struct bce_softc *);
397static void bce_enable_intr (struct bce_softc *, int);
398
346static void bce_intr (void *);
347static void bce_set_rx_mode (struct bce_softc *);
348static void bce_stats_update (struct bce_softc *);
349static void bce_tick (void *);
350static void bce_pulse (void *);
351static void bce_add_sysctls (struct bce_softc *);
352
353

--- 41 unchanged lines hidden (view full) ---

395
396DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
397DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
398
399
400/****************************************************************************/
401/* Tunable device values */
402/****************************************************************************/
399static void bce_intr (void *);
400static void bce_set_rx_mode (struct bce_softc *);
401static void bce_stats_update (struct bce_softc *);
402static void bce_tick (void *);
403static void bce_pulse (void *);
404static void bce_add_sysctls (struct bce_softc *);
405
406

--- 41 unchanged lines hidden (view full) ---

448
449DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
450DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
451
452
453/****************************************************************************/
454/* Tunable device values */
455/****************************************************************************/
403static int bce_tso_enable = TRUE;
404static int bce_msi_enable = 1;
405
406SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
407
408/* Allowable values are TRUE or FALSE */
456SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
457
458/* Allowable values are TRUE or FALSE */
459static int bce_tso_enable = TRUE;
409TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
410SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
411"TSO Enable/Disable");
412
460TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
461SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
462"TSO Enable/Disable");
463
413/* Allowable values are 0 (IRQ only) and 1 (IRQ or MSI) */
464/* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
465/* ToDo: Add MSI-X support. */
466static int bce_msi_enable = 1;
414TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
415SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
467TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
468SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
416"MSI | INTx selector");
469"MSI-X|MSI|INTx selector");
417
418/* ToDo: Add tunable to enable/disable strict MTU handling. */
419/* Currently allows "loose" RX MTU checking (i.e. sets the */
420/* h/w RX MTU to the size of the largest receive buffer, or */
421/* 2048 bytes). */
422
470
471/* ToDo: Add tunable to enable/disable strict MTU handling. */
472/* Currently allows "loose" RX MTU checking (i.e. sets the */
473/* h/w RX MTU to the size of the largest receive buffer, or */
474/* 2048 bytes). */
475
476
423/****************************************************************************/
424/* Device probe function. */
425/* */
426/* Compares the device to the driver's list of supported devices and */
427/* reports back to the OS whether this is the right driver for the device. */
428/* */
429/* Returns: */
430/* BUS_PROBE_DEFAULT on success, positive value on failure. */

--- 14 unchanged lines hidden (view full) ---

445 sc->bce_dev = dev;
446
447 /* Get the data for the device to be probed. */
448 vid = pci_get_vendor(dev);
449 did = pci_get_device(dev);
450 svid = pci_get_subvendor(dev);
451 sdid = pci_get_subdevice(dev);
452
477/****************************************************************************/
478/* Device probe function. */
479/* */
480/* Compares the device to the driver's list of supported devices and */
481/* reports back to the OS whether this is the right driver for the device. */
482/* */
483/* Returns: */
484/* BUS_PROBE_DEFAULT on success, positive value on failure. */

--- 14 unchanged lines hidden (view full) ---

499 sc->bce_dev = dev;
500
501 /* Get the data for the device to be probed. */
502 vid = pci_get_vendor(dev);
503 did = pci_get_device(dev);
504 svid = pci_get_subvendor(dev);
505 sdid = pci_get_subdevice(dev);
506
453 DBPRINT(sc, BCE_VERBOSE_LOAD,
507 DBPRINT(sc, BCE_EXTREME_LOAD,
454 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
455 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
456
457 /* Look through the list of known devices for a match. */
458 while(t->bce_name != NULL) {
459
508 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
509 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
510
511 /* Look through the list of known devices for a match. */
512 while(t->bce_name != NULL) {
513
460 if ((vid == t->bce_vid) && (did == t->bce_did) &&
514 if ((vid == t->bce_vid) && (did == t->bce_did) &&
461 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
462 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
463
464 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
465
466 if (descbuf == NULL)
467 return(ENOMEM);
468
469 /* Print out the device identity. */
515 ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
516 ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
517
518 descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
519
520 if (descbuf == NULL)
521 return(ENOMEM);
522
523 /* Print out the device identity. */
470 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
524 snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
471 t->bce_name,
472 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
473 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
474
475 device_set_desc_copy(dev, descbuf);
476 free(descbuf, M_TEMP);
477 return(BUS_PROBE_DEFAULT);
478 }
479 t++;
480 }
481
482 return(ENXIO);
483}
484
485
486/****************************************************************************/
525 t->bce_name,
526 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
527 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
528
529 device_set_desc_copy(dev, descbuf);
530 free(descbuf, M_TEMP);
531 return(BUS_PROBE_DEFAULT);
532 }
533 t++;
534 }
535
536 return(ENXIO);
537}
538
539
540/****************************************************************************/
541/* PCI Capabilities Probe Function. */
542/* */
543/* Walks the PCI capabiites list for the device to find what features are */
544/* supported. */
545/* */
546/* Returns: */
547/* None. */
548/****************************************************************************/
549static void
550bce_print_adapter_info(struct bce_softc *sc)
551{
552 DBENTER(BCE_VERBOSE_LOAD);
553
554 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
555 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
556 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
557
558 /* Bus info. */
559 if (sc->bce_flags & BCE_PCIE_FLAG) {
560 printf("Bus (PCIe x%d, ", sc->link_width);
561 switch (sc->link_speed) {
562 case 1: printf("2.5Gbps); "); break;
563 case 2: printf("5Gbps); "); break;
564 default: printf("Unknown link speed); ");
565 }
566 } else {
567 printf("Bus (PCI%s, %s, %dMHz); ",
568 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
569 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
570 sc->bus_speed_mhz);
571 }
572
573 /* Firmware version and device features. */
574 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
575#ifdef BCE_USE_SPLIT_HEADER
576 printf("SPLT ");
577#endif
578 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
579 printf("MFW ");
580 if (sc->bce_flags & BCE_USING_MSI_FLAG)
581 printf("MSI ");
582 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
583 printf("MSI-X ");
584 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
585 printf("2.5G ");
586 printf(")\n");
587
588 DBEXIT(BCE_VERBOSE_LOAD);
589}
590
591
592/****************************************************************************/
593/* PCI Capabilities Probe Function. */
594/* */
595/* Walks the PCI capabiites list for the device to find what features are */
596/* supported. */
597/* */
598/* Returns: */
599/* None. */
600/****************************************************************************/
601static void
602bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
603{
604 u32 reg;
605
606 DBENTER(BCE_VERBOSE_LOAD);
607
608 /* Check if PCI-X capability is enabled. */
609 if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
610 if (reg != 0)
611 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
612 }
613
614 /* Check if PCIe capability is enabled. */
615 if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
616 if (reg != 0) {
617 u16 link_status = pci_read_config(dev, reg + 0x12, 2);
618 DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = 0x%08X\n",
619 link_status);
620 sc->link_speed = link_status & 0xf;
621 sc->link_width = (link_status >> 4) & 0x3f;
622 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
623 sc->bce_flags |= BCE_PCIE_FLAG;
624 }
625 }
626
627 /* Check if MSI capability is enabled. */
628 if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
629 if (reg != 0)
630 sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
631 }
632
633 /* Check if MSI-X capability is enabled. */
634 if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
635 if (reg != 0)
636 sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
637 }
638
639 DBEXIT(BCE_VERBOSE_LOAD);
640}
641
642
643/****************************************************************************/
487/* Device attach function. */
488/* */
489/* Allocates device resources, performs secondary chip identification, */
490/* resets and initializes the hardware, and initializes driver instance */
491/* variables. */
492/* */
493/* Returns: */
494/* 0 on success, positive value on failure. */
495/****************************************************************************/
496static int
497bce_attach(device_t dev)
498{
499 struct bce_softc *sc;
500 struct ifnet *ifp;
501 u32 val;
644/* Device attach function. */
645/* */
646/* Allocates device resources, performs secondary chip identification, */
647/* resets and initializes the hardware, and initializes driver instance */
648/* variables. */
649/* */
650/* Returns: */
651/* 0 on success, positive value on failure. */
652/****************************************************************************/
653static int
654bce_attach(device_t dev)
655{
656 struct bce_softc *sc;
657 struct ifnet *ifp;
658 u32 val;
502 int count, rid, rc = 0;
659 int error, rid, rc = 0;
503
504 sc = device_get_softc(dev);
505 sc->bce_dev = dev;
506
660
661 sc = device_get_softc(dev);
662 sc->bce_dev = dev;
663
507 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
664 DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
508
509 sc->bce_unit = device_get_unit(dev);
510
511 /* Set initial device and PHY flags */
512 sc->bce_flags = 0;
513 sc->bce_phy_flags = 0;
514
515 pci_enable_busmaster(dev);
516
517 /* Allocate PCI memory resources. */
518 rid = PCIR_BAR(0);
519 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
520 &rid, RF_ACTIVE);
521
522 if (sc->bce_res_mem == NULL) {
665
666 sc->bce_unit = device_get_unit(dev);
667
668 /* Set initial device and PHY flags */
669 sc->bce_flags = 0;
670 sc->bce_phy_flags = 0;
671
672 pci_enable_busmaster(dev);
673
674 /* Allocate PCI memory resources. */
675 rid = PCIR_BAR(0);
676 sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
677 &rid, RF_ACTIVE);
678
679 if (sc->bce_res_mem == NULL) {
523 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
680 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
524 __FILE__, __LINE__);
525 rc = ENXIO;
526 goto bce_attach_fail;
527 }
528
529 /* Get various resource handles. */
530 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
531 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
532 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
533
681 __FILE__, __LINE__);
682 rc = ENXIO;
683 goto bce_attach_fail;
684 }
685
686 /* Get various resource handles. */
687 sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
688 sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
689 sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
690
534 /* If MSI is enabled in the driver, get the vector count. */
535 count = bce_msi_enable ? pci_msi_count(dev) : 0;
691 bce_probe_pci_caps(dev, sc);
536
692
537 /* Allocate PCI IRQ resources. */
538 if (count == 1 && pci_alloc_msi(dev, &count) == 0 && count == 1) {
539 rid = 1;
540 sc->bce_flags |= BCE_USING_MSI_FLAG;
541 DBPRINT(sc, BCE_VERBOSE_LOAD,
542 "Allocating %d MSI interrupt(s)\n", count);
543 } else {
693 rid = 1;
694#if 0
695 /* Try allocating MSI-X interrupts. */
696 if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
697 (bce_msi_enable >= 2) &&
698 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
699 &rid, RF_ACTIVE)) != NULL)) {
700
701 msi_needed = sc->bce_msi_count = 1;
702
703 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
704 (sc->bce_msi_count != msi_needed)) {
705 BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
706 "Received = %d, error = %d\n", __FILE__, __LINE__,
707 msi_needed, sc->bce_msi_count, error);
708 sc->bce_msi_count = 0;
709 pci_release_msi(dev);
710 bus_release_resource(dev, SYS_RES_MEMORY, rid,
711 sc->bce_res_irq);
712 sc->bce_res_irq = NULL;
713 } else {
714 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
715 __FUNCTION__);
716 sc->bce_flags |= BCE_USING_MSIX_FLAG;
717 sc->bce_intr = bce_intr;
718 }
719 }
720#endif
721
722 /* Try allocating a MSI interrupt. */
723 if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
724 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
725 sc->bce_msi_count = 1;
726 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
727 BCE_PRINTF("%s(%d): MSI allocation failed! error = %d\n",
728 __FILE__, __LINE__, error);
729 sc->bce_msi_count = 0;
730 pci_release_msi(dev);
731 } else {
732 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI interrupt.\n",
733 __FUNCTION__);
734 sc->bce_flags |= BCE_USING_MSI_FLAG;
735 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
736 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
737 sc->bce_irq_rid = 1;
738 sc->bce_intr = bce_intr;
739 }
740 }
741
742 /* Try allocating a legacy interrupt. */
743 if (sc->bce_msi_count == 0) {
744 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
745 __FUNCTION__);
544 rid = 0;
746 rid = 0;
545 DBPRINT(sc, BCE_VERBOSE_LOAD, "Allocating IRQ interrupt\n");
747 sc->bce_intr = bce_intr;
546 }
547
748 }
749
548 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
549 RF_SHAREABLE | RF_ACTIVE);
750 sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
751 &rid, RF_SHAREABLE | RF_ACTIVE);
550
752
753 sc->bce_irq_rid = rid;
754
755 /* Report any IRQ allocation errors. */
551 if (sc->bce_res_irq == NULL) {
756 if (sc->bce_res_irq == NULL) {
552 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
757 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
553 __FILE__, __LINE__);
554 rc = ENXIO;
555 goto bce_attach_fail;
556 }
557
558 /* Initialize mutex for the current device instance. */
559 BCE_LOCK_INIT(sc, device_get_nameunit(dev));
560

--- 11 unchanged lines hidden (view full) ---

572 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
573
574 /* Weed out any non-production controller revisions. */
575 switch(BCE_CHIP_ID(sc)) {
576 case BCE_CHIP_ID_5706_A0:
577 case BCE_CHIP_ID_5706_A1:
578 case BCE_CHIP_ID_5708_A0:
579 case BCE_CHIP_ID_5708_B0:
758 __FILE__, __LINE__);
759 rc = ENXIO;
760 goto bce_attach_fail;
761 }
762
763 /* Initialize mutex for the current device instance. */
764 BCE_LOCK_INIT(sc, device_get_nameunit(dev));
765

--- 11 unchanged lines hidden (view full) ---

777 sc->bce_chipid = REG_RD(sc, BCE_MISC_ID);
778
779 /* Weed out any non-production controller revisions. */
780 switch(BCE_CHIP_ID(sc)) {
781 case BCE_CHIP_ID_5706_A0:
782 case BCE_CHIP_ID_5706_A1:
783 case BCE_CHIP_ID_5708_A0:
784 case BCE_CHIP_ID_5708_B0:
785 case BCE_CHIP_ID_5709_A0:
786 case BCE_CHIP_ID_5709_B0:
787 case BCE_CHIP_ID_5709_B1:
788 case BCE_CHIP_ID_5709_B2:
580 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n",
789 BCE_PRINTF("%s(%d): Unsupported controller revision (%c%d)!\n",
581 __FILE__, __LINE__,
790 __FILE__, __LINE__,
582 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
583 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
584 rc = ENODEV;
585 goto bce_attach_fail;
586 }
587
791 (((pci_read_config(dev, PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
792 (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
793 rc = ENODEV;
794 goto bce_attach_fail;
795 }
796
588 /*
589 * The embedded PCIe to PCI-X bridge (EPB)
590 * in the 5708 cannot address memory above
591 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
797 /*
798 * The embedded PCIe to PCI-X bridge (EPB)
799 * in the 5708 cannot address memory above
800 * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
592 */
593 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
594 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
595 else
596 sc->max_bus_addr = BUS_SPACE_MAXADDR;
597
598 /*
599 * Find the base address for shared memory access.
600 * Newer versions of bootcode use a signature and offset
601 * while older versions use a fixed address.
602 */
603 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
604 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
801 */
802 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
803 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
804 else
805 sc->max_bus_addr = BUS_SPACE_MAXADDR;
806
807 /*
808 * Find the base address for shared memory access.
809 * Newer versions of bootcode use a signature and offset
810 * while older versions use a fixed address.
811 */
812 val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
813 if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
605 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0);
814 /* Multi-port devices use different offsets in shared memory. */
815 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
816 (pci_get_function(sc->bce_dev) << 2));
606 else
607 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
608
817 else
818 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
819
609 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
820 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
610 __FUNCTION__, sc->bce_shmem_base);
611
612 /* Fetch the bootcode revision. */
821 __FUNCTION__, sc->bce_shmem_base);
822
823 /* Fetch the bootcode revision. */
613 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
824 sc->bce_fw_ver = REG_RD_IND(sc, sc->bce_shmem_base +
614 BCE_DEV_INFO_BC_REV);
615
616 /* Check if any management firmware is running. */
617 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
618 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
619 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
620
621 /* Get PCI bus information (speed and type). */

--- 38 unchanged lines hidden (view full) ---

660 sc->bus_speed_mhz = 33;
661 }
662
663 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
664 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
665
666 /* Reset the controller and announce to bootcode that driver is present. */
667 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
825 BCE_DEV_INFO_BC_REV);
826
827 /* Check if any management firmware is running. */
828 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_PORT_FEATURE);
829 if (val & (BCE_PORT_FEATURE_ASF_ENABLED | BCE_PORT_FEATURE_IMD_ENABLED))
830 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
831
832 /* Get PCI bus information (speed and type). */

--- 38 unchanged lines hidden (view full) ---

871 sc->bus_speed_mhz = 33;
872 }
873
874 if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
875 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
876
877 /* Reset the controller and announce to bootcode that driver is present. */
878 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
668 BCE_PRINTF("%s(%d): Controller reset failed!\n",
879 BCE_PRINTF("%s(%d): Controller reset failed!\n",
669 __FILE__, __LINE__);
670 rc = ENXIO;
671 goto bce_attach_fail;
672 }
673
674 /* Initialize the controller. */
675 if (bce_chipinit(sc)) {
676 BCE_PRINTF("%s(%d): Controller initialization failed!\n",

--- 13 unchanged lines hidden (view full) ---

690 /* Fetch the permanent Ethernet MAC address. */
691 bce_get_mac_addr(sc);
692
693 /*
694 * Trip points control how many BDs
695 * should be ready before generating an
696 * interrupt while ticks control how long
697 * a BD can sit in the chain before
880 __FILE__, __LINE__);
881 rc = ENXIO;
882 goto bce_attach_fail;
883 }
884
885 /* Initialize the controller. */
886 if (bce_chipinit(sc)) {
887 BCE_PRINTF("%s(%d): Controller initialization failed!\n",

--- 13 unchanged lines hidden (view full) ---

901 /* Fetch the permanent Ethernet MAC address. */
902 bce_get_mac_addr(sc);
903
904 /*
905 * Trip points control how many BDs
906 * should be ready before generating an
907 * interrupt while ticks control how long
908 * a BD can sit in the chain before
698 * generating an interrupt. Set the default
909 * generating an interrupt. Set the default
699 * values for the RX and TX chains.
700 */
701
702#ifdef BCE_DEBUG
703 /* Force more frequent interrupts. */
704 sc->bce_tx_quick_cons_trip_int = 1;
705 sc->bce_tx_quick_cons_trip = 1;
706 sc->bce_tx_ticks_int = 0;

--- 14 unchanged lines hidden (view full) ---

721 sc->bce_rx_quick_cons_trip = 6;
722 sc->bce_rx_ticks_int = 18;
723 sc->bce_rx_ticks = 18;
724#endif
725
726 /* Update statistics once every second. */
727 sc->bce_stats_ticks = 1000000 & 0xffff00;
728
910 * values for the RX and TX chains.
911 */
912
913#ifdef BCE_DEBUG
914 /* Force more frequent interrupts. */
915 sc->bce_tx_quick_cons_trip_int = 1;
916 sc->bce_tx_quick_cons_trip = 1;
917 sc->bce_tx_ticks_int = 0;

--- 14 unchanged lines hidden (view full) ---

932 sc->bce_rx_quick_cons_trip = 6;
933 sc->bce_rx_ticks_int = 18;
934 sc->bce_rx_ticks = 18;
935#endif
936
937 /* Update statistics once every second. */
938 sc->bce_stats_ticks = 1000000 & 0xffff00;
939
729 /*
730 * The SerDes based NetXtreme II controllers
731 * that support 2.5Gb operation (currently
732 * 5708S) use a PHY at address 2, otherwise
733 * the PHY is present at address 1.
734 */
735 sc->bce_phy_addr = 1;
940 /* Find the media type for the adapter. */
941 bce_get_media(sc);
736
942
737 if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
738 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
739 sc->bce_flags |= BCE_NO_WOL_FLAG;
740 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
741 sc->bce_phy_addr = 2;
742 val = REG_RD_IND(sc, sc->bce_shmem_base +
743 BCE_SHARED_HW_CFG_CONFIG);
744 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
745 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
746 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n");
747 }
748 }
749 }
750
751 /* Store data needed by PHY driver for backplane applications */
752 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base +
753 BCE_SHARED_HW_CFG_CONFIG);
754 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base +
943 /* Store data needed by PHY driver for backplane applications */
944 sc->bce_shared_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base +
945 BCE_SHARED_HW_CFG_CONFIG);
946 sc->bce_port_hw_cfg = REG_RD_IND(sc, sc->bce_shmem_base +
755 BCE_SHARED_HW_CFG_CONFIG);
947 BCE_PORT_HW_CFG_CONFIG);
756
757 /* Allocate DMA memory resources. */
758 if (bce_dma_alloc(dev)) {
759 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
760 __FILE__, __LINE__);
761 rc = ENXIO;
762 goto bce_attach_fail;
763 }
764
765 /* Allocate an ifnet structure. */
766 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
767 if (ifp == NULL) {
948
949 /* Allocate DMA memory resources. */
950 if (bce_dma_alloc(dev)) {
951 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
952 __FILE__, __LINE__);
953 rc = ENXIO;
954 goto bce_attach_fail;
955 }
956
957 /* Allocate an ifnet structure. */
958 ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
959 if (ifp == NULL) {
768 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
960 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
769 __FILE__, __LINE__);
770 rc = ENXIO;
771 goto bce_attach_fail;
772 }
773
774 /* Initialize the ifnet interface. */
775 ifp->if_softc = sc;
776 if_initname(ifp, device_get_name(dev), device_get_unit(dev));

--- 8 unchanged lines hidden (view full) ---

785 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4;
786 } else {
787 ifp->if_hwassist = BCE_IF_HWASSIST;
788 ifp->if_capabilities = BCE_IF_CAPABILITIES;
789 }
790
791 ifp->if_capenable = ifp->if_capabilities;
792
961 __FILE__, __LINE__);
962 rc = ENXIO;
963 goto bce_attach_fail;
964 }
965
966 /* Initialize the ifnet interface. */
967 ifp->if_softc = sc;
968 if_initname(ifp, device_get_name(dev), device_get_unit(dev));

--- 8 unchanged lines hidden (view full) ---

977 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4;
978 } else {
979 ifp->if_hwassist = BCE_IF_HWASSIST;
980 ifp->if_capabilities = BCE_IF_CAPABILITIES;
981 }
982
983 ifp->if_capenable = ifp->if_capabilities;
984
793 /* Use standard mbuf sizes for buffer allocation. */
985 /*
986 * Assume standard mbuf sizes for buffer allocation.
987 * This may change later if the MTU size is set to
988 * something other than 1500.
989 */
794#ifdef BCE_USE_SPLIT_HEADER
795 sc->rx_bd_mbuf_alloc_size = MHLEN;
796 /* Make sure offset is 16 byte aligned for hardware. */
797 sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) -
798 (MSIZE - MHLEN);
799 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
800 sc->rx_bd_mbuf_align_pad;
801 sc->pg_bd_mbuf_alloc_size = MCLBYTES;

--- 11 unchanged lines hidden (view full) ---

813 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
814 ifp->if_baudrate = IF_Mbps(2500ULL);
815 else
816 ifp->if_baudrate = IF_Mbps(1000);
817
818 /* Check for an MII child bus by probing the PHY. */
819 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
820 bce_ifmedia_sts)) {
990#ifdef BCE_USE_SPLIT_HEADER
991 sc->rx_bd_mbuf_alloc_size = MHLEN;
992 /* Make sure offset is 16 byte aligned for hardware. */
993 sc->rx_bd_mbuf_align_pad = roundup2((MSIZE - MHLEN), 16) -
994 (MSIZE - MHLEN);
995 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
996 sc->rx_bd_mbuf_align_pad;
997 sc->pg_bd_mbuf_alloc_size = MCLBYTES;

--- 11 unchanged lines hidden (view full) ---

1009 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1010 ifp->if_baudrate = IF_Mbps(2500ULL);
1011 else
1012 ifp->if_baudrate = IF_Mbps(1000);
1013
1014 /* Check for an MII child bus by probing the PHY. */
1015 if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
1016 bce_ifmedia_sts)) {
821 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
1017 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
822 __FILE__, __LINE__);
823 rc = ENXIO;
824 goto bce_attach_fail;
825 }
826
827 /* Attach to the Ethernet interface list. */
828 ether_ifattach(ifp, sc->eaddr);
829
830#if __FreeBSD_version < 500000
831 callout_init(&sc->bce_tick_callout);
832 callout_init(&sc->bce_pulse_callout);
833#else
834 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
835 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
836#endif
837
838 /* Hookup IRQ last. */
1018 __FILE__, __LINE__);
1019 rc = ENXIO;
1020 goto bce_attach_fail;
1021 }
1022
1023 /* Attach to the Ethernet interface list. */
1024 ether_ifattach(ifp, sc->eaddr);
1025
1026#if __FreeBSD_version < 500000
1027 callout_init(&sc->bce_tick_callout);
1028 callout_init(&sc->bce_pulse_callout);
1029#else
1030 callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1031 callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1032#endif
1033
1034 /* Hookup IRQ last. */
839 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE, NULL,
840 bce_intr, sc, &sc->bce_intrhand);
1035 rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1036 NULL, bce_intr, sc, &sc->bce_intrhand);
841
842 if (rc) {
1037
1038 if (rc) {
843 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1039 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
844 __FILE__, __LINE__);
845 bce_detach(dev);
846 goto bce_attach_exit;
847 }
848
1040 __FILE__, __LINE__);
1041 bce_detach(dev);
1042 goto bce_attach_exit;
1043 }
1044
849 /*
850 * At this point we've acquired all the resources
1045 /*
1046 * At this point we've acquired all the resources
851 * we need to run so there's no turning back, we're
852 * cleared for launch.
853 */
854
855 /* Print some important debugging info. */
856 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
857
858 /* Add the supported sysctls to the kernel. */
859 bce_add_sysctls(sc);
860
861 BCE_LOCK(sc);
1047 * we need to run so there's no turning back, we're
1048 * cleared for launch.
1049 */
1050
1051 /* Print some important debugging info. */
1052 DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1053
1054 /* Add the supported sysctls to the kernel. */
1055 bce_add_sysctls(sc);
1056
1057 BCE_LOCK(sc);
862 /*
1058 /*
863 * The chip reset earlier notified the bootcode that
864 * a driver is present. We now need to start our pulse
865 * routine so that the bootcode is reminded that we're
866 * still running.
867 */
868 bce_pulse(sc);
869
870 bce_mgmt_init_locked(sc);
871 BCE_UNLOCK(sc);
872
873 /* Finally, print some useful adapter info */
1059 * The chip reset earlier notified the bootcode that
1060 * a driver is present. We now need to start our pulse
1061 * routine so that the bootcode is reminded that we're
1062 * still running.
1063 */
1064 bce_pulse(sc);
1065
1066 bce_mgmt_init_locked(sc);
1067 BCE_UNLOCK(sc);
1068
1069 /* Finally, print some useful adapter info */
874 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
875 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
876 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
877 printf("Bus (PCI%s, %s, %dMHz); ",
878 ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
879 ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
880 sc->bus_speed_mhz);
881 printf("F/W (0x%08X); Flags( ", sc->bce_fw_ver);
882#ifdef BCE_USE_SPLIT_HEADER
883 printf("SPLT ");
884#endif
885 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
886 printf("MFW ");
887 if (sc->bce_flags & BCE_USING_MSI_FLAG)
888 printf("MSI ");
889 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
890 printf("2.5G ");
891 printf(")\n");
892
1070 bce_print_adapter_info(sc);
893 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
894 __FUNCTION__, sc);
895
896 goto bce_attach_exit;
897
898bce_attach_fail:
899 bce_release_resources(sc);
900
901bce_attach_exit:
902
1071 DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1072 __FUNCTION__, sc);
1073
1074 goto bce_attach_exit;
1075
1076bce_attach_fail:
1077 bce_release_resources(sc);
1078
1079bce_attach_exit:
1080
903 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
1081 DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
904
905 return(rc);
906}
907
908
909/****************************************************************************/
910/* Device detach function. */
911/* */

--- 4 unchanged lines hidden (view full) ---

916/****************************************************************************/
917static int
918bce_detach(device_t dev)
919{
920 struct bce_softc *sc = device_get_softc(dev);
921 struct ifnet *ifp;
922 u32 msg;
923
1082
1083 return(rc);
1084}
1085
1086
1087/****************************************************************************/
1088/* Device detach function. */
1089/* */

--- 4 unchanged lines hidden (view full) ---

1094/****************************************************************************/
1095static int
1096bce_detach(device_t dev)
1097{
1098 struct bce_softc *sc = device_get_softc(dev);
1099 struct ifnet *ifp;
1100 u32 msg;
1101
924 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
1102 DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
925
926 ifp = sc->bce_ifp;
927
928 /* Stop and reset the controller. */
929 BCE_LOCK(sc);
930
931 /* Stop the pulse so the bootcode can go to driver absent state. */
932 callout_stop(&sc->bce_pulse_callout);

--- 11 unchanged lines hidden (view full) ---

944
945 /* If we have a child device on the MII bus remove it too. */
946 bus_generic_detach(dev);
947 device_delete_child(dev, sc->bce_miibus);
948
949 /* Release all remaining resources. */
950 bce_release_resources(sc);
951
1103
1104 ifp = sc->bce_ifp;
1105
1106 /* Stop and reset the controller. */
1107 BCE_LOCK(sc);
1108
1109 /* Stop the pulse so the bootcode can go to driver absent state. */
1110 callout_stop(&sc->bce_pulse_callout);

--- 11 unchanged lines hidden (view full) ---

1122
1123 /* If we have a child device on the MII bus remove it too. */
1124 bus_generic_detach(dev);
1125 device_delete_child(dev, sc->bce_miibus);
1126
1127 /* Release all remaining resources. */
1128 bce_release_resources(sc);
1129
952 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
1130 DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
953
954 return(0);
955}
956
957
958/****************************************************************************/
959/* Device shutdown function. */
960/* */
961/* Stops and resets the controller. */
962/* */
963/* Returns: */
964/* 0 on success, positive value on failure. */
965/****************************************************************************/
966static int
967bce_shutdown(device_t dev)
968{
969 struct bce_softc *sc = device_get_softc(dev);
970 u32 msg;
971
1131
1132 return(0);
1133}
1134
1135
1136/****************************************************************************/
1137/* Device shutdown function. */
1138/* */
1139/* Stops and resets the controller. */
1140/* */
1141/* Returns: */
1142/* 0 on success, positive value on failure. */
1143/****************************************************************************/
1144static int
1145bce_shutdown(device_t dev)
1146{
1147 struct bce_softc *sc = device_get_softc(dev);
1148 u32 msg;
1149
972 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Entering %s()\n", __FUNCTION__);
1150 DBENTER(BCE_VERBOSE);
973
974 BCE_LOCK(sc);
975 bce_stop(sc);
976 if (sc->bce_flags & BCE_NO_WOL_FLAG)
977 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
978 else
979 msg = BCE_DRV_MSG_CODE_UNLOAD;
980 bce_reset(sc, msg);
981 BCE_UNLOCK(sc);
1151
1152 BCE_LOCK(sc);
1153 bce_stop(sc);
1154 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1155 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1156 else
1157 msg = BCE_DRV_MSG_CODE_UNLOAD;
1158 bce_reset(sc, msg);
1159 BCE_UNLOCK(sc);
982
983 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Exiting %s()\n", __FUNCTION__);
984
1160
1161 DBEXIT(BCE_VERBOSE);
1162
985 return (0);
986}
987
988
1163 return (0);
1164}
1165
1166
1167#ifdef BCE_DEBUG
989/****************************************************************************/
1168/****************************************************************************/
1169/* Register read. */
1170/* */
1171/* Returns: */
1172/* The value of the register. */
1173/****************************************************************************/
1174static u32
1175bce_reg_rd(struct bce_softc *sc, u32 offset)
1176{
1177 u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
1178 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1179 __FUNCTION__, offset, val);
1180 return val;
1181}
1182
1183
1184/****************************************************************************/
1185/* Register write (16 bit). */
1186/* */
1187/* Returns: */
1188/* Nothing. */
1189/****************************************************************************/
1190static void
1191bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1192{
1193 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1194 __FUNCTION__, offset, val);
1195 bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
1196}
1197
1198
1199/****************************************************************************/
1200/* Register write. */
1201/* */
1202/* Returns: */
1203/* Nothing. */
1204/****************************************************************************/
1205static void
1206bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1207{
1208 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1209 __FUNCTION__, offset, val);
1210 bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
1211}
1212#endif
1213
1214/****************************************************************************/
990/* Indirect register read. */
991/* */
992/* Reads NetXtreme II registers using an index/data register pair in PCI */
993/* configuration space. Using this mechanism avoids issues with posted */
994/* reads but is much slower than memory-mapped I/O. */
995/* */
996/* Returns: */
997/* The value of the register. */

--- 4 unchanged lines hidden (view full) ---

1002 device_t dev;
1003 dev = sc->bce_dev;
1004
1005 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1006#ifdef BCE_DEBUG
1007 {
1008 u32 val;
1009 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1215/* Indirect register read. */
1216/* */
1217/* Reads NetXtreme II registers using an index/data register pair in PCI */
1218/* configuration space. Using this mechanism avoids issues with posted */
1219/* reads but is much slower than memory-mapped I/O. */
1220/* */
1221/* Returns: */
1222/* The value of the register. */

--- 4 unchanged lines hidden (view full) ---

1227 device_t dev;
1228 dev = sc->bce_dev;
1229
1230 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1231#ifdef BCE_DEBUG
1232 {
1233 u32 val;
1234 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1010 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1235 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1011 __FUNCTION__, offset, val);
1012 return val;
1013 }
1014#else
1015 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1016#endif
1017}
1018

--- 9 unchanged lines hidden (view full) ---

1028/* Nothing. */
1029/****************************************************************************/
1030static void
1031bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1032{
1033 device_t dev;
1034 dev = sc->bce_dev;
1035
1236 __FUNCTION__, offset, val);
1237 return val;
1238 }
1239#else
1240 return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1241#endif
1242}
1243

--- 9 unchanged lines hidden (view full) ---

1253/* Nothing. */
1254/****************************************************************************/
1255static void
1256bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1257{
1258 device_t dev;
1259 dev = sc->bce_dev;
1260
1036 DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1261 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1037 __FUNCTION__, offset, val);
1038
1039 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1040 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1041}
1042
1043
1044#ifdef BCE_DEBUG
1045/****************************************************************************/
1046/* Context memory read. */
1047/* */
1048/* The NetXtreme II controller uses context memory to track connection */
1049/* information for L2 and higher network protocols. */
1050/* */
1051/* Returns: */
1052/* The requested 32 bit value of context memory. */
1053/****************************************************************************/
1054static u32
1262 __FUNCTION__, offset, val);
1263
1264 pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1265 pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1266}
1267
1268
1269#ifdef BCE_DEBUG
1270/****************************************************************************/
1271/* Context memory read. */
1272/* */
1273/* The NetXtreme II controller uses context memory to track connection */
1274/* information for L2 and higher network protocols. */
1275/* */
1276/* Returns: */
1277/* The requested 32 bit value of context memory. */
1278/****************************************************************************/
1279static u32
1055bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 offset)
1280bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1056{
1281{
1057 u32 val;
1282 u32 idx, offset, retry_cnt = 5, val;
1058
1283
1059 offset += cid_addr;
1060 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1061 val = REG_RD(sc, BCE_CTX_DATA);
1284 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1285 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1286 __FUNCTION__, cid_addr));
1062
1287
1063 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1064 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val);
1288 offset = ctx_offset + cid_addr;
1065
1289
1290 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1291
1292 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1293
1294 for (idx = 0; idx < retry_cnt; idx++) {
1295 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1296 if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1297 break;
1298 DELAY(5);
1299 }
1300
1301 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1302 BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1303 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1304 __FILE__, __LINE__, cid_addr, ctx_offset);
1305
1306 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1307 } else {
1308 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1309 val = REG_RD(sc, BCE_CTX_DATA);
1310 }
1311
1312 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1313 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1314
1066 return(val);
1067}
1068#endif
1069
1070
1071/****************************************************************************/
1072/* Context memory write. */
1073/* */
1074/* The NetXtreme II controller uses context memory to track connection */
1075/* information for L2 and higher network protocols. */
1076/* */
1077/* Returns: */
1078/* Nothing. */
1079/****************************************************************************/
1080static void
1315 return(val);
1316}
1317#endif
1318
1319
1320/****************************************************************************/
1321/* Context memory write. */
1322/* */
1323/* The NetXtreme II controller uses context memory to track connection */
1324/* information for L2 and higher network protocols. */
1325/* */
1326/* Returns: */
1327/* Nothing. */
1328/****************************************************************************/
1329static void
1081bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 offset, u32 val)
1330bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1082{
1331{
1332 u32 idx, offset = ctx_offset + cid_addr;
1333 u32 val, retry_cnt = 5;
1083
1334
1084 DBPRINT(sc, BCE_EXCESSIVE, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1085 "val = 0x%08X\n", __FUNCTION__, cid_addr, offset, val);
1335 DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1336 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1086
1337
1087 offset += cid_addr;
1088 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1089 REG_WR(sc, BCE_CTX_DATA, val);
1338 DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1339 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1340 __FUNCTION__, cid_addr));
1341
1342 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1343
1344 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1345 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1346
1347 for (idx = 0; idx < retry_cnt; idx++) {
1348 val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1349 if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1350 break;
1351 DELAY(5);
1352 }
1353
1354 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1355 BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1356 "cid_addr = 0x%08X, offset = 0x%08X!\n",
1357 __FILE__, __LINE__, cid_addr, ctx_offset);
1358
1359 } else {
1360 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1361 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1362 }
1090}
1091
1092
1093/****************************************************************************/
1094/* PHY register read. */
1095/* */
1096/* Implements register reads on the MII bus. */
1097/* */

--- 6 unchanged lines hidden (view full) ---

1104 struct bce_softc *sc;
1105 u32 val;
1106 int i;
1107
1108 sc = device_get_softc(dev);
1109
1110 /* Make sure we are accessing the correct PHY address. */
1111 if (phy != sc->bce_phy_addr) {
1363}
1364
1365
1366/****************************************************************************/
1367/* PHY register read. */
1368/* */
1369/* Implements register reads on the MII bus. */
1370/* */

--- 6 unchanged lines hidden (view full) ---

1377 struct bce_softc *sc;
1378 u32 val;
1379 int i;
1380
1381 sc = device_get_softc(dev);
1382
1383 /* Make sure we are accessing the correct PHY address. */
1384 if (phy != sc->bce_phy_addr) {
1112 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY read!\n", phy);
1385 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY read!\n", phy);
1113 return(0);
1114 }
1115
1116 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1117 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1118 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1119
1120 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1121 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1122
1123 DELAY(40);
1124 }
1125
1386 return(0);
1387 }
1388
1389 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1390 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1391 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1392
1393 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1394 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1395
1396 DELAY(40);
1397 }
1398
1399
1126 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1127 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1128 BCE_EMAC_MDIO_COMM_START_BUSY;
1129 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1130
1131 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1132 DELAY(10);
1133

--- 11 unchanged lines hidden (view full) ---

1145 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1146 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1147 __FILE__, __LINE__, phy, reg);
1148 val = 0x0;
1149 } else {
1150 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1151 }
1152
1400 val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1401 BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1402 BCE_EMAC_MDIO_COMM_START_BUSY;
1403 REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1404
1405 for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1406 DELAY(10);
1407

--- 11 unchanged lines hidden (view full) ---

1419 if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1420 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1421 __FILE__, __LINE__, phy, reg);
1422 val = 0x0;
1423 } else {
1424 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1425 }
1426
1153 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1154 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);
1155
1156 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1157 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1158 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1159
1160 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1161 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1162
1163 DELAY(40);
1164 }
1165
1427
1428 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1429 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1430 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1431
1432 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1433 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1434
1435 DELAY(40);
1436 }
1437
1438 DB_PRINT_PHY_REG(reg, val);
1166 return (val & 0xffff);
1167
1168}
1169
1170
1171/****************************************************************************/
1172/* PHY register write. */
1173/* */

--- 8 unchanged lines hidden (view full) ---

1182 struct bce_softc *sc;
1183 u32 val1;
1184 int i;
1185
1186 sc = device_get_softc(dev);
1187
1188 /* Make sure we are accessing the correct PHY address. */
1189 if (phy != sc->bce_phy_addr) {
1439 return (val & 0xffff);
1440
1441}
1442
1443
1444/****************************************************************************/
1445/* PHY register write. */
1446/* */

--- 8 unchanged lines hidden (view full) ---

1455 struct bce_softc *sc;
1456 u32 val1;
1457 int i;
1458
1459 sc = device_get_softc(dev);
1460
1461 /* Make sure we are accessing the correct PHY address. */
1462 if (phy != sc->bce_phy_addr) {
1190 DBPRINT(sc, BCE_EXCESSIVE_PHY, "Invalid PHY address %d for PHY write!\n", phy);
1463 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d for PHY write!\n", phy);
1191 return(0);
1192 }
1193
1464 return(0);
1465 }
1466
1194 DBPRINT(sc, BCE_EXCESSIVE, "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1195 __FUNCTION__, phy, (u16) reg & 0xffff, (u16) val & 0xffff);
1467 DB_PRINT_PHY_REG(reg, val);
1196
1197 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1198 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1199 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1200
1201 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1202 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1203

--- 11 unchanged lines hidden (view full) ---

1215 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1216 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1217 DELAY(5);
1218 break;
1219 }
1220 }
1221
1222 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1468
1469 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1470 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1471 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1472
1473 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1474 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1475

--- 11 unchanged lines hidden (view full) ---

1487 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1488 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1489 DELAY(5);
1490 break;
1491 }
1492 }
1493
1494 if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1223 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1495 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1224 __FILE__, __LINE__);
1225
1226 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1227 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1228 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1229
1230 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1231 REG_RD(sc, BCE_EMAC_MDIO_MODE);

--- 18 unchanged lines hidden (view full) ---

1250bce_miibus_statchg(device_t dev)
1251{
1252 struct bce_softc *sc;
1253 struct mii_data *mii;
1254 int val;
1255
1256 sc = device_get_softc(dev);
1257
1496 __FILE__, __LINE__);
1497
1498 if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1499 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1500 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1501
1502 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1503 REG_RD(sc, BCE_EMAC_MDIO_MODE);

--- 18 unchanged lines hidden (view full) ---

1522bce_miibus_statchg(device_t dev)
1523{
1524 struct bce_softc *sc;
1525 struct mii_data *mii;
1526 int val;
1527
1528 sc = device_get_softc(dev);
1529
1530 DBENTER(BCE_VERBOSE_PHY);
1531
1258 mii = device_get_softc(sc->bce_miibus);
1259
1260 val = REG_RD(sc, BCE_EMAC_MODE);
1532 mii = device_get_softc(sc->bce_miibus);
1533
1534 val = REG_RD(sc, BCE_EMAC_MODE);
1261 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
1262 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
1535 val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
1536 BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
1263 BCE_EMAC_MODE_25G);
1264
1265 /* Set MII or GMII interface based on the speed negotiated by the PHY. */
1266 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1267 case IFM_10_T:
1268 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1269 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n");
1270 val |= BCE_EMAC_MODE_PORT_MII_10;

--- 32 unchanged lines hidden (view full) ---

1303 /* ToDo: Enable flow control support in brgphy and bge. */
1304 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
1305 if (mii->mii_media_active & IFM_FLAG0)
1306 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1307 if (mii->mii_media_active & IFM_FLAG1)
1308 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1309#endif
1310
1537 BCE_EMAC_MODE_25G);
1538
1539 /* Set MII or GMII interface based on the speed negotiated by the PHY. */
1540 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1541 case IFM_10_T:
1542 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1543 DBPRINT(sc, BCE_INFO, "Enabling 10Mb interface.\n");
1544 val |= BCE_EMAC_MODE_PORT_MII_10;

--- 32 unchanged lines hidden (view full) ---

1577 /* ToDo: Enable flow control support in brgphy and bge. */
1578 /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
1579 if (mii->mii_media_active & IFM_FLAG0)
1580 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1581 if (mii->mii_media_active & IFM_FLAG1)
1582 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1583#endif
1584
1585 DBEXIT(BCE_VERBOSE_PHY);
1311}
1312
1313
1314/****************************************************************************/
1315/* Acquire NVRAM lock. */
1316/* */
1317/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1318/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1319/* for use by the driver. */
1320/* */
1321/* Returns: */
1322/* 0 on success, positive value on failure. */
1323/****************************************************************************/
1324static int
1325bce_acquire_nvram_lock(struct bce_softc *sc)
1326{
1327 u32 val;
1586}
1587
1588
1589/****************************************************************************/
1590/* Acquire NVRAM lock. */
1591/* */
1592/* Before the NVRAM can be accessed the caller must acquire an NVRAM lock. */
1593/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1594/* for use by the driver. */
1595/* */
1596/* Returns: */
1597/* 0 on success, positive value on failure. */
1598/****************************************************************************/
1599static int
1600bce_acquire_nvram_lock(struct bce_softc *sc)
1601{
1602 u32 val;
1328 int j;
1603 int j, rc = 0;
1329
1604
1330 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Acquiring NVRAM lock.\n");
1605 DBENTER(BCE_VERBOSE_NVRAM);
1331
1332 /* Request access to the flash interface. */
1333 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1334 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1335 val = REG_RD(sc, BCE_NVM_SW_ARB);
1336 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1337 break;
1338
1339 DELAY(5);
1340 }
1341
1342 if (j >= NVRAM_TIMEOUT_COUNT) {
1343 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1606
1607 /* Request access to the flash interface. */
1608 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1609 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1610 val = REG_RD(sc, BCE_NVM_SW_ARB);
1611 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1612 break;
1613
1614 DELAY(5);
1615 }
1616
1617 if (j >= NVRAM_TIMEOUT_COUNT) {
1618 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1344 return EBUSY;
1619 rc = EBUSY;
1345 }
1346
1620 }
1621
1347 return 0;
1622 DBEXIT(BCE_VERBOSE_NVRAM);
1623 return (rc);
1348}
1349
1350
1351/****************************************************************************/
1352/* Release NVRAM lock. */
1353/* */
1354/* When the caller is finished accessing NVRAM the lock must be released. */
1355/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1356/* for use by the driver. */
1357/* */
1358/* Returns: */
1359/* 0 on success, positive value on failure. */
1360/****************************************************************************/
1361static int
1362bce_release_nvram_lock(struct bce_softc *sc)
1363{
1624}
1625
1626
1627/****************************************************************************/
1628/* Release NVRAM lock. */
1629/* */
1630/* When the caller is finished accessing NVRAM the lock must be released. */
1631/* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is */
1632/* for use by the driver. */
1633/* */
1634/* Returns: */
1635/* 0 on success, positive value on failure. */
1636/****************************************************************************/
1637static int
1638bce_release_nvram_lock(struct bce_softc *sc)
1639{
1364 int j;
1365 u32 val;
1640 u32 val;
1641 int j, rc = 0;
1366
1642
1367 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Releasing NVRAM lock.\n");
1643 DBENTER(BCE_VERBOSE_NVRAM);
1368
1369 /*
1370 * Relinquish nvram interface.
1371 */
1372 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1373
1374 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1375 val = REG_RD(sc, BCE_NVM_SW_ARB);
1376 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1377 break;
1378
1379 DELAY(5);
1380 }
1381
1382 if (j >= NVRAM_TIMEOUT_COUNT) {
1644
1645 /*
1646 * Relinquish nvram interface.
1647 */
1648 REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1649
1650 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1651 val = REG_RD(sc, BCE_NVM_SW_ARB);
1652 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1653 break;
1654
1655 DELAY(5);
1656 }
1657
1658 if (j >= NVRAM_TIMEOUT_COUNT) {
1383 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1384 return EBUSY;
1659 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
1660 rc = EBUSY;
1385 }
1386
1661 }
1662
1387 return 0;
1663 DBEXIT(BCE_VERBOSE_NVRAM);
1664 return (rc);
1388}
1389
1390
1391#ifdef BCE_NVRAM_WRITE_SUPPORT
1392/****************************************************************************/
1393/* Enable NVRAM write access. */
1394/* */
1395/* Before writing to NVRAM the caller must enable NVRAM writes. */
1396/* */
1397/* Returns: */
1398/* 0 on success, positive value on failure. */
1399/****************************************************************************/
1400static int
1401bce_enable_nvram_write(struct bce_softc *sc)
1402{
1403 u32 val;
1665}
1666
1667
1668#ifdef BCE_NVRAM_WRITE_SUPPORT
1669/****************************************************************************/
1670/* Enable NVRAM write access. */
1671/* */
1672/* Before writing to NVRAM the caller must enable NVRAM writes. */
1673/* */
1674/* Returns: */
1675/* 0 on success, positive value on failure. */
1676/****************************************************************************/
1677static int
1678bce_enable_nvram_write(struct bce_softc *sc)
1679{
1680 u32 val;
1681 int rc = 0;
1404
1682
1405 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM write.\n");
1683 DBENTER(BCE_VERBOSE_NVRAM);
1406
1407 val = REG_RD(sc, BCE_MISC_CFG);
1408 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1409
1684
1685 val = REG_RD(sc, BCE_MISC_CFG);
1686 REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1687
1410 if (!sc->bce_flash_info->buffered) {
1688 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
1411 int j;
1412
1413 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1414 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1415
1416 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1417 DELAY(5);
1418
1419 val = REG_RD(sc, BCE_NVM_COMMAND);
1420 if (val & BCE_NVM_COMMAND_DONE)
1421 break;
1422 }
1423
1424 if (j >= NVRAM_TIMEOUT_COUNT) {
1425 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1689 int j;
1690
1691 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1692 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1693
1694 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1695 DELAY(5);
1696
1697 val = REG_RD(sc, BCE_NVM_COMMAND);
1698 if (val & BCE_NVM_COMMAND_DONE)
1699 break;
1700 }
1701
1702 if (j >= NVRAM_TIMEOUT_COUNT) {
1703 DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1426 return EBUSY;
1704 rc = EBUSY;
1427 }
1428 }
1705 }
1706 }
1429 return 0;
1707
1708 DBENTER(BCE_VERBOSE_NVRAM);
1709 return (rc);
1430}
1431
1432
1433/****************************************************************************/
1434/* Disable NVRAM write access. */
1435/* */
1436/* When the caller is finished writing to NVRAM write access must be */
1437/* disabled. */
1438/* */
1439/* Returns: */
1440/* Nothing. */
1441/****************************************************************************/
1442static void
1443bce_disable_nvram_write(struct bce_softc *sc)
1444{
1445 u32 val;
1446
1710}
1711
1712
1713/****************************************************************************/
1714/* Disable NVRAM write access. */
1715/* */
1716/* When the caller is finished writing to NVRAM write access must be */
1717/* disabled. */
1718/* */
1719/* Returns: */
1720/* Nothing. */
1721/****************************************************************************/
1722static void
1723bce_disable_nvram_write(struct bce_softc *sc)
1724{
1725 u32 val;
1726
1447 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM write.\n");
1727 DBENTER(BCE_VERBOSE_NVRAM);
1448
1449 val = REG_RD(sc, BCE_MISC_CFG);
1450 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1728
1729 val = REG_RD(sc, BCE_MISC_CFG);
1730 REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1731
1732 DBEXIT(BCE_VERBOSE_NVRAM);
1733
1451}
1452#endif
1453
1454
1455/****************************************************************************/
1456/* Enable NVRAM access. */
1457/* */
1458/* Before accessing NVRAM for read or write operations the caller must */
1459/* enabled NVRAM access. */
1460/* */
1461/* Returns: */
1462/* Nothing. */
1463/****************************************************************************/
1464static void
1465bce_enable_nvram_access(struct bce_softc *sc)
1466{
1467 u32 val;
1468
1734}
1735#endif
1736
1737
1738/****************************************************************************/
1739/* Enable NVRAM access. */
1740/* */
1741/* Before accessing NVRAM for read or write operations the caller must */
1742/* enabled NVRAM access. */
1743/* */
1744/* Returns: */
1745/* Nothing. */
1746/****************************************************************************/
1747static void
1748bce_enable_nvram_access(struct bce_softc *sc)
1749{
1750 u32 val;
1751
1469 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Enabling NVRAM access.\n");
1752 DBENTER(BCE_VERBOSE_NVRAM);
1470
1471 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1472 /* Enable both bits, even on read. */
1473 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1474 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1753
1754 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1755 /* Enable both bits, even on read. */
1756 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1757 val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1758
1759 DBEXIT(BCE_VERBOSE_NVRAM);
1475}
1476
1477
1478/****************************************************************************/
1479/* Disable NVRAM access. */
1480/* */
1481/* When the caller is finished accessing NVRAM access must be disabled. */
1482/* */
1483/* Returns: */
1484/* Nothing. */
1485/****************************************************************************/
1486static void
1487bce_disable_nvram_access(struct bce_softc *sc)
1488{
1489 u32 val;
1490
1760}
1761
1762
1763/****************************************************************************/
1764/* Disable NVRAM access. */
1765/* */
1766/* When the caller is finished accessing NVRAM access must be disabled. */
1767/* */
1768/* Returns: */
1769/* Nothing. */
1770/****************************************************************************/
1771static void
1772bce_disable_nvram_access(struct bce_softc *sc)
1773{
1774 u32 val;
1775
1491 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Disabling NVRAM access.\n");
1776 DBENTER(BCE_VERBOSE_NVRAM);
1492
1493 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1494
1495 /* Disable both bits, even after read. */
1496 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1497 val & ~(BCE_NVM_ACCESS_ENABLE_EN |
1498 BCE_NVM_ACCESS_ENABLE_WR_EN));
1777
1778 val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1779
1780 /* Disable both bits, even after read. */
1781 REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1782 val & ~(BCE_NVM_ACCESS_ENABLE_EN |
1783 BCE_NVM_ACCESS_ENABLE_WR_EN));
1784
1785 DBEXIT(BCE_VERBOSE_NVRAM);
1499}
1500
1501
1502#ifdef BCE_NVRAM_WRITE_SUPPORT
1503/****************************************************************************/
1504/* Erase NVRAM page before writing. */
1505/* */
1506/* Non-buffered flash parts require that a page be erased before it is */
1507/* written. */
1508/* */
1509/* Returns: */
1510/* 0 on success, positive value on failure. */
1511/****************************************************************************/
1512static int
1513bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
1514{
1515 u32 cmd;
1786}
1787
1788
1789#ifdef BCE_NVRAM_WRITE_SUPPORT
1790/****************************************************************************/
1791/* Erase NVRAM page before writing. */
1792/* */
1793/* Non-buffered flash parts require that a page be erased before it is */
1794/* written. */
1795/* */
1796/* Returns: */
1797/* 0 on success, positive value on failure. */
1798/****************************************************************************/
1799static int
1800bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
1801{
1802 u32 cmd;
1516 int j;
1803 int j, rc = 0;
1517
1804
1805 DBENTER(BCE_VERBOSE_NVRAM);
1806
1518 /* Buffered flash doesn't require an erase. */
1807 /* Buffered flash doesn't require an erase. */
1519 if (sc->bce_flash_info->buffered)
1520 return 0;
1808 if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
1809 goto bce_nvram_erase_page_exit;
1521
1810
1522 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Erasing NVRAM page.\n");
1523
1524 /* Build an erase command. */
1525 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1526 BCE_NVM_COMMAND_DOIT;
1527
1528 /*
1529 * Clear the DONE bit separately, set the NVRAM adress to erase,
1530 * and issue the erase command.
1531 */

--- 9 unchanged lines hidden (view full) ---

1541
1542 val = REG_RD(sc, BCE_NVM_COMMAND);
1543 if (val & BCE_NVM_COMMAND_DONE)
1544 break;
1545 }
1546
1547 if (j >= NVRAM_TIMEOUT_COUNT) {
1548 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1811 /* Build an erase command. */
1812 cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
1813 BCE_NVM_COMMAND_DOIT;
1814
1815 /*
1816 * Clear the DONE bit separately, set the NVRAM adress to erase,
1817 * and issue the erase command.
1818 */

--- 9 unchanged lines hidden (view full) ---

1828
1829 val = REG_RD(sc, BCE_NVM_COMMAND);
1830 if (val & BCE_NVM_COMMAND_DONE)
1831 break;
1832 }
1833
1834 if (j >= NVRAM_TIMEOUT_COUNT) {
1835 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
1549 return EBUSY;
1836 rc = EBUSY;
1550 }
1551
1837 }
1838
1552 return 0;
1839bce_nvram_erase_page_exit:
1840 DBEXIT(BCE_VERBOSE_NVRAM);
1841 return (rc);
1553}
1554#endif /* BCE_NVRAM_WRITE_SUPPORT */
1555
1556
1557/****************************************************************************/
1558/* Read a dword (32 bits) from NVRAM. */
1559/* */
1560/* Read a 32 bit word from NVRAM. The caller is assumed to have already */

--- 4 unchanged lines hidden (view full) ---

1565/****************************************************************************/
1566static int
1567bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val,
1568 u32 cmd_flags)
1569{
1570 u32 cmd;
1571 int i, rc = 0;
1572
1842}
1843#endif /* BCE_NVRAM_WRITE_SUPPORT */
1844
1845
1846/****************************************************************************/
1847/* Read a dword (32 bits) from NVRAM. */
1848/* */
1849/* Read a 32 bit word from NVRAM. The caller is assumed to have already */

--- 4 unchanged lines hidden (view full) ---

1854/****************************************************************************/
1855static int
1856bce_nvram_read_dword(struct bce_softc *sc, u32 offset, u8 *ret_val,
1857 u32 cmd_flags)
1858{
1859 u32 cmd;
1860 int i, rc = 0;
1861
1862 DBENTER(BCE_EXTREME_NVRAM);
1863
1573 /* Build the command word. */
1574 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1575
1864 /* Build the command word. */
1865 cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1866
1576 /* Calculate the offset for buffered flash. */
1577 if (sc->bce_flash_info->buffered) {
1867 /* Calculate the offset for buffered flash if translation is used. */
1868 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1578 offset = ((offset / sc->bce_flash_info->page_size) <<
1579 sc->bce_flash_info->page_bits) +
1580 (offset % sc->bce_flash_info->page_size);
1581 }
1582
1583 /*
1584 * Clear the DONE bit separately, set the address to read,
1585 * and issue the read.

--- 20 unchanged lines hidden (view full) ---

1606
1607 /* Check for errors. */
1608 if (i >= NVRAM_TIMEOUT_COUNT) {
1609 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n",
1610 __FILE__, __LINE__, offset);
1611 rc = EBUSY;
1612 }
1613
1869 offset = ((offset / sc->bce_flash_info->page_size) <<
1870 sc->bce_flash_info->page_bits) +
1871 (offset % sc->bce_flash_info->page_size);
1872 }
1873
1874 /*
1875 * Clear the DONE bit separately, set the address to read,
1876 * and issue the read.

--- 20 unchanged lines hidden (view full) ---

1897
1898 /* Check for errors. */
1899 if (i >= NVRAM_TIMEOUT_COUNT) {
1900 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at offset 0x%08X!\n",
1901 __FILE__, __LINE__, offset);
1902 rc = EBUSY;
1903 }
1904
1905 DBEXIT(BCE_EXTREME_NVRAM);
1614 return(rc);
1615}
1616
1617
1618#ifdef BCE_NVRAM_WRITE_SUPPORT
1619/****************************************************************************/
1620/* Write a dword (32 bits) to NVRAM. */
1621/* */

--- 4 unchanged lines hidden (view full) ---

1626/* Returns: */
1627/* 0 on success, positive value on failure. */
1628/****************************************************************************/
1629static int
1630bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
1631 u32 cmd_flags)
1632{
1633 u32 cmd, val32;
1906 return(rc);
1907}
1908
1909
1910#ifdef BCE_NVRAM_WRITE_SUPPORT
1911/****************************************************************************/
1912/* Write a dword (32 bits) to NVRAM. */
1913/* */

--- 4 unchanged lines hidden (view full) ---

1918/* Returns: */
1919/* 0 on success, positive value on failure. */
1920/****************************************************************************/
1921static int
1922bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
1923 u32 cmd_flags)
1924{
1925 u32 cmd, val32;
1634 int j;
1926 int j, rc = 0;
1635
1927
1928 DBENTER(BCE_VERBOSE_NVRAM);
1929
1636 /* Build the command word. */
1637 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1638
1930 /* Build the command word. */
1931 cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
1932
1639 /* Calculate the offset for buffered flash. */
1640 if (sc->bce_flash_info->buffered) {
1933 /* Calculate the offset for buffered flash if translation is used. */
1934 if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1641 offset = ((offset / sc->bce_flash_info->page_size) <<
1642 sc->bce_flash_info->page_bits) +
1643 (offset % sc->bce_flash_info->page_size);
1644 }
1645
1646 /*
1647 * Clear the DONE bit separately, convert NVRAM data to big-endian,
1648 * set the NVRAM address to write, and issue the write command

--- 10 unchanged lines hidden (view full) ---

1659 DELAY(5);
1660
1661 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1662 break;
1663 }
1664 if (j >= NVRAM_TIMEOUT_COUNT) {
1665 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n",
1666 __FILE__, __LINE__, offset);
1935 offset = ((offset / sc->bce_flash_info->page_size) <<
1936 sc->bce_flash_info->page_bits) +
1937 (offset % sc->bce_flash_info->page_size);
1938 }
1939
1940 /*
1941 * Clear the DONE bit separately, convert NVRAM data to big-endian,
1942 * set the NVRAM address to write, and issue the write command

--- 10 unchanged lines hidden (view full) ---

1953 DELAY(5);
1954
1955 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
1956 break;
1957 }
1958 if (j >= NVRAM_TIMEOUT_COUNT) {
1959 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at offset 0x%08X\n",
1960 __FILE__, __LINE__, offset);
1667 return EBUSY;
1961 rc = EBUSY;
1668 }
1669
1962 }
1963
1670 return 0;
1964 DBEXIT(BCE_VERBOSE_NVRAM);
1965 return (rc);
1671}
1672#endif /* BCE_NVRAM_WRITE_SUPPORT */
1673
1674
1675/****************************************************************************/
1676/* Initialize NVRAM access. */
1677/* */
1678/* Identify the NVRAM device in use and prepare the NVRAM interface to */
1679/* access that device. */
1680/* */
1681/* Returns: */
1682/* 0 on success, positive value on failure. */
1683/****************************************************************************/
1684static int
1685bce_init_nvram(struct bce_softc *sc)
1686{
1687 u32 val;
1966}
1967#endif /* BCE_NVRAM_WRITE_SUPPORT */
1968
1969
1970/****************************************************************************/
1971/* Initialize NVRAM access. */
1972/* */
1973/* Identify the NVRAM device in use and prepare the NVRAM interface to */
1974/* access that device. */
1975/* */
1976/* Returns: */
1977/* 0 on success, positive value on failure. */
1978/****************************************************************************/
1979static int
1980bce_init_nvram(struct bce_softc *sc)
1981{
1982 u32 val;
1688 int j, entry_count, rc;
1983 int j, entry_count, rc = 0;
1689 struct flash_spec *flash;
1690
1984 struct flash_spec *flash;
1985
1691 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Entering %s()\n", __FUNCTION__);
1986 DBENTER(BCE_VERBOSE_NVRAM);
1692
1987
1988 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1989 sc->bce_flash_info = &flash_5709;
1990 goto bce_init_nvram_get_flash_size;
1991 }
1992
1693 /* Determine the selected interface. */
1694 val = REG_RD(sc, BCE_NVM_CFG1);
1695
1696 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1697
1993 /* Determine the selected interface. */
1994 val = REG_RD(sc, BCE_NVM_CFG1);
1995
1996 entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1997
1698 rc = 0;
1699
1700 /*
1701 * Flash reconfiguration is required to support additional
1702 * NVRAM devices not directly supported in hardware.
1703 * Check if the flash interface was reconfigured
1704 * by the bootcode.
1705 */
1706
1707 if (val & 0x40000000) {
1708 /* Flash interface reconfigured by bootcode. */
1709
1998 /*
1999 * Flash reconfiguration is required to support additional
2000 * NVRAM devices not directly supported in hardware.
2001 * Check if the flash interface was reconfigured
2002 * by the bootcode.
2003 */
2004
2005 if (val & 0x40000000) {
2006 /* Flash interface reconfigured by bootcode. */
2007
1710 DBPRINT(sc,BCE_INFO_LOAD,
2008 DBPRINT(sc,BCE_INFO_LOAD,
1711 "bce_init_nvram(): Flash WAS reconfigured.\n");
1712
1713 for (j = 0, flash = &flash_table[0]; j < entry_count;
1714 j++, flash++) {
1715 if ((val & FLASH_BACKUP_STRAP_MASK) ==
1716 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1717 sc->bce_flash_info = flash;
1718 break;
1719 }
1720 }
1721 } else {
1722 /* Flash interface not yet reconfigured. */
1723 u32 mask;
1724
2009 "bce_init_nvram(): Flash WAS reconfigured.\n");
2010
2011 for (j = 0, flash = &flash_table[0]; j < entry_count;
2012 j++, flash++) {
2013 if ((val & FLASH_BACKUP_STRAP_MASK) ==
2014 (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2015 sc->bce_flash_info = flash;
2016 break;
2017 }
2018 }
2019 } else {
2020 /* Flash interface not yet reconfigured. */
2021 u32 mask;
2022
1725 DBPRINT(sc,BCE_INFO_LOAD,
1726 "bce_init_nvram(): Flash was NOT reconfigured.\n");
2023 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2024 __FUNCTION__);
1727
1728 if (val & (1 << 23))
1729 mask = FLASH_BACKUP_STRAP_MASK;
1730 else
1731 mask = FLASH_STRAP_MASK;
1732
1733 /* Look for the matching NVRAM device configuration data. */
1734 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {

--- 19 unchanged lines hidden (view full) ---

1754 break;
1755 }
1756 }
1757 }
1758
1759 /* Check if a matching device was found. */
1760 if (j == entry_count) {
1761 sc->bce_flash_info = NULL;
2025
2026 if (val & (1 << 23))
2027 mask = FLASH_BACKUP_STRAP_MASK;
2028 else
2029 mask = FLASH_STRAP_MASK;
2030
2031 /* Look for the matching NVRAM device configuration data. */
2032 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {

--- 19 unchanged lines hidden (view full) ---

2052 break;
2053 }
2054 }
2055 }
2056
2057 /* Check if a matching device was found. */
2058 if (j == entry_count) {
2059 sc->bce_flash_info = NULL;
1762 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2060 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
1763 __FILE__, __LINE__);
1764 rc = ENODEV;
1765 }
1766
2061 __FILE__, __LINE__);
2062 rc = ENODEV;
2063 }
2064
2065bce_init_nvram_get_flash_size:
1767 /* Write the flash config data to the shared memory interface. */
1768 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2);
1769 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1770 if (val)
1771 sc->bce_flash_size = val;
1772 else
1773 sc->bce_flash_size = sc->bce_flash_info->total_size;
1774
2066 /* Write the flash config data to the shared memory interface. */
2067 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_SHARED_HW_CFG_CONFIG2);
2068 val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2069 if (val)
2070 sc->bce_flash_size = val;
2071 else
2072 sc->bce_flash_size = sc->bce_flash_info->total_size;
2073
1775 DBPRINT(sc, BCE_INFO_LOAD, "bce_init_nvram() flash->total_size = 0x%08X\n",
2074 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2075 __FUNCTION__, sc->bce_flash_info->name,
1776 sc->bce_flash_info->total_size);
1777
2076 sc->bce_flash_info->total_size);
2077
1778 DBPRINT(sc, BCE_VERBOSE_NVRAM, "Exiting %s()\n", __FUNCTION__);
1779
2078 DBEXIT(BCE_VERBOSE_NVRAM);
1780 return rc;
1781}
1782
1783
1784/****************************************************************************/
1785/* Read an arbitrary range of data from NVRAM. */
1786/* */
1787/* Prepares the NVRAM interface for access and reads the requested data */

--- 4 unchanged lines hidden (view full) ---

1792/****************************************************************************/
1793static int
1794bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
1795 int buf_size)
1796{
1797 int rc = 0;
1798 u32 cmd_flags, offset32, len32, extra;
1799
2079 return rc;
2080}
2081
2082
2083/****************************************************************************/
2084/* Read an arbitrary range of data from NVRAM. */
2085/* */
2086/* Prepares the NVRAM interface for access and reads the requested data */

--- 4 unchanged lines hidden (view full) ---

2091/****************************************************************************/
2092static int
2093bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2094 int buf_size)
2095{
2096 int rc = 0;
2097 u32 cmd_flags, offset32, len32, extra;
2098
2099 DBENTER(BCE_VERBOSE_NVRAM);
2100
1800 if (buf_size == 0)
2101 if (buf_size == 0)
1801 return 0;
2102 goto bce_nvram_read_exit;
1802
1803 /* Request access to the flash interface. */
1804 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2103
2104 /* Request access to the flash interface. */
2105 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
1805 return rc;
2106 goto bce_nvram_read_exit;
1806
1807 /* Enable access to flash interface */
1808 bce_enable_nvram_access(sc);
1809
1810 len32 = buf_size;
1811 offset32 = offset;
1812 extra = 0;
1813

--- 65 unchanged lines hidden (view full) ---

1879
1880 /* Advance to the next dword. */
1881 offset32 += 4;
1882 ret_buf += 4;
1883 len32 -= 4;
1884 }
1885
1886 if (rc)
2107
2108 /* Enable access to flash interface */
2109 bce_enable_nvram_access(sc);
2110
2111 len32 = buf_size;
2112 offset32 = offset;
2113 extra = 0;
2114

--- 65 unchanged lines hidden (view full) ---

2180
2181 /* Advance to the next dword. */
2182 offset32 += 4;
2183 ret_buf += 4;
2184 len32 -= 4;
2185 }
2186
2187 if (rc)
1887 return rc;
2188 goto bce_nvram_read_locked_exit;
1888
1889 cmd_flags = BCE_NVM_COMMAND_LAST;
1890 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1891
1892 memcpy(ret_buf, buf, 4 - extra);
1893 }
1894
2189
2190 cmd_flags = BCE_NVM_COMMAND_LAST;
2191 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2192
2193 memcpy(ret_buf, buf, 4 - extra);
2194 }
2195
2196bce_nvram_read_locked_exit:
1895 /* Disable access to flash interface and release the lock. */
1896 bce_disable_nvram_access(sc);
1897 bce_release_nvram_lock(sc);
1898
2197 /* Disable access to flash interface and release the lock. */
2198 bce_disable_nvram_access(sc);
2199 bce_release_nvram_lock(sc);
2200
2201bce_nvram_read_exit:
2202 DBEXIT(BCE_VERBOSE_NVRAM);
1899 return rc;
1900}
1901
1902
1903#ifdef BCE_NVRAM_WRITE_SUPPORT
1904/****************************************************************************/
1905/* Write an arbitrary range of data from NVRAM. */
1906/* */

--- 8 unchanged lines hidden (view full) ---

1915bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
1916 int buf_size)
1917{
1918 u32 written, offset32, len32;
1919 u8 *buf, start[4], end[4];
1920 int rc = 0;
1921 int align_start, align_end;
1922
2203 return rc;
2204}
2205
2206
2207#ifdef BCE_NVRAM_WRITE_SUPPORT
2208/****************************************************************************/
2209/* Write an arbitrary range of data from NVRAM. */
2210/* */

--- 8 unchanged lines hidden (view full) ---

2219bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2220 int buf_size)
2221{
2222 u32 written, offset32, len32;
2223 u8 *buf, start[4], end[4];
2224 int rc = 0;
2225 int align_start, align_end;
2226
2227 DBENTER(BCE_VERBOSE_NVRAM);
2228
1923 buf = data_buf;
1924 offset32 = offset;
1925 len32 = buf_size;
1926 align_start = align_end = 0;
1927
1928 if ((align_start = (offset32 & 3))) {
1929 offset32 &= ~3;
1930 len32 += align_start;
1931 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2229 buf = data_buf;
2230 offset32 = offset;
2231 len32 = buf_size;
2232 align_start = align_end = 0;
2233
2234 if ((align_start = (offset32 & 3))) {
2235 offset32 &= ~3;
2236 len32 += align_start;
2237 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
1932 return rc;
2238 goto bce_nvram_write_exit;
1933 }
1934
1935 if (len32 & 3) {
1936 if ((len32 > 4) || !align_start) {
1937 align_end = 4 - (len32 & 3);
1938 len32 += align_end;
1939 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
1940 end, 4))) {
2239 }
2240
2241 if (len32 & 3) {
2242 if ((len32 > 4) || !align_start) {
2243 align_end = 4 - (len32 & 3);
2244 len32 += align_end;
2245 if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2246 end, 4))) {
1941 return rc;
2247 goto bce_nvram_write_exit;
1942 }
1943 }
1944 }
1945
1946 if (align_start || align_end) {
1947 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2248 }
2249 }
2250 }
2251
2252 if (align_start || align_end) {
2253 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
1948 if (buf == 0)
1949 return ENOMEM;
2254 if (buf == 0) {
2255 rc = ENOMEM;
2256 goto bce_nvram_write_exit;
2257 }
2258
1950 if (align_start) {
1951 memcpy(buf, start, 4);
1952 }
2259 if (align_start) {
2260 memcpy(buf, start, 4);
2261 }
2262
1953 if (align_end) {
1954 memcpy(buf + len32 - 4, end, 4);
1955 }
1956 memcpy(buf + align_start, data_buf, buf_size);
1957 }
1958
1959 written = 0;
1960 while ((written < len32) && (rc == 0)) {

--- 10 unchanged lines hidden (view full) ---

1971 /* Find the data_start addr */
1972 data_start = (written == 0) ? offset32 : page_start;
1973 /* Find the data_end addr */
1974 data_end = (page_end > offset32 + len32) ?
1975 (offset32 + len32) : page_end;
1976
1977 /* Request access to the flash interface. */
1978 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2263 if (align_end) {
2264 memcpy(buf + len32 - 4, end, 4);
2265 }
2266 memcpy(buf + align_start, data_buf, buf_size);
2267 }
2268
2269 written = 0;
2270 while ((written < len32) && (rc == 0)) {

--- 10 unchanged lines hidden (view full) ---

2281 /* Find the data_start addr */
2282 data_start = (written == 0) ? offset32 : page_start;
2283 /* Find the data_end addr */
2284 data_end = (page_end > offset32 + len32) ?
2285 (offset32 + len32) : page_end;
2286
2287 /* Request access to the flash interface. */
2288 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
1979 goto nvram_write_end;
2289 goto bce_nvram_write_exit;
1980
1981 /* Enable access to flash interface */
1982 bce_enable_nvram_access(sc);
1983
1984 cmd_flags = BCE_NVM_COMMAND_FIRST;
2290
2291 /* Enable access to flash interface */
2292 bce_enable_nvram_access(sc);
2293
2294 cmd_flags = BCE_NVM_COMMAND_FIRST;
1985 if (sc->bce_flash_info->buffered == 0) {
2295 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
1986 int j;
1987
1988 /* Read the whole page into the buffer
1989 * (non-buffer flash only) */
1990 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
1991 if (j == (sc->bce_flash_info->page_size - 4)) {
1992 cmd_flags |= BCE_NVM_COMMAND_LAST;
1993 }
1994 rc = bce_nvram_read_dword(sc,
1995 page_start + j,
1996 &flash_buffer[j],
1997 cmd_flags);
1998
1999 if (rc)
2296 int j;
2297
2298 /* Read the whole page into the buffer
2299 * (non-buffer flash only) */
2300 for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2301 if (j == (sc->bce_flash_info->page_size - 4)) {
2302 cmd_flags |= BCE_NVM_COMMAND_LAST;
2303 }
2304 rc = bce_nvram_read_dword(sc,
2305 page_start + j,
2306 &flash_buffer[j],
2307 cmd_flags);
2308
2309 if (rc)
2000 goto nvram_write_end;
2310 goto bce_nvram_write_locked_exit;
2001
2002 cmd_flags = 0;
2003 }
2004 }
2005
2006 /* Enable writes to flash interface (unlock write-protect) */
2007 if ((rc = bce_enable_nvram_write(sc)) != 0)
2311
2312 cmd_flags = 0;
2313 }
2314 }
2315
2316 /* Enable writes to flash interface (unlock write-protect) */
2317 if ((rc = bce_enable_nvram_write(sc)) != 0)
2008 goto nvram_write_end;
2318 goto bce_nvram_write_locked_exit;
2009
2010 /* Erase the page */
2011 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2319
2320 /* Erase the page */
2321 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2012 goto nvram_write_end;
2322 goto bce_nvram_write_locked_exit;
2013
2014 /* Re-enable the write again for the actual write */
2015 bce_enable_nvram_write(sc);
2016
2017 /* Loop to write back the buffer data from page_start to
2018 * data_start */
2019 i = 0;
2323
2324 /* Re-enable the write again for the actual write */
2325 bce_enable_nvram_write(sc);
2326
2327 /* Loop to write back the buffer data from page_start to
2328 * data_start */
2329 i = 0;
2020 if (sc->bce_flash_info->buffered == 0) {
2330 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2021 for (addr = page_start; addr < data_start;
2022 addr += 4, i += 4) {
2023
2024 rc = bce_nvram_write_dword(sc, addr,
2025 &flash_buffer[i], cmd_flags);
2026
2027 if (rc != 0)
2331 for (addr = page_start; addr < data_start;
2332 addr += 4, i += 4) {
2333
2334 rc = bce_nvram_write_dword(sc, addr,
2335 &flash_buffer[i], cmd_flags);
2336
2337 if (rc != 0)
2028 goto nvram_write_end;
2338 goto bce_nvram_write_locked_exit;
2029
2030 cmd_flags = 0;
2031 }
2032 }
2033
2034 /* Loop to write the new data from data_start to data_end */
2035 for (addr = data_start; addr < data_end; addr += 4, i++) {
2036 if ((addr == page_end - 4) ||
2339
2340 cmd_flags = 0;
2341 }
2342 }
2343
2344 /* Loop to write the new data from data_start to data_end */
2345 for (addr = data_start; addr < data_end; addr += 4, i++) {
2346 if ((addr == page_end - 4) ||
2037 ((sc->bce_flash_info->buffered) &&
2038 (addr == data_end - 4))) {
2347 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2348 (addr == data_end - 4))) {
2039
2040 cmd_flags |= BCE_NVM_COMMAND_LAST;
2041 }
2042 rc = bce_nvram_write_dword(sc, addr, buf,
2043 cmd_flags);
2044
2045 if (rc != 0)
2349
2350 cmd_flags |= BCE_NVM_COMMAND_LAST;
2351 }
2352 rc = bce_nvram_write_dword(sc, addr, buf,
2353 cmd_flags);
2354
2355 if (rc != 0)
2046 goto nvram_write_end;
2356 goto bce_nvram_write_locked_exit;
2047
2048 cmd_flags = 0;
2049 buf += 4;
2050 }
2051
2052 /* Loop to write back the buffer data from data_end
2053 * to page_end */
2357
2358 cmd_flags = 0;
2359 buf += 4;
2360 }
2361
2362 /* Loop to write back the buffer data from data_end
2363 * to page_end */
2054 if (sc->bce_flash_info->buffered == 0) {
2364 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2055 for (addr = data_end; addr < page_end;
2056 addr += 4, i += 4) {
2057
2058 if (addr == page_end-4) {
2059 cmd_flags = BCE_NVM_COMMAND_LAST;
2060 }
2061 rc = bce_nvram_write_dword(sc, addr,
2062 &flash_buffer[i], cmd_flags);
2063
2064 if (rc != 0)
2365 for (addr = data_end; addr < page_end;
2366 addr += 4, i += 4) {
2367
2368 if (addr == page_end-4) {
2369 cmd_flags = BCE_NVM_COMMAND_LAST;
2370 }
2371 rc = bce_nvram_write_dword(sc, addr,
2372 &flash_buffer[i], cmd_flags);
2373
2374 if (rc != 0)
2065 goto nvram_write_end;
2375 goto bce_nvram_write_locked_exit;
2066
2067 cmd_flags = 0;
2068 }
2069 }
2070
2071 /* Disable writes to flash interface (lock write-protect) */
2072 bce_disable_nvram_write(sc);
2073
2074 /* Disable access to flash interface */
2075 bce_disable_nvram_access(sc);
2076 bce_release_nvram_lock(sc);
2077
2078 /* Increment written */
2079 written += data_end - data_start;
2080 }
2081
2376
2377 cmd_flags = 0;
2378 }
2379 }
2380
2381 /* Disable writes to flash interface (lock write-protect) */
2382 bce_disable_nvram_write(sc);
2383
2384 /* Disable access to flash interface */
2385 bce_disable_nvram_access(sc);
2386 bce_release_nvram_lock(sc);
2387
2388 /* Increment written */
2389 written += data_end - data_start;
2390 }
2391
2082nvram_write_end:
2392 goto bce_nvram_write_exit;
2393
2394bce_nvram_write_locked_exit:
2395 bce_disable_nvram_write(sc);
2396 bce_disable_nvram_access(sc);
2397 bce_release_nvram_lock(sc);
2398
2399bce_nvram_write_exit:
2083 if (align_start || align_end)
2084 free(buf, M_DEVBUF);
2085
2400 if (align_start || align_end)
2401 free(buf, M_DEVBUF);
2402
2086 return rc;
2403 DBEXIT(BCE_VERBOSE_NVRAM);
2404 return (rc);
2087}
2088#endif /* BCE_NVRAM_WRITE_SUPPORT */
2089
2090
2091/****************************************************************************/
2092/* Verifies that NVRAM is accessible and contains valid data. */
2093/* */
2094/* Reads the configuration data from NVRAM and verifies that the CRC is */

--- 5 unchanged lines hidden (view full) ---

2100static int
2101bce_nvram_test(struct bce_softc *sc)
2102{
2103 u32 buf[BCE_NVRAM_SIZE / 4];
2104 u8 *data = (u8 *) buf;
2105 int rc = 0;
2106 u32 magic, csum;
2107
2405}
2406#endif /* BCE_NVRAM_WRITE_SUPPORT */
2407
2408
2409/****************************************************************************/
2410/* Verifies that NVRAM is accessible and contains valid data. */
2411/* */
2412/* Reads the configuration data from NVRAM and verifies that the CRC is */

--- 5 unchanged lines hidden (view full) ---

2418static int
2419bce_nvram_test(struct bce_softc *sc)
2420{
2421 u32 buf[BCE_NVRAM_SIZE / 4];
2422 u8 *data = (u8 *) buf;
2423 int rc = 0;
2424 u32 magic, csum;
2425
2426 DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2108
2109 /*
2110 * Check that the device NVRAM is valid by reading
2111 * the magic value at offset 0.
2112 */
2427
2428 /*
2429 * Check that the device NVRAM is valid by reading
2430 * the magic value at offset 0.
2431 */
2113 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0)
2114 goto bce_nvram_test_done;
2432 if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2433 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n", __FILE__, __LINE__);
2434 goto bce_nvram_test_exit;
2435 }
2115
2436
2116
2437 /*
2438 * Verify that offset 0 of the NVRAM contains
2439 * a valid magic number.
2440 */
2117 magic = bce_be32toh(buf[0]);
2118 if (magic != BCE_NVRAM_MAGIC) {
2119 rc = ENODEV;
2120 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, "
2121 "Found: 0x%08X\n",
2122 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2441 magic = bce_be32toh(buf[0]);
2442 if (magic != BCE_NVRAM_MAGIC) {
2443 rc = ENODEV;
2444 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! Expected: 0x%08X, "
2445 "Found: 0x%08X\n",
2446 __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2123 goto bce_nvram_test_done;
2447 goto bce_nvram_test_exit;
2124 }
2125
2126 /*
2127 * Verify that the device NVRAM includes valid
2128 * configuration data.
2129 */
2448 }
2449
2450 /*
2451 * Verify that the device NVRAM includes valid
2452 * configuration data.
2453 */
2130 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0)
2131 goto bce_nvram_test_done;
2454 if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2455 BCE_PRINTF("%s(%d): Unable to read Manufacturing Information from "
2456 "NVRAM!\n", __FILE__, __LINE__);
2457 goto bce_nvram_test_exit;
2458 }
2132
2133 csum = ether_crc32_le(data, 0x100);
2134 if (csum != BCE_CRC32_RESIDUAL) {
2135 rc = ENODEV;
2136 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! "
2137 "Expected: 0x%08X, Found: 0x%08X\n",
2138 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2459
2460 csum = ether_crc32_le(data, 0x100);
2461 if (csum != BCE_CRC32_RESIDUAL) {
2462 rc = ENODEV;
2463 BCE_PRINTF("%s(%d): Invalid Manufacturing Information NVRAM CRC! "
2464 "Expected: 0x%08X, Found: 0x%08X\n",
2465 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2139 goto bce_nvram_test_done;
2466 goto bce_nvram_test_exit;
2140 }
2141
2142 csum = ether_crc32_le(data + 0x100, 0x100);
2143 if (csum != BCE_CRC32_RESIDUAL) {
2467 }
2468
2469 csum = ether_crc32_le(data + 0x100, 0x100);
2470 if (csum != BCE_CRC32_RESIDUAL) {
2471 rc = ENODEV;
2144 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information "
2145 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2146 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2472 BCE_PRINTF("%s(%d): Invalid Feature Configuration Information "
2473 "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
2474 __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2147 rc = ENODEV;
2148 }
2149
2475 }
2476
2150bce_nvram_test_done:
2477bce_nvram_test_exit:
2478 DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2151 return rc;
2152}
2153
2154
2155/****************************************************************************/
2479 return rc;
2480}
2481
2482
2483/****************************************************************************/
2484/* Identifies the current media type of the controller and sets the PHY */
2485/* address. */
2486/* */
2487/* Returns: */
2488/* Nothing. */
2489/****************************************************************************/
2490static void
2491bce_get_media(struct bce_softc *sc)
2492{
2493 u32 val;
2494
2495 DBENTER(BCE_VERBOSE);
2496
2497 sc->bce_phy_addr = 1;
2498
2499 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2500 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
2501 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
2502 u32 strap;
2503
2504 /*
2505 * The BCM5709S is software configurable
2506 * for Copper or SerDes operation.
2507 */
2508 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
2509 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for copper.\n");
2510 goto bce_get_media_exit;
2511 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
2512 DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded for dual media.\n");
2513 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2514 goto bce_get_media_exit;
2515 }
2516
2517 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
2518 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
2519 else
2520 strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
2521
2522 if (pci_get_function(sc->bce_dev) == 0) {
2523 switch (strap) {
2524 case 0x4:
2525 case 0x5:
2526 case 0x6:
2527 DBPRINT(sc, BCE_INFO_LOAD,
2528 "BCM5709 s/w configured for SerDes.\n");
2529 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2530 default:
2531 DBPRINT(sc, BCE_INFO_LOAD,
2532 "BCM5709 s/w configured for Copper.\n");
2533 }
2534 } else {
2535 switch (strap) {
2536 case 0x1:
2537 case 0x2:
2538 case 0x4:
2539 DBPRINT(sc, BCE_INFO_LOAD,
2540 "BCM5709 s/w configured for SerDes.\n");
2541 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2542 default:
2543 DBPRINT(sc, BCE_INFO_LOAD,
2544 "BCM5709 s/w configured for Copper.\n");
2545 }
2546 }
2547
2548 } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
2549 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2550
2551 if (sc->bce_phy_flags && BCE_PHY_SERDES_FLAG) {
2552 sc->bce_flags |= BCE_NO_WOL_FLAG;
2553 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2554 sc->bce_phy_addr = 2;
2555 val = REG_RD_IND(sc, sc->bce_shmem_base +
2556 BCE_SHARED_HW_CFG_CONFIG);
2557 if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
2558 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2559 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb capable adapter\n");
2560 }
2561 }
2562 } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2563 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
2564 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2565
2566bce_get_media_exit:
2567 DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
2568 "Using PHY address %d.\n", sc->bce_phy_addr);
2569
2570 DBEXIT(BCE_VERBOSE);
2571}
2572
2573
2574/****************************************************************************/
2156/* Free any DMA memory owned by the driver. */
2157/* */
2158/* Scans through each data structre that requires DMA memory and frees */
2159/* the memory if allocated. */
2160/* */
2161/* Returns: */
2162/* Nothing. */
2163/****************************************************************************/
2164static void
2165bce_dma_free(struct bce_softc *sc)
2166{
2167 int i;
2168
2575/* Free any DMA memory owned by the driver. */
2576/* */
2577/* Scans through each data structre that requires DMA memory and frees */
2578/* the memory if allocated. */
2579/* */
2580/* Returns: */
2581/* Nothing. */
2582/****************************************************************************/
2583static void
2584bce_dma_free(struct bce_softc *sc)
2585{
2586 int i;
2587
2169 DBPRINT(sc,BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
2588 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2170
2589
2171 /* Destroy the status block. */
2590 /* Free, unmap, and destroy the status block. */
2172 if (sc->status_block != NULL) {
2173 bus_dmamem_free(
2174 sc->status_tag,
2175 sc->status_block,
2176 sc->status_map);
2177 sc->status_block = NULL;
2178 }
2179

--- 7 unchanged lines hidden (view full) ---

2187 }
2188
2189 if (sc->status_tag != NULL) {
2190 bus_dma_tag_destroy(sc->status_tag);
2191 sc->status_tag = NULL;
2192 }
2193
2194
2591 if (sc->status_block != NULL) {
2592 bus_dmamem_free(
2593 sc->status_tag,
2594 sc->status_block,
2595 sc->status_map);
2596 sc->status_block = NULL;
2597 }
2598

--- 7 unchanged lines hidden (view full) ---

2606 }
2607
2608 if (sc->status_tag != NULL) {
2609 bus_dma_tag_destroy(sc->status_tag);
2610 sc->status_tag = NULL;
2611 }
2612
2613
2195 /* Destroy the statistics block. */
2614 /* Free, unmap, and destroy the statistics block. */
2196 if (sc->stats_block != NULL) {
2197 bus_dmamem_free(
2198 sc->stats_tag,
2199 sc->stats_block,
2200 sc->stats_map);
2201 sc->stats_block = NULL;
2202 }
2203

--- 7 unchanged lines hidden (view full) ---

2211 }
2212
2213 if (sc->stats_tag != NULL) {
2214 bus_dma_tag_destroy(sc->stats_tag);
2215 sc->stats_tag = NULL;
2216 }
2217
2218
2615 if (sc->stats_block != NULL) {
2616 bus_dmamem_free(
2617 sc->stats_tag,
2618 sc->stats_block,
2619 sc->stats_map);
2620 sc->stats_block = NULL;
2621 }
2622

--- 7 unchanged lines hidden (view full) ---

2630 }
2631
2632 if (sc->stats_tag != NULL) {
2633 bus_dma_tag_destroy(sc->stats_tag);
2634 sc->stats_tag = NULL;
2635 }
2636
2637
2638 /* Free, unmap and destroy all context memory pages. */
2639 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2640 for (i = 0; i < sc->ctx_pages; i++ ) {
2641 if (sc->ctx_block[i] != NULL) {
2642 bus_dmamem_free(
2643 sc->ctx_tag,
2644 sc->ctx_block[i],
2645 sc->ctx_map[i]);
2646 sc->ctx_block[i] = NULL;
2647 }
2648
2649 if (sc->ctx_map[i] != NULL) {
2650 bus_dmamap_unload(
2651 sc->ctx_tag,
2652 sc->ctx_map[i]);
2653 bus_dmamap_destroy(
2654 sc->ctx_tag,
2655 sc->ctx_map[i]);
2656 sc->ctx_map[i] = NULL;
2657 }
2658 }
2659
2660 /* Destroy the context memory tag. */
2661 if (sc->ctx_tag != NULL) {
2662 bus_dma_tag_destroy(sc->ctx_tag);
2663 sc->ctx_tag = NULL;
2664 }
2665 }
2666
2667
2219 /* Free, unmap and destroy all TX buffer descriptor chain pages. */
2220 for (i = 0; i < TX_PAGES; i++ ) {
2221 if (sc->tx_bd_chain[i] != NULL) {
2222 bus_dmamem_free(
2223 sc->tx_bd_chain_tag,
2224 sc->tx_bd_chain[i],
2225 sc->tx_bd_chain_map[i]);
2226 sc->tx_bd_chain[i] = NULL;

--- 73 unchanged lines hidden (view full) ---

2300 sc->pg_bd_chain_tag = NULL;
2301 }
2302#endif
2303
2304
2305 /* Unload and destroy the TX mbuf maps. */
2306 for (i = 0; i < TOTAL_TX_BD; i++) {
2307 if (sc->tx_mbuf_map[i] != NULL) {
2668 /* Free, unmap and destroy all TX buffer descriptor chain pages. */
2669 for (i = 0; i < TX_PAGES; i++ ) {
2670 if (sc->tx_bd_chain[i] != NULL) {
2671 bus_dmamem_free(
2672 sc->tx_bd_chain_tag,
2673 sc->tx_bd_chain[i],
2674 sc->tx_bd_chain_map[i]);
2675 sc->tx_bd_chain[i] = NULL;

--- 73 unchanged lines hidden (view full) ---

2749 sc->pg_bd_chain_tag = NULL;
2750 }
2751#endif
2752
2753
2754 /* Unload and destroy the TX mbuf maps. */
2755 for (i = 0; i < TOTAL_TX_BD; i++) {
2756 if (sc->tx_mbuf_map[i] != NULL) {
2308 bus_dmamap_unload(sc->tx_mbuf_tag,
2757 bus_dmamap_unload(sc->tx_mbuf_tag,
2309 sc->tx_mbuf_map[i]);
2758 sc->tx_mbuf_map[i]);
2310 bus_dmamap_destroy(sc->tx_mbuf_tag,
2759 bus_dmamap_destroy(sc->tx_mbuf_tag,
2311 sc->tx_mbuf_map[i]);
2312 sc->tx_mbuf_map[i] = NULL;
2313 }
2314 }
2315
2316 /* Destroy the TX mbuf tag. */
2317 if (sc->tx_mbuf_tag != NULL) {
2318 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2319 sc->tx_mbuf_tag = NULL;
2320 }
2321
2322 /* Unload and destroy the RX mbuf maps. */
2323 for (i = 0; i < TOTAL_RX_BD; i++) {
2324 if (sc->rx_mbuf_map[i] != NULL) {
2760 sc->tx_mbuf_map[i]);
2761 sc->tx_mbuf_map[i] = NULL;
2762 }
2763 }
2764
2765 /* Destroy the TX mbuf tag. */
2766 if (sc->tx_mbuf_tag != NULL) {
2767 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2768 sc->tx_mbuf_tag = NULL;
2769 }
2770
2771 /* Unload and destroy the RX mbuf maps. */
2772 for (i = 0; i < TOTAL_RX_BD; i++) {
2773 if (sc->rx_mbuf_map[i] != NULL) {
2325 bus_dmamap_unload(sc->rx_mbuf_tag,
2774 bus_dmamap_unload(sc->rx_mbuf_tag,
2326 sc->rx_mbuf_map[i]);
2775 sc->rx_mbuf_map[i]);
2327 bus_dmamap_destroy(sc->rx_mbuf_tag,
2776 bus_dmamap_destroy(sc->rx_mbuf_tag,
2328 sc->rx_mbuf_map[i]);
2329 sc->rx_mbuf_map[i] = NULL;
2330 }
2331 }
2332
2333 /* Destroy the RX mbuf tag. */
2334 if (sc->rx_mbuf_tag != NULL) {
2335 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2336 sc->rx_mbuf_tag = NULL;
2337 }
2338
2339#ifdef BCE_USE_SPLIT_HEADER
2340 /* Unload and destroy the page mbuf maps. */
2341 for (i = 0; i < TOTAL_PG_BD; i++) {
2342 if (sc->pg_mbuf_map[i] != NULL) {
2777 sc->rx_mbuf_map[i]);
2778 sc->rx_mbuf_map[i] = NULL;
2779 }
2780 }
2781
2782 /* Destroy the RX mbuf tag. */
2783 if (sc->rx_mbuf_tag != NULL) {
2784 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2785 sc->rx_mbuf_tag = NULL;
2786 }
2787
2788#ifdef BCE_USE_SPLIT_HEADER
2789 /* Unload and destroy the page mbuf maps. */
2790 for (i = 0; i < TOTAL_PG_BD; i++) {
2791 if (sc->pg_mbuf_map[i] != NULL) {
2343 bus_dmamap_unload(sc->pg_mbuf_tag,
2792 bus_dmamap_unload(sc->pg_mbuf_tag,
2344 sc->pg_mbuf_map[i]);
2793 sc->pg_mbuf_map[i]);
2345 bus_dmamap_destroy(sc->pg_mbuf_tag,
2794 bus_dmamap_destroy(sc->pg_mbuf_tag,
2346 sc->pg_mbuf_map[i]);
2347 sc->pg_mbuf_map[i] = NULL;
2348 }
2349 }
2350
2351 /* Destroy the page mbuf tag. */
2352 if (sc->pg_mbuf_tag != NULL) {
2353 bus_dma_tag_destroy(sc->pg_mbuf_tag);
2354 sc->pg_mbuf_tag = NULL;
2355 }
2356#endif
2357
2358 /* Destroy the parent tag */
2359 if (sc->parent_tag != NULL) {
2360 bus_dma_tag_destroy(sc->parent_tag);
2361 sc->parent_tag = NULL;
2362 }
2363
2795 sc->pg_mbuf_map[i]);
2796 sc->pg_mbuf_map[i] = NULL;
2797 }
2798 }
2799
2800 /* Destroy the page mbuf tag. */
2801 if (sc->pg_mbuf_tag != NULL) {
2802 bus_dma_tag_destroy(sc->pg_mbuf_tag);
2803 sc->pg_mbuf_tag = NULL;
2804 }
2805#endif
2806
2807 /* Destroy the parent tag */
2808 if (sc->parent_tag != NULL) {
2809 bus_dma_tag_destroy(sc->parent_tag);
2810 sc->parent_tag = NULL;
2811 }
2812
2364 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
2365
2813 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2366}
2367
2368
2369/****************************************************************************/
2370/* Get DMA memory from the OS. */
2371/* */
2372/* Validates that the OS has provided DMA buffers in response to a */
2373/* bus_dmamap_load() call and saves the physical address of those buffers. */

--- 9 unchanged lines hidden (view full) ---

2383{
2384 bus_addr_t *busaddr = arg;
2385
2386 /* Simulate a mapping failure. */
2387 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2388 printf("bce: %s(%d): Simulating DMA mapping error.\n",
2389 __FILE__, __LINE__);
2390 error = ENOMEM);
2814}
2815
2816
2817/****************************************************************************/
2818/* Get DMA memory from the OS. */
2819/* */
2820/* Validates that the OS has provided DMA buffers in response to a */
2821/* bus_dmamap_load() call and saves the physical address of those buffers. */

--- 9 unchanged lines hidden (view full) ---

2831{
2832 bus_addr_t *busaddr = arg;
2833
2834 /* Simulate a mapping failure. */
2835 DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2836 printf("bce: %s(%d): Simulating DMA mapping error.\n",
2837 __FILE__, __LINE__);
2838 error = ENOMEM);
2391
2839
2392 /* Check for an error and signal the caller that an error occurred. */
2393 if (error) {
2394 printf("bce %s(%d): DMA mapping error! error = %d, "
2395 "nseg = %d\n", __FILE__, __LINE__, error, nseg);
2396 *busaddr = 0;
2397 return;
2398 }
2399

--- 5 unchanged lines hidden (view full) ---

2405/****************************************************************************/
2406/* Allocate any DMA memory needed by the driver. */
2407/* */
2408/* Allocates DMA memory needed for the various global structures needed by */
2409/* hardware. */
2410/* */
2411/* Memory alignment requirements: */
2412/* -----------------+----------+----------+ */
2840 /* Check for an error and signal the caller that an error occurred. */
2841 if (error) {
2842 printf("bce %s(%d): DMA mapping error! error = %d, "
2843 "nseg = %d\n", __FILE__, __LINE__, error, nseg);
2844 *busaddr = 0;
2845 return;
2846 }
2847

--- 5 unchanged lines hidden (view full) ---

2853/****************************************************************************/
2854/* Allocate any DMA memory needed by the driver. */
2855/* */
2856/* Allocates DMA memory needed for the various global structures needed by */
2857/* hardware. */
2858/* */
2859/* Memory alignment requirements: */
2860/* -----------------+----------+----------+ */
2413/* Data Structure | 5706 | 5708 | */
2414/* -----------------+----------+----------+ */
2415/* Status Block | 8 bytes | 8 bytes | */
2416/* Statistics Block | 8 bytes | 8 bytes | */
2417/* RX Buffers | 16 bytes | 16 bytes | */
2418/* PG Buffers | none | none | */
2419/* TX Buffers | none | none | */
2420/* Chain Pages(1) | 4KiB | 4KiB | */
2421/* -----------------+----------+----------+ */
2861/* | 5706 | 5708 | 5709 | 5716 | */
2862/* -----------------+----------+----------+----------+----------+ */
2863/* Status Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2864/* Statistics Block | 8 bytes | 8 bytes | 16 bytes | 16 bytes | */
2865/* RX Buffers | 16 bytes | 16 bytes | 16 bytes | 16 bytes | */
2866/* PG Buffers | none | none | none | none | */
2867/* TX Buffers | none | none | none | none | */
2868/* Chain Pages(1) | 4KiB | 4KiB | 4KiB | 4KiB | */
2869/* -----------------+----------+----------+----------+----------+ */
2422/* */
2423/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2424/* */
2425/* Returns: */
2426/* 0 for success, positive value for failure. */
2427/****************************************************************************/
2428static int
2429bce_dma_alloc(device_t dev)
2430{
2431 struct bce_softc *sc;
2432 int i, error, rc = 0;
2433 bus_addr_t busaddr;
2434 bus_size_t max_size, max_seg_size;
2435 int max_segments;
2436
2437 sc = device_get_softc(dev);
2870/* */
2871/* (1) Must align with CPU page size (BCM_PAGE_SZIE). */
2872/* */
2873/* Returns: */
2874/* 0 for success, positive value for failure. */
2875/****************************************************************************/
2876static int
2877bce_dma_alloc(device_t dev)
2878{
2879 struct bce_softc *sc;
2880 int i, error, rc = 0;
2881 bus_addr_t busaddr;
2882 bus_size_t max_size, max_seg_size;
2883 int max_segments;
2884
2885 sc = device_get_softc(dev);
2438
2439 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
2440
2886
2887 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
2888
2441 /*
2442 * Allocate the parent bus DMA tag appropriate for PCI.
2443 */
2444 if (bus_dma_tag_create(NULL,
2445 1,
2446 BCE_DMA_BOUNDARY,
2447 sc->max_bus_addr,
2448 BUS_SPACE_MAXADDR,

--- 7 unchanged lines hidden (view full) ---

2456 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
2457 __FILE__, __LINE__);
2458 rc = ENOMEM;
2459 goto bce_dma_alloc_exit;
2460 }
2461
2462 /*
2463 * Create a DMA tag for the status block, allocate and clear the
2889 /*
2890 * Allocate the parent bus DMA tag appropriate for PCI.
2891 */
2892 if (bus_dma_tag_create(NULL,
2893 1,
2894 BCE_DMA_BOUNDARY,
2895 sc->max_bus_addr,
2896 BUS_SPACE_MAXADDR,

--- 7 unchanged lines hidden (view full) ---

2904 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
2905 __FILE__, __LINE__);
2906 rc = ENOMEM;
2907 goto bce_dma_alloc_exit;
2908 }
2909
2910 /*
2911 * Create a DMA tag for the status block, allocate and clear the
2464 * memory, map the memory into DMA space, and fetch the physical
2912 * memory, map the memory into DMA space, and fetch the physical
2465 * address of the block.
2466 */
2467 if (bus_dma_tag_create(sc->parent_tag,
2468 BCE_DMA_ALIGN,
2469 BCE_DMA_BOUNDARY,
2470 sc->max_bus_addr,
2471 BUS_SPACE_MAXADDR,
2472 NULL, NULL,

--- 23 unchanged lines hidden (view full) ---

2496
2497 error = bus_dmamap_load(sc->status_tag,
2498 sc->status_map,
2499 sc->status_block,
2500 BCE_STATUS_BLK_SZ,
2501 bce_dma_map_addr,
2502 &busaddr,
2503 BUS_DMA_NOWAIT);
2913 * address of the block.
2914 */
2915 if (bus_dma_tag_create(sc->parent_tag,
2916 BCE_DMA_ALIGN,
2917 BCE_DMA_BOUNDARY,
2918 sc->max_bus_addr,
2919 BUS_SPACE_MAXADDR,
2920 NULL, NULL,

--- 23 unchanged lines hidden (view full) ---

2944
2945 error = bus_dmamap_load(sc->status_tag,
2946 sc->status_map,
2947 sc->status_block,
2948 BCE_STATUS_BLK_SZ,
2949 bce_dma_map_addr,
2950 &busaddr,
2951 BUS_DMA_NOWAIT);
2504
2952
2505 if (error) {
2506 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n",
2507 __FILE__, __LINE__);
2508 rc = ENOMEM;
2509 goto bce_dma_alloc_exit;
2510 }
2511
2512 sc->status_block_paddr = busaddr;
2513 /* DRC - Fix for 64 bit addresses. */
2514 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2515 (u32) sc->status_block_paddr);
2516
2517 /*
2518 * Create a DMA tag for the statistics block, allocate and clear the
2953 if (error) {
2954 BCE_PRINTF("%s(%d): Could not map status block DMA memory!\n",
2955 __FILE__, __LINE__);
2956 rc = ENOMEM;
2957 goto bce_dma_alloc_exit;
2958 }
2959
2960 sc->status_block_paddr = busaddr;
2961 /* DRC - Fix for 64 bit addresses. */
2962 DBPRINT(sc, BCE_INFO, "status_block_paddr = 0x%08X\n",
2963 (u32) sc->status_block_paddr);
2964
2965 /*
2966 * Create a DMA tag for the statistics block, allocate and clear the
2519 * memory, map the memory into DMA space, and fetch the physical
2967 * memory, map the memory into DMA space, and fetch the physical
2520 * address of the block.
2521 */
2522 if (bus_dma_tag_create(sc->parent_tag,
2523 BCE_DMA_ALIGN,
2524 BCE_DMA_BOUNDARY,
2525 sc->max_bus_addr,
2526 BUS_SPACE_MAXADDR,
2527 NULL, NULL,

--- 33 unchanged lines hidden (view full) ---

2561 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n",
2562 __FILE__, __LINE__);
2563 rc = ENOMEM;
2564 goto bce_dma_alloc_exit;
2565 }
2566
2567 sc->stats_block_paddr = busaddr;
2568 /* DRC - Fix for 64 bit address. */
2968 * address of the block.
2969 */
2970 if (bus_dma_tag_create(sc->parent_tag,
2971 BCE_DMA_ALIGN,
2972 BCE_DMA_BOUNDARY,
2973 sc->max_bus_addr,
2974 BUS_SPACE_MAXADDR,
2975 NULL, NULL,

--- 33 unchanged lines hidden (view full) ---

3009 BCE_PRINTF("%s(%d): Could not map statistics block DMA memory!\n",
3010 __FILE__, __LINE__);
3011 rc = ENOMEM;
3012 goto bce_dma_alloc_exit;
3013 }
3014
3015 sc->stats_block_paddr = busaddr;
3016 /* DRC - Fix for 64 bit address. */
2569 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n",
3017 DBPRINT(sc,BCE_INFO, "stats_block_paddr = 0x%08X\n",
2570 (u32) sc->stats_block_paddr);
2571
3018 (u32) sc->stats_block_paddr);
3019
3020 /* BCM5709 uses host memory as cache for context memory. */
3021 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3022 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3023 if (sc->ctx_pages == 0)
3024 sc->ctx_pages = 1;
3025
3026 DBRUNIF((sc->ctx_pages > 512),
3027 BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3028 __FILE__, __LINE__, sc->ctx_pages));
3029
3030 /*
3031 * Create a DMA tag for the context pages,
3032 * allocate and clear the memory, map the
3033 * memory into DMA space, and fetch the
3034 * physical address of the block.
3035 */
3036 if(bus_dma_tag_create(sc->parent_tag,
3037 BCM_PAGE_SIZE,
3038 BCE_DMA_BOUNDARY,
3039 sc->max_bus_addr,
3040 BUS_SPACE_MAXADDR,
3041 NULL, NULL,
3042 BCM_PAGE_SIZE,
3043 1,
3044 BCM_PAGE_SIZE,
3045 0,
3046 NULL, NULL,
3047 &sc->ctx_tag)) {
3048 BCE_PRINTF("%s(%d): Could not allocate CTX DMA tag!\n",
3049 __FILE__, __LINE__);
3050 rc = ENOMEM;
3051 goto bce_dma_alloc_exit;
3052 }
3053
3054 for (i = 0; i < sc->ctx_pages; i++) {
3055
3056 if(bus_dmamem_alloc(sc->ctx_tag,
3057 (void **)&sc->ctx_block[i],
3058 BUS_DMA_NOWAIT,
3059 &sc->ctx_map[i])) {
3060 BCE_PRINTF("%s(%d): Could not allocate CTX "
3061 "DMA memory!\n", __FILE__, __LINE__);
3062 rc = ENOMEM;
3063 goto bce_dma_alloc_exit;
3064 }
3065
3066 bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE);
3067
3068 error = bus_dmamap_load(sc->ctx_tag,
3069 sc->ctx_map[i],
3070 sc->ctx_block[i],
3071 BCM_PAGE_SIZE,
3072 bce_dma_map_addr,
3073 &busaddr,
3074 BUS_DMA_NOWAIT);
3075
3076 if (error) {
3077 BCE_PRINTF("%s(%d): Could not map CTX DMA memory!\n",
3078 __FILE__, __LINE__);
3079 rc = ENOMEM;
3080 goto bce_dma_alloc_exit;
3081 }
3082
3083 sc->ctx_paddr[i] = busaddr;
3084 /* DRC - Fix for 64 bit systems. */
3085 DBPRINT(sc, BCE_INFO, "ctx_paddr[%d] = 0x%08X\n",
3086 i, (u32) sc->ctx_paddr[i]);
3087 }
3088 }
3089
2572 /*
2573 * Create a DMA tag for the TX buffer descriptor chain,
2574 * allocate and clear the memory, and fetch the
2575 * physical address of the block.
2576 */
2577 if(bus_dma_tag_create(sc->parent_tag,
2578 BCM_PAGE_SIZE,
2579 BCE_DMA_BOUNDARY,
2580 sc->max_bus_addr,
3090 /*
3091 * Create a DMA tag for the TX buffer descriptor chain,
3092 * allocate and clear the memory, and fetch the
3093 * physical address of the block.
3094 */
3095 if(bus_dma_tag_create(sc->parent_tag,
3096 BCM_PAGE_SIZE,
3097 BCE_DMA_BOUNDARY,
3098 sc->max_bus_addr,
2581 BUS_SPACE_MAXADDR,
3099 BUS_SPACE_MAXADDR,
2582 NULL, NULL,
2583 BCE_TX_CHAIN_PAGE_SZ,
2584 1,
2585 BCE_TX_CHAIN_PAGE_SZ,
2586 0,
2587 NULL, NULL,
2588 &sc->tx_bd_chain_tag)) {
2589 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n",

--- 26 unchanged lines hidden (view full) ---

2616 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n",
2617 __FILE__, __LINE__);
2618 rc = ENOMEM;
2619 goto bce_dma_alloc_exit;
2620 }
2621
2622 sc->tx_bd_chain_paddr[i] = busaddr;
2623 /* DRC - Fix for 64 bit systems. */
3100 NULL, NULL,
3101 BCE_TX_CHAIN_PAGE_SZ,
3102 1,
3103 BCE_TX_CHAIN_PAGE_SZ,
3104 0,
3105 NULL, NULL,
3106 &sc->tx_bd_chain_tag)) {
3107 BCE_PRINTF("%s(%d): Could not allocate TX descriptor chain DMA tag!\n",

--- 26 unchanged lines hidden (view full) ---

3134 BCE_PRINTF("%s(%d): Could not map TX descriptor chain DMA memory!\n",
3135 __FILE__, __LINE__);
3136 rc = ENOMEM;
3137 goto bce_dma_alloc_exit;
3138 }
3139
3140 sc->tx_bd_chain_paddr[i] = busaddr;
3141 /* DRC - Fix for 64 bit systems. */
2624 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
3142 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n",
2625 i, (u32) sc->tx_bd_chain_paddr[i]);
2626 }
2627
2628 /* Check the required size before mapping to conserve resources. */
2629 if (bce_tso_enable) {
2630 max_size = BCE_TSO_MAX_SIZE;
2631 max_segments = BCE_MAX_SEGMENTS;
2632 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
2633 } else {
2634 max_size = MCLBYTES * BCE_MAX_SEGMENTS;
2635 max_segments = BCE_MAX_SEGMENTS;
2636 max_seg_size = MCLBYTES;
2637 }
3143 i, (u32) sc->tx_bd_chain_paddr[i]);
3144 }
3145
3146 /* Check the required size before mapping to conserve resources. */
3147 if (bce_tso_enable) {
3148 max_size = BCE_TSO_MAX_SIZE;
3149 max_segments = BCE_MAX_SEGMENTS;
3150 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3151 } else {
3152 max_size = MCLBYTES * BCE_MAX_SEGMENTS;
3153 max_segments = BCE_MAX_SEGMENTS;
3154 max_seg_size = MCLBYTES;
3155 }
2638
3156
2639 /* Create a DMA tag for TX mbufs. */
2640 if (bus_dma_tag_create(sc->parent_tag,
2641 1,
2642 BCE_DMA_BOUNDARY,
2643 sc->max_bus_addr,
2644 BUS_SPACE_MAXADDR,
2645 NULL, NULL,
2646 max_size,

--- 5 unchanged lines hidden (view full) ---

2652 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
2653 __FILE__, __LINE__);
2654 rc = ENOMEM;
2655 goto bce_dma_alloc_exit;
2656 }
2657
2658 /* Create DMA maps for the TX mbufs clusters. */
2659 for (i = 0; i < TOTAL_TX_BD; i++) {
3157 /* Create a DMA tag for TX mbufs. */
3158 if (bus_dma_tag_create(sc->parent_tag,
3159 1,
3160 BCE_DMA_BOUNDARY,
3161 sc->max_bus_addr,
3162 BUS_SPACE_MAXADDR,
3163 NULL, NULL,
3164 max_size,

--- 5 unchanged lines hidden (view full) ---

3170 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3171 __FILE__, __LINE__);
3172 rc = ENOMEM;
3173 goto bce_dma_alloc_exit;
3174 }
3175
3176 /* Create DMA maps for the TX mbufs clusters. */
3177 for (i = 0; i < TOTAL_TX_BD; i++) {
2660 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3178 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
2661 &sc->tx_mbuf_map[i])) {
2662 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n",
2663 __FILE__, __LINE__);
2664 rc = ENOMEM;
2665 goto bce_dma_alloc_exit;
2666 }
2667 }
2668

--- 151 unchanged lines hidden (view full) ---

2820 /* DRC - Fix for 64 bit systems. */
2821 DBPRINT(sc, BCE_INFO, "pg_bd_chain_paddr[%d] = 0x%08X\n",
2822 i, (u32) sc->pg_bd_chain_paddr[i]);
2823 }
2824
2825 /*
2826 * Create a DMA tag for page mbufs.
2827 */
3179 &sc->tx_mbuf_map[i])) {
3180 BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA map!\n",
3181 __FILE__, __LINE__);
3182 rc = ENOMEM;
3183 goto bce_dma_alloc_exit;
3184 }
3185 }
3186

--- 151 unchanged lines hidden (view full) ---

3338 /* DRC - Fix for 64 bit systems. */
3339 DBPRINT(sc, BCE_INFO, "pg_bd_chain_paddr[%d] = 0x%08X\n",
3340 i, (u32) sc->pg_bd_chain_paddr[i]);
3341 }
3342
3343 /*
3344 * Create a DMA tag for page mbufs.
3345 */
2828 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3346 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
2829 MCLBYTES : sc->pg_bd_mbuf_alloc_size);
2830
2831 if (bus_dma_tag_create(sc->parent_tag,
2832 1,
2833 BCE_DMA_BOUNDARY,
2834 sc->max_bus_addr,
2835 BUS_SPACE_MAXADDR,
2836 NULL, NULL,

--- 17 unchanged lines hidden (view full) ---

2854 __FILE__, __LINE__);
2855 rc = ENOMEM;
2856 goto bce_dma_alloc_exit;
2857 }
2858 }
2859#endif
2860
2861bce_dma_alloc_exit:
3347 MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3348
3349 if (bus_dma_tag_create(sc->parent_tag,
3350 1,
3351 BCE_DMA_BOUNDARY,
3352 sc->max_bus_addr,
3353 BUS_SPACE_MAXADDR,
3354 NULL, NULL,

--- 17 unchanged lines hidden (view full) ---

3372 __FILE__, __LINE__);
3373 rc = ENOMEM;
3374 goto bce_dma_alloc_exit;
3375 }
3376 }
3377#endif
3378
3379bce_dma_alloc_exit:
2862 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
2863
3380 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
2864 return(rc);
2865}
2866
2867
2868/****************************************************************************/
2869/* Release all resources used by the driver. */
2870/* */
2871/* Releases all resources acquired by the driver including interrupts, */
2872/* interrupt handler, interfaces, mutexes, and DMA memory. */
2873/* */
2874/* Returns: */
2875/* Nothing. */
2876/****************************************************************************/
2877static void
2878bce_release_resources(struct bce_softc *sc)
2879{
2880 device_t dev;
2881
3381 return(rc);
3382}
3383
3384
3385/****************************************************************************/
3386/* Release all resources used by the driver. */
3387/* */
3388/* Releases all resources acquired by the driver including interrupts, */
3389/* interrupt handler, interfaces, mutexes, and DMA memory. */
3390/* */
3391/* Returns: */
3392/* Nothing. */
3393/****************************************************************************/
3394static void
3395bce_release_resources(struct bce_softc *sc)
3396{
3397 device_t dev;
3398
2882 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
3399 DBENTER(BCE_VERBOSE_RESET);
2883
2884 dev = sc->bce_dev;
2885
2886 bce_dma_free(sc);
2887
2888 if (sc->bce_intrhand != NULL) {
2889 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
2890 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
2891 }
2892
2893 if (sc->bce_res_irq != NULL) {
2894 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3400
3401 dev = sc->bce_dev;
3402
3403 bce_dma_free(sc);
3404
3405 if (sc->bce_intrhand != NULL) {
3406 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3407 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3408 }
3409
3410 if (sc->bce_res_irq != NULL) {
3411 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
2895 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_flags & BCE_USING_MSI_FLAG ? 1 : 0,
3412 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
2896 sc->bce_res_irq);
2897 }
2898
3413 sc->bce_res_irq);
3414 }
3415
2899 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
2900 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI vector.\n");
3416 if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3417 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
2901 pci_release_msi(dev);
2902 }
2903
2904 if (sc->bce_res_mem != NULL) {
2905 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
2906 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem);
2907 }
2908
2909 if (sc->bce_ifp != NULL) {
2910 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
2911 if_free(sc->bce_ifp);
2912 }
2913
2914 if (mtx_initialized(&sc->bce_mtx))
2915 BCE_LOCK_DESTROY(sc);
2916
3418 pci_release_msi(dev);
3419 }
3420
3421 if (sc->bce_res_mem != NULL) {
3422 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3423 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0), sc->bce_res_mem);
3424 }
3425
3426 if (sc->bce_ifp != NULL) {
3427 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3428 if_free(sc->bce_ifp);
3429 }
3430
3431 if (mtx_initialized(&sc->bce_mtx))
3432 BCE_LOCK_DESTROY(sc);
3433
2917 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
2918
3434 DBEXIT(BCE_VERBOSE_RESET);
2919}
2920
2921
2922/****************************************************************************/
2923/* Firmware synchronization. */
2924/* */
2925/* Before performing certain events such as a chip reset, synchronize with */
2926/* the firmware first. */
2927/* */
2928/* Returns: */
2929/* 0 for success, positive value for failure. */
2930/****************************************************************************/
2931static int
2932bce_fw_sync(struct bce_softc *sc, u32 msg_data)
2933{
2934 int i, rc = 0;
2935 u32 val;
2936
3435}
3436
3437
3438/****************************************************************************/
3439/* Firmware synchronization. */
3440/* */
3441/* Before performing certain events such as a chip reset, synchronize with */
3442/* the firmware first. */
3443/* */
3444/* Returns: */
3445/* 0 for success, positive value for failure. */
3446/****************************************************************************/
3447static int
3448bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3449{
3450 int i, rc = 0;
3451 u32 val;
3452
3453 DBENTER(BCE_VERBOSE_RESET);
3454
2937 /* Don't waste any time if we've timed out before. */
2938 if (sc->bce_fw_timed_out) {
2939 rc = EBUSY;
2940 goto bce_fw_sync_exit;
2941 }
2942
2943 /* Increment the message sequence number. */
2944 sc->bce_fw_wr_seq++;
2945 msg_data |= sc->bce_fw_wr_seq;
2946
3455 /* Don't waste any time if we've timed out before. */
3456 if (sc->bce_fw_timed_out) {
3457 rc = EBUSY;
3458 goto bce_fw_sync_exit;
3459 }
3460
3461 /* Increment the message sequence number. */
3462 sc->bce_fw_wr_seq++;
3463 msg_data |= sc->bce_fw_wr_seq;
3464
2947 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
3465 DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = 0x%08X\n",
3466 msg_data);
2948
2949 /* Send the message to the bootcode driver mailbox. */
2950 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2951
2952 /* Wait for the bootcode to acknowledge the message. */
2953 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2954 /* Check for a response in the bootcode firmware mailbox. */
2955 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);

--- 15 unchanged lines hidden (view full) ---

2971
2972 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
2973
2974 sc->bce_fw_timed_out = 1;
2975 rc = EBUSY;
2976 }
2977
2978bce_fw_sync_exit:
3467
3468 /* Send the message to the bootcode driver mailbox. */
3469 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
3470
3471 /* Wait for the bootcode to acknowledge the message. */
3472 for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3473 /* Check for a response in the bootcode firmware mailbox. */
3474 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_FW_MB);

--- 15 unchanged lines hidden (view full) ---

3490
3491 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_MB, msg_data);
3492
3493 sc->bce_fw_timed_out = 1;
3494 rc = EBUSY;
3495 }
3496
3497bce_fw_sync_exit:
3498 DBEXIT(BCE_VERBOSE_RESET);
2979 return (rc);
2980}
2981
2982
2983/****************************************************************************/
2984/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
2985/* */
2986/* Returns: */
2987/* Nothing. */
2988/****************************************************************************/
2989static void
3499 return (rc);
3500}
3501
3502
3503/****************************************************************************/
3504/* Load Receive Virtual 2 Physical (RV2P) processor firmware. */
3505/* */
3506/* Returns: */
3507/* Nothing. */
3508/****************************************************************************/
3509static void
2990bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
3510bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
2991 u32 rv2p_code_len, u32 rv2p_proc)
2992{
2993 int i;
2994 u32 val;
2995
3511 u32 rv2p_code_len, u32 rv2p_proc)
3512{
3513 int i;
3514 u32 val;
3515
3516 DBENTER(BCE_VERBOSE_RESET);
3517
2996 /* Set the page size used by RV2P. */
2997 if (rv2p_proc == RV2P_PROC2) {
2998 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
2999 }
3000
3001 for (i = 0; i < rv2p_code_len; i += 8) {
3002 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3003 rv2p_code++;

--- 12 unchanged lines hidden (view full) ---

3016
3017 /* Reset the processor, un-stall is done later. */
3018 if (rv2p_proc == RV2P_PROC1) {
3019 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3020 }
3021 else {
3022 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3023 }
3518 /* Set the page size used by RV2P. */
3519 if (rv2p_proc == RV2P_PROC2) {
3520 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
3521 }
3522
3523 for (i = 0; i < rv2p_code_len; i += 8) {
3524 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3525 rv2p_code++;

--- 12 unchanged lines hidden (view full) ---

3538
3539 /* Reset the processor, un-stall is done later. */
3540 if (rv2p_proc == RV2P_PROC1) {
3541 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3542 }
3543 else {
3544 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3545 }
3546
3547 DBEXIT(BCE_VERBOSE_RESET);
3024}
3025
3026
3027/****************************************************************************/
3028/* Load RISC processor firmware. */
3029/* */
3030/* Loads firmware from the file if_bcefw.h into the scratchpad memory */
3031/* associated with a particular processor. */
3032/* */
3033/* Returns: */
3034/* Nothing. */
3035/****************************************************************************/
3036static void
3037bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3038 struct fw_info *fw)
3039{
3040 u32 offset;
3041 u32 val;
3042
3548}
3549
3550
3551/****************************************************************************/
3552/* Load RISC processor firmware. */
3553/* */
3554/* Loads firmware from the file if_bcefw.h into the scratchpad memory */
3555/* associated with a particular processor. */
3556/* */
3557/* Returns: */
3558/* Nothing. */
3559/****************************************************************************/
3560static void
3561bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3562 struct fw_info *fw)
3563{
3564 u32 offset;
3565 u32 val;
3566
3567 DBENTER(BCE_VERBOSE_RESET);
3568
3043 /* Halt the CPU. */
3044 val = REG_RD_IND(sc, cpu_reg->mode);
3045 val |= cpu_reg->mode_value_halt;
3046 REG_WR_IND(sc, cpu_reg->mode, val);
3047 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3048
3049 /* Load the Text area. */
3050 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);

--- 50 unchanged lines hidden (view full) ---

3101 REG_WR_IND(sc, cpu_reg->inst, 0);
3102 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
3103
3104 /* Start the CPU. */
3105 val = REG_RD_IND(sc, cpu_reg->mode);
3106 val &= ~cpu_reg->mode_value_halt;
3107 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3108 REG_WR_IND(sc, cpu_reg->mode, val);
3569 /* Halt the CPU. */
3570 val = REG_RD_IND(sc, cpu_reg->mode);
3571 val |= cpu_reg->mode_value_halt;
3572 REG_WR_IND(sc, cpu_reg->mode, val);
3573 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3574
3575 /* Load the Text area. */
3576 offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);

--- 50 unchanged lines hidden (view full) ---

3627 REG_WR_IND(sc, cpu_reg->inst, 0);
3628 REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
3629
3630 /* Start the CPU. */
3631 val = REG_RD_IND(sc, cpu_reg->mode);
3632 val &= ~cpu_reg->mode_value_halt;
3633 REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3634 REG_WR_IND(sc, cpu_reg->mode, val);
3635
3636 DBEXIT(BCE_VERBOSE_RESET);
3109}
3110
3111
3112/****************************************************************************/
3637}
3638
3639
3640/****************************************************************************/
3113/* Initialize the RV2P, RX, TX, TPAT, and COM CPUs. */
3641/* Initialize the RX CPU. */
3114/* */
3642/* */
3115/* Loads the firmware for each CPU and starts the CPU. */
3116/* */
3117/* Returns: */
3118/* Nothing. */
3119/****************************************************************************/
3120static void
3643/* Returns: */
3644/* Nothing. */
3645/****************************************************************************/
3646static void
3121bce_init_cpus(struct bce_softc *sc)
3647bce_init_rxp_cpu(struct bce_softc *sc)
3122{
3123 struct cpu_reg cpu_reg;
3124 struct fw_info fw;
3125
3648{
3649 struct cpu_reg cpu_reg;
3650 struct fw_info fw;
3651
3126 /* Initialize the RV2P processor. */
3127 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1), RV2P_PROC1);
3128 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2), RV2P_PROC2);
3652 DBENTER(BCE_VERBOSE_RESET);
3129
3653
3130 /* Initialize the RX Processor. */
3131 cpu_reg.mode = BCE_RXP_CPU_MODE;
3132 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3133 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3134 cpu_reg.state = BCE_RXP_CPU_STATE;
3135 cpu_reg.state_value_clear = 0xffffff;
3136 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3137 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3138 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3139 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3140 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3141 cpu_reg.spad_base = BCE_RXP_SCRATCH;
3142 cpu_reg.mips_view_base = 0x8000000;
3143
3654 cpu_reg.mode = BCE_RXP_CPU_MODE;
3655 cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3656 cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3657 cpu_reg.state = BCE_RXP_CPU_STATE;
3658 cpu_reg.state_value_clear = 0xffffff;
3659 cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3660 cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3661 cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3662 cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3663 cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3664 cpu_reg.spad_base = BCE_RXP_SCRATCH;
3665 cpu_reg.mips_view_base = 0x8000000;
3666
3144 fw.ver_major = bce_RXP_b06FwReleaseMajor;
3145 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
3146 fw.ver_fix = bce_RXP_b06FwReleaseFix;
3147 fw.start_addr = bce_RXP_b06FwStartAddr;
3667 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3668 fw.ver_major = bce_RXP_b09FwReleaseMajor;
3669 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
3670 fw.ver_fix = bce_RXP_b09FwReleaseFix;
3671 fw.start_addr = bce_RXP_b09FwStartAddr;
3148
3672
3149 fw.text_addr = bce_RXP_b06FwTextAddr;
3150 fw.text_len = bce_RXP_b06FwTextLen;
3151 fw.text_index = 0;
3152 fw.text = bce_RXP_b06FwText;
3673 fw.text_addr = bce_RXP_b09FwTextAddr;
3674 fw.text_len = bce_RXP_b09FwTextLen;
3675 fw.text_index = 0;
3676 fw.text = bce_RXP_b09FwText;
3153
3677
3154 fw.data_addr = bce_RXP_b06FwDataAddr;
3155 fw.data_len = bce_RXP_b06FwDataLen;
3156 fw.data_index = 0;
3157 fw.data = bce_RXP_b06FwData;
3678 fw.data_addr = bce_RXP_b09FwDataAddr;
3679 fw.data_len = bce_RXP_b09FwDataLen;
3680 fw.data_index = 0;
3681 fw.data = bce_RXP_b09FwData;
3158
3682
3159 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
3160 fw.sbss_len = bce_RXP_b06FwSbssLen;
3161 fw.sbss_index = 0;
3162 fw.sbss = bce_RXP_b06FwSbss;
3683 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
3684 fw.sbss_len = bce_RXP_b09FwSbssLen;
3685 fw.sbss_index = 0;
3686 fw.sbss = bce_RXP_b09FwSbss;
3163
3687
3164 fw.bss_addr = bce_RXP_b06FwBssAddr;
3165 fw.bss_len = bce_RXP_b06FwBssLen;
3166 fw.bss_index = 0;
3167 fw.bss = bce_RXP_b06FwBss;
3688 fw.bss_addr = bce_RXP_b09FwBssAddr;
3689 fw.bss_len = bce_RXP_b09FwBssLen;
3690 fw.bss_index = 0;
3691 fw.bss = bce_RXP_b09FwBss;
3168
3692
3169 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
3170 fw.rodata_len = bce_RXP_b06FwRodataLen;
3171 fw.rodata_index = 0;
3172 fw.rodata = bce_RXP_b06FwRodata;
3693 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
3694 fw.rodata_len = bce_RXP_b09FwRodataLen;
3695 fw.rodata_index = 0;
3696 fw.rodata = bce_RXP_b09FwRodata;
3697 } else {
3698 fw.ver_major = bce_RXP_b06FwReleaseMajor;
3699 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
3700 fw.ver_fix = bce_RXP_b06FwReleaseFix;
3701 fw.start_addr = bce_RXP_b06FwStartAddr;
3173
3702
3703 fw.text_addr = bce_RXP_b06FwTextAddr;
3704 fw.text_len = bce_RXP_b06FwTextLen;
3705 fw.text_index = 0;
3706 fw.text = bce_RXP_b06FwText;
3707
3708 fw.data_addr = bce_RXP_b06FwDataAddr;
3709 fw.data_len = bce_RXP_b06FwDataLen;
3710 fw.data_index = 0;
3711 fw.data = bce_RXP_b06FwData;
3712
3713 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
3714 fw.sbss_len = bce_RXP_b06FwSbssLen;
3715 fw.sbss_index = 0;
3716 fw.sbss = bce_RXP_b06FwSbss;
3717
3718 fw.bss_addr = bce_RXP_b06FwBssAddr;
3719 fw.bss_len = bce_RXP_b06FwBssLen;
3720 fw.bss_index = 0;
3721 fw.bss = bce_RXP_b06FwBss;
3722
3723 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
3724 fw.rodata_len = bce_RXP_b06FwRodataLen;
3725 fw.rodata_index = 0;
3726 fw.rodata = bce_RXP_b06FwRodata;
3727 }
3728
3174 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
3175 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3176
3729 DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
3730 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3731
3177 /* Initialize the TX Processor. */
3732 DBEXIT(BCE_VERBOSE_RESET);
3733}
3734
3735
3736/****************************************************************************/
3737/* Initialize the TX CPU. */
3738/* */
3739/* Returns: */
3740/* Nothing. */
3741/****************************************************************************/
3742static void
3743bce_init_txp_cpu(struct bce_softc *sc)
3744{
3745 struct cpu_reg cpu_reg;
3746 struct fw_info fw;
3747
3748 DBENTER(BCE_VERBOSE_RESET);
3749
3178 cpu_reg.mode = BCE_TXP_CPU_MODE;
3179 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
3180 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
3181 cpu_reg.state = BCE_TXP_CPU_STATE;
3182 cpu_reg.state_value_clear = 0xffffff;
3183 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
3184 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
3185 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
3186 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
3187 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
3188 cpu_reg.spad_base = BCE_TXP_SCRATCH;
3189 cpu_reg.mips_view_base = 0x8000000;
3190
3750 cpu_reg.mode = BCE_TXP_CPU_MODE;
3751 cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
3752 cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
3753 cpu_reg.state = BCE_TXP_CPU_STATE;
3754 cpu_reg.state_value_clear = 0xffffff;
3755 cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
3756 cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
3757 cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
3758 cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
3759 cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
3760 cpu_reg.spad_base = BCE_TXP_SCRATCH;
3761 cpu_reg.mips_view_base = 0x8000000;
3762
3191 fw.ver_major = bce_TXP_b06FwReleaseMajor;
3192 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
3193 fw.ver_fix = bce_TXP_b06FwReleaseFix;
3194 fw.start_addr = bce_TXP_b06FwStartAddr;
3763 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3764 fw.ver_major = bce_TXP_b09FwReleaseMajor;
3765 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
3766 fw.ver_fix = bce_TXP_b09FwReleaseFix;
3767 fw.start_addr = bce_TXP_b09FwStartAddr;
3195
3768
3196 fw.text_addr = bce_TXP_b06FwTextAddr;
3197 fw.text_len = bce_TXP_b06FwTextLen;
3198 fw.text_index = 0;
3199 fw.text = bce_TXP_b06FwText;
3769 fw.text_addr = bce_TXP_b09FwTextAddr;
3770 fw.text_len = bce_TXP_b09FwTextLen;
3771 fw.text_index = 0;
3772 fw.text = bce_TXP_b09FwText;
3200
3773
3201 fw.data_addr = bce_TXP_b06FwDataAddr;
3202 fw.data_len = bce_TXP_b06FwDataLen;
3203 fw.data_index = 0;
3204 fw.data = bce_TXP_b06FwData;
3774 fw.data_addr = bce_TXP_b09FwDataAddr;
3775 fw.data_len = bce_TXP_b09FwDataLen;
3776 fw.data_index = 0;
3777 fw.data = bce_TXP_b09FwData;
3205
3778
3206 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
3207 fw.sbss_len = bce_TXP_b06FwSbssLen;
3208 fw.sbss_index = 0;
3209 fw.sbss = bce_TXP_b06FwSbss;
3779 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
3780 fw.sbss_len = bce_TXP_b09FwSbssLen;
3781 fw.sbss_index = 0;
3782 fw.sbss = bce_TXP_b09FwSbss;
3210
3783
3211 fw.bss_addr = bce_TXP_b06FwBssAddr;
3212 fw.bss_len = bce_TXP_b06FwBssLen;
3213 fw.bss_index = 0;
3214 fw.bss = bce_TXP_b06FwBss;
3784 fw.bss_addr = bce_TXP_b09FwBssAddr;
3785 fw.bss_len = bce_TXP_b09FwBssLen;
3786 fw.bss_index = 0;
3787 fw.bss = bce_TXP_b09FwBss;
3215
3788
3216 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
3217 fw.rodata_len = bce_TXP_b06FwRodataLen;
3218 fw.rodata_index = 0;
3219 fw.rodata = bce_TXP_b06FwRodata;
3789 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
3790 fw.rodata_len = bce_TXP_b09FwRodataLen;
3791 fw.rodata_index = 0;
3792 fw.rodata = bce_TXP_b09FwRodata;
3793 } else {
3794 fw.ver_major = bce_TXP_b06FwReleaseMajor;
3795 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
3796 fw.ver_fix = bce_TXP_b06FwReleaseFix;
3797 fw.start_addr = bce_TXP_b06FwStartAddr;
3220
3798
3799 fw.text_addr = bce_TXP_b06FwTextAddr;
3800 fw.text_len = bce_TXP_b06FwTextLen;
3801 fw.text_index = 0;
3802 fw.text = bce_TXP_b06FwText;
3803
3804 fw.data_addr = bce_TXP_b06FwDataAddr;
3805 fw.data_len = bce_TXP_b06FwDataLen;
3806 fw.data_index = 0;
3807 fw.data = bce_TXP_b06FwData;
3808
3809 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
3810 fw.sbss_len = bce_TXP_b06FwSbssLen;
3811 fw.sbss_index = 0;
3812 fw.sbss = bce_TXP_b06FwSbss;
3813
3814 fw.bss_addr = bce_TXP_b06FwBssAddr;
3815 fw.bss_len = bce_TXP_b06FwBssLen;
3816 fw.bss_index = 0;
3817 fw.bss = bce_TXP_b06FwBss;
3818
3819 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
3820 fw.rodata_len = bce_TXP_b06FwRodataLen;
3821 fw.rodata_index = 0;
3822 fw.rodata = bce_TXP_b06FwRodata;
3823 }
3824
3221 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
3222 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3223
3825 DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
3826 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3827
3224 /* Initialize the TX Patch-up Processor. */
3828 DBEXIT(BCE_VERBOSE_RESET);
3829}
3830
3831
3832/****************************************************************************/
3833/* Initialize the TPAT CPU. */
3834/* */
3835/* Returns: */
3836/* Nothing. */
3837/****************************************************************************/
3838static void
3839bce_init_tpat_cpu(struct bce_softc *sc)
3840{
3841 struct cpu_reg cpu_reg;
3842 struct fw_info fw;
3843
3844 DBENTER(BCE_VERBOSE_RESET);
3845
3225 cpu_reg.mode = BCE_TPAT_CPU_MODE;
3226 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
3227 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
3228 cpu_reg.state = BCE_TPAT_CPU_STATE;
3229 cpu_reg.state_value_clear = 0xffffff;
3230 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
3231 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
3232 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
3233 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3234 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3235 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3236 cpu_reg.mips_view_base = 0x8000000;
3237
3846 cpu_reg.mode = BCE_TPAT_CPU_MODE;
3847 cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
3848 cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
3849 cpu_reg.state = BCE_TPAT_CPU_STATE;
3850 cpu_reg.state_value_clear = 0xffffff;
3851 cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
3852 cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
3853 cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
3854 cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
3855 cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
3856 cpu_reg.spad_base = BCE_TPAT_SCRATCH;
3857 cpu_reg.mips_view_base = 0x8000000;
3858
3238 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3239 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3240 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3241 fw.start_addr = bce_TPAT_b06FwStartAddr;
3859 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3860 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
3861 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
3862 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3863 fw.start_addr = bce_TPAT_b09FwStartAddr;
3242
3864
3243 fw.text_addr = bce_TPAT_b06FwTextAddr;
3244 fw.text_len = bce_TPAT_b06FwTextLen;
3245 fw.text_index = 0;
3246 fw.text = bce_TPAT_b06FwText;
3865 fw.text_addr = bce_TPAT_b09FwTextAddr;
3866 fw.text_len = bce_TPAT_b09FwTextLen;
3867 fw.text_index = 0;
3868 fw.text = bce_TPAT_b09FwText;
3247
3869
3248 fw.data_addr = bce_TPAT_b06FwDataAddr;
3249 fw.data_len = bce_TPAT_b06FwDataLen;
3250 fw.data_index = 0;
3251 fw.data = bce_TPAT_b06FwData;
3870 fw.data_addr = bce_TPAT_b09FwDataAddr;
3871 fw.data_len = bce_TPAT_b09FwDataLen;
3872 fw.data_index = 0;
3873 fw.data = bce_TPAT_b09FwData;
3252
3874
3253 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3254 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3255 fw.sbss_index = 0;
3256 fw.sbss = bce_TPAT_b06FwSbss;
3875 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3876 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3877 fw.sbss_index = 0;
3878 fw.sbss = bce_TPAT_b09FwSbss;
3257
3879
3258 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3259 fw.bss_len = bce_TPAT_b06FwBssLen;
3260 fw.bss_index = 0;
3261 fw.bss = bce_TPAT_b06FwBss;
3880 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3881 fw.bss_len = bce_TPAT_b09FwBssLen;
3882 fw.bss_index = 0;
3883 fw.bss = bce_TPAT_b09FwBss;
3262
3884
3263 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3264 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3265 fw.rodata_index = 0;
3266 fw.rodata = bce_TPAT_b06FwRodata;
3885 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3886 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3887 fw.rodata_index = 0;
3888 fw.rodata = bce_TPAT_b09FwRodata;
3889 } else {
3890 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3891 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3892 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3893 fw.start_addr = bce_TPAT_b06FwStartAddr;
3267
3894
3268 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3269 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3895 fw.text_addr = bce_TPAT_b06FwTextAddr;
3896 fw.text_len = bce_TPAT_b06FwTextLen;
3897 fw.text_index = 0;
3898 fw.text = bce_TPAT_b06FwText;
3270
3899
3271 /* Initialize the Completion Processor. */
3272 cpu_reg.mode = BCE_COM_CPU_MODE;
3273 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3274 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3275 cpu_reg.state = BCE_COM_CPU_STATE;
3276 cpu_reg.state_value_clear = 0xffffff;
3277 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3278 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3279 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3280 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3281 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3282 cpu_reg.spad_base = BCE_COM_SCRATCH;
3283 cpu_reg.mips_view_base = 0x8000000;
3900 fw.data_addr = bce_TPAT_b06FwDataAddr;
3901 fw.data_len = bce_TPAT_b06FwDataLen;
3902 fw.data_index = 0;
3903 fw.data = bce_TPAT_b06FwData;
3284
3904
3285 fw.ver_major = bce_COM_b06FwReleaseMajor;
3286 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3287 fw.ver_fix = bce_COM_b06FwReleaseFix;
3288 fw.start_addr = bce_COM_b06FwStartAddr;
3905 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3906 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3907 fw.sbss_index = 0;
3908 fw.sbss = bce_TPAT_b06FwSbss;
3289
3909
3290 fw.text_addr = bce_COM_b06FwTextAddr;
3291 fw.text_len = bce_COM_b06FwTextLen;
3292 fw.text_index = 0;
3293 fw.text = bce_COM_b06FwText;
3910 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3911 fw.bss_len = bce_TPAT_b06FwBssLen;
3912 fw.bss_index = 0;
3913 fw.bss = bce_TPAT_b06FwBss;
3294
3914
3295 fw.data_addr = bce_COM_b06FwDataAddr;
3296 fw.data_len = bce_COM_b06FwDataLen;
3297 fw.data_index = 0;
3298 fw.data = bce_COM_b06FwData;
3915 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3916 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3917 fw.rodata_index = 0;
3918 fw.rodata = bce_TPAT_b06FwRodata;
3919 }
3299
3920
3300 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3301 fw.sbss_len = bce_COM_b06FwSbssLen;
3302 fw.sbss_index = 0;
3303 fw.sbss = bce_COM_b06FwSbss;
3921 DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3922 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3304
3923
3305 fw.bss_addr = bce_COM_b06FwBssAddr;
3306 fw.bss_len = bce_COM_b06FwBssLen;
3307 fw.bss_index = 0;
3308 fw.bss = bce_COM_b06FwBss;
3924 DBEXIT(BCE_VERBOSE_RESET);
3925}
3309
3926
3310 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3311 fw.rodata_len = bce_COM_b06FwRodataLen;
3312 fw.rodata_index = 0;
3313 fw.rodata = bce_COM_b06FwRodata;
3314
3927
3315 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3316 bce_load_cpu_fw(sc, &cpu_reg, &fw);
3928/****************************************************************************/
3929/* Initialize the CP CPU. */
3930/* */
3931/* Returns: */
3932/* Nothing. */
3933/****************************************************************************/
3934static void
3935bce_init_cp_cpu(struct bce_softc *sc)
3936{
3937 struct cpu_reg cpu_reg;
3938 struct fw_info fw;
3317
3939
3318 /* Initialize the Command Processor. */
3940 DBENTER(BCE_VERBOSE_RESET);
3941
3319 cpu_reg.mode = BCE_CP_CPU_MODE;
3320 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3321 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3322 cpu_reg.state = BCE_CP_CPU_STATE;
3323 cpu_reg.state_value_clear = 0xffffff;
3324 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3325 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3326 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3327 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3328 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3329 cpu_reg.spad_base = BCE_CP_SCRATCH;
3330 cpu_reg.mips_view_base = 0x8000000;
3331
3942 cpu_reg.mode = BCE_CP_CPU_MODE;
3943 cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3944 cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3945 cpu_reg.state = BCE_CP_CPU_STATE;
3946 cpu_reg.state_value_clear = 0xffffff;
3947 cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3948 cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3949 cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3950 cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3951 cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3952 cpu_reg.spad_base = BCE_CP_SCRATCH;
3953 cpu_reg.mips_view_base = 0x8000000;
3954
3332 fw.ver_major = bce_CP_b06FwReleaseMajor;
3333 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3334 fw.ver_fix = bce_CP_b06FwReleaseFix;
3335 fw.start_addr = bce_CP_b06FwStartAddr;
3955 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3956 fw.ver_major = bce_CP_b09FwReleaseMajor;
3957 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3958 fw.ver_fix = bce_CP_b09FwReleaseFix;
3959 fw.start_addr = bce_CP_b09FwStartAddr;
3336
3960
3337 fw.text_addr = bce_CP_b06FwTextAddr;
3338 fw.text_len = bce_CP_b06FwTextLen;
3339 fw.text_index = 0;
3340 fw.text = bce_CP_b06FwText;
3961 fw.text_addr = bce_CP_b09FwTextAddr;
3962 fw.text_len = bce_CP_b09FwTextLen;
3963 fw.text_index = 0;
3964 fw.text = bce_CP_b09FwText;
3341
3965
3342 fw.data_addr = bce_CP_b06FwDataAddr;
3343 fw.data_len = bce_CP_b06FwDataLen;
3344 fw.data_index = 0;
3345 fw.data = bce_CP_b06FwData;
3966 fw.data_addr = bce_CP_b09FwDataAddr;
3967 fw.data_len = bce_CP_b09FwDataLen;
3968 fw.data_index = 0;
3969 fw.data = bce_CP_b09FwData;
3346
3970
3347 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3348 fw.sbss_len = bce_CP_b06FwSbssLen;
3349 fw.sbss_index = 0;
3350 fw.sbss = bce_CP_b06FwSbss;
3971 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3972 fw.sbss_len = bce_CP_b09FwSbssLen;
3973 fw.sbss_index = 0;
3974 fw.sbss = bce_CP_b09FwSbss;
3351
3975
3352 fw.bss_addr = bce_CP_b06FwBssAddr;
3353 fw.bss_len = bce_CP_b06FwBssLen;
3354 fw.bss_index = 0;
3355 fw.bss = bce_CP_b06FwBss;
3976 fw.bss_addr = bce_CP_b09FwBssAddr;
3977 fw.bss_len = bce_CP_b09FwBssLen;
3978 fw.bss_index = 0;
3979 fw.bss = bce_CP_b09FwBss;
3356
3980
3357 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3358 fw.rodata_len = bce_CP_b06FwRodataLen;
3359 fw.rodata_index = 0;
3360 fw.rodata = bce_CP_b06FwRodata;
3981 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3982 fw.rodata_len = bce_CP_b09FwRodataLen;
3983 fw.rodata_index = 0;
3984 fw.rodata = bce_CP_b09FwRodata;
3985 } else {
3986 fw.ver_major = bce_CP_b06FwReleaseMajor;
3987 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3988 fw.ver_fix = bce_CP_b06FwReleaseFix;
3989 fw.start_addr = bce_CP_b06FwStartAddr;
3361
3990
3991 fw.text_addr = bce_CP_b06FwTextAddr;
3992 fw.text_len = bce_CP_b06FwTextLen;
3993 fw.text_index = 0;
3994 fw.text = bce_CP_b06FwText;
3995
3996 fw.data_addr = bce_CP_b06FwDataAddr;
3997 fw.data_len = bce_CP_b06FwDataLen;
3998 fw.data_index = 0;
3999 fw.data = bce_CP_b06FwData;
4000
4001 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4002 fw.sbss_len = bce_CP_b06FwSbssLen;
4003 fw.sbss_index = 0;
4004 fw.sbss = bce_CP_b06FwSbss;
4005
4006 fw.bss_addr = bce_CP_b06FwBssAddr;
4007 fw.bss_len = bce_CP_b06FwBssLen;
4008 fw.bss_index = 0;
4009 fw.bss = bce_CP_b06FwBss;
4010
4011 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4012 fw.rodata_len = bce_CP_b06FwRodataLen;
4013 fw.rodata_index = 0;
4014 fw.rodata = bce_CP_b06FwRodata;
4015 }
4016
3362 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3363 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4017 DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4018 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4019
4020 DBEXIT(BCE_VERBOSE_RESET);
3364}
3365
3366
3367/****************************************************************************/
4021}
4022
4023
4024/****************************************************************************/
4025/* Initialize the COM CPU. */
4026/* */
4027/* Returns: */
4028/* Nothing. */
4029/****************************************************************************/
4030static void
4031bce_init_com_cpu(struct bce_softc *sc)
4032{
4033 struct cpu_reg cpu_reg;
4034 struct fw_info fw;
4035
4036 DBENTER(BCE_VERBOSE_RESET);
4037
4038 cpu_reg.mode = BCE_COM_CPU_MODE;
4039 cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4040 cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4041 cpu_reg.state = BCE_COM_CPU_STATE;
4042 cpu_reg.state_value_clear = 0xffffff;
4043 cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4044 cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4045 cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4046 cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4047 cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4048 cpu_reg.spad_base = BCE_COM_SCRATCH;
4049 cpu_reg.mips_view_base = 0x8000000;
4050
4051 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4052 fw.ver_major = bce_COM_b09FwReleaseMajor;
4053 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4054 fw.ver_fix = bce_COM_b09FwReleaseFix;
4055 fw.start_addr = bce_COM_b09FwStartAddr;
4056
4057 fw.text_addr = bce_COM_b09FwTextAddr;
4058 fw.text_len = bce_COM_b09FwTextLen;
4059 fw.text_index = 0;
4060 fw.text = bce_COM_b09FwText;
4061
4062 fw.data_addr = bce_COM_b09FwDataAddr;
4063 fw.data_len = bce_COM_b09FwDataLen;
4064 fw.data_index = 0;
4065 fw.data = bce_COM_b09FwData;
4066
4067 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4068 fw.sbss_len = bce_COM_b09FwSbssLen;
4069 fw.sbss_index = 0;
4070 fw.sbss = bce_COM_b09FwSbss;
4071
4072 fw.bss_addr = bce_COM_b09FwBssAddr;
4073 fw.bss_len = bce_COM_b09FwBssLen;
4074 fw.bss_index = 0;
4075 fw.bss = bce_COM_b09FwBss;
4076
4077 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4078 fw.rodata_len = bce_COM_b09FwRodataLen;
4079 fw.rodata_index = 0;
4080 fw.rodata = bce_COM_b09FwRodata;
4081 } else {
4082 fw.ver_major = bce_COM_b06FwReleaseMajor;
4083 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4084 fw.ver_fix = bce_COM_b06FwReleaseFix;
4085 fw.start_addr = bce_COM_b06FwStartAddr;
4086
4087 fw.text_addr = bce_COM_b06FwTextAddr;
4088 fw.text_len = bce_COM_b06FwTextLen;
4089 fw.text_index = 0;
4090 fw.text = bce_COM_b06FwText;
4091
4092 fw.data_addr = bce_COM_b06FwDataAddr;
4093 fw.data_len = bce_COM_b06FwDataLen;
4094 fw.data_index = 0;
4095 fw.data = bce_COM_b06FwData;
4096
4097 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4098 fw.sbss_len = bce_COM_b06FwSbssLen;
4099 fw.sbss_index = 0;
4100 fw.sbss = bce_COM_b06FwSbss;
4101
4102 fw.bss_addr = bce_COM_b06FwBssAddr;
4103 fw.bss_len = bce_COM_b06FwBssLen;
4104 fw.bss_index = 0;
4105 fw.bss = bce_COM_b06FwBss;
4106
4107 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4108 fw.rodata_len = bce_COM_b06FwRodataLen;
4109 fw.rodata_index = 0;
4110 fw.rodata = bce_COM_b06FwRodata;
4111 }
4112
4113 DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4114 bce_load_cpu_fw(sc, &cpu_reg, &fw);
4115
4116 DBEXIT(BCE_VERBOSE_RESET);
4117}
4118
4119
4120/****************************************************************************/
4121/* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs. */
4122/* */
4123/* Loads the firmware for each CPU and starts the CPU. */
4124/* */
4125/* Returns: */
4126/* Nothing. */
4127/****************************************************************************/
4128static void
4129bce_init_cpus(struct bce_softc *sc)
4130{
4131 DBENTER(BCE_VERBOSE_RESET);
4132
4133 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4134 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1, sizeof(bce_xi_rv2p_proc1),
4135 RV2P_PROC1);
4136 bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2, sizeof(bce_xi_rv2p_proc2),
4137 RV2P_PROC2);
4138 } else {
4139 bce_load_rv2p_fw(sc, bce_rv2p_proc1, sizeof(bce_rv2p_proc1),
4140 RV2P_PROC1);
4141 bce_load_rv2p_fw(sc, bce_rv2p_proc2, sizeof(bce_rv2p_proc2),
4142 RV2P_PROC2);
4143 }
4144
4145 bce_init_rxp_cpu(sc);
4146 bce_init_txp_cpu(sc);
4147 bce_init_tpat_cpu(sc);
4148 bce_init_com_cpu(sc);
4149 bce_init_cp_cpu(sc);
4150
4151 DBEXIT(BCE_VERBOSE_RESET);
4152}
4153
4154
4155/****************************************************************************/
3368/* Initialize context memory. */
3369/* */
3370/* Clears the memory associated with each Context ID (CID). */
3371/* */
3372/* Returns: */
3373/* Nothing. */
3374/****************************************************************************/
3375static void
3376bce_init_ctx(struct bce_softc *sc)
3377{
4156/* Initialize context memory. */
4157/* */
4158/* Clears the memory associated with each Context ID (CID). */
4159/* */
4160/* Returns: */
4161/* Nothing. */
4162/****************************************************************************/
4163static void
4164bce_init_ctx(struct bce_softc *sc)
4165{
3378 u32 vcid = 96;
3379
4166
3380 while (vcid) {
3381 u32 vcid_addr, pcid_addr, offset;
3382 int i;
4167 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3383
4168
3384 vcid--;
4169 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4170 /* DRC: Replace this constant value with a #define. */
4171 int i, retry_cnt = 10;
4172 u32 val;
3385
4173
3386 vcid_addr = GET_CID_ADDR(vcid);
3387 pcid_addr = vcid_addr;
4174 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
3388
4175
3389 for (i = 0; i < (CTX_SIZE / PHY_CTX_SIZE); i++) {
3390 vcid_addr += (i << PHY_CTX_SHIFT);
3391 pcid_addr += (i << PHY_CTX_SHIFT);
4176 /*
4177 * BCM5709 context memory may be cached
4178 * in host memory so prepare the host memory
4179 * for access.
4180 */
4181 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4182 val |= (BCM_PAGE_BITS - 8) << 16;
4183 REG_WR(sc, BCE_CTX_COMMAND, val);
3392
4184
3393 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3394 REG_WR(sc, BCE_CTX_PAGE_TBL, pcid_addr);
4185 /* Wait for mem init command to complete. */
4186 for (i = 0; i < retry_cnt; i++) {
4187 val = REG_RD(sc, BCE_CTX_COMMAND);
4188 if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4189 break;
4190 DELAY(2);
4191 }
3395
4192
3396 /* Zero out the context. */
3397 for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3398 CTX_WR(sc, vcid_addr, offset, 0);
4193 /* ToDo: Consider returning an error here. */
4194 DBRUNIF((val & BCE_CTX_COMMAND_MEM_INIT),
4195 BCE_PRINTF("%s(): Context memory initialization failed!\n",
4196 __FUNCTION__));
4197
4198 for (i = 0; i < sc->ctx_pages; i++) {
4199 int j;
4200
4201 /* Set the physical address of the context memory cache. */
4202 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4203 BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4204 BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4205 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4206 BCE_ADDR_HI(sc->ctx_paddr[i]));
4207 REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4208 BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4209
4210 /* Verify that the context memory write was successful. */
4211 for (j = 0; j < retry_cnt; j++) {
4212 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4213 if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4214 break;
4215 DELAY(5);
4216 }
4217
4218 /* ToDo: Consider returning an error here. */
4219 DBRUNIF((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ),
4220 BCE_PRINTF("%s(): Failed to initialize context page %d!\n",
4221 __FUNCTION__, i));
3399 }
4222 }
4223 } else {
4224 u32 vcid_addr, offset;
4225
4226 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4227
4228 /*
4229 * For the 5706/5708, context memory is local to
4230 * the controller, so initialize the controller
4231 * context memory.
4232 */
4233
4234 vcid_addr = GET_CID_ADDR(96);
4235 while (vcid_addr) {
4236
4237 vcid_addr -= PHY_CTX_SIZE;
4238
4239 REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4240 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4241
4242 for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4243 CTX_WR(sc, 0x00, offset, 0);
4244 }
4245
4246 REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4247 REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4248 }
4249
3400 }
4250 }
4251 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3401}
3402
3403
3404/****************************************************************************/
3405/* Fetch the permanent MAC address of the controller. */
3406/* */
3407/* Returns: */
3408/* Nothing. */
3409/****************************************************************************/
3410static void
3411bce_get_mac_addr(struct bce_softc *sc)
3412{
3413 u32 mac_lo = 0, mac_hi = 0;
3414
4252}
4253
4254
4255/****************************************************************************/
4256/* Fetch the permanent MAC address of the controller. */
4257/* */
4258/* Returns: */
4259/* Nothing. */
4260/****************************************************************************/
4261static void
4262bce_get_mac_addr(struct bce_softc *sc)
4263{
4264 u32 mac_lo = 0, mac_hi = 0;
4265
4266 DBENTER(BCE_VERBOSE_RESET);
3415 /*
3416 * The NetXtreme II bootcode populates various NIC
3417 * power-on and runtime configuration items in a
3418 * shared memory area. The factory configured MAC
3419 * address is available from both NVRAM and the
3420 * shared memory area so we'll read the value from
3421 * shared memory for speed.
3422 */
3423
3424 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base +
3425 BCE_PORT_HW_CFG_MAC_UPPER);
3426 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base +
3427 BCE_PORT_HW_CFG_MAC_LOWER);
3428
3429 if ((mac_lo == 0) && (mac_hi == 0)) {
4267 /*
4268 * The NetXtreme II bootcode populates various NIC
4269 * power-on and runtime configuration items in a
4270 * shared memory area. The factory configured MAC
4271 * address is available from both NVRAM and the
4272 * shared memory area so we'll read the value from
4273 * shared memory for speed.
4274 */
4275
4276 mac_hi = REG_RD_IND(sc, sc->bce_shmem_base +
4277 BCE_PORT_HW_CFG_MAC_UPPER);
4278 mac_lo = REG_RD_IND(sc, sc->bce_shmem_base +
4279 BCE_PORT_HW_CFG_MAC_LOWER);
4280
4281 if ((mac_lo == 0) && (mac_hi == 0)) {
3430 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4282 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
3431 __FILE__, __LINE__);
3432 } else {
3433 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3434 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3435 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3436 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3437 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3438 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3439 }
3440
3441 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
4283 __FILE__, __LINE__);
4284 } else {
4285 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4286 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4287 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4288 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4289 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4290 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4291 }
4292
4293 DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
4294 DBEXIT(BCE_VERBOSE_RESET);
3442}
3443
3444
3445/****************************************************************************/
3446/* Program the MAC address. */
3447/* */
3448/* Returns: */
3449/* Nothing. */
3450/****************************************************************************/
3451static void
3452bce_set_mac_addr(struct bce_softc *sc)
3453{
3454 u32 val;
3455 u8 *mac_addr = sc->eaddr;
3456
4295}
4296
4297
4298/****************************************************************************/
4299/* Program the MAC address. */
4300/* */
4301/* Returns: */
4302/* Nothing. */
4303/****************************************************************************/
4304static void
4305bce_set_mac_addr(struct bce_softc *sc)
4306{
4307 u32 val;
4308 u8 *mac_addr = sc->eaddr;
4309
4310 /* ToDo: Add support for setting multiple MAC addresses. */
4311
4312 DBENTER(BCE_VERBOSE_RESET);
3457 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":");
3458
3459 val = (mac_addr[0] << 8) | mac_addr[1];
3460
3461 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3462
3463 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
3464 (mac_addr[4] << 8) | mac_addr[5];
3465
3466 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4313 DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = %6D\n", sc->eaddr, ":");
4314
4315 val = (mac_addr[0] << 8) | mac_addr[1];
4316
4317 REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4318
4319 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4320 (mac_addr[4] << 8) | mac_addr[5];
4321
4322 REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4323
4324 DBEXIT(BCE_VERBOSE_RESET);
3467}
3468
3469
3470/****************************************************************************/
3471/* Stop the controller. */
3472/* */
3473/* Returns: */
3474/* Nothing. */
3475/****************************************************************************/
3476static void
3477bce_stop(struct bce_softc *sc)
3478{
3479 struct ifnet *ifp;
3480 struct ifmedia_entry *ifm;
3481 struct mii_data *mii = NULL;
3482 int mtmp, itmp;
3483
4325}
4326
4327
4328/****************************************************************************/
4329/* Stop the controller. */
4330/* */
4331/* Returns: */
4332/* Nothing. */
4333/****************************************************************************/
4334static void
4335bce_stop(struct bce_softc *sc)
4336{
4337 struct ifnet *ifp;
4338 struct ifmedia_entry *ifm;
4339 struct mii_data *mii = NULL;
4340 int mtmp, itmp;
4341
3484 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
4342 DBENTER(BCE_VERBOSE_RESET);
3485
3486 BCE_LOCK_ASSERT(sc);
3487
3488 ifp = sc->bce_ifp;
3489
3490 mii = device_get_softc(sc->bce_miibus);
3491
3492 callout_stop(&sc->bce_tick_callout);
3493
3494 /* Disable the transmit/receive blocks. */
4343
4344 BCE_LOCK_ASSERT(sc);
4345
4346 ifp = sc->bce_ifp;
4347
4348 mii = device_get_softc(sc->bce_miibus);
4349
4350 callout_stop(&sc->bce_tick_callout);
4351
4352 /* Disable the transmit/receive blocks. */
3495 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, 0x5ffffff);
4353 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3496 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3497 DELAY(20);
3498
3499 bce_disable_intr(sc);
3500
3501 /* Free RX buffers. */
3502#ifdef BCE_USE_SPLIT_HEADER
3503 bce_free_pg_chain(sc);

--- 23 unchanged lines hidden (view full) ---

3527
3528 ifp->if_flags = itmp;
3529 sc->watchdog_timer = 0;
3530
3531 sc->bce_link = 0;
3532
3533 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
3534
4354 REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4355 DELAY(20);
4356
4357 bce_disable_intr(sc);
4358
4359 /* Free RX buffers. */
4360#ifdef BCE_USE_SPLIT_HEADER
4361 bce_free_pg_chain(sc);

--- 23 unchanged lines hidden (view full) ---

4385
4386 ifp->if_flags = itmp;
4387 sc->watchdog_timer = 0;
4388
4389 sc->bce_link = 0;
4390
4391 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4392
3535 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4393 DBEXIT(BCE_VERBOSE_RESET);
3536}
3537
3538
3539static int
3540bce_reset(struct bce_softc *sc, u32 reset_code)
3541{
3542 u32 val;
3543 int i, rc = 0;
3544
4394}
4395
4396
4397static int
4398bce_reset(struct bce_softc *sc, u32 reset_code)
4399{
4400 u32 val;
4401 int i, rc = 0;
4402
3545 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4403 DBENTER(BCE_VERBOSE_RESET);
4404
4405 DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
3546 __FUNCTION__, reset_code);
3547
3548 /* Wait for pending PCI transactions to complete. */
3549 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3550 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3551 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3552 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3553 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3554 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3555 DELAY(5);
3556
4406 __FUNCTION__, reset_code);
4407
4408 /* Wait for pending PCI transactions to complete. */
4409 REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4410 BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4411 BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4412 BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4413 BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4414 val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4415 DELAY(5);
4416
4417 /* Disable DMA */
4418 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4419 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4420 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4421 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4422 }
4423
3557 /* Assume bootcode is running. */
3558 sc->bce_fw_timed_out = 0;
3559
3560 /* Give the firmware a chance to prepare for the reset. */
3561 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3562 if (rc)
3563 goto bce_reset_exit;
3564
3565 /* Set a firmware reminder that this is a soft reset. */
3566 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
3567 BCE_DRV_RESET_SIGNATURE_MAGIC);
3568
3569 /* Dummy read to force the chip to complete all current transactions. */
3570 val = REG_RD(sc, BCE_MISC_ID);
3571
3572 /* Chip reset. */
4424 /* Assume bootcode is running. */
4425 sc->bce_fw_timed_out = 0;
4426
4427 /* Give the firmware a chance to prepare for the reset. */
4428 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4429 if (rc)
4430 goto bce_reset_exit;
4431
4432 /* Set a firmware reminder that this is a soft reset. */
4433 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_RESET_SIGNATURE,
4434 BCE_DRV_RESET_SIGNATURE_MAGIC);
4435
4436 /* Dummy read to force the chip to complete all current transactions. */
4437 val = REG_RD(sc, BCE_MISC_ID);
4438
4439 /* Chip reset. */
3573 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3574 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3575 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3576 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4440 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4441 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
4442 REG_RD(sc, BCE_MISC_COMMAND);
4443 DELAY(5);
3577
4444
3578 /* Allow up to 30us for reset to complete. */
3579 for (i = 0; i < 10; i++) {
3580 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3581 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3582 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
3583 break;
4445 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4446 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4447
4448 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4449 } else {
4450 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4451 BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4452 BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4453 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4454
4455 /* Allow up to 30us for reset to complete. */
4456 for (i = 0; i < 10; i++) {
4457 val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
4458 if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4459 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4460 break;
4461 }
4462 DELAY(10);
3584 }
4463 }
3585 DELAY(10);
3586 }
3587
4464
3588 /* Check that reset completed successfully. */
3589 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3590 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3591 BCE_PRINTF("%s(%d): Reset failed!\n",
3592 __FILE__, __LINE__);
3593 rc = EBUSY;
3594 goto bce_reset_exit;
4465 /* Check that reset completed successfully. */
4466 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4467 BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4468 BCE_PRINTF("%s(%d): Reset failed!\n",
4469 __FILE__, __LINE__);
4470 rc = EBUSY;
4471 goto bce_reset_exit;
4472 }
3595 }
3596
3597 /* Make sure byte swapping is properly configured. */
3598 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3599 if (val != 0x01020304) {
4473 }
4474
4475 /* Make sure byte swapping is properly configured. */
4476 val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
4477 if (val != 0x01020304) {
3600 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
4478 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
3601 __FILE__, __LINE__);
3602 rc = ENODEV;
3603 goto bce_reset_exit;
3604 }
3605
3606 /* Just completed a reset, assume that firmware is running again. */
3607 sc->bce_fw_timed_out = 0;
3608
3609 /* Wait for the firmware to finish its initialization. */
3610 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3611 if (rc)
3612 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n",
3613 __FILE__, __LINE__);
3614
3615bce_reset_exit:
4479 __FILE__, __LINE__);
4480 rc = ENODEV;
4481 goto bce_reset_exit;
4482 }
4483
4484 /* Just completed a reset, assume that firmware is running again. */
4485 sc->bce_fw_timed_out = 0;
4486
4487 /* Wait for the firmware to finish its initialization. */
4488 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
4489 if (rc)
4490 BCE_PRINTF("%s(%d): Firmware did not complete initialization!\n",
4491 __FILE__, __LINE__);
4492
4493bce_reset_exit:
4494 DBEXIT(BCE_VERBOSE_RESET);
3616 return (rc);
3617}
3618
3619
3620static int
3621bce_chipinit(struct bce_softc *sc)
3622{
3623 u32 val;
3624 int rc = 0;
3625
4495 return (rc);
4496}
4497
4498
4499static int
4500bce_chipinit(struct bce_softc *sc)
4501{
4502 u32 val;
4503 int rc = 0;
4504
3626 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
4505 DBENTER(BCE_VERBOSE_RESET);
3627
4506
3628 /* Make sure the interrupt is not active. */
3629 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
4507 bce_disable_intr(sc);
3630
4508
3631 /*
4509 /*
3632 * Initialize DMA byte/word swapping, configure the number of DMA
3633 * channels and PCI clock compensation delay.
3634 */
3635 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3636 BCE_DMA_CONFIG_DATA_WORD_SWAP |
3637#if BYTE_ORDER == BIG_ENDIAN
3638 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3639#endif

--- 13 unchanged lines hidden (view full) ---

3653 */
3654 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
3655 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
3656 !(sc->bce_flags & BCE_PCIX_FLAG))
3657 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3658
3659 REG_WR(sc, BCE_DMA_CONFIG, val);
3660
4510 * Initialize DMA byte/word swapping, configure the number of DMA
4511 * channels and PCI clock compensation delay.
4512 */
4513 val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
4514 BCE_DMA_CONFIG_DATA_WORD_SWAP |
4515#if BYTE_ORDER == BIG_ENDIAN
4516 BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
4517#endif

--- 13 unchanged lines hidden (view full) ---

4531 */
4532 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
4533 (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
4534 !(sc->bce_flags & BCE_PCIX_FLAG))
4535 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
4536
4537 REG_WR(sc, BCE_DMA_CONFIG, val);
4538
3661 /* Clear the PCI-X relaxed ordering bit. See errata E3_5708CA0_570. */
3662 if (sc->bce_flags & BCE_PCIX_FLAG) {
3663 u16 val;
3664
3665 val = pci_read_config(sc->bce_dev, BCE_PCI_PCIX_CMD, 2);
3666 pci_write_config(sc->bce_dev, BCE_PCI_PCIX_CMD, val & ~0x2, 2);
3667 }
3668
3669 /* Enable the RX_V2P and Context state machines before access. */
3670 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3671 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3672 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3673 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3674
3675 /* Initialize context mapping and zero out the quick contexts. */
3676 bce_init_ctx(sc);

--- 6 unchanged lines hidden (view full) ---

3683 rc = ENODEV;
3684 goto bce_chipinit_exit;
3685 }
3686
3687 /* Set the kernel bypass block size */
3688 val = REG_RD(sc, BCE_MQ_CONFIG);
3689 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3690 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4539 /* Enable the RX_V2P and Context state machines before access. */
4540 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4541 BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4542 BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4543 BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4544
4545 /* Initialize context mapping and zero out the quick contexts. */
4546 bce_init_ctx(sc);

--- 6 unchanged lines hidden (view full) ---

4553 rc = ENODEV;
4554 goto bce_chipinit_exit;
4555 }
4556
4557 /* Set the kernel bypass block size */
4558 val = REG_RD(sc, BCE_MQ_CONFIG);
4559 val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4560 val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4561
4562 /* Enable bins used on the 5709. */
4563 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4564 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
4565 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
4566 val |= BCE_MQ_CONFIG_HALT_DIS;
4567 }
4568
3691 REG_WR(sc, BCE_MQ_CONFIG, val);
3692
3693 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3694 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3695 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3696
3697 /* Set the page size and clear the RV2P processor stall bits. */
3698 val = (BCM_PAGE_BITS - 8) << 24;
3699 REG_WR(sc, BCE_RV2P_CONFIG, val);
3700
3701 /* Configure page size. */
3702 val = REG_RD(sc, BCE_TBDR_CONFIG);
3703 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
3704 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
3705 REG_WR(sc, BCE_TBDR_CONFIG, val);
3706
4569 REG_WR(sc, BCE_MQ_CONFIG, val);
4570
4571 val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4572 REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
4573 REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
4574
4575 /* Set the page size and clear the RV2P processor stall bits. */
4576 val = (BCM_PAGE_BITS - 8) << 24;
4577 REG_WR(sc, BCE_RV2P_CONFIG, val);
4578
4579 /* Configure page size. */
4580 val = REG_RD(sc, BCE_TBDR_CONFIG);
4581 val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
4582 val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4583 REG_WR(sc, BCE_TBDR_CONFIG, val);
4584
4585 /* Set the perfect match control register to default. */
4586 REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
4587
3707bce_chipinit_exit:
4588bce_chipinit_exit:
3708 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4589 DBEXIT(BCE_VERBOSE_RESET);
3709
3710 return(rc);
3711}
3712
3713
3714/****************************************************************************/
3715/* Initialize the controller in preparation to send/receive traffic. */
3716/* */
3717/* Returns: */
3718/* 0 for success, positive value for failure. */
3719/****************************************************************************/
3720static int
3721bce_blockinit(struct bce_softc *sc)
3722{
3723 u32 reg, val;
3724 int rc = 0;
3725
4590
4591 return(rc);
4592}
4593
4594
4595/****************************************************************************/
4596/* Initialize the controller in preparation to send/receive traffic. */
4597/* */
4598/* Returns: */
4599/* 0 for success, positive value for failure. */
4600/****************************************************************************/
4601static int
4602bce_blockinit(struct bce_softc *sc)
4603{
4604 u32 reg, val;
4605 int rc = 0;
4606
3726 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
4607 DBENTER(BCE_VERBOSE_RESET);
3727
3728 /* Load the hardware default MAC address. */
3729 bce_set_mac_addr(sc);
3730
3731 /* Set the Ethernet backoff seed value */
3732 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
3733 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
3734 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);

--- 29 unchanged lines hidden (view full) ---

3764 REG_WR(sc, BCE_HC_RX_TICKS,
3765 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
3766 REG_WR(sc, BCE_HC_COM_TICKS,
3767 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
3768 REG_WR(sc, BCE_HC_CMD_TICKS,
3769 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
3770 REG_WR(sc, BCE_HC_STATS_TICKS,
3771 (sc->bce_stats_ticks & 0xffff00));
4608
4609 /* Load the hardware default MAC address. */
4610 bce_set_mac_addr(sc);
4611
4612 /* Set the Ethernet backoff seed value */
4613 val = sc->eaddr[0] + (sc->eaddr[1] << 8) +
4614 (sc->eaddr[2] << 16) + (sc->eaddr[3] ) +
4615 (sc->eaddr[4] << 8) + (sc->eaddr[5] << 16);

--- 29 unchanged lines hidden (view full) ---

4645 REG_WR(sc, BCE_HC_RX_TICKS,
4646 (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
4647 REG_WR(sc, BCE_HC_COM_TICKS,
4648 (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
4649 REG_WR(sc, BCE_HC_CMD_TICKS,
4650 (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
4651 REG_WR(sc, BCE_HC_STATS_TICKS,
4652 (sc->bce_stats_ticks & 0xffff00));
3772 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS,
3773 0xbb8); /* 3ms */
3774 REG_WR(sc, BCE_HC_CONFIG,
3775 (BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
3776 BCE_HC_CONFIG_COLLECT_STATS));
4653 REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8); /* 3ms */
3777
4654
4655 /* Configure the Host Coalescing block. */
4656 val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
4657 BCE_HC_CONFIG_COLLECT_STATS;
4658
4659#if 0
4660 /* ToDo: Add MSI-X support. */
4661 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
4662 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
4663 BCE_HC_SB_CONFIG_1;
4664
4665 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
4666
4667 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
4668 BCE_HC_SB_CONFIG_1_ONE_SHOT);
4669
4670 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
4671 (sc->tx_quick_cons_trip_int << 16) |
4672 sc->tx_quick_cons_trip);
4673
4674 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
4675 (sc->tx_ticks_int << 16) | sc->tx_ticks);
4676
4677 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4678 }
4679
4680 /*
4681 * Tell the HC block to automatically set the
4682 * INT_MASK bit after an MSI/MSI-X interrupt
4683 * is generated so the driver doesn't have to.
4684 */
4685 if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
4686 val |= BCE_HC_CONFIG_ONE_SHOT;
4687
4688 /* Set the MSI-X status blocks to 128 byte boundaries. */
4689 if (sc->bce_flags & BCE_USING_MSIX_FLAG)
4690 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4691#endif
4692
4693 REG_WR(sc, BCE_HC_CONFIG, val);
4694
3778 /* Clear the internal statistics counters. */
3779 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
3780
3781 /* Verify that bootcode is running. */
3782 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
3783
3784 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
3785 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",

--- 5 unchanged lines hidden (view full) ---

3791 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
3792 "Expected: 08%08X\n", __FILE__, __LINE__,
3793 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
3794 BCE_DEV_INFO_SIGNATURE_MAGIC);
3795 rc = ENODEV;
3796 goto bce_blockinit_exit;
3797 }
3798
4695 /* Clear the internal statistics counters. */
4696 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4697
4698 /* Verify that bootcode is running. */
4699 reg = REG_RD_IND(sc, sc->bce_shmem_base + BCE_DEV_INFO_SIGNATURE);
4700
4701 DBRUNIF(DB_RANDOMTRUE(bce_debug_bootcode_running_failure),
4702 BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",

--- 5 unchanged lines hidden (view full) ---

4708 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4709 "Expected: 08%08X\n", __FILE__, __LINE__,
4710 (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
4711 BCE_DEV_INFO_SIGNATURE_MAGIC);
4712 rc = ENODEV;
4713 goto bce_blockinit_exit;
4714 }
4715
4716 /* Enable DMA */
4717 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4718 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4719 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4720 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4721 }
4722
3799 /* Allow bootcode to apply any additional fixes before enabling MAC. */
3800 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
3801
3802 /* Enable link state change interrupt generation. */
3803 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
3804
3805 /* Enable all remaining blocks in the MAC. */
4723 /* Allow bootcode to apply any additional fixes before enabling MAC. */
4724 rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 | BCE_DRV_MSG_CODE_RESET);
4725
4726 /* Enable link state change interrupt generation. */
4727 REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
4728
4729 /* Enable all remaining blocks in the MAC. */
3806 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
4730 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
4731 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT_XI);
4732 else
4733 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
4734
3807 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
3808 DELAY(20);
3809
4735 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4736 DELAY(20);
4737
4738 /* Save the current host coalescing block settings. */
4739 sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
4740
3810bce_blockinit_exit:
4741bce_blockinit_exit:
3811 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4742 DBEXIT(BCE_VERBOSE_RESET);
3812
3813 return (rc);
3814}
3815
3816
3817/****************************************************************************/
3818/* Encapsulate an mbuf into the rx_bd chain. */
3819/* */

--- 8 unchanged lines hidden (view full) ---

3828 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
3829 struct mbuf *m_new = NULL;
3830 struct rx_bd *rxbd;
3831 int nsegs, error, rc = 0;
3832#ifdef BCE_DEBUG
3833 u16 debug_chain_prod = *chain_prod;
3834#endif
3835
4743
4744 return (rc);
4745}
4746
4747
4748/****************************************************************************/
4749/* Encapsulate an mbuf into the rx_bd chain. */
4750/* */

--- 8 unchanged lines hidden (view full) ---

4759 bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4760 struct mbuf *m_new = NULL;
4761 struct rx_bd *rxbd;
4762 int nsegs, error, rc = 0;
4763#ifdef BCE_DEBUG
4764 u16 debug_chain_prod = *chain_prod;
4765#endif
4766
3836 DBPRINT(sc, (BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD), "Entering %s()\n",
3837 __FUNCTION__);
4767 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
3838
3839 /* Make sure the inputs are valid. */
3840 DBRUNIF((*chain_prod > MAX_RX_BD),
3841 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n",
3842 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD));
3843
4768
4769 /* Make sure the inputs are valid. */
4770 DBRUNIF((*chain_prod > MAX_RX_BD),
4771 BCE_PRINTF("%s(%d): RX producer out of range: 0x%04X > 0x%04X\n",
4772 __FILE__, __LINE__, *chain_prod, (u16) MAX_RX_BD));
4773
3844 DBPRINT(sc, BCE_VERBOSE, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
4774 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, chain_prod = 0x%04X, "
3845 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
3846
3847 /* Update some debug statistic counters */
4775 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
4776
4777 /* Update some debug statistic counters */
3848 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4778 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
3849 sc->rx_low_watermark = sc->free_rx_bd);
3850 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
3851
3852 /* Check whether this is a new mbuf allocation. */
3853 if (m == NULL) {
3854
3855 /* Simulate an mbuf allocation failure. */
3856 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4779 sc->rx_low_watermark = sc->free_rx_bd);
4780 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4781
4782 /* Check whether this is a new mbuf allocation. */
4783 if (m == NULL) {
4784
4785 /* Simulate an mbuf allocation failure. */
4786 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3857 sc->mbuf_alloc_failed++;
4787 sc->mbuf_alloc_failed++;
3858 sc->debug_mbuf_sim_alloc_failed++;
3859 rc = ENOBUFS;
3860 goto bce_get_rx_buf_exit);
3861
3862 /* This is a new mbuf allocation. */
3863#ifdef BCE_USE_SPLIT_HEADER
3864 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
3865#else
4788 sc->debug_mbuf_sim_alloc_failed++;
4789 rc = ENOBUFS;
4790 goto bce_get_rx_buf_exit);
4791
4792 /* This is a new mbuf allocation. */
4793#ifdef BCE_USE_SPLIT_HEADER
4794 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
4795#else
3866 if (sc->rx_bd_mbuf_alloc_size == MCLBYTES)
4796 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
3867 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
3868 else
3869 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size);
3870#endif
3871
3872 if (m_new == NULL) {
3873 sc->mbuf_alloc_failed++;
3874 rc = ENOBUFS;

--- 26 unchanged lines hidden (view full) ---

3901 __FILE__, __LINE__, error);
3902
3903 m_freem(m_new);
3904 DBRUN(sc->debug_rx_mbuf_alloc--);
3905
3906 rc = ENOBUFS;
3907 goto bce_get_rx_buf_exit;
3908 }
4797 m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
4798 else
4799 m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, sc->rx_bd_mbuf_alloc_size);
4800#endif
4801
4802 if (m_new == NULL) {
4803 sc->mbuf_alloc_failed++;
4804 rc = ENOBUFS;

--- 26 unchanged lines hidden (view full) ---

4831 __FILE__, __LINE__, error);
4832
4833 m_freem(m_new);
4834 DBRUN(sc->debug_rx_mbuf_alloc--);
4835
4836 rc = ENOBUFS;
4837 goto bce_get_rx_buf_exit;
4838 }
3909
4839
3910 /* All mbufs must map to a single segment. */
3911 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
3912 __FUNCTION__, nsegs));
3913
3914 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
3915
3916 /* Setup the rx_bd for the segment. */
3917 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
3918
3919 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
3920 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
3921 rxbd->rx_bd_len = htole32(segs[0].ds_len);
3922 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
4840 /* All mbufs must map to a single segment. */
4841 KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
4842 __FUNCTION__, nsegs));
4843
4844 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
4845
4846 /* Setup the rx_bd for the segment. */
4847 rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
4848
4849 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(segs[0].ds_addr));
4850 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(segs[0].ds_addr));
4851 rxbd->rx_bd_len = htole32(segs[0].ds_len);
4852 rxbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
3923 *prod_bseq += segs[0].ds_len;
4853 *prod_bseq += segs[0].ds_len;
3924
3925 /* Save the mbuf and update our counter. */
3926 sc->rx_mbuf_ptr[*chain_prod] = m_new;
3927 sc->free_rx_bd -= nsegs;
3928
4854
4855 /* Save the mbuf and update our counter. */
4856 sc->rx_mbuf_ptr[*chain_prod] = m_new;
4857 sc->free_rx_bd -= nsegs;
4858
3929 DBRUNMSG(BCE_EXCESSIVE, bce_dump_rx_mbuf_chain(sc, debug_chain_prod,
4859 DBRUNMSG(BCE_INSANE_RECV, bce_dump_rx_mbuf_chain(sc, debug_chain_prod,
3930 nsegs));
3931
4860 nsegs));
4861
3932 DBPRINT(sc, BCE_VERBOSE, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
4862 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, chain_prod = 0x%04X, "
3933 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
3934
3935bce_get_rx_buf_exit:
4863 "prod_bseq = 0x%08X\n", __FUNCTION__, *prod, *chain_prod, *prod_bseq);
4864
4865bce_get_rx_buf_exit:
3936 DBPRINT(sc, (BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD), "Exiting %s()\n",
3937 __FUNCTION__);
4866 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
3938
3939 return(rc);
3940}
3941
3942
3943#ifdef BCE_USE_SPLIT_HEADER
3944/****************************************************************************/
3945/* Encapsulate an mbuf cluster into the page chain. */

--- 9 unchanged lines hidden (view full) ---

3955 bus_addr_t busaddr;
3956 struct mbuf *m_new = NULL;
3957 struct rx_bd *pgbd;
3958 int error, rc = 0;
3959#ifdef BCE_DEBUG
3960 u16 debug_prod_idx = *prod_idx;
3961#endif
3962
4867
4868 return(rc);
4869}
4870
4871
4872#ifdef BCE_USE_SPLIT_HEADER
4873/****************************************************************************/
4874/* Encapsulate an mbuf cluster into the page chain. */

--- 9 unchanged lines hidden (view full) ---

4884 bus_addr_t busaddr;
4885 struct mbuf *m_new = NULL;
4886 struct rx_bd *pgbd;
4887 int error, rc = 0;
4888#ifdef BCE_DEBUG
4889 u16 debug_prod_idx = *prod_idx;
4890#endif
4891
3963 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Entering %s()\n",
3964 __FUNCTION__);
4892 DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
3965
3966 /* Make sure the inputs are valid. */
3967 DBRUNIF((*prod_idx > MAX_PG_BD),
3968 BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n",
3969 __FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD));
3970
4893
4894 /* Make sure the inputs are valid. */
4895 DBRUNIF((*prod_idx > MAX_PG_BD),
4896 BCE_PRINTF("%s(%d): page producer out of range: 0x%04X > 0x%04X\n",
4897 __FILE__, __LINE__, *prod_idx, (u16) MAX_PG_BD));
4898
3971 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(enter): prod = 0x%04X, "
4899 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
3972 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
3973
3974 /* Update counters if we've hit a new low or run out of pages. */
4900 "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
4901
4902 /* Update counters if we've hit a new low or run out of pages. */
3975 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
4903 DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
3976 sc->pg_low_watermark = sc->free_pg_bd);
3977 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
3978
3979 /* Check whether this is a new mbuf allocation. */
3980 if (m == NULL) {
3981
3982 /* Simulate an mbuf allocation failure. */
3983 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
4904 sc->pg_low_watermark = sc->free_pg_bd);
4905 DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
4906
4907 /* Check whether this is a new mbuf allocation. */
4908 if (m == NULL) {
4909
4910 /* Simulate an mbuf allocation failure. */
4911 DBRUNIF(DB_RANDOMTRUE(bce_debug_mbuf_allocation_failure),
3984 sc->mbuf_alloc_failed++;
4912 sc->mbuf_alloc_failed++;
3985 sc->debug_mbuf_sim_alloc_failed++;
3986 rc = ENOBUFS;
3987 goto bce_get_pg_buf_exit);
3988
3989 /* This is a new mbuf allocation. */
3990 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
3991 if (m_new == NULL) {
3992 sc->mbuf_alloc_failed++;

--- 26 unchanged lines hidden (view full) ---

4019 DBRUN(sc->debug_pg_mbuf_alloc--);
4020
4021 rc = ENOBUFS;
4022 goto bce_get_pg_buf_exit;
4023 }
4024
4025 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
4026
4913 sc->debug_mbuf_sim_alloc_failed++;
4914 rc = ENOBUFS;
4915 goto bce_get_pg_buf_exit);
4916
4917 /* This is a new mbuf allocation. */
4918 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
4919 if (m_new == NULL) {
4920 sc->mbuf_alloc_failed++;

--- 26 unchanged lines hidden (view full) ---

4947 DBRUN(sc->debug_pg_mbuf_alloc--);
4948
4949 rc = ENOBUFS;
4950 goto bce_get_pg_buf_exit;
4951 }
4952
4953 /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREWRITE) here? */
4954
4027 /*
4955 /*
4028 * The page chain uses the same rx_bd data structure
4029 * as the receive chain but doesn't require a byte sequence (bseq).
4030 */
4031 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
4032
4033 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr));
4034 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr));
4035 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size);
4036 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
4037
4038 /* Save the mbuf and update our counter. */
4039 sc->pg_mbuf_ptr[*prod_idx] = m_new;
4040 sc->free_pg_bd--;
4041
4956 * The page chain uses the same rx_bd data structure
4957 * as the receive chain but doesn't require a byte sequence (bseq).
4958 */
4959 pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
4960
4961 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(busaddr));
4962 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(busaddr));
4963 pgbd->rx_bd_len = htole32(sc->pg_bd_mbuf_alloc_size);
4964 pgbd->rx_bd_flags = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
4965
4966 /* Save the mbuf and update our counter. */
4967 sc->pg_mbuf_ptr[*prod_idx] = m_new;
4968 sc->free_pg_bd--;
4969
4042 DBRUNMSG(BCE_VERBOSE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx,
4970 DBRUNMSG(BCE_INSANE_RECV, bce_dump_pg_mbuf_chain(sc, debug_prod_idx,
4043 1));
4044
4971 1));
4972
4045 DBPRINT(sc, BCE_VERBOSE_RECV, "%s(exit): prod = 0x%04X, "
4973 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
4046 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
4047
4048bce_get_pg_buf_exit:
4974 "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
4975
4976bce_get_pg_buf_exit:
4049 DBPRINT(sc, (BCE_VERBOSE_RESET | BCE_VERBOSE_RECV), "Exiting %s()\n",
4050 __FUNCTION__);
4977 DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
4051
4052 return(rc);
4053}
4054#endif /* BCE_USE_SPLIT_HEADER */
4055
4978
4979 return(rc);
4980}
4981#endif /* BCE_USE_SPLIT_HEADER */
4982
4983/****************************************************************************/
4984/* Initialize the TX context memory. */
4985/* */
4986/* Returns: */
4987/* Nothing */
4988/****************************************************************************/
4989static void
4990bce_init_tx_context(struct bce_softc *sc)
4991{
4992 u32 val;
4056
4993
4994 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
4995
4996 /* Initialize the context ID for an L2 TX chain. */
4997 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4998 /* Set the CID type to support an L2 connection. */
4999 val = BCE_L2CTX_TYPE_TYPE_L2 | BCE_L2CTX_TYPE_SIZE_L2;
5000 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE_XI, val);
5001 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5002 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE_XI, val);
5003
5004 /* Point the hardware to the first page in the chain. */
5005 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5006 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI_XI, val);
5007 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5008 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO_XI, val);
5009 } else {
5010 /* Set the CID type to support an L2 connection. */
5011 val = BCE_L2CTX_TYPE_TYPE_L2 | BCE_L2CTX_TYPE_SIZE_L2;
5012 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
5013 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
5014 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
5015
5016 /* Point the hardware to the first page in the chain. */
5017 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5018 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
5019 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5020 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
5021 }
5022
5023 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5024}
5025
5026
4057/****************************************************************************/
4058/* Allocate memory and initialize the TX data structures. */
4059/* */
4060/* Returns: */
4061/* 0 for success, positive value for failure. */
4062/****************************************************************************/
4063static int
4064bce_init_tx_chain(struct bce_softc *sc)
4065{
4066 struct tx_bd *txbd;
5027/****************************************************************************/
5028/* Allocate memory and initialize the TX data structures. */
5029/* */
5030/* Returns: */
5031/* 0 for success, positive value for failure. */
5032/****************************************************************************/
5033static int
5034bce_init_tx_chain(struct bce_softc *sc)
5035{
5036 struct tx_bd *txbd;
4067 u32 val;
4068 int i, rc = 0;
4069
5037 int i, rc = 0;
5038
4070 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
5039 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
4071
4072 /* Set the initial TX producer/consumer indices. */
4073 sc->tx_prod = 0;
4074 sc->tx_cons = 0;
4075 sc->tx_prod_bseq = 0;
4076 sc->used_tx_bd = 0;
4077 sc->max_tx_bd = USABLE_TX_BD;
4078 DBRUN(sc->tx_hi_watermark = USABLE_TX_BD);

--- 20 unchanged lines hidden (view full) ---

4099 j = 0;
4100 else
4101 j = i + 1;
4102
4103 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
4104 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
4105 }
4106
5040
5041 /* Set the initial TX producer/consumer indices. */
5042 sc->tx_prod = 0;
5043 sc->tx_cons = 0;
5044 sc->tx_prod_bseq = 0;
5045 sc->used_tx_bd = 0;
5046 sc->max_tx_bd = USABLE_TX_BD;
5047 DBRUN(sc->tx_hi_watermark = USABLE_TX_BD);

--- 20 unchanged lines hidden (view full) ---

5068 j = 0;
5069 else
5070 j = i + 1;
5071
5072 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5073 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5074 }
5075
4107 /* Initialize the context ID for an L2 TX chain. */
4108 val = BCE_L2CTX_TYPE_TYPE_L2;
4109 val |= BCE_L2CTX_TYPE_SIZE_L2;
4110 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TYPE, val);
5076 bce_init_tx_context(sc);
4111
5077
4112 val = BCE_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
4113 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_CMD_TYPE, val);
5078 DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
5079 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
4114
5080
4115 /* Point the hardware to the first page in the chain. */
4116 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
4117 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_HI, val);
4118 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
4119 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TBDR_BHADDR_LO, val);
4120
4121 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
4122
4123 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4124
4125 return(rc);
4126}
4127
4128
4129/****************************************************************************/
4130/* Free memory and clear the TX data structures. */
4131/* */
4132/* Returns: */
4133/* Nothing. */
4134/****************************************************************************/
4135static void
4136bce_free_tx_chain(struct bce_softc *sc)
4137{
4138 int i;
4139
5081 return(rc);
5082}
5083
5084
5085/****************************************************************************/
5086/* Free memory and clear the TX data structures. */
5087/* */
5088/* Returns: */
5089/* Nothing. */
5090/****************************************************************************/
5091static void
5092bce_free_tx_chain(struct bce_softc *sc)
5093{
5094 int i;
5095
4140 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
5096 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
4141
4142 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
4143 for (i = 0; i < TOTAL_TX_BD; i++) {
4144 if (sc->tx_mbuf_ptr[i] != NULL) {
4145 if (sc->tx_mbuf_map != NULL)
4146 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
4147 BUS_DMASYNC_POSTWRITE);
4148 m_freem(sc->tx_mbuf_ptr[i]);
4149 sc->tx_mbuf_ptr[i] = NULL;
4150 DBRUN(sc->debug_tx_mbuf_alloc--);
5097
5098 /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5099 for (i = 0; i < TOTAL_TX_BD; i++) {
5100 if (sc->tx_mbuf_ptr[i] != NULL) {
5101 if (sc->tx_mbuf_map != NULL)
5102 bus_dmamap_sync(sc->tx_mbuf_tag, sc->tx_mbuf_map[i],
5103 BUS_DMASYNC_POSTWRITE);
5104 m_freem(sc->tx_mbuf_ptr[i]);
5105 sc->tx_mbuf_ptr[i] = NULL;
5106 DBRUN(sc->debug_tx_mbuf_alloc--);
4151 }
5107 }
4152 }
4153
4154 /* Clear each TX chain page. */
4155 for (i = 0; i < TX_PAGES; i++)
4156 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
4157
4158 sc->used_tx_bd = 0;
4159
4160 /* Check if we lost any mbufs in the process. */
4161 DBRUNIF((sc->debug_tx_mbuf_alloc),
4162 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
4163 "from tx chain!\n",
4164 __FILE__, __LINE__, sc->debug_tx_mbuf_alloc));
4165
5108 }
5109
5110 /* Clear each TX chain page. */
5111 for (i = 0; i < TX_PAGES; i++)
5112 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5113
5114 sc->used_tx_bd = 0;
5115
5116 /* Check if we lost any mbufs in the process. */
5117 DBRUNIF((sc->debug_tx_mbuf_alloc),
5118 BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5119 "from tx chain!\n",
5120 __FILE__, __LINE__, sc->debug_tx_mbuf_alloc));
5121
4166 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
5122 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
4167}
4168
4169
4170/****************************************************************************/
5123}
5124
5125
5126/****************************************************************************/
5127/* Initialize the RX context memory. */
5128/* */
5129/* Returns: */
5130/* Nothing */
5131/****************************************************************************/
5132static void
5133bce_init_rx_context(struct bce_softc *sc)
5134{
5135 u32 val;
5136
5137 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5138
5139 /* Initialize the context ID for an L2 RX chain. */
5140 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5141 BCE_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
5142
5143 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5144 u32 lo_water, hi_water;
5145
5146 lo_water = BCE_L2CTX_LO_WATER_MARK_DEFAULT;
5147 hi_water = USABLE_RX_BD / 4;
5148
5149 lo_water /= BCE_L2CTX_LO_WATER_MARK_SCALE;
5150 hi_water /= BCE_L2CTX_HI_WATER_MARK_SCALE;
5151
5152 if (hi_water > 0xf)
5153 hi_water = 0xf;
5154 else if (hi_water == 0)
5155 lo_water = 0;
5156 val |= lo_water | (hi_water << BCE_L2CTX_HI_WATER_MARK_SHIFT);
5157 }
5158
5159 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
5160
5161 /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5162 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5163 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5164 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5165 }
5166
5167 /* Point the hardware to the first page in the chain. */
5168 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5169 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
5170 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5171 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
5172
5173 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5174}
5175
5176
5177/****************************************************************************/
4171/* Allocate memory and initialize the RX data structures. */
4172/* */
4173/* Returns: */
4174/* 0 for success, positive value for failure. */
4175/****************************************************************************/
4176static int
4177bce_init_rx_chain(struct bce_softc *sc)
4178{
4179 struct rx_bd *rxbd;
4180 int i, rc = 0;
5178/* Allocate memory and initialize the RX data structures. */
5179/* */
5180/* Returns: */
5181/* 0 for success, positive value for failure. */
5182/****************************************************************************/
5183static int
5184bce_init_rx_chain(struct bce_softc *sc)
5185{
5186 struct rx_bd *rxbd;
5187 int i, rc = 0;
4181 u32 val;
4182
5188
4183 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
5189 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5190 BCE_VERBOSE_CTX);
4184
4185 /* Initialize the RX producer and consumer indices. */
4186 sc->rx_prod = 0;
4187 sc->rx_cons = 0;
4188 sc->rx_prod_bseq = 0;
4189 sc->free_rx_bd = USABLE_RX_BD;
4190 sc->max_rx_bd = USABLE_RX_BD;
4191 DBRUN(sc->rx_low_watermark = sc->max_rx_bd);

--- 11 unchanged lines hidden (view full) ---

4203 else
4204 j = i + 1;
4205
4206 /* Setup the chain page pointers. */
4207 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
4208 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
4209 }
4210
5191
5192 /* Initialize the RX producer and consumer indices. */
5193 sc->rx_prod = 0;
5194 sc->rx_cons = 0;
5195 sc->rx_prod_bseq = 0;
5196 sc->free_rx_bd = USABLE_RX_BD;
5197 sc->max_rx_bd = USABLE_RX_BD;
5198 DBRUN(sc->rx_low_watermark = sc->max_rx_bd);

--- 11 unchanged lines hidden (view full) ---

5210 else
5211 j = i + 1;
5212
5213 /* Setup the chain page pointers. */
5214 rxbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5215 rxbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5216 }
5217
4211 /* Initialize the context ID for an L2 RX chain. */
4212 val = BCE_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE;
4213 val |= BCE_L2CTX_CTX_TYPE_SIZE_L2;
4214 val |= 0x02 << 8;
4215 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_CTX_TYPE, val);
4216
4217 /* Point the hardware to the first page in the chain. */
4218 val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
4219 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_HI, val);
4220 val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
4221 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_BDHADDR_LO, val);
4222
4223 /* Fill up the RX chain. */
5218/* Fill up the RX chain. */
4224 bce_fill_rx_chain(sc);
4225
4226 for (i = 0; i < RX_PAGES; i++) {
4227 bus_dmamap_sync(
4228 sc->rx_bd_chain_tag,
4229 sc->rx_bd_chain_map[i],
4230 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4231 }
4232
5219 bce_fill_rx_chain(sc);
5220
5221 for (i = 0; i < RX_PAGES; i++) {
5222 bus_dmamap_sync(
5223 sc->rx_bd_chain_tag,
5224 sc->rx_bd_chain_map[i],
5225 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5226 }
5227
4233 DBRUNMSG(BCE_VERBOSE_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
5228 bce_init_rx_context(sc);
4234
5229
4235 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4236
5230 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_chain(sc, 0, TOTAL_RX_BD));
5231 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5232 BCE_VERBOSE_CTX);
5233 /* ToDo: Are there possible failure modes here? */
4237 return(rc);
4238}
4239
4240
4241/****************************************************************************/
4242/* Add mbufs to the RX chain until its full or an mbuf allocation error */
4243/* occurs. */
4244/* */
4245/* Returns: */
4246/* Nothing */
4247/****************************************************************************/
4248static void
4249bce_fill_rx_chain(struct bce_softc *sc)
4250{
4251 u16 prod, prod_idx;
4252 u32 prod_bseq;
4253
5234 return(rc);
5235}
5236
5237
5238/****************************************************************************/
5239/* Add mbufs to the RX chain until its full or an mbuf allocation error */
5240/* occurs. */
5241/* */
5242/* Returns: */
5243/* Nothing */
5244/****************************************************************************/
5245static void
5246bce_fill_rx_chain(struct bce_softc *sc)
5247{
5248 u16 prod, prod_idx;
5249 u32 prod_bseq;
5250
4254 DBPRINT(sc, BCE_VERBOSE_RECV, "Entering %s()\n", __FUNCTION__);
5251 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5252 BCE_VERBOSE_CTX);
4255
5253
5254 /* Get the RX chain producer indices. */
4256 prod = sc->rx_prod;
4257 prod_bseq = sc->rx_prod_bseq;
4258
4259 /* Keep filling the RX chain until it's full. */
4260 while (sc->free_rx_bd > 0) {
4261 prod_idx = RX_CHAIN_IDX(prod);
4262 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
4263 /* Bail out if we can't add an mbuf to the chain. */
4264 break;
4265 }
4266 prod = NEXT_RX_BD(prod);
4267 }
4268
5255 prod = sc->rx_prod;
5256 prod_bseq = sc->rx_prod_bseq;
5257
5258 /* Keep filling the RX chain until it's full. */
5259 while (sc->free_rx_bd > 0) {
5260 prod_idx = RX_CHAIN_IDX(prod);
5261 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5262 /* Bail out if we can't add an mbuf to the chain. */
5263 break;
5264 }
5265 prod = NEXT_RX_BD(prod);
5266 }
5267
4269 /* Save the RX chain producer index. */
5268 /* Save the RX chain producer indices. */
4270 sc->rx_prod = prod;
4271 sc->rx_prod_bseq = prod_bseq;
4272
4273 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5269 sc->rx_prod = prod;
5270 sc->rx_prod_bseq = prod_bseq;
5271
5272 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
4274 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5273 BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
4275 __FUNCTION__, sc->rx_prod));
4276
5274 __FUNCTION__, sc->rx_prod));
5275
4277 /* Tell the chip about the waiting rx_bd's. */
4278 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BDIDX, sc->rx_prod);
4279 REG_WR(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_BSEQ, sc->rx_prod_bseq);
5276 /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5277 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_BDIDX,
5278 sc->rx_prod);
5279 REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_BSEQ,
5280 sc->rx_prod_bseq);
4280
5281
4281 DBPRINT(sc, BCE_VERBOSE_RECV, "Exiting %s()\n", __FUNCTION__);
5282 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5283 BCE_VERBOSE_CTX);
4282}
4283
4284
4285/****************************************************************************/
4286/* Free memory and clear the RX data structures. */
4287/* */
4288/* Returns: */
4289/* Nothing. */
4290/****************************************************************************/
4291static void
4292bce_free_rx_chain(struct bce_softc *sc)
4293{
4294 int i;
4295
5284}
5285
5286
5287/****************************************************************************/
5288/* Free memory and clear the RX data structures. */
5289/* */
5290/* Returns: */
5291/* Nothing. */
5292/****************************************************************************/
5293static void
5294bce_free_rx_chain(struct bce_softc *sc)
5295{
5296 int i;
5297
4296 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
5298 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
4297
5299
4298#ifdef BCE_USE_SPLIT_HEADER
4299 /* Clear the jumbo page chain support. */
4300 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, 0);
4301#endif
4302
4303 /* Free any mbufs still in the RX mbuf chain. */
4304 for (i = 0; i < TOTAL_RX_BD; i++) {
4305 if (sc->rx_mbuf_ptr[i] != NULL) {
4306 if (sc->rx_mbuf_map[i] != NULL)
4307 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
4308 BUS_DMASYNC_POSTREAD);
4309 m_freem(sc->rx_mbuf_ptr[i]);
4310 sc->rx_mbuf_ptr[i] = NULL;

--- 7 unchanged lines hidden (view full) ---

4318
4319 sc->free_rx_bd = sc->max_rx_bd;
4320
4321 /* Check if we lost any mbufs in the process. */
4322 DBRUNIF((sc->debug_rx_mbuf_alloc),
4323 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
4324 __FUNCTION__, sc->debug_rx_mbuf_alloc));
4325
5300 /* Free any mbufs still in the RX mbuf chain. */
5301 for (i = 0; i < TOTAL_RX_BD; i++) {
5302 if (sc->rx_mbuf_ptr[i] != NULL) {
5303 if (sc->rx_mbuf_map[i] != NULL)
5304 bus_dmamap_sync(sc->rx_mbuf_tag, sc->rx_mbuf_map[i],
5305 BUS_DMASYNC_POSTREAD);
5306 m_freem(sc->rx_mbuf_ptr[i]);
5307 sc->rx_mbuf_ptr[i] = NULL;

--- 7 unchanged lines hidden (view full) ---

5315
5316 sc->free_rx_bd = sc->max_rx_bd;
5317
5318 /* Check if we lost any mbufs in the process. */
5319 DBRUNIF((sc->debug_rx_mbuf_alloc),
5320 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5321 __FUNCTION__, sc->debug_rx_mbuf_alloc));
5322
4326 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
5323 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
4327}
4328
4329
4330#ifdef BCE_USE_SPLIT_HEADER
4331/****************************************************************************/
4332/* Allocate memory and initialize the page data structures. */
4333/* Assumes that bce_init_rx_chain() has not already been called. */
4334/* */
4335/* Returns: */
4336/* 0 for success, positive value for failure. */
4337/****************************************************************************/
4338static int
4339bce_init_pg_chain(struct bce_softc *sc)
4340{
4341 struct rx_bd *pgbd;
4342 int i, rc = 0;
4343 u32 val;
4344
5324}
5325
5326
5327#ifdef BCE_USE_SPLIT_HEADER
5328/****************************************************************************/
5329/* Allocate memory and initialize the page data structures. */
5330/* Assumes that bce_init_rx_chain() has not already been called. */
5331/* */
5332/* Returns: */
5333/* 0 for success, positive value for failure. */
5334/****************************************************************************/
5335static int
5336bce_init_pg_chain(struct bce_softc *sc)
5337{
5338 struct rx_bd *pgbd;
5339 int i, rc = 0;
5340 u32 val;
5341
4345 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
5342 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5343 BCE_VERBOSE_CTX);
4346
4347 /* Initialize the page producer and consumer indices. */
4348 sc->pg_prod = 0;
4349 sc->pg_cons = 0;
4350 sc->free_pg_bd = USABLE_PG_BD;
4351 sc->max_pg_bd = USABLE_PG_BD;
4352 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
4353 DBRUN(sc->pg_empty_count = 0);

--- 10 unchanged lines hidden (view full) ---

4364 else
4365 j = i + 1;
4366
4367 /* Setup the chain page pointers. */
4368 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
4369 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
4370 }
4371
5344
5345 /* Initialize the page producer and consumer indices. */
5346 sc->pg_prod = 0;
5347 sc->pg_cons = 0;
5348 sc->free_pg_bd = USABLE_PG_BD;
5349 sc->max_pg_bd = USABLE_PG_BD;
5350 DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5351 DBRUN(sc->pg_empty_count = 0);

--- 10 unchanged lines hidden (view full) ---

5362 else
5363 j = i + 1;
5364
5365 /* Setup the chain page pointers. */
5366 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5367 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5368 }
5369
4372 /* Point the hardware to the first page in the page chain. */
4373 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
4374 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_HI, val);
4375 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
4376 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_LO, val);
5370 /* Setup the MQ BIN mapping for host_pg_bidx. */
5371 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5372 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
4377
5373
5374 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, 0);
5375
4378 /* Configure the rx_bd and page chain mbuf cluster size. */
5376 /* Configure the rx_bd and page chain mbuf cluster size. */
4379#ifdef BCE_USE_SPLIT_HEADER
4380 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
5377 val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
4381#else
4382 val = (sc->rx_bd_mbuf_data_len << 16);
4383#endif
4384 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, val);
4385
4386 /* Configure the context reserved for jumbo support. */
4387 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RBDC_KEY,
4388 BCE_L2CTX_RBDC_JUMBO_KEY);
4389
5378 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_PG_BUF_SIZE, val);
5379
5380 /* Configure the context reserved for jumbo support. */
5381 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RBDC_KEY,
5382 BCE_L2CTX_RBDC_JUMBO_KEY);
5383
5384 /* Point the hardware to the first page in the page chain. */
5385 val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5386 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_HI, val);
5387 val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5388 CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_NX_PG_BDHADDR_LO, val);
5389
4390 /* Fill up the page chain. */
4391 bce_fill_pg_chain(sc);
4392
4393 for (i = 0; i < PG_PAGES; i++) {
4394 bus_dmamap_sync(
4395 sc->pg_bd_chain_tag,
4396 sc->pg_bd_chain_map[i],
4397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
4398 }
4399
5390 /* Fill up the page chain. */
5391 bce_fill_pg_chain(sc);
5392
5393 for (i = 0; i < PG_PAGES; i++) {
5394 bus_dmamap_sync(
5395 sc->pg_bd_chain_tag,
5396 sc->pg_bd_chain_map[i],
5397 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5398 }
5399
4400 DBRUNMSG(BCE_VERBOSE_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD));
4401 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4402
5400 DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD));
5401 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5402 BCE_VERBOSE_CTX);
4403 return(rc);
4404}
4405
5403 return(rc);
5404}
5405
5406
4406/****************************************************************************/
4407/* Add mbufs to the page chain until its full or an mbuf allocation error */
4408/* occurs. */
4409/* */
4410/* Returns: */
4411/* Nothing */
4412/****************************************************************************/
4413static void
4414bce_fill_pg_chain(struct bce_softc *sc)
4415{
4416 u16 prod, prod_idx;
4417
5407/****************************************************************************/
5408/* Add mbufs to the page chain until its full or an mbuf allocation error */
5409/* occurs. */
5410/* */
5411/* Returns: */
5412/* Nothing */
5413/****************************************************************************/
5414static void
5415bce_fill_pg_chain(struct bce_softc *sc)
5416{
5417 u16 prod, prod_idx;
5418
4418 DBPRINT(sc, BCE_EXCESSIVE_RECV, "Entering %s()\n", __FUNCTION__);
5419 DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5420 BCE_VERBOSE_CTX);
4419
5421
5422 /* Get the page chain prodcuer index. */
4420 prod = sc->pg_prod;
4421
4422 /* Keep filling the page chain until it's full. */
4423 while (sc->free_pg_bd > 0) {
4424 prod_idx = PG_CHAIN_IDX(prod);
4425 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
4426 /* Bail out if we can't add an mbuf to the chain. */
4427 break;
4428 }
4429 prod = NEXT_PG_BD(prod);
4430 }
4431
4432 /* Save the page chain producer index. */
4433 sc->pg_prod = prod;
4434
4435 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5423 prod = sc->pg_prod;
5424
5425 /* Keep filling the page chain until it's full. */
5426 while (sc->free_pg_bd > 0) {
5427 prod_idx = PG_CHAIN_IDX(prod);
5428 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
5429 /* Bail out if we can't add an mbuf to the chain. */
5430 break;
5431 }
5432 prod = NEXT_PG_BD(prod);
5433 }
5434
5435 /* Save the page chain producer index. */
5436 sc->pg_prod = prod;
5437
5438 DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
4436 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5439 BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
4437 __FUNCTION__, sc->pg_prod));
4438
5440 __FUNCTION__, sc->pg_prod));
5441
4439 /* Tell the chip about the new rx_bd's in the page chain. */
4440 REG_WR16(sc, MB_RX_CID_ADDR + BCE_L2CTX_HOST_PG_BDIDX, sc->pg_prod);
5442 /*
5443 * Write the mailbox and tell the chip about
5444 * the new rx_bd's in the page chain.
5445 */
5446 REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2CTX_HOST_PG_BDIDX,
5447 sc->pg_prod);
4441
5448
4442 DBPRINT(sc, BCE_EXCESSIVE_RECV, "Exiting %s()\n", __FUNCTION__);
5449 DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5450 BCE_VERBOSE_CTX);
4443}
4444
4445
4446/****************************************************************************/
4447/* Free memory and clear the RX data structures. */
4448/* */
4449/* Returns: */
4450/* Nothing. */
4451/****************************************************************************/
4452static void
4453bce_free_pg_chain(struct bce_softc *sc)
4454{
4455 int i;
4456
5451}
5452
5453
5454/****************************************************************************/
5455/* Free memory and clear the RX data structures. */
5456/* */
5457/* Returns: */
5458/* Nothing. */
5459/****************************************************************************/
5460static void
5461bce_free_pg_chain(struct bce_softc *sc)
5462{
5463 int i;
5464
4457 DBPRINT(sc, BCE_EXCESSIVE_RESET, "Entering %s()\n", __FUNCTION__);
5465 DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
4458
4459 /* Free any mbufs still in the mbuf page chain. */
4460 for (i = 0; i < TOTAL_PG_BD; i++) {
4461 if (sc->pg_mbuf_ptr[i] != NULL) {
4462 if (sc->pg_mbuf_map[i] != NULL)
4463 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i],
4464 BUS_DMASYNC_POSTREAD);
4465 m_freem(sc->pg_mbuf_ptr[i]);

--- 8 unchanged lines hidden (view full) ---

4474
4475 sc->free_pg_bd = sc->max_pg_bd;
4476
4477 /* Check if we lost any mbufs in the process. */
4478 DBRUNIF((sc->debug_pg_mbuf_alloc),
4479 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
4480 __FUNCTION__, sc->debug_pg_mbuf_alloc));
4481
5466
5467 /* Free any mbufs still in the mbuf page chain. */
5468 for (i = 0; i < TOTAL_PG_BD; i++) {
5469 if (sc->pg_mbuf_ptr[i] != NULL) {
5470 if (sc->pg_mbuf_map[i] != NULL)
5471 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i],
5472 BUS_DMASYNC_POSTREAD);
5473 m_freem(sc->pg_mbuf_ptr[i]);

--- 8 unchanged lines hidden (view full) ---

5482
5483 sc->free_pg_bd = sc->max_pg_bd;
5484
5485 /* Check if we lost any mbufs in the process. */
5486 DBRUNIF((sc->debug_pg_mbuf_alloc),
5487 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
5488 __FUNCTION__, sc->debug_pg_mbuf_alloc));
5489
4482 DBPRINT(sc, BCE_EXCESSIVE_RESET, "Exiting %s()\n", __FUNCTION__);
5490 DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
4483}
4484#endif /* BCE_USE_SPLIT_HEADER */
4485
4486
4487/****************************************************************************/
4488/* Set media options. */
4489/* */
4490/* Returns: */
4491/* 0 for success, positive value for failure. */
4492/****************************************************************************/
4493static int
4494bce_ifmedia_upd(struct ifnet *ifp)
4495{
5491}
5492#endif /* BCE_USE_SPLIT_HEADER */
5493
5494
5495/****************************************************************************/
5496/* Set media options. */
5497/* */
5498/* Returns: */
5499/* 0 for success, positive value for failure. */
5500/****************************************************************************/
5501static int
5502bce_ifmedia_upd(struct ifnet *ifp)
5503{
4496 struct bce_softc *sc;
5504 struct bce_softc *sc = ifp->if_softc;
4497
5505
4498 sc = ifp->if_softc;
5506 DBENTER(BCE_VERBOSE);
5507
4499 BCE_LOCK(sc);
4500 bce_ifmedia_upd_locked(ifp);
4501 BCE_UNLOCK(sc);
5508 BCE_LOCK(sc);
5509 bce_ifmedia_upd_locked(ifp);
5510 BCE_UNLOCK(sc);
5511
5512 DBEXIT(BCE_VERBOSE);
4502 return (0);
4503}
4504
4505
4506/****************************************************************************/
4507/* Set media options. */
4508/* */
4509/* Returns: */
4510/* Nothing. */
4511/****************************************************************************/
4512static void
4513bce_ifmedia_upd_locked(struct ifnet *ifp)
4514{
5513 return (0);
5514}
5515
5516
5517/****************************************************************************/
5518/* Set media options. */
5519/* */
5520/* Returns: */
5521/* Nothing. */
5522/****************************************************************************/
5523static void
5524bce_ifmedia_upd_locked(struct ifnet *ifp)
5525{
4515 struct bce_softc *sc;
5526 struct bce_softc *sc = ifp->if_softc;
4516 struct mii_data *mii;
5527 struct mii_data *mii;
4517 struct ifmedia *ifm;
4518
5528
4519 sc = ifp->if_softc;
4520 ifm = &sc->bce_ifmedia;
5529 DBENTER(BCE_VERBOSE);
5530
4521 BCE_LOCK_ASSERT(sc);
4522
4523 mii = device_get_softc(sc->bce_miibus);
4524
4525 /* Make sure the MII bus has been enumerated. */
4526 if (mii) {
4527 sc->bce_link = 0;
4528 if (mii->mii_instance) {
4529 struct mii_softc *miisc;
4530
4531 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
4532 mii_phy_reset(miisc);
4533 }
4534 mii_mediachg(mii);
4535 }
5531 BCE_LOCK_ASSERT(sc);
5532
5533 mii = device_get_softc(sc->bce_miibus);
5534
5535 /* Make sure the MII bus has been enumerated. */
5536 if (mii) {
5537 sc->bce_link = 0;
5538 if (mii->mii_instance) {
5539 struct mii_softc *miisc;
5540
5541 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5542 mii_phy_reset(miisc);
5543 }
5544 mii_mediachg(mii);
5545 }
5546
5547 DBEXIT(BCE_VERBOSE);
4536}
4537
4538
4539/****************************************************************************/
4540/* Reports current media status. */
4541/* */
4542/* Returns: */
4543/* Nothing. */
4544/****************************************************************************/
4545static void
4546bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
4547{
5548}
5549
5550
5551/****************************************************************************/
5552/* Reports current media status. */
5553/* */
5554/* Returns: */
5555/* Nothing. */
5556/****************************************************************************/
5557static void
5558bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5559{
4548 struct bce_softc *sc;
5560 struct bce_softc *sc = ifp->if_softc;
4549 struct mii_data *mii;
4550
5561 struct mii_data *mii;
5562
4551 sc = ifp->if_softc;
5563 DBENTER(BCE_VERBOSE);
4552
4553 BCE_LOCK(sc);
4554
4555 mii = device_get_softc(sc->bce_miibus);
4556
4557 mii_pollstat(mii);
4558 ifmr->ifm_active = mii->mii_media_active;
4559 ifmr->ifm_status = mii->mii_media_status;
4560
4561 BCE_UNLOCK(sc);
5564
5565 BCE_LOCK(sc);
5566
5567 mii = device_get_softc(sc->bce_miibus);
5568
5569 mii_pollstat(mii);
5570 ifmr->ifm_active = mii->mii_media_active;
5571 ifmr->ifm_status = mii->mii_media_status;
5572
5573 BCE_UNLOCK(sc);
5574
5575 DBEXIT(BCE_VERBOSE);
4562}
4563
4564
4565/****************************************************************************/
4566/* Handles PHY generated interrupt events. */
4567/* */
4568/* Returns: */
4569/* Nothing. */
4570/****************************************************************************/
4571static void
4572bce_phy_intr(struct bce_softc *sc)
4573{
4574 u32 new_link_state, old_link_state;
4575
5576}
5577
5578
5579/****************************************************************************/
5580/* Handles PHY generated interrupt events. */
5581/* */
5582/* Returns: */
5583/* Nothing. */
5584/****************************************************************************/
5585static void
5586bce_phy_intr(struct bce_softc *sc)
5587{
5588 u32 new_link_state, old_link_state;
5589
5590 DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5591
4576 new_link_state = sc->status_block->status_attn_bits &
4577 STATUS_ATTN_BITS_LINK_STATE;
4578 old_link_state = sc->status_block->status_attn_bits_ack &
4579 STATUS_ATTN_BITS_LINK_STATE;
4580
4581 /* Handle any changes if the link state has changed. */
4582 if (new_link_state != old_link_state) {
4583
5592 new_link_state = sc->status_block->status_attn_bits &
5593 STATUS_ATTN_BITS_LINK_STATE;
5594 old_link_state = sc->status_block->status_attn_bits_ack &
5595 STATUS_ATTN_BITS_LINK_STATE;
5596
5597 /* Handle any changes if the link state has changed. */
5598 if (new_link_state != old_link_state) {
5599
4584 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
4585
4586 sc->bce_link = 0;
4587 callout_stop(&sc->bce_tick_callout);
4588 bce_tick(sc);
4589
4590 /* Update the status_attn_bits_ack field in the status block. */
4591 if (new_link_state) {
4592 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
4593 STATUS_ATTN_BITS_LINK_STATE);
5600 /* Update the status_attn_bits_ack field in the status block. */
5601 if (new_link_state) {
5602 REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
5603 STATUS_ATTN_BITS_LINK_STATE);
4594 DBPRINT(sc, BCE_INFO_MISC, "Link is now UP.\n");
5604 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
5605 __FUNCTION__);
4595 }
4596 else {
4597 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
4598 STATUS_ATTN_BITS_LINK_STATE);
5606 }
5607 else {
5608 REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
5609 STATUS_ATTN_BITS_LINK_STATE);
4599 DBPRINT(sc, BCE_INFO_MISC, "Link is now DOWN.\n");
5610 DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
5611 __FUNCTION__);
4600 }
4601
5612 }
5613
5614 /*
5615 * Assume link is down and allow
5616 * tick routine to update the state
5617 * based on the actual media state.
5618 */
5619 sc->bce_link = 0;
5620 callout_stop(&sc->bce_tick_callout);
5621 bce_tick(sc);
4602 }
4603
4604 /* Acknowledge the link change interrupt. */
4605 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
5622 }
5623
5624 /* Acknowledge the link change interrupt. */
5625 REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
5626
5627 DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
4606}
4607
4608
4609/****************************************************************************/
4610/* Reads the receive consumer value from the status block (skipping over */
4611/* chain page pointer if necessary). */
4612/* */
4613/* Returns: */

--- 5 unchanged lines hidden (view full) ---

4619 u16 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4620
4621 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4622 hw_cons++;
4623
4624 return hw_cons;
4625}
4626
5628}
5629
5630
5631/****************************************************************************/
5632/* Reads the receive consumer value from the status block (skipping over */
5633/* chain page pointer if necessary). */
5634/* */
5635/* Returns: */

--- 5 unchanged lines hidden (view full) ---

5641 u16 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
5642
5643 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
5644 hw_cons++;
5645
5646 return hw_cons;
5647}
5648
4627
4628/****************************************************************************/
4629/* Handles received frame interrupt events. */
4630/* */
4631/* Returns: */
4632/* Nothing. */
4633/****************************************************************************/
4634static void
4635bce_rx_intr(struct bce_softc *sc)
4636{
4637 struct ifnet *ifp = sc->bce_ifp;
4638 struct l2_fhdr *l2fhdr;
4639 unsigned int pkt_len;
4640 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
4641 u32 status;
4642#ifdef BCE_USE_SPLIT_HEADER
5649/****************************************************************************/
5650/* Handles received frame interrupt events. */
5651/* */
5652/* Returns: */
5653/* Nothing. */
5654/****************************************************************************/
5655static void
5656bce_rx_intr(struct bce_softc *sc)
5657{
5658 struct ifnet *ifp = sc->bce_ifp;
5659 struct l2_fhdr *l2fhdr;
5660 unsigned int pkt_len;
5661 u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
5662 u32 status;
5663#ifdef BCE_USE_SPLIT_HEADER
4643 unsigned int pages, rem_len;
5664 unsigned int rem_len;
4644 u16 sw_pg_cons, sw_pg_cons_idx;
4645#endif
4646
5665 u16 sw_pg_cons, sw_pg_cons_idx;
5666#endif
5667
5668 DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
5669 DBRUN(sc->rx_interrupts++);
5670 DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
5671 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
5672 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4647
5673
4648#ifdef BCE_DEBUG
4649 u32 timer_start, timer_end;
4650 timer_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4651 sc->rx_interrupts++;
4652#endif
4653
4654 /* Prepare the RX chain pages to be accessed by the host CPU. */
4655 for (int i = 0; i < RX_PAGES; i++)
4656 bus_dmamap_sync(sc->rx_bd_chain_tag,
4657 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
4658
4659#ifdef BCE_USE_SPLIT_HEADER
4660 /* Prepare the page chain pages to be accessed by the host CPU. */
4661 for (int i = 0; i < PG_PAGES; i++)

--- 5 unchanged lines hidden (view full) ---

4667 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4668
4669 /* Get working copies of the driver's view of the consumer indices. */
4670 sw_rx_cons = sc->rx_cons;
4671#ifdef BCE_USE_SPLIT_HEADER
4672 sw_pg_cons = sc->pg_cons;
4673#endif
4674
5674 /* Prepare the RX chain pages to be accessed by the host CPU. */
5675 for (int i = 0; i < RX_PAGES; i++)
5676 bus_dmamap_sync(sc->rx_bd_chain_tag,
5677 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
5678
5679#ifdef BCE_USE_SPLIT_HEADER
5680 /* Prepare the page chain pages to be accessed by the host CPU. */
5681 for (int i = 0; i < PG_PAGES; i++)

--- 5 unchanged lines hidden (view full) ---

5687 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
5688
5689 /* Get working copies of the driver's view of the consumer indices. */
5690 sw_rx_cons = sc->rx_cons;
5691#ifdef BCE_USE_SPLIT_HEADER
5692 sw_pg_cons = sc->pg_cons;
5693#endif
5694
4675 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): rx_prod = 0x%04X, "
4676 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4677 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4678
4679 /* Update some debug statistics counters */
4680 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4681 sc->rx_low_watermark = sc->free_rx_bd);
4682 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4683
4684 /* Scan through the receive chain as long as there is work to do */
4685 /* ToDo: Consider setting a limit on the number of packets processed. */
4686 while (sw_rx_cons != hw_rx_cons) {
4687 struct mbuf *m0;
5695 /* Update some debug statistics counters */
5696 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5697 sc->rx_low_watermark = sc->free_rx_bd);
5698 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
5699
5700 /* Scan through the receive chain as long as there is work to do */
5701 /* ToDo: Consider setting a limit on the number of packets processed. */
5702 while (sw_rx_cons != hw_rx_cons) {
5703 struct mbuf *m0;
4688
5704
4689 /* Convert the producer/consumer indices to an actual rx_bd index. */
4690 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
4691
4692 /* Unmap the mbuf from DMA space. */
5705 /* Convert the producer/consumer indices to an actual rx_bd index. */
5706 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
5707
5708 /* Unmap the mbuf from DMA space. */
4693 bus_dmamap_sync(sc->rx_mbuf_tag,
5709 bus_dmamap_sync(sc->rx_mbuf_tag,
4694 sc->rx_mbuf_map[sw_rx_cons_idx],
4695 BUS_DMASYNC_POSTREAD);
4696 bus_dmamap_unload(sc->rx_mbuf_tag,
4697 sc->rx_mbuf_map[sw_rx_cons_idx]);
4698
4699 /* Remove the mbuf from the RX chain. */
4700 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
4701 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
4702 DBRUN(sc->debug_rx_mbuf_alloc--);
4703 sc->free_rx_bd++;
5710 sc->rx_mbuf_map[sw_rx_cons_idx],
5711 BUS_DMASYNC_POSTREAD);
5712 bus_dmamap_unload(sc->rx_mbuf_tag,
5713 sc->rx_mbuf_map[sw_rx_cons_idx]);
5714
5715 /* Remove the mbuf from the RX chain. */
5716 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
5717 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
5718 DBRUN(sc->debug_rx_mbuf_alloc--);
5719 sc->free_rx_bd++;
4704
5720
4705 /*
5721 /*
4706 * Frames received on the NetXteme II are prepended
5722 * Frames received on the NetXteme II are prepended
4707 * with an l2_fhdr structure which provides status
4708 * information about the received frame (including
4709 * VLAN tags and checksum info). The frames are also
4710 * automatically adjusted to align the IP header
5723 * with an l2_fhdr structure which provides status
5724 * information about the received frame (including
5725 * VLAN tags and checksum info). The frames are also
5726 * automatically adjusted to align the IP header
4711 * (i.e. two null bytes are inserted before the
5727 * (i.e. two null bytes are inserted before the
4712 * Ethernet header). As a result the data DMA'd by
4713 * the controller into the mbuf is as follows:
4714 * +---------+-----+---------------------+-----+
4715 * | l2_fhdr | pad | packet data | FCS |
4716 * +---------+-----+---------------------+-----+
4717 * The l2_fhdr needs to be checked and skipped and
5728 * Ethernet header). As a result the data DMA'd by
5729 * the controller into the mbuf is as follows:
5730 * +---------+-----+---------------------+-----+
5731 * | l2_fhdr | pad | packet data | FCS |
5732 * +---------+-----+---------------------+-----+
5733 * The l2_fhdr needs to be checked and skipped and
4718 * the FCS needs to be stripped before sending the
5734 * the FCS needs to be stripped before sending the
4719 * packet up the stack.
4720 */
4721 l2fhdr = mtod(m0, struct l2_fhdr *);
4722
4723 /* Get the packet data + FCS length and the status. */
4724 pkt_len = l2fhdr->l2_fhdr_pkt_len;
4725 status = l2fhdr->l2_fhdr_status;
4726
4727 /*
4728 * Skip over the l2_fhdr and pad, resulting in the
5735 * packet up the stack.
5736 */
5737 l2fhdr = mtod(m0, struct l2_fhdr *);
5738
5739 /* Get the packet data + FCS length and the status. */
5740 pkt_len = l2fhdr->l2_fhdr_pkt_len;
5741 status = l2fhdr->l2_fhdr_status;
5742
5743 /*
5744 * Skip over the l2_fhdr and pad, resulting in the
4729 * following data in the mbuf:
5745 * following data in the mbuf:
4730 * +---------------------+-----+
4731 * | packet data | FCS |
4732 * +---------------------+-----+
4733 */
4734 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
4735
5746 * +---------------------+-----+
5747 * | packet data | FCS |
5748 * +---------------------+-----+
5749 */
5750 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
5751
4736
4737#ifdef BCE_USE_SPLIT_HEADER
4738 /*
4739 * Check whether the received frame fits in a single
5752#ifdef BCE_USE_SPLIT_HEADER
5753 /*
5754 * Check whether the received frame fits in a single
4740 * mbuf or not (i.e. packet data + FCS <=
5755 * mbuf or not (i.e. packet data + FCS <=
4741 * sc->rx_bd_mbuf_data_len bytes).
4742 */
4743 if (pkt_len > m0->m_len) {
4744 /*
4745 * The received frame is larger than a single mbuf.
4746 * If the frame was a TCP frame then only the TCP
5756 * sc->rx_bd_mbuf_data_len bytes).
5757 */
5758 if (pkt_len > m0->m_len) {
5759 /*
5760 * The received frame is larger than a single mbuf.
5761 * If the frame was a TCP frame then only the TCP
4747 * header is placed in the mbuf, the remaining
5762 * header is placed in the mbuf, the remaining
4748 * payload (including FCS) is placed in the page
4749 * chain, the SPLIT flag is set, and the header
4750 * length is placed in the IP checksum field.
4751 * If the frame is not a TCP frame then the mbuf
5763 * payload (including FCS) is placed in the page
5764 * chain, the SPLIT flag is set, and the header
5765 * length is placed in the IP checksum field.
5766 * If the frame is not a TCP frame then the mbuf
4752 * is filled and the remaining bytes are placed
5767 * is filled and the remaining bytes are placed
4753 * in the page chain.
4754 */
4755
4756 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n",
4757 __FUNCTION__);
4758
5768 * in the page chain.
5769 */
5770
5771 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n",
5772 __FUNCTION__);
5773
5774 /*
5775 * When the page chain is enabled and the TCP
5776 * header has been split from the TCP payload,
5777 * the ip_xsum structure will reflect the length
5778 * of the TCP header, not the IP checksum. Set
5779 * the packet length of the mbuf accordingly.
5780 */
4759 if (status & L2_FHDR_STATUS_SPLIT)
4760 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
4761
4762 rem_len = pkt_len - m0->m_len;
4763
5781 if (status & L2_FHDR_STATUS_SPLIT)
5782 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
5783
5784 rem_len = pkt_len - m0->m_len;
5785
4764 /* Calculate how many pages to pull off the page chain. */
4765 /* ToDo: The following assumes that mbuf clusters are 2KB. */
4766 pages = (rem_len + sc->pg_bd_mbuf_alloc_size) >> 11;
4767
4768 /* Pull mbufs off the page chain for the remaining data. */
4769 while (rem_len > 0) {
4770 struct mbuf *m_pg;
5786 /* Pull mbufs off the page chain for the remaining data. */
5787 while (rem_len > 0) {
5788 struct mbuf *m_pg;
4771
5789
4772 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
4773
4774 /* Remove the mbuf from the page chain. */
4775 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
4776 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
4777 DBRUN(sc->debug_pg_mbuf_alloc--);
4778 sc->free_pg_bd++;
4779
4780 /* Unmap the page chain mbuf from DMA space. */
5790 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
5791
5792 /* Remove the mbuf from the page chain. */
5793 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
5794 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
5795 DBRUN(sc->debug_pg_mbuf_alloc--);
5796 sc->free_pg_bd++;
5797
5798 /* Unmap the page chain mbuf from DMA space. */
4781 bus_dmamap_sync(sc->pg_mbuf_tag,
5799 bus_dmamap_sync(sc->pg_mbuf_tag,
4782 sc->pg_mbuf_map[sw_pg_cons_idx],
4783 BUS_DMASYNC_POSTREAD);
4784 bus_dmamap_unload(sc->pg_mbuf_tag,
4785 sc->pg_mbuf_map[sw_pg_cons_idx]);
4786
4787 /* Adjust the mbuf length. */
4788 if (rem_len < m_pg->m_len) {
4789 /* The mbuf chain is complete. */

--- 29 unchanged lines hidden (view full) ---

4819 }
4820#endif
4821
4822 /* Remove the trailing Ethernet FCS. */
4823 m_adj(m0, -ETHER_CRC_LEN);
4824
4825 /* Check that the resulting mbuf chain is valid. */
4826 DBRUN(m_sanity(m0, FALSE));
5800 sc->pg_mbuf_map[sw_pg_cons_idx],
5801 BUS_DMASYNC_POSTREAD);
5802 bus_dmamap_unload(sc->pg_mbuf_tag,
5803 sc->pg_mbuf_map[sw_pg_cons_idx]);
5804
5805 /* Adjust the mbuf length. */
5806 if (rem_len < m_pg->m_len) {
5807 /* The mbuf chain is complete. */

--- 29 unchanged lines hidden (view full) ---

5837 }
5838#endif
5839
5840 /* Remove the trailing Ethernet FCS. */
5841 m_adj(m0, -ETHER_CRC_LEN);
5842
5843 /* Check that the resulting mbuf chain is valid. */
5844 DBRUN(m_sanity(m0, FALSE));
5845 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
5846 (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
5847 BCE_PRINTF("Invalid Ethernet frame size!\n");
5848 m_print(m0, 128));
4827
5849
4828 DBRUNIF((m0->m_len < ETHER_HDR_LEN),
4829 BCE_PRINTF("%s(): Unexpected length = %d!.\n",
4830 __FUNCTION__, m0->m_len);
4831 bce_breakpoint(sc));
4832
4833 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4834 BCE_PRINTF("Simulating l2_fhdr status error.\n");
4835 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4836
4837 /* Check the received frame for errors. */
5850 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
5851 BCE_PRINTF("Simulating l2_fhdr status error.\n");
5852 status = status | L2_FHDR_ERRORS_PHY_DECODE);
5853
5854 /* Check the received frame for errors. */
4838 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4839 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
5855 if (status & (L2_FHDR_ERRORS_BAD_CRC |
5856 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
4840 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
4841
4842 /* Log the error and release the mbuf. */
4843 ifp->if_ierrors++;
4844 DBRUN(sc->l2fhdr_status_errors++);
5857 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {
5858
5859 /* Log the error and release the mbuf. */
5860 ifp->if_ierrors++;
5861 DBRUN(sc->l2fhdr_status_errors++);
4845
5862
4846 m_freem(m0);
4847 m0 = NULL;
4848 goto bce_rx_int_next_rx;
4849 }
4850
4851 /* Send the packet to the appropriate interface. */
4852 m0->m_pkthdr.rcvif = ifp;
4853

--- 17 unchanged lines hidden (view full) ---

4871 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
4872 L2_FHDR_STATUS_UDP_DATAGRAM)) {
4873
4874 /* Check for a good TCP/UDP checksum. */
4875 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
4876 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
4877 m0->m_pkthdr.csum_data =
4878 l2fhdr->l2_fhdr_tcp_udp_xsum;
5863 m_freem(m0);
5864 m0 = NULL;
5865 goto bce_rx_int_next_rx;
5866 }
5867
5868 /* Send the packet to the appropriate interface. */
5869 m0->m_pkthdr.rcvif = ifp;
5870

--- 17 unchanged lines hidden (view full) ---

5888 if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
5889 L2_FHDR_STATUS_UDP_DATAGRAM)) {
5890
5891 /* Check for a good TCP/UDP checksum. */
5892 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
5893 L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
5894 m0->m_pkthdr.csum_data =
5895 l2fhdr->l2_fhdr_tcp_udp_xsum;
4879 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID
5896 m0->m_pkthdr.csum_flags |= (CSUM_DATA_VALID
4880 | CSUM_PSEUDO_HDR);
4881 }
4882 }
5897 | CSUM_PSEUDO_HDR);
5898 }
5899 }
4883 }
5900 }
4884
4885 /*
4886 * If we received a packet with a vlan tag,
4887 * attach that information to the packet.
4888 */
4889 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
4890#if __FreeBSD_version < 700000
4891 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue);
4892#else
4893 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag;
4894 m0->m_flags |= M_VLANTAG;
5901
5902 /*
5903 * If we received a packet with a vlan tag,
5904 * attach that information to the packet.
5905 */
5906 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
5907#if __FreeBSD_version < 700000
5908 VLAN_INPUT_TAG(ifp, m0, l2fhdr->l2_fhdr_vlan_tag, continue);
5909#else
5910 m0->m_pkthdr.ether_vtag = l2fhdr->l2_fhdr_vlan_tag;
5911 m0->m_flags |= M_VLANTAG;
4895#endif
5912#endif
4896 }
4897
4898 /* Pass the mbuf off to the upper layers. */
4899 ifp->if_ipackets++;
4900
4901bce_rx_int_next_rx:
4902 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
4903
4904 /* If we have a packet, pass it up the stack */
4905 if (m0) {
4906 /* Make sure we don't lose our place when we release the lock. */
4907 sc->rx_cons = sw_rx_cons;
4908#ifdef BCE_USE_SPLIT_HEADER
4909 sc->pg_cons = sw_pg_cons;
4910#endif
4911
4912 BCE_UNLOCK(sc);
4913 (*ifp->if_input)(ifp, m0);
4914 BCE_LOCK(sc);
5913 }
5914
5915 /* Pass the mbuf off to the upper layers. */
5916 ifp->if_ipackets++;
5917
5918bce_rx_int_next_rx:
5919 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
5920
5921 /* If we have a packet, pass it up the stack */
5922 if (m0) {
5923 /* Make sure we don't lose our place when we release the lock. */
5924 sc->rx_cons = sw_rx_cons;
5925#ifdef BCE_USE_SPLIT_HEADER
5926 sc->pg_cons = sw_pg_cons;
5927#endif
5928
5929 BCE_UNLOCK(sc);
5930 (*ifp->if_input)(ifp, m0);
5931 BCE_LOCK(sc);
4915
5932
4916 /* Recover our place. */
4917 sw_rx_cons = sc->rx_cons;
4918#ifdef BCE_USE_SPLIT_HEADER
4919 sw_pg_cons = sc->pg_cons;
4920#endif
4921 }
4922
4923 /* Refresh hw_cons to see if there's new work */

--- 15 unchanged lines hidden (view full) ---

4939 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4940
4941#ifdef BCE_USE_SPLIT_HEADER
4942 for (int i = 0; i < PG_PAGES; i++)
4943 bus_dmamap_sync(sc->pg_bd_chain_tag,
4944 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4945#endif
4946
5933 /* Recover our place. */
5934 sw_rx_cons = sc->rx_cons;
5935#ifdef BCE_USE_SPLIT_HEADER
5936 sw_pg_cons = sc->pg_cons;
5937#endif
5938 }
5939
5940 /* Refresh hw_cons to see if there's new work */

--- 15 unchanged lines hidden (view full) ---

5956 sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
5957
5958#ifdef BCE_USE_SPLIT_HEADER
5959 for (int i = 0; i < PG_PAGES; i++)
5960 bus_dmamap_sync(sc->pg_bd_chain_tag,
5961 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
5962#endif
5963
4947 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
5964 DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
4948 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4949 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
5965 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
5966 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4950
4951#ifdef BCE_DEBUG
4952 timer_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4953 sc->rx_intr_time += (u64) (timer_start > timer_end ?
4954 (timer_start - timer_end) : (~timer_start + timer_end + 1));
4955#endif
5967 DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
4956}
4957
4958
4959/****************************************************************************/
4960/* Reads the transmit consumer value from the status block (skipping over */
4961/* chain page pointer if necessary). */
4962/* */
4963/* Returns: */

--- 18 unchanged lines hidden (view full) ---

4982/* Nothing. */
4983/****************************************************************************/
4984static void
4985bce_tx_intr(struct bce_softc *sc)
4986{
4987 struct ifnet *ifp = sc->bce_ifp;
4988 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4989
5968}
5969
5970
5971/****************************************************************************/
5972/* Reads the transmit consumer value from the status block (skipping over */
5973/* chain page pointer if necessary). */
5974/* */
5975/* Returns: */

--- 18 unchanged lines hidden (view full) ---

5994/* Nothing. */
5995/****************************************************************************/
5996static void
5997bce_tx_intr(struct bce_softc *sc)
5998{
5999 struct ifnet *ifp = sc->bce_ifp;
6000 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6001
4990#ifdef BCE_DEBUG
4991 u32 timer_start, timer_end;
4992 timer_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4993 sc->tx_interrupts++;
4994#endif
6002 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6003 DBRUN(sc->tx_interrupts++);
6004 DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6005 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6006 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
4995
4996 BCE_LOCK_ASSERT(sc);
4997
4998 /* Get the hardware's view of the TX consumer index. */
4999 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
5000 sw_tx_cons = sc->tx_cons;
5001
5002 /* Prevent speculative reads from getting ahead of the status block. */
6007
6008 BCE_LOCK_ASSERT(sc);
6009
6010 /* Get the hardware's view of the TX consumer index. */
6011 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6012 sw_tx_cons = sc->tx_cons;
6013
6014 /* Prevent speculative reads from getting ahead of the status block. */
5003 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6015 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5004 BUS_SPACE_BARRIER_READ);
5005
5006 /* Cycle through any completed TX chain page entries. */
5007 while (sw_tx_cons != hw_tx_cons) {
5008#ifdef BCE_DEBUG
5009 struct tx_bd *txbd = NULL;
5010#endif
5011 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
5012
5013 DBPRINT(sc, BCE_INFO_SEND,
5014 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
5015 "sw_tx_chain_cons = 0x%04X\n",
5016 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
5017
5018 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
5019 BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6016 BUS_SPACE_BARRIER_READ);
6017
6018 /* Cycle through any completed TX chain page entries. */
6019 while (sw_tx_cons != hw_tx_cons) {
6020#ifdef BCE_DEBUG
6021 struct tx_bd *txbd = NULL;
6022#endif
6023 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6024
6025 DBPRINT(sc, BCE_INFO_SEND,
6026 "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6027 "sw_tx_chain_cons = 0x%04X\n",
6028 __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6029
6030 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
6031 BCE_PRINTF("%s(%d): TX chain consumer out of range! "
5020 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6032 " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
5021 (int) MAX_TX_BD);
5022 bce_breakpoint(sc));
5023
5024 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
5025 [TX_IDX(sw_tx_chain_cons)]);
6033 (int) MAX_TX_BD);
6034 bce_breakpoint(sc));
6035
6036 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6037 [TX_IDX(sw_tx_chain_cons)]);
5026
6038
5027 DBRUNIF((txbd == NULL),
6039 DBRUNIF((txbd == NULL),
5028 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6040 BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
5029 __FILE__, __LINE__, sw_tx_chain_cons);
5030 bce_breakpoint(sc));
5031
5032 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
5033 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
5034
5035 /*
5036 * Free the associated mbuf. Remember
5037 * that only the last tx_bd of a packet
5038 * has an mbuf pointer and DMA map.
5039 */
5040 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
5041
5042 /* Validate that this is the last tx_bd. */
5043 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
5044 BCE_PRINTF("%s(%d): tx_bd END flag not set but "
5045 "txmbuf == NULL!\n", __FILE__, __LINE__);
5046 bce_breakpoint(sc));
5047
6041 __FILE__, __LINE__, sw_tx_chain_cons);
6042 bce_breakpoint(sc));
6043
6044 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6045 bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6046
6047 /*
6048 * Free the associated mbuf. Remember
6049 * that only the last tx_bd of a packet
6050 * has an mbuf pointer and DMA map.
6051 */
6052 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6053
6054 /* Validate that this is the last tx_bd. */
6055 DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6056 BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6057 "txmbuf == NULL!\n", __FILE__, __LINE__);
6058 bce_breakpoint(sc));
6059
5048 DBRUNMSG(BCE_INFO_SEND,
6060 DBRUNMSG(BCE_INFO_SEND,
5049 BCE_PRINTF("%s(): Unloading map/freeing mbuf "
5050 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons));
5051
5052 /* Unmap the mbuf. */
5053 bus_dmamap_unload(sc->tx_mbuf_tag,
5054 sc->tx_mbuf_map[sw_tx_chain_cons]);
6061 BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6062 "from tx_bd[0x%04X]\n", __FUNCTION__, sw_tx_chain_cons));
6063
6064 /* Unmap the mbuf. */
6065 bus_dmamap_unload(sc->tx_mbuf_tag,
6066 sc->tx_mbuf_map[sw_tx_chain_cons]);
5055
6067
5056 /* Free the mbuf. */
5057 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
5058 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
5059 DBRUN(sc->debug_tx_mbuf_alloc--);
5060
5061 ifp->if_opackets++;
5062 }
5063
5064 sc->used_tx_bd--;
5065 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
5066
5067 /* Refresh hw_cons to see if there's new work. */
5068 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
5069
5070 /* Prevent speculative reads from getting ahead of the status block. */
6068 /* Free the mbuf. */
6069 m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6070 sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6071 DBRUN(sc->debug_tx_mbuf_alloc--);
6072
6073 ifp->if_opackets++;
6074 }
6075
6076 sc->used_tx_bd--;
6077 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6078
6079 /* Refresh hw_cons to see if there's new work. */
6080 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6081
6082 /* Prevent speculative reads from getting ahead of the status block. */
5071 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6083 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5072 BUS_SPACE_BARRIER_READ);
5073 }
5074
5075 /* Clear the TX timeout timer. */
5076 sc->watchdog_timer = 0;
5077
5078 /* Clear the tx hardware queue full flag. */
5079 if (sc->used_tx_bd < sc->max_tx_bd) {
5080 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6084 BUS_SPACE_BARRIER_READ);
6085 }
6086
6087 /* Clear the TX timeout timer. */
6088 sc->watchdog_timer = 0;
6089
6090 /* Clear the tx hardware queue full flag. */
6091 if (sc->used_tx_bd < sc->max_tx_bd) {
6092 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
5081 DBPRINT(sc, BCE_INFO_SEND,
5082 "%s(): Open TX chain! %d/%d (used/total)\n",
6093 DBPRINT(sc, BCE_INFO_SEND,
6094 "%s(): Open TX chain! %d/%d (used/total)\n",
5083 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
5084 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5085 }
5086
5087 sc->tx_cons = sw_tx_cons;
6095 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6096 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6097 }
6098
6099 sc->tx_cons = sw_tx_cons;
5088#ifdef BCE_DEBUG
5089 timer_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
5090 sc->tx_intr_time += (u64) (timer_start > timer_end ?
5091 (timer_start - timer_end) : (~timer_start + timer_end + 1));
5092#endif
6100
6101 DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6102 "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6103 __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6104 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
5093}
5094
5095
5096/****************************************************************************/
5097/* Disables interrupt generation. */
5098/* */
5099/* Returns: */
5100/* Nothing. */
5101/****************************************************************************/
5102static void
5103bce_disable_intr(struct bce_softc *sc)
5104{
6105}
6106
6107
6108/****************************************************************************/
6109/* Disables interrupt generation. */
6110/* */
6111/* Returns: */
6112/* Nothing. */
6113/****************************************************************************/
6114static void
6115bce_disable_intr(struct bce_softc *sc)
6116{
5105 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5106 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6117 DBENTER(BCE_VERBOSE_INTR);
6118
6119 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5107 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6120 REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6121
6122 DBEXIT(BCE_VERBOSE_INTR);
5108}
5109
5110
5111/****************************************************************************/
5112/* Enables interrupt generation. */
5113/* */
5114/* Returns: */
5115/* Nothing. */
5116/****************************************************************************/
5117static void
6123}
6124
6125
6126/****************************************************************************/
6127/* Enables interrupt generation. */
6128/* */
6129/* Returns: */
6130/* Nothing. */
6131/****************************************************************************/
6132static void
5118bce_enable_intr(struct bce_softc *sc)
6133bce_enable_intr(struct bce_softc *sc, int coal_now)
5119{
6134{
5120 u32 val;
6135 DBENTER(BCE_VERBOSE_INTR);
5121
5122 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5123 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
5124 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
5125
5126 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5127 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
5128
6136
6137 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6138 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
6139 BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6140
6141 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6142 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6143
5129 val = REG_RD(sc, BCE_HC_COMMAND);
5130 REG_WR(sc, BCE_HC_COMMAND, val | BCE_HC_COMMAND_COAL_NOW);
6144 /* Force an immediate interrupt (whether there is new data or not). */
6145 if (coal_now)
6146 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6147
6148 DBEXIT(BCE_VERBOSE_INTR);
5131}
5132
5133
5134/****************************************************************************/
5135/* Handles controller initialization. */
5136/* */
5137/* Returns: */
5138/* Nothing. */
5139/****************************************************************************/
5140static void
5141bce_init_locked(struct bce_softc *sc)
5142{
5143 struct ifnet *ifp;
5144 u32 ether_mtu = 0;
5145
6149}
6150
6151
6152/****************************************************************************/
6153/* Handles controller initialization. */
6154/* */
6155/* Returns: */
6156/* Nothing. */
6157/****************************************************************************/
6158static void
6159bce_init_locked(struct bce_softc *sc)
6160{
6161 struct ifnet *ifp;
6162 u32 ether_mtu = 0;
6163
5146 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
6164 DBENTER(BCE_VERBOSE_RESET);
5147
5148 BCE_LOCK_ASSERT(sc);
5149
5150 ifp = sc->bce_ifp;
5151
5152 /* Check if the driver is still running and bail out if it is. */
5153 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5154 goto bce_init_locked_exit;
5155
5156 bce_stop(sc);
5157
5158 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
6165
6166 BCE_LOCK_ASSERT(sc);
6167
6168 ifp = sc->bce_ifp;
6169
6170 /* Check if the driver is still running and bail out if it is. */
6171 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6172 goto bce_init_locked_exit;
6173
6174 bce_stop(sc);
6175
6176 if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
5159 BCE_PRINTF("%s(%d): Controller reset failed!\n",
6177 BCE_PRINTF("%s(%d): Controller reset failed!\n",
5160 __FILE__, __LINE__);
5161 goto bce_init_locked_exit;
5162 }
5163
5164 if (bce_chipinit(sc)) {
6178 __FILE__, __LINE__);
6179 goto bce_init_locked_exit;
6180 }
6181
6182 if (bce_chipinit(sc)) {
5165 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
6183 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
5166 __FILE__, __LINE__);
5167 goto bce_init_locked_exit;
5168 }
5169
5170 if (bce_blockinit(sc)) {
6184 __FILE__, __LINE__);
6185 goto bce_init_locked_exit;
6186 }
6187
6188 if (bce_blockinit(sc)) {
5171 BCE_PRINTF("%s(%d): Block initialization failed!\n",
6189 BCE_PRINTF("%s(%d): Block initialization failed!\n",
5172 __FILE__, __LINE__);
5173 goto bce_init_locked_exit;
5174 }
5175
5176 /* Load our MAC address. */
5177 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
5178 bce_set_mac_addr(sc);
5179

--- 8 unchanged lines hidden (view full) ---

5188 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
5189 ether_mtu = sc->rx_bd_mbuf_data_len;
5190#endif
5191 else
5192 ether_mtu = ifp->if_mtu;
5193
5194 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
5195
6190 __FILE__, __LINE__);
6191 goto bce_init_locked_exit;
6192 }
6193
6194 /* Load our MAC address. */
6195 bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6196 bce_set_mac_addr(sc);
6197

--- 8 unchanged lines hidden (view full) ---

6206 if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
6207 ether_mtu = sc->rx_bd_mbuf_data_len;
6208#endif
6209 else
6210 ether_mtu = ifp->if_mtu;
6211
6212 ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
6213
5196 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__,
6214 DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n", __FUNCTION__,
5197 ether_mtu);
5198
5199 /* Program the mtu, enabling jumbo frame support if necessary. */
5200 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
6215 ether_mtu);
6216
6217 /* Program the mtu, enabling jumbo frame support if necessary. */
6218 if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
5201 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
5202 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6219 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6220 min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
5203 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
5204 else
5205 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
5206
5207 DBPRINT(sc, BCE_INFO_LOAD,
5208 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
5209 "rx_bd_mbuf_align_pad = %d, pg_bd_mbuf_alloc_size = %d\n",
5210 __FUNCTION__, sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,

--- 4 unchanged lines hidden (view full) ---

5215
5216#ifdef BCE_USE_SPLIT_HEADER
5217 /* Init page buffer descriptor chain. */
5218 bce_init_pg_chain(sc);
5219#endif
5220
5221 /* Init RX buffer descriptor chain. */
5222 bce_init_rx_chain(sc);
6221 BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6222 else
6223 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6224
6225 DBPRINT(sc, BCE_INFO_LOAD,
6226 "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
6227 "rx_bd_mbuf_align_pad = %d, pg_bd_mbuf_alloc_size = %d\n",
6228 __FUNCTION__, sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,

--- 4 unchanged lines hidden (view full) ---

6233
6234#ifdef BCE_USE_SPLIT_HEADER
6235 /* Init page buffer descriptor chain. */
6236 bce_init_pg_chain(sc);
6237#endif
6238
6239 /* Init RX buffer descriptor chain. */
6240 bce_init_rx_chain(sc);
5223
6241
5224 /* Init TX buffer descriptor chain. */
5225 bce_init_tx_chain(sc);
5226
5227 /* Enable host interrupts. */
6242 /* Init TX buffer descriptor chain. */
6243 bce_init_tx_chain(sc);
6244
6245 /* Enable host interrupts. */
5228 bce_enable_intr(sc);
6246 bce_enable_intr(sc, 1);
5229
5230 bce_ifmedia_upd_locked(ifp);
5231
5232 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5233 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5234
5235 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
5236
5237bce_init_locked_exit:
6247
6248 bce_ifmedia_upd_locked(ifp);
6249
6250 ifp->if_drv_flags |= IFF_DRV_RUNNING;
6251 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6252
6253 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6254
6255bce_init_locked_exit:
5238 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
5239
5240 return;
6256 DBEXIT(BCE_VERBOSE_RESET);
5241}
5242
5243
5244/****************************************************************************/
5245/* Initialize the controller just enough so that any management firmware */
5246/* running on the device will continue to operate correctly. */
5247/* */
5248/* Returns: */
5249/* Nothing. */
5250/****************************************************************************/
5251static void
5252bce_mgmt_init_locked(struct bce_softc *sc)
5253{
5254 struct ifnet *ifp;
5255
6257}
6258
6259
6260/****************************************************************************/
6261/* Initialize the controller just enough so that any management firmware */
6262/* running on the device will continue to operate correctly. */
6263/* */
6264/* Returns: */
6265/* Nothing. */
6266/****************************************************************************/
6267static void
6268bce_mgmt_init_locked(struct bce_softc *sc)
6269{
6270 struct ifnet *ifp;
6271
5256 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
6272 DBENTER(BCE_VERBOSE_RESET);
5257
5258 BCE_LOCK_ASSERT(sc);
5259
5260 /* Bail out if management firmware is not running. */
5261 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
6273
6274 BCE_LOCK_ASSERT(sc);
6275
6276 /* Bail out if management firmware is not running. */
6277 if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
5262 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
6278 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
5263 "No management firmware running...\n");
5264 goto bce_mgmt_init_locked_exit;
5265 }
5266
5267 ifp = sc->bce_ifp;
5268
5269 /* Enable all critical blocks in the MAC. */
6279 "No management firmware running...\n");
6280 goto bce_mgmt_init_locked_exit;
6281 }
6282
6283 ifp = sc->bce_ifp;
6284
6285 /* Enable all critical blocks in the MAC. */
5270 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, 0x5ffffff);
6286 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
5271 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5272 DELAY(20);
5273
5274 bce_ifmedia_upd_locked(ifp);
6287 REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
6288 DELAY(20);
6289
6290 bce_ifmedia_upd_locked(ifp);
5275bce_mgmt_init_locked_exit:
5276 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
5277
6291
5278 return;
6292bce_mgmt_init_locked_exit:
6293 DBEXIT(BCE_VERBOSE_RESET);
5279}
5280
5281
5282/****************************************************************************/
5283/* Handles controller initialization when called from an unlocked routine. */
5284/* */
5285/* Returns: */
5286/* Nothing. */
5287/****************************************************************************/
5288static void
5289bce_init(void *xsc)
5290{
5291 struct bce_softc *sc = xsc;
5292
6294}
6295
6296
6297/****************************************************************************/
6298/* Handles controller initialization when called from an unlocked routine. */
6299/* */
6300/* Returns: */
6301/* Nothing. */
6302/****************************************************************************/
6303static void
6304bce_init(void *xsc)
6305{
6306 struct bce_softc *sc = xsc;
6307
6308 DBENTER(BCE_VERBOSE_RESET);
6309
5293 BCE_LOCK(sc);
5294 bce_init_locked(sc);
5295 BCE_UNLOCK(sc);
6310 BCE_LOCK(sc);
6311 bce_init_locked(sc);
6312 BCE_UNLOCK(sc);
6313
6314 DBEXIT(BCE_VERBOSE_RESET);
5296}
5297
5298
5299/****************************************************************************/
5300/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
5301/* memory visible to the controller. */
5302/* */
5303/* Returns: */

--- 10 unchanged lines hidden (view full) ---

5314 struct mbuf *m0;
5315 struct ether_vlan_header *eh;
5316 struct ip *ip;
5317 struct tcphdr *th;
5318 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0;
5319 u32 prod_bseq;
5320 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
5321
6315}
6316
6317
6318/****************************************************************************/
6319/* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
6320/* memory visible to the controller. */
6321/* */
6322/* Returns: */

--- 10 unchanged lines hidden (view full) ---

6333 struct mbuf *m0;
6334 struct ether_vlan_header *eh;
6335 struct ip *ip;
6336 struct tcphdr *th;
6337 u16 prod, chain_prod, etype, mss = 0, vlan_tag = 0, flags = 0;
6338 u32 prod_bseq;
6339 int hdr_len = 0, e_hlen = 0, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
6340
5322
5323#ifdef BCE_DEBUG
5324 u16 debug_prod;
5325#endif
5326 int i, error, nsegs, rc = 0;
5327
6341#ifdef BCE_DEBUG
6342 u16 debug_prod;
6343#endif
6344 int i, error, nsegs, rc = 0;
6345
6346 DBENTER(BCE_VERBOSE_SEND);
6347 DBPRINT(sc, BCE_INFO_SEND,
6348 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = %04X, "
6349 "tx_prod_bseq = 0x%08X\n",
6350 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod),
6351 sc->tx_prod_bseq);
6352
5328 /* Transfer any checksum offload flags to the bd. */
5329 m0 = *m_head;
5330 if (m0->m_pkthdr.csum_flags) {
5331 if (m0->m_pkthdr.csum_flags & CSUM_IP)
5332 flags |= TX_BD_FLAGS_IP_CKSUM;
5333 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
5334 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
5335 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {

--- 17 unchanged lines hidden (view full) ---

5353 ip = (struct ip *)(m0->m_data + e_hlen);
5354
5355 /* TSO only supported for TCP protocol */
5356 if (ip->ip_p != IPPROTO_TCP) {
5357 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
5358 __FILE__, __LINE__);
5359 goto bce_tx_encap_skip_tso;
5360 }
6353 /* Transfer any checksum offload flags to the bd. */
6354 m0 = *m_head;
6355 if (m0->m_pkthdr.csum_flags) {
6356 if (m0->m_pkthdr.csum_flags & CSUM_IP)
6357 flags |= TX_BD_FLAGS_IP_CKSUM;
6358 if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
6359 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6360 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {

--- 17 unchanged lines hidden (view full) ---

6378 ip = (struct ip *)(m0->m_data + e_hlen);
6379
6380 /* TSO only supported for TCP protocol */
6381 if (ip->ip_p != IPPROTO_TCP) {
6382 BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
6383 __FILE__, __LINE__);
6384 goto bce_tx_encap_skip_tso;
6385 }
5361
6386
5362 /* Get IP header length in bytes (min 20) */
5363 ip_hlen = ip->ip_hl << 2;
5364
5365 /* Get the TCP header length in bytes (min 20) */
5366 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
5367 tcp_hlen = (th->th_off << 2);
5368
5369 /* IP header length and checksum will be calc'd by hardware */

--- 8 unchanged lines hidden (view full) ---

5378 default:
5379 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
5380 __FILE__, __LINE__);
5381 goto bce_tx_encap_skip_tso;
5382 }
5383
5384 hdr_len = e_hlen + ip_hlen + tcp_hlen;
5385
6387 /* Get IP header length in bytes (min 20) */
6388 ip_hlen = ip->ip_hl << 2;
6389
6390 /* Get the TCP header length in bytes (min 20) */
6391 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
6392 tcp_hlen = (th->th_off << 2);
6393
6394 /* IP header length and checksum will be calc'd by hardware */

--- 8 unchanged lines hidden (view full) ---

6403 default:
6404 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
6405 __FILE__, __LINE__);
6406 goto bce_tx_encap_skip_tso;
6407 }
6408
6409 hdr_len = e_hlen + ip_hlen + tcp_hlen;
6410
5386 DBPRINT(sc, BCE_EXCESSIVE_SEND,
6411 DBPRINT(sc, BCE_EXTREME_SEND,
5387 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
5388 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len);
5389
5390 /* Set the LSO flag in the TX BD */
5391 flags |= TX_BD_FLAGS_SW_LSO;
5392 /* Set the length of IP + TCP options (in 32 bit words) */
5393 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8);
5394

--- 14 unchanged lines hidden (view full) ---

5409 map = sc->tx_mbuf_map[chain_prod];
5410
5411 /* Map the mbuf into our DMA address space. */
5412 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
5413 segs, &nsegs, BUS_DMA_NOWAIT);
5414
5415 /* Check if the DMA mapping was successful */
5416 if (error == EFBIG) {
6412 "%s(): hdr_len = %d, e_hlen = %d, ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
6413 __FUNCTION__, hdr_len, e_hlen, ip_hlen, tcp_hlen, ip_len);
6414
6415 /* Set the LSO flag in the TX BD */
6416 flags |= TX_BD_FLAGS_SW_LSO;
6417 /* Set the length of IP + TCP options (in 32 bit words) */
6418 flags |= (((ip_hlen + tcp_hlen - 40) >> 2) << 8);
6419

--- 14 unchanged lines hidden (view full) ---

6434 map = sc->tx_mbuf_map[chain_prod];
6435
6436 /* Map the mbuf into our DMA address space. */
6437 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6438 segs, &nsegs, BUS_DMA_NOWAIT);
6439
6440 /* Check if the DMA mapping was successful */
6441 if (error == EFBIG) {
5417
6442
5418 /* The mbuf is too fragmented for our DMA mapping. */
5419 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n",
5420 __FUNCTION__, nsegs);
5421 DBRUN(bce_dump_mbuf(sc, m0););
5422
5423 /* Try to defrag the mbuf. */
5424 m0 = m_defrag(*m_head, M_DONTWAIT);
5425 if (m0 == NULL) {
5426 /* Defrag was unsuccessful */
5427 m_freem(*m_head);
5428 *m_head = NULL;
5429 sc->mbuf_alloc_failed++;
6443 /* The mbuf is too fragmented for our DMA mapping. */
6444 DBPRINT(sc, BCE_WARN, "%s(): fragmented mbuf (%d pieces)\n",
6445 __FUNCTION__, nsegs);
6446 DBRUN(bce_dump_mbuf(sc, m0););
6447
6448 /* Try to defrag the mbuf. */
6449 m0 = m_defrag(*m_head, M_DONTWAIT);
6450 if (m0 == NULL) {
6451 /* Defrag was unsuccessful */
6452 m_freem(*m_head);
6453 *m_head = NULL;
6454 sc->mbuf_alloc_failed++;
5430 return (ENOBUFS);
6455 rc = ENOBUFS;
6456 goto bce_tx_encap_exit;
5431 }
5432
5433 /* Defrag was successful, try mapping again */
5434 *m_head = m0;
5435 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
5436 segs, &nsegs, BUS_DMA_NOWAIT);
5437
5438 /* Still getting an error after a defrag. */
5439 if (error == ENOMEM) {
5440 /* Insufficient DMA buffers available. */
5441 sc->tx_dma_map_failures++;
6457 }
6458
6459 /* Defrag was successful, try mapping again */
6460 *m_head = m0;
6461 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6462 segs, &nsegs, BUS_DMA_NOWAIT);
6463
6464 /* Still getting an error after a defrag. */
6465 if (error == ENOMEM) {
6466 /* Insufficient DMA buffers available. */
6467 sc->tx_dma_map_failures++;
5442 return (error);
6468 rc = error;
6469 goto bce_tx_encap_exit;
5443 } else if (error != 0) {
5444 /* Still can't map the mbuf, release it and return an error. */
5445 BCE_PRINTF(
5446 "%s(%d): Unknown error mapping mbuf into TX chain!\n",
5447 __FILE__, __LINE__);
5448 m_freem(m0);
5449 *m_head = NULL;
5450 sc->tx_dma_map_failures++;
6470 } else if (error != 0) {
6471 /* Still can't map the mbuf, release it and return an error. */
6472 BCE_PRINTF(
6473 "%s(%d): Unknown error mapping mbuf into TX chain!\n",
6474 __FILE__, __LINE__);
6475 m_freem(m0);
6476 *m_head = NULL;
6477 sc->tx_dma_map_failures++;
5451 return (ENOBUFS);
6478 rc = ENOBUFS;
6479 goto bce_tx_encap_exit;
5452 }
5453 } else if (error == ENOMEM) {
5454 /* Insufficient DMA buffers available. */
5455 sc->tx_dma_map_failures++;
6480 }
6481 } else if (error == ENOMEM) {
6482 /* Insufficient DMA buffers available. */
6483 sc->tx_dma_map_failures++;
5456 return (error);
6484 rc = error;
6485 goto bce_tx_encap_exit;
5457 } else if (error != 0) {
5458 m_freem(m0);
5459 *m_head = NULL;
5460 sc->tx_dma_map_failures++;
6486 } else if (error != 0) {
6487 m_freem(m0);
6488 *m_head = NULL;
6489 sc->tx_dma_map_failures++;
5461 return (error);
6490 rc = error;
6491 goto bce_tx_encap_exit;
5462 }
5463
5464 /* Make sure there's room in the chain */
5465 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
5466 bus_dmamap_unload(sc->tx_mbuf_tag, map);
6492 }
6493
6494 /* Make sure there's room in the chain */
6495 if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6496 bus_dmamap_unload(sc->tx_mbuf_tag, map);
5467 return (ENOBUFS);
6497 rc = ENOBUFS;
6498 goto bce_tx_encap_exit;
5468 }
5469
5470 /* prod points to an empty tx_bd at this point. */
5471 prod_bseq = sc->tx_prod_bseq;
5472
5473#ifdef BCE_DEBUG
5474 debug_prod = chain_prod;
5475#endif

--- 23 unchanged lines hidden (view full) ---

5499 if (i == 0)
5500 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
5501 prod = NEXT_TX_BD(prod);
5502 }
5503
5504 /* Set the END flag on the last TX buffer descriptor. */
5505 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5506
6499 }
6500
6501 /* prod points to an empty tx_bd at this point. */
6502 prod_bseq = sc->tx_prod_bseq;
6503
6504#ifdef BCE_DEBUG
6505 debug_prod = chain_prod;
6506#endif

--- 23 unchanged lines hidden (view full) ---

6530 if (i == 0)
6531 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
6532 prod = NEXT_TX_BD(prod);
6533 }
6534
6535 /* Set the END flag on the last TX buffer descriptor. */
6536 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
6537
5507 DBRUNMSG(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs));
6538 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs));
5508
5509 DBPRINT(sc, BCE_INFO_SEND,
5510 "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, "
5511 "prod_bseq = 0x%08X\n",
5512 __FUNCTION__, prod, chain_prod, prod_bseq);
5513
5514 /*
5515 * Ensure that the mbuf pointer for this transmission
5516 * is placed at the array index of the last
5517 * descriptor in this chain. This is done
6539
6540 DBPRINT(sc, BCE_INFO_SEND,
6541 "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, "
6542 "prod_bseq = 0x%08X\n",
6543 __FUNCTION__, prod, chain_prod, prod_bseq);
6544
6545 /*
6546 * Ensure that the mbuf pointer for this transmission
6547 * is placed at the array index of the last
6548 * descriptor in this chain. This is done
5518 * because a single map is used for all
6549 * because a single map is used for all
5519 * segments of the mbuf and we don't want to
5520 * unload the map before all of the segments
5521 * have been freed.
5522 */
5523 sc->tx_mbuf_ptr[chain_prod] = m0;
5524 sc->used_tx_bd += nsegs;
5525
5526 /* Update some debug statistic counters */
6550 * segments of the mbuf and we don't want to
6551 * unload the map before all of the segments
6552 * have been freed.
6553 */
6554 sc->tx_mbuf_ptr[chain_prod] = m0;
6555 sc->used_tx_bd += nsegs;
6556
6557 /* Update some debug statistic counters */
5527 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
6558 DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
5528 sc->tx_hi_watermark = sc->used_tx_bd);
5529 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
5530 DBRUNIF(sc->debug_tx_mbuf_alloc++);
5531
6559 sc->tx_hi_watermark = sc->used_tx_bd);
6560 DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
6561 DBRUNIF(sc->debug_tx_mbuf_alloc++);
6562
5532 DBRUNMSG(BCE_EXCESSIVE_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
6563 DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
5533
5534 /* prod points to the next free tx_bd at this point. */
5535 sc->tx_prod = prod;
5536 sc->tx_prod_bseq = prod_bseq;
5537
6564
6565 /* prod points to the next free tx_bd at this point. */
6566 sc->tx_prod = prod;
6567 sc->tx_prod_bseq = prod_bseq;
6568
6569 DBPRINT(sc, BCE_INFO_SEND,
6570 "%s(exit): prod = 0x%04X, chain_prod = %04X, "
6571 "prod_bseq = 0x%08X\n",
6572 __FUNCTION__, sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod),
6573 sc->tx_prod_bseq);
6574
6575bce_tx_encap_exit:
6576 DBEXIT(BCE_VERBOSE_SEND);
5538 return(rc);
5539}
5540
5541
5542/****************************************************************************/
5543/* Main transmit routine when called from another routine with a lock. */
5544/* */
5545/* Returns: */
5546/* Nothing. */
5547/****************************************************************************/
5548static void
5549bce_start_locked(struct ifnet *ifp)
5550{
5551 struct bce_softc *sc = ifp->if_softc;
5552 struct mbuf *m_head = NULL;
5553 int count = 0;
5554 u16 tx_prod, tx_chain_prod;
5555
6577 return(rc);
6578}
6579
6580
6581/****************************************************************************/
6582/* Main transmit routine when called from another routine with a lock. */
6583/* */
6584/* Returns: */
6585/* Nothing. */
6586/****************************************************************************/
6587static void
6588bce_start_locked(struct ifnet *ifp)
6589{
6590 struct bce_softc *sc = ifp->if_softc;
6591 struct mbuf *m_head = NULL;
6592 int count = 0;
6593 u16 tx_prod, tx_chain_prod;
6594
6595 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
6596
6597 BCE_LOCK_ASSERT(sc);
6598
5556 /* prod points to the next free tx_bd. */
5557 tx_prod = sc->tx_prod;
5558 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
5559
5560 DBPRINT(sc, BCE_INFO_SEND,
5561 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
5562 "tx_prod_bseq = 0x%08X\n",
5563 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
5564
5565 /* If there's no link or the transmit queue is empty then just exit. */
5566 if (!sc->bce_link) {
6599 /* prod points to the next free tx_bd. */
6600 tx_prod = sc->tx_prod;
6601 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
6602
6603 DBPRINT(sc, BCE_INFO_SEND,
6604 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
6605 "tx_prod_bseq = 0x%08X\n",
6606 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
6607
6608 /* If there's no link or the transmit queue is empty then just exit. */
6609 if (!sc->bce_link) {
5567 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
6610 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
5568 __FUNCTION__);
5569 goto bce_start_locked_exit;
5570 }
5571
5572 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
6611 __FUNCTION__);
6612 goto bce_start_locked_exit;
6613 }
6614
6615 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5573 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
6616 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
5574 __FUNCTION__);
5575 goto bce_start_locked_exit;
5576 }
5577
5578 /*
5579 * Keep adding entries while there is space in the ring.
5580 */
5581 while (sc->used_tx_bd < sc->max_tx_bd) {
5582
5583 /* Check for any frames to send. */
5584 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
6617 __FUNCTION__);
6618 goto bce_start_locked_exit;
6619 }
6620
6621 /*
6622 * Keep adding entries while there is space in the ring.
6623 */
6624 while (sc->used_tx_bd < sc->max_tx_bd) {
6625
6626 /* Check for any frames to send. */
6627 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
6628
6629 /* Stop when the transmit queue is empty. */
5585 if (m_head == NULL)
5586 break;
5587
5588 /*
5589 * Pack the data into the transmit ring. If we
5590 * don't have room, place the mbuf back at the
5591 * head of the queue and set the OACTIVE flag
5592 * to wait for the NIC to drain the chain.
5593 */
5594 if (bce_tx_encap(sc, &m_head)) {
6630 if (m_head == NULL)
6631 break;
6632
6633 /*
6634 * Pack the data into the transmit ring. If we
6635 * don't have room, place the mbuf back at the
6636 * head of the queue and set the OACTIVE flag
6637 * to wait for the NIC to drain the chain.
6638 */
6639 if (bce_tx_encap(sc, &m_head)) {
6640 /* No room, put the frame back on the transmit queue. */
5595 if (m_head != NULL)
5596 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
5597 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
5598 DBPRINT(sc, BCE_INFO_SEND,
6641 if (m_head != NULL)
6642 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
6643 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
6644 DBPRINT(sc, BCE_INFO_SEND,
5599 "TX chain is closed for business! Total tx_bd used = %d\n",
6645 "TX chain is closed for business! Total tx_bd used = %d\n",
5600 sc->used_tx_bd);
5601 break;
5602 }
5603
5604 count++;
5605
5606 /* Send a copy of the frame to any BPF listeners. */
5607 ETHER_BPF_MTAP(ifp, m_head);
5608 }
5609
6646 sc->used_tx_bd);
6647 break;
6648 }
6649
6650 count++;
6651
6652 /* Send a copy of the frame to any BPF listeners. */
6653 ETHER_BPF_MTAP(ifp, m_head);
6654 }
6655
6656 /* Exit if no packets were dequeued. */
5610 if (count == 0) {
6657 if (count == 0) {
5611 /* no packets were dequeued */
5612 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n",
6658 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n",
5613 __FUNCTION__);
5614 goto bce_start_locked_exit;
5615 }
5616
6659 __FUNCTION__);
6660 goto bce_start_locked_exit;
6661 }
6662
5617 /* Update the driver's counters. */
5618 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod);
6663 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into send queue.\n",
6664 __FUNCTION__, count);
5619
6665
5620 /* Start the transmit. */
5621 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5622 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
6666 REG_WR(sc, BCE_MQ_COMMAND, REG_RD(sc, BCE_MQ_COMMAND) | BCE_MQ_COMMAND_NO_MAP_ERROR);
5623
6667
6668 /* Write the mailbox and tell the chip about the waiting tx_bd's. */
6669 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; "
6670 "BCE_L2CTX_TX_HOST_BIDX = 0x%08X, sc->tx_prod = 0x%04X\n",
6671 __FUNCTION__,
6672 MB_GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
6673 REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
6674 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): MB_GET_CID_ADDR(TX_CID) = 0x%08X; "
6675 "BCE_L2CTX_TX_HOST_BSEQ = 0x%08X, sc->tx_prod_bseq = 0x%04X\n",
6676 __FUNCTION__,
6677 MB_GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
6678 REG_WR(sc, MB_GET_CID_ADDR(TX_CID) + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
6679
5624 /* Set the tx timeout. */
5625 sc->watchdog_timer = BCE_TX_TIMEOUT;
5626
6680 /* Set the tx timeout. */
6681 sc->watchdog_timer = BCE_TX_TIMEOUT;
6682
5627bce_start_locked_exit:
5628 DBPRINT(sc, BCE_INFO_SEND,
5629 "%s(exit ): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
5630 "tx_prod_bseq = 0x%08X\n",
5631 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
6683 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
6684 DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
5632
6685
6686bce_start_locked_exit:
6687 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5633 return;
5634}
5635
5636
5637/****************************************************************************/
5638/* Main transmit routine when called from another routine without a lock. */
5639/* */
5640/* Returns: */
5641/* Nothing. */
5642/****************************************************************************/
5643static void
5644bce_start(struct ifnet *ifp)
5645{
5646 struct bce_softc *sc = ifp->if_softc;
5647
6688 return;
6689}
6690
6691
6692/****************************************************************************/
6693/* Main transmit routine when called from another routine without a lock. */
6694/* */
6695/* Returns: */
6696/* Nothing. */
6697/****************************************************************************/
6698static void
6699bce_start(struct ifnet *ifp)
6700{
6701 struct bce_softc *sc = ifp->if_softc;
6702
6703 DBENTER(BCE_VERBOSE_SEND);
6704
5648 BCE_LOCK(sc);
5649 bce_start_locked(ifp);
5650 BCE_UNLOCK(sc);
6705 BCE_LOCK(sc);
6706 bce_start_locked(ifp);
6707 BCE_UNLOCK(sc);
6708
6709 DBEXIT(BCE_VERBOSE_SEND);
5651}
5652
5653
5654/****************************************************************************/
5655/* Handles any IOCTL calls from the operating system. */
5656/* */
5657/* Returns: */
5658/* 0 for success, positive value for failure. */
5659/****************************************************************************/
5660static int
5661bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
5662{
5663 struct bce_softc *sc = ifp->if_softc;
5664 struct ifreq *ifr = (struct ifreq *) data;
5665 struct mii_data *mii;
5666 int mask, error = 0;
5667
6710}
6711
6712
6713/****************************************************************************/
6714/* Handles any IOCTL calls from the operating system. */
6715/* */
6716/* Returns: */
6717/* 0 for success, positive value for failure. */
6718/****************************************************************************/
6719static int
6720bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
6721{
6722 struct bce_softc *sc = ifp->if_softc;
6723 struct ifreq *ifr = (struct ifreq *) data;
6724 struct mii_data *mii;
6725 int mask, error = 0;
6726
6727 DBENTER(BCE_VERBOSE_MISC);
6728
5668 switch(command) {
5669
5670 /* Set the interface MTU. */
5671 case SIOCSIFMTU:
5672 /* Check that the MTU setting is supported. */
6729 switch(command) {
6730
6731 /* Set the interface MTU. */
6732 case SIOCSIFMTU:
6733 /* Check that the MTU setting is supported. */
5673 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
6734 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
5674 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
5675 error = EINVAL;
5676 break;
5677 }
5678
5679 DBPRINT(sc, BCE_INFO_MISC,
6735 (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
6736 error = EINVAL;
6737 break;
6738 }
6739
6740 DBPRINT(sc, BCE_INFO_MISC,
5680 "SIOCSIFMTU: Changing MTU from %d to %d\n",
6741 "SIOCSIFMTU: Changing MTU from %d to %d\n",
5681 (int) ifp->if_mtu, (int) ifr->ifr_mtu);
5682
5683 BCE_LOCK(sc);
5684 ifp->if_mtu = ifr->ifr_mtu;
5685 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5686#ifdef BCE_USE_SPLIT_HEADER
5687 /* No buffer allocation size changes are necessary. */
5688#else

--- 73 unchanged lines hidden (view full) ---

5762 &mii->mii_media, command);
5763 break;
5764
5765 /* Set interface capability */
5766 case SIOCSIFCAP:
5767 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5768 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
5769
6742 (int) ifp->if_mtu, (int) ifr->ifr_mtu);
6743
6744 BCE_LOCK(sc);
6745 ifp->if_mtu = ifr->ifr_mtu;
6746 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
6747#ifdef BCE_USE_SPLIT_HEADER
6748 /* No buffer allocation size changes are necessary. */
6749#else

--- 73 unchanged lines hidden (view full) ---

6823 &mii->mii_media, command);
6824 break;
6825
6826 /* Set interface capability */
6827 case SIOCSIFCAP:
6828 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
6829 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
6830
5770 /* Toggle the TX checksum capabilites enable flag. */
6831 /* Toggle the TX checksum capabilites enable flag. */
5771 if (mask & IFCAP_TXCSUM) {
5772 ifp->if_capenable ^= IFCAP_TXCSUM;
5773 if (IFCAP_TXCSUM & ifp->if_capenable)
5774 ifp->if_hwassist = BCE_IF_HWASSIST;
5775 else
5776 ifp->if_hwassist = 0;
5777 }
5778

--- 34 unchanged lines hidden (view full) ---

5813
5814 break;
5815 default:
5816 /* We don't know how to handle the IOCTL, pass it on. */
5817 error = ether_ioctl(ifp, command, data);
5818 break;
5819 }
5820
6832 if (mask & IFCAP_TXCSUM) {
6833 ifp->if_capenable ^= IFCAP_TXCSUM;
6834 if (IFCAP_TXCSUM & ifp->if_capenable)
6835 ifp->if_hwassist = BCE_IF_HWASSIST;
6836 else
6837 ifp->if_hwassist = 0;
6838 }
6839

--- 34 unchanged lines hidden (view full) ---

6874
6875 break;
6876 default:
6877 /* We don't know how to handle the IOCTL, pass it on. */
6878 error = ether_ioctl(ifp, command, data);
6879 break;
6880 }
6881
6882 DBEXIT(BCE_VERBOSE_MISC);
5821 return(error);
5822}
5823
5824
5825/****************************************************************************/
5826/* Transmit timeout handler. */
5827/* */
5828/* Returns: */
5829/* Nothing. */
5830/****************************************************************************/
5831static void
5832bce_watchdog(struct bce_softc *sc)
5833{
6883 return(error);
6884}
6885
6886
6887/****************************************************************************/
6888/* Transmit timeout handler. */
6889/* */
6890/* Returns: */
6891/* Nothing. */
6892/****************************************************************************/
6893static void
6894bce_watchdog(struct bce_softc *sc)
6895{
6896 DBENTER(BCE_EXTREME_SEND);
5834
5835 BCE_LOCK_ASSERT(sc);
5836
6897
6898 BCE_LOCK_ASSERT(sc);
6899
6900 /* If the watchdog timer hasn't expired then just exit. */
5837 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
6901 if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
5838 return;
6902 goto bce_watchdog_exit;
5839
6903
5840 /*
5841 * If we are in this routine because of pause frames, then
5842 * don't reset the hardware.
5843 */
5844 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
5845 return;
6904 /* If pause frames are active then don't reset the hardware. */
6905 /* ToDo: Should we reset the timer here? */
6906 if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
6907 goto bce_watchdog_exit;
5846
6908
5847 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
6909 BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
5848 __FILE__, __LINE__);
5849
6910 __FILE__, __LINE__);
6911
5850 DBRUNMSG(BCE_VERBOSE_SEND,
6912 DBRUNMSG(BCE_INFO,
5851 bce_dump_driver_state(sc);
6913 bce_dump_driver_state(sc);
5852 bce_dump_status_block(sc));
6914 bce_dump_status_block(sc);
6915 bce_dump_stats_block(sc);
6916 bce_dump_ftqs(sc);
6917 bce_dump_txp_state(sc, 0);
6918 bce_dump_rxp_state(sc, 0);
6919 bce_dump_tpat_state(sc, 0);
6920 bce_dump_cp_state(sc, 0);
6921 bce_dump_com_state(sc, 0));
5853
6922
5854 /* DBRUN(BCE_FATAL, bce_breakpoint(sc)); */
6923 DBRUN(bce_breakpoint(sc));
5855
5856 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5857
5858 bce_init_locked(sc);
5859 sc->bce_ifp->if_oerrors++;
5860
6924
6925 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
6926
6927 bce_init_locked(sc);
6928 sc->bce_ifp->if_oerrors++;
6929
6930bce_watchdog_exit:
6931 DBEXIT(BCE_EXTREME_SEND);
5861}
5862
5863
5864/*
5865 * Interrupt handler.
5866 */
5867/****************************************************************************/
5868/* Main interrupt entry point. Verifies that the controller generated the */

--- 9 unchanged lines hidden (view full) ---

5878 struct bce_softc *sc;
5879 struct ifnet *ifp;
5880 u32 status_attn_bits;
5881 u16 hw_rx_cons, hw_tx_cons;
5882
5883 sc = xsc;
5884 ifp = sc->bce_ifp;
5885
6932}
6933
6934
6935/*
6936 * Interrupt handler.
6937 */
6938/****************************************************************************/
6939/* Main interrupt entry point. Verifies that the controller generated the */

--- 9 unchanged lines hidden (view full) ---

6949 struct bce_softc *sc;
6950 struct ifnet *ifp;
6951 u32 status_attn_bits;
6952 u16 hw_rx_cons, hw_tx_cons;
6953
6954 sc = xsc;
6955 ifp = sc->bce_ifp;
6956
5886 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__);
6957 DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6958 DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
6959
5887 BCE_LOCK(sc);
5888
5889 DBRUN(sc->interrupts_generated++);
5890
5891 bus_dmamap_sync(sc->status_tag, sc->status_map,
5892 BUS_DMASYNC_POSTWRITE);
5893
5894 /*
5895 * If the hardware status block index
5896 * matches the last value read by the
5897 * driver and we haven't asserted our
5898 * interrupt then there's nothing to do.
5899 */
6960 BCE_LOCK(sc);
6961
6962 DBRUN(sc->interrupts_generated++);
6963
6964 bus_dmamap_sync(sc->status_tag, sc->status_map,
6965 BUS_DMASYNC_POSTWRITE);
6966
6967 /*
6968 * If the hardware status block index
6969 * matches the last value read by the
6970 * driver and we haven't asserted our
6971 * interrupt then there's nothing to do.
6972 */
5900 if ((sc->status_block->status_idx == sc->last_status_idx) &&
5901 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5902 goto bce_intr_exit;
6973 if ((sc->status_block->status_idx == sc->last_status_idx) &&
6974 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
6975 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
6976 __FUNCTION__);
6977 goto bce_intr_exit;
6978 }
5903
5904 /* Ack the interrupt and stop others from occuring. */
5905 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5906 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5907 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5908
5909 /* Check if the hardware has finished any work. */
5910 hw_rx_cons = bce_get_hw_rx_cons(sc);

--- 8 unchanged lines hidden (view full) ---

5919 BCE_PRINTF("Simulating unexpected status attention bit set.");
5920 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);
5921
5922 /* Was it a link change interrupt? */
5923 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
5924 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
5925 bce_phy_intr(sc);
5926
6979
6980 /* Ack the interrupt and stop others from occuring. */
6981 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6982 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
6983 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6984
6985 /* Check if the hardware has finished any work. */
6986 hw_rx_cons = bce_get_hw_rx_cons(sc);

--- 8 unchanged lines hidden (view full) ---

6995 BCE_PRINTF("Simulating unexpected status attention bit set.");
6996 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);
6997
6998 /* Was it a link change interrupt? */
6999 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7000 (sc->status_block->status_attn_bits_ack & STATUS_ATTN_BITS_LINK_STATE))
7001 bce_phy_intr(sc);
7002
7003 /* Clear any transient status updates during link state change. */
7004 REG_WR(sc, BCE_HC_COMMAND,
7005 sc->hc_command | BCE_HC_COMMAND_COAL_NOW_WO_INT);
7006 REG_RD(sc, BCE_HC_COMMAND);
7007
5927 /* If any other attention is asserted then the chip is toast. */
5928 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7008 /* If any other attention is asserted then the chip is toast. */
7009 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
5929 (sc->status_block->status_attn_bits_ack &
7010 (sc->status_block->status_attn_bits_ack &
5930 ~STATUS_ATTN_BITS_LINK_STATE))) {
5931
5932 DBRUN(sc->unexpected_attentions++);
5933
7011 ~STATUS_ATTN_BITS_LINK_STATE))) {
7012
7013 DBRUN(sc->unexpected_attentions++);
7014
5934 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n",
7015 BCE_PRINTF("%s(%d): Fatal attention detected: 0x%08X\n",
5935 __FILE__, __LINE__, sc->status_block->status_attn_bits);
5936
7016 __FILE__, __LINE__, sc->status_block->status_attn_bits);
7017
5937 DBRUNMSG(BCE_FATAL,
7018 DBRUNMSG(BCE_FATAL,
5938 if (bce_debug_unexpected_attention == 0)
5939 bce_breakpoint(sc));
5940
5941 bce_init_locked(sc);
5942 goto bce_intr_exit;
5943 }
5944
5945 /* Check for any completed RX frames. */
5946 if (hw_rx_cons != sc->hw_rx_cons)
5947 bce_rx_intr(sc);
5948
5949 /* Check for any completed TX frames. */
5950 if (hw_tx_cons != sc->hw_tx_cons)
5951 bce_tx_intr(sc);
5952
5953 /* Save the status block index value for use during the next interrupt. */
5954 sc->last_status_idx = sc->status_block->status_idx;
5955
5956 /* Prevent speculative reads from getting ahead of the status block. */
7019 if (bce_debug_unexpected_attention == 0)
7020 bce_breakpoint(sc));
7021
7022 bce_init_locked(sc);
7023 goto bce_intr_exit;
7024 }
7025
7026 /* Check for any completed RX frames. */
7027 if (hw_rx_cons != sc->hw_rx_cons)
7028 bce_rx_intr(sc);
7029
7030 /* Check for any completed TX frames. */
7031 if (hw_tx_cons != sc->hw_tx_cons)
7032 bce_tx_intr(sc);
7033
7034 /* Save the status block index value for use during the next interrupt. */
7035 sc->last_status_idx = sc->status_block->status_idx;
7036
7037 /* Prevent speculative reads from getting ahead of the status block. */
5957 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7038 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5958 BUS_SPACE_BARRIER_READ);
5959
5960 /* If there's no work left then exit the interrupt service routine. */
5961 hw_rx_cons = bce_get_hw_rx_cons(sc);
5962 hw_tx_cons = bce_get_hw_tx_cons(sc);
5963
5964 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5965 break;
7039 BUS_SPACE_BARRIER_READ);
7040
7041 /* If there's no work left then exit the interrupt service routine. */
7042 hw_rx_cons = bce_get_hw_rx_cons(sc);
7043 hw_tx_cons = bce_get_hw_tx_cons(sc);
7044
7045 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
7046 break;
5966
7047
5967 }
5968
5969 bus_dmamap_sync(sc->status_tag, sc->status_map,
5970 BUS_DMASYNC_PREWRITE);
5971
5972 /* Re-enable interrupts. */
7048 }
7049
7050 bus_dmamap_sync(sc->status_tag, sc->status_map,
7051 BUS_DMASYNC_PREWRITE);
7052
7053 /* Re-enable interrupts. */
5973 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5974 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx |
5975 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5976 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5977 BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7054 bce_enable_intr(sc, 0);
5978
5979 /* Handle any frames that arrived while handling the interrupt. */
5980 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
5981 bce_start_locked(ifp);
5982
5983bce_intr_exit:
5984 BCE_UNLOCK(sc);
7055
7056 /* Handle any frames that arrived while handling the interrupt. */
7057 if (ifp->if_drv_flags & IFF_DRV_RUNNING && !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
7058 bce_start_locked(ifp);
7059
7060bce_intr_exit:
7061 BCE_UNLOCK(sc);
7062
7063 DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
5985}
5986
5987
5988/****************************************************************************/
5989/* Programs the various packet receive modes (broadcast and multicast). */
5990/* */
5991/* Returns: */
5992/* Nothing. */
5993/****************************************************************************/
5994static void
5995bce_set_rx_mode(struct bce_softc *sc)
5996{
5997 struct ifnet *ifp;
5998 struct ifmultiaddr *ifma;
5999 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
6000 u32 rx_mode, sort_mode;
6001 int h, i;
6002
7064}
7065
7066
7067/****************************************************************************/
7068/* Programs the various packet receive modes (broadcast and multicast). */
7069/* */
7070/* Returns: */
7071/* Nothing. */
7072/****************************************************************************/
7073static void
7074bce_set_rx_mode(struct bce_softc *sc)
7075{
7076 struct ifnet *ifp;
7077 struct ifmultiaddr *ifma;
7078 u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7079 u32 rx_mode, sort_mode;
7080 int h, i;
7081
7082 DBENTER(BCE_VERBOSE_MISC);
7083
6003 BCE_LOCK_ASSERT(sc);
6004
6005 ifp = sc->bce_ifp;
6006
6007 /* Initialize receive mode default settings. */
6008 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
6009 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
6010 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;

--- 41 unchanged lines hidden (view full) ---

6052 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
6053 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
6054
6055 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
6056 }
6057
6058 /* Only make changes if the recive mode has actually changed. */
6059 if (rx_mode != sc->rx_mode) {
7084 BCE_LOCK_ASSERT(sc);
7085
7086 ifp = sc->bce_ifp;
7087
7088 /* Initialize receive mode default settings. */
7089 rx_mode = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7090 BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
7091 sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;

--- 41 unchanged lines hidden (view full) ---

7133 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7134 REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
7135
7136 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
7137 }
7138
7139 /* Only make changes if the recive mode has actually changed. */
7140 if (rx_mode != sc->rx_mode) {
6060 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n",
7141 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: 0x%08X\n",
6061 rx_mode);
6062
6063 sc->rx_mode = rx_mode;
6064 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
6065 }
6066
6067 /* Disable and clear the exisitng sort before enabling a new sort. */
6068 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
6069 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
6070 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7142 rx_mode);
7143
7144 sc->rx_mode = rx_mode;
7145 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
7146 }
7147
7148 /* Disable and clear the exisitng sort before enabling a new sort. */
7149 REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
7150 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
7151 REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7152
7153 DBEXIT(BCE_VERBOSE_MISC);
6071}
6072
6073
6074/****************************************************************************/
6075/* Called periodically to updates statistics from the controllers */
6076/* statistics block. */
6077/* */
6078/* Returns: */
6079/* Nothing. */
6080/****************************************************************************/
6081static void
6082bce_stats_update(struct bce_softc *sc)
6083{
6084 struct ifnet *ifp;
6085 struct statistics_block *stats;
6086
7154}
7155
7156
7157/****************************************************************************/
7158/* Called periodically to updates statistics from the controllers */
7159/* statistics block. */
7160/* */
7161/* Returns: */
7162/* Nothing. */
7163/****************************************************************************/
7164static void
7165bce_stats_update(struct bce_softc *sc)
7166{
7167 struct ifnet *ifp;
7168 struct statistics_block *stats;
7169
6087 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__);
7170 DBENTER(BCE_EXTREME_MISC);
6088
6089 ifp = sc->bce_ifp;
6090
6091 stats = (struct statistics_block *) sc->stats_block;
6092
7171
7172 ifp = sc->bce_ifp;
7173
7174 stats = (struct statistics_block *) sc->stats_block;
7175
6093 /*
6094 * Update the interface statistics from the
6095 * hardware statistics.
6096 */
6097 ifp->if_collisions = (u_long) stats->stat_EtherStatsCollisions;
6098
6099 ifp->if_ierrors = (u_long) stats->stat_EtherStatsUndersizePkts +
6100 (u_long) stats->stat_EtherStatsOverrsizePkts +
6101 (u_long) stats->stat_IfInMBUFDiscards +
6102 (u_long) stats->stat_Dot3StatsAlignmentErrors +
6103 (u_long) stats->stat_Dot3StatsFCSErrors;
6104
6105 ifp->if_oerrors = (u_long) stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
6106 (u_long) stats->stat_Dot3StatsExcessiveCollisions +
6107 (u_long) stats->stat_Dot3StatsLateCollisions;
6108
6109 /*
6110 * Certain controllers don't report
7176 /*
7177 * Certain controllers don't report
6111 * carrier sense errors correctly.
7178 * carrier sense errors correctly.
6112 * See errata E11_5708CA0_1165.
7179 * See errata E11_5708CA0_1165.
6113 */
6114 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
6115 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
6116 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
6117
6118 /*
6119 * Update the sysctl statistics from the
6120 * hardware statistics.
6121 */
7180 */
7181 if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
7182 !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
7183 ifp->if_oerrors += (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
7184
7185 /*
7186 * Update the sysctl statistics from the
7187 * hardware statistics.
7188 */
6122 sc->stat_IfHCInOctets =
6123 ((u64) stats->stat_IfHCInOctets_hi << 32) +
7189 sc->stat_IfHCInOctets =
7190 ((u64) stats->stat_IfHCInOctets_hi << 32) +
6124 (u64) stats->stat_IfHCInOctets_lo;
6125
6126 sc->stat_IfHCInBadOctets =
7191 (u64) stats->stat_IfHCInOctets_lo;
7192
7193 sc->stat_IfHCInBadOctets =
6127 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
7194 ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
6128 (u64) stats->stat_IfHCInBadOctets_lo;
6129
6130 sc->stat_IfHCOutOctets =
6131 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
6132 (u64) stats->stat_IfHCOutOctets_lo;
6133
6134 sc->stat_IfHCOutBadOctets =
6135 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +

--- 24 unchanged lines hidden (view full) ---

6160 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
6161
6162 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
6163 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
6164
6165 sc->stat_Dot3StatsCarrierSenseErrors =
6166 stats->stat_Dot3StatsCarrierSenseErrors;
6167
7195 (u64) stats->stat_IfHCInBadOctets_lo;
7196
7197 sc->stat_IfHCOutOctets =
7198 ((u64) stats->stat_IfHCOutOctets_hi << 32) +
7199 (u64) stats->stat_IfHCOutOctets_lo;
7200
7201 sc->stat_IfHCOutBadOctets =
7202 ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +

--- 24 unchanged lines hidden (view full) ---

7227 (u64) stats->stat_IfHCOutBroadcastPkts_lo;
7228
7229 sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
7230 stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
7231
7232 sc->stat_Dot3StatsCarrierSenseErrors =
7233 stats->stat_Dot3StatsCarrierSenseErrors;
7234
6168 sc->stat_Dot3StatsFCSErrors =
7235 sc->stat_Dot3StatsFCSErrors =
6169 stats->stat_Dot3StatsFCSErrors;
6170
6171 sc->stat_Dot3StatsAlignmentErrors =
6172 stats->stat_Dot3StatsAlignmentErrors;
6173
6174 sc->stat_Dot3StatsSingleCollisionFrames =
6175 stats->stat_Dot3StatsSingleCollisionFrames;
6176

--- 111 unchanged lines hidden (view full) ---

6288 sc->stat_CatchupInMBUFDiscards =
6289 stats->stat_CatchupInMBUFDiscards;
6290
6291 sc->stat_CatchupInRuleCheckerP4Hit =
6292 stats->stat_CatchupInRuleCheckerP4Hit;
6293
6294 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
6295
7236 stats->stat_Dot3StatsFCSErrors;
7237
7238 sc->stat_Dot3StatsAlignmentErrors =
7239 stats->stat_Dot3StatsAlignmentErrors;
7240
7241 sc->stat_Dot3StatsSingleCollisionFrames =
7242 stats->stat_Dot3StatsSingleCollisionFrames;
7243

--- 111 unchanged lines hidden (view full) ---

7355 sc->stat_CatchupInMBUFDiscards =
7356 stats->stat_CatchupInMBUFDiscards;
7357
7358 sc->stat_CatchupInRuleCheckerP4Hit =
7359 stats->stat_CatchupInRuleCheckerP4Hit;
7360
7361 sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
7362
6296 DBPRINT(sc, BCE_EXCESSIVE, "Exiting %s()\n", __FUNCTION__);
7363 /*
7364 * Update the interface statistics from the
7365 * hardware statistics.
7366 */
7367 ifp->if_collisions = (u_long) sc->stat_EtherStatsCollisions;
7368
7369 ifp->if_ierrors = (u_long) sc->stat_EtherStatsUndersizePkts +
7370 (u_long) sc->stat_EtherStatsOverrsizePkts +
7371 (u_long) sc->stat_IfInMBUFDiscards +
7372 (u_long) sc->stat_Dot3StatsAlignmentErrors +
7373 (u_long) sc->stat_Dot3StatsFCSErrors +
7374 (u_long) sc->stat_IfInFramesL2FilterDiscards +
7375 (u_long) sc->stat_IfInRuleCheckerDiscards +
7376 (u_long) sc->stat_IfInFTQDiscards +
7377 (u_long) sc->com_no_buffers;
7378
7379 ifp->if_oerrors = (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
7380 (u_long) sc->stat_Dot3StatsExcessiveCollisions +
7381 (u_long) sc->stat_Dot3StatsLateCollisions;
7382
7383 DBEXIT(BCE_EXTREME_MISC);
6297}
6298
6299
6300/****************************************************************************/
6301/* Periodic function to notify the bootcode that the driver is still */
6302/* present. */
6303/* */
6304/* Returns: */
6305/* Nothing. */
6306/****************************************************************************/
6307static void
6308bce_pulse(void *xsc)
6309{
6310 struct bce_softc *sc = xsc;
6311 u32 msg;
6312
7384}
7385
7386
7387/****************************************************************************/
7388/* Periodic function to notify the bootcode that the driver is still */
7389/* present. */
7390/* */
7391/* Returns: */
7392/* Nothing. */
7393/****************************************************************************/
7394static void
7395bce_pulse(void *xsc)
7396{
7397 struct bce_softc *sc = xsc;
7398 u32 msg;
7399
6313 DBPRINT(sc, BCE_EXCESSIVE_MISC, "pulse\n");
7400 DBENTER(BCE_EXTREME_MISC);
6314
6315 BCE_LOCK_ASSERT(sc);
6316
6317 /* Tell the firmware that the driver is still running. */
6318 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
6319 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
6320
6321 /* Schedule the next pulse. */
6322 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
6323
7401
7402 BCE_LOCK_ASSERT(sc);
7403
7404 /* Tell the firmware that the driver is still running. */
7405 msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
7406 REG_WR_IND(sc, sc->bce_shmem_base + BCE_DRV_PULSE_MB, msg);
7407
7408 /* Schedule the next pulse. */
7409 callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
7410
6324 return;
7411 DBEXIT(BCE_EXTREME_MISC);
6325}
6326
6327
6328/****************************************************************************/
6329/* Periodic function to perform maintenance tasks. */
6330/* */
6331/* Returns: */
6332/* Nothing. */
6333/****************************************************************************/
6334static void
6335bce_tick(void *xsc)
6336{
6337 struct bce_softc *sc = xsc;
6338 struct mii_data *mii;
6339 struct ifnet *ifp;
6340
6341 ifp = sc->bce_ifp;
6342
7412}
7413
7414
7415/****************************************************************************/
7416/* Periodic function to perform maintenance tasks. */
7417/* */
7418/* Returns: */
7419/* Nothing. */
7420/****************************************************************************/
7421static void
7422bce_tick(void *xsc)
7423{
7424 struct bce_softc *sc = xsc;
7425 struct mii_data *mii;
7426 struct ifnet *ifp;
7427
7428 ifp = sc->bce_ifp;
7429
7430 DBENTER(BCE_EXTREME_MISC);
7431
6343 BCE_LOCK_ASSERT(sc);
6344
6345 /* Schedule the next tick. */
6346 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6347
6348 /* Update the statistics from the hardware statistics block. */
6349 bce_stats_update(sc);
6350
6351 /* Top off the receive and page chains. */
6352#ifdef BCE_USE_SPLIT_HEADER
6353 bce_fill_pg_chain(sc);
6354#endif
6355 bce_fill_rx_chain(sc);
6356
6357 /* Check that chip hasn't hung. */
6358 bce_watchdog(sc);
6359
6360 /* If link is up already up then we're done. */
6361 if (sc->bce_link)
7432 BCE_LOCK_ASSERT(sc);
7433
7434 /* Schedule the next tick. */
7435 callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7436
7437 /* Update the statistics from the hardware statistics block. */
7438 bce_stats_update(sc);
7439
7440 /* Top off the receive and page chains. */
7441#ifdef BCE_USE_SPLIT_HEADER
7442 bce_fill_pg_chain(sc);
7443#endif
7444 bce_fill_rx_chain(sc);
7445
7446 /* Check that chip hasn't hung. */
7447 bce_watchdog(sc);
7448
7449 /* If link is up already up then we're done. */
7450 if (sc->bce_link)
6362 goto bce_tick_locked_exit;
7451 goto bce_tick_exit;
6363
6364 mii = device_get_softc(sc->bce_miibus);
6365 mii_tick(mii);
6366
6367 /* Check if the link has come up. */
7452
7453 mii = device_get_softc(sc->bce_miibus);
7454 mii_tick(mii);
7455
7456 /* Check if the link has come up. */
6368 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE &&
6369 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
7457 if ((mii->mii_media_status & IFM_ACTIVE) &&
7458 (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
7459 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n", __FUNCTION__);
6370 sc->bce_link++;
6371 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
6372 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) &&
6373 bootverbose)
7460 sc->bce_link++;
7461 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
7462 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) &&
7463 bootverbose)
6374 BCE_PRINTF("Gigabit link up\n");
6375
7464 BCE_PRINTF("Gigabit link up!\n");
6376 /* Now that link is up, handle any outstanding TX traffic. */
7465 /* Now that link is up, handle any outstanding TX traffic. */
6377 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
7466 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7467 DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found pending TX traffic.\n",
7468 __FUNCTION__);
6378 bce_start_locked(ifp);
7469 bce_start_locked(ifp);
7470 }
6379 }
6380
7471 }
7472
6381bce_tick_locked_exit:
7473bce_tick_exit:
7474 DBEXIT(BCE_EXTREME_MISC);
6382 return;
6383}
6384
6385
6386#ifdef BCE_DEBUG
6387/****************************************************************************/
6388/* Allows the driver state to be dumped through the sysctl interface. */
6389/* */

--- 158 unchanged lines hidden (view full) ---

6548 sc = (struct bce_softc *)arg1;
6549 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD);
6550 }
6551
6552 return error;
6553}
6554#endif
6555
7475 return;
7476}
7477
7478
7479#ifdef BCE_DEBUG
7480/****************************************************************************/
7481/* Allows the driver state to be dumped through the sysctl interface. */
7482/* */

--- 158 unchanged lines hidden (view full) ---

7641 sc = (struct bce_softc *)arg1;
7642 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD);
7643 }
7644
7645 return error;
7646}
7647#endif
7648
7649/****************************************************************************/
7650/* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in */
7651/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
7652/* */
7653/* Returns: */
7654/* 0 for success, positive value for failure. */
7655/****************************************************************************/
7656static int
7657bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
7658{
7659 struct bce_softc *sc = (struct bce_softc *)arg1;
7660 int error;
7661 u32 result;
7662 u32 val[1];
7663 u8 *data = (u8 *) val;
6556
7664
7665 result = -1;
7666 error = sysctl_handle_int(oidp, &result, 0, req);
7667 if (error || (req->newptr == NULL))
7668 return (error);
7669
7670 bce_nvram_read(sc, result, data, 4);
7671 BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
7672
7673 return (error);
7674}
7675
7676
6557/****************************************************************************/
6558/* Provides a sysctl interface to allow reading arbitrary registers in the */
6559/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6560/* */
6561/* Returns: */
6562/* 0 for success, positive value for failure. */
6563/****************************************************************************/
6564static int
6565bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
6566{
7677/****************************************************************************/
7678/* Provides a sysctl interface to allow reading arbitrary registers in the */
7679/* device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
7680/* */
7681/* Returns: */
7682/* 0 for success, positive value for failure. */
7683/****************************************************************************/
7684static int
7685bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
7686{
6567 struct bce_softc *sc;
7687 struct bce_softc *sc = (struct bce_softc *)arg1;
6568 int error;
6569 u32 val, result;
7688 int error;
7689 u32 val, result;
6570
7690
6571 result = -1;
6572 error = sysctl_handle_int(oidp, &result, 0, req);
6573 if (error || (req->newptr == NULL))
6574 return (error);
7691 result = -1;
7692 error = sysctl_handle_int(oidp, &result, 0, req);
7693 if (error || (req->newptr == NULL))
7694 return (error);
6575
7695
6576 /* Make sure the register is accessible. */
6577 if (result < 0x8000) {
7696 /* Make sure the register is accessible. */
7697 if (result < 0x8000) {
6578 sc = (struct bce_softc *)arg1;
6579 val = REG_RD(sc, result);
6580 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
6581 } else if (result < 0x0280000) {
7698 val = REG_RD(sc, result);
7699 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
7700 } else if (result < 0x0280000) {
6582 sc = (struct bce_softc *)arg1;
6583 val = REG_RD_IND(sc, result);
6584 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
6585 }
7701 val = REG_RD_IND(sc, result);
7702 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
7703 }
6586
7704
6587 return (error);
6588}
6589
7705 return (error);
7706}
7707
6590
7708
6591/****************************************************************************/
6592/* Provides a sysctl interface to allow reading arbitrary PHY registers in */
6593/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6594/* */
6595/* Returns: */
6596/* 0 for success, positive value for failure. */
6597/****************************************************************************/
6598static int

--- 16 unchanged lines hidden (view full) ---

6615 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
6616 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
6617 }
6618 return (error);
6619}
6620
6621
6622/****************************************************************************/
7709/****************************************************************************/
7710/* Provides a sysctl interface to allow reading arbitrary PHY registers in */
7711/* the device. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
7712/* */
7713/* Returns: */
7714/* 0 for success, positive value for failure. */
7715/****************************************************************************/
7716static int

--- 16 unchanged lines hidden (view full) ---

7733 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
7734 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
7735 }
7736 return (error);
7737}
7738
7739
7740/****************************************************************************/
7741/* Provides a sysctl interface to allow reading a CID. */
7742/* */
7743/* Returns: */
7744/* 0 for success, positive value for failure. */
7745/****************************************************************************/
7746static int
7747bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
7748{
7749 struct bce_softc *sc;
7750 int error;
7751 u16 result;
7752
7753 result = -1;
7754 error = sysctl_handle_int(oidp, &result, 0, req);
7755 if (error || (req->newptr == NULL))
7756 return (error);
7757
7758 /* Make sure the register is accessible. */
7759 if (result <= TX_CID) {
7760 sc = (struct bce_softc *)arg1;
7761 bce_dump_ctx(sc, result);
7762 }
7763
7764 return (error);
7765}
7766
7767
7768 /****************************************************************************/
6623/* Provides a sysctl interface to forcing the driver to dump state and */
6624/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
6625/* */
6626/* Returns: */
6627/* 0 for success, positive value for failure. */
6628/****************************************************************************/
6629static int
6630bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)

--- 25 unchanged lines hidden (view full) ---

6656/* 0 for success, positive value for failure. */
6657/****************************************************************************/
6658static void
6659bce_add_sysctls(struct bce_softc *sc)
6660{
6661 struct sysctl_ctx_list *ctx;
6662 struct sysctl_oid_list *children;
6663
7769/* Provides a sysctl interface to forcing the driver to dump state and */
7770/* enter the debugger. DO NOT ENABLE ON PRODUCTION SYSTEMS! */
7771/* */
7772/* Returns: */
7773/* 0 for success, positive value for failure. */
7774/****************************************************************************/
7775static int
7776bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)

--- 25 unchanged lines hidden (view full) ---

7802/* 0 for success, positive value for failure. */
7803/****************************************************************************/
7804static void
7805bce_add_sysctls(struct bce_softc *sc)
7806{
7807 struct sysctl_ctx_list *ctx;
7808 struct sysctl_oid_list *children;
7809
7810 DBENTER(BCE_VERBOSE_MISC);
7811
6664 ctx = device_get_sysctl_ctx(sc->bce_dev);
6665 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
6666
6667#ifdef BCE_DEBUG
7812 ctx = device_get_sysctl_ctx(sc->bce_dev);
7813 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
7814
7815#ifdef BCE_DEBUG
6668 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7816 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6669 "rx_low_watermark",
6670 CTLFLAG_RD, &sc->rx_low_watermark,
6671 0, "Lowest level of free rx_bd's");
6672
7817 "rx_low_watermark",
7818 CTLFLAG_RD, &sc->rx_low_watermark,
7819 0, "Lowest level of free rx_bd's");
7820
6673 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7821 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6674 "rx_empty_count",
6675 CTLFLAG_RD, &sc->rx_empty_count,
6676 0, "Number of times the RX chain was empty");
6677
7822 "rx_empty_count",
7823 CTLFLAG_RD, &sc->rx_empty_count,
7824 0, "Number of times the RX chain was empty");
7825
6678 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7826 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6679 "tx_hi_watermark",
6680 CTLFLAG_RD, &sc->tx_hi_watermark,
6681 0, "Highest level of used tx_bd's");
6682
7827 "tx_hi_watermark",
7828 CTLFLAG_RD, &sc->tx_hi_watermark,
7829 0, "Highest level of used tx_bd's");
7830
6683 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7831 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6684 "tx_full_count",
6685 CTLFLAG_RD, &sc->tx_full_count,
6686 0, "Number of times the TX chain was full");
6687
7832 "tx_full_count",
7833 CTLFLAG_RD, &sc->tx_full_count,
7834 0, "Number of times the TX chain was full");
7835
6688 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7836 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6689 "l2fhdr_status_errors",
6690 CTLFLAG_RD, &sc->l2fhdr_status_errors,
6691 0, "l2_fhdr status errors");
6692
7837 "l2fhdr_status_errors",
7838 CTLFLAG_RD, &sc->l2fhdr_status_errors,
7839 0, "l2_fhdr status errors");
7840
6693 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7841 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6694 "unexpected_attentions",
6695 CTLFLAG_RD, &sc->unexpected_attentions,
6696 0, "Unexpected attentions");
6697
7842 "unexpected_attentions",
7843 CTLFLAG_RD, &sc->unexpected_attentions,
7844 0, "Unexpected attentions");
7845
6698 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7846 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6699 "lost_status_block_updates",
6700 CTLFLAG_RD, &sc->lost_status_block_updates,
6701 0, "Lost status block updates");
6702
7847 "lost_status_block_updates",
7848 CTLFLAG_RD, &sc->lost_status_block_updates,
7849 0, "Lost status block updates");
7850
6703 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7851 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6704 "debug_mbuf_sim_alloc_failed",
6705 CTLFLAG_RD, &sc->debug_mbuf_sim_alloc_failed,
6706 0, "Simulated mbuf cluster allocation failures");
6707
7852 "debug_mbuf_sim_alloc_failed",
7853 CTLFLAG_RD, &sc->debug_mbuf_sim_alloc_failed,
7854 0, "Simulated mbuf cluster allocation failures");
7855
6708 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7856 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6709 "requested_tso_frames",
6710 CTLFLAG_RD, &sc->requested_tso_frames,
6711 0, "Number of TSO frames received");
6712
7857 "requested_tso_frames",
7858 CTLFLAG_RD, &sc->requested_tso_frames,
7859 0, "Number of TSO frames received");
7860
6713 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7861 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6714 "rx_interrupts",
6715 CTLFLAG_RD, &sc->rx_interrupts,
6716 0, "Number of RX interrupts");
6717
7862 "rx_interrupts",
7863 CTLFLAG_RD, &sc->rx_interrupts,
7864 0, "Number of RX interrupts");
7865
6718 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7866 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6719 "tx_interrupts",
6720 CTLFLAG_RD, &sc->tx_interrupts,
6721 0, "Number of TX interrupts");
6722
7867 "tx_interrupts",
7868 CTLFLAG_RD, &sc->tx_interrupts,
7869 0, "Number of TX interrupts");
7870
6723 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7871 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6724 "rx_intr_time",
6725 CTLFLAG_RD, &sc->rx_intr_time,
6726 "RX interrupt time");
6727
7872 "rx_intr_time",
7873 CTLFLAG_RD, &sc->rx_intr_time,
7874 "RX interrupt time");
7875
6728 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7876 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6729 "tx_intr_time",
6730 CTLFLAG_RD, &sc->tx_intr_time,
6731 "TX interrupt time");
7877 "tx_intr_time",
7878 CTLFLAG_RD, &sc->tx_intr_time,
7879 "TX interrupt time");
7880#endif
6732
7881
6733#endif
6734
6735 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7882 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6736 "mbuf_alloc_failed",
6737 CTLFLAG_RD, &sc->mbuf_alloc_failed,
6738 0, "mbuf cluster allocation failures");
6739
7883 "mbuf_alloc_failed",
7884 CTLFLAG_RD, &sc->mbuf_alloc_failed,
7885 0, "mbuf cluster allocation failures");
7886
6740 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
7887 SYSCTL_ADD_INT(ctx, children, OID_AUTO,
6741 "tx_dma_map_failures",
6742 CTLFLAG_RD, &sc->tx_dma_map_failures,
6743 0, "tx dma mapping failures");
6744
7888 "tx_dma_map_failures",
7889 CTLFLAG_RD, &sc->tx_dma_map_failures,
7890 0, "tx dma mapping failures");
7891
6745 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7892 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6746 "stat_IfHcInOctets",
6747 CTLFLAG_RD, &sc->stat_IfHCInOctets,
6748 "Bytes received");
6749
7893 "stat_IfHcInOctets",
7894 CTLFLAG_RD, &sc->stat_IfHCInOctets,
7895 "Bytes received");
7896
6750 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7897 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6751 "stat_IfHCInBadOctets",
6752 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
6753 "Bad bytes received");
6754
7898 "stat_IfHCInBadOctets",
7899 CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
7900 "Bad bytes received");
7901
6755 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7902 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6756 "stat_IfHCOutOctets",
6757 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
6758 "Bytes sent");
6759
7903 "stat_IfHCOutOctets",
7904 CTLFLAG_RD, &sc->stat_IfHCOutOctets,
7905 "Bytes sent");
7906
6760 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7907 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6761 "stat_IfHCOutBadOctets",
6762 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
6763 "Bad bytes sent");
6764
7908 "stat_IfHCOutBadOctets",
7909 CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
7910 "Bad bytes sent");
7911
6765 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7912 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6766 "stat_IfHCInUcastPkts",
6767 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
6768 "Unicast packets received");
6769
7913 "stat_IfHCInUcastPkts",
7914 CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
7915 "Unicast packets received");
7916
6770 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7917 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6771 "stat_IfHCInMulticastPkts",
6772 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
6773 "Multicast packets received");
6774
7918 "stat_IfHCInMulticastPkts",
7919 CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
7920 "Multicast packets received");
7921
6775 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7922 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6776 "stat_IfHCInBroadcastPkts",
6777 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
6778 "Broadcast packets received");
6779
7923 "stat_IfHCInBroadcastPkts",
7924 CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
7925 "Broadcast packets received");
7926
6780 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7927 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6781 "stat_IfHCOutUcastPkts",
6782 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
6783 "Unicast packets sent");
6784
7928 "stat_IfHCOutUcastPkts",
7929 CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
7930 "Unicast packets sent");
7931
6785 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7932 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6786 "stat_IfHCOutMulticastPkts",
6787 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
6788 "Multicast packets sent");
6789
7933 "stat_IfHCOutMulticastPkts",
7934 CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
7935 "Multicast packets sent");
7936
6790 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
7937 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
6791 "stat_IfHCOutBroadcastPkts",
6792 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
6793 "Broadcast packets sent");
6794
7938 "stat_IfHCOutBroadcastPkts",
7939 CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
7940 "Broadcast packets sent");
7941
6795 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7942 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6796 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
6797 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
6798 0, "Internal MAC transmit errors");
6799
7943 "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
7944 CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
7945 0, "Internal MAC transmit errors");
7946
6800 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7947 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6801 "stat_Dot3StatsCarrierSenseErrors",
6802 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
6803 0, "Carrier sense errors");
6804
7948 "stat_Dot3StatsCarrierSenseErrors",
7949 CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
7950 0, "Carrier sense errors");
7951
6805 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7952 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6806 "stat_Dot3StatsFCSErrors",
6807 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
6808 0, "Frame check sequence errors");
6809
7953 "stat_Dot3StatsFCSErrors",
7954 CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
7955 0, "Frame check sequence errors");
7956
6810 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7957 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6811 "stat_Dot3StatsAlignmentErrors",
6812 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
6813 0, "Alignment errors");
6814
7958 "stat_Dot3StatsAlignmentErrors",
7959 CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
7960 0, "Alignment errors");
7961
6815 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7962 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6816 "stat_Dot3StatsSingleCollisionFrames",
6817 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
6818 0, "Single Collision Frames");
6819
7963 "stat_Dot3StatsSingleCollisionFrames",
7964 CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
7965 0, "Single Collision Frames");
7966
6820 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7967 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6821 "stat_Dot3StatsMultipleCollisionFrames",
6822 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
6823 0, "Multiple Collision Frames");
6824
7968 "stat_Dot3StatsMultipleCollisionFrames",
7969 CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
7970 0, "Multiple Collision Frames");
7971
6825 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7972 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6826 "stat_Dot3StatsDeferredTransmissions",
6827 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
6828 0, "Deferred Transmissions");
6829
7973 "stat_Dot3StatsDeferredTransmissions",
7974 CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
7975 0, "Deferred Transmissions");
7976
6830 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7977 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6831 "stat_Dot3StatsExcessiveCollisions",
6832 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
6833 0, "Excessive Collisions");
6834
7978 "stat_Dot3StatsExcessiveCollisions",
7979 CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
7980 0, "Excessive Collisions");
7981
6835 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7982 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6836 "stat_Dot3StatsLateCollisions",
6837 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
6838 0, "Late Collisions");
6839
7983 "stat_Dot3StatsLateCollisions",
7984 CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
7985 0, "Late Collisions");
7986
6840 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7987 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6841 "stat_EtherStatsCollisions",
6842 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
6843 0, "Collisions");
6844
7988 "stat_EtherStatsCollisions",
7989 CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
7990 0, "Collisions");
7991
6845 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7992 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6846 "stat_EtherStatsFragments",
6847 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
6848 0, "Fragments");
6849
7993 "stat_EtherStatsFragments",
7994 CTLFLAG_RD, &sc->stat_EtherStatsFragments,
7995 0, "Fragments");
7996
6850 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7997 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6851 "stat_EtherStatsJabbers",
6852 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
6853 0, "Jabbers");
6854
7998 "stat_EtherStatsJabbers",
7999 CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
8000 0, "Jabbers");
8001
6855 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8002 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6856 "stat_EtherStatsUndersizePkts",
6857 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
6858 0, "Undersize packets");
6859
8003 "stat_EtherStatsUndersizePkts",
8004 CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8005 0, "Undersize packets");
8006
6860 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8007 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6861 "stat_EtherStatsOverrsizePkts",
6862 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
6863 0, "stat_EtherStatsOverrsizePkts");
6864
8008 "stat_EtherStatsOverrsizePkts",
8009 CTLFLAG_RD, &sc->stat_EtherStatsOverrsizePkts,
8010 0, "stat_EtherStatsOverrsizePkts");
8011
6865 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8012 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6866 "stat_EtherStatsPktsRx64Octets",
6867 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
6868 0, "Bytes received in 64 byte packets");
6869
8013 "stat_EtherStatsPktsRx64Octets",
8014 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8015 0, "Bytes received in 64 byte packets");
8016
6870 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8017 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6871 "stat_EtherStatsPktsRx65Octetsto127Octets",
6872 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
6873 0, "Bytes received in 65 to 127 byte packets");
6874
8018 "stat_EtherStatsPktsRx65Octetsto127Octets",
8019 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
8020 0, "Bytes received in 65 to 127 byte packets");
8021
6875 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8022 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6876 "stat_EtherStatsPktsRx128Octetsto255Octets",
6877 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
6878 0, "Bytes received in 128 to 255 byte packets");
6879
8023 "stat_EtherStatsPktsRx128Octetsto255Octets",
8024 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
8025 0, "Bytes received in 128 to 255 byte packets");
8026
6880 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8027 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6881 "stat_EtherStatsPktsRx256Octetsto511Octets",
6882 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
6883 0, "Bytes received in 256 to 511 byte packets");
6884
8028 "stat_EtherStatsPktsRx256Octetsto511Octets",
8029 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
8030 0, "Bytes received in 256 to 511 byte packets");
8031
6885 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8032 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6886 "stat_EtherStatsPktsRx512Octetsto1023Octets",
6887 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
6888 0, "Bytes received in 512 to 1023 byte packets");
6889
8033 "stat_EtherStatsPktsRx512Octetsto1023Octets",
8034 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
8035 0, "Bytes received in 512 to 1023 byte packets");
8036
6890 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8037 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6891 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
6892 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
6893 0, "Bytes received in 1024 t0 1522 byte packets");
6894
8038 "stat_EtherStatsPktsRx1024Octetsto1522Octets",
8039 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
8040 0, "Bytes received in 1024 t0 1522 byte packets");
8041
6895 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8042 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6896 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
6897 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
6898 0, "Bytes received in 1523 to 9022 byte packets");
6899
8043 "stat_EtherStatsPktsRx1523Octetsto9022Octets",
8044 CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
8045 0, "Bytes received in 1523 to 9022 byte packets");
8046
6900 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8047 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6901 "stat_EtherStatsPktsTx64Octets",
6902 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
6903 0, "Bytes sent in 64 byte packets");
6904
8048 "stat_EtherStatsPktsTx64Octets",
8049 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
8050 0, "Bytes sent in 64 byte packets");
8051
6905 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8052 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6906 "stat_EtherStatsPktsTx65Octetsto127Octets",
6907 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
6908 0, "Bytes sent in 65 to 127 byte packets");
6909
8053 "stat_EtherStatsPktsTx65Octetsto127Octets",
8054 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
8055 0, "Bytes sent in 65 to 127 byte packets");
8056
6910 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8057 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6911 "stat_EtherStatsPktsTx128Octetsto255Octets",
6912 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
6913 0, "Bytes sent in 128 to 255 byte packets");
6914
8058 "stat_EtherStatsPktsTx128Octetsto255Octets",
8059 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
8060 0, "Bytes sent in 128 to 255 byte packets");
8061
6915 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8062 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6916 "stat_EtherStatsPktsTx256Octetsto511Octets",
6917 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
6918 0, "Bytes sent in 256 to 511 byte packets");
6919
8063 "stat_EtherStatsPktsTx256Octetsto511Octets",
8064 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
8065 0, "Bytes sent in 256 to 511 byte packets");
8066
6920 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8067 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6921 "stat_EtherStatsPktsTx512Octetsto1023Octets",
6922 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
6923 0, "Bytes sent in 512 to 1023 byte packets");
6924
8068 "stat_EtherStatsPktsTx512Octetsto1023Octets",
8069 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
8070 0, "Bytes sent in 512 to 1023 byte packets");
8071
6925 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8072 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6926 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
6927 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
6928 0, "Bytes sent in 1024 to 1522 byte packets");
6929
8073 "stat_EtherStatsPktsTx1024Octetsto1522Octets",
8074 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
8075 0, "Bytes sent in 1024 to 1522 byte packets");
8076
6930 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8077 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6931 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
6932 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
6933 0, "Bytes sent in 1523 to 9022 byte packets");
6934
8078 "stat_EtherStatsPktsTx1523Octetsto9022Octets",
8079 CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
8080 0, "Bytes sent in 1523 to 9022 byte packets");
8081
6935 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8082 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6936 "stat_XonPauseFramesReceived",
6937 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
6938 0, "XON pause frames receved");
6939
8083 "stat_XonPauseFramesReceived",
8084 CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
8085 0, "XON pause frames receved");
8086
6940 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8087 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6941 "stat_XoffPauseFramesReceived",
6942 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
6943 0, "XOFF pause frames received");
6944
8088 "stat_XoffPauseFramesReceived",
8089 CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
8090 0, "XOFF pause frames received");
8091
6945 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8092 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6946 "stat_OutXonSent",
6947 CTLFLAG_RD, &sc->stat_OutXonSent,
6948 0, "XON pause frames sent");
6949
8093 "stat_OutXonSent",
8094 CTLFLAG_RD, &sc->stat_OutXonSent,
8095 0, "XON pause frames sent");
8096
6950 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8097 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6951 "stat_OutXoffSent",
6952 CTLFLAG_RD, &sc->stat_OutXoffSent,
6953 0, "XOFF pause frames sent");
6954
8098 "stat_OutXoffSent",
8099 CTLFLAG_RD, &sc->stat_OutXoffSent,
8100 0, "XOFF pause frames sent");
8101
6955 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8102 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6956 "stat_FlowControlDone",
6957 CTLFLAG_RD, &sc->stat_FlowControlDone,
6958 0, "Flow control done");
6959
8103 "stat_FlowControlDone",
8104 CTLFLAG_RD, &sc->stat_FlowControlDone,
8105 0, "Flow control done");
8106
6960 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6961 "stat_MacControlFramesReceived",
6962 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
6963 0, "MAC control frames received");
6964
8108 "stat_MacControlFramesReceived",
8109 CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
8110 0, "MAC control frames received");
8111
6965 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8112 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6966 "stat_XoffStateEntered",
6967 CTLFLAG_RD, &sc->stat_XoffStateEntered,
6968 0, "XOFF state entered");
6969
8113 "stat_XoffStateEntered",
8114 CTLFLAG_RD, &sc->stat_XoffStateEntered,
8115 0, "XOFF state entered");
8116
6970 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6971 "stat_IfInFramesL2FilterDiscards",
6972 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
6973 0, "Received L2 packets discarded");
6974
8118 "stat_IfInFramesL2FilterDiscards",
8119 CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
8120 0, "Received L2 packets discarded");
8121
6975 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8122 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6976 "stat_IfInRuleCheckerDiscards",
6977 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
6978 0, "Received packets discarded by rule");
6979
8123 "stat_IfInRuleCheckerDiscards",
8124 CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
8125 0, "Received packets discarded by rule");
8126
6980 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8127 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6981 "stat_IfInFTQDiscards",
6982 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
6983 0, "Received packet FTQ discards");
6984
8128 "stat_IfInFTQDiscards",
8129 CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
8130 0, "Received packet FTQ discards");
8131
6985 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8132 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6986 "stat_IfInMBUFDiscards",
6987 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
6988 0, "Received packets discarded due to lack of controller buffer memory");
6989
8133 "stat_IfInMBUFDiscards",
8134 CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
8135 0, "Received packets discarded due to lack of controller buffer memory");
8136
6990 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8137 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6991 "stat_IfInRuleCheckerP4Hit",
6992 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
6993 0, "Received packets rule checker hits");
6994
8138 "stat_IfInRuleCheckerP4Hit",
8139 CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
8140 0, "Received packets rule checker hits");
8141
6995 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8142 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
6996 "stat_CatchupInRuleCheckerDiscards",
6997 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
6998 0, "Received packets discarded in Catchup path");
6999
8143 "stat_CatchupInRuleCheckerDiscards",
8144 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
8145 0, "Received packets discarded in Catchup path");
8146
7000 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8147 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7001 "stat_CatchupInFTQDiscards",
7002 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
7003 0, "Received packets discarded in FTQ in Catchup path");
7004
8148 "stat_CatchupInFTQDiscards",
8149 CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
8150 0, "Received packets discarded in FTQ in Catchup path");
8151
7005 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8152 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7006 "stat_CatchupInMBUFDiscards",
7007 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
7008 0, "Received packets discarded in controller buffer memory in Catchup path");
7009
8153 "stat_CatchupInMBUFDiscards",
8154 CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
8155 0, "Received packets discarded in controller buffer memory in Catchup path");
8156
7010 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8157 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7011 "stat_CatchupInRuleCheckerP4Hit",
7012 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
7013 0, "Received packets rule checker hits in Catchup path");
7014
8158 "stat_CatchupInRuleCheckerP4Hit",
8159 CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
8160 0, "Received packets rule checker hits in Catchup path");
8161
7015 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8162 SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
7016 "com_no_buffers",
7017 CTLFLAG_RD, &sc->com_no_buffers,
7018 0, "Valid packets received but no RX buffers available");
7019
7020#ifdef BCE_DEBUG
7021 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
7022 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
7023 (void *)sc, 0,

--- 20 unchanged lines hidden (view full) ---

7044 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
7045
7046#ifdef BCE_USE_SPLIT_HEADER
7047 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
7048 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
7049 (void *)sc, 0,
7050 bce_sysctl_dump_pg_chain, "I", "Dump page chain");
7051#endif
8163 "com_no_buffers",
8164 CTLFLAG_RD, &sc->com_no_buffers,
8165 0, "Valid packets received but no RX buffers available");
8166
8167#ifdef BCE_DEBUG
8168 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8169 "driver_state", CTLTYPE_INT | CTLFLAG_RW,
8170 (void *)sc, 0,

--- 20 unchanged lines hidden (view full) ---

8191 bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
8192
8193#ifdef BCE_USE_SPLIT_HEADER
8194 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8195 "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
8196 (void *)sc, 0,
8197 bce_sysctl_dump_pg_chain, "I", "Dump page chain");
8198#endif
8199 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8200 "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
8201 (void *)sc, 0,
8202 bce_sysctl_dump_ctx, "I", "Dump context memory");
7052
7053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
7054 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
7055 (void *)sc, 0,
7056 bce_sysctl_breakpoint, "I", "Driver breakpoint");
7057
8203
8204 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8205 "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
8206 (void *)sc, 0,
8207 bce_sysctl_breakpoint, "I", "Driver breakpoint");
8208
7058 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
7059 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
7060 (void *)sc, 0,
8209 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8210 "reg_read", CTLTYPE_INT | CTLFLAG_RW,
8211 (void *)sc, 0,
7061 bce_sysctl_reg_read, "I", "Register read");
7062
8212 bce_sysctl_reg_read, "I", "Register read");
8213
7063 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
7064 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
7065 (void *)sc, 0,
8214 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8215 "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
8216 (void *)sc, 0,
8217 bce_sysctl_nvram_read, "I", "NVRAM read");
8218
8219 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8220 "phy_read", CTLTYPE_INT | CTLFLAG_RW,
8221 (void *)sc, 0,
7066 bce_sysctl_phy_read, "I", "PHY register read");
7067
7068#endif
7069
8222 bce_sysctl_phy_read, "I", "PHY register read");
8223
8224#endif
8225
8226 DBEXIT(BCE_VERBOSE_MISC);
7070}
7071
7072
7073/****************************************************************************/
7074/* BCE Debug Routines */
7075/****************************************************************************/
7076#ifdef BCE_DEBUG
7077

--- 5 unchanged lines hidden (view full) ---

7083/****************************************************************************/
7084static void
7085bce_freeze_controller(struct bce_softc *sc)
7086{
7087 u32 val;
7088 val = REG_RD(sc, BCE_MISC_COMMAND);
7089 val |= BCE_MISC_COMMAND_DISABLE_ALL;
7090 REG_WR(sc, BCE_MISC_COMMAND, val);
8227}
8228
8229
8230/****************************************************************************/
8231/* BCE Debug Routines */
8232/****************************************************************************/
8233#ifdef BCE_DEBUG
8234

--- 5 unchanged lines hidden (view full) ---

8240/****************************************************************************/
8241static void
8242bce_freeze_controller(struct bce_softc *sc)
8243{
8244 u32 val;
8245 val = REG_RD(sc, BCE_MISC_COMMAND);
8246 val |= BCE_MISC_COMMAND_DISABLE_ALL;
8247 REG_WR(sc, BCE_MISC_COMMAND, val);
7091
7092}
7093
7094
7095/****************************************************************************/
7096/* Unfreezes the controller after a freeze operation. This may not always */
7097/* work and the controller will require a reset! */
7098/* */
7099/* Returns: */
7100/* Nothing. */
7101/****************************************************************************/
7102static void
7103bce_unfreeze_controller(struct bce_softc *sc)
7104{
7105 u32 val;
7106 val = REG_RD(sc, BCE_MISC_COMMAND);
7107 val |= BCE_MISC_COMMAND_ENABLE_ALL;
7108 REG_WR(sc, BCE_MISC_COMMAND, val);
8248}
8249
8250
8251/****************************************************************************/
8252/* Unfreezes the controller after a freeze operation. This may not always */
8253/* work and the controller will require a reset! */
8254/* */
8255/* Returns: */
8256/* Nothing. */
8257/****************************************************************************/
8258static void
8259bce_unfreeze_controller(struct bce_softc *sc)
8260{
8261 u32 val;
8262 val = REG_RD(sc, BCE_MISC_COMMAND);
8263 val |= BCE_MISC_COMMAND_ENABLE_ALL;
8264 REG_WR(sc, BCE_MISC_COMMAND, val);
7109
7110}
7111
7112/****************************************************************************/
7113/* Prints out information about an mbuf. */
7114/* */
7115/* Returns: */
7116/* Nothing. */
7117/****************************************************************************/
8265}
8266
8267/****************************************************************************/
8268/* Prints out information about an mbuf. */
8269/* */
8270/* Returns: */
8271/* Nothing. */
8272/****************************************************************************/
7118static void
8273static __attribute__ ((noinline)) void
7119bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
7120{
7121 struct mbuf *mp = m;
7122
7123 if (m == NULL) {
7124 BCE_PRINTF("mbuf: null pointer\n");
7125 return;
7126 }
7127
7128 while (mp) {
8274bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
8275{
8276 struct mbuf *mp = m;
8277
8278 if (m == NULL) {
8279 BCE_PRINTF("mbuf: null pointer\n");
8280 return;
8281 }
8282
8283 while (mp) {
7129 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n",
7130 mp, mp->m_len, mp->m_flags,
8284 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, m_data = %p\n",
8285 mp, mp->m_len, mp->m_flags,
7131 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY",
7132 mp->m_data);
7133
7134 if (mp->m_flags & M_PKTHDR) {
8286 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY",
8287 mp->m_data);
8288
8289 if (mp->m_flags & M_PKTHDR) {
7135 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n",
8290 BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, csum_flags = %b\n",
7136 mp->m_pkthdr.len, mp->m_flags,
7137 "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG"
7138 "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE",
7139 mp->m_pkthdr.csum_flags,
7140 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
7141 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
7142 "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR");
7143 }
7144
7145 if (mp->m_flags & M_EXT) {
8291 mp->m_pkthdr.len, mp->m_flags,
8292 "\20\12M_BCAST\13M_MCAST\14M_FRAG\15M_FIRSTFRAG"
8293 "\16M_LASTFRAG\21M_VLANTAG\22M_PROMISC\23M_NOFREE",
8294 mp->m_pkthdr.csum_flags,
8295 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
8296 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
8297 "\12CSUM_IP_VALID\13CSUM_DATA_VALID\14CSUM_PSEUDO_HDR");
8298 }
8299
8300 if (mp->m_flags & M_EXT) {
7146 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
8301 BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
7147 mp->m_ext.ext_buf, mp->m_ext.ext_size);
7148 switch (mp->m_ext.ext_type) {
7149 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break;
7150 case EXT_SFBUF: printf("EXT_SFBUF\n"); break;
7151 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break;
7152 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break;
7153 case EXT_PACKET: printf("EXT_PACKET\n"); break;
7154 case EXT_MBUF: printf("EXT_MBUF\n"); break;

--- 11 unchanged lines hidden (view full) ---

7166
7167
7168/****************************************************************************/
7169/* Prints out the mbufs in the TX mbuf chain. */
7170/* */
7171/* Returns: */
7172/* Nothing. */
7173/****************************************************************************/
8302 mp->m_ext.ext_buf, mp->m_ext.ext_size);
8303 switch (mp->m_ext.ext_type) {
8304 case EXT_CLUSTER: printf("EXT_CLUSTER\n"); break;
8305 case EXT_SFBUF: printf("EXT_SFBUF\n"); break;
8306 case EXT_JUMBO9: printf("EXT_JUMBO9\n"); break;
8307 case EXT_JUMBO16: printf("EXT_JUMBO16\n"); break;
8308 case EXT_PACKET: printf("EXT_PACKET\n"); break;
8309 case EXT_MBUF: printf("EXT_MBUF\n"); break;

--- 11 unchanged lines hidden (view full) ---

8321
8322
8323/****************************************************************************/
8324/* Prints out the mbufs in the TX mbuf chain. */
8325/* */
8326/* Returns: */
8327/* Nothing. */
8328/****************************************************************************/
7174static void
8329static __attribute__ ((noinline)) void
7175bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
7176{
7177 struct mbuf *m;
7178
7179 BCE_PRINTF(
7180 "----------------------------"
7181 " tx mbuf data "
7182 "----------------------------\n");

--- 13 unchanged lines hidden (view full) ---

7196
7197
7198/****************************************************************************/
7199/* Prints out the mbufs in the RX mbuf chain. */
7200/* */
7201/* Returns: */
7202/* Nothing. */
7203/****************************************************************************/
8330bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8331{
8332 struct mbuf *m;
8333
8334 BCE_PRINTF(
8335 "----------------------------"
8336 " tx mbuf data "
8337 "----------------------------\n");

--- 13 unchanged lines hidden (view full) ---

8351
8352
8353/****************************************************************************/
8354/* Prints out the mbufs in the RX mbuf chain. */
8355/* */
8356/* Returns: */
8357/* Nothing. */
8358/****************************************************************************/
7204static void
8359static __attribute__ ((noinline)) void
7205bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
7206{
7207 struct mbuf *m;
7208
7209 BCE_PRINTF(
7210 "----------------------------"
7211 " rx mbuf data "
7212 "----------------------------\n");

--- 15 unchanged lines hidden (view full) ---

7228
7229#ifdef BCE_USE_SPLIT_HEADER
7230/****************************************************************************/
7231/* Prints out the mbufs in the mbuf page chain. */
7232/* */
7233/* Returns: */
7234/* Nothing. */
7235/****************************************************************************/
8360bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8361{
8362 struct mbuf *m;
8363
8364 BCE_PRINTF(
8365 "----------------------------"
8366 " rx mbuf data "
8367 "----------------------------\n");

--- 15 unchanged lines hidden (view full) ---

8383
8384#ifdef BCE_USE_SPLIT_HEADER
8385/****************************************************************************/
8386/* Prints out the mbufs in the mbuf page chain. */
8387/* */
8388/* Returns: */
8389/* Nothing. */
8390/****************************************************************************/
7236static void
8391static __attribute__ ((noinline)) void
7237bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
7238{
7239 struct mbuf *m;
7240
7241 BCE_PRINTF(
7242 "----------------------------"
7243 " pg mbuf data "
7244 "----------------------------\n");

--- 15 unchanged lines hidden (view full) ---

7260
7261
7262/****************************************************************************/
7263/* Prints out a tx_bd structure. */
7264/* */
7265/* Returns: */
7266/* Nothing. */
7267/****************************************************************************/
8392bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
8393{
8394 struct mbuf *m;
8395
8396 BCE_PRINTF(
8397 "----------------------------"
8398 " pg mbuf data "
8399 "----------------------------\n");

--- 15 unchanged lines hidden (view full) ---

8415
8416
8417/****************************************************************************/
8418/* Prints out a tx_bd structure. */
8419/* */
8420/* Returns: */
8421/* Nothing. */
8422/****************************************************************************/
7268static void
8423static __attribute__ ((noinline)) void
7269bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
7270{
7271 if (idx > MAX_TX_BD)
7272 /* Index out of range. */
7273 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
7274 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
7275 /* TX Chain page pointer. */
8424bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
8425{
8426 if (idx > MAX_TX_BD)
8427 /* Index out of range. */
8428 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
8429 else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
8430 /* TX Chain page pointer. */
7276 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8431 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
7277 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
7278 else {
7279 /* Normal tx_bd entry. */
7280 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8432 idx, txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo);
8433 else {
8434 /* Normal tx_bd entry. */
8435 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
7281 "vlan tag= 0x%04X, flags = 0x%04X (", idx,
8436 "vlan tag= 0x%04X, flags = 0x%04X (", idx,
7282 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
7283 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag,
7284 txbd->tx_bd_flags);
7285
7286 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
7287 printf(" CONN_FAULT");
7288
7289 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)

--- 26 unchanged lines hidden (view full) ---

7316 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
7317 printf(" FLAGS");
7318
7319 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
7320 printf(" SNAP");
7321
7322 printf(" )\n");
7323 }
8437 txbd->tx_bd_haddr_hi, txbd->tx_bd_haddr_lo,
8438 txbd->tx_bd_mss_nbytes, txbd->tx_bd_vlan_tag,
8439 txbd->tx_bd_flags);
8440
8441 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT)
8442 printf(" CONN_FAULT");
8443
8444 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM)

--- 26 unchanged lines hidden (view full) ---

8471 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS)
8472 printf(" FLAGS");
8473
8474 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP)
8475 printf(" SNAP");
8476
8477 printf(" )\n");
8478 }
7324
8479
7325}
7326
7327
7328/****************************************************************************/
7329/* Prints out a rx_bd structure. */
7330/* */
7331/* Returns: */
7332/* Nothing. */
7333/****************************************************************************/
8480}
8481
8482
8483/****************************************************************************/
8484/* Prints out a rx_bd structure. */
8485/* */
8486/* Returns: */
8487/* Nothing. */
8488/****************************************************************************/
7334static void
8489static __attribute__ ((noinline)) void
7335bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
7336{
7337 if (idx > MAX_RX_BD)
7338 /* Index out of range. */
7339 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
7340 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
7341 /* RX Chain page pointer. */
8490bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
8491{
8492 if (idx > MAX_RX_BD)
8493 /* Index out of range. */
8494 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
8495 else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
8496 /* RX Chain page pointer. */
7342 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8497 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
7343 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
7344 else
7345 /* Normal rx_bd entry. */
7346 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8498 idx, rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo);
8499 else
8500 /* Normal rx_bd entry. */
8501 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
7347 "flags = 0x%08X\n", idx,
8502 "flags = 0x%08X\n", idx,
7348 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
7349 rxbd->rx_bd_len, rxbd->rx_bd_flags);
7350}
7351
7352
7353#ifdef BCE_USE_SPLIT_HEADER
7354/****************************************************************************/
7355/* Prints out a rx_bd structure in the page chain. */
7356/* */
7357/* Returns: */
7358/* Nothing. */
7359/****************************************************************************/
8503 rxbd->rx_bd_haddr_hi, rxbd->rx_bd_haddr_lo,
8504 rxbd->rx_bd_len, rxbd->rx_bd_flags);
8505}
8506
8507
8508#ifdef BCE_USE_SPLIT_HEADER
8509/****************************************************************************/
8510/* Prints out a rx_bd structure in the page chain. */
8511/* */
8512/* Returns: */
8513/* Nothing. */
8514/****************************************************************************/
7360static void
8515static __attribute__ ((noinline)) void
7361bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
7362{
7363 if (idx > MAX_PG_BD)
7364 /* Index out of range. */
7365 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
7366 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
7367 /* Page Chain page pointer. */
8516bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
8517{
8518 if (idx > MAX_PG_BD)
8519 /* Index out of range. */
8520 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
8521 else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
8522 /* Page Chain page pointer. */
7368 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
8523 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
7369 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
7370 else
7371 /* Normal rx_bd entry. */
7372 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
8524 idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
8525 else
8526 /* Normal rx_bd entry. */
8527 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
7373 "flags = 0x%08X\n", idx,
8528 "flags = 0x%08X\n", idx,
7374 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
7375 pgbd->rx_bd_len, pgbd->rx_bd_flags);
7376}
7377#endif
7378
7379
7380/****************************************************************************/
7381/* Prints out a l2_fhdr structure. */
7382/* */
7383/* Returns: */
7384/* Nothing. */
7385/****************************************************************************/
8529 pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
8530 pgbd->rx_bd_len, pgbd->rx_bd_flags);
8531}
8532#endif
8533
8534
8535/****************************************************************************/
8536/* Prints out a l2_fhdr structure. */
8537/* */
8538/* Returns: */
8539/* Nothing. */
8540/****************************************************************************/
7386static void
8541static __attribute__ ((noinline)) void
7387bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
7388{
7389 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
7390 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
7391 "tcp_udp_xsum = 0x%04X\n", idx,
8542bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
8543{
8544 BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
8545 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
8546 "tcp_udp_xsum = 0x%04X\n", idx,
7392 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
7393 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
8547 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
8548 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
7394 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
7395}
7396
7397
7398/****************************************************************************/
8549 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
8550}
8551
8552
8553/****************************************************************************/
7399/* Prints out the L2 context memory. (Only useful for CID 0 to 15. ) */
8554/* Prints out context memory info. (Only useful for CID 0 to 16.) */
7400/* */
7401/* Returns: */
7402/* Nothing. */
7403/****************************************************************************/
8555/* */
8556/* Returns: */
8557/* Nothing. */
8558/****************************************************************************/
7404static void
8559static __attribute__ ((noinline)) void
7405bce_dump_ctx(struct bce_softc *sc, u16 cid)
7406{
8560bce_dump_ctx(struct bce_softc *sc, u16 cid)
8561{
7407 if (cid < TX_CID) {
8562 if (cid <= TX_CID) {
7408 BCE_PRINTF(
7409 "----------------------------"
7410 " CTX Data "
7411 "----------------------------\n");
7412
7413 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
8563 BCE_PRINTF(
8564 "----------------------------"
8565 " CTX Data "
8566 "----------------------------\n");
8567
8568 BCE_PRINTF(" 0x%04X - (CID) Context ID\n", cid);
7414 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BDIDX) host rx producer index\n",
7415 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BDIDX));
7416 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BSEQ) host byte sequence\n",
7417 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BSEQ));
7418 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BSEQ) h/w byte sequence\n",
7419 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BSEQ));
7420 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_HI) h/w buffer descriptor address\n",
7421 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_HI));
7422 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_LO) h/w buffer descriptor address\n",
7423 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_LO));
7424 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDIDX) h/w rx consumer index\n",
7425 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDIDX));
7426 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_PG_BDIDX) host page producer index\n",
7427 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_PG_BDIDX));
7428 BCE_PRINTF(" 0x%08X - (L2CTX_PG_BUF_SIZE) host rx_bd/page buffer size\n",
7429 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_PG_BUF_SIZE));
7430 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_HI) h/w page chain address\n",
7431 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_HI));
7432 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_LO) h/w page chain address\n",
7433 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_LO));
7434 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDIDX) h/w page consumer index\n",
7435 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDIDX));
7436
8569
8570 if (cid == RX_CID) {
8571 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BDIDX) host rx producer index\n",
8572 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BDIDX));
8573 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_BSEQ) host byte sequence\n",
8574 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_BSEQ));
8575 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BSEQ) h/w byte sequence\n",
8576 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BSEQ));
8577 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_HI) h/w buffer descriptor address\n",
8578 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_HI));
8579 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDHADDR_LO) h/w buffer descriptor address\n",
8580 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDHADDR_LO));
8581 BCE_PRINTF(" 0x%08X - (L2CTX_NX_BDIDX) h/w rx consumer index\n",
8582 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_BDIDX));
8583 BCE_PRINTF(" 0x%08X - (L2CTX_HOST_PG_BDIDX) host page producer index\n",
8584 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_HOST_PG_BDIDX));
8585 BCE_PRINTF(" 0x%08X - (L2CTX_PG_BUF_SIZE) host rx_bd/page buffer size\n",
8586 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_PG_BUF_SIZE));
8587 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_HI) h/w page chain address\n",
8588 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_HI));
8589 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDHADDR_LO) h/w page chain address\n",
8590 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDHADDR_LO));
8591 BCE_PRINTF(" 0x%08X - (L2CTX_NX_PG_BDIDX) h/w page consumer index\n",
8592 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_NX_PG_BDIDX));
8593 } else if (cid == TX_CID) {
8594 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
8595 BCE_PRINTF(" 0x%08X - (L2CTX_TYPE_XI) ctx type\n",
8596 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TYPE_XI));
8597 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TYPE_XI) ctx cmd\n",
8598 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_CMD_TYPE_XI));
8599 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BDHADDR_HI_XI) h/w buffer descriptor address\n",
8600 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_HI_XI));
8601 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BHADDR_LO_XI) h/w buffer descriptor address\n",
8602 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_LO_XI));
8603 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) host producer index\n",
8604 CTX_RD(sc, GET_CID_ADDR(cid), 0x240));
8605 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) host byte sequence\n",
8606 CTX_RD(sc, GET_CID_ADDR(cid), 0x248));
8607 } else {
8608 BCE_PRINTF(" 0x%08X - (L2CTX_TYPE_TYPE_L2) ctx type\n",
8609 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TYPE_TYPE_L2));
8610 BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TYPE_TYPE_L2) ctx cmd\n",
8611 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_CMD_TYPE_TYPE_L2));
8612 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BDHADDR_HI) h/w buffer descriptor address\n",
8613 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_HI));
8614 BCE_PRINTF(" 0x%08X - (L2CTX_TBDR_BHADDR_LO) h/w buffer descriptor address\n",
8615 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TBDR_BHADDR_LO));
8616 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host producer index\n",
8617 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_HOST_BIDX));
8618 BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte sequence\n",
8619 CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_HOST_BSEQ));
8620 }
8621 } else
8622 BCE_PRINTF(" Unknown CID\n");
8623
7437 BCE_PRINTF(
7438 "----------------------------"
8624 BCE_PRINTF(
8625 "----------------------------"
8626 " Raw CTX "
8627 "----------------------------\n");
8628
8629 for (int i = 0x0; i < 0x300; i += 0x10) {
8630 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
8631 i,
8632 CTX_RD(sc, GET_CID_ADDR(cid), i),
8633 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
8634 CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
8635 CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
8636 }
8637
8638
8639 BCE_PRINTF(
8640 "----------------------------"
7439 "----------------"
7440 "----------------------------\n");
7441 }
7442}
7443
7444
7445/****************************************************************************/
7446/* Prints out the FTQ data. */
7447/* */
7448/* Returns: */
7449/* Nothing. */
7450/****************************************************************************/
8641 "----------------"
8642 "----------------------------\n");
8643 }
8644}
8645
8646
8647/****************************************************************************/
8648/* Prints out the FTQ data. */
8649/* */
8650/* Returns: */
8651/* Nothing. */
8652/****************************************************************************/
7451static void
8653static __attribute__ ((noinline)) void
7452bce_dump_ftqs(struct bce_softc *sc)
7453{
8654bce_dump_ftqs(struct bce_softc *sc)
8655{
7454 u32 cmd, ctl, cur_depth, max_depth, valid_cnt;
8656 u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
7455
7456 BCE_PRINTF(
7457 "----------------------------"
7458 " FTQ Data "
7459 "----------------------------\n");
7460
8657
8658 BCE_PRINTF(
8659 "----------------------------"
8660 " FTQ Data "
8661 "----------------------------\n");
8662
7461 BCE_PRINTF(" FTQ Command Control Depth_Now Max_Depth Valid_Cnt\n");
7462 BCE_PRINTF(" ----- ---------- ---------- ---------- ---------- ----------\n");
8663 BCE_PRINTF(" FTQ Command Control Depth_Now Max_Depth Valid_Cnt \n");
8664 BCE_PRINTF(" ------- ---------- ---------- ---------- ---------- ----------\n");
7463
7464 /* Setup the generic statistic counters for the FTQ valid count. */
8665
8666 /* Setup the generic statistic counters for the FTQ valid count. */
7465 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0,
7466 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
7467 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) |
7468 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) |
7469 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT)));
7470 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1,
7471 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
7472 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) |
7473 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) |
7474 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT)));
7475 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2,
7476 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
7477 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) |
7478 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
7479 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT)));
7480 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3,
7481 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
7482 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
7483 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
7484 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT)));
8667 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
8668 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT << 16) |
8669 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT << 8) |
8670 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
8671 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
7485
8672
8673 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT << 24) |
8674 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT << 16) |
8675 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT << 8) |
8676 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
8677 REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
7486
8678
8679 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT << 24) |
8680 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT << 16) |
8681 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
8682 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
8683 REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
8684
8685 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
8686 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
8687 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
8688 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
8689 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
8690
7487 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
7488 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
7489 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
7490 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
7491 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
8691 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
8692 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
8693 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
8694 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
8695 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7492 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8696 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7493 cmd, ctl, cur_depth, max_depth, valid_cnt);
7494
7495 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
7496 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
7497 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
7498 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
7499 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
8697 cmd, ctl, cur_depth, max_depth, valid_cnt);
8698
8699 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
8700 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
8701 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
8702 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
8703 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7500 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8704 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7501 cmd, ctl, cur_depth, max_depth, valid_cnt);
7502
7503 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
7504 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
7505 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
7506 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
7507 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
8705 cmd, ctl, cur_depth, max_depth, valid_cnt);
8706
8707 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
8708 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
8709 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
8710 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
8711 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7508 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8712 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7509 cmd, ctl, cur_depth, max_depth, valid_cnt);
7510
7511 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
7512 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
7513 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
7514 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
7515 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
8713 cmd, ctl, cur_depth, max_depth, valid_cnt);
8714
8715 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
8716 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
8717 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
8718 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
8719 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
7516 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8720 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7517 cmd, ctl, cur_depth, max_depth, valid_cnt);
7518
7519 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
7520 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
7521 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
7522 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
7523 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
8721 cmd, ctl, cur_depth, max_depth, valid_cnt);
8722
8723 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
8724 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
8725 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
8726 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
8727 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
7524 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8728 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7525 cmd, ctl, cur_depth, max_depth, valid_cnt);
7526
7527 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
7528 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
7529 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
7530 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
7531 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
8729 cmd, ctl, cur_depth, max_depth, valid_cnt);
8730
8731 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
8732 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
8733 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
8734 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
8735 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
7532 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8736 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7533 cmd, ctl, cur_depth, max_depth, valid_cnt);
7534
7535 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
7536 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
7537 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
7538 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
7539 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
8737 cmd, ctl, cur_depth, max_depth, valid_cnt);
8738
8739 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
8740 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
8741 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
8742 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
8743 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
7540 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8744 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7541 cmd, ctl, cur_depth, max_depth, valid_cnt);
7542
7543 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
7544 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
7545 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
7546 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
7547 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
8745 cmd, ctl, cur_depth, max_depth, valid_cnt);
8746
8747 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
8748 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
8749 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
8750 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
8751 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
7548 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8752 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7549 cmd, ctl, cur_depth, max_depth, valid_cnt);
7550
7551 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
7552 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
7553 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
7554 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
7555 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
8753 cmd, ctl, cur_depth, max_depth, valid_cnt);
8754
8755 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
8756 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
8757 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
8758 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
8759 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
7556 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8760 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7557 cmd, ctl, cur_depth, max_depth, valid_cnt);
7558
7559 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
7560 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
7561 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
7562 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
7563 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
8761 cmd, ctl, cur_depth, max_depth, valid_cnt);
8762
8763 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
8764 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
8765 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
8766 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
8767 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
7564 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8768 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7565 cmd, ctl, cur_depth, max_depth, valid_cnt);
7566
7567 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
7568 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
7569 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
7570 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
7571 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
8769 cmd, ctl, cur_depth, max_depth, valid_cnt);
8770
8771 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
8772 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
8773 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
8774 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
8775 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
7572 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8776 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7573 cmd, ctl, cur_depth, max_depth, valid_cnt);
7574
8777 cmd, ctl, cur_depth, max_depth, valid_cnt);
8778
7575
7576 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
7577 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
7578 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
7579 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
7580 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
8779 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
8780 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
8781 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
8782 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
8783 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
7581 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8784 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7582 cmd, ctl, cur_depth, max_depth, valid_cnt);
7583
7584 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
7585 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
7586 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
7587 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
7588 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
8785 cmd, ctl, cur_depth, max_depth, valid_cnt);
8786
8787 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
8788 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
8789 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
8790 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
8791 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
7589 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8792 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7590 cmd, ctl, cur_depth, max_depth, valid_cnt);
7591
7592 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
7593 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
7594 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
7595 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
7596 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
8793 cmd, ctl, cur_depth, max_depth, valid_cnt);
8794
8795 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
8796 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
8797 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
8798 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
8799 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
7597 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8800 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7598 cmd, ctl, cur_depth, max_depth, valid_cnt);
7599
7600 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
7601 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
7602 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
7603 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
7604 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
8801 cmd, ctl, cur_depth, max_depth, valid_cnt);
8802
8803 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
8804 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
8805 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
8806 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
8807 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
7605 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8808 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7606 cmd, ctl, cur_depth, max_depth, valid_cnt);
7607
7608 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
7609 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
7610 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
7611 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
7612 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
8809 cmd, ctl, cur_depth, max_depth, valid_cnt);
8810
8811 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
8812 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
8813 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
8814 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
8815 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
7613 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8816 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7614 cmd, ctl, cur_depth, max_depth, valid_cnt);
7615
7616 /* Setup the generic statistic counters for the FTQ valid count. */
8817 cmd, ctl, cur_depth, max_depth, valid_cnt);
8818
8819 /* Setup the generic statistic counters for the FTQ valid count. */
7617 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0,
7618 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
7619 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
7620 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT)));
8820 val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
8821 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
8822 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
7621
8823
8824 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
8825 val = val | (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI << 24);
8826 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
8827
7622 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
7623 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
7624 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
7625 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
7626 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
8828 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
8829 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
8830 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
8831 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
8832 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7627 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8833 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7628 cmd, ctl, cur_depth, max_depth, valid_cnt);
7629
7630 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
7631 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
7632 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
7633 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
7634 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
8834 cmd, ctl, cur_depth, max_depth, valid_cnt);
8835
8836 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
8837 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
8838 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
8839 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
8840 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7635 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8841 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7636 cmd, ctl, cur_depth, max_depth, valid_cnt);
7637
7638 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
7639 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
7640 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
7641 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
7642 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
8842 cmd, ctl, cur_depth, max_depth, valid_cnt);
8843
8844 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
8845 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
8846 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
8847 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
8848 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7643 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8849 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7644 cmd, ctl, cur_depth, max_depth, valid_cnt);
7645
8850 cmd, ctl, cur_depth, max_depth, valid_cnt);
8851
8852 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
8853 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
8854 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
8855 cur_depth = (ctl & 0xFFC00000) >> 22;
8856 max_depth = (ctl & 0x003FF000) >> 12;
8857 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
8858 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
8859 cmd, ctl, cur_depth, max_depth, valid_cnt);
8860 }
8861
7646 BCE_PRINTF(
7647 "----------------------------"
7648 "----------------"
7649 "----------------------------\n");
7650}
7651
7652
7653/****************************************************************************/
7654/* Prints out the TX chain. */
7655/* */
7656/* Returns: */
7657/* Nothing. */
7658/****************************************************************************/
8862 BCE_PRINTF(
8863 "----------------------------"
8864 "----------------"
8865 "----------------------------\n");
8866}
8867
8868
8869/****************************************************************************/
8870/* Prints out the TX chain. */
8871/* */
8872/* Returns: */
8873/* Nothing. */
8874/****************************************************************************/
7659static void
8875static __attribute__ ((noinline)) void
7660bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
7661{
7662 struct tx_bd *txbd;
7663
7664 /* First some info about the tx_bd chain structure. */
7665 BCE_PRINTF(
7666 "----------------------------"
7667 " tx_bd chain "

--- 27 unchanged lines hidden (view full) ---

7695
7696
7697/****************************************************************************/
7698/* Prints out the RX chain. */
7699/* */
7700/* Returns: */
7701/* Nothing. */
7702/****************************************************************************/
8876bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
8877{
8878 struct tx_bd *txbd;
8879
8880 /* First some info about the tx_bd chain structure. */
8881 BCE_PRINTF(
8882 "----------------------------"
8883 " tx_bd chain "

--- 27 unchanged lines hidden (view full) ---

8911
8912
8913/****************************************************************************/
8914/* Prints out the RX chain. */
8915/* */
8916/* Returns: */
8917/* Nothing. */
8918/****************************************************************************/
7703static void
8919static __attribute__ ((noinline)) void
7704bce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count)
7705{
7706 struct rx_bd *rxbd;
7707
7708 /* First some info about the rx_bd chain structure. */
7709 BCE_PRINTF(
7710 "----------------------------"
7711 " rx_bd chain "

--- 28 unchanged lines hidden (view full) ---

7740
7741#ifdef BCE_USE_SPLIT_HEADER
7742/****************************************************************************/
7743/* Prints out the page chain. */
7744/* */
7745/* Returns: */
7746/* Nothing. */
7747/****************************************************************************/
8920bce_dump_rx_chain(struct bce_softc *sc, u16 rx_prod, int count)
8921{
8922 struct rx_bd *rxbd;
8923
8924 /* First some info about the rx_bd chain structure. */
8925 BCE_PRINTF(
8926 "----------------------------"
8927 " rx_bd chain "

--- 28 unchanged lines hidden (view full) ---

8956
8957#ifdef BCE_USE_SPLIT_HEADER
8958/****************************************************************************/
8959/* Prints out the page chain. */
8960/* */
8961/* Returns: */
8962/* Nothing. */
8963/****************************************************************************/
7748static void
8964static __attribute__ ((noinline)) void
7749bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
7750{
7751 struct rx_bd *pgbd;
7752
7753 /* First some info about the page chain structure. */
7754 BCE_PRINTF(
7755 "----------------------------"
7756 " page chain "

--- 29 unchanged lines hidden (view full) ---

7786
7787
7788/****************************************************************************/
7789/* Prints out the status block from host memory. */
7790/* */
7791/* Returns: */
7792/* Nothing. */
7793/****************************************************************************/
8965bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
8966{
8967 struct rx_bd *pgbd;
8968
8969 /* First some info about the page chain structure. */
8970 BCE_PRINTF(
8971 "----------------------------"
8972 " page chain "

--- 29 unchanged lines hidden (view full) ---

9002
9003
9004/****************************************************************************/
9005/* Prints out the status block from host memory. */
9006/* */
9007/* Returns: */
9008/* Nothing. */
9009/****************************************************************************/
7794static void
9010static __attribute__ ((noinline)) void
7795bce_dump_status_block(struct bce_softc *sc)
7796{
7797 struct status_block *sblk;
7798
7799 sblk = sc->status_block;
7800
7801 BCE_PRINTF(
7802 "----------------------------"
7803 " Status Block "
7804 "----------------------------\n");
7805
7806 BCE_PRINTF(" 0x%08X - attn_bits\n",
7807 sblk->status_attn_bits);
7808
7809 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
7810 sblk->status_attn_bits_ack);
7811
7812 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n",
9011bce_dump_status_block(struct bce_softc *sc)
9012{
9013 struct status_block *sblk;
9014
9015 sblk = sc->status_block;
9016
9017 BCE_PRINTF(
9018 "----------------------------"
9019 " Status Block "
9020 "----------------------------\n");
9021
9022 BCE_PRINTF(" 0x%08X - attn_bits\n",
9023 sblk->status_attn_bits);
9024
9025 BCE_PRINTF(" 0x%08X - attn_bits_ack\n",
9026 sblk->status_attn_bits_ack);
9027
9028 BCE_PRINTF("0x%04X(0x%04X) - rx_cons0\n",
7813 sblk->status_rx_quick_consumer_index0,
9029 sblk->status_rx_quick_consumer_index0,
7814 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
7815
7816 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n",
9030 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index0));
9031
9032 BCE_PRINTF("0x%04X(0x%04X) - tx_cons0\n",
7817 sblk->status_tx_quick_consumer_index0,
9033 sblk->status_tx_quick_consumer_index0,
7818 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
7819
7820 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
7821
7822 /* Theses indices are not used for normal L2 drivers. */
7823 if (sblk->status_rx_quick_consumer_index1)
7824 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n",
7825 sblk->status_rx_quick_consumer_index1,

--- 19 unchanged lines hidden (view full) ---

7845 sblk->status_rx_quick_consumer_index3,
7846 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
7847
7848 if (sblk->status_tx_quick_consumer_index3)
7849 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n",
7850 sblk->status_tx_quick_consumer_index3,
7851 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
7852
9034 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index0));
9035
9036 BCE_PRINTF(" 0x%04X - status_idx\n", sblk->status_idx);
9037
9038 /* Theses indices are not used for normal L2 drivers. */
9039 if (sblk->status_rx_quick_consumer_index1)
9040 BCE_PRINTF("0x%04X(0x%04X) - rx_cons1\n",
9041 sblk->status_rx_quick_consumer_index1,

--- 19 unchanged lines hidden (view full) ---

9061 sblk->status_rx_quick_consumer_index3,
9062 (u16) RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index3));
9063
9064 if (sblk->status_tx_quick_consumer_index3)
9065 BCE_PRINTF("0x%04X(0x%04X) - tx_cons3\n",
9066 sblk->status_tx_quick_consumer_index3,
9067 (u16) TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index3));
9068
7853 if (sblk->status_rx_quick_consumer_index4 ||
9069 if (sblk->status_rx_quick_consumer_index4 ||
7854 sblk->status_rx_quick_consumer_index5)
7855 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
7856 sblk->status_rx_quick_consumer_index4,
7857 sblk->status_rx_quick_consumer_index5);
7858
9070 sblk->status_rx_quick_consumer_index5)
9071 BCE_PRINTF("rx_cons4 = 0x%08X, rx_cons5 = 0x%08X\n",
9072 sblk->status_rx_quick_consumer_index4,
9073 sblk->status_rx_quick_consumer_index5);
9074
7859 if (sblk->status_rx_quick_consumer_index6 ||
9075 if (sblk->status_rx_quick_consumer_index6 ||
7860 sblk->status_rx_quick_consumer_index7)
7861 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
7862 sblk->status_rx_quick_consumer_index6,
7863 sblk->status_rx_quick_consumer_index7);
7864
9076 sblk->status_rx_quick_consumer_index7)
9077 BCE_PRINTF("rx_cons6 = 0x%08X, rx_cons7 = 0x%08X\n",
9078 sblk->status_rx_quick_consumer_index6,
9079 sblk->status_rx_quick_consumer_index7);
9080
7865 if (sblk->status_rx_quick_consumer_index8 ||
9081 if (sblk->status_rx_quick_consumer_index8 ||
7866 sblk->status_rx_quick_consumer_index9)
7867 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
7868 sblk->status_rx_quick_consumer_index8,
7869 sblk->status_rx_quick_consumer_index9);
7870
9082 sblk->status_rx_quick_consumer_index9)
9083 BCE_PRINTF("rx_cons8 = 0x%08X, rx_cons9 = 0x%08X\n",
9084 sblk->status_rx_quick_consumer_index8,
9085 sblk->status_rx_quick_consumer_index9);
9086
7871 if (sblk->status_rx_quick_consumer_index10 ||
9087 if (sblk->status_rx_quick_consumer_index10 ||
7872 sblk->status_rx_quick_consumer_index11)
7873 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
7874 sblk->status_rx_quick_consumer_index10,
7875 sblk->status_rx_quick_consumer_index11);
7876
9088 sblk->status_rx_quick_consumer_index11)
9089 BCE_PRINTF("rx_cons10 = 0x%08X, rx_cons11 = 0x%08X\n",
9090 sblk->status_rx_quick_consumer_index10,
9091 sblk->status_rx_quick_consumer_index11);
9092
7877 if (sblk->status_rx_quick_consumer_index12 ||
9093 if (sblk->status_rx_quick_consumer_index12 ||
7878 sblk->status_rx_quick_consumer_index13)
7879 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
7880 sblk->status_rx_quick_consumer_index12,
7881 sblk->status_rx_quick_consumer_index13);
7882
9094 sblk->status_rx_quick_consumer_index13)
9095 BCE_PRINTF("rx_cons12 = 0x%08X, rx_cons13 = 0x%08X\n",
9096 sblk->status_rx_quick_consumer_index12,
9097 sblk->status_rx_quick_consumer_index13);
9098
7883 if (sblk->status_rx_quick_consumer_index14 ||
9099 if (sblk->status_rx_quick_consumer_index14 ||
7884 sblk->status_rx_quick_consumer_index15)
7885 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
7886 sblk->status_rx_quick_consumer_index14,
7887 sblk->status_rx_quick_consumer_index15);
7888
9100 sblk->status_rx_quick_consumer_index15)
9101 BCE_PRINTF("rx_cons14 = 0x%08X, rx_cons15 = 0x%08X\n",
9102 sblk->status_rx_quick_consumer_index14,
9103 sblk->status_rx_quick_consumer_index15);
9104
7889 if (sblk->status_completion_producer_index ||
9105 if (sblk->status_completion_producer_index ||
7890 sblk->status_cmd_consumer_index)
7891 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
7892 sblk->status_completion_producer_index,
7893 sblk->status_cmd_consumer_index);
7894
7895 BCE_PRINTF(
7896 "----------------------------"
7897 "----------------"
7898 "----------------------------\n");
7899}
7900
7901
7902/****************************************************************************/
7903/* Prints out the statistics block from host memory. */
7904/* */
7905/* Returns: */
7906/* Nothing. */
7907/****************************************************************************/
9106 sblk->status_cmd_consumer_index)
9107 BCE_PRINTF("com_prod = 0x%08X, cmd_cons = 0x%08X\n",
9108 sblk->status_completion_producer_index,
9109 sblk->status_cmd_consumer_index);
9110
9111 BCE_PRINTF(
9112 "----------------------------"
9113 "----------------"
9114 "----------------------------\n");
9115}
9116
9117
9118/****************************************************************************/
9119/* Prints out the statistics block from host memory. */
9120/* */
9121/* Returns: */
9122/* Nothing. */
9123/****************************************************************************/
7908static void
9124static __attribute__ ((noinline)) void
7909bce_dump_stats_block(struct bce_softc *sc)
7910{
7911 struct statistics_block *sblk;
7912
7913 sblk = sc->stats_block;
7914
7915 BCE_PRINTF(
7916 "---------------"
7917 " Stats Block (All Stats Not Shown Are 0) "
7918 "---------------\n");
7919
9125bce_dump_stats_block(struct bce_softc *sc)
9126{
9127 struct statistics_block *sblk;
9128
9129 sblk = sc->stats_block;
9130
9131 BCE_PRINTF(
9132 "---------------"
9133 " Stats Block (All Stats Not Shown Are 0) "
9134 "---------------\n");
9135
7920 if (sblk->stat_IfHCInOctets_hi
9136 if (sblk->stat_IfHCInOctets_hi
7921 || sblk->stat_IfHCInOctets_lo)
7922 BCE_PRINTF("0x%08X:%08X : "
9137 || sblk->stat_IfHCInOctets_lo)
9138 BCE_PRINTF("0x%08X:%08X : "
7923 "IfHcInOctets\n",
7924 sblk->stat_IfHCInOctets_hi,
9139 "IfHcInOctets\n",
9140 sblk->stat_IfHCInOctets_hi,
7925 sblk->stat_IfHCInOctets_lo);
7926
9141 sblk->stat_IfHCInOctets_lo);
9142
7927 if (sblk->stat_IfHCInBadOctets_hi
9143 if (sblk->stat_IfHCInBadOctets_hi
7928 || sblk->stat_IfHCInBadOctets_lo)
7929 BCE_PRINTF("0x%08X:%08X : "
9144 || sblk->stat_IfHCInBadOctets_lo)
9145 BCE_PRINTF("0x%08X:%08X : "
7930 "IfHcInBadOctets\n",
7931 sblk->stat_IfHCInBadOctets_hi,
9146 "IfHcInBadOctets\n",
9147 sblk->stat_IfHCInBadOctets_hi,
7932 sblk->stat_IfHCInBadOctets_lo);
7933
9148 sblk->stat_IfHCInBadOctets_lo);
9149
7934 if (sblk->stat_IfHCOutOctets_hi
9150 if (sblk->stat_IfHCOutOctets_hi
7935 || sblk->stat_IfHCOutOctets_lo)
7936 BCE_PRINTF("0x%08X:%08X : "
9151 || sblk->stat_IfHCOutOctets_lo)
9152 BCE_PRINTF("0x%08X:%08X : "
7937 "IfHcOutOctets\n",
7938 sblk->stat_IfHCOutOctets_hi,
9153 "IfHcOutOctets\n",
9154 sblk->stat_IfHCOutOctets_hi,
7939 sblk->stat_IfHCOutOctets_lo);
7940
9155 sblk->stat_IfHCOutOctets_lo);
9156
7941 if (sblk->stat_IfHCOutBadOctets_hi
9157 if (sblk->stat_IfHCOutBadOctets_hi
7942 || sblk->stat_IfHCOutBadOctets_lo)
7943 BCE_PRINTF("0x%08X:%08X : "
9158 || sblk->stat_IfHCOutBadOctets_lo)
9159 BCE_PRINTF("0x%08X:%08X : "
7944 "IfHcOutBadOctets\n",
7945 sblk->stat_IfHCOutBadOctets_hi,
9160 "IfHcOutBadOctets\n",
9161 sblk->stat_IfHCOutBadOctets_hi,
7946 sblk->stat_IfHCOutBadOctets_lo);
7947
9162 sblk->stat_IfHCOutBadOctets_lo);
9163
7948 if (sblk->stat_IfHCInUcastPkts_hi
9164 if (sblk->stat_IfHCInUcastPkts_hi
7949 || sblk->stat_IfHCInUcastPkts_lo)
7950 BCE_PRINTF("0x%08X:%08X : "
9165 || sblk->stat_IfHCInUcastPkts_lo)
9166 BCE_PRINTF("0x%08X:%08X : "
7951 "IfHcInUcastPkts\n",
7952 sblk->stat_IfHCInUcastPkts_hi,
9167 "IfHcInUcastPkts\n",
9168 sblk->stat_IfHCInUcastPkts_hi,
7953 sblk->stat_IfHCInUcastPkts_lo);
7954
9169 sblk->stat_IfHCInUcastPkts_lo);
9170
7955 if (sblk->stat_IfHCInBroadcastPkts_hi
9171 if (sblk->stat_IfHCInBroadcastPkts_hi
7956 || sblk->stat_IfHCInBroadcastPkts_lo)
7957 BCE_PRINTF("0x%08X:%08X : "
9172 || sblk->stat_IfHCInBroadcastPkts_lo)
9173 BCE_PRINTF("0x%08X:%08X : "
7958 "IfHcInBroadcastPkts\n",
7959 sblk->stat_IfHCInBroadcastPkts_hi,
9174 "IfHcInBroadcastPkts\n",
9175 sblk->stat_IfHCInBroadcastPkts_hi,
7960 sblk->stat_IfHCInBroadcastPkts_lo);
7961
9176 sblk->stat_IfHCInBroadcastPkts_lo);
9177
7962 if (sblk->stat_IfHCInMulticastPkts_hi
9178 if (sblk->stat_IfHCInMulticastPkts_hi
7963 || sblk->stat_IfHCInMulticastPkts_lo)
7964 BCE_PRINTF("0x%08X:%08X : "
9179 || sblk->stat_IfHCInMulticastPkts_lo)
9180 BCE_PRINTF("0x%08X:%08X : "
7965 "IfHcInMulticastPkts\n",
7966 sblk->stat_IfHCInMulticastPkts_hi,
9181 "IfHcInMulticastPkts\n",
9182 sblk->stat_IfHCInMulticastPkts_hi,
7967 sblk->stat_IfHCInMulticastPkts_lo);
7968
9183 sblk->stat_IfHCInMulticastPkts_lo);
9184
7969 if (sblk->stat_IfHCOutUcastPkts_hi
9185 if (sblk->stat_IfHCOutUcastPkts_hi
7970 || sblk->stat_IfHCOutUcastPkts_lo)
7971 BCE_PRINTF("0x%08X:%08X : "
9186 || sblk->stat_IfHCOutUcastPkts_lo)
9187 BCE_PRINTF("0x%08X:%08X : "
7972 "IfHcOutUcastPkts\n",
7973 sblk->stat_IfHCOutUcastPkts_hi,
9188 "IfHcOutUcastPkts\n",
9189 sblk->stat_IfHCOutUcastPkts_hi,
7974 sblk->stat_IfHCOutUcastPkts_lo);
7975
9190 sblk->stat_IfHCOutUcastPkts_lo);
9191
7976 if (sblk->stat_IfHCOutBroadcastPkts_hi
9192 if (sblk->stat_IfHCOutBroadcastPkts_hi
7977 || sblk->stat_IfHCOutBroadcastPkts_lo)
7978 BCE_PRINTF("0x%08X:%08X : "
9193 || sblk->stat_IfHCOutBroadcastPkts_lo)
9194 BCE_PRINTF("0x%08X:%08X : "
7979 "IfHcOutBroadcastPkts\n",
7980 sblk->stat_IfHCOutBroadcastPkts_hi,
9195 "IfHcOutBroadcastPkts\n",
9196 sblk->stat_IfHCOutBroadcastPkts_hi,
7981 sblk->stat_IfHCOutBroadcastPkts_lo);
7982
9197 sblk->stat_IfHCOutBroadcastPkts_lo);
9198
7983 if (sblk->stat_IfHCOutMulticastPkts_hi
9199 if (sblk->stat_IfHCOutMulticastPkts_hi
7984 || sblk->stat_IfHCOutMulticastPkts_lo)
7985 BCE_PRINTF("0x%08X:%08X : "
9200 || sblk->stat_IfHCOutMulticastPkts_lo)
9201 BCE_PRINTF("0x%08X:%08X : "
7986 "IfHcOutMulticastPkts\n",
7987 sblk->stat_IfHCOutMulticastPkts_hi,
9202 "IfHcOutMulticastPkts\n",
9203 sblk->stat_IfHCOutMulticastPkts_hi,
7988 sblk->stat_IfHCOutMulticastPkts_lo);
7989
7990 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors)
7991 BCE_PRINTF(" 0x%08X : "
9204 sblk->stat_IfHCOutMulticastPkts_lo);
9205
9206 if (sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors)
9207 BCE_PRINTF(" 0x%08X : "
7992 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
9208 "emac_tx_stat_dot3statsinternalmactransmiterrors\n",
7993 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
7994
7995 if (sblk->stat_Dot3StatsCarrierSenseErrors)
7996 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n",
7997 sblk->stat_Dot3StatsCarrierSenseErrors);
7998
7999 if (sblk->stat_Dot3StatsFCSErrors)
8000 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n",

--- 5 unchanged lines hidden (view full) ---

8006
8007 if (sblk->stat_Dot3StatsSingleCollisionFrames)
8008 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n",
8009 sblk->stat_Dot3StatsSingleCollisionFrames);
8010
8011 if (sblk->stat_Dot3StatsMultipleCollisionFrames)
8012 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n",
8013 sblk->stat_Dot3StatsMultipleCollisionFrames);
9209 sblk->stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
9210
9211 if (sblk->stat_Dot3StatsCarrierSenseErrors)
9212 BCE_PRINTF(" 0x%08X : Dot3StatsCarrierSenseErrors\n",
9213 sblk->stat_Dot3StatsCarrierSenseErrors);
9214
9215 if (sblk->stat_Dot3StatsFCSErrors)
9216 BCE_PRINTF(" 0x%08X : Dot3StatsFCSErrors\n",

--- 5 unchanged lines hidden (view full) ---

9222
9223 if (sblk->stat_Dot3StatsSingleCollisionFrames)
9224 BCE_PRINTF(" 0x%08X : Dot3StatsSingleCollisionFrames\n",
9225 sblk->stat_Dot3StatsSingleCollisionFrames);
9226
9227 if (sblk->stat_Dot3StatsMultipleCollisionFrames)
9228 BCE_PRINTF(" 0x%08X : Dot3StatsMultipleCollisionFrames\n",
9229 sblk->stat_Dot3StatsMultipleCollisionFrames);
8014
9230
8015 if (sblk->stat_Dot3StatsDeferredTransmissions)
8016 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n",
8017 sblk->stat_Dot3StatsDeferredTransmissions);
8018
8019 if (sblk->stat_Dot3StatsExcessiveCollisions)
8020 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n",
8021 sblk->stat_Dot3StatsExcessiveCollisions);
8022
8023 if (sblk->stat_Dot3StatsLateCollisions)
8024 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n",
8025 sblk->stat_Dot3StatsLateCollisions);
8026
8027 if (sblk->stat_EtherStatsCollisions)
8028 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n",
8029 sblk->stat_EtherStatsCollisions);
8030
9231 if (sblk->stat_Dot3StatsDeferredTransmissions)
9232 BCE_PRINTF(" 0x%08X : Dot3StatsDeferredTransmissions\n",
9233 sblk->stat_Dot3StatsDeferredTransmissions);
9234
9235 if (sblk->stat_Dot3StatsExcessiveCollisions)
9236 BCE_PRINTF(" 0x%08X : Dot3StatsExcessiveCollisions\n",
9237 sblk->stat_Dot3StatsExcessiveCollisions);
9238
9239 if (sblk->stat_Dot3StatsLateCollisions)
9240 BCE_PRINTF(" 0x%08X : Dot3StatsLateCollisions\n",
9241 sblk->stat_Dot3StatsLateCollisions);
9242
9243 if (sblk->stat_EtherStatsCollisions)
9244 BCE_PRINTF(" 0x%08X : EtherStatsCollisions\n",
9245 sblk->stat_EtherStatsCollisions);
9246
8031 if (sblk->stat_EtherStatsFragments)
9247 if (sblk->stat_EtherStatsFragments)
8032 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n",
8033 sblk->stat_EtherStatsFragments);
8034
8035 if (sblk->stat_EtherStatsJabbers)
8036 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n",
8037 sblk->stat_EtherStatsJabbers);
8038
8039 if (sblk->stat_EtherStatsUndersizePkts)

--- 132 unchanged lines hidden (view full) ---

8172
8173
8174/****************************************************************************/
8175/* Prints out a summary of the driver state. */
8176/* */
8177/* Returns: */
8178/* Nothing. */
8179/****************************************************************************/
9248 BCE_PRINTF(" 0x%08X : EtherStatsFragments\n",
9249 sblk->stat_EtherStatsFragments);
9250
9251 if (sblk->stat_EtherStatsJabbers)
9252 BCE_PRINTF(" 0x%08X : EtherStatsJabbers\n",
9253 sblk->stat_EtherStatsJabbers);
9254
9255 if (sblk->stat_EtherStatsUndersizePkts)

--- 132 unchanged lines hidden (view full) ---

9388
9389
9390/****************************************************************************/
9391/* Prints out a summary of the driver state. */
9392/* */
9393/* Returns: */
9394/* Nothing. */
9395/****************************************************************************/
8180static void
9396static __attribute__ ((noinline)) void
8181bce_dump_driver_state(struct bce_softc *sc)
8182{
8183 u32 val_hi, val_lo;
8184
8185 BCE_PRINTF(
8186 "-----------------------------"
8187 " Driver State "
8188 "-----------------------------\n");

--- 41 unchanged lines hidden (view full) ---

8230 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
8231 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
8232 BCE_PRINTF(
8233 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n",
8234 val_hi, val_lo);
8235
8236 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
8237 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
9397bce_dump_driver_state(struct bce_softc *sc)
9398{
9399 u32 val_hi, val_lo;
9400
9401 BCE_PRINTF(
9402 "-----------------------------"
9403 " Driver State "
9404 "-----------------------------\n");

--- 41 unchanged lines hidden (view full) ---

9446 val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
9447 val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
9448 BCE_PRINTF(
9449 "0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain virtual address\n",
9450 val_hi, val_lo);
9451
9452 val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
9453 val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
8238 BCE_PRINTF(
9454 BCE_PRINTF(
8239 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n",
8240 val_hi, val_lo);
8241
8242#ifdef BCE_USE_SPLIT_HEADER
8243 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
8244 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
9455 "0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain virtual address\n",
9456 val_hi, val_lo);
9457
9458#ifdef BCE_USE_SPLIT_HEADER
9459 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
9460 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
8245 BCE_PRINTF(
9461 BCE_PRINTF(
8246 "0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n",
8247 val_hi, val_lo);
8248#endif
8249
8250 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n",
8251 sc->interrupts_generated);
9462 "0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain virtual address\n",
9463 val_hi, val_lo);
9464#endif
9465
9466 BCE_PRINTF(" 0x%08X - (sc->interrupts_generated) h/w intrs\n",
9467 sc->interrupts_generated);
8252
9468
8253 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n",
8254 sc->rx_interrupts);
8255
8256 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n",
8257 sc->tx_interrupts);
8258
8259 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n",
8260 sc->last_status_idx);

--- 51 unchanged lines hidden (view full) ---

8312 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) "
8313 "mbuf alloc failures\n",
8314 sc->mbuf_alloc_failed);
8315
8316 BCE_PRINTF(" 0x%08X - (sc->debug_mbuf_sim_alloc_failed) "
8317 "simulated mbuf alloc failures\n",
8318 sc->debug_mbuf_sim_alloc_failed);
8319
9469 BCE_PRINTF(" 0x%08X - (sc->rx_interrupts) rx interrupts handled\n",
9470 sc->rx_interrupts);
9471
9472 BCE_PRINTF(" 0x%08X - (sc->tx_interrupts) tx interrupts handled\n",
9473 sc->tx_interrupts);
9474
9475 BCE_PRINTF(" 0x%08X - (sc->last_status_idx) status block index\n",
9476 sc->last_status_idx);

--- 51 unchanged lines hidden (view full) ---

9528 BCE_PRINTF(" 0x%08X - (sc->mbuf_alloc_failed) "
9529 "mbuf alloc failures\n",
9530 sc->mbuf_alloc_failed);
9531
9532 BCE_PRINTF(" 0x%08X - (sc->debug_mbuf_sim_alloc_failed) "
9533 "simulated mbuf alloc failures\n",
9534 sc->debug_mbuf_sim_alloc_failed);
9535
9536 BCE_PRINTF(" 0x%08X - (sc->bce_flags) bce mac flags\n",
9537 sc->bce_flags);
9538
9539 BCE_PRINTF(" 0x%08X - (sc->bce_phy_flags) bce phy flags\n",
9540 sc->bce_phy_flags);
9541
8320 BCE_PRINTF(
8321 "----------------------------"
8322 "----------------"
8323 "----------------------------\n");
8324}
8325
8326
8327/****************************************************************************/
8328/* Prints out the hardware state through a summary of important register, */
8329/* followed by a complete register dump. */
8330/* */
8331/* Returns: */
8332/* Nothing. */
8333/****************************************************************************/
9542 BCE_PRINTF(
9543 "----------------------------"
9544 "----------------"
9545 "----------------------------\n");
9546}
9547
9548
9549/****************************************************************************/
9550/* Prints out the hardware state through a summary of important register, */
9551/* followed by a complete register dump. */
9552/* */
9553/* Returns: */
9554/* Nothing. */
9555/****************************************************************************/
8334static void
9556static __attribute__ ((noinline)) void
8335bce_dump_hw_state(struct bce_softc *sc)
8336{
8337 u32 val;
8338
8339 BCE_PRINTF(
8340 "----------------------------"
8341 " Hardware State "
8342 "----------------------------\n");

--- 47 unchanged lines hidden (view full) ---

8390 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE);
8391
8392 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
8393 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE);
8394
8395 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
8396 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE);
8397
9557bce_dump_hw_state(struct bce_softc *sc)
9558{
9559 u32 val;
9560
9561 BCE_PRINTF(
9562 "----------------------------"
9563 " Hardware State "
9564 "----------------------------\n");

--- 47 unchanged lines hidden (view full) ---

9612 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE);
9613
9614 val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
9615 BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n", val, BCE_MCP_CPU_STATE);
9616
9617 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
9618 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE);
9619
8398 BCE_PRINTF(
9620 BCE_PRINTF(
8399 "----------------------------"
8400 "----------------"
8401 "----------------------------\n");
8402
9621 "----------------------------"
9622 "----------------"
9623 "----------------------------\n");
9624
8403 BCE_PRINTF(
9625 BCE_PRINTF(
8404 "----------------------------"
8405 " Register Dump "
8406 "----------------------------\n");
8407
8408 for (int i = 0x400; i < 0x8000; i += 0x10) {
8409 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
8410 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
8411 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
8412 }
8413
9626 "----------------------------"
9627 " Register Dump "
9628 "----------------------------\n");
9629
9630 for (int i = 0x400; i < 0x8000; i += 0x10) {
9631 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9632 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
9633 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
9634 }
9635
8414 BCE_PRINTF(
9636 BCE_PRINTF(
8415 "----------------------------"
8416 "----------------"
8417 "----------------------------\n");
8418}
8419
8420
8421/****************************************************************************/
9637 "----------------------------"
9638 "----------------"
9639 "----------------------------\n");
9640}
9641
9642
9643/****************************************************************************/
9644/* Prints out the mailbox queue registers. */
9645/* */
9646/* Returns: */
9647/* Nothing. */
9648/****************************************************************************/
9649static __attribute__ ((noinline)) void
9650bce_dump_mq_regs(struct bce_softc *sc)
9651{
9652 BCE_PRINTF(
9653 "----------------------------"
9654 " MQ Regs "
9655 "----------------------------\n");
9656
9657 BCE_PRINTF(
9658 "----------------------------"
9659 "----------------"
9660 "----------------------------\n");
9661
9662 for (int i = 0x3c00; i < 0x4000; i += 0x10) {
9663 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9664 i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
9665 REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
9666 }
9667
9668 BCE_PRINTF(
9669 "----------------------------"
9670 "----------------"
9671 "----------------------------\n");
9672}
9673
9674
9675/****************************************************************************/
8422/* Prints out the bootcode state. */
8423/* */
8424/* Returns: */
8425/* Nothing. */
8426/****************************************************************************/
9676/* Prints out the bootcode state. */
9677/* */
9678/* Returns: */
9679/* Nothing. */
9680/****************************************************************************/
8427static void
9681static __attribute__ ((noinline)) void
8428bce_dump_bc_state(struct bce_softc *sc)
8429{
8430 u32 val;
8431
8432 BCE_PRINTF(
8433 "----------------------------"
8434 " Bootcode State "
8435 "----------------------------\n");

--- 11 unchanged lines hidden (view full) ---

8447 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION);
8448 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
8449 val, BCE_BC_CONDITION);
8450
8451 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD);
8452 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
8453 val, BCE_BC_STATE_DEBUG_CMD);
8454
9682bce_dump_bc_state(struct bce_softc *sc)
9683{
9684 u32 val;
9685
9686 BCE_PRINTF(
9687 "----------------------------"
9688 " Bootcode State "
9689 "----------------------------\n");

--- 11 unchanged lines hidden (view full) ---

9701 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_CONDITION);
9702 BCE_PRINTF("0x%08X - (0x%06X) condition\n",
9703 val, BCE_BC_CONDITION);
9704
9705 val = REG_RD_IND(sc, sc->bce_shmem_base + BCE_BC_STATE_DEBUG_CMD);
9706 BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
9707 val, BCE_BC_STATE_DEBUG_CMD);
9708
8455 BCE_PRINTF(
9709 BCE_PRINTF(
8456 "----------------------------"
8457 "----------------"
8458 "----------------------------\n");
8459}
8460
8461
8462/****************************************************************************/
9710 "----------------------------"
9711 "----------------"
9712 "----------------------------\n");
9713}
9714
9715
9716/****************************************************************************/
8463/* Prints out the TXP state. */
9717/* Prints out the TXP processor state. */
8464/* */
8465/* Returns: */
8466/* Nothing. */
8467/****************************************************************************/
9718/* */
9719/* Returns: */
9720/* Nothing. */
9721/****************************************************************************/
8468static void
8469bce_dump_txp_state(struct bce_softc *sc)
9722static __attribute__ ((noinline)) void
9723bce_dump_txp_state(struct bce_softc *sc, int regs)
8470{
9724{
8471 u32 val1;
9725 u32 val;
8472
8473 BCE_PRINTF(
8474 "----------------------------"
8475 " TXP State "
8476 "----------------------------\n");
8477
9726
9727 BCE_PRINTF(
9728 "----------------------------"
9729 " TXP State "
9730 "----------------------------\n");
9731
8478 val1 = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
8479 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val1, BCE_TXP_CPU_MODE);
9732 val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
9733 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n", val, BCE_TXP_CPU_MODE);
8480
9734
8481 val1 = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
8482 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val1, BCE_TXP_CPU_STATE);
9735 val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
9736 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n", val, BCE_TXP_CPU_STATE);
8483
9737
8484 val1 = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
8485 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val1, BCE_TXP_CPU_EVENT_MASK);
9738 val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
9739 BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n", val,
9740 BCE_TXP_CPU_EVENT_MASK);
8486
9741
8487 BCE_PRINTF(
8488 "----------------------------"
8489 " Register Dump "
8490 "----------------------------\n");
9742 if (regs) {
9743 BCE_PRINTF(
9744 "----------------------------"
9745 " Register Dump "
9746 "----------------------------\n");
8491
9747
8492 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
8493 /* Skip the big blank spaces */
8494 if (i < 0x454000 && i > 0x5ffff)
8495 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
8496 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
8497 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9748 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
9749 /* Skip the big blank spaces */
9750 if (i < 0x454000 && i > 0x5ffff)
9751 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9752 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9753 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9754 }
8498 }
8499
9755 }
9756
8500 BCE_PRINTF(
9757 BCE_PRINTF(
8501 "----------------------------"
8502 "----------------"
8503 "----------------------------\n");
8504}
8505
8506
8507/****************************************************************************/
9758 "----------------------------"
9759 "----------------"
9760 "----------------------------\n");
9761}
9762
9763
9764/****************************************************************************/
8508/* Prints out the RXP state. */
9765/* Prints out the RXP processor state. */
8509/* */
8510/* Returns: */
8511/* Nothing. */
8512/****************************************************************************/
9766/* */
9767/* Returns: */
9768/* Nothing. */
9769/****************************************************************************/
8513static void
8514bce_dump_rxp_state(struct bce_softc *sc)
9770static __attribute__ ((noinline)) void
9771bce_dump_rxp_state(struct bce_softc *sc, int regs)
8515{
9772{
8516 u32 val1;
9773 u32 val;
8517
8518 BCE_PRINTF(
8519 "----------------------------"
8520 " RXP State "
8521 "----------------------------\n");
8522
9774
9775 BCE_PRINTF(
9776 "----------------------------"
9777 " RXP State "
9778 "----------------------------\n");
9779
8523 val1 = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
8524 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val1, BCE_RXP_CPU_MODE);
9780 val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
9781 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n", val, BCE_RXP_CPU_MODE);
8525
9782
8526 val1 = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
8527 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val1, BCE_RXP_CPU_STATE);
9783 val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
9784 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n", val, BCE_RXP_CPU_STATE);
8528
9785
8529 val1 = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
8530 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val1, BCE_RXP_CPU_EVENT_MASK);
9786 val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
9787 BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n", val,
9788 BCE_RXP_CPU_EVENT_MASK);
8531
9789
8532 BCE_PRINTF(
9790 if (regs) {
9791 BCE_PRINTF(
9792 "----------------------------"
9793 " Register Dump "
9794 "----------------------------\n");
9795
9796 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
9797 /* Skip the big blank sapces */
9798 if (i < 0xc5400 && i > 0xdffff)
9799 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9800 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9801 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9802 }
9803 }
9804
9805 BCE_PRINTF(
8533 "----------------------------"
9806 "----------------------------"
8534 " Register Dump "
9807 "----------------"
8535 "----------------------------\n");
9808 "----------------------------\n");
9809}
8536
9810
8537 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
8538 /* Skip the big blank sapces */
8539 if (i < 0xc5400 && i > 0xdffff)
8540 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
8541 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
8542 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9811
9812/****************************************************************************/
9813/* Prints out the TPAT processor state. */
9814/* */
9815/* Returns: */
9816/* Nothing. */
9817/****************************************************************************/
9818static __attribute__ ((noinline)) void
9819bce_dump_tpat_state(struct bce_softc *sc, int regs)
9820{
9821 u32 val;
9822
9823 BCE_PRINTF(
9824 "----------------------------"
9825 " TPAT State "
9826 "----------------------------\n");
9827
9828 val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
9829 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val, BCE_TPAT_CPU_MODE);
9830
9831 val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
9832 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val, BCE_TPAT_CPU_STATE);
9833
9834 val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
9835 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val,
9836 BCE_TPAT_CPU_EVENT_MASK);
9837
9838 if (regs) {
9839 BCE_PRINTF(
9840 "----------------------------"
9841 " Register Dump "
9842 "----------------------------\n");
9843
9844 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
9845 /* Skip the big blank spaces */
9846 if (i < 0x854000 && i > 0x9ffff)
9847 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9848 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9849 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9850 }
8543 }
8544
9851 }
9852
8545 BCE_PRINTF(
9853 BCE_PRINTF(
8546 "----------------------------"
8547 "----------------"
8548 "----------------------------\n");
8549}
8550
8551
8552/****************************************************************************/
9854 "----------------------------"
9855 "----------------"
9856 "----------------------------\n");
9857}
9858
9859
9860/****************************************************************************/
8553/* Prints out the TPAT state. */
9861/* Prints out the Command Procesor (CP) state. */
8554/* */
8555/* Returns: */
8556/* Nothing. */
8557/****************************************************************************/
9862/* */
9863/* Returns: */
9864/* Nothing. */
9865/****************************************************************************/
8558static void
8559bce_dump_tpat_state(struct bce_softc *sc)
9866static __attribute__ ((noinline)) void
9867bce_dump_cp_state(struct bce_softc *sc, int regs)
8560{
9868{
8561 u32 val1;
9869 u32 val;
8562
8563 BCE_PRINTF(
8564 "----------------------------"
9870
9871 BCE_PRINTF(
9872 "----------------------------"
8565 " TPAT State "
9873 " CP State "
8566 "----------------------------\n");
8567
9874 "----------------------------\n");
9875
8568 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
8569 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n", val1, BCE_TPAT_CPU_MODE);
9876 val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
9877 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n", val, BCE_CP_CPU_MODE);
8570
9878
8571 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
8572 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n", val1, BCE_TPAT_CPU_STATE);
9879 val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
9880 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n", val, BCE_CP_CPU_STATE);
8573
9881
8574 val1 = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
8575 BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n", val1, BCE_TPAT_CPU_EVENT_MASK);
9882 val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
9883 BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
9884 BCE_CP_CPU_EVENT_MASK);
8576
9885
8577 BCE_PRINTF(
9886 if (regs) {
9887 BCE_PRINTF(
9888 "----------------------------"
9889 " Register Dump "
9890 "----------------------------\n");
9891
9892 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
9893 /* Skip the big blank spaces */
9894 if (i < 0x185400 && i > 0x19ffff)
9895 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9896 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9897 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9898 }
9899 }
9900
9901 BCE_PRINTF(
8578 "----------------------------"
9902 "----------------------------"
8579 " Register Dump "
9903 "----------------"
8580 "----------------------------\n");
9904 "----------------------------\n");
9905}
8581
9906
8582 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
8583 /* Skip the big blank spaces */
8584 if (i < 0x854000 && i > 0x9ffff)
9907
9908/****************************************************************************/
9909/* Prints out the Completion Procesor (COM) state. */
9910/* */
9911/* Returns: */
9912/* Nothing. */
9913/****************************************************************************/
9914static __attribute__ ((noinline)) void
9915bce_dump_com_state(struct bce_softc *sc, int regs)
9916{
9917 u32 val;
9918
9919 BCE_PRINTF(
9920 "----------------------------"
9921 " COM State "
9922 "----------------------------\n");
9923
9924 val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
9925 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n", val, BCE_COM_CPU_MODE);
9926
9927 val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
9928 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n", val, BCE_COM_CPU_STATE);
9929
9930 val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
9931 BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
9932 BCE_COM_CPU_EVENT_MASK);
9933
9934 if (regs) {
9935 BCE_PRINTF(
9936 "----------------------------"
9937 " Register Dump "
9938 "----------------------------\n");
9939
9940 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
8585 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
8586 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
8587 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9941 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
9942 i, REG_RD_IND(sc, i), REG_RD_IND(sc, i + 0x4),
9943 REG_RD_IND(sc, i + 0x8), REG_RD_IND(sc, i + 0xC));
9944 }
8588 }
8589
9945 }
9946
8590 BCE_PRINTF(
9947 BCE_PRINTF(
8591 "----------------------------"
8592 "----------------"
8593 "----------------------------\n");
8594}
8595
8596
9948 "----------------------------"
9949 "----------------"
9950 "----------------------------\n");
9951}
9952
9953
8597/* ToDo: Add CP and COM proccessor state dumps. */
8598
8599
8600/****************************************************************************/
8601/* Prints out the driver state and then enters the debugger. */
8602/* */
8603/* Returns: */
8604/* Nothing. */
8605/****************************************************************************/
8606static void
8607bce_breakpoint(struct bce_softc *sc)
8608{
8609
9954/****************************************************************************/
9955/* Prints out the driver state and then enters the debugger. */
9956/* */
9957/* Returns: */
9958/* Nothing. */
9959/****************************************************************************/
9960static void
9961bce_breakpoint(struct bce_softc *sc)
9962{
9963
8610 /*
8611 * Unreachable code to silence compiler warnings
8612 * about unused functions.
9964 /*
9965 * Unreachable code to silence compiler warnings
9966 * about unused functions.
8613 */
8614 if (0) {
8615 bce_freeze_controller(sc);
8616 bce_unfreeze_controller(sc);
8617 bce_dump_txbd(sc, 0, NULL);
8618 bce_dump_rxbd(sc, 0, NULL);
8619 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
8620 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
8621 bce_dump_l2fhdr(sc, 0, NULL);
8622 bce_dump_ctx(sc, RX_CID);
8623 bce_dump_ftqs(sc);
8624 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
8625 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
8626 bce_dump_status_block(sc);
8627 bce_dump_stats_block(sc);
8628 bce_dump_driver_state(sc);
8629 bce_dump_hw_state(sc);
8630 bce_dump_bc_state(sc);
9967 */
9968 if (0) {
9969 bce_freeze_controller(sc);
9970 bce_unfreeze_controller(sc);
9971 bce_dump_txbd(sc, 0, NULL);
9972 bce_dump_rxbd(sc, 0, NULL);
9973 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
9974 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
9975 bce_dump_l2fhdr(sc, 0, NULL);
9976 bce_dump_ctx(sc, RX_CID);
9977 bce_dump_ftqs(sc);
9978 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
9979 bce_dump_rx_chain(sc, 0, USABLE_RX_BD);
9980 bce_dump_status_block(sc);
9981 bce_dump_stats_block(sc);
9982 bce_dump_driver_state(sc);
9983 bce_dump_hw_state(sc);
9984 bce_dump_bc_state(sc);
8631 bce_dump_txp_state(sc);
8632 bce_dump_rxp_state(sc);
8633 bce_dump_tpat_state(sc);
9985 bce_dump_txp_state(sc, 0);
9986 bce_dump_rxp_state(sc, 0);
9987 bce_dump_tpat_state(sc, 0);
9988 bce_dump_cp_state(sc, 0);
9989 bce_dump_com_state(sc, 0);
8634#ifdef BCE_USE_SPLIT_HEADER
8635 bce_dump_pgbd(sc, 0, NULL);
8636 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD);
8637 bce_dump_pg_chain(sc, 0, USABLE_PG_BD);
8638#endif
8639 }
8640
8641 bce_dump_status_block(sc);
8642 bce_dump_driver_state(sc);
8643
8644 /* Call the debugger. */
8645 breakpoint();
8646
8647 return;
8648}
8649#endif
8650
9990#ifdef BCE_USE_SPLIT_HEADER
9991 bce_dump_pgbd(sc, 0, NULL);
9992 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD);
9993 bce_dump_pg_chain(sc, 0, USABLE_PG_BD);
9994#endif
9995 }
9996
9997 bce_dump_status_block(sc);
9998 bce_dump_driver_state(sc);
9999
10000 /* Call the debugger. */
10001 breakpoint();
10002
10003 return;
10004}
10005#endif
10006