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if_bce.c (176448) if_bce.c (178132)
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
1/*-
2 * Copyright (c) 2006-2008 Broadcom Corporation
3 * David Christensen <davidch@broadcom.com>. All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 *

--- 15 unchanged lines hidden (view full) ---

24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 176448 2008-02-22 00:46:22Z davidch $");
32__FBSDID("$FreeBSD: head/sys/dev/bce/if_bce.c 178132 2008-04-11 23:10:40Z davidch $");
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 *

--- 282 unchanged lines hidden (view full) ---

323static void bce_get_mac_addr (struct bce_softc *);
324static void bce_set_mac_addr (struct bce_softc *);
325static void bce_phy_intr (struct bce_softc *);
326static inline u16 bce_get_hw_rx_cons(struct bce_softc *);
327static void bce_rx_intr (struct bce_softc *);
328static void bce_tx_intr (struct bce_softc *);
329static void bce_disable_intr (struct bce_softc *);
330static void bce_enable_intr (struct bce_softc *);
33
34/*
35 * The following controllers are supported by this driver:
36 * BCM5706C A2, A3
37 * BCM5706S A2, A3
38 * BCM5708C B1, B2
39 * BCM5708S B1, B2
40 *

--- 282 unchanged lines hidden (view full) ---

323static void bce_get_mac_addr (struct bce_softc *);
324static void bce_set_mac_addr (struct bce_softc *);
325static void bce_phy_intr (struct bce_softc *);
326static inline u16 bce_get_hw_rx_cons(struct bce_softc *);
327static void bce_rx_intr (struct bce_softc *);
328static void bce_tx_intr (struct bce_softc *);
329static void bce_disable_intr (struct bce_softc *);
330static void bce_enable_intr (struct bce_softc *);
331
332#ifdef DEVICE_POLLING
333static void bce_poll_locked (struct ifnet *, enum poll_cmd, int);
334static void bce_poll (struct ifnet *, enum poll_cmd, int);
335#endif
336static void bce_intr (void *);
337static void bce_set_rx_mode (struct bce_softc *);
338static void bce_stats_update (struct bce_softc *);
339static void bce_tick (void *);
340static void bce_pulse (void *);
341static void bce_add_sysctls (struct bce_softc *);
342
343

--- 435 unchanged lines hidden (view full) ---

779 }
780
781 ifp->if_capenable = ifp->if_capabilities;
782
783 /* Use standard mbuf sizes for buffer allocation. */
784 sc->rx_bd_mbuf_alloc_size = MHLEN;
785 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
786
331static void bce_intr (void *);
332static void bce_set_rx_mode (struct bce_softc *);
333static void bce_stats_update (struct bce_softc *);
334static void bce_tick (void *);
335static void bce_pulse (void *);
336static void bce_add_sysctls (struct bce_softc *);
337
338

--- 435 unchanged lines hidden (view full) ---

774 }
775
776 ifp->if_capenable = ifp->if_capabilities;
777
778 /* Use standard mbuf sizes for buffer allocation. */
779 sc->rx_bd_mbuf_alloc_size = MHLEN;
780 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
781
787#ifdef DEVICE_POLLING
788 ifp->if_capabilities |= IFCAP_POLLING;
789#endif
790
791 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
792 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
793 IFQ_SET_READY(&ifp->if_snd);
794
795 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
796 ifp->if_baudrate = IF_Mbps(2500ULL);
797 else
798 ifp->if_baudrate = IF_Mbps(1000);

--- 100 unchanged lines hidden (view full) ---

899 struct bce_softc *sc = device_get_softc(dev);
900 struct ifnet *ifp;
901 u32 msg;
902
903 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
904
905 ifp = sc->bce_ifp;
906
782 ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
783 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
784 IFQ_SET_READY(&ifp->if_snd);
785
786 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
787 ifp->if_baudrate = IF_Mbps(2500ULL);
788 else
789 ifp->if_baudrate = IF_Mbps(1000);

--- 100 unchanged lines hidden (view full) ---

890 struct bce_softc *sc = device_get_softc(dev);
891 struct ifnet *ifp;
892 u32 msg;
893
894 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
895
896 ifp = sc->bce_ifp;
897
907#ifdef DEVICE_POLLING
908 if (ifp->if_capenable & IFCAP_POLLING)
909 ether_poll_deregister(ifp);
910#endif
911
912 /* Stop and reset the controller. */
913 BCE_LOCK(sc);
914
915 /* Stop the pulse so the bootcode can go to driver absent state. */
916 callout_stop(&sc->bce_pulse_callout);
917
918 bce_stop(sc);
919 if (sc->bce_flags & BCE_NO_WOL_FLAG)

--- 3467 unchanged lines hidden (view full) ---

4387/* Returns: */
4388/* Nothing. */
4389/****************************************************************************/
4390static void
4391bce_free_pg_chain(struct bce_softc *sc)
4392{
4393 int i;
4394
898 /* Stop and reset the controller. */
899 BCE_LOCK(sc);
900
901 /* Stop the pulse so the bootcode can go to driver absent state. */
902 callout_stop(&sc->bce_pulse_callout);
903
904 bce_stop(sc);
905 if (sc->bce_flags & BCE_NO_WOL_FLAG)

--- 3467 unchanged lines hidden (view full) ---

4373/* Returns: */
4374/* Nothing. */
4375/****************************************************************************/
4376static void
4377bce_free_pg_chain(struct bce_softc *sc)
4378{
4379 int i;
4380
4395 DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __FUNCTION__);
4381 DBPRINT(sc, BCE_EXCESSIVE_RESET, "Entering %s()\n", __FUNCTION__);
4396
4397 /* Free any mbufs still in the mbuf page chain. */
4398 for (i = 0; i < TOTAL_PG_BD; i++) {
4399 if (sc->pg_mbuf_ptr[i] != NULL) {
4400 if (sc->pg_mbuf_map[i] != NULL)
4401 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i],
4402 BUS_DMASYNC_POSTREAD);
4403 m_freem(sc->pg_mbuf_ptr[i]);

--- 8 unchanged lines hidden (view full) ---

4412
4413 sc->free_pg_bd = sc->max_pg_bd;
4414
4415 /* Check if we lost any mbufs in the process. */
4416 DBRUNIF((sc->debug_pg_mbuf_alloc),
4417 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
4418 __FUNCTION__, sc->debug_pg_mbuf_alloc));
4419
4382
4383 /* Free any mbufs still in the mbuf page chain. */
4384 for (i = 0; i < TOTAL_PG_BD; i++) {
4385 if (sc->pg_mbuf_ptr[i] != NULL) {
4386 if (sc->pg_mbuf_map[i] != NULL)
4387 bus_dmamap_sync(sc->pg_mbuf_tag, sc->pg_mbuf_map[i],
4388 BUS_DMASYNC_POSTREAD);
4389 m_freem(sc->pg_mbuf_ptr[i]);

--- 8 unchanged lines hidden (view full) ---

4398
4399 sc->free_pg_bd = sc->max_pg_bd;
4400
4401 /* Check if we lost any mbufs in the process. */
4402 DBRUNIF((sc->debug_pg_mbuf_alloc),
4403 BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
4404 __FUNCTION__, sc->debug_pg_mbuf_alloc));
4405
4420 DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __FUNCTION__);
4406 DBPRINT(sc, BCE_EXCESSIVE_RESET, "Exiting %s()\n", __FUNCTION__);
4421}
4422
4423
4424/****************************************************************************/
4425/* Set media options. */
4426/* */
4427/* Returns: */
4428/* 0 for success, positive value for failure. */

--- 127 unchanged lines hidden (view full) ---

4556 u16 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4557
4558 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4559 hw_cons++;
4560
4561 return hw_cons;
4562}
4563
4407}
4408
4409
4410/****************************************************************************/
4411/* Set media options. */
4412/* */
4413/* Returns: */
4414/* 0 for success, positive value for failure. */

--- 127 unchanged lines hidden (view full) ---

4542 u16 hw_cons = sc->status_block->status_rx_quick_consumer_index0;
4543
4544 if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
4545 hw_cons++;
4546
4547 return hw_cons;
4548}
4549
4550
4564/****************************************************************************/
4565/* Handles received frame interrupt events. */
4566/* */
4567/* Returns: */
4568/* Nothing. */
4569/****************************************************************************/
4570static void
4571bce_rx_intr(struct bce_softc *sc)
4572{
4573 struct ifnet *ifp = sc->bce_ifp;
4574 struct l2_fhdr *l2fhdr;
4575 unsigned int pages, pkt_len, rem_len;
4576 u16 sw_rx_cons, sw_rx_cons_idx, sw_pg_cons, sw_pg_cons_idx, hw_rx_cons;
4577 u32 status;
4578
4551/****************************************************************************/
4552/* Handles received frame interrupt events. */
4553/* */
4554/* Returns: */
4555/* Nothing. */
4556/****************************************************************************/
4557static void
4558bce_rx_intr(struct bce_softc *sc)
4559{
4560 struct ifnet *ifp = sc->bce_ifp;
4561 struct l2_fhdr *l2fhdr;
4562 unsigned int pages, pkt_len, rem_len;
4563 u16 sw_rx_cons, sw_rx_cons_idx, sw_pg_cons, sw_pg_cons_idx, hw_rx_cons;
4564 u32 status;
4565
4566
4579#ifdef BCE_DEBUG
4567#ifdef BCE_DEBUG
4580 u32 rx_intr_start, rx_intr_end;
4581 rx_intr_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4568 u32 timer_start, timer_end;
4569 timer_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4582 sc->rx_interrupts++;
4583#endif
4584
4585 /* Prepare the RX chain pages to be accessed by the host CPU. */
4586 for (int i = 0; i < RX_PAGES; i++)
4587 bus_dmamap_sync(sc->rx_bd_chain_tag,
4588 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
4589

--- 4 unchanged lines hidden (view full) ---

4594
4595 /* Get the hardware's view of the RX consumer index. */
4596 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4597
4598 /* Get working copies of the driver's view of the consumer indices. */
4599 sw_rx_cons = sc->rx_cons;
4600 sw_pg_cons = sc->pg_cons;
4601
4570 sc->rx_interrupts++;
4571#endif
4572
4573 /* Prepare the RX chain pages to be accessed by the host CPU. */
4574 for (int i = 0; i < RX_PAGES; i++)
4575 bus_dmamap_sync(sc->rx_bd_chain_tag,
4576 sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTWRITE);
4577

--- 4 unchanged lines hidden (view full) ---

4582
4583 /* Get the hardware's view of the RX consumer index. */
4584 hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
4585
4586 /* Get working copies of the driver's view of the consumer indices. */
4587 sw_rx_cons = sc->rx_cons;
4588 sw_pg_cons = sc->pg_cons;
4589
4590 DBPRINT(sc, BCE_INFO_RECV, "%s(enter): rx_prod = 0x%04X, "
4591 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4592 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4593
4602 /* Update some debug statistics counters */
4603 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4604 sc->rx_low_watermark = sc->free_rx_bd);
4605 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4606
4607 /* Scan through the receive chain as long as there is work to do */
4608 /* ToDo: Consider setting a limit on the number of packets processed. */
4609 while (sw_rx_cons != hw_rx_cons) {
4610 struct mbuf *m0;
4594 /* Update some debug statistics counters */
4595 DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
4596 sc->rx_low_watermark = sc->free_rx_bd);
4597 DBRUNIF((sc->free_rx_bd == sc->max_rx_bd), sc->rx_empty_count++);
4598
4599 /* Scan through the receive chain as long as there is work to do */
4600 /* ToDo: Consider setting a limit on the number of packets processed. */
4601 while (sw_rx_cons != hw_rx_cons) {
4602 struct mbuf *m0;
4611
4603
4612 /* Convert the producer/consumer indices to an actual rx_bd index. */
4613 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
4614
4604 /* Convert the producer/consumer indices to an actual rx_bd index. */
4605 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
4606
4615#ifdef DEVICE_POLLING
4616 if (ifp->if_capenable & IFCAP_POLLING) {
4617 if (sc->bce_rxcycles <= 0)
4618 break;
4619 sc->bce_rxcycles--;
4620 }
4621#endif
4622
4623 /* Unmap the mbuf from DMA space. */
4624 bus_dmamap_sync(sc->rx_mbuf_tag,
4625 sc->rx_mbuf_map[sw_rx_cons_idx],
4626 BUS_DMASYNC_POSTREAD);
4627 bus_dmamap_unload(sc->rx_mbuf_tag,
4628 sc->rx_mbuf_map[sw_rx_cons_idx]);
4629
4630 /* Remove the mbuf from the RX chain. */

--- 45 unchanged lines hidden (view full) ---

4676 * header is placed in the mbuf, the remaining
4677 * payload (including FCS) is placed in the page
4678 * chain, the SPLIT flag is set, and the header
4679 * length is placed in the IP checksum field.
4680 * If the frame is not a TCP frame then the mbuf
4681 * is filled and the remaining bytes are placed
4682 * in the page chain.
4683 */
4607 /* Unmap the mbuf from DMA space. */
4608 bus_dmamap_sync(sc->rx_mbuf_tag,
4609 sc->rx_mbuf_map[sw_rx_cons_idx],
4610 BUS_DMASYNC_POSTREAD);
4611 bus_dmamap_unload(sc->rx_mbuf_tag,
4612 sc->rx_mbuf_map[sw_rx_cons_idx]);
4613
4614 /* Remove the mbuf from the RX chain. */

--- 45 unchanged lines hidden (view full) ---

4660 * header is placed in the mbuf, the remaining
4661 * payload (including FCS) is placed in the page
4662 * chain, the SPLIT flag is set, and the header
4663 * length is placed in the IP checksum field.
4664 * If the frame is not a TCP frame then the mbuf
4665 * is filled and the remaining bytes are placed
4666 * in the page chain.
4667 */
4668
4669 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large packet.\n",
4670 __FUNCTION__);
4671
4684 if (status & L2_FHDR_STATUS_SPLIT)
4685 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
4686
4687 rem_len = pkt_len - m0->m_len;
4688
4689 /* Calculate how many pages to pull off the page chain. */
4690 /* ToDo: The following assumes that mbuf clusters are 2KB. */
4691 pages = (rem_len + sc->pg_bd_mbuf_alloc_size) >> 11;

--- 39 unchanged lines hidden (view full) ---

4731 } else {
4732 /*
4733 * The received packet is small and fits in a
4734 * single mbuf (i.e. the l2_fhdr + pad + packet +
4735 * FCS <= MHLEN). In other words, the packet is
4736 * 154 bytes or less in size.
4737 */
4738
4672 if (status & L2_FHDR_STATUS_SPLIT)
4673 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
4674
4675 rem_len = pkt_len - m0->m_len;
4676
4677 /* Calculate how many pages to pull off the page chain. */
4678 /* ToDo: The following assumes that mbuf clusters are 2KB. */
4679 pages = (rem_len + sc->pg_bd_mbuf_alloc_size) >> 11;

--- 39 unchanged lines hidden (view full) ---

4719 } else {
4720 /*
4721 * The received packet is small and fits in a
4722 * single mbuf (i.e. the l2_fhdr + pad + packet +
4723 * FCS <= MHLEN). In other words, the packet is
4724 * 154 bytes or less in size.
4725 */
4726
4727 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small packet.\n",
4728 __FUNCTION__);
4729
4739 /* Set the total packet length. */
4740 m0->m_pkthdr.len = m0->m_len = pkt_len;
4741 }
4742
4743 /* Remove the trailing Ethernet FCS. */
4744 m_adj(m0, -ETHER_CRC_LEN);
4745
4746 /* Check that the resulting mbuf chain is valid. */
4747 DBRUN(m_sanity(m0, FALSE));
4748
4730 /* Set the total packet length. */
4731 m0->m_pkthdr.len = m0->m_len = pkt_len;
4732 }
4733
4734 /* Remove the trailing Ethernet FCS. */
4735 m_adj(m0, -ETHER_CRC_LEN);
4736
4737 /* Check that the resulting mbuf chain is valid. */
4738 DBRUN(m_sanity(m0, FALSE));
4739
4740 DBRUNIF((m0->m_len < ETHER_HDR_LEN),
4741 BCE_PRINTF("%s(): Unexpected length = %d!.\n",
4742 __FUNCTION__, m0->m_len);
4743 bce_breakpoint(sc));
4744
4749 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4750 BCE_PRINTF("Simulating l2_fhdr status error.\n");
4751 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4752
4753 /* Check the received frame for errors. */
4754 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4755 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
4756 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {

--- 94 unchanged lines hidden (view full) ---

4851 for (int i = 0; i < PG_PAGES; i++)
4852 bus_dmamap_sync(sc->pg_bd_chain_tag,
4853 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4854
4855 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4856 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4857 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4858
4745 DBRUNIF(DB_RANDOMTRUE(bce_debug_l2fhdr_status_check),
4746 BCE_PRINTF("Simulating l2_fhdr status error.\n");
4747 status = status | L2_FHDR_ERRORS_PHY_DECODE);
4748
4749 /* Check the received frame for errors. */
4750 if (status & (L2_FHDR_ERRORS_BAD_CRC |
4751 L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
4752 L2_FHDR_ERRORS_TOO_SHORT | L2_FHDR_ERRORS_GIANT_FRAME)) {

--- 94 unchanged lines hidden (view full) ---

4847 for (int i = 0; i < PG_PAGES; i++)
4848 bus_dmamap_sync(sc->pg_bd_chain_tag,
4849 sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
4850
4851 DBPRINT(sc, BCE_INFO_RECV, "%s(exit): rx_prod = 0x%04X, "
4852 "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
4853 __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
4854
4859 DBRUN(rx_intr_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4860 sc->rx_intr_time += (u64) BCE_TIME_DELTA(rx_intr_start, rx_intr_end));
4855#ifdef BCE_DEBUG
4856 timer_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4857 sc->rx_intr_time += (u64) (timer_start > timer_end ?
4858 (timer_start - timer_end) : (~timer_start + timer_end + 1));
4859#endif
4861}
4862
4863
4864/****************************************************************************/
4860}
4861
4862
4863/****************************************************************************/
4864/* Reads the transmit consumer value from the status block (skipping over */
4865/* chain page pointer if necessary). */
4866/* */
4867/* Returns: */
4868/* hw_cons */
4869/****************************************************************************/
4870static inline u16
4871bce_get_hw_tx_cons(struct bce_softc *sc)
4872{
4873 u16 hw_cons = sc->status_block->status_tx_quick_consumer_index0;
4874
4875 if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4876 hw_cons++;
4877
4878 return hw_cons;
4879}
4880
4881
4882/****************************************************************************/
4865/* Handles transmit completion interrupt events. */
4866/* */
4867/* Returns: */
4868/* Nothing. */
4869/****************************************************************************/
4870static void
4871bce_tx_intr(struct bce_softc *sc)
4872{
4883/* Handles transmit completion interrupt events. */
4884/* */
4885/* Returns: */
4886/* Nothing. */
4887/****************************************************************************/
4888static void
4889bce_tx_intr(struct bce_softc *sc)
4890{
4873 struct status_block *sblk = sc->status_block;
4874 struct ifnet *ifp = sc->bce_ifp;
4875 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4876
4877#ifdef BCE_DEBUG
4891 struct ifnet *ifp = sc->bce_ifp;
4892 u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
4893
4894#ifdef BCE_DEBUG
4878 u32 tx_intr_start, tx_intr_end;
4879 tx_intr_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4895 u32 timer_start, timer_end;
4896 timer_start = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4880 sc->tx_interrupts++;
4881#endif
4882
4883 BCE_LOCK_ASSERT(sc);
4884
4885 /* Get the hardware's view of the TX consumer index. */
4897 sc->tx_interrupts++;
4898#endif
4899
4900 BCE_LOCK_ASSERT(sc);
4901
4902 /* Get the hardware's view of the TX consumer index. */
4886 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
4887
4888 /* Skip to the next entry if this is a chain page pointer. */
4889 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4890 hw_tx_cons++;
4891
4903 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4892 sw_tx_cons = sc->tx_cons;
4893
4894 /* Prevent speculative reads from getting ahead of the status block. */
4895 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4896 BUS_SPACE_BARRIER_READ);
4897
4898 /* Cycle through any completed TX chain page entries. */
4899 while (sw_tx_cons != hw_tx_cons) {

--- 52 unchanged lines hidden (view full) ---

4952
4953 ifp->if_opackets++;
4954 }
4955
4956 sc->used_tx_bd--;
4957 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4958
4959 /* Refresh hw_cons to see if there's new work. */
4904 sw_tx_cons = sc->tx_cons;
4905
4906 /* Prevent speculative reads from getting ahead of the status block. */
4907 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4908 BUS_SPACE_BARRIER_READ);
4909
4910 /* Cycle through any completed TX chain page entries. */
4911 while (sw_tx_cons != hw_tx_cons) {

--- 52 unchanged lines hidden (view full) ---

4964
4965 ifp->if_opackets++;
4966 }
4967
4968 sc->used_tx_bd--;
4969 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
4970
4971 /* Refresh hw_cons to see if there's new work. */
4960 hw_tx_cons = sc->hw_tx_cons = sblk->status_tx_quick_consumer_index0;
4961 if ((hw_tx_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
4962 hw_tx_cons++;
4972 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
4963
4964 /* Prevent speculative reads from getting ahead of the status block. */
4965 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4966 BUS_SPACE_BARRIER_READ);
4967 }
4968
4969 /* Clear the TX timeout timer. */
4970 sc->watchdog_timer = 0;
4971
4972 /* Clear the tx hardware queue full flag. */
4973 if (sc->used_tx_bd < sc->max_tx_bd) {
4974 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
4975 DBPRINT(sc, BCE_INFO_SEND,
4976 "%s(): Open TX chain! %d/%d (used/total)\n",
4977 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
4978 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4979 }
4980
4981 sc->tx_cons = sw_tx_cons;
4973
4974 /* Prevent speculative reads from getting ahead of the status block. */
4975 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
4976 BUS_SPACE_BARRIER_READ);
4977 }
4978
4979 /* Clear the TX timeout timer. */
4980 sc->watchdog_timer = 0;
4981
4982 /* Clear the tx hardware queue full flag. */
4983 if (sc->used_tx_bd < sc->max_tx_bd) {
4984 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
4985 DBPRINT(sc, BCE_INFO_SEND,
4986 "%s(): Open TX chain! %d/%d (used/total)\n",
4987 __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
4988 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4989 }
4990
4991 sc->tx_cons = sw_tx_cons;
4982 DBRUN(tx_intr_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4983 sc->tx_intr_time += (u64) BCE_TIME_DELTA(tx_intr_start, tx_intr_end));
4992#ifdef BCE_DEBUG
4993 timer_end = REG_RD(sc, BCE_TIMER_25MHZ_FREE_RUN);
4994 sc->tx_intr_time += (u64) (timer_start > timer_end ?
4995 (timer_start - timer_end) : (~timer_start + timer_end + 1));
4996#endif
4984}
4985
4986
4987/****************************************************************************/
4988/* Disables interrupt generation. */
4989/* */
4990/* Returns: */
4991/* Nothing. */

--- 107 unchanged lines hidden (view full) ---

5099 bce_init_pg_chain(sc);
5100
5101 /* Init RX buffer descriptor chain. */
5102 bce_init_rx_chain(sc);
5103
5104 /* Init TX buffer descriptor chain. */
5105 bce_init_tx_chain(sc);
5106
4997}
4998
4999
5000/****************************************************************************/
5001/* Disables interrupt generation. */
5002/* */
5003/* Returns: */
5004/* Nothing. */

--- 107 unchanged lines hidden (view full) ---

5112 bce_init_pg_chain(sc);
5113
5114 /* Init RX buffer descriptor chain. */
5115 bce_init_rx_chain(sc);
5116
5117 /* Init TX buffer descriptor chain. */
5118 bce_init_tx_chain(sc);
5119
5107#ifdef DEVICE_POLLING
5108 /* Disable interrupts if we are polling. */
5109 if (ifp->if_capenable & IFCAP_POLLING) {
5110 bce_disable_intr(sc);
5111
5112 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5113 (1 << 16) | sc->bce_rx_quick_cons_trip);
5114 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5115 (1 << 16) | sc->bce_tx_quick_cons_trip);
5116 } else
5117#endif
5118 /* Enable host interrupts. */
5119 bce_enable_intr(sc);
5120
5121 bce_ifmedia_upd_locked(ifp);
5122
5123 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5124 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5125

--- 235 unchanged lines hidden (view full) ---

5361 /* prod points to an empty tx_bd at this point. */
5362 prod_bseq = sc->tx_prod_bseq;
5363
5364#ifdef BCE_DEBUG
5365 debug_prod = chain_prod;
5366#endif
5367
5368 DBPRINT(sc, BCE_INFO_SEND,
5120 /* Enable host interrupts. */
5121 bce_enable_intr(sc);
5122
5123 bce_ifmedia_upd_locked(ifp);
5124
5125 ifp->if_drv_flags |= IFF_DRV_RUNNING;
5126 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
5127

--- 235 unchanged lines hidden (view full) ---

5363 /* prod points to an empty tx_bd at this point. */
5364 prod_bseq = sc->tx_prod_bseq;
5365
5366#ifdef BCE_DEBUG
5367 debug_prod = chain_prod;
5368#endif
5369
5370 DBPRINT(sc, BCE_INFO_SEND,
5369 "%s(): Start: prod = 0x%04X, chain_prod = %04X, "
5371 "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
5370 "prod_bseq = 0x%08X\n",
5371 __FUNCTION__, prod, chain_prod, prod_bseq);
5372
5373 /*
5374 * Cycle through each mbuf segment that makes up
5375 * the outgoing frame, gathering the mapping info
5376 * for that segment and creating a tx_bd for
5377 * the mbuf.

--- 15 unchanged lines hidden (view full) ---

5393 }
5394
5395 /* Set the END flag on the last TX buffer descriptor. */
5396 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5397
5398 DBRUNMSG(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs));
5399
5400 DBPRINT(sc, BCE_INFO_SEND,
5372 "prod_bseq = 0x%08X\n",
5373 __FUNCTION__, prod, chain_prod, prod_bseq);
5374
5375 /*
5376 * Cycle through each mbuf segment that makes up
5377 * the outgoing frame, gathering the mapping info
5378 * for that segment and creating a tx_bd for
5379 * the mbuf.

--- 15 unchanged lines hidden (view full) ---

5395 }
5396
5397 /* Set the END flag on the last TX buffer descriptor. */
5398 txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
5399
5400 DBRUNMSG(BCE_EXCESSIVE_SEND, bce_dump_tx_chain(sc, debug_prod, nsegs));
5401
5402 DBPRINT(sc, BCE_INFO_SEND,
5401 "%s(): End: prod = 0x%04X, chain_prod = %04X, "
5403 "%s( end ): prod = 0x%04X, chain_prod = 0x%04X, "
5402 "prod_bseq = 0x%08X\n",
5403 __FUNCTION__, prod, chain_prod, prod_bseq);
5404
5405 /*
5406 * Ensure that the mbuf pointer for this transmission
5407 * is placed at the array index of the last
5408 * descriptor in this chain. This is done
5409 * because a single map is used for all

--- 29 unchanged lines hidden (view full) ---

5439static void
5440bce_start_locked(struct ifnet *ifp)
5441{
5442 struct bce_softc *sc = ifp->if_softc;
5443 struct mbuf *m_head = NULL;
5444 int count = 0;
5445 u16 tx_prod, tx_chain_prod;
5446
5404 "prod_bseq = 0x%08X\n",
5405 __FUNCTION__, prod, chain_prod, prod_bseq);
5406
5407 /*
5408 * Ensure that the mbuf pointer for this transmission
5409 * is placed at the array index of the last
5410 * descriptor in this chain. This is done
5411 * because a single map is used for all

--- 29 unchanged lines hidden (view full) ---

5441static void
5442bce_start_locked(struct ifnet *ifp)
5443{
5444 struct bce_softc *sc = ifp->if_softc;
5445 struct mbuf *m_head = NULL;
5446 int count = 0;
5447 u16 tx_prod, tx_chain_prod;
5448
5447 /* If there's no link or the transmit queue is empty then just exit. */
5448 if (!sc->bce_link || IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5449 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link or transmit queue empty.\n",
5450 __FUNCTION__);
5451 goto bce_start_locked_exit;
5452 }
5453
5454 /* prod points to the next free tx_bd. */
5455 tx_prod = sc->tx_prod;
5456 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
5457
5458 DBPRINT(sc, BCE_INFO_SEND,
5449 /* prod points to the next free tx_bd. */
5450 tx_prod = sc->tx_prod;
5451 tx_chain_prod = TX_CHAIN_IDX(tx_prod);
5452
5453 DBPRINT(sc, BCE_INFO_SEND,
5459 "%s(): Start: tx_prod = 0x%04X, tx_chain_prod = %04X, "
5454 "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
5460 "tx_prod_bseq = 0x%08X\n",
5461 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
5462
5455 "tx_prod_bseq = 0x%08X\n",
5456 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
5457
5458 /* If there's no link or the transmit queue is empty then just exit. */
5459 if (!sc->bce_link) {
5460 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
5461 __FUNCTION__);
5462 goto bce_start_locked_exit;
5463 }
5464
5465 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
5466 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
5467 __FUNCTION__);
5468 goto bce_start_locked_exit;
5469 }
5470
5463 /*
5464 * Keep adding entries while there is space in the ring.
5465 */
5466 while (sc->used_tx_bd < sc->max_tx_bd) {
5467
5468 /* Check for any frames to send. */
5469 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5470 if (m_head == NULL)

--- 26 unchanged lines hidden (view full) ---

5497 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n",
5498 __FUNCTION__);
5499 goto bce_start_locked_exit;
5500 }
5501
5502 /* Update the driver's counters. */
5503 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod);
5504
5471 /*
5472 * Keep adding entries while there is space in the ring.
5473 */
5474 while (sc->used_tx_bd < sc->max_tx_bd) {
5475
5476 /* Check for any frames to send. */
5477 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
5478 if (m_head == NULL)

--- 26 unchanged lines hidden (view full) ---

5505 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were dequeued\n",
5506 __FUNCTION__);
5507 goto bce_start_locked_exit;
5508 }
5509
5510 /* Update the driver's counters. */
5511 tx_chain_prod = TX_CHAIN_IDX(sc->tx_prod);
5512
5505 DBPRINT(sc, BCE_INFO_SEND,
5506 "%s(): End: tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
5507 "tx_prod_bseq = 0x%08X\n",
5508 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
5509
5510 /* Start the transmit. */
5511 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5512 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5513
5514 /* Set the tx timeout. */
5515 sc->watchdog_timer = BCE_TX_TIMEOUT;
5516
5517bce_start_locked_exit:
5513 /* Start the transmit. */
5514 REG_WR16(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BIDX, sc->tx_prod);
5515 REG_WR(sc, MB_TX_CID_ADDR + BCE_L2CTX_TX_HOST_BSEQ, sc->tx_prod_bseq);
5516
5517 /* Set the tx timeout. */
5518 sc->watchdog_timer = BCE_TX_TIMEOUT;
5519
5520bce_start_locked_exit:
5521 DBPRINT(sc, BCE_INFO_SEND,
5522 "%s(exit ): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
5523 "tx_prod_bseq = 0x%08X\n",
5524 __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
5525
5518 return;
5519}
5520
5521
5522/****************************************************************************/
5523/* Main transmit routine when called from another routine without a lock. */
5524/* */
5525/* Returns: */

--- 104 unchanged lines hidden (view full) ---

5630 &mii->mii_media, command);
5631 break;
5632
5633 /* Set interface capability */
5634 case SIOCSIFCAP:
5635 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5636 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
5637
5526 return;
5527}
5528
5529
5530/****************************************************************************/
5531/* Main transmit routine when called from another routine without a lock. */
5532/* */
5533/* Returns: */

--- 104 unchanged lines hidden (view full) ---

5638 &mii->mii_media, command);
5639 break;
5640
5641 /* Set interface capability */
5642 case SIOCSIFCAP:
5643 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
5644 DBPRINT(sc, BCE_INFO_MISC, "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
5645
5638#ifdef DEVICE_POLLING
5639 if (mask & IFCAP_POLLING) {
5640 if (ifr->ifr_reqcap & IFCAP_POLLING) {
5641
5642 /* Setup the poll routine to call. */
5643 error = ether_poll_register(bce_poll, ifp);
5644 if (error) {
5645 BCE_PRINTF("%s(%d): Error registering poll function!\n",
5646 __FILE__, __LINE__);
5647 goto bce_ioctl_exit;
5648 }
5649
5650 /* Clear the interrupt. */
5651 BCE_LOCK(sc);
5652 bce_disable_intr(sc);
5653
5654 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5655 (1 << 16) | sc->bce_rx_quick_cons_trip);
5656 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5657 (1 << 16) | sc->bce_tx_quick_cons_trip);
5658
5659 ifp->if_capenable |= IFCAP_POLLING;
5660 BCE_UNLOCK(sc);
5661 } else {
5662 /* Clear the poll routine. */
5663 error = ether_poll_deregister(ifp);
5664
5665 /* Enable interrupt even in error case */
5666 BCE_LOCK(sc);
5667 bce_enable_intr(sc);
5668
5669 REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5670 (sc->bce_tx_quick_cons_trip_int << 16) |
5671 sc->bce_tx_quick_cons_trip);
5672 REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5673 (sc->bce_rx_quick_cons_trip_int << 16) |
5674 sc->bce_rx_quick_cons_trip);
5675
5676 ifp->if_capenable &= ~IFCAP_POLLING;
5677 BCE_UNLOCK(sc);
5678 }
5679 }
5680#endif /*DEVICE_POLLING */
5681
5682 /* Toggle the TX checksum capabilites enable flag. */
5683 if (mask & IFCAP_TXCSUM) {
5684 ifp->if_capenable ^= IFCAP_TXCSUM;
5685 if (IFCAP_TXCSUM & ifp->if_capenable)
5686 ifp->if_hwassist = BCE_IF_HWASSIST;
5687 else
5688 ifp->if_hwassist = 0;
5689 }

--- 35 unchanged lines hidden (view full) ---

5725
5726 break;
5727 default:
5728 /* We don't know how to handle the IOCTL, pass it on. */
5729 error = ether_ioctl(ifp, command, data);
5730 break;
5731 }
5732
5646 /* Toggle the TX checksum capabilites enable flag. */
5647 if (mask & IFCAP_TXCSUM) {
5648 ifp->if_capenable ^= IFCAP_TXCSUM;
5649 if (IFCAP_TXCSUM & ifp->if_capenable)
5650 ifp->if_hwassist = BCE_IF_HWASSIST;
5651 else
5652 ifp->if_hwassist = 0;
5653 }

--- 35 unchanged lines hidden (view full) ---

5689
5690 break;
5691 default:
5692 /* We don't know how to handle the IOCTL, pass it on. */
5693 error = ether_ioctl(ifp, command, data);
5694 break;
5695 }
5696
5733#ifdef DEVICE_POLLING
5734bce_ioctl_exit:
5735#endif
5736 return(error);
5737}
5738
5739
5740/****************************************************************************/
5741/* Transmit timeout handler. */
5742/* */
5743/* Returns: */

--- 27 unchanged lines hidden (view full) ---

5771 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5772
5773 bce_init_locked(sc);
5774 sc->bce_ifp->if_oerrors++;
5775
5776}
5777
5778
5697 return(error);
5698}
5699
5700
5701/****************************************************************************/
5702/* Transmit timeout handler. */
5703/* */
5704/* Returns: */

--- 27 unchanged lines hidden (view full) ---

5732 sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
5733
5734 bce_init_locked(sc);
5735 sc->bce_ifp->if_oerrors++;
5736
5737}
5738
5739
5779#ifdef DEVICE_POLLING
5780static void
5781bce_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count)
5782{
5783 struct bce_softc *sc = ifp->if_softc;
5784
5785 BCE_LOCK_ASSERT(sc);
5786
5787 sc->bce_rxcycles = count;
5788
5789 bus_dmamap_sync(sc->status_tag, sc->status_map,
5790 BUS_DMASYNC_POSTWRITE);
5791
5792 /* Check for any completed RX frames. */
5793 if (sc->status_block->status_rx_quick_consumer_index0 !=
5794 sc->hw_rx_cons)
5795 bce_rx_intr(sc);
5796
5797 /* Check for any completed TX frames. */
5798 if (sc->status_block->status_tx_quick_consumer_index0 !=
5799 sc->hw_tx_cons)
5800 bce_tx_intr(sc);
5801
5802 /* Check for new frames to transmit. */
5803 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
5804 bce_start_locked(ifp);
5805
5806}
5807
5808
5809static void
5810bce_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
5811{
5812 struct bce_softc *sc = ifp->if_softc;
5813
5814 BCE_LOCK(sc);
5815 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
5816 bce_poll_locked(ifp, cmd, count);
5817 BCE_UNLOCK(sc);
5818}
5819#endif /* DEVICE_POLLING */
5820
5821
5822#if 0
5823static inline int
5824bce_has_work(struct bce_softc *sc)
5825{
5826 struct status_block *stat = sc->status_block;
5827
5828 if ((stat->status_rx_quick_consumer_index0 != sc->hw_rx_cons) ||
5829 (stat->status_tx_quick_consumer_index0 != sc->hw_tx_cons))
5830 return 1;
5831
5832 if (((stat->status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) != 0) !=
5833 bp->link_up)
5834 return 1;
5835
5836 return 0;
5837}
5838#endif
5839
5840
5841/*
5842 * Interrupt handler.
5843 */
5844/****************************************************************************/
5845/* Main interrupt entry point. Verifies that the controller generated the */
5846/* interrupt and then calls a separate routine for handle the various */
5847/* interrupt causes (PHY, TX, RX). */
5848/* */
5849/* Returns: */
5850/* 0 for success, positive value for failure. */
5851/****************************************************************************/
5852static void
5853bce_intr(void *xsc)
5854{
5855 struct bce_softc *sc;
5856 struct ifnet *ifp;
5857 u32 status_attn_bits;
5740/*
5741 * Interrupt handler.
5742 */
5743/****************************************************************************/
5744/* Main interrupt entry point. Verifies that the controller generated the */
5745/* interrupt and then calls a separate routine for handle the various */
5746/* interrupt causes (PHY, TX, RX). */
5747/* */
5748/* Returns: */
5749/* 0 for success, positive value for failure. */
5750/****************************************************************************/
5751static void
5752bce_intr(void *xsc)
5753{
5754 struct bce_softc *sc;
5755 struct ifnet *ifp;
5756 u32 status_attn_bits;
5757 u16 hw_rx_cons, hw_tx_cons;
5858
5859 sc = xsc;
5860 ifp = sc->bce_ifp;
5861
5862 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__);
5863 BCE_LOCK(sc);
5864
5865 DBRUN(sc->interrupts_generated++);
5866
5758
5759 sc = xsc;
5760 ifp = sc->bce_ifp;
5761
5762 DBPRINT(sc, BCE_EXCESSIVE, "Entering %s()\n", __FUNCTION__);
5763 BCE_LOCK(sc);
5764
5765 DBRUN(sc->interrupts_generated++);
5766
5867#ifdef DEVICE_POLLING
5868 if (ifp->if_capenable & IFCAP_POLLING) {
5869 DBPRINT(sc, BCE_INFO_MISC, "Polling enabled!\n");
5870 goto bce_intr_exit;
5871 }
5872#endif
5873
5874 bus_dmamap_sync(sc->status_tag, sc->status_map,
5875 BUS_DMASYNC_POSTWRITE);
5876
5877 /*
5878 * If the hardware status block index
5879 * matches the last value read by the
5880 * driver and we haven't asserted our
5881 * interrupt then there's nothing to do.
5882 */
5883 if ((sc->status_block->status_idx == sc->last_status_idx) &&
5884 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5885 goto bce_intr_exit;
5886
5887 /* Ack the interrupt and stop others from occuring. */
5888 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5889 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5890 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5891
5767 bus_dmamap_sync(sc->status_tag, sc->status_map,
5768 BUS_DMASYNC_POSTWRITE);
5769
5770 /*
5771 * If the hardware status block index
5772 * matches the last value read by the
5773 * driver and we haven't asserted our
5774 * interrupt then there's nothing to do.
5775 */
5776 if ((sc->status_block->status_idx == sc->last_status_idx) &&
5777 (REG_RD(sc, BCE_PCICFG_MISC_STATUS) & BCE_PCICFG_MISC_STATUS_INTA_VALUE))
5778 goto bce_intr_exit;
5779
5780 /* Ack the interrupt and stop others from occuring. */
5781 REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
5782 BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
5783 BCE_PCICFG_INT_ACK_CMD_MASK_INT);
5784
5785 /* Check if the hardware has finished any work. */
5786 hw_rx_cons = bce_get_hw_rx_cons(sc);
5787 hw_tx_cons = bce_get_hw_tx_cons(sc);
5788
5892 /* Keep processing data as long as there is work to do. */
5893 for (;;) {
5894
5895 status_attn_bits = sc->status_block->status_attn_bits;
5896
5897 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5898 BCE_PRINTF("Simulating unexpected status attention bit set.");
5899 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);

--- 17 unchanged lines hidden (view full) ---

5917 if (bce_debug_unexpected_attention == 0)
5918 bce_breakpoint(sc));
5919
5920 bce_init_locked(sc);
5921 goto bce_intr_exit;
5922 }
5923
5924 /* Check for any completed RX frames. */
5789 /* Keep processing data as long as there is work to do. */
5790 for (;;) {
5791
5792 status_attn_bits = sc->status_block->status_attn_bits;
5793
5794 DBRUNIF(DB_RANDOMTRUE(bce_debug_unexpected_attention),
5795 BCE_PRINTF("Simulating unexpected status attention bit set.");
5796 status_attn_bits = status_attn_bits | STATUS_ATTN_BITS_PARITY_ERROR);

--- 17 unchanged lines hidden (view full) ---

5814 if (bce_debug_unexpected_attention == 0)
5815 bce_breakpoint(sc));
5816
5817 bce_init_locked(sc);
5818 goto bce_intr_exit;
5819 }
5820
5821 /* Check for any completed RX frames. */
5925 if (sc->status_block->status_rx_quick_consumer_index0 != sc->hw_rx_cons)
5822 if (hw_rx_cons != sc->hw_rx_cons)
5926 bce_rx_intr(sc);
5927
5928 /* Check for any completed TX frames. */
5823 bce_rx_intr(sc);
5824
5825 /* Check for any completed TX frames. */
5929 if (sc->status_block->status_tx_quick_consumer_index0 != sc->hw_tx_cons)
5826 if (hw_tx_cons != sc->hw_tx_cons)
5930 bce_tx_intr(sc);
5931
5932 /* Save the status block index value for use during the next interrupt. */
5933 sc->last_status_idx = sc->status_block->status_idx;
5934
5935 /* Prevent speculative reads from getting ahead of the status block. */
5936 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5937 BUS_SPACE_BARRIER_READ);
5938
5939 /* If there's no work left then exit the interrupt service routine. */
5827 bce_tx_intr(sc);
5828
5829 /* Save the status block index value for use during the next interrupt. */
5830 sc->last_status_idx = sc->status_block->status_idx;
5831
5832 /* Prevent speculative reads from getting ahead of the status block. */
5833 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
5834 BUS_SPACE_BARRIER_READ);
5835
5836 /* If there's no work left then exit the interrupt service routine. */
5940 if ((sc->status_block->status_rx_quick_consumer_index0 == sc->hw_rx_cons) &&
5941 (sc->status_block->status_tx_quick_consumer_index0 == sc->hw_tx_cons))
5837 hw_rx_cons = bce_get_hw_rx_cons(sc);
5838 hw_tx_cons = bce_get_hw_tx_cons(sc);
5839
5840 if ((hw_rx_cons == sc->hw_rx_cons) && (hw_tx_cons == sc->hw_tx_cons))
5942 break;
5943
5944 }
5945
5946 bus_dmamap_sync(sc->status_tag, sc->status_map,
5947 BUS_DMASYNC_PREWRITE);
5948
5949 /* Re-enable interrupts. */

--- 392 unchanged lines hidden (view full) ---

6342 /* Check if the link has come up. */
6343 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE &&
6344 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6345 sc->bce_link++;
6346 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
6347 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) &&
6348 bootverbose)
6349 BCE_PRINTF("Gigabit link up\n");
5841 break;
5842
5843 }
5844
5845 bus_dmamap_sync(sc->status_tag, sc->status_map,
5846 BUS_DMASYNC_PREWRITE);
5847
5848 /* Re-enable interrupts. */

--- 392 unchanged lines hidden (view full) ---

6241 /* Check if the link has come up. */
6242 if (!sc->bce_link && mii->mii_media_status & IFM_ACTIVE &&
6243 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
6244 sc->bce_link++;
6245 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
6246 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) &&
6247 bootverbose)
6248 BCE_PRINTF("Gigabit link up\n");
6249
6350 /* Now that link is up, handle any outstanding TX traffic. */
6351 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
6352 bce_start_locked(ifp);
6353 }
6354
6355bce_tick_locked_exit:
6356 return;
6357}

--- 1086 unchanged lines hidden (view full) ---

7444 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
7445 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT)));
7446 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3,
7447 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
7448 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
7449 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
7450 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT)));
7451
6250 /* Now that link is up, handle any outstanding TX traffic. */
6251 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
6252 bce_start_locked(ifp);
6253 }
6254
6255bce_tick_locked_exit:
6256 return;
6257}

--- 1086 unchanged lines hidden (view full) ---

7344 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT << 8) |
7345 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT)));
7346 REG_WR(sc, BCE_HC_STAT_GEN_SEL_3,
7347 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT << 24) |
7348 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT << 16) |
7349 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT << 8) |
7350 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT)));
7351
7452 cmd = REG_RD(sc, 0x23f8); /* RLUP_FTQ_CMD */
7453 ctl = REG_RD(sc, 0x23fc); /* RLUP_FTQ_CTL */
7454 cur_depth = (ctl & 0xFFC00000) >> 22;
7455 max_depth = (ctl & 0x003FF000) >> 12;
7352
7353 cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
7354 ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
7355 cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
7356 max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
7456 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7457 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7458 cmd, ctl, cur_depth, max_depth, valid_cnt);
7459
7357 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7358 BCE_PRINTF(" RLUP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7359 cmd, ctl, cur_depth, max_depth, valid_cnt);
7360
7460 cmd = REG_RD_IND(sc, 0xc53f8); /* RXP_FTQ_CMD */
7461 ctl = REG_RD_IND(sc, 0xc53fc); /* RXP_FTQ_CTL */
7462 cur_depth = (ctl & 0xFFC00000) >> 22;
7463 max_depth = (ctl & 0x003FF000) >> 12;
7361 cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
7362 ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
7363 cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
7364 max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
7464 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7465 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7466 cmd, ctl, cur_depth, max_depth, valid_cnt);
7467
7365 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7366 BCE_PRINTF(" RXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7367 cmd, ctl, cur_depth, max_depth, valid_cnt);
7368
7468 cmd = REG_RD_IND(sc, 0xc53b8); /* RXP_CFTQ_CMD */
7469 ctl = REG_RD_IND(sc, 0xc53bc); /* RXP_CFTQ_CTL */
7470 cur_depth = (ctl & 0xFFC00000) >> 22;
7471 max_depth = (ctl & 0x003FF000) >> 12;
7369 cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
7370 ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
7371 cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
7372 max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
7472 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7473 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7474 cmd, ctl, cur_depth, max_depth, valid_cnt);
7475
7373 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7374 BCE_PRINTF(" RXPC 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7375 cmd, ctl, cur_depth, max_depth, valid_cnt);
7376
7476 cmd = REG_RD(sc, 0x2b78); /* RV2P_PFTQ_CMD */
7477 ctl = REG_RD(sc, 0x2b7c); /* RV2P_PFTQ_CTL */
7478 cur_depth = (ctl & 0xFFC00000) >> 22;
7479 max_depth = (ctl & 0x003FF000) >> 12;
7377 cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
7378 ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
7379 cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
7380 max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
7480 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
7481 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7482 cmd, ctl, cur_depth, max_depth, valid_cnt);
7483
7381 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
7382 BCE_PRINTF(" RV2PP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7383 cmd, ctl, cur_depth, max_depth, valid_cnt);
7384
7484 cmd = REG_RD(sc, 0x2bf8); /* RV2P_MFTQ_CMD */
7485 ctl = REG_RD(sc, 0x2bfc); /* RV2P_MFTQ_CTL */
7486 cur_depth = (ctl & 0xFFC00000) >> 22;
7487 max_depth = (ctl & 0x003FF000) >> 12;
7385 cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
7386 ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
7387 cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
7388 max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
7488 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
7489 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7490 cmd, ctl, cur_depth, max_depth, valid_cnt);
7491
7389 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
7390 BCE_PRINTF(" RV2PM 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7391 cmd, ctl, cur_depth, max_depth, valid_cnt);
7392
7492 cmd = REG_RD(sc, 0x2bb8); /* RV2P_TFTQ_CMD */
7493 ctl = REG_RD(sc, 0x2bbc); /* RV2P_TFTQ_CTL */
7494 cur_depth = (ctl & 0xFFC00000) >> 22;
7495 max_depth = (ctl & 0x003FF000) >> 12;
7393 cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
7394 ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
7395 cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
7396 max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
7496 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
7497 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7498 cmd, ctl, cur_depth, max_depth, valid_cnt);
7499
7397 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
7398 BCE_PRINTF(" RV2PT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7399 cmd, ctl, cur_depth, max_depth, valid_cnt);
7400
7500 cmd = REG_RD(sc, 0x2ff8); /* RDMA_FTQ_CMD */
7501 ctl = REG_RD(sc, 0x2ffc); /* RDMA_FTQ_CTL */
7502 cur_depth = (ctl & 0xFFC00000) >> 22;
7503 max_depth = (ctl & 0x003FF000) >> 12;
7401 cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
7402 ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
7403 cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
7404 max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
7504 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
7505 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7506 cmd, ctl, cur_depth, max_depth, valid_cnt);
7507
7405 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
7406 BCE_PRINTF(" RDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7407 cmd, ctl, cur_depth, max_depth, valid_cnt);
7408
7508 cmd = REG_RD(sc, 0x4ff8); /* TSCH_FTQ_CMD */
7509 ctl = REG_RD(sc, 0x4ffc); /* TSCH_FTQ_CTL */
7510 cur_depth = (ctl & 0xFFC00000) >> 22;
7511 max_depth = (ctl & 0x003FF000) >> 12;
7409 cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
7410 ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
7411 cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
7412 max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
7512 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
7513 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7514 cmd, ctl, cur_depth, max_depth, valid_cnt);
7515
7413 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
7414 BCE_PRINTF(" TSCH 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7415 cmd, ctl, cur_depth, max_depth, valid_cnt);
7416
7516 cmd = REG_RD(sc, 0x53f8); /* TBDR_FTQ_CMD */
7517 ctl = REG_RD(sc, 0x53fc); /* TBDR_FTQ_CTL */
7518 cur_depth = (ctl & 0xFFC00000) >> 22;
7519 max_depth = (ctl & 0x003FF000) >> 12;
7417 cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
7418 ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
7419 cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
7420 max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
7520 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
7521 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7522 cmd, ctl, cur_depth, max_depth, valid_cnt);
7523
7421 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
7422 BCE_PRINTF(" TBDR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7423 cmd, ctl, cur_depth, max_depth, valid_cnt);
7424
7524 cmd = REG_RD_IND(sc, 0x453f8); /* TXP_FTQ_CMD */
7525 ctl = REG_RD_IND(sc, 0x453fc); /* TXP_FTQ_CTL */
7526 cur_depth = (ctl & 0xFFC00000) >> 22;
7527 max_depth = (ctl & 0x003FF000) >> 12;
7425 cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
7426 ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
7427 cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
7428 max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
7528 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
7529 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7530 cmd, ctl, cur_depth, max_depth, valid_cnt);
7531
7429 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
7430 BCE_PRINTF(" TXP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7431 cmd, ctl, cur_depth, max_depth, valid_cnt);
7432
7532 cmd = REG_RD(sc, 0x5ff8); /* TDMA_FTQ_CMD */
7533 ctl = REG_RD(sc, 0x5ffc); /* TDMA_FTQ_CTL */
7534 cur_depth = (ctl & 0xFFC00000) >> 22;
7535 max_depth = (ctl & 0x003FF000) >> 12;
7433 cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
7434 ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
7435 cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
7436 max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
7536 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
7537 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7538 cmd, ctl, cur_depth, max_depth, valid_cnt);
7539
7437 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
7438 BCE_PRINTF(" TDMA 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7439 cmd, ctl, cur_depth, max_depth, valid_cnt);
7440
7540 cmd = REG_RD_IND(sc, 0x853f8); /* TPAT_FTQ_CMD */
7541 ctl = REG_RD_IND(sc, 0x853fc); /* TPAT_FTQ_CTL */
7542 cur_depth = (ctl & 0xFFC00000) >> 22;
7543 max_depth = (ctl & 0x003FF000) >> 12;
7441
7442 cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
7443 ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
7444 cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
7445 max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
7544 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
7545 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7546 cmd, ctl, cur_depth, max_depth, valid_cnt);
7547
7446 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
7447 BCE_PRINTF(" TPAT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7448 cmd, ctl, cur_depth, max_depth, valid_cnt);
7449
7548 cmd = REG_RD_IND(sc, 0x1c03f8); /* TAS_FTQ_CMD */
7549 ctl = REG_RD_IND(sc, 0x1c03fc); /* TAS_FTQ_CTL */
7550 cur_depth = (ctl & 0xFFC00000) >> 22;
7551 max_depth = (ctl & 0x003FF000) >> 12;
7450 cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
7451 ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
7452 cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
7453 max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
7552 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
7553 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7554 cmd, ctl, cur_depth, max_depth, valid_cnt);
7555
7454 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
7455 BCE_PRINTF(" TAS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7456 cmd, ctl, cur_depth, max_depth, valid_cnt);
7457
7556 cmd = REG_RD_IND(sc, 0x105378); /* COM_COMXQ_FTQ_CMD */
7557 ctl = REG_RD_IND(sc, 0x10537c); /* COM_COMXQ_FTQ_CTL */
7558 cur_depth = (ctl & 0xFFC00000) >> 22;
7559 max_depth = (ctl & 0x003FF000) >> 12;
7458 cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
7459 ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
7460 cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
7461 max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
7560 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
7561 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7562 cmd, ctl, cur_depth, max_depth, valid_cnt);
7563
7462 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
7463 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7464 cmd, ctl, cur_depth, max_depth, valid_cnt);
7465
7564 cmd = REG_RD_IND(sc, 0x1053b8); /* COM_COMTQ_FTQ_CMD */
7565 ctl = REG_RD_IND(sc, 0x1053bc); /* COM_COMTQ_FTQ_CTL */
7566 cur_depth = (ctl & 0xFFC00000) >> 22;
7567 max_depth = (ctl & 0x003FF000) >> 12;
7466 cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
7467 ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
7468 cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
7469 max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
7568 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
7569 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7570 cmd, ctl, cur_depth, max_depth, valid_cnt);
7571
7470 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
7471 BCE_PRINTF(" COMT 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7472 cmd, ctl, cur_depth, max_depth, valid_cnt);
7473
7572 cmd = REG_RD_IND(sc, 0x1053f8); /* COM_COMQ_FTQ_CMD */
7573 ctl = REG_RD_IND(sc, 0x1053fc); /* COM_COMQ_FTQ_CTL */
7574 cur_depth = (ctl & 0xFFC00000) >> 22;
7575 max_depth = (ctl & 0x003FF000) >> 12;
7474 cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
7475 ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
7476 cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
7477 max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
7576 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
7577 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7578 cmd, ctl, cur_depth, max_depth, valid_cnt);
7579
7580 /* Setup the generic statistic counters for the FTQ valid count. */
7581 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0,
7582 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
7583 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
7584 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT)));
7585
7478 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
7479 BCE_PRINTF(" COMX 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7480 cmd, ctl, cur_depth, max_depth, valid_cnt);
7481
7482 /* Setup the generic statistic counters for the FTQ valid count. */
7483 REG_WR(sc, BCE_HC_STAT_GEN_SEL_0,
7484 ((BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT << 16) |
7485 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT << 8) |
7486 (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT)));
7487
7586 cmd = REG_RD_IND(sc, 0x1453f8); /* MCP_MCPQ_FTQ_CMD */
7587 ctl = REG_RD_IND(sc, 0x1453fc); /* MCP_MCPQ_FTQ_CTL */
7588 cur_depth = (ctl & 0xFFC00000) >> 22;
7589 max_depth = (ctl & 0x003FF000) >> 12;
7488 cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
7489 ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
7490 cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
7491 max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
7590 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7591 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7592 cmd, ctl, cur_depth, max_depth, valid_cnt);
7593
7492 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
7493 BCE_PRINTF(" MCP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7494 cmd, ctl, cur_depth, max_depth, valid_cnt);
7495
7594 cmd = REG_RD_IND(sc, 0x1853f8); /* CP_CPQ_FTQ_CMD */
7595 ctl = REG_RD_IND(sc, 0x1853fc); /* CP_CPQ_FTQ_CTL */
7596 cur_depth = (ctl & 0xFFC00000) >> 22;
7597 max_depth = (ctl & 0x003FF000) >> 12;
7496 cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
7497 ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
7498 cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
7499 max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
7598 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7599 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7600 cmd, ctl, cur_depth, max_depth, valid_cnt);
7601
7500 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
7501 BCE_PRINTF(" CP 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7502 cmd, ctl, cur_depth, max_depth, valid_cnt);
7503
7602 cmd = REG_RD(sc, 0x43f8); /* CSCH_CH_FTQ_CMD */
7603 ctl = REG_RD(sc, 0x43fc); /* CSCH_CH_FTQ_CTL */
7604 cur_depth = (ctl & 0xFFC00000) >> 22;
7605 max_depth = (ctl & 0x003FF000) >> 12;
7504 cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
7505 ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
7506 cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
7507 max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
7606 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7607 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7608 cmd, ctl, cur_depth, max_depth, valid_cnt);
7609
7610 BCE_PRINTF(
7611 "----------------------------"
7612 "----------------"
7613 "----------------------------\n");

--- 991 unchanged lines hidden --- 		7508 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
7509 BCE_PRINTF(" CS 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
7510 cmd, ctl, cur_depth, max_depth, valid_cnt);
7511
7512 BCE_PRINTF(
7513 "----------------------------"
7514 "----------------"
7515 "----------------------------\n");

--- 991 unchanged lines hidden ---