258 uint32_t sc_eerd; /* regdomain from EEPROM */ 259 uint32_t sc_eecc; /* country code from EEPROM */ 260 /* rate tables */ 261 const HAL_RATE_TABLE *sc_rates[IEEE80211_MODE_MAX]; 262 const HAL_RATE_TABLE *sc_currates; /* current rate table */ 263 enum ieee80211_phymode sc_curmode; /* current phy mode */ 264 HAL_OPMODE sc_opmode; /* current operating mode */ 265 u_int16_t sc_curtxpow; /* current tx power limit */ 266 u_int16_t sc_curaid; /* current association id */ 267 struct ieee80211_channel *sc_curchan; /* current installed channel */ 268 u_int8_t sc_curbssid[IEEE80211_ADDR_LEN]; 269 u_int8_t sc_rixmap[256]; /* IEEE to h/w rate table ix */ 270 struct { 271 u_int8_t ieeerate; /* IEEE rate */ 272 u_int8_t rxflags; /* radiotap rx flags */ 273 u_int8_t txflags; /* radiotap tx flags */ 274 u_int16_t ledon; /* softled on time */ 275 u_int16_t ledoff; /* softled off time */ 276 } sc_hwmap[32]; /* h/w rate ix mappings */ 277 u_int8_t sc_protrix; /* protection rate index */ 278 u_int8_t sc_lastdatarix; /* last data frame rate index */ 279 u_int sc_mcastrate; /* ieee rate for mcastrateix */ 280 u_int sc_fftxqmin; /* min frames before staging */ 281 u_int sc_fftxqmax; /* max frames before drop */ 282 u_int sc_txantenna; /* tx antenna (fixed or auto) */ 283 HAL_INT sc_imask; /* interrupt mask copy */ 284 u_int sc_keymax; /* size of key cache */ 285 u_int8_t sc_keymap[ATH_KEYBYTES];/* key use bit map */ 286 287 u_int sc_ledpin; /* GPIO pin for driving LED */ 288 u_int sc_ledon; /* pin setting for LED on */ 289 u_int sc_ledidle; /* idle polling interval */ 290 int sc_ledevent; /* time of last LED event */ 291 u_int8_t sc_txrix; /* current tx rate for LED */ 292 u_int16_t sc_ledoff; /* off time for current blink */ 293 struct callout sc_ledtimer; /* led off timer */ 294 295 u_int sc_rfsilentpin; /* GPIO pin for rfkill int */ 296 u_int sc_rfsilentpol; /* pin setting for rfkill on */ 297 298 struct ath_descdma sc_rxdma; /* RX descriptors */ 299 ath_bufhead sc_rxbuf; /* receive buffer */ 300 struct mbuf *sc_rxpending; /* pending receive data */ 301 u_int32_t *sc_rxlink; /* link ptr in last RX desc */ 302 struct task sc_rxtask; /* rx int processing */ 303 u_int8_t sc_defant; /* current default antenna */ 304 u_int8_t sc_rxotherant; /* rx's on non-default antenna*/ 305 u_int64_t sc_lastrx; /* tsf at last rx'd frame */ 306 struct ath_rx_status *sc_lastrs; /* h/w status of last rx */ 307 struct ath_rx_radiotap_header sc_rx_th; 308 int sc_rx_th_len; 309 u_int sc_monpass; /* frames to pass in mon.mode */ 310 311 struct ath_descdma sc_txdma; /* TX descriptors */ 312 ath_bufhead sc_txbuf; /* transmit buffer */ 313 struct mtx sc_txbuflock; /* txbuf lock */ 314 char sc_txname[12]; /* e.g. "ath0_buf" */ 315 u_int sc_txqsetup; /* h/w queues setup */ 316 u_int sc_txintrperiod;/* tx interrupt batching */ 317 struct ath_txq sc_txq[HAL_NUM_TX_QUEUES]; 318 struct ath_txq *sc_ac2q[5]; /* WME AC -> h/w q map */ 319 struct task sc_txtask; /* tx int processing */ 320 int sc_wd_timer; /* count down for wd timer */ 321 struct callout sc_wd_ch; /* tx watchdog timer */ 322 struct ath_tx_radiotap_header sc_tx_th; 323 int sc_tx_th_len; 324 325 struct ath_descdma sc_bdma; /* beacon descriptors */ 326 ath_bufhead sc_bbuf; /* beacon buffers */ 327 u_int sc_bhalq; /* HAL q for outgoing beacons */ 328 u_int sc_bmisscount; /* missed beacon transmits */ 329 u_int32_t sc_ant_tx[8]; /* recent tx frames/antenna */ 330 struct ath_txq *sc_cabq; /* tx q for cab frames */ 331 struct task sc_bmisstask; /* bmiss int processing */ 332 struct task sc_bstucktask; /* stuck beacon processing */ 333 enum { 334 OK, /* no change needed */ 335 UPDATE, /* update pending */ 336 COMMIT /* beacon sent, commit change */ 337 } sc_updateslot; /* slot time update fsm */ 338 int sc_slotupdate; /* slot to advance fsm */ 339 struct ieee80211vap *sc_bslot[ATH_BCBUF]; 340 int sc_nbcnvaps; /* # vaps with beacons */ 341 342 struct callout sc_cal_ch; /* callout handle for cals */ 343 int sc_lastlongcal; /* last long cal completed */ 344 int sc_lastcalreset;/* last cal reset done */ 345 int sc_lastani; /* last ANI poll */ 346 int sc_lastshortcal; /* last short calibration */ 347 HAL_BOOL sc_doresetcal; /* Yes, we're doing a reset cal atm */ 348 HAL_NODE_STATS sc_halstats; /* station-mode rssi stats */ 349 u_int sc_tdmadbaprep; /* TDMA DBA prep time */ 350 u_int sc_tdmaswbaprep;/* TDMA SWBA prep time */ 351 u_int sc_tdmaswba; /* TDMA SWBA counter */ 352 u_int32_t sc_tdmabintval; /* TDMA beacon interval (TU) */ 353 u_int32_t sc_tdmaguard; /* TDMA guard time (usec) */ 354 u_int sc_tdmaslotlen; /* TDMA slot length (usec) */ 355 u_int32_t sc_avgtsfdeltap;/* TDMA slot adjust (+) */ 356 u_int32_t sc_avgtsfdeltam;/* TDMA slot adjust (-) */ 357 uint16_t *sc_eepromdata; /* Local eeprom data, if AR9100 */ 358 int sc_txchainmask; /* currently configured TX chainmask */ 359 int sc_rxchainmask; /* currently configured RX chainmask */ 360}; 361 362#define ATH_LOCK_INIT(_sc) \ 363 mtx_init(&(_sc)->sc_mtx, device_get_nameunit((_sc)->sc_dev), \ 364 NULL, MTX_DEF | MTX_RECURSE) 365#define ATH_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx) 366#define ATH_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 367#define ATH_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 368#define ATH_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 369 370#define ATH_TXQ_SETUP(sc, i) ((sc)->sc_txqsetup & (1<<i)) 371 372#define ATH_TXBUF_LOCK_INIT(_sc) do { \ 373 snprintf((_sc)->sc_txname, sizeof((_sc)->sc_txname), "%s_buf", \ 374 device_get_nameunit((_sc)->sc_dev)); \ 375 mtx_init(&(_sc)->sc_txbuflock, (_sc)->sc_txname, NULL, MTX_DEF); \ 376} while (0) 377#define ATH_TXBUF_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_txbuflock) 378#define ATH_TXBUF_LOCK(_sc) mtx_lock(&(_sc)->sc_txbuflock) 379#define ATH_TXBUF_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_txbuflock) 380#define ATH_TXBUF_LOCK_ASSERT(_sc) \ 381 mtx_assert(&(_sc)->sc_txbuflock, MA_OWNED) 382 383int ath_attach(u_int16_t, struct ath_softc *); 384int ath_detach(struct ath_softc *); 385void ath_resume(struct ath_softc *); 386void ath_suspend(struct ath_softc *); 387void ath_shutdown(struct ath_softc *); 388void ath_intr(void *); 389 390/* 391 * HAL definitions to comply with local coding convention. 392 */ 393#define ath_hal_detach(_ah) \ 394 ((*(_ah)->ah_detach)((_ah))) 395#define ath_hal_reset(_ah, _opmode, _chan, _outdoor, _pstatus) \ 396 ((*(_ah)->ah_reset)((_ah), (_opmode), (_chan), (_outdoor), (_pstatus))) 397#define ath_hal_macversion(_ah) \ 398 (((_ah)->ah_macVersion << 4) | ((_ah)->ah_macRev)) 399#define ath_hal_getratetable(_ah, _mode) \ 400 ((*(_ah)->ah_getRateTable)((_ah), (_mode))) 401#define ath_hal_getmac(_ah, _mac) \ 402 ((*(_ah)->ah_getMacAddress)((_ah), (_mac))) 403#define ath_hal_setmac(_ah, _mac) \ 404 ((*(_ah)->ah_setMacAddress)((_ah), (_mac))) 405#define ath_hal_getbssidmask(_ah, _mask) \ 406 ((*(_ah)->ah_getBssIdMask)((_ah), (_mask))) 407#define ath_hal_setbssidmask(_ah, _mask) \ 408 ((*(_ah)->ah_setBssIdMask)((_ah), (_mask))) 409#define ath_hal_intrset(_ah, _mask) \ 410 ((*(_ah)->ah_setInterrupts)((_ah), (_mask))) 411#define ath_hal_intrget(_ah) \ 412 ((*(_ah)->ah_getInterrupts)((_ah))) 413#define ath_hal_intrpend(_ah) \ 414 ((*(_ah)->ah_isInterruptPending)((_ah))) 415#define ath_hal_getisr(_ah, _pmask) \ 416 ((*(_ah)->ah_getPendingInterrupts)((_ah), (_pmask))) 417#define ath_hal_updatetxtriglevel(_ah, _inc) \ 418 ((*(_ah)->ah_updateTxTrigLevel)((_ah), (_inc))) 419#define ath_hal_setpower(_ah, _mode) \ 420 ((*(_ah)->ah_setPowerMode)((_ah), (_mode), AH_TRUE)) 421#define ath_hal_keycachesize(_ah) \ 422 ((*(_ah)->ah_getKeyCacheSize)((_ah))) 423#define ath_hal_keyreset(_ah, _ix) \ 424 ((*(_ah)->ah_resetKeyCacheEntry)((_ah), (_ix))) 425#define ath_hal_keyset(_ah, _ix, _pk, _mac) \ 426 ((*(_ah)->ah_setKeyCacheEntry)((_ah), (_ix), (_pk), (_mac), AH_FALSE)) 427#define ath_hal_keyisvalid(_ah, _ix) \ 428 (((*(_ah)->ah_isKeyCacheEntryValid)((_ah), (_ix)))) 429#define ath_hal_keysetmac(_ah, _ix, _mac) \ 430 ((*(_ah)->ah_setKeyCacheEntryMac)((_ah), (_ix), (_mac))) 431#define ath_hal_getrxfilter(_ah) \ 432 ((*(_ah)->ah_getRxFilter)((_ah))) 433#define ath_hal_setrxfilter(_ah, _filter) \ 434 ((*(_ah)->ah_setRxFilter)((_ah), (_filter))) 435#define ath_hal_setmcastfilter(_ah, _mfilt0, _mfilt1) \ 436 ((*(_ah)->ah_setMulticastFilter)((_ah), (_mfilt0), (_mfilt1))) 437#define ath_hal_waitforbeacon(_ah, _bf) \ 438 ((*(_ah)->ah_waitForBeaconDone)((_ah), (_bf)->bf_daddr)) 439#define ath_hal_putrxbuf(_ah, _bufaddr) \ 440 ((*(_ah)->ah_setRxDP)((_ah), (_bufaddr))) 441/* NB: common across all chips */ 442#define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 443#define ath_hal_gettsf32(_ah) \ 444 OS_REG_READ(_ah, AR_TSF_L32) 445#define ath_hal_gettsf64(_ah) \ 446 ((*(_ah)->ah_getTsf64)((_ah))) 447#define ath_hal_resettsf(_ah) \ 448 ((*(_ah)->ah_resetTsf)((_ah))) 449#define ath_hal_rxena(_ah) \ 450 ((*(_ah)->ah_enableReceive)((_ah))) 451#define ath_hal_puttxbuf(_ah, _q, _bufaddr) \ 452 ((*(_ah)->ah_setTxDP)((_ah), (_q), (_bufaddr))) 453#define ath_hal_gettxbuf(_ah, _q) \ 454 ((*(_ah)->ah_getTxDP)((_ah), (_q))) 455#define ath_hal_numtxpending(_ah, _q) \ 456 ((*(_ah)->ah_numTxPending)((_ah), (_q))) 457#define ath_hal_getrxbuf(_ah) \ 458 ((*(_ah)->ah_getRxDP)((_ah))) 459#define ath_hal_txstart(_ah, _q) \ 460 ((*(_ah)->ah_startTxDma)((_ah), (_q))) 461#define ath_hal_setchannel(_ah, _chan) \ 462 ((*(_ah)->ah_setChannel)((_ah), (_chan))) 463#define ath_hal_calibrate(_ah, _chan, _iqcal) \ 464 ((*(_ah)->ah_perCalibration)((_ah), (_chan), (_iqcal))) 465#define ath_hal_calibrateN(_ah, _chan, _lcal, _isdone) \ 466 ((*(_ah)->ah_perCalibrationN)((_ah), (_chan), 0x1, (_lcal), (_isdone))) 467#define ath_hal_calreset(_ah, _chan) \ 468 ((*(_ah)->ah_resetCalValid)((_ah), (_chan))) 469#define ath_hal_setledstate(_ah, _state) \ 470 ((*(_ah)->ah_setLedState)((_ah), (_state))) 471#define ath_hal_beaconinit(_ah, _nextb, _bperiod) \ 472 ((*(_ah)->ah_beaconInit)((_ah), (_nextb), (_bperiod))) 473#define ath_hal_beaconreset(_ah) \ 474 ((*(_ah)->ah_resetStationBeaconTimers)((_ah))) 475#define ath_hal_beaconsettimers(_ah, _bt) \ 476 ((*(_ah)->ah_setBeaconTimers)((_ah), (_bt))) 477#define ath_hal_beacontimers(_ah, _bs) \ 478 ((*(_ah)->ah_setStationBeaconTimers)((_ah), (_bs))) 479#define ath_hal_setassocid(_ah, _bss, _associd) \ 480 ((*(_ah)->ah_writeAssocid)((_ah), (_bss), (_associd))) 481#define ath_hal_phydisable(_ah) \ 482 ((*(_ah)->ah_phyDisable)((_ah))) 483#define ath_hal_setopmode(_ah) \ 484 ((*(_ah)->ah_setPCUConfig)((_ah))) 485#define ath_hal_stoptxdma(_ah, _qnum) \ 486 ((*(_ah)->ah_stopTxDma)((_ah), (_qnum))) 487#define ath_hal_stoppcurecv(_ah) \ 488 ((*(_ah)->ah_stopPcuReceive)((_ah))) 489#define ath_hal_startpcurecv(_ah) \ 490 ((*(_ah)->ah_startPcuReceive)((_ah))) 491#define ath_hal_stopdmarecv(_ah) \ 492 ((*(_ah)->ah_stopDmaReceive)((_ah))) 493#define ath_hal_getdiagstate(_ah, _id, _indata, _insize, _outdata, _outsize) \ 494 ((*(_ah)->ah_getDiagState)((_ah), (_id), \ 495 (_indata), (_insize), (_outdata), (_outsize))) 496#define ath_hal_getfatalstate(_ah, _outdata, _outsize) \ 497 ath_hal_getdiagstate(_ah, 29, NULL, 0, (_outdata), _outsize) 498#define ath_hal_setuptxqueue(_ah, _type, _irq) \ 499 ((*(_ah)->ah_setupTxQueue)((_ah), (_type), (_irq))) 500#define ath_hal_resettxqueue(_ah, _q) \ 501 ((*(_ah)->ah_resetTxQueue)((_ah), (_q))) 502#define ath_hal_releasetxqueue(_ah, _q) \ 503 ((*(_ah)->ah_releaseTxQueue)((_ah), (_q))) 504#define ath_hal_gettxqueueprops(_ah, _q, _qi) \ 505 ((*(_ah)->ah_getTxQueueProps)((_ah), (_q), (_qi))) 506#define ath_hal_settxqueueprops(_ah, _q, _qi) \ 507 ((*(_ah)->ah_setTxQueueProps)((_ah), (_q), (_qi))) 508/* NB: common across all chips */ 509#define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 510#define ath_hal_txqenabled(_ah, _qnum) \ 511 (OS_REG_READ(_ah, AR_Q_TXE) & (1<<(_qnum))) 512#define ath_hal_getrfgain(_ah) \ 513 ((*(_ah)->ah_getRfGain)((_ah))) 514#define ath_hal_getdefantenna(_ah) \ 515 ((*(_ah)->ah_getDefAntenna)((_ah))) 516#define ath_hal_setdefantenna(_ah, _ant) \ 517 ((*(_ah)->ah_setDefAntenna)((_ah), (_ant))) 518#define ath_hal_rxmonitor(_ah, _arg, _chan) \ 519 ((*(_ah)->ah_rxMonitor)((_ah), (_arg), (_chan))) 520#define ath_hal_ani_poll(_ah, _chan) \ 521 ((*(_ah)->ah_aniPoll)((_ah), (_chan))) 522#define ath_hal_mibevent(_ah, _stats) \ 523 ((*(_ah)->ah_procMibEvent)((_ah), (_stats))) 524#define ath_hal_setslottime(_ah, _us) \ 525 ((*(_ah)->ah_setSlotTime)((_ah), (_us))) 526#define ath_hal_getslottime(_ah) \ 527 ((*(_ah)->ah_getSlotTime)((_ah))) 528#define ath_hal_setacktimeout(_ah, _us) \ 529 ((*(_ah)->ah_setAckTimeout)((_ah), (_us))) 530#define ath_hal_getacktimeout(_ah) \ 531 ((*(_ah)->ah_getAckTimeout)((_ah))) 532#define ath_hal_setctstimeout(_ah, _us) \ 533 ((*(_ah)->ah_setCTSTimeout)((_ah), (_us))) 534#define ath_hal_getctstimeout(_ah) \ 535 ((*(_ah)->ah_getCTSTimeout)((_ah))) 536#define ath_hal_getcapability(_ah, _cap, _param, _result) \ 537 ((*(_ah)->ah_getCapability)((_ah), (_cap), (_param), (_result))) 538#define ath_hal_setcapability(_ah, _cap, _param, _v, _status) \ 539 ((*(_ah)->ah_setCapability)((_ah), (_cap), (_param), (_v), (_status))) 540#define ath_hal_ciphersupported(_ah, _cipher) \ 541 (ath_hal_getcapability(_ah, HAL_CAP_CIPHER, _cipher, NULL) == HAL_OK) 542#define ath_hal_getregdomain(_ah, _prd) \ 543 (ath_hal_getcapability(_ah, HAL_CAP_REG_DMN, 0, (_prd)) == HAL_OK) 544#define ath_hal_setregdomain(_ah, _rd) \ 545 ath_hal_setcapability(_ah, HAL_CAP_REG_DMN, 0, _rd, NULL) 546#define ath_hal_getcountrycode(_ah, _pcc) \ 547 (*(_pcc) = (_ah)->ah_countryCode) 548#define ath_hal_gettkipmic(_ah) \ 549 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_MIC, 1, NULL) == HAL_OK) 550#define ath_hal_settkipmic(_ah, _v) \ 551 ath_hal_setcapability(_ah, HAL_CAP_TKIP_MIC, 1, _v, NULL) 552#define ath_hal_hastkipsplit(_ah) \ 553 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 0, NULL) == HAL_OK) 554#define ath_hal_gettkipsplit(_ah) \ 555 (ath_hal_getcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, NULL) == HAL_OK) 556#define ath_hal_settkipsplit(_ah, _v) \ 557 ath_hal_setcapability(_ah, HAL_CAP_TKIP_SPLIT, 1, _v, NULL) 558#define ath_hal_haswmetkipmic(_ah) \ 559 (ath_hal_getcapability(_ah, HAL_CAP_WME_TKIPMIC, 0, NULL) == HAL_OK) 560#define ath_hal_hwphycounters(_ah) \ 561 (ath_hal_getcapability(_ah, HAL_CAP_PHYCOUNTERS, 0, NULL) == HAL_OK) 562#define ath_hal_hasdiversity(_ah) \ 563 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 0, NULL) == HAL_OK) 564#define ath_hal_getdiversity(_ah) \ 565 (ath_hal_getcapability(_ah, HAL_CAP_DIVERSITY, 1, NULL) == HAL_OK) 566#define ath_hal_setdiversity(_ah, _v) \ 567 ath_hal_setcapability(_ah, HAL_CAP_DIVERSITY, 1, _v, NULL) 568#define ath_hal_getantennaswitch(_ah) \ 569 ((*(_ah)->ah_getAntennaSwitch)((_ah))) 570#define ath_hal_setantennaswitch(_ah, _v) \ 571 ((*(_ah)->ah_setAntennaSwitch)((_ah), (_v))) 572#define ath_hal_getdiag(_ah, _pv) \ 573 (ath_hal_getcapability(_ah, HAL_CAP_DIAG, 0, _pv) == HAL_OK) 574#define ath_hal_setdiag(_ah, _v) \ 575 ath_hal_setcapability(_ah, HAL_CAP_DIAG, 0, _v, NULL) 576#define ath_hal_getnumtxqueues(_ah, _pv) \ 577 (ath_hal_getcapability(_ah, HAL_CAP_NUM_TXQUEUES, 0, _pv) == HAL_OK) 578#define ath_hal_hasveol(_ah) \ 579 (ath_hal_getcapability(_ah, HAL_CAP_VEOL, 0, NULL) == HAL_OK) 580#define ath_hal_hastxpowlimit(_ah) \ 581 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 0, NULL) == HAL_OK) 582#define ath_hal_settxpowlimit(_ah, _pow) \ 583 ((*(_ah)->ah_setTxPowerLimit)((_ah), (_pow))) 584#define ath_hal_gettxpowlimit(_ah, _ppow) \ 585 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 1, _ppow) == HAL_OK) 586#define ath_hal_getmaxtxpow(_ah, _ppow) \ 587 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 2, _ppow) == HAL_OK) 588#define ath_hal_gettpscale(_ah, _scale) \ 589 (ath_hal_getcapability(_ah, HAL_CAP_TXPOW, 3, _scale) == HAL_OK) 590#define ath_hal_settpscale(_ah, _v) \ 591 ath_hal_setcapability(_ah, HAL_CAP_TXPOW, 3, _v, NULL) 592#define ath_hal_hastpc(_ah) \ 593 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 0, NULL) == HAL_OK) 594#define ath_hal_gettpc(_ah) \ 595 (ath_hal_getcapability(_ah, HAL_CAP_TPC, 1, NULL) == HAL_OK) 596#define ath_hal_settpc(_ah, _v) \ 597 ath_hal_setcapability(_ah, HAL_CAP_TPC, 1, _v, NULL) 598#define ath_hal_hasbursting(_ah) \ 599 (ath_hal_getcapability(_ah, HAL_CAP_BURST, 0, NULL) == HAL_OK) 600#define ath_hal_setmcastkeysearch(_ah, _v) \ 601 ath_hal_setcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, _v, NULL) 602#define ath_hal_hasmcastkeysearch(_ah) \ 603 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 0, NULL) == HAL_OK) 604#define ath_hal_getmcastkeysearch(_ah) \ 605 (ath_hal_getcapability(_ah, HAL_CAP_MCAST_KEYSRCH, 1, NULL) == HAL_OK) 606#define ath_hal_hasfastframes(_ah) \ 607 (ath_hal_getcapability(_ah, HAL_CAP_FASTFRAME, 0, NULL) == HAL_OK) 608#define ath_hal_hasbssidmask(_ah) \ 609 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMASK, 0, NULL) == HAL_OK) 610#define ath_hal_hasbssidmatch(_ah) \ 611 (ath_hal_getcapability(_ah, HAL_CAP_BSSIDMATCH, 0, NULL) == HAL_OK) 612#define ath_hal_hastsfadjust(_ah) \ 613 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 0, NULL) == HAL_OK) 614#define ath_hal_gettsfadjust(_ah) \ 615 (ath_hal_getcapability(_ah, HAL_CAP_TSF_ADJUST, 1, NULL) == HAL_OK) 616#define ath_hal_settsfadjust(_ah, _onoff) \ 617 ath_hal_setcapability(_ah, HAL_CAP_TSF_ADJUST, 1, _onoff, NULL) 618#define ath_hal_hasrfsilent(_ah) \ 619 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 0, NULL) == HAL_OK) 620#define ath_hal_getrfkill(_ah) \ 621 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 1, NULL) == HAL_OK) 622#define ath_hal_setrfkill(_ah, _onoff) \ 623 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 1, _onoff, NULL) 624#define ath_hal_getrfsilent(_ah, _prfsilent) \ 625 (ath_hal_getcapability(_ah, HAL_CAP_RFSILENT, 2, _prfsilent) == HAL_OK) 626#define ath_hal_setrfsilent(_ah, _rfsilent) \ 627 ath_hal_setcapability(_ah, HAL_CAP_RFSILENT, 2, _rfsilent, NULL) 628#define ath_hal_gettpack(_ah, _ptpack) \ 629 (ath_hal_getcapability(_ah, HAL_CAP_TPC_ACK, 0, _ptpack) == HAL_OK) 630#define ath_hal_settpack(_ah, _tpack) \ 631 ath_hal_setcapability(_ah, HAL_CAP_TPC_ACK, 0, _tpack, NULL) 632#define ath_hal_gettpcts(_ah, _ptpcts) \ 633 (ath_hal_getcapability(_ah, HAL_CAP_TPC_CTS, 0, _ptpcts) == HAL_OK) 634#define ath_hal_settpcts(_ah, _tpcts) \ 635 ath_hal_setcapability(_ah, HAL_CAP_TPC_CTS, 0, _tpcts, NULL) 636#define ath_hal_hasintmit(_ah) \ 637 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 0, NULL) == HAL_OK) 638#define ath_hal_getintmit(_ah) \ 639 (ath_hal_getcapability(_ah, HAL_CAP_INTMIT, 1, NULL) == HAL_OK) 640#define ath_hal_setintmit(_ah, _v) \ 641 ath_hal_setcapability(_ah, HAL_CAP_INTMIT, 1, _v, NULL) 642#define ath_hal_getchannoise(_ah, _c) \ 643 ((*(_ah)->ah_getChanNoise)((_ah), (_c))) 644#define ath_hal_getrxchainmask(_ah, _prxchainmask) \ 645 (ath_hal_getcapability(_ah, HAL_CAP_RX_CHAINMASK, 0, _prxchainmask)) 646#define ath_hal_gettxchainmask(_ah, _ptxchainmask) \ 647 (ath_hal_getcapability(_ah, HAL_CAP_TX_CHAINMASK, 0, _ptxchainmask)) 648#define ath_hal_split4ktrans(_ah) \ 649 (ath_hal_getcapability(_ah, HAP_CAP_SPLIT_4KB_TRANS, 0, NULL) == HAL_OK)
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652 653#define ath_hal_setuprxdesc(_ah, _ds, _size, _intreq) \ 654 ((*(_ah)->ah_setupRxDesc)((_ah), (_ds), (_size), (_intreq))) 655#define ath_hal_rxprocdesc(_ah, _ds, _dspa, _dsnext, _rs) \ 656 ((*(_ah)->ah_procRxDesc)((_ah), (_ds), (_dspa), (_dsnext), 0, (_rs))) 657#define ath_hal_setuptxdesc(_ah, _ds, _plen, _hlen, _atype, _txpow, \ 658 _txr0, _txtr0, _keyix, _ant, _flags, \ 659 _rtsrate, _rtsdura) \ 660 ((*(_ah)->ah_setupTxDesc)((_ah), (_ds), (_plen), (_hlen), (_atype), \ 661 (_txpow), (_txr0), (_txtr0), (_keyix), (_ant), \ 662 (_flags), (_rtsrate), (_rtsdura), 0, 0, 0)) 663#define ath_hal_setupxtxdesc(_ah, _ds, \ 664 _txr1, _txtr1, _txr2, _txtr2, _txr3, _txtr3) \ 665 ((*(_ah)->ah_setupXTxDesc)((_ah), (_ds), \ 666 (_txr1), (_txtr1), (_txr2), (_txtr2), (_txr3), (_txtr3))) 667#define ath_hal_filltxdesc(_ah, _ds, _l, _first, _last, _ds0) \ 668 ((*(_ah)->ah_fillTxDesc)((_ah), (_ds), (_l), (_first), (_last), (_ds0))) 669#define ath_hal_txprocdesc(_ah, _ds, _ts) \ 670 ((*(_ah)->ah_procTxDesc)((_ah), (_ds), (_ts))) 671#define ath_hal_gettxintrtxqs(_ah, _txqs) \ 672 ((*(_ah)->ah_getTxIntrQueue)((_ah), (_txqs))) 673#define ath_hal_gettxcompletionrates(_ah, _ds, _rates, _tries) \ 674 ((*(_ah)->ah_getTxCompletionRates)((_ah), (_ds), (_rates), (_tries))) 675 676#define ath_hal_chaintxdesc(_ah, _ds, _pktlen, _hdrlen, _type, _keyix, \ 677 _cipher, _delims, _seglen, _first, _last) \ 678 ((*(_ah)->ah_chainTxDesc((_ah), (_ds), (_pktlen), (_hdrlen), \ 679 (_type), (_keyix), (_cipher), (_delims), (_seglen), \ 680 (_first), (_last)))) 681#define ath_hal_setupfirsttxdesc(_ah, _ds, _aggrlen, _flags, _txpower, \ 682 _txr0, _txtr0, _antm, _rcr, _rcd) \ 683 ((*(_ah)->ah_setupFirstTxDesc)((_ah), (_ds), (_aggrlen), (_flags), \ 684 (_txpower), (_txr0), (_txtr0), (_antm), (_rcr), (_rcd))) 685#define ath_hal_setuplasttxdesc(_ah, _ds, _ds0) \ 686 ((*(_ah)->ah_setupLastTxDesc)((_ah), (_ds), (_ds0))) 687#define ath_hal_set11nratescenario(_ah, _ds, _dur, _rt, _series, _ns, _flags) \ 688 ((*(_ah)->ah_set11nRateScenario)((_ah), (_ds), (_dur), (_rt), \ 689 (_series), (_ns), (_flags))) 690#define ath_hal_set11naggrmiddle(_ah, _ds, _num) \ 691 ((*(_ah)->ah_set11nAggrMiddle((_ah), (_ds), (_num)))) 692#define ath_hal_set11nburstduration(_ah, _ds, _dur) \ 693 ((*(_ah)->ah_set11nBurstDuration)((_ah), (_ds), (_dur))) 694 695#define ath_hal_gpioCfgOutput(_ah, _gpio, _type) \ 696 ((*(_ah)->ah_gpioCfgOutput)((_ah), (_gpio), (_type))) 697#define ath_hal_gpioset(_ah, _gpio, _b) \ 698 ((*(_ah)->ah_gpioSet)((_ah), (_gpio), (_b))) 699#define ath_hal_gpioget(_ah, _gpio) \ 700 ((*(_ah)->ah_gpioGet)((_ah), (_gpio))) 701#define ath_hal_gpiosetintr(_ah, _gpio, _b) \ 702 ((*(_ah)->ah_gpioSetIntr)((_ah), (_gpio), (_b))) 703 704#define ath_hal_radar_wait(_ah, _chan) \ 705 ((*(_ah)->ah_radarWait)((_ah), (_chan))) 706 707#endif /* _DEV_ATH_ATHVAR_H */
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